system_stm32l4xx.c File Reference

CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. More...

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Detailed Description

CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.

Author:

MCD Application Team

Version:

V1.0.1

Date:

16-September-2015 This file provides two functions and one global variable to be called from user application:

• SystemInit(): This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32l4xx.s" file.

• SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.

• SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

After each device reset the MSI (4 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to configure the system clock before to branch to main program.

This file configures the system clock as follows: ============================================================================= ----------------------------------------------------------------------------- System Clock source | MSI ----------------------------------------------------------------------------- SYSCLK(Hz) | 4000000 ----------------------------------------------------------------------------- HCLK(Hz) | 4000000 ----------------------------------------------------------------------------- AHB Prescaler | 1 ----------------------------------------------------------------------------- APB1 Prescaler | 1 ----------------------------------------------------------------------------- APB2 Prescaler | 1 ----------------------------------------------------------------------------- PLL_M | 1 ----------------------------------------------------------------------------- PLL_N | 8 ----------------------------------------------------------------------------- PLL_P | 7 ----------------------------------------------------------------------------- PLL_Q | 2 ----------------------------------------------------------------------------- PLL_R | 2 ----------------------------------------------------------------------------- PLLSAI1_P | NA ----------------------------------------------------------------------------- PLLSAI1_Q | NA ----------------------------------------------------------------------------- PLLSAI1_R | NA ----------------------------------------------------------------------------- PLLSAI2_P | NA ----------------------------------------------------------------------------- PLLSAI2_Q | NA ----------------------------------------------------------------------------- PLLSAI2_R | NA ----------------------------------------------------------------------------- Require 48MHz for USB OTG FS, | Disabled SDIO and RNG clock | ----------------------------------------------------------------------------- =============================================================================

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Definition in file system_stm32l4xx.c.