mfxstm32l152.h

00001 /**
00002   ******************************************************************************
00003   * @file    mfxstm32l152.h
00004   * @author  MCD Application Team
00005   * @version V2.0.0
00006   * @date    24-June-2015
00007   * @brief   This file contains all the functions prototypes for the
00008   *          mfxstm32l152.c IO expander driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00013   *
00014   * Redistribution and use in source and binary forms, with or without modification,
00015   * are permitted provided that the following conditions are met:
00016   *   1. Redistributions of source code must retain the above copyright notice,
00017   *      this list of conditions and the following disclaimer.
00018   *   2. Redistributions in binary form must reproduce the above copyright notice,
00019   *      this list of conditions and the following disclaimer in the documentation
00020   *      and/or other materials provided with the distribution.
00021   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00022   *      may be used to endorse or promote products derived from this software
00023   *      without specific prior written permission.
00024   *
00025   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00026   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00027   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00028   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00029   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00030   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00031   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00032   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00033   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00034   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00035   *
00036   ******************************************************************************
00037   */ 
00038 
00039 /* Define to prevent recursive inclusion -------------------------------------*/
00040 #ifndef __MFXSTM32L152_H
00041 #define __MFXSTM32L152_H
00042 
00043 #ifdef __cplusplus
00044  extern "C" {
00045 #endif   
00046    
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "../Common/ts.h"
00049 #include "../Common/io.h"
00050 #include "../Common/idd.h"
00051 
00052 /** @addtogroup BSP
00053   * @{
00054   */ 
00055 
00056 /** @addtogroup Component
00057   * @{
00058   */
00059     
00060 /** @defgroup MFXSTM32L152
00061   * @{
00062   */    
00063 
00064 /* Exported types ------------------------------------------------------------*/
00065 
00066 /** @defgroup MFXSTM32L152_Exported_Types
00067   * @{
00068   */ 
00069 typedef struct
00070 {
00071   uint8_t SYS_CTRL;
00072   uint8_t ERROR_SRC;
00073   uint8_t ERROR_MSG;
00074   uint8_t IRQ_OUT;
00075   uint8_t IRQ_SRC_EN;
00076   uint8_t IRQ_PENDING;
00077   uint8_t IDD_CTRL;
00078   uint8_t IDD_PRE_DELAY;
00079   uint8_t IDD_SHUNT0_MSB;
00080   uint8_t IDD_SHUNT0_LSB;
00081   uint8_t IDD_SHUNT1_MSB;
00082   uint8_t IDD_SHUNT1_LSB;
00083   uint8_t IDD_SHUNT2_MSB;
00084   uint8_t IDD_SHUNT2_LSB;
00085   uint8_t IDD_SHUNT3_MSB;
00086   uint8_t IDD_SHUNT3_LSB;
00087   uint8_t IDD_SHUNT4_MSB;
00088   uint8_t IDD_SHUNT4_LSB;
00089   uint8_t IDD_GAIN_MSB;
00090   uint8_t IDD_GAIN_LSB;
00091   uint8_t IDD_VDD_MIN_MSB;
00092   uint8_t IDD_VDD_MIN_LSB;
00093   uint8_t IDD_VALUE_MSB;
00094   uint8_t IDD_VALUE_MID;
00095   uint8_t IDD_VALUE_LSB;
00096   uint8_t IDD_CAL_OFFSET_MSB;
00097   uint8_t IDD_CAL_OFFSET_LSB;
00098   uint8_t IDD_SHUNT_USED;
00099 }IDD_dbgTypeDef;
00100 
00101 /**
00102   * @}
00103   */
00104 
00105 /* Exported constants --------------------------------------------------------*/
00106   
00107 /** @defgroup MFXSTM32L152_Exported_Constants
00108   * @{
00109   */ 
00110 
00111  /**
00112   * @brief  MFX COMMON defines
00113   */
00114    
00115  /**
00116   * @brief  Register address: chip IDs (R)
00117   */
00118 #define MFXSTM32L152_REG_ADR_ID                 ((uint8_t)0x00)
00119  /**
00120   * @brief  Register address: chip FW_VERSION  (R)
00121   */
00122 #define MFXSTM32L152_REG_ADR_FW_VERSION_MSB     ((uint8_t)0x01)
00123 #define MFXSTM32L152_REG_ADR_FW_VERSION_LSB     ((uint8_t)0x00)
00124  /**
00125   * @brief  Register address: System Control Register (R/W)
00126   */
00127 #define MFXSTM32L152_REG_ADR_SYS_CTRL           ((uint8_t)0x40)
00128  /**
00129   * @brief  Register address: Vdd monitoring (R)
00130   */
00131 #define MFXSTM32L152_REG_ADR_VDD_REF_MSB        ((uint8_t)0x06)
00132 #define MFXSTM32L152_REG_ADR_VDD_REF_LSB        ((uint8_t)0x07)
00133  /**
00134   * @brief  Register address: Error source
00135   */
00136 #define MFXSTM32L152_REG_ADR_ERROR_SRC          ((uint8_t)0x03)
00137  /**
00138   * @brief  Register address: Error Message
00139   */
00140 #define MFXSTM32L152_REG_ADR_ERROR_MSG          ((uint8_t)0x04)
00141 
00142  /**
00143   * @brief  Reg Addr IRQs: to config the pin that informs Main MCU that MFX events appear
00144   */
00145 #define MFXSTM32L152_REG_ADR_MFX_IRQ_OUT        ((uint8_t)0x41)
00146  /**
00147   * @brief  Reg Addr IRQs: to select the events which activate the MFXSTM32L152_IRQ_OUT signal
00148   */
00149 #define MFXSTM32L152_REG_ADR_IRQ_SRC_EN         ((uint8_t)0x42)
00150  /**
00151   * @brief  Reg Addr IRQs: the Main MCU must read the IRQ_PENDING register to know the interrupt reason
00152   */
00153 #define MFXSTM32L152_REG_ADR_IRQ_PENDING        ((uint8_t)0x08)
00154  /**
00155   * @brief  Reg Addr IRQs: the Main MCU must acknowledge it thanks to a writing access to the IRQ_ACK register
00156   */
00157 #define MFXSTM32L152_REG_ADR_IRQ_ACK            ((uint8_t)0x44)
00158    
00159   /**
00160   * @brief  MFXSTM32L152_REG_ADR_ID choices
00161   */
00162 #define MFXSTM32L152_ID_1                    ((uint8_t)0x7B)
00163 #define MFXSTM32L152_ID_2                    ((uint8_t)0x79)
00164    
00165   /**
00166   * @brief  MFXSTM32L152_REG_ADR_SYS_CTRL choices
00167   */
00168 #define MFXSTM32L152_SWRST                    ((uint8_t)0x80)
00169 #define MFXSTM32L152_STANDBY                  ((uint8_t)0x40)
00170 #define MFXSTM32L152_ALTERNATE_GPIO_EN        ((uint8_t)0x08) /* by the way if IDD and TS are enabled they take automatically the AF pins*/
00171 #define MFXSTM32L152_IDD_EN                   ((uint8_t)0x04)
00172 #define MFXSTM32L152_TS_EN                    ((uint8_t)0x02)
00173 #define MFXSTM32L152_GPIO_EN                  ((uint8_t)0x01)
00174 
00175   /**
00176   * @brief  MFXSTM32L152_REG_ADR_ERROR_SRC choices
00177   */
00178 #define MFXSTM32L152_IDD_ERROR_SRC             ((uint8_t)0x04)  /* Error raised by Idd */
00179 #define MFXSTM32L152_TS_ERROR_SRC              ((uint8_t)0x02)  /* Error raised by Touch Screen */
00180 #define MFXSTM32L152_GPIO_ERROR_SRC            ((uint8_t)0x01)  /* Error raised by Gpio */
00181 
00182  /**
00183   * @brief  MFXSTM32L152_REG_ADR_MFX_IRQ_OUT choices
00184   */
00185 #define MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN   ((uint8_t)0x00)
00186 #define MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL    ((uint8_t)0x01)
00187 #define MFXSTM32L152_OUT_PIN_POLARITY_LOW     ((uint8_t)0x00)
00188 #define MFXSTM32L152_OUT_PIN_POLARITY_HIGH    ((uint8_t)0x02)
00189 
00190  /**
00191    * @brief  REG_ADR_IRQ_SRC_EN, REG_ADR_IRQ_PENDING & REG_ADR_IRQ_ACK choices
00192   */
00193 #define MFXSTM32L152_IRQ_TS_OVF               ((uint8_t)0x80)  /* TouchScreen FIFO Overflow irq*/
00194 #define MFXSTM32L152_IRQ_TS_FULL              ((uint8_t)0x40)  /* TouchScreen FIFO Full irq*/
00195 #define MFXSTM32L152_IRQ_TS_TH                ((uint8_t)0x20)  /* TouchScreen FIFO threshold triggered irq*/
00196 #define MFXSTM32L152_IRQ_TS_NE                ((uint8_t)0x10)  /* TouchScreen FIFO Not Empty irq*/
00197 #define MFXSTM32L152_IRQ_TS_DET               ((uint8_t)0x08)  /* TouchScreen Detect irq*/
00198 #define MFXSTM32L152_IRQ_ERROR                ((uint8_t)0x04)  /* Error message from MFXSTM32L152 firmware irq */
00199 #define MFXSTM32L152_IRQ_IDD                  ((uint8_t)0x02)  /* IDD function irq */
00200 #define MFXSTM32L152_IRQ_GPIO                 ((uint8_t)0x01)  /* General GPIO irq (only for SRC_EN and PENDING) */
00201 #define MFXSTM32L152_IRQ_ALL                  ((uint8_t)0xFF)  /* All global interrupts          */
00202 #define MFXSTM32L152_IRQ_TS                  (MFXSTM32L152_IRQ_TS_DET | MFXSTM32L152_IRQ_TS_NE |  MFXSTM32L152_IRQ_TS_TH | MFXSTM32L152_IRQ_TS_FULL | MFXSTM32L152_IRQ_TS_OVF ) 
00203 
00204    
00205  /**
00206   * @brief  GPIO: 24 programmable input/output called MFXSTM32L152_GPIO[23:0] are provided
00207   */
00208 
00209  /**
00210    * @brief  Reg addr: GPIO DIRECTION (R/W): GPIO pins direction: (0) input, (1) output.
00211   */
00212 #define MFXSTM32L152_REG_ADR_GPIO_DIR1          ((uint8_t)0x60)  /* gpio [0:7] */
00213 #define MFXSTM32L152_REG_ADR_GPIO_DIR2          ((uint8_t)0x61)  /* gpio [8:15] */
00214 #define MFXSTM32L152_REG_ADR_GPIO_DIR3          ((uint8_t)0x62)  /* agpio [0:7] */
00215  /**
00216   * @brief  Reg addr: GPIO TYPE (R/W): If GPIO in output: (0) output push pull, (1) output open drain.
00217   *                          If GPIO in input: (0) input without pull resistor, (1) input with pull resistor.
00218   */
00219 #define MFXSTM32L152_REG_ADR_GPIO_TYPE1         ((uint8_t)0x64)  /* gpio [0:7] */
00220 #define MFXSTM32L152_REG_ADR_GPIO_TYPE2         ((uint8_t)0x65)  /* gpio [8:15] */
00221 #define MFXSTM32L152_REG_ADR_GPIO_TYPE3         ((uint8_t)0x66)  /* agpio [0:7] */
00222  /**
00223   * @brief  Reg addr: GPIO PULL_UP_PULL_DOWN (R/W):  discussion open with Jean Claude
00224   */
00225 #define MFXSTM32L152_REG_ADR_GPIO_PUPD1         ((uint8_t)0x68)  /* gpio [0:7] */
00226 #define MFXSTM32L152_REG_ADR_GPIO_PUPD2         ((uint8_t)0x69)  /* gpio [8:15] */
00227 #define MFXSTM32L152_REG_ADR_GPIO_PUPD3         ((uint8_t)0x6A)  /* agpio [0:7] */
00228  /**
00229   * @brief  Reg addr: GPIO SET (W): When GPIO is in output mode, write (1) puts the corresponding GPO in High level.
00230   */
00231 #define MFXSTM32L152_REG_ADR_GPO_SET1           ((uint8_t)0x6C)  /* gpio [0:7] */
00232 #define MFXSTM32L152_REG_ADR_GPO_SET2           ((uint8_t)0x6D)  /* gpio [8:15] */
00233 #define MFXSTM32L152_REG_ADR_GPO_SET3           ((uint8_t)0x6E)  /* agpio [0:7] */
00234  /**
00235   * @brief  Reg addr: GPIO CLEAR (W): When GPIO is in output mode, write (1) puts the corresponding GPO in Low level.
00236   */
00237 #define MFXSTM32L152_REG_ADR_GPO_CLR1           ((uint8_t)0x70)  /* gpio [0:7] */
00238 #define MFXSTM32L152_REG_ADR_GPO_CLR2           ((uint8_t)0x71)  /* gpio [8:15] */
00239 #define MFXSTM32L152_REG_ADR_GPO_CLR3           ((uint8_t)0x72)  /* agpio [0:7] */
00240  /**
00241   * @brief  Reg addr: GPIO STATE (R): Give state of the GPIO pin.
00242   */
00243 #define MFXSTM32L152_REG_ADR_GPIO_STATE1         ((uint8_t)0x10)  /* gpio [0:7] */
00244 #define MFXSTM32L152_REG_ADR_GPIO_STATE2         ((uint8_t)0x11)  /* gpio [8:15] */
00245 #define MFXSTM32L152_REG_ADR_GPIO_STATE3         ((uint8_t)0x12)  /* agpio [0:7] */
00246 
00247   /**
00248   * @brief  GPIO IRQ_GPIs
00249   */
00250 /* GPIOs can INDIVIDUALLY generate interruption to the Main MCU thanks to the MFXSTM32L152_IRQ_OUT signal */
00251 /* the general MFXSTM32L152_IRQ_GPIO_SRC_EN shall be enabled too          */
00252   /**
00253   * @brief  GPIO IRQ_GPI_SRC1/2/3 (R/W): registers enable or not the feature to generate irq
00254   */
00255 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1       ((uint8_t)0x48)  /* gpio [0:7] */
00256 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC2       ((uint8_t)0x49)  /* gpio [8:15] */
00257 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC3       ((uint8_t)0x4A)  /* agpio [0:7] */
00258   /**
00259   * @brief  GPIO IRQ_GPI_EVT1/2/3 (R/W): Irq generated on level (0) or edge (1).
00260   */
00261 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1       ((uint8_t)0x4C)  /* gpio [0:7] */
00262 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT2       ((uint8_t)0x4D)  /* gpio [8:15] */
00263 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT3       ((uint8_t)0x4E)  /* agpio [0:7] */
00264   /**
00265   * @brief  GPIO IRQ_GPI_TYPE1/2/3 (R/W): Irq generated on (0) : Low level or Falling edge. (1) : High level or Rising edge.
00266   */
00267 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1      ((uint8_t)0x50)  /* gpio [0:7] */
00268 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE2      ((uint8_t)0x51)  /* gpio [8:15] */
00269 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE3      ((uint8_t)0x52)  /* agpio [0:7] */
00270   /**
00271   * @brief  GPIO IRQ_GPI_PENDING1/2/3 (R): irq occurs
00272   */
00273 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1   ((uint8_t)0x0C)  /* gpio [0:7] */
00274 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2   ((uint8_t)0x0D)  /* gpio [8:15] */
00275 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3   ((uint8_t)0x0E)  /* agpio [0:7] */
00276   /**
00277   * @brief  GPIO IRQ_GPI_ACK1/2/3 (W): Write (1) to acknowledge IRQ event
00278   */
00279 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1       ((uint8_t)0x54)  /* gpio [0:7] */
00280 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2       ((uint8_t)0x55)  /* gpio [8:15] */
00281 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3       ((uint8_t)0x56)  /* agpio [0:7] */
00282 
00283    
00284  /**
00285   * @brief  GPIO: IO Pins definition
00286   */
00287 #define MFXSTM32L152_GPIO_PIN_0                  ((uint32_t)0x0001)
00288 #define MFXSTM32L152_GPIO_PIN_1                  ((uint32_t)0x0002)
00289 #define MFXSTM32L152_GPIO_PIN_2                  ((uint32_t)0x0004)
00290 #define MFXSTM32L152_GPIO_PIN_3                  ((uint32_t)0x0008)
00291 #define MFXSTM32L152_GPIO_PIN_4                  ((uint32_t)0x0010)
00292 #define MFXSTM32L152_GPIO_PIN_5                  ((uint32_t)0x0020)
00293 #define MFXSTM32L152_GPIO_PIN_6                  ((uint32_t)0x0040)
00294 #define MFXSTM32L152_GPIO_PIN_7                  ((uint32_t)0x0080)
00295 
00296 #define MFXSTM32L152_GPIO_PIN_8                  ((uint32_t)0x0100) 
00297 #define MFXSTM32L152_GPIO_PIN_9                  ((uint32_t)0x0200) 
00298 #define MFXSTM32L152_GPIO_PIN_10                 ((uint32_t)0x0400) 
00299 #define MFXSTM32L152_GPIO_PIN_11                 ((uint32_t)0x0800)
00300 #define MFXSTM32L152_GPIO_PIN_12                 ((uint32_t)0x1000) 
00301 #define MFXSTM32L152_GPIO_PIN_13                 ((uint32_t)0x2000) 
00302 #define MFXSTM32L152_GPIO_PIN_14                 ((uint32_t)0x4000) 
00303 #define MFXSTM32L152_GPIO_PIN_15                 ((uint32_t)0x8000) 
00304 
00305 #define MFXSTM32L152_GPIO_PIN_16               ((uint32_t)0x010000)
00306 #define MFXSTM32L152_GPIO_PIN_17               ((uint32_t)0x020000)
00307 #define MFXSTM32L152_GPIO_PIN_18               ((uint32_t)0x040000)
00308 #define MFXSTM32L152_GPIO_PIN_19               ((uint32_t)0x080000)
00309 #define MFXSTM32L152_GPIO_PIN_20               ((uint32_t)0x100000)
00310 #define MFXSTM32L152_GPIO_PIN_21               ((uint32_t)0x200000)
00311 #define MFXSTM32L152_GPIO_PIN_22               ((uint32_t)0x400000)
00312 #define MFXSTM32L152_GPIO_PIN_23               ((uint32_t)0x800000)
00313 
00314 #define MFXSTM32L152_AGPIO_PIN_0               MFXSTM32L152_GPIO_PIN_16
00315 #define MFXSTM32L152_AGPIO_PIN_1               MFXSTM32L152_GPIO_PIN_17
00316 #define MFXSTM32L152_AGPIO_PIN_2               MFXSTM32L152_GPIO_PIN_18
00317 #define MFXSTM32L152_AGPIO_PIN_3               MFXSTM32L152_GPIO_PIN_19
00318 #define MFXSTM32L152_AGPIO_PIN_4               MFXSTM32L152_GPIO_PIN_20
00319 #define MFXSTM32L152_AGPIO_PIN_5               MFXSTM32L152_GPIO_PIN_21
00320 #define MFXSTM32L152_AGPIO_PIN_6               MFXSTM32L152_GPIO_PIN_22
00321 #define MFXSTM32L152_AGPIO_PIN_7               MFXSTM32L152_GPIO_PIN_23
00322 
00323 #define MFXSTM32L152_GPIO_PINS_ALL             ((uint32_t)0xFFFFFF)
00324 
00325  /**
00326   * @brief  GPIO: constant
00327   */
00328 #define MFXSTM32L152_GPIO_DIR_IN                ((uint8_t)0x0)  
00329 #define MFXSTM32L152_GPIO_DIR_OUT               ((uint8_t)0x1)  
00330 #define MFXSTM32L152_IRQ_GPI_EVT_LEVEL          ((uint8_t)0x0)  
00331 #define MFXSTM32L152_IRQ_GPI_EVT_EDGE           ((uint8_t)0x1)  
00332 #define MFXSTM32L152_IRQ_GPI_TYPE_LLFE          ((uint8_t)0x0)  /* Low Level Falling Edge */
00333 #define MFXSTM32L152_IRQ_GPI_TYPE_HLRE          ((uint8_t)0x1)  /*High Level Raising Edge */
00334 #define MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR  ((uint8_t)0x0)  
00335 #define MFXSTM32L152_GPI_WITH_PULL_RESISTOR     ((uint8_t)0x1)  
00336 #define MFXSTM32L152_GPO_PUSH_PULL              ((uint8_t)0x0)  
00337 #define MFXSTM32L152_GPO_OPEN_DRAIN             ((uint8_t)0x1)  
00338 #define MFXSTM32L152_GPIO_PULL_DOWN             ((uint8_t)0x0)  
00339 #define MFXSTM32L152_GPIO_PULL_UP               ((uint8_t)0x1)   
00340    
00341    
00342   /**
00343   * @brief  TOUCH SCREEN Registers
00344   */
00345 
00346   /**
00347   * @brief  Touch Screen Registers
00348   */
00349 #define MFXSTM32L152_TS_SETTLING            ((uint8_t)0xA0)
00350 #define MFXSTM32L152_TS_TOUCH_DET_DELAY     ((uint8_t)0xA1)
00351 #define MFXSTM32L152_TS_AVE                 ((uint8_t)0xA2)
00352 #define MFXSTM32L152_TS_TRACK               ((uint8_t)0xA3)
00353 #define MFXSTM32L152_TS_FIFO_TH             ((uint8_t)0xA4)
00354 #define MFXSTM32L152_TS_FIFO_STA            ((uint8_t)0x20)
00355 #define MFXSTM32L152_TS_FIFO_LEVEL          ((uint8_t)0x21)
00356 #define MFXSTM32L152_TS_XY_DATA             ((uint8_t)0x24)
00357 
00358   /**
00359   * @brief TS registers masks
00360   */
00361 #define MFXSTM32L152_TS_CTRL_STATUS         ((uint8_t)0x08)
00362 #define MFXSTM32L152_TS_CLEAR_FIFO          ((uint8_t)0x80)
00363 
00364 
00365 /**
00366   * @brief  Register address: Idd control register (R/W)
00367   */
00368 #define MFXSTM32L152_REG_ADR_IDD_CTRL           ((uint8_t)0x80)
00369 
00370 /**
00371   * @brief  Register address: Idd pre delay  register (R/W)
00372   */
00373 #define MFXSTM32L152_REG_ADR_IDD_PRE_DELAY      ((uint8_t)0x81)
00374 
00375 /**
00376   * @brief  Register address: Idd Shunt registers (R/W)
00377   */
00378 #define MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB     ((uint8_t)0x82)
00379 #define MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB     ((uint8_t)0x83)
00380 #define MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB     ((uint8_t)0x84)
00381 #define MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB     ((uint8_t)0x85)
00382 #define MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB     ((uint8_t)0x86)
00383 #define MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB     ((uint8_t)0x87)
00384 #define MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB     ((uint8_t)0x88)
00385 #define MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB     ((uint8_t)0x89)
00386 #define MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB     ((uint8_t)0x8A)
00387 #define MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB     ((uint8_t)0x8B)
00388 
00389 /**
00390   * @brief  Register address: Idd ampli gain register (R/W)
00391   */
00392 #define MFXSTM32L152_REG_ADR_IDD_GAIN_MSB       ((uint8_t)0x8C)
00393 #define MFXSTM32L152_REG_ADR_IDD_GAIN_LSB       ((uint8_t)0x8D)
00394 
00395 /**
00396   * @brief  Register address: Idd VDD min register (R/W)
00397   */
00398 #define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB    ((uint8_t)0x8E)
00399 #define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB    ((uint8_t)0x8F)
00400 
00401 /**
00402   * @brief  Register address: Idd value register (R)
00403   */
00404 #define MFXSTM32L152_REG_ADR_IDD_VALUE_MSB      ((uint8_t)0x14)
00405 #define MFXSTM32L152_REG_ADR_IDD_VALUE_MID      ((uint8_t)0x15)
00406 #define MFXSTM32L152_REG_ADR_IDD_VALUE_LSB      ((uint8_t)0x16)
00407 
00408 /**
00409   * @brief  Register address: Idd calibration offset register (R)
00410   */
00411 #define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_MSB ((uint8_t)0x18)
00412 #define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_LSB ((uint8_t)0x19)
00413 
00414 /**
00415   * @brief  Register address: Idd shunt used offset register (R)
00416   */
00417 #define MFXSTM32L152_REG_ADR_IDD_SHUNT_USED     ((uint8_t)0x1A)
00418 
00419 /**
00420   * @brief  Register address: shunt stabilisation delay registers (R/W)
00421   */
00422 #define MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION  ((uint8_t)0x90)
00423 #define MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION  ((uint8_t)0x91)
00424 #define MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION  ((uint8_t)0x92)
00425 #define MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION  ((uint8_t)0x93)
00426 #define MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION  ((uint8_t)0x94)
00427 
00428 /**
00429   * @brief  Register address: Idd number of measurements register (R/W)
00430   */
00431 #define MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS    ((uint8_t)0x96)
00432 
00433 /**
00434   * @brief  Register address: Idd delta delay between 2 measurements register (R/W)
00435   */
00436 #define MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY  ((uint8_t)0x97)
00437 
00438 /**
00439   * @brief  Register address: Idd number of shunt on board register (R/W)
00440   */
00441 #define MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD  ((uint8_t)0x98)
00442 
00443  
00444 
00445 /** @defgroup IDD_Control_Register_Defines  IDD Control Register Defines
00446   * @{
00447   */
00448 /**
00449   * @brief  IDD control register masks
00450   */
00451 #define MFXSTM32L152_IDD_CTRL_REQ                       ((uint8_t)0x01)
00452 #define MFXSTM32L152_IDD_CTRL_SHUNT_NB                  ((uint8_t)0x0E)
00453 #define MFXSTM32L152_IDD_CTRL_VREF_DIS                  ((uint8_t)0x40)
00454 #define MFXSTM32L152_IDD_CTRL_CAL_DIS                   ((uint8_t)0x80)
00455 
00456 /**
00457   * @brief  IDD Shunt Number
00458   */
00459 #define MFXSTM32L152_IDD_SHUNT_NB_1                     ((uint8_t) 0x01)
00460 #define MFXSTM32L152_IDD_SHUNT_NB_2                     ((uint8_t) 0x02)
00461 #define MFXSTM32L152_IDD_SHUNT_NB_3                     ((uint8_t) 0x03)
00462 #define MFXSTM32L152_IDD_SHUNT_NB_4                     ((uint8_t) 0x04)
00463 #define MFXSTM32L152_IDD_SHUNT_NB_5                     ((uint8_t) 0x05)
00464 
00465 /**
00466   * @brief  Vref Measurement
00467   */
00468 #define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_ENABLE   ((uint8_t) 0x00)
00469 #define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_DISABLE  ((uint8_t) 0x70)
00470 
00471 /**
00472   * @brief  IDD Calibration
00473   */
00474 #define MFXSTM32L152_IDD_AUTO_CALIBRATION_ENABLE        ((uint8_t) 0x00)
00475 #define MFXSTM32L152_IDD_AUTO_CALIBRATION_DISABLE       ((uint8_t) 0x80)
00476 /**
00477   * @}
00478   */
00479 
00480 /** @defgroup IDD_PreDelay_Defines  IDD PreDelay Defines
00481   * @{
00482   */
00483 /**
00484   * @brief  IDD PreDelay masks
00485   */
00486 #define MFXSTM32L152_IDD_PREDELAY_UNIT                  ((uint8_t) 0x80)
00487 #define MFXSTM32L152_IDD_PREDELAY_VALUE                 ((uint8_t) 0x7F)
00488 
00489 
00490 /**
00491   * @brief  IDD PreDelay unit
00492   */
00493 #define MFXSTM32L152_IDD_PREDELAY_0_5_MS                ((uint8_t) 0x00)
00494 #define MFXSTM32L152_IDD_PREDELAY_20_MS                 ((uint8_t) 0x80)
00495 /**
00496   * @}
00497   */
00498 
00499 /** @defgroup IDD_DeltaDelay_Defines  IDD Delta DElay Defines
00500   * @{
00501   */
00502 /**
00503   * @brief  IDD Delta Delay masks
00504   */
00505 #define MFXSTM32L152_IDD_DELTADELAY_UNIT                ((uint8_t) 0x80)
00506 #define MFXSTM32L152_IDD_DELTADELAY_VALUE               ((uint8_t) 0x7F)
00507 
00508 
00509 /**
00510   * @brief  IDD Delta Delay unit
00511   */
00512 #define MFXSTM32L152_IDD_DELTADELAY_0_5_MS              ((uint8_t) 0x00)
00513 #define MFXSTM32L152_IDD_DELTADELAY_20_MS               ((uint8_t) 0x80)
00514 
00515 
00516 /**
00517   * @}
00518   */
00519 
00520 /**
00521   * @}
00522   */
00523 
00524  
00525 /* Exported macro ------------------------------------------------------------*/
00526    
00527 /** @defgroup MFXSTM32L152_Exported_Macros
00528   * @{
00529   */ 
00530 
00531 /**
00532   * @}
00533   */ 
00534 
00535 /* Exported functions --------------------------------------------------------*/
00536   
00537 /** @defgroup MFXSTM32L152_Exported_Functions
00538   * @{
00539   */
00540 
00541 /** 
00542   * @brief MFXSTM32L152 Control functions
00543   */
00544 void     mfxstm32l152_Init(uint16_t DeviceAddr);
00545 void     mfxstm32l152_DeInit(uint16_t DeviceAddr);
00546 void     mfxstm32l152_Reset(uint16_t DeviceAddr);
00547 uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr);
00548 uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr);
00549 void     mfxstm32l152_LowPower(uint16_t DeviceAddr);
00550 void     mfxstm32l152_WakeUp(uint16_t DeviceAddr);
00551 
00552 void     mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source);
00553 void     mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source);
00554 uint8_t  mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source);
00555 void     mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source);
00556 
00557 void     mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity);
00558 void     mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type);
00559 
00560 
00561 /** 
00562   * @brief MFXSTM32L152 IO functionalities functions
00563   */
00564 void     mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin);
00565 uint8_t  mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode);
00566 void     mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState);
00567 uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin);
00568 void     mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr);
00569 void     mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr);
00570 uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin);
00571 void     mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin);
00572 
00573 void     mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction);
00574 void     mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr);
00575 void     mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr);
00576 void     mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type);
00577 void     mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt);
00578 void     mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin);
00579 void     mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin);
00580 
00581 /** 
00582   * @brief MFXSTM32L152 Touch screen functionalities functions
00583   */
00584 void     mfxstm32l152_TS_Start(uint16_t DeviceAddr);
00585 uint8_t  mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr);
00586 void     mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y);
00587 void     mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr);
00588 void     mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr);
00589 uint8_t  mfxstm32l152_TS_ITStatus (uint16_t DeviceAddr);
00590 void     mfxstm32l152_TS_ClearIT (uint16_t DeviceAddr);
00591 
00592 /**
00593   * @brief MFXSTM32L152 IDD current measurement functionalities functions
00594   */
00595 void     mfxstm32l152_IDD_Start(uint16_t DeviceAddr);
00596 void     mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig);
00597 void     mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit);
00598 void     mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue);
00599 uint8_t  mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr);
00600 void     mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr);
00601 void     mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr);
00602 uint8_t  mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr);
00603 void     mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr);
00604 
00605 /**
00606   * @brief MFXSTM32L152 Error management functions
00607   */
00608 uint8_t  mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr);
00609 uint8_t  mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr);
00610 void     mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr);
00611 void     mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr);
00612 uint8_t  mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr);
00613 void     mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr);
00614 
00615 uint8_t  mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr);
00616 void     mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value);
00617 
00618 
00619 
00620 /** 
00621   * @brief iobus prototypes (they should be defined in common/stm32_iobus.h)
00622   */
00623 void     MFX_IO_Init(void);
00624 void     MFX_IO_DeInit(void);
00625 void     MFX_IO_ITConfig (void);
00626 void     MFX_IO_EnableWakeupPin(void);
00627 void     MFX_IO_Wakeup(void);
00628 void     MFX_IO_Delay(uint32_t delay);
00629 void     MFX_IO_Write(uint16_t addr, uint8_t reg, uint8_t value);
00630 uint8_t  MFX_IO_Read(uint16_t addr, uint8_t reg);
00631 uint16_t MFX_IO_ReadMultiple(uint16_t addr, uint8_t reg, uint8_t *buffer, uint16_t length);
00632 
00633 /**
00634   * @}
00635   */ 
00636 
00637 /* Touch screen driver structure */
00638 extern TS_DrvTypeDef mfxstm32l152_ts_drv;
00639 
00640 /* IO driver structure */
00641 extern IO_DrvTypeDef mfxstm32l152_io_drv;
00642 
00643 /* IDD driver structure */
00644 extern IDD_DrvTypeDef mfxstm32l152_idd_drv;
00645 
00646 
00647 #ifdef __cplusplus
00648 }
00649 #endif
00650 #endif /* __MFXSTM32L152_H */
00651 
00652 
00653 /**
00654   * @}
00655   */ 
00656 
00657 /**
00658   * @}
00659   */
00660 
00661 /**
00662   * @}
00663   */ 
00664 
00665 /**
00666   * @}
00667   */       
00668 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00669