mfxstm32l152.c

00001 /** 
00002   ******************************************************************************
00003   * @file    mfxstm32l152.c
00004   * @author  MCD Application Team
00005   * @version V2.0.0
00006   * @date    24-June-2015
00007   * @brief   This file provides a set of functions needed to manage the MFXSTM32L152
00008   *          IO Expander devices.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00013   *
00014   * Redistribution and use in source and binary forms, with or without modification,
00015   * are permitted provided that the following conditions are met:
00016   *   1. Redistributions of source code must retain the above copyright notice,
00017   *      this list of conditions and the following disclaimer.
00018   *   2. Redistributions in binary form must reproduce the above copyright notice,
00019   *      this list of conditions and the following disclaimer in the documentation
00020   *      and/or other materials provided with the distribution.
00021   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00022   *      may be used to endorse or promote products derived from this software
00023   *      without specific prior written permission.
00024   *
00025   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00026   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00027   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00028   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00029   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00030   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00031   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00032   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00033   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00034   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00035   *
00036   ******************************************************************************
00037   */  
00038 
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "mfxstm32l152.h"
00041 
00042 /** @addtogroup BSP
00043   * @{
00044   */
00045 
00046 /** @addtogroup Component
00047   * @{
00048   */ 
00049   
00050 /** @defgroup MFXSTM32L152
00051   * @{
00052   */   
00053   
00054 /* Private typedef -----------------------------------------------------------*/
00055 
00056 /** @defgroup MFXSTM32L152_Private_Types_Definitions
00057   * @{
00058   */ 
00059  
00060 /* Private define ------------------------------------------------------------*/
00061 
00062 /** @defgroup MFXSTM32L152_Private_Defines
00063   * @{
00064   */ 
00065 #define MFXSTM32L152_MAX_INSTANCE         3
00066 
00067 /* Private macro -------------------------------------------------------------*/
00068 
00069 /** @defgroup MFXSTM32L152_Private_Macros
00070   * @{
00071   */ 
00072   
00073 /* Private variables ---------------------------------------------------------*/
00074 
00075 /** @defgroup MFXSTM32L152_Private_Variables
00076   * @{
00077   */ 
00078 
00079 /* Touch screen driver structure initialization */  
00080 TS_DrvTypeDef mfxstm32l152_ts_drv = 
00081 {
00082   mfxstm32l152_Init,
00083   mfxstm32l152_ReadID,
00084   mfxstm32l152_Reset,
00085   
00086   mfxstm32l152_TS_Start,
00087   mfxstm32l152_TS_DetectTouch,
00088   mfxstm32l152_TS_GetXY,
00089   
00090   mfxstm32l152_TS_EnableIT,
00091   mfxstm32l152_TS_ClearIT,
00092   mfxstm32l152_TS_ITStatus,
00093   mfxstm32l152_TS_DisableIT,
00094 };
00095 
00096 /* IO driver structure initialization */ 
00097 IO_DrvTypeDef mfxstm32l152_io_drv = 
00098 {
00099   mfxstm32l152_Init,
00100   mfxstm32l152_ReadID,
00101   mfxstm32l152_Reset,
00102   
00103   mfxstm32l152_IO_Start,
00104   mfxstm32l152_IO_Config,
00105   mfxstm32l152_IO_WritePin,
00106   mfxstm32l152_IO_ReadPin,
00107   
00108   mfxstm32l152_IO_EnableIT,
00109   mfxstm32l152_IO_DisableIT,
00110   mfxstm32l152_IO_ITStatus,
00111   mfxstm32l152_IO_ClearIT,
00112 };
00113 
00114 /* IDD driver structure initialization */
00115 IDD_DrvTypeDef mfxstm32l152_idd_drv =
00116 {
00117   mfxstm32l152_Init,
00118   mfxstm32l152_DeInit,
00119   mfxstm32l152_ReadID,
00120   mfxstm32l152_Reset,
00121   mfxstm32l152_LowPower,
00122   mfxstm32l152_WakeUp,
00123 
00124   mfxstm32l152_IDD_Start,
00125   mfxstm32l152_IDD_Config,
00126   mfxstm32l152_IDD_GetValue,
00127 
00128   mfxstm32l152_IDD_EnableIT,
00129   mfxstm32l152_IDD_ClearIT,
00130   mfxstm32l152_IDD_GetITStatus,
00131   mfxstm32l152_IDD_DisableIT,
00132 
00133   mfxstm32l152_Error_EnableIT,
00134   mfxstm32l152_Error_ClearIT,
00135   mfxstm32l152_Error_GetITStatus,
00136   mfxstm32l152_Error_DisableIT,
00137   mfxstm32l152_Error_ReadSrc,
00138   mfxstm32l152_Error_ReadMsg
00139 };
00140 
00141 
00142 /* mfxstm32l152 instances by address */
00143 uint8_t mfxstm32l152[MFXSTM32L152_MAX_INSTANCE] = {0};
00144 /**
00145   * @}
00146   */ 
00147     
00148 /* Private function prototypes -----------------------------------------------*/
00149 
00150 /** @defgroup MFXSTM32L152_Private_Function_Prototypes
00151   * @{
00152   */
00153 static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr); 
00154 static uint8_t  mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr);
00155 static void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue );
00156 
00157 /* Private functions ---------------------------------------------------------*/
00158 
00159 /** @defgroup MFXSTM32L152_Private_Functions
00160   * @{
00161   */
00162 
00163 /**
00164   * @brief  Initialize the mfxstm32l152 and configure the needed hardware resources
00165   * @param  DeviceAddr: Device address on communication Bus.
00166   * @retval None
00167   */
00168 void mfxstm32l152_Init(uint16_t DeviceAddr)
00169 {
00170   uint8_t instance;
00171   uint8_t empty;
00172   
00173   /* Check if device instance already exists */
00174   instance = mfxstm32l152_GetInstance(DeviceAddr);
00175   
00176   /* To prevent double initialization */
00177   if(instance == 0xFF)
00178   {
00179     /* Look for empty instance */
00180     empty = mfxstm32l152_GetInstance(0);
00181     
00182     if(empty < MFXSTM32L152_MAX_INSTANCE)
00183     {
00184       /* Register the current device instance */
00185       mfxstm32l152[empty] = DeviceAddr;
00186       
00187       /* Initialize IO BUS layer */
00188       MFX_IO_Init();
00189     }
00190   }
00191   
00192   mfxstm32l152_SetIrqOutPinPolarity(DeviceAddr, MFXSTM32L152_OUT_PIN_POLARITY_HIGH);
00193   mfxstm32l152_SetIrqOutPinType(DeviceAddr, MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL);
00194 }
00195 
00196 /**
00197   * @brief  DeInitialize the mfxstm32l152 and unconfigure the needed hardware resources
00198   * @param  DeviceAddr: Device address on communication Bus.
00199   * @retval None
00200   */
00201 void mfxstm32l152_DeInit(uint16_t DeviceAddr)
00202 {
00203   uint8_t instance;
00204   
00205   /* release existing instance */
00206   instance = mfxstm32l152_ReleaseInstance(DeviceAddr);
00207   
00208   /* De-Init only if instance was previously registered */
00209   if(instance != 0xFF)
00210   {
00211     /* De-Initialize IO BUS layer */
00212     MFX_IO_DeInit();
00213   }
00214 }
00215 
00216 /**
00217   * @brief  Reset the mfxstm32l152 by Software.
00218   * @param  DeviceAddr: Device address on communication Bus.  
00219   * @retval None
00220   */
00221 void mfxstm32l152_Reset(uint16_t DeviceAddr)
00222 {
00223   /* Soft Reset */  
00224   MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_SWRST);
00225 
00226   /* Wait for a delay to ensure registers erasing */
00227   MFX_IO_Delay(10);
00228 }
00229 
00230 /**
00231   * @brief  Put mfxstm32l152 Device in Low Power standby mode
00232   * @param  DeviceAddr: Device address on communication Bus.
00233   * @retval None
00234   */
00235 void  mfxstm32l152_LowPower(uint16_t DeviceAddr)
00236 {
00237   /* Enter standby mode */
00238   MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_STANDBY);
00239 
00240   /* enable wakeup pin */
00241   MFX_IO_EnableWakeupPin();
00242 }
00243 
00244 /**
00245   * @brief  WakeUp mfxstm32l152 from standby mode
00246   * @param  DeviceAddr: Device address on communication Bus.
00247   * @retval None
00248   */
00249 void  mfxstm32l152_WakeUp(uint16_t DeviceAddr)
00250 {
00251   uint8_t instance;
00252   
00253   /* Check if device instance already exists */
00254   instance = mfxstm32l152_GetInstance(DeviceAddr);
00255   
00256   /* if instance does not exist, first initialize pins*/
00257   if(instance == 0xFF)
00258   {
00259     /* enable wakeup pin */
00260     MFX_IO_EnableWakeupPin();
00261   }
00262 
00263   /* toggle wakeup pin */
00264   MFX_IO_Wakeup();
00265 }
00266 
00267 /**
00268   * @brief  Read the MFXSTM32L152 IO Expander device ID.
00269   * @param  DeviceAddr: Device address on communication Bus.  
00270   * @retval The Device ID (two bytes).
00271   */
00272 uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr)
00273 {
00274   uint8_t id;
00275   
00276   /* Wait for a delay to ensure the state of registers */
00277   MFX_IO_Delay(1);
00278 
00279   /* Initialize IO BUS layer */
00280   MFX_IO_Init();
00281   
00282   id = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_ID);
00283   
00284   /* Return the device ID value */
00285   return (id);
00286 }
00287 
00288 /**
00289   * @brief  Read the MFXSTM32L152 device firmware version.
00290   * @param  DeviceAddr: Device address on communication Bus.  
00291   * @retval The Device FW version (two bytes).
00292   */
00293 uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr)
00294 {
00295   uint8_t  data[2];
00296 
00297   MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_FW_VERSION_MSB, data, sizeof(data)) ;
00298 
00299   /* Recompose MFX firmware value */
00300   return ((data[0] << 8) | data[1]);
00301 }
00302 
00303 /**
00304   * @brief  Enable the interrupt mode for the selected IT source
00305   * @param  DeviceAddr: Device address on communication Bus.  
00306   * @param Source: The interrupt source to be configured, could be:
00307   *   @arg  MFXSTM32L152_IRQ_GPIO: IO interrupt 
00308   *   @arg  MFXSTM32L152_IRQ_IDD : IDD interrupt    
00309   *   @arg  MFXSTM32L152_IRQ_ERROR : Error interrupt    
00310   *   @arg  MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt  
00311   *   @arg  MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty  
00312   *   @arg  MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered  
00313   *   @arg  MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full  
00314   *   @arg  MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow  
00315   * @retval None
00316   */  
00317 void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source)
00318 {
00319   uint8_t tmp = 0;
00320   
00321   /* Get the current value of the INT_EN register */
00322   tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
00323 
00324   /* Set the interrupts to be Enabled */    
00325   tmp |= Source; 
00326   
00327   /* Set the register */
00328   MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
00329 }
00330 
00331 /**
00332   * @brief  Disable the interrupt mode for the selected IT source
00333   * @param  DeviceAddr: Device address on communication Bus.  
00334   * @param  Source: The interrupt source to be configured, could be:
00335   *   @arg  MFXSTM32L152_IRQ_GPIO: IO interrupt 
00336   *   @arg  MFXSTM32L152_IRQ_IDD : IDD interrupt    
00337   *   @arg  MFXSTM32L152_IRQ_ERROR : Error interrupt    
00338   *   @arg  MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt  
00339   *   @arg  MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty  
00340   *   @arg  MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered  
00341   *   @arg  MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full  
00342   *   @arg  MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow  
00343   * @retval None
00344   */
00345 void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source)
00346 {
00347   uint8_t tmp = 0;
00348   
00349   /* Get the current value of the INT_EN register */
00350   tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
00351 
00352   /* Set the interrupts to be Enabled */    
00353   tmp &= ~Source; 
00354   
00355   /* Set the register */
00356   MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
00357 }
00358 
00359 
00360 /**
00361   * @brief  Returns the selected Global interrupt source pending bit value
00362   * @param  DeviceAddr: Device address on communication Bus. 
00363   * @param  Source: the Global interrupt source to be checked, could be:
00364   *   @arg  MFXSTM32L152_IRQ_GPIO: IO interrupt 
00365   *   @arg  MFXSTM32L152_IRQ_IDD : IDD interrupt    
00366   *   @arg  MFXSTM32L152_IRQ_ERROR : Error interrupt    
00367   *   @arg  MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt  
00368   *   @arg  MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty  
00369   *   @arg  MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered  
00370   *   @arg  MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full  
00371   *   @arg  MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow  
00372   * @retval The value of the checked Global interrupt source status.
00373   */
00374 uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source)
00375 {
00376   /* Return the global IT source status (pending or not)*/
00377   return((MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_PENDING) & Source));
00378 }
00379 
00380 /**
00381   * @brief  Clear the selected Global interrupt pending bit(s)
00382   * @param  DeviceAddr: Device address on communication Bus. 
00383   * @param  Source: the Global interrupt source to be cleared, could be any combination
00384   *         of the below values. The acknowledge signal for MFXSTM32L152_GPIOs configured in input 
00385   *         with interrupt is not on this register but in IRQ_GPI_ACK1, IRQ_GPI_ACK2 registers.          
00386   *   @arg  MFXSTM32L152_IRQ_IDD : IDD interrupt    
00387   *   @arg  MFXSTM32L152_IRQ_ERROR : Error interrupt    
00388   *   @arg  MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt  
00389   *   @arg  MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty  
00390   *   @arg  MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered  
00391   *   @arg  MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full  
00392   *   @arg  MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow  
00393   *  /\/\ IMPORTANT NOTE /\/\ must not use MFXSTM32L152_IRQ_GPIO as argument, see IRQ_GPI_ACK1 and IRQ_GPI_ACK2 registers 
00394   * @retval None
00395   */
00396 void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source)
00397 {
00398   /* Write 1 to the bits that have to be cleared */
00399   MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_ACK, Source);
00400 }
00401 
00402 /**
00403   * @brief  Set the global interrupt Polarity of IRQ_OUT_PIN.
00404   * @param  DeviceAddr: Device address on communication Bus.  
00405   * @param  Polarity: the IT mode polarity, could be one of the following values:
00406   *   @arg  MFXSTM32L152_OUT_PIN_POLARITY_LOW: Interrupt output line is active Low edge      
00407   *   @arg  MFXSTM32L152_OUT_PIN_POLARITY_HIGH: Interrupt line output is active High edge              
00408   * @retval None
00409   */
00410 void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity)
00411 {
00412   uint8_t tmp = 0;
00413   
00414   /* Get the current register value */ 
00415   tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
00416   
00417   /* Mask the polarity bits */
00418   tmp &= ~(uint8_t)0x02;
00419     
00420   /* Modify the Interrupt Output line configuration */
00421   tmp |= Polarity;
00422   
00423   /* Set the new register value */
00424   MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
00425 
00426   /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
00427   MFX_IO_Delay(1);
00428   
00429 }
00430 
00431 /**
00432   * @brief  Set the global interrupt Type of IRQ_OUT_PIN. 
00433   * @param  DeviceAddr: Device address on communication Bus.      
00434   * @param  Type: Interrupt line activity type, could be one of the following values:
00435   *   @arg  MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN: Open Drain output Interrupt line          
00436   *   @arg  MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL: Push Pull output Interrupt line            
00437   * @retval None
00438   */
00439 void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type)
00440 {
00441   uint8_t tmp = 0;
00442   
00443   /* Get the current register value */ 
00444   tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
00445   
00446   /* Mask the type bits */
00447   tmp &= ~(uint8_t)0x01;
00448     
00449   /* Modify the Interrupt Output line configuration */
00450   tmp |= Type;
00451   
00452   /* Set the new register value */
00453   MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
00454 
00455   /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
00456   MFX_IO_Delay(1);
00457   
00458 }
00459 
00460 
00461 /* ------------------------------------------------------------------ */
00462 /* ----------------------- GPIO ------------------------------------- */
00463 /* ------------------------------------------------------------------ */
00464 
00465 
00466 /**
00467   * @brief  Start the IO functionality used and enable the AF for selected IO pin(s).
00468   * @param  DeviceAddr: Device address on communication Bus.  
00469   * @param  AF_en: 0 to disable, else enabled. 
00470   * @retval None
00471   */
00472 void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin)
00473 {
00474   uint8_t mode;
00475   
00476   /* Get the current register value */
00477   mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
00478   
00479   /* Set the IO Functionalities to be Enabled */    
00480   mode |= MFXSTM32L152_GPIO_EN;  
00481   
00482   /* Enable ALTERNATE functions */
00483   /* AGPIO[0..3] can be either IDD or GPIO */ 
00484   /* AGPIO[4..7] can be either TS or GPIO */ 
00485   /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
00486   /*  however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */ 
00487   /* so if IDD and TS are both active it is better to let ALTERNATE off (0) */
00488   /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
00489   /* remind that AGPIO are less efficient then normal GPIO (They use pooling rather then EXTI */
00490   if (IO_Pin > 0xFFFF)
00491   {
00492     mode |= MFXSTM32L152_ALTERNATE_GPIO_EN;  
00493   }
00494   else
00495   {
00496     mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;  
00497   }  
00498 
00499   /* Write the new register value */  
00500   MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
00501   
00502   /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
00503   MFX_IO_Delay(1);
00504 }
00505 
00506 /**
00507   * @brief  Configures the IO pin(s) according to IO mode structure value.
00508   * @param  DeviceAddr: Device address on communication Bus.  
00509   * @param  IO_Pin: The output pin to be set or reset. This parameter can be one 
00510   *         of the following values:   
00511   *   @arg  MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
00512   * @param  IO_Mode: The IO pin mode to configure, could be one of the following values:
00513   *   @arg  IO_MODE_INPUT
00514   *   @arg  IO_MODE_OUTPUT
00515   *   @arg  IO_MODE_IT_RISING_EDGE
00516   *   @arg  IO_MODE_IT_FALLING_EDGE
00517   *   @arg  IO_MODE_IT_LOW_LEVEL
00518   *   @arg  IO_MODE_IT_HIGH_LEVEL            
00519   *   @arg  IO_MODE_INPUT_PU,
00520   *   @arg  IO_MODE_INPUT_PD,
00521   *   @arg  IO_MODE_OUTPUT_OD_PU,
00522   *   @arg  IO_MODE_OUTPUT_OD_PD,
00523   *   @arg  IO_MODE_OUTPUT_PP_PU,
00524   *   @arg  IO_MODE_OUTPUT_PP_PD,
00525   *   @arg  IO_MODE_IT_RISING_EDGE_PU
00526   *   @arg  IO_MODE_IT_FALLING_EDGE_PU
00527   *   @arg  IO_MODE_IT_LOW_LEVEL_PU
00528   *   @arg  IO_MODE_IT_HIGH_LEVEL_PU
00529   *   @arg  IO_MODE_IT_RISING_EDGE_PD
00530   *   @arg  IO_MODE_IT_FALLING_EDGE_PD
00531   *   @arg  IO_MODE_IT_LOW_LEVEL_PD
00532   *   @arg  IO_MODE_IT_HIGH_LEVEL_PD
00533   * @retval None
00534   */
00535 uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode)
00536 {
00537   uint8_t error_code = 0;
00538 
00539   /* Configure IO pin according to selected IO mode */
00540   switch(IO_Mode)
00541   {
00542   case IO_MODE_OFF: /* Off or analog mode */
00543   case IO_MODE_ANALOG: /* Off or analog mode */
00544     mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
00545     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
00546     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
00547     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
00548     break;
00549 
00550   case IO_MODE_INPUT: /* Input mode */
00551     mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
00552     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
00553     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
00554     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
00555     break;
00556     
00557   case IO_MODE_INPUT_PU: /* Input mode */
00558     mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
00559     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
00560     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
00561     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
00562     break;
00563     
00564   case IO_MODE_INPUT_PD: /* Input mode */
00565     mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
00566     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
00567     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
00568     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
00569     break;
00570 
00571   case IO_MODE_OUTPUT: /* Output mode */
00572   case IO_MODE_OUTPUT_PP_PD: /* Output mode */
00573     mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
00574     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
00575     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
00576     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
00577     break;
00578 
00579   case IO_MODE_OUTPUT_PP_PU: /* Output mode */
00580     mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
00581     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
00582     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
00583     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
00584     break;
00585 
00586   case IO_MODE_OUTPUT_OD_PD: /* Output mode */
00587     mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
00588     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
00589     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
00590     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
00591     break;
00592 
00593   case IO_MODE_OUTPUT_OD_PU: /* Output mode */
00594     mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
00595     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
00596     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
00597     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
00598     break;
00599 
00600   case IO_MODE_IT_RISING_EDGE: /* Interrupt rising edge mode */
00601     mfxstm32l152_IO_EnableIT(DeviceAddr);
00602     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); 
00603     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
00604     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
00605     mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
00606     mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
00607     mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
00608     break;
00609 
00610   case IO_MODE_IT_RISING_EDGE_PU: /* Interrupt rising edge mode */
00611     mfxstm32l152_IO_EnableIT(DeviceAddr);
00612     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
00613     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
00614     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
00615     mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
00616     mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
00617     mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin);  /* last to do: enable IT */
00618     break;
00619 
00620   case IO_MODE_IT_RISING_EDGE_PD: /* Interrupt rising edge mode */
00621     mfxstm32l152_IO_EnableIT(DeviceAddr);
00622     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
00623     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
00624     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
00625     mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);      
00626     mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE); 
00627     mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin);  /* last to do: enable IT */
00628     break;
00629 
00630   case IO_MODE_IT_FALLING_EDGE: /* Interrupt falling edge mode */
00631     mfxstm32l152_IO_EnableIT(DeviceAddr);
00632     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
00633     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
00634     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
00635     mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
00636     mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
00637     mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin);  /* last to do: enable IT */
00638     break;
00639 
00640   case IO_MODE_IT_FALLING_EDGE_PU: /* Interrupt falling edge mode */
00641     mfxstm32l152_IO_EnableIT(DeviceAddr);
00642     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
00643     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
00644     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
00645     mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
00646     mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
00647     mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin);  /* last to do: enable IT */
00648     break;
00649 
00650   case IO_MODE_IT_FALLING_EDGE_PD: /* Interrupt falling edge mode */
00651     mfxstm32l152_IO_EnableIT(DeviceAddr);
00652     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); 
00653     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
00654     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
00655     mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);    
00656     mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE); 
00657     mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin);  /* last to do: enable IT */
00658     break;
00659 
00660   case IO_MODE_IT_LOW_LEVEL: /* Low level interrupt mode */
00661     mfxstm32l152_IO_EnableIT(DeviceAddr);
00662     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); 
00663     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
00664     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
00665     mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
00666     mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
00667     mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin);  /* last to do: enable IT */
00668     break;
00669 
00670   case IO_MODE_IT_LOW_LEVEL_PU: /* Low level interrupt mode */
00671     mfxstm32l152_IO_EnableIT(DeviceAddr);
00672     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
00673     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
00674     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
00675     mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
00676     mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
00677     mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin);  /* last to do: enable IT */
00678     break;
00679 
00680   case IO_MODE_IT_LOW_LEVEL_PD: /* Low level interrupt mode */
00681     mfxstm32l152_IO_EnableIT(DeviceAddr);
00682     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
00683     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
00684     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
00685     mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
00686     mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);      
00687     mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin);  /* last to do: enable IT */
00688     break;
00689     
00690   case IO_MODE_IT_HIGH_LEVEL: /* High level interrupt mode */
00691     mfxstm32l152_IO_EnableIT(DeviceAddr);
00692     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN); 
00693     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
00694     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
00695     mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
00696     mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
00697     mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin);  /* last to do: enable IT */
00698     break;
00699 
00700   case IO_MODE_IT_HIGH_LEVEL_PU: /* High level interrupt mode */
00701     mfxstm32l152_IO_EnableIT(DeviceAddr);
00702     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
00703     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
00704     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
00705     mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
00706     mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
00707     mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin);  /* last to do: enable IT */
00708     break;
00709 
00710   case IO_MODE_IT_HIGH_LEVEL_PD: /* High level interrupt mode */
00711     mfxstm32l152_IO_EnableIT(DeviceAddr);
00712     mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
00713     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
00714     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
00715     mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
00716     mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);  
00717     mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin);  /* last to do: enable IT */
00718     break;    
00719   
00720   default:
00721     error_code = (uint8_t) IO_Mode;
00722     break;    
00723   } 
00724 
00725   return error_code;
00726 }
00727 
00728 /**
00729   * @brief  Initialize the selected IO pin direction.
00730   * @param  DeviceAddr: Device address on communication Bus.
00731   * @param  IO_Pin: The IO pin to be configured. This parameter could be any 
00732   *         combination of the following values:
00733   *   @arg  MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.   
00734   * @param  Direction: could be MFXSTM32L152_GPIO_DIR_IN or MFXSTM32L152_GPIO_DIR_OUT.      
00735   * @retval None
00736   */
00737 void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction)
00738 {
00739   mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_DIR1, IO_Pin, Direction);
00740 }
00741 
00742 /**
00743   * @brief  Set the global interrupt Type. 
00744   * @param  DeviceAddr: Device address on communication Bus.      
00745   * @param  IO_Pin: The IO pin to be configured. This parameter could be any 
00746   *         combination of the following values:
00747   *   @arg  MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.   
00748   * @param  Evt: Interrupt line activity type, could be one of the following values:
00749   *   @arg  MFXSTM32L152_IRQ_GPI_EVT_LEVEL: Interrupt line is active in level model         
00750   *   @arg  MFXSTM32L152_IRQ_GPI_EVT_EDGE: Interrupt line is active in edge model           
00751   * @retval None
00752   */
00753 void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt)
00754 {
00755   mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1, IO_Pin, Evt);
00756   MFX_IO_Delay(1);
00757 }
00758 
00759 /**
00760   * @brief  Configure the Edge for which a transition is detectable for the
00761   *         selected pin.
00762   * @param  DeviceAddr: Device address on communication Bus.
00763   * @param  IO_Pin: The IO pin to be configured. This parameter could be any 
00764   *         combination of the following values:
00765   *   @arg  MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.  
00766   * @param  Evt: Interrupt line activity type, could be one of the following values:
00767   *   @arg  MFXSTM32L152_IRQ_GPI_TYPE_LLFE: Interrupt line is active in Low Level or Falling Edge         
00768   *   @arg  MFXSTM32L152_IRQ_GPI_TYPE_HLRE: Interrupt line is active in High Level or Rising Edge           
00769   * @retval None
00770   */
00771 void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type)
00772 {
00773   mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1, IO_Pin, Type);
00774   MFX_IO_Delay(1);
00775 }
00776 
00777 /**
00778   * @brief  When GPIO is in output mode, puts the corresponding GPO in High (1) or Low (0) level.
00779   * @param  DeviceAddr: Device address on communication Bus.  
00780   * @param  IO_Pin: The output pin to be set or reset. This parameter can be one 
00781   *         of the following values:
00782   *   @arg  MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. 
00783   * @param PinState: The new IO pin state.
00784   * @retval None
00785   */
00786 void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState)
00787 {
00788   /* Apply the bit value to the selected pin */
00789   if (PinState != 0)
00790   {
00791     /* Set the SET register */
00792     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_SET1, IO_Pin, 1);
00793   }
00794   else
00795   {
00796     /* Set the CLEAR register */
00797     mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_CLR1, IO_Pin, 1);
00798   } 
00799 }
00800 
00801 /**
00802   * @brief  Return the state of the selected IO pin(s).
00803   * @param  DeviceAddr: Device address on communication Bus.  
00804   * @param  IO_Pin: The output pin to be set or reset. This parameter can be one 
00805   *         of the following values:
00806   *   @arg  MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. 
00807   * @retval IO pin(s) state.
00808   */
00809 uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin)
00810 {
00811   uint8_t tmp1;
00812   uint16_t tmp2;
00813   uint32_t tmp3;
00814   
00815   tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE1);
00816   tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE2);
00817   tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE3);
00818   tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
00819   
00820   return(tmp3 & IO_Pin);
00821 }
00822 
00823 /**
00824   * @brief  Enable the global IO interrupt source.
00825   * @param  DeviceAddr: Device address on communication Bus.  
00826   * @retval None
00827   */
00828 void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr)
00829 { 
00830   MFX_IO_ITConfig();
00831     
00832   /* Enable global IO IT source */
00833   mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
00834 }
00835 
00836 /**
00837   * @brief  Disable the global IO interrupt source.
00838   * @param  DeviceAddr: Device address on communication Bus.   
00839   * @retval None
00840   */
00841 void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr)
00842 {
00843   /* Disable global IO IT source */
00844   mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);    
00845 }
00846   
00847 /**
00848   * @brief  Enable interrupt mode for the selected IO pin(s).
00849   * @param  DeviceAddr: Device address on communication Bus.
00850   * @param  IO_Pin: The IO interrupt to be enabled. This parameter could be any 
00851   *         combination of the following values:
00852   *   @arg  MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
00853   * @retval None
00854   */
00855 void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
00856 {
00857   mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 1);
00858 }
00859 
00860 /**
00861   * @brief  Disable interrupt mode for the selected IO pin(s).
00862   * @param  DeviceAddr: Device address on communication Bus.
00863   * @param  IO_Pin: The IO interrupt to be disabled. This parameter could be any 
00864   *         combination of the following values:
00865   *   @arg  MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
00866   * @retval None
00867   */
00868 void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
00869 {
00870   mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 0);
00871 }
00872 
00873 
00874 /**
00875   * @brief  Check the status of the selected IO interrupt pending bit
00876   * @param  DeviceAddr: Device address on communication Bus.
00877   * @param  IO_Pin: The IO interrupt to be checked could be:
00878   *   @arg  MFXSTM32L152_GPIO_PIN_x Where x can be from 0 to 23.             
00879   * @retval Status of the checked IO pin(s).
00880   */
00881 uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin)
00882 {
00883   /* Get the Interrupt status */
00884   uint8_t tmp1;
00885   uint16_t tmp2;
00886   uint32_t tmp3;
00887 
00888   tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1);
00889   tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2);
00890   tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3);
00891   tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
00892   
00893   return(tmp3 & IO_Pin);
00894 }
00895 
00896 /**
00897   * @brief  Clear the selected IO interrupt pending bit(s). It clear automatically also the general MFXSTM32L152_REG_ADR_IRQ_PENDING
00898   * @param  DeviceAddr: Device address on communication Bus.
00899   * @param  IO_Pin: the IO interrupt to be cleared, could be:
00900   *   @arg  MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.            
00901   * @retval None
00902   */
00903 void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin)
00904 {
00905   /* Clear the IO IT pending bit(s) by acknowledging */
00906   /* it cleans automatically also the Global IRQ_GPIO */
00907   /* normally this function is called under interrupt */
00908   uint8_t pin_0_7, pin_8_15, pin_16_23;
00909 
00910   pin_0_7   = IO_Pin & 0x0000ff;
00911   pin_8_15  = IO_Pin >> 8;
00912   pin_8_15   = pin_8_15 & 0x00ff;
00913   pin_16_23 = IO_Pin >> 16;
00914 
00915   if (pin_0_7)
00916   {
00917     MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1, pin_0_7);
00918   }
00919   if (pin_8_15)
00920   {
00921     MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2, pin_8_15);
00922   }
00923   if (pin_16_23)
00924   {
00925     MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3, pin_16_23);
00926   }
00927 }
00928 
00929 
00930 /**
00931   * @brief  Enable the AF for aGPIO.
00932   * @param  DeviceAddr: Device address on communication Bus.  
00933   * @retval None
00934   */
00935 void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr)
00936 {
00937   uint8_t mode;
00938 
00939   /* Get the current register value */
00940   mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
00941   
00942   /* Enable ALTERNATE functions */
00943   /* AGPIO[0..3] can be either IDD or GPIO */ 
00944   /* AGPIO[4..7] can be either TS or GPIO */ 
00945   /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
00946   /*  however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */ 
00947   /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
00948   /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
00949   /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
00950   mode |= MFXSTM32L152_ALTERNATE_GPIO_EN;  
00951  
00952   /* Write the new register value */  
00953   MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
00954 }
00955 
00956 /**
00957   * @brief  Disable the AF for aGPIO.
00958   * @param  DeviceAddr: Device address on communication Bus.  
00959   * @retval None
00960   */
00961  void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr)
00962 {
00963   uint8_t mode;
00964 
00965   /* Get the current register value */
00966   mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
00967   
00968   /* Enable ALTERNATE functions */
00969   /* AGPIO[0..3] can be either IDD or GPIO */ 
00970   /* AGPIO[4..7] can be either TS or GPIO */ 
00971   /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
00972   /*  however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */ 
00973   /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
00974   /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
00975   /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
00976   mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;  
00977  
00978   /* Write the new register value */  
00979   MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
00980   
00981 }
00982 
00983 
00984 /* ------------------------------------------------------------------ */
00985 /* --------------------- TOUCH SCREEN ------------------------------- */
00986 /* ------------------------------------------------------------------ */
00987 
00988 /**
00989   * @brief  Configures the touch Screen Controller (Single point detection)
00990   * @param  DeviceAddr: Device address on communication Bus.
00991   * @retval None.
00992   */
00993 void mfxstm32l152_TS_Start(uint16_t DeviceAddr)
00994 {
00995   uint8_t mode;
00996 
00997   /* Get the current register value */
00998   mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
00999   
01000   /* Set the Functionalities to be Enabled */    
01001   mode |= MFXSTM32L152_TS_EN;  
01002   
01003   /* Set the new register value */  
01004   MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
01005      
01006   /* Wait for 2 ms */
01007   MFX_IO_Delay(2); 
01008   
01009   /* Select 2 nF filter capacitor */
01010   /* Configuration: 
01011      - Touch average control    : 4 samples
01012      - Touch delay time         : 500 uS
01013      - Panel driver setting time: 500 uS 
01014   */
01015   MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_SETTLING, 0x32);
01016   MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TOUCH_DET_DELAY, 0x5);
01017   MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_AVE, 0x04);
01018   
01019   /* Configure the Touch FIFO threshold: single point reading */
01020   MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, 0x01);
01021   
01022   /* Clear the FIFO memory content. */
01023   MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
01024 
01025   /* Touch screen control configuration :
01026      - No window tracking index
01027    */
01028   MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TRACK, 0x00);
01029   
01030  
01031   /*  Clear all the IT status pending bits if any */
01032   mfxstm32l152_IO_ClearIT(DeviceAddr, 0xFFFFFF);
01033 
01034   /* Wait for 1 ms delay */
01035   MFX_IO_Delay(1);
01036 }
01037 
01038 /**
01039   * @brief  Return if there is touch detected or not.
01040   * @param  DeviceAddr: Device address on communication Bus.
01041   * @retval Touch detected state.
01042   */
01043 uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr)
01044 {
01045   uint8_t state;
01046   uint8_t ret = 0;
01047  
01048   state = MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_STA);
01049   state = ((state & (uint8_t)MFXSTM32L152_TS_CTRL_STATUS) == (uint8_t)MFXSTM32L152_TS_CTRL_STATUS);
01050   
01051   if(state > 0)
01052   {
01053     if(MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_LEVEL) > 0)
01054     {
01055       ret = 1;
01056     }
01057   }
01058   
01059   return ret;
01060 }
01061 
01062 /**
01063   * @brief  Get the touch screen X and Y positions values
01064   * @param  DeviceAddr: Device address on communication Bus.
01065   * @param  X: Pointer to X position value
01066   * @param  Y: Pointer to Y position value   
01067   * @retval None.
01068   */
01069 void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y)
01070 {
01071   uint8_t  data_xy[3];
01072 
01073   MFX_IO_ReadMultiple(DeviceAddr, MFXSTM32L152_TS_XY_DATA, data_xy, sizeof(data_xy)) ;
01074   
01075   /* Calculate positions values */
01076   *X = (data_xy[1]<<4) + (data_xy[0]>>4); 
01077   *Y = (data_xy[2]<<4) + (data_xy[0]&4); 
01078 
01079   /* Reset the FIFO memory content. */
01080   MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
01081 }
01082 
01083 /**
01084   * @brief  Configure the selected source to generate a global interrupt or not
01085   * @param  DeviceAddr: Device address on communication Bus.  
01086   * @retval None
01087   */
01088 void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr)
01089 {
01090   MFX_IO_ITConfig();
01091   
01092   /* Enable global TS IT source */
01093   mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
01094 }
01095 
01096 /**
01097   * @brief  Configure the selected source to generate a global interrupt or not
01098   * @param  DeviceAddr: Device address on communication Bus.    
01099   * @retval None
01100   */
01101 void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr)
01102 {
01103   /* Disable global TS IT source */
01104   mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);    
01105 }
01106 
01107 /**
01108   * @brief  Configure the selected source to generate a global interrupt or not
01109   * @param  DeviceAddr: Device address on communication Bus.    
01110   * @retval TS interrupts status
01111   */
01112 uint8_t mfxstm32l152_TS_ITStatus(uint16_t DeviceAddr)
01113 {
01114   /* Return TS interrupts status */
01115   return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_TS));
01116 }
01117 
01118 /**
01119   * @brief  Configure the selected source to generate a global interrupt or not
01120   * @param  DeviceAddr: Device address on communication Bus.  
01121   * @retval None
01122   */
01123 void mfxstm32l152_TS_ClearIT(uint16_t DeviceAddr)
01124 {
01125   /* Clear the global TS IT source */
01126   mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_TS);
01127 }
01128 
01129 /* ------------------------------------------------------------------ */
01130 /* --------------------- IDD MEASUREMENT ---------------------------- */
01131 /* ------------------------------------------------------------------ */
01132 
01133 /**
01134   * @brief  Launch IDD current measurement
01135   * @param  DeviceAddr: Device address on communication Bus
01136   * @retval None.
01137   */
01138 void mfxstm32l152_IDD_Start(uint16_t DeviceAddr)
01139 {
01140   uint8_t mode = 0;
01141 
01142   /* Get the current register value */
01143   mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
01144 
01145   /* Set the Functionalities to be enabled */
01146   mode |= MFXSTM32L152_IDD_CTRL_REQ;
01147 
01148   /* Start measurement campaign */
01149   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
01150 }
01151 
01152 /**
01153   * @brief  Configures the IDD current measurement
01154   * @param  DeviceAddr: Device address on communication Bus.
01155   * @param  MfxIddConfig: Parameters depending on hardware config.
01156   * @retval None
01157   */
01158 void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig)
01159 {
01160   uint8_t value = 0;
01161   uint8_t mode = 0;
01162 
01163   /* Get the current register value */
01164   mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
01165 
01166   if((mode & MFXSTM32L152_IDD_EN) != MFXSTM32L152_IDD_EN)
01167   {
01168     /* Set the Functionalities to be enabled */
01169     mode |= MFXSTM32L152_IDD_EN;
01170 
01171     /* Set the new register value */
01172     MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
01173   }
01174 
01175   /* Control register setting: number of shunts */
01176   value =  ((MfxIddConfig.ShuntNbUsed << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
01177   value |= (MfxIddConfig.VrefMeasurement & MFXSTM32L152_IDD_CTRL_VREF_DIS);
01178   value |= (MfxIddConfig.Calibration & MFXSTM32L152_IDD_CTRL_CAL_DIS);
01179   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, value);
01180 
01181   /* Idd pre delay configuration: unit and value*/
01182   value = (MfxIddConfig.PreDelayUnit & MFXSTM32L152_IDD_PREDELAY_UNIT) |
01183           (MfxIddConfig.PreDelayValue & MFXSTM32L152_IDD_PREDELAY_VALUE);
01184   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_PRE_DELAY, value);
01185 
01186   /* Shunt 0 register value: MSB then LSB */
01187   value = (uint8_t) (MfxIddConfig.Shunt0Value >> 8);
01188   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB, value);
01189   value = (uint8_t) (MfxIddConfig.Shunt0Value);
01190   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB, value);
01191 
01192   /* Shunt 1 register value: MSB then LSB */
01193   value = (uint8_t) (MfxIddConfig.Shunt1Value >> 8);
01194   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB, value);
01195   value = (uint8_t) (MfxIddConfig.Shunt1Value);
01196   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB, value);
01197 
01198   /* Shunt 2 register value: MSB then LSB */
01199   value = (uint8_t) (MfxIddConfig.Shunt2Value >> 8);
01200   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB, value);
01201   value = (uint8_t) (MfxIddConfig.Shunt2Value);
01202   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB, value);
01203 
01204   /* Shunt 3 register value: MSB then LSB */
01205   value = (uint8_t) (MfxIddConfig.Shunt3Value >> 8);
01206   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB, value);
01207   value = (uint8_t) (MfxIddConfig.Shunt3Value);
01208   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB, value);
01209 
01210   /* Shunt 4 register value: MSB then LSB */
01211   value = (uint8_t) (MfxIddConfig.Shunt4Value >> 8);
01212   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB, value);
01213   value = (uint8_t) (MfxIddConfig.Shunt4Value);
01214   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB, value);
01215 
01216   /* Shunt 0 stabilization delay */
01217   value = MfxIddConfig.Shunt0StabDelay;
01218   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION, value);
01219 
01220   /* Shunt 1 stabilization delay */
01221   value = MfxIddConfig.Shunt1StabDelay;
01222   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION, value);
01223 
01224   /* Shunt 2 stabilization delay */
01225   value = MfxIddConfig.Shunt2StabDelay;
01226   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION, value);
01227 
01228   /* Shunt 3 stabilization delay */
01229   value = MfxIddConfig.Shunt3StabDelay;
01230   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION, value);
01231 
01232   /* Shunt 4 stabilization delay */
01233   value = MfxIddConfig.Shunt4StabDelay;
01234   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION, value);
01235 
01236   /* Idd ampli gain value: MSB then LSB */
01237   value = (uint8_t) (MfxIddConfig.AmpliGain >> 8);
01238   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_MSB, value);
01239   value = (uint8_t) (MfxIddConfig.AmpliGain);
01240   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_LSB, value);
01241 
01242   /* Idd VDD min value: MSB then LSB */
01243   value = (uint8_t) (MfxIddConfig.VddMin >> 8);
01244   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB, value);
01245   value = (uint8_t) (MfxIddConfig.VddMin);
01246   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB, value);
01247 
01248   /* Idd number of measurements */
01249   value = MfxIddConfig.MeasureNb;
01250   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS, value);
01251 
01252   /* Idd delta delay configuration: unit and value */
01253   value = (MfxIddConfig.DeltaDelayUnit & MFXSTM32L152_IDD_DELTADELAY_UNIT) |
01254           (MfxIddConfig.DeltaDelayValue & MFXSTM32L152_IDD_DELTADELAY_VALUE);
01255   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY, value);
01256 
01257   /* Idd number of shut on board */
01258   value = MfxIddConfig.ShuntNbOnBoard;
01259   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD, value);
01260 }
01261 
01262 /**
01263   * @brief  This function allows to modify number of shunt used for a measurement
01264   * @param  DeviceAddr: Device address on communication Bus
01265   * @retval None.
01266   */
01267 void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit)
01268 {
01269   uint8_t mode = 0;
01270 
01271   /* Get the current register value */
01272   mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
01273 
01274   /* Clear number of shunt limit */
01275   mode &= ~(MFXSTM32L152_IDD_CTRL_SHUNT_NB);
01276 
01277   /* Clear number of shunt limit */
01278   mode |= ((ShuntNbLimit << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
01279 
01280   /* Write noewx desired limit */
01281   MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
01282 }
01283 
01284 /**
01285   * @brief  Get Idd current value
01286   * @param  DeviceAddr: Device address on communication Bus
01287   * @param  ReadValue: Pointer on value to be read
01288   * @retval Idd value in 10 nA.
01289   */
01290 void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue)
01291 {
01292   uint8_t  data[3];
01293 
01294   MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VALUE_MSB, data, sizeof(data)) ;
01295 
01296   /* Recompose Idd current value */
01297   *ReadValue = (data[0] << 16) | (data[1] << 8) | data[2];
01298 
01299 }
01300 
01301 /**
01302   * @brief  Get Last shunt used for measurement
01303   * @param  DeviceAddr: Device address on communication Bus
01304   * @retval Last shunt used 
01305   */
01306 uint8_t  mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr)
01307 {
01308   return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT_USED));
01309 }
01310 
01311 /**
01312   * @brief  Configure mfx to enable Idd interrupt
01313   * @param  DeviceAddr: Device address on communication Bus.
01314   * @retval None
01315   */
01316 void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr)
01317 {
01318   MFX_IO_ITConfig();
01319 
01320   /* Enable global IDD interrupt source */
01321   mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
01322 }
01323 
01324 /**
01325   * @brief  Clear Idd global interrupt
01326   * @param  DeviceAddr: Device address on communication Bus.
01327   * @retval None
01328   */
01329 void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr)
01330 {
01331   /* Clear the global IDD interrupt source */
01332   mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_IDD);
01333 }
01334 
01335 /**
01336   * @brief  get Idd interrupt status
01337   * @param  DeviceAddr: Device address on communication Bus.
01338   * @retval IDD interrupts status
01339   */
01340 uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr)
01341 {
01342   /* Return IDD interrupt status */
01343   return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_IDD));
01344 }
01345 
01346 /**
01347   * @brief  disable Idd interrupt
01348   * @param  DeviceAddr: Device address on communication Bus.
01349   * @retval None.
01350   */
01351 void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr)
01352 {
01353   /* Disable global IDD interrupt source */
01354   mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
01355 }
01356 
01357 
01358 /* ------------------------------------------------------------------ */
01359 /* --------------------- ERROR MANAGEMENT --------------------------- */
01360 /* ------------------------------------------------------------------ */
01361 
01362 /**
01363   * @brief  Read Error Source.
01364   * @param  DeviceAddr: Device address on communication Bus.
01365   * @retval Error message code with error source
01366   */
01367 uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr)
01368 {
01369   /* Get the current source register value */
01370   return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_SRC));
01371 }
01372 
01373 /**
01374   * @brief  Read Error Message
01375   * @param  DeviceAddr: Device address on communication Bus.
01376   * @retval Error message code with error source
01377   */
01378 uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr)
01379 {
01380   /* Get the current message register value */
01381   return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_MSG));
01382 }
01383 
01384 /**
01385   * @brief  Enable Error global interrupt
01386   * @param  DeviceAddr: Device address on communication Bus.
01387   * @retval None
01388   */
01389 
01390 void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr)
01391 {
01392   MFX_IO_ITConfig();
01393 
01394   /* Enable global Error interrupt source */
01395   mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
01396 }
01397 
01398 /**
01399   * @brief  Clear Error global interrupt
01400   * @param  DeviceAddr: Device address on communication Bus.
01401   * @retval None
01402   */
01403 void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr)
01404 {
01405   /* Clear the global Error interrupt source */
01406   mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
01407 }
01408 
01409 /**
01410   * @brief  get Error interrupt status
01411   * @param  DeviceAddr: Device address on communication Bus.
01412   * @retval Error interrupts status
01413   */
01414 uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr)
01415 {
01416   /* Return Error interrupt status */
01417   return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_ERROR));
01418 }
01419 
01420 /**
01421   * @brief  disable Error interrupt
01422   * @param  DeviceAddr: Device address on communication Bus.
01423   * @retval None.
01424   */
01425 void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr)
01426 {
01427   /* Disable global Error interrupt source */
01428   mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
01429 }
01430 
01431 /**
01432   * @brief  FOR DEBUG ONLY
01433   */
01434 uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr)
01435 {
01436   /* Get the current register value */ 
01437   return(MFX_IO_Read((uint8_t) DeviceAddr, RegAddr));
01438 }
01439 
01440 void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value)
01441 {
01442   /* set the current register value */ 
01443   MFX_IO_Write((uint8_t) DeviceAddr, RegAddr, Value);
01444 }
01445 
01446 /* ------------------------------------------------------------------ */
01447 /* ----------------------- Private functions ------------------------ */
01448 /* ------------------------------------------------------------------ */
01449 /**
01450   * @brief  Check if the device instance of the selected address is already registered
01451   *         and return its index  
01452   * @param  DeviceAddr: Device address on communication Bus.
01453   * @retval Index of the device instance if registered, 0xFF if not.
01454   */
01455 static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr)
01456 {
01457   uint8_t idx = 0;
01458   
01459   /* Check all the registered instances */
01460   for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
01461   {
01462     if(mfxstm32l152[idx] == DeviceAddr)
01463     {
01464       return idx; 
01465     }
01466   }
01467   
01468   return 0xFF;
01469 }
01470 
01471 /**
01472   * @brief  Release registered device instance
01473   * @param  DeviceAddr: Device address on communication Bus.
01474   * @retval Index of released device instance, 0xFF if not.
01475   */
01476 static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr)
01477 {
01478   uint8_t idx = 0;
01479   
01480   /* Check for all the registered instances */
01481   for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
01482   {
01483     if(mfxstm32l152[idx] == DeviceAddr)
01484     {
01485       mfxstm32l152[idx] = 0;
01486       return idx;
01487     }
01488   }
01489   return 0xFF;
01490 }
01491 
01492 /**
01493   * @brief  Internal routine
01494   * @param  DeviceAddr: Device address on communication Bus. 
01495   * @param  RegisterAddr: Register Address
01496   * @param  PinPosition: Pin [0:23]
01497   * @param  PinValue: 0/1
01498   * @retval None
01499   */
01500 void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue )
01501 {
01502   uint8_t tmp = 0;
01503   uint8_t pin_0_7, pin_8_15, pin_16_23;
01504 
01505   pin_0_7   = PinPosition & 0x0000ff;
01506   pin_8_15  = PinPosition >> 8;
01507   pin_8_15   = pin_8_15 & 0x00ff;
01508   pin_16_23 = PinPosition >> 16;
01509   
01510   if (pin_0_7)
01511   {  
01512     /* Get the current register value */ 
01513     tmp = MFX_IO_Read(DeviceAddr, RegisterAddr);
01514   
01515     /* Set the selected pin direction */
01516     if (PinValue != 0)
01517     {
01518       tmp |= (uint8_t)pin_0_7;
01519     }  
01520     else 
01521     {
01522       tmp &= ~(uint8_t)pin_0_7;
01523     }
01524   
01525     /* Set the new register value */
01526     MFX_IO_Write(DeviceAddr, RegisterAddr, tmp);
01527   }
01528 
01529   if (pin_8_15)
01530   {
01531     /* Get the current register value */ 
01532     tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+1);
01533   
01534     /* Set the selected pin direction */
01535     if (PinValue != 0)
01536     {
01537       tmp |= (uint8_t)pin_8_15;
01538     }  
01539     else 
01540     {
01541       tmp &= ~(uint8_t)pin_8_15;
01542     }
01543   
01544     /* Set the new register value */
01545     MFX_IO_Write(DeviceAddr, RegisterAddr+1, tmp);
01546   }  
01547 
01548   if (pin_16_23)
01549   {
01550     /* Get the current register value */ 
01551     tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+2);
01552   
01553     /* Set the selected pin direction */
01554     if (PinValue != 0)
01555     {
01556       tmp |= (uint8_t)pin_16_23;
01557     }  
01558     else 
01559     {
01560       tmp &= ~(uint8_t)pin_16_23;
01561     }
01562   
01563     /* Set the new register value */
01564     MFX_IO_Write(DeviceAddr, RegisterAddr+2, tmp);
01565   } 
01566 }
01567 
01568 
01569 /**
01570   * @}
01571   */ 
01572 
01573 /**
01574   * @}
01575   */ 
01576 
01577 /**
01578   * @}
01579   */ 
01580 
01581 /**
01582   * @}
01583   */      
01584 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
01585