BSP driver for DISCO_L496AG
Dependents: DISCO_L496AG-LCD-prova_1 DISCO_L496AG-LCD-prova_2 DISCO_L496AG-LCD-demo DISCO_L496AG-SRAM-demo
mfxstm32l152.h
00001 /** 00002 ****************************************************************************** 00003 * @file mfxstm32l152.h 00004 * @author MCD Application Team 00005 * @brief This file contains all the functions prototypes for the 00006 * mfxstm32l152.c IO expander driver. 00007 ****************************************************************************** 00008 * @attention 00009 * 00010 * <h2><center>© Copyright (c) 2015 STMicroelectronics. 00011 * All rights reserved.</center></h2> 00012 * 00013 * This software component is licensed by ST under BSD 3-Clause license, 00014 * the "License"; You may not use this file except in compliance with the 00015 * License. You may obtain a copy of the License at: 00016 * opensource.org/licenses/BSD-3-Clause 00017 * 00018 ****************************************************************************** 00019 */ 00020 00021 /* Define to prevent recursive inclusion -------------------------------------*/ 00022 #ifndef __MFXSTM32L152_H 00023 #define __MFXSTM32L152_H 00024 00025 #ifdef __cplusplus 00026 extern "C" { 00027 #endif 00028 00029 /* Includes ------------------------------------------------------------------*/ 00030 #include "../Common/ts.h" 00031 #include "../Common/io.h" 00032 #include "../Common/idd.h" 00033 00034 /** @addtogroup BSP 00035 * @{ 00036 */ 00037 00038 /** @addtogroup Component 00039 * @{ 00040 */ 00041 00042 /** @defgroup MFXSTM32L152 00043 * @{ 00044 */ 00045 00046 /* Exported types ------------------------------------------------------------*/ 00047 00048 /** @defgroup MFXSTM32L152_Exported_Types 00049 * @{ 00050 */ 00051 typedef struct 00052 { 00053 uint8_t SYS_CTRL; 00054 uint8_t ERROR_SRC; 00055 uint8_t ERROR_MSG; 00056 uint8_t IRQ_OUT; 00057 uint8_t IRQ_SRC_EN; 00058 uint8_t IRQ_PENDING; 00059 uint8_t IDD_CTRL; 00060 uint8_t IDD_PRE_DELAY; 00061 uint8_t IDD_SHUNT0_MSB; 00062 uint8_t IDD_SHUNT0_LSB; 00063 uint8_t IDD_SHUNT1_MSB; 00064 uint8_t IDD_SHUNT1_LSB; 00065 uint8_t IDD_SHUNT2_MSB; 00066 uint8_t IDD_SHUNT2_LSB; 00067 uint8_t IDD_SHUNT3_MSB; 00068 uint8_t IDD_SHUNT3_LSB; 00069 uint8_t IDD_SHUNT4_MSB; 00070 uint8_t IDD_SHUNT4_LSB; 00071 uint8_t IDD_GAIN_MSB; 00072 uint8_t IDD_GAIN_LSB; 00073 uint8_t IDD_VDD_MIN_MSB; 00074 uint8_t IDD_VDD_MIN_LSB; 00075 uint8_t IDD_VALUE_MSB; 00076 uint8_t IDD_VALUE_MID; 00077 uint8_t IDD_VALUE_LSB; 00078 uint8_t IDD_CAL_OFFSET_MSB; 00079 uint8_t IDD_CAL_OFFSET_LSB; 00080 uint8_t IDD_SHUNT_USED; 00081 }IDD_dbgTypeDef; 00082 00083 /** 00084 * @} 00085 */ 00086 00087 /* Exported constants --------------------------------------------------------*/ 00088 00089 /** @defgroup MFXSTM32L152_Exported_Constants 00090 * @{ 00091 */ 00092 00093 /** 00094 * @brief MFX COMMON defines 00095 */ 00096 00097 /** 00098 * @brief Register address: chip IDs (R) 00099 */ 00100 #define MFXSTM32L152_REG_ADR_ID ((uint8_t)0x00) 00101 /** 00102 * @brief Register address: chip FW_VERSION (R) 00103 */ 00104 #define MFXSTM32L152_REG_ADR_FW_VERSION_MSB ((uint8_t)0x01) 00105 #define MFXSTM32L152_REG_ADR_FW_VERSION_LSB ((uint8_t)0x00) 00106 /** 00107 * @brief Register address: System Control Register (R/W) 00108 */ 00109 #define MFXSTM32L152_REG_ADR_SYS_CTRL ((uint8_t)0x40) 00110 /** 00111 * @brief Register address: Vdd monitoring (R) 00112 */ 00113 #define MFXSTM32L152_REG_ADR_VDD_REF_MSB ((uint8_t)0x06) 00114 #define MFXSTM32L152_REG_ADR_VDD_REF_LSB ((uint8_t)0x07) 00115 /** 00116 * @brief Register address: Error source 00117 */ 00118 #define MFXSTM32L152_REG_ADR_ERROR_SRC ((uint8_t)0x03) 00119 /** 00120 * @brief Register address: Error Message 00121 */ 00122 #define MFXSTM32L152_REG_ADR_ERROR_MSG ((uint8_t)0x04) 00123 00124 /** 00125 * @brief Reg Addr IRQs: to config the pin that informs Main MCU that MFX events appear 00126 */ 00127 #define MFXSTM32L152_REG_ADR_MFX_IRQ_OUT ((uint8_t)0x41) 00128 /** 00129 * @brief Reg Addr IRQs: to select the events which activate the MFXSTM32L152_IRQ_OUT signal 00130 */ 00131 #define MFXSTM32L152_REG_ADR_IRQ_SRC_EN ((uint8_t)0x42) 00132 /** 00133 * @brief Reg Addr IRQs: the Main MCU must read the IRQ_PENDING register to know the interrupt reason 00134 */ 00135 #define MFXSTM32L152_REG_ADR_IRQ_PENDING ((uint8_t)0x08) 00136 /** 00137 * @brief Reg Addr IRQs: the Main MCU must acknowledge it thanks to a writing access to the IRQ_ACK register 00138 */ 00139 #define MFXSTM32L152_REG_ADR_IRQ_ACK ((uint8_t)0x44) 00140 00141 /** 00142 * @brief MFXSTM32L152_REG_ADR_ID choices 00143 */ 00144 #define MFXSTM32L152_ID_1 ((uint8_t)0x7B) 00145 #define MFXSTM32L152_ID_2 ((uint8_t)0x79) 00146 00147 /** 00148 * @brief MFXSTM32L152_REG_ADR_SYS_CTRL choices 00149 */ 00150 #define MFXSTM32L152_SWRST ((uint8_t)0x80) 00151 #define MFXSTM32L152_STANDBY ((uint8_t)0x40) 00152 #define MFXSTM32L152_ALTERNATE_GPIO_EN ((uint8_t)0x08) /* by the way if IDD and TS are enabled they take automatically the AF pins*/ 00153 #define MFXSTM32L152_IDD_EN ((uint8_t)0x04) 00154 #define MFXSTM32L152_TS_EN ((uint8_t)0x02) 00155 #define MFXSTM32L152_GPIO_EN ((uint8_t)0x01) 00156 00157 /** 00158 * @brief MFXSTM32L152_REG_ADR_ERROR_SRC choices 00159 */ 00160 #define MFXSTM32L152_IDD_ERROR_SRC ((uint8_t)0x04) /* Error raised by Idd */ 00161 #define MFXSTM32L152_TS_ERROR_SRC ((uint8_t)0x02) /* Error raised by Touch Screen */ 00162 #define MFXSTM32L152_GPIO_ERROR_SRC ((uint8_t)0x01) /* Error raised by Gpio */ 00163 00164 /** 00165 * @brief MFXSTM32L152_REG_ADR_MFX_IRQ_OUT choices 00166 */ 00167 #define MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN ((uint8_t)0x00) 00168 #define MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL ((uint8_t)0x01) 00169 #define MFXSTM32L152_OUT_PIN_POLARITY_LOW ((uint8_t)0x00) 00170 #define MFXSTM32L152_OUT_PIN_POLARITY_HIGH ((uint8_t)0x02) 00171 00172 /** 00173 * @brief REG_ADR_IRQ_SRC_EN, REG_ADR_IRQ_PENDING & REG_ADR_IRQ_ACK choices 00174 */ 00175 #define MFXSTM32L152_IRQ_TS_OVF ((uint8_t)0x80) /* TouchScreen FIFO Overflow irq*/ 00176 #define MFXSTM32L152_IRQ_TS_FULL ((uint8_t)0x40) /* TouchScreen FIFO Full irq*/ 00177 #define MFXSTM32L152_IRQ_TS_TH ((uint8_t)0x20) /* TouchScreen FIFO threshold triggered irq*/ 00178 #define MFXSTM32L152_IRQ_TS_NE ((uint8_t)0x10) /* TouchScreen FIFO Not Empty irq*/ 00179 #define MFXSTM32L152_IRQ_TS_DET ((uint8_t)0x08) /* TouchScreen Detect irq*/ 00180 #define MFXSTM32L152_IRQ_ERROR ((uint8_t)0x04) /* Error message from MFXSTM32L152 firmware irq */ 00181 #define MFXSTM32L152_IRQ_IDD ((uint8_t)0x02) /* IDD function irq */ 00182 #define MFXSTM32L152_IRQ_GPIO ((uint8_t)0x01) /* General GPIO irq (only for SRC_EN and PENDING) */ 00183 #define MFXSTM32L152_IRQ_ALL ((uint8_t)0xFF) /* All global interrupts */ 00184 #define MFXSTM32L152_IRQ_TS (MFXSTM32L152_IRQ_TS_DET | MFXSTM32L152_IRQ_TS_NE | MFXSTM32L152_IRQ_TS_TH | MFXSTM32L152_IRQ_TS_FULL | MFXSTM32L152_IRQ_TS_OVF ) 00185 00186 00187 /** 00188 * @brief GPIO: 24 programmable input/output called MFXSTM32L152_GPIO[23:0] are provided 00189 */ 00190 00191 /** 00192 * @brief Reg addr: GPIO DIRECTION (R/W): GPIO pins direction: (0) input, (1) output. 00193 */ 00194 #define MFXSTM32L152_REG_ADR_GPIO_DIR1 ((uint8_t)0x60) /* gpio [0:7] */ 00195 #define MFXSTM32L152_REG_ADR_GPIO_DIR2 ((uint8_t)0x61) /* gpio [8:15] */ 00196 #define MFXSTM32L152_REG_ADR_GPIO_DIR3 ((uint8_t)0x62) /* agpio [0:7] */ 00197 /** 00198 * @brief Reg addr: GPIO TYPE (R/W): If GPIO in output: (0) output push pull, (1) output open drain. 00199 * If GPIO in input: (0) input without pull resistor, (1) input with pull resistor. 00200 */ 00201 #define MFXSTM32L152_REG_ADR_GPIO_TYPE1 ((uint8_t)0x64) /* gpio [0:7] */ 00202 #define MFXSTM32L152_REG_ADR_GPIO_TYPE2 ((uint8_t)0x65) /* gpio [8:15] */ 00203 #define MFXSTM32L152_REG_ADR_GPIO_TYPE3 ((uint8_t)0x66) /* agpio [0:7] */ 00204 /** 00205 * @brief Reg addr: GPIO PULL_UP_PULL_DOWN (R/W): discussion open with Jean Claude 00206 */ 00207 #define MFXSTM32L152_REG_ADR_GPIO_PUPD1 ((uint8_t)0x68) /* gpio [0:7] */ 00208 #define MFXSTM32L152_REG_ADR_GPIO_PUPD2 ((uint8_t)0x69) /* gpio [8:15] */ 00209 #define MFXSTM32L152_REG_ADR_GPIO_PUPD3 ((uint8_t)0x6A) /* agpio [0:7] */ 00210 /** 00211 * @brief Reg addr: GPIO SET (W): When GPIO is in output mode, write (1) puts the corresponding GPO in High level. 00212 */ 00213 #define MFXSTM32L152_REG_ADR_GPO_SET1 ((uint8_t)0x6C) /* gpio [0:7] */ 00214 #define MFXSTM32L152_REG_ADR_GPO_SET2 ((uint8_t)0x6D) /* gpio [8:15] */ 00215 #define MFXSTM32L152_REG_ADR_GPO_SET3 ((uint8_t)0x6E) /* agpio [0:7] */ 00216 /** 00217 * @brief Reg addr: GPIO CLEAR (W): When GPIO is in output mode, write (1) puts the corresponding GPO in Low level. 00218 */ 00219 #define MFXSTM32L152_REG_ADR_GPO_CLR1 ((uint8_t)0x70) /* gpio [0:7] */ 00220 #define MFXSTM32L152_REG_ADR_GPO_CLR2 ((uint8_t)0x71) /* gpio [8:15] */ 00221 #define MFXSTM32L152_REG_ADR_GPO_CLR3 ((uint8_t)0x72) /* agpio [0:7] */ 00222 /** 00223 * @brief Reg addr: GPIO STATE (R): Give state of the GPIO pin. 00224 */ 00225 #define MFXSTM32L152_REG_ADR_GPIO_STATE1 ((uint8_t)0x10) /* gpio [0:7] */ 00226 #define MFXSTM32L152_REG_ADR_GPIO_STATE2 ((uint8_t)0x11) /* gpio [8:15] */ 00227 #define MFXSTM32L152_REG_ADR_GPIO_STATE3 ((uint8_t)0x12) /* agpio [0:7] */ 00228 00229 /** 00230 * @brief GPIO IRQ_GPIs 00231 */ 00232 /* GPIOs can INDIVIDUALLY generate interruption to the Main MCU thanks to the MFXSTM32L152_IRQ_OUT signal */ 00233 /* the general MFXSTM32L152_IRQ_GPIO_SRC_EN shall be enabled too */ 00234 /** 00235 * @brief GPIO IRQ_GPI_SRC1/2/3 (R/W): registers enable or not the feature to generate irq 00236 */ 00237 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1 ((uint8_t)0x48) /* gpio [0:7] */ 00238 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC2 ((uint8_t)0x49) /* gpio [8:15] */ 00239 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC3 ((uint8_t)0x4A) /* agpio [0:7] */ 00240 /** 00241 * @brief GPIO IRQ_GPI_EVT1/2/3 (R/W): Irq generated on level (0) or edge (1). 00242 */ 00243 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1 ((uint8_t)0x4C) /* gpio [0:7] */ 00244 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT2 ((uint8_t)0x4D) /* gpio [8:15] */ 00245 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT3 ((uint8_t)0x4E) /* agpio [0:7] */ 00246 /** 00247 * @brief GPIO IRQ_GPI_TYPE1/2/3 (R/W): Irq generated on (0) : Low level or Falling edge. (1) : High level or Rising edge. 00248 */ 00249 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1 ((uint8_t)0x50) /* gpio [0:7] */ 00250 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE2 ((uint8_t)0x51) /* gpio [8:15] */ 00251 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE3 ((uint8_t)0x52) /* agpio [0:7] */ 00252 /** 00253 * @brief GPIO IRQ_GPI_PENDING1/2/3 (R): irq occurs 00254 */ 00255 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1 ((uint8_t)0x0C) /* gpio [0:7] */ 00256 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2 ((uint8_t)0x0D) /* gpio [8:15] */ 00257 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3 ((uint8_t)0x0E) /* agpio [0:7] */ 00258 /** 00259 * @brief GPIO IRQ_GPI_ACK1/2/3 (W): Write (1) to acknowledge IRQ event 00260 */ 00261 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1 ((uint8_t)0x54) /* gpio [0:7] */ 00262 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2 ((uint8_t)0x55) /* gpio [8:15] */ 00263 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3 ((uint8_t)0x56) /* agpio [0:7] */ 00264 00265 00266 /** 00267 * @brief GPIO: IO Pins definition 00268 */ 00269 #define MFXSTM32L152_GPIO_PIN_0 ((uint32_t)0x0001) 00270 #define MFXSTM32L152_GPIO_PIN_1 ((uint32_t)0x0002) 00271 #define MFXSTM32L152_GPIO_PIN_2 ((uint32_t)0x0004) 00272 #define MFXSTM32L152_GPIO_PIN_3 ((uint32_t)0x0008) 00273 #define MFXSTM32L152_GPIO_PIN_4 ((uint32_t)0x0010) 00274 #define MFXSTM32L152_GPIO_PIN_5 ((uint32_t)0x0020) 00275 #define MFXSTM32L152_GPIO_PIN_6 ((uint32_t)0x0040) 00276 #define MFXSTM32L152_GPIO_PIN_7 ((uint32_t)0x0080) 00277 00278 #define MFXSTM32L152_GPIO_PIN_8 ((uint32_t)0x0100) 00279 #define MFXSTM32L152_GPIO_PIN_9 ((uint32_t)0x0200) 00280 #define MFXSTM32L152_GPIO_PIN_10 ((uint32_t)0x0400) 00281 #define MFXSTM32L152_GPIO_PIN_11 ((uint32_t)0x0800) 00282 #define MFXSTM32L152_GPIO_PIN_12 ((uint32_t)0x1000) 00283 #define MFXSTM32L152_GPIO_PIN_13 ((uint32_t)0x2000) 00284 #define MFXSTM32L152_GPIO_PIN_14 ((uint32_t)0x4000) 00285 #define MFXSTM32L152_GPIO_PIN_15 ((uint32_t)0x8000) 00286 00287 #define MFXSTM32L152_GPIO_PIN_16 ((uint32_t)0x010000) 00288 #define MFXSTM32L152_GPIO_PIN_17 ((uint32_t)0x020000) 00289 #define MFXSTM32L152_GPIO_PIN_18 ((uint32_t)0x040000) 00290 #define MFXSTM32L152_GPIO_PIN_19 ((uint32_t)0x080000) 00291 #define MFXSTM32L152_GPIO_PIN_20 ((uint32_t)0x100000) 00292 #define MFXSTM32L152_GPIO_PIN_21 ((uint32_t)0x200000) 00293 #define MFXSTM32L152_GPIO_PIN_22 ((uint32_t)0x400000) 00294 #define MFXSTM32L152_GPIO_PIN_23 ((uint32_t)0x800000) 00295 00296 #define MFXSTM32L152_AGPIO_PIN_0 MFXSTM32L152_GPIO_PIN_16 00297 #define MFXSTM32L152_AGPIO_PIN_1 MFXSTM32L152_GPIO_PIN_17 00298 #define MFXSTM32L152_AGPIO_PIN_2 MFXSTM32L152_GPIO_PIN_18 00299 #define MFXSTM32L152_AGPIO_PIN_3 MFXSTM32L152_GPIO_PIN_19 00300 #define MFXSTM32L152_AGPIO_PIN_4 MFXSTM32L152_GPIO_PIN_20 00301 #define MFXSTM32L152_AGPIO_PIN_5 MFXSTM32L152_GPIO_PIN_21 00302 #define MFXSTM32L152_AGPIO_PIN_6 MFXSTM32L152_GPIO_PIN_22 00303 #define MFXSTM32L152_AGPIO_PIN_7 MFXSTM32L152_GPIO_PIN_23 00304 00305 #define MFXSTM32L152_GPIO_PINS_ALL ((uint32_t)0xFFFFFF) 00306 00307 /** 00308 * @brief GPIO: constant 00309 */ 00310 #define MFXSTM32L152_GPIO_DIR_IN ((uint8_t)0x0) 00311 #define MFXSTM32L152_GPIO_DIR_OUT ((uint8_t)0x1) 00312 #define MFXSTM32L152_IRQ_GPI_EVT_LEVEL ((uint8_t)0x0) 00313 #define MFXSTM32L152_IRQ_GPI_EVT_EDGE ((uint8_t)0x1) 00314 #define MFXSTM32L152_IRQ_GPI_TYPE_LLFE ((uint8_t)0x0) /* Low Level Falling Edge */ 00315 #define MFXSTM32L152_IRQ_GPI_TYPE_HLRE ((uint8_t)0x1) /*High Level Raising Edge */ 00316 #define MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR ((uint8_t)0x0) 00317 #define MFXSTM32L152_GPI_WITH_PULL_RESISTOR ((uint8_t)0x1) 00318 #define MFXSTM32L152_GPO_PUSH_PULL ((uint8_t)0x0) 00319 #define MFXSTM32L152_GPO_OPEN_DRAIN ((uint8_t)0x1) 00320 #define MFXSTM32L152_GPIO_PULL_DOWN ((uint8_t)0x0) 00321 #define MFXSTM32L152_GPIO_PULL_UP ((uint8_t)0x1) 00322 00323 00324 /** 00325 * @brief TOUCH SCREEN Registers 00326 */ 00327 00328 /** 00329 * @brief Touch Screen Registers 00330 */ 00331 #define MFXSTM32L152_TS_SETTLING ((uint8_t)0xA0) 00332 #define MFXSTM32L152_TS_TOUCH_DET_DELAY ((uint8_t)0xA1) 00333 #define MFXSTM32L152_TS_AVE ((uint8_t)0xA2) 00334 #define MFXSTM32L152_TS_TRACK ((uint8_t)0xA3) 00335 #define MFXSTM32L152_TS_FIFO_TH ((uint8_t)0xA4) 00336 #define MFXSTM32L152_TS_FIFO_STA ((uint8_t)0x20) 00337 #define MFXSTM32L152_TS_FIFO_LEVEL ((uint8_t)0x21) 00338 #define MFXSTM32L152_TS_XY_DATA ((uint8_t)0x24) 00339 00340 /** 00341 * @brief TS registers masks 00342 */ 00343 #define MFXSTM32L152_TS_CTRL_STATUS ((uint8_t)0x08) 00344 #define MFXSTM32L152_TS_CLEAR_FIFO ((uint8_t)0x80) 00345 00346 00347 /** 00348 * @brief Register address: Idd control register (R/W) 00349 */ 00350 #define MFXSTM32L152_REG_ADR_IDD_CTRL ((uint8_t)0x80) 00351 00352 /** 00353 * @brief Register address: Idd pre delay register (R/W) 00354 */ 00355 #define MFXSTM32L152_REG_ADR_IDD_PRE_DELAY ((uint8_t)0x81) 00356 00357 /** 00358 * @brief Register address: Idd Shunt registers (R/W) 00359 */ 00360 #define MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB ((uint8_t)0x82) 00361 #define MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB ((uint8_t)0x83) 00362 #define MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB ((uint8_t)0x84) 00363 #define MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB ((uint8_t)0x85) 00364 #define MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB ((uint8_t)0x86) 00365 #define MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB ((uint8_t)0x87) 00366 #define MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB ((uint8_t)0x88) 00367 #define MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB ((uint8_t)0x89) 00368 #define MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB ((uint8_t)0x8A) 00369 #define MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB ((uint8_t)0x8B) 00370 00371 /** 00372 * @brief Register address: Idd ampli gain register (R/W) 00373 */ 00374 #define MFXSTM32L152_REG_ADR_IDD_GAIN_MSB ((uint8_t)0x8C) 00375 #define MFXSTM32L152_REG_ADR_IDD_GAIN_LSB ((uint8_t)0x8D) 00376 00377 /** 00378 * @brief Register address: Idd VDD min register (R/W) 00379 */ 00380 #define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB ((uint8_t)0x8E) 00381 #define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB ((uint8_t)0x8F) 00382 00383 /** 00384 * @brief Register address: Idd value register (R) 00385 */ 00386 #define MFXSTM32L152_REG_ADR_IDD_VALUE_MSB ((uint8_t)0x14) 00387 #define MFXSTM32L152_REG_ADR_IDD_VALUE_MID ((uint8_t)0x15) 00388 #define MFXSTM32L152_REG_ADR_IDD_VALUE_LSB ((uint8_t)0x16) 00389 00390 /** 00391 * @brief Register address: Idd calibration offset register (R) 00392 */ 00393 #define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_MSB ((uint8_t)0x18) 00394 #define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_LSB ((uint8_t)0x19) 00395 00396 /** 00397 * @brief Register address: Idd shunt used offset register (R) 00398 */ 00399 #define MFXSTM32L152_REG_ADR_IDD_SHUNT_USED ((uint8_t)0x1A) 00400 00401 /** 00402 * @brief Register address: shunt stabilisation delay registers (R/W) 00403 */ 00404 #define MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION ((uint8_t)0x90) 00405 #define MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION ((uint8_t)0x91) 00406 #define MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION ((uint8_t)0x92) 00407 #define MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION ((uint8_t)0x93) 00408 #define MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION ((uint8_t)0x94) 00409 00410 /** 00411 * @brief Register address: Idd number of measurements register (R/W) 00412 */ 00413 #define MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS ((uint8_t)0x96) 00414 00415 /** 00416 * @brief Register address: Idd delta delay between 2 measurements register (R/W) 00417 */ 00418 #define MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY ((uint8_t)0x97) 00419 00420 /** 00421 * @brief Register address: Idd number of shunt on board register (R/W) 00422 */ 00423 #define MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD ((uint8_t)0x98) 00424 00425 00426 00427 /** @defgroup IDD_Control_Register_Defines IDD Control Register Defines 00428 * @{ 00429 */ 00430 /** 00431 * @brief IDD control register masks 00432 */ 00433 #define MFXSTM32L152_IDD_CTRL_REQ ((uint8_t)0x01) 00434 #define MFXSTM32L152_IDD_CTRL_SHUNT_NB ((uint8_t)0x0E) 00435 #define MFXSTM32L152_IDD_CTRL_VREF_DIS ((uint8_t)0x40) 00436 #define MFXSTM32L152_IDD_CTRL_CAL_DIS ((uint8_t)0x80) 00437 00438 /** 00439 * @brief IDD Shunt Number 00440 */ 00441 #define MFXSTM32L152_IDD_SHUNT_NB_1 ((uint8_t) 0x01) 00442 #define MFXSTM32L152_IDD_SHUNT_NB_2 ((uint8_t) 0x02) 00443 #define MFXSTM32L152_IDD_SHUNT_NB_3 ((uint8_t) 0x03) 00444 #define MFXSTM32L152_IDD_SHUNT_NB_4 ((uint8_t) 0x04) 00445 #define MFXSTM32L152_IDD_SHUNT_NB_5 ((uint8_t) 0x05) 00446 00447 /** 00448 * @brief Vref Measurement 00449 */ 00450 #define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_ENABLE ((uint8_t) 0x00) 00451 #define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_DISABLE ((uint8_t) 0x70) 00452 00453 /** 00454 * @brief IDD Calibration 00455 */ 00456 #define MFXSTM32L152_IDD_AUTO_CALIBRATION_ENABLE ((uint8_t) 0x00) 00457 #define MFXSTM32L152_IDD_AUTO_CALIBRATION_DISABLE ((uint8_t) 0x80) 00458 /** 00459 * @} 00460 */ 00461 00462 /** @defgroup IDD_PreDelay_Defines IDD PreDelay Defines 00463 * @{ 00464 */ 00465 /** 00466 * @brief IDD PreDelay masks 00467 */ 00468 #define MFXSTM32L152_IDD_PREDELAY_UNIT ((uint8_t) 0x80) 00469 #define MFXSTM32L152_IDD_PREDELAY_VALUE ((uint8_t) 0x7F) 00470 00471 00472 /** 00473 * @brief IDD PreDelay unit 00474 */ 00475 #define MFXSTM32L152_IDD_PREDELAY_0_5_MS ((uint8_t) 0x00) 00476 #define MFXSTM32L152_IDD_PREDELAY_20_MS ((uint8_t) 0x80) 00477 /** 00478 * @} 00479 */ 00480 00481 /** @defgroup IDD_DeltaDelay_Defines IDD Delta DElay Defines 00482 * @{ 00483 */ 00484 /** 00485 * @brief IDD Delta Delay masks 00486 */ 00487 #define MFXSTM32L152_IDD_DELTADELAY_UNIT ((uint8_t) 0x80) 00488 #define MFXSTM32L152_IDD_DELTADELAY_VALUE ((uint8_t) 0x7F) 00489 00490 00491 /** 00492 * @brief IDD Delta Delay unit 00493 */ 00494 #define MFXSTM32L152_IDD_DELTADELAY_0_5_MS ((uint8_t) 0x00) 00495 #define MFXSTM32L152_IDD_DELTADELAY_20_MS ((uint8_t) 0x80) 00496 00497 00498 /** 00499 * @} 00500 */ 00501 00502 /** 00503 * @} 00504 */ 00505 00506 00507 /* Exported macro ------------------------------------------------------------*/ 00508 00509 /** @defgroup MFXSTM32L152_Exported_Macros 00510 * @{ 00511 */ 00512 00513 /** 00514 * @} 00515 */ 00516 00517 /* Exported functions --------------------------------------------------------*/ 00518 00519 /** @defgroup MFXSTM32L152_Exported_Functions 00520 * @{ 00521 */ 00522 00523 /** 00524 * @brief MFXSTM32L152 Control functions 00525 */ 00526 void mfxstm32l152_Init(uint16_t DeviceAddr); 00527 void mfxstm32l152_DeInit(uint16_t DeviceAddr); 00528 void mfxstm32l152_Reset(uint16_t DeviceAddr); 00529 uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr); 00530 uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr); 00531 void mfxstm32l152_LowPower(uint16_t DeviceAddr); 00532 void mfxstm32l152_WakeUp(uint16_t DeviceAddr); 00533 00534 void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source); 00535 void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source); 00536 uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source); 00537 void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source); 00538 00539 void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity); 00540 void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type); 00541 00542 00543 /** 00544 * @brief MFXSTM32L152 IO functionalities functions 00545 */ 00546 void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin); 00547 uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode); 00548 void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState); 00549 uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin); 00550 void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr); 00551 void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr); 00552 uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin); 00553 void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin); 00554 00555 void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction); 00556 void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr); 00557 void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr); 00558 void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type); 00559 void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt); 00560 void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin); 00561 void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin); 00562 00563 /** 00564 * @brief MFXSTM32L152 Touch screen functionalities functions 00565 */ 00566 void mfxstm32l152_TS_Start(uint16_t DeviceAddr); 00567 uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr); 00568 void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y); 00569 void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr); 00570 void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr); 00571 uint8_t mfxstm32l152_TS_ITStatus (uint16_t DeviceAddr); 00572 void mfxstm32l152_TS_ClearIT (uint16_t DeviceAddr); 00573 00574 /** 00575 * @brief MFXSTM32L152 IDD current measurement functionalities functions 00576 */ 00577 void mfxstm32l152_IDD_Start(uint16_t DeviceAddr); 00578 void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig); 00579 void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit); 00580 void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue); 00581 uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr); 00582 void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr); 00583 void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr); 00584 uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr); 00585 void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr); 00586 00587 /** 00588 * @brief MFXSTM32L152 Error management functions 00589 */ 00590 uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr); 00591 uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr); 00592 void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr); 00593 void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr); 00594 uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr); 00595 void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr); 00596 00597 uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr); 00598 void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value); 00599 00600 00601 00602 /** 00603 * @brief iobus prototypes (they should be defined in common/stm32_iobus.h) 00604 */ 00605 void MFX_IO_Init(void); 00606 void MFX_IO_DeInit(void); 00607 void MFX_IO_ITConfig (void); 00608 void MFX_IO_EnableWakeupPin(void); 00609 void MFX_IO_Wakeup(void); 00610 void MFX_IO_Delay(uint32_t delay); 00611 void MFX_IO_Write(uint16_t addr, uint8_t reg, uint8_t value); 00612 uint8_t MFX_IO_Read(uint16_t addr, uint8_t reg); 00613 uint16_t MFX_IO_ReadMultiple(uint16_t addr, uint8_t reg, uint8_t *buffer, uint16_t length); 00614 00615 /** 00616 * @} 00617 */ 00618 00619 /* Touch screen driver structure */ 00620 extern TS_DrvTypeDef mfxstm32l152_ts_drv; 00621 00622 /* IO driver structure */ 00623 extern IO_DrvTypeDef mfxstm32l152_io_drv; 00624 00625 /* IDD driver structure */ 00626 extern IDD_DrvTypeDef mfxstm32l152_idd_drv; 00627 00628 00629 #ifdef __cplusplus 00630 } 00631 #endif 00632 #endif /* __MFXSTM32L152_H */ 00633 00634 00635 /** 00636 * @} 00637 */ 00638 00639 /** 00640 * @} 00641 */ 00642 00643 /** 00644 * @} 00645 */ 00646 00647 /** 00648 * @} 00649 */ 00650 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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