Rename library

Dependencies:   X_NUCLEO_COMMON ST_INTERFACES

Dependents:   VL53L3CX_NoShield_1Sensor_poll_Mb06x VL53L3_NoShield_1Sensor_polling_Mb63 X_NUCLEO_53L3A2 53L3A2_Ranging

Committer:
Charles MacNeill
Date:
Wed Jul 14 12:45:49 2021 +0100
Revision:
5:89031b2f5316
The class files now just are wrappers for the files in the "MODULES" directory.The porting directory includes the mbed interface

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Charles MacNeill 5:89031b2f5316 1
Charles MacNeill 5:89031b2f5316 2 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
Charles MacNeill 5:89031b2f5316 3 /******************************************************************************
Charles MacNeill 5:89031b2f5316 4 * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
Charles MacNeill 5:89031b2f5316 5
Charles MacNeill 5:89031b2f5316 6 This file is part of VL53LX and is dual licensed,
Charles MacNeill 5:89031b2f5316 7 either GPL-2.0+
Charles MacNeill 5:89031b2f5316 8 or 'BSD 3-clause "New" or "Revised" License' , at your option.
Charles MacNeill 5:89031b2f5316 9 ******************************************************************************
Charles MacNeill 5:89031b2f5316 10 */
Charles MacNeill 5:89031b2f5316 11
Charles MacNeill 5:89031b2f5316 12
Charles MacNeill 5:89031b2f5316 13 #ifndef _VL53LX_REGISTER_STRUCTS_H_
Charles MacNeill 5:89031b2f5316 14 #define _VL53LX_REGISTER_STRUCTS_H_
Charles MacNeill 5:89031b2f5316 15
Charles MacNeill 5:89031b2f5316 16 #include "vl53lx_types.h"
Charles MacNeill 5:89031b2f5316 17 #include "vl53lx_register_map.h"
Charles MacNeill 5:89031b2f5316 18
Charles MacNeill 5:89031b2f5316 19 #define VL53LX_STATIC_NVM_MANAGED_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 20 VL53LX_I2C_SLAVE__DEVICE_ADDRESS
Charles MacNeill 5:89031b2f5316 21 #define VL53LX_CUSTOMER_NVM_MANAGED_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 22 VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_0
Charles MacNeill 5:89031b2f5316 23 #define VL53LX_STATIC_CONFIG_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 24 VL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS
Charles MacNeill 5:89031b2f5316 25 #define VL53LX_GENERAL_CONFIG_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 26 VL53LX_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE
Charles MacNeill 5:89031b2f5316 27 #define VL53LX_TIMING_CONFIG_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 28 VL53LX_MM_CONFIG__TIMEOUT_MACROP_A_HI
Charles MacNeill 5:89031b2f5316 29 #define VL53LX_DYNAMIC_CONFIG_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 30 VL53LX_SYSTEM__GROUPED_PARAMETER_HOLD_0
Charles MacNeill 5:89031b2f5316 31 #define VL53LX_SYSTEM_CONTROL_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 32 VL53LX_POWER_MANAGEMENT__GO1_POWER_FORCE
Charles MacNeill 5:89031b2f5316 33 #define VL53LX_SYSTEM_RESULTS_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 34 VL53LX_RESULT__INTERRUPT_STATUS
Charles MacNeill 5:89031b2f5316 35 #define VL53LX_CORE_RESULTS_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 36 VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
Charles MacNeill 5:89031b2f5316 37 #define VL53LX_DEBUG_RESULTS_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 38 VL53LX_PHASECAL_RESULT__REFERENCE_PHASE
Charles MacNeill 5:89031b2f5316 39 #define VL53LX_NVM_COPY_DATA_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 40 VL53LX_IDENTIFICATION__MODEL_ID
Charles MacNeill 5:89031b2f5316 41 #define VL53LX_PREV_SHADOW_SYSTEM_RESULTS_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 42 VL53LX_PREV_SHADOW_RESULT__INTERRUPT_STATUS
Charles MacNeill 5:89031b2f5316 43 #define VL53LX_PREV_SHADOW_CORE_RESULTS_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 44 VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
Charles MacNeill 5:89031b2f5316 45 #define VL53LX_PATCH_DEBUG_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 46 VL53LX_RESULT__DEBUG_STATUS
Charles MacNeill 5:89031b2f5316 47 #define VL53LX_GPH_GENERAL_CONFIG_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 48 VL53LX_GPH__SYSTEM__THRESH_RATE_HIGH
Charles MacNeill 5:89031b2f5316 49 #define VL53LX_GPH_STATIC_CONFIG_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 50 VL53LX_GPH__DSS_CONFIG__ROI_MODE_CONTROL
Charles MacNeill 5:89031b2f5316 51 #define VL53LX_GPH_TIMING_CONFIG_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 52 VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI
Charles MacNeill 5:89031b2f5316 53 #define VL53LX_FW_INTERNAL_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 54 VL53LX_FIRMWARE__INTERNAL_STREAM_COUNT_DIV
Charles MacNeill 5:89031b2f5316 55 #define VL53LX_PATCH_RESULTS_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 56 VL53LX_DSS_CALC__ROI_CTRL
Charles MacNeill 5:89031b2f5316 57 #define VL53LX_SHADOW_SYSTEM_RESULTS_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 58 VL53LX_SHADOW_PHASECAL_RESULT__VCSEL_START
Charles MacNeill 5:89031b2f5316 59 #define VL53LX_SHADOW_CORE_RESULTS_I2C_INDEX \
Charles MacNeill 5:89031b2f5316 60 VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
Charles MacNeill 5:89031b2f5316 61
Charles MacNeill 5:89031b2f5316 62 #define VL53LX_STATIC_NVM_MANAGED_I2C_SIZE_BYTES 11
Charles MacNeill 5:89031b2f5316 63 #define VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES 23
Charles MacNeill 5:89031b2f5316 64 #define VL53LX_STATIC_CONFIG_I2C_SIZE_BYTES 32
Charles MacNeill 5:89031b2f5316 65 #define VL53LX_GENERAL_CONFIG_I2C_SIZE_BYTES 22
Charles MacNeill 5:89031b2f5316 66 #define VL53LX_TIMING_CONFIG_I2C_SIZE_BYTES 23
Charles MacNeill 5:89031b2f5316 67 #define VL53LX_DYNAMIC_CONFIG_I2C_SIZE_BYTES 18
Charles MacNeill 5:89031b2f5316 68 #define VL53LX_SYSTEM_CONTROL_I2C_SIZE_BYTES 5
Charles MacNeill 5:89031b2f5316 69 #define VL53LX_SYSTEM_RESULTS_I2C_SIZE_BYTES 44
Charles MacNeill 5:89031b2f5316 70 #define VL53LX_CORE_RESULTS_I2C_SIZE_BYTES 33
Charles MacNeill 5:89031b2f5316 71 #define VL53LX_DEBUG_RESULTS_I2C_SIZE_BYTES 56
Charles MacNeill 5:89031b2f5316 72 #define VL53LX_NVM_COPY_DATA_I2C_SIZE_BYTES 49
Charles MacNeill 5:89031b2f5316 73 #define VL53LX_PREV_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 44
Charles MacNeill 5:89031b2f5316 74 #define VL53LX_PREV_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33
Charles MacNeill 5:89031b2f5316 75 #define VL53LX_PATCH_DEBUG_I2C_SIZE_BYTES 2
Charles MacNeill 5:89031b2f5316 76 #define VL53LX_GPH_GENERAL_CONFIG_I2C_SIZE_BYTES 5
Charles MacNeill 5:89031b2f5316 77 #define VL53LX_GPH_STATIC_CONFIG_I2C_SIZE_BYTES 6
Charles MacNeill 5:89031b2f5316 78 #define VL53LX_GPH_TIMING_CONFIG_I2C_SIZE_BYTES 16
Charles MacNeill 5:89031b2f5316 79 #define VL53LX_FW_INTERNAL_I2C_SIZE_BYTES 2
Charles MacNeill 5:89031b2f5316 80 #define VL53LX_PATCH_RESULTS_I2C_SIZE_BYTES 90
Charles MacNeill 5:89031b2f5316 81 #define VL53LX_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 82
Charles MacNeill 5:89031b2f5316 82 #define VL53LX_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33
Charles MacNeill 5:89031b2f5316 83
Charles MacNeill 5:89031b2f5316 84
Charles MacNeill 5:89031b2f5316 85
Charles MacNeill 5:89031b2f5316 86
Charles MacNeill 5:89031b2f5316 87 typedef struct {
Charles MacNeill 5:89031b2f5316 88 uint8_t i2c_slave__device_address;
Charles MacNeill 5:89031b2f5316 89
Charles MacNeill 5:89031b2f5316 90 uint8_t ana_config__vhv_ref_sel_vddpix;
Charles MacNeill 5:89031b2f5316 91
Charles MacNeill 5:89031b2f5316 92 uint8_t ana_config__vhv_ref_sel_vquench;
Charles MacNeill 5:89031b2f5316 93
Charles MacNeill 5:89031b2f5316 94 uint8_t ana_config__reg_avdd1v2_sel;
Charles MacNeill 5:89031b2f5316 95
Charles MacNeill 5:89031b2f5316 96 uint8_t ana_config__fast_osc__trim;
Charles MacNeill 5:89031b2f5316 97
Charles MacNeill 5:89031b2f5316 98 uint16_t osc_measured__fast_osc__frequency;
Charles MacNeill 5:89031b2f5316 99
Charles MacNeill 5:89031b2f5316 100 uint8_t vhv_config__timeout_macrop_loop_bound;
Charles MacNeill 5:89031b2f5316 101
Charles MacNeill 5:89031b2f5316 102 uint8_t vhv_config__count_thresh;
Charles MacNeill 5:89031b2f5316 103
Charles MacNeill 5:89031b2f5316 104 uint8_t vhv_config__offset;
Charles MacNeill 5:89031b2f5316 105
Charles MacNeill 5:89031b2f5316 106 uint8_t vhv_config__init;
Charles MacNeill 5:89031b2f5316 107
Charles MacNeill 5:89031b2f5316 108 } VL53LX_static_nvm_managed_t;
Charles MacNeill 5:89031b2f5316 109
Charles MacNeill 5:89031b2f5316 110
Charles MacNeill 5:89031b2f5316 111
Charles MacNeill 5:89031b2f5316 112
Charles MacNeill 5:89031b2f5316 113 typedef struct {
Charles MacNeill 5:89031b2f5316 114 uint8_t global_config__spad_enables_ref_0;
Charles MacNeill 5:89031b2f5316 115
Charles MacNeill 5:89031b2f5316 116 uint8_t global_config__spad_enables_ref_1;
Charles MacNeill 5:89031b2f5316 117
Charles MacNeill 5:89031b2f5316 118 uint8_t global_config__spad_enables_ref_2;
Charles MacNeill 5:89031b2f5316 119
Charles MacNeill 5:89031b2f5316 120 uint8_t global_config__spad_enables_ref_3;
Charles MacNeill 5:89031b2f5316 121
Charles MacNeill 5:89031b2f5316 122 uint8_t global_config__spad_enables_ref_4;
Charles MacNeill 5:89031b2f5316 123
Charles MacNeill 5:89031b2f5316 124 uint8_t global_config__spad_enables_ref_5;
Charles MacNeill 5:89031b2f5316 125
Charles MacNeill 5:89031b2f5316 126 uint8_t global_config__ref_en_start_select;
Charles MacNeill 5:89031b2f5316 127
Charles MacNeill 5:89031b2f5316 128 uint8_t ref_spad_man__num_requested_ref_spads;
Charles MacNeill 5:89031b2f5316 129
Charles MacNeill 5:89031b2f5316 130 uint8_t ref_spad_man__ref_location;
Charles MacNeill 5:89031b2f5316 131
Charles MacNeill 5:89031b2f5316 132 uint16_t algo__crosstalk_compensation_plane_offset_kcps;
Charles MacNeill 5:89031b2f5316 133
Charles MacNeill 5:89031b2f5316 134 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
Charles MacNeill 5:89031b2f5316 135
Charles MacNeill 5:89031b2f5316 136 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
Charles MacNeill 5:89031b2f5316 137
Charles MacNeill 5:89031b2f5316 138 uint16_t ref_spad_char__total_rate_target_mcps;
Charles MacNeill 5:89031b2f5316 139
Charles MacNeill 5:89031b2f5316 140 int16_t algo__part_to_part_range_offset_mm;
Charles MacNeill 5:89031b2f5316 141
Charles MacNeill 5:89031b2f5316 142 int16_t mm_config__inner_offset_mm;
Charles MacNeill 5:89031b2f5316 143
Charles MacNeill 5:89031b2f5316 144 int16_t mm_config__outer_offset_mm;
Charles MacNeill 5:89031b2f5316 145
Charles MacNeill 5:89031b2f5316 146 } VL53LX_customer_nvm_managed_t;
Charles MacNeill 5:89031b2f5316 147
Charles MacNeill 5:89031b2f5316 148
Charles MacNeill 5:89031b2f5316 149
Charles MacNeill 5:89031b2f5316 150
Charles MacNeill 5:89031b2f5316 151 typedef struct {
Charles MacNeill 5:89031b2f5316 152 uint16_t dss_config__target_total_rate_mcps;
Charles MacNeill 5:89031b2f5316 153
Charles MacNeill 5:89031b2f5316 154 uint8_t debug__ctrl;
Charles MacNeill 5:89031b2f5316 155
Charles MacNeill 5:89031b2f5316 156 uint8_t test_mode__ctrl;
Charles MacNeill 5:89031b2f5316 157
Charles MacNeill 5:89031b2f5316 158 uint8_t clk_gating__ctrl;
Charles MacNeill 5:89031b2f5316 159
Charles MacNeill 5:89031b2f5316 160 uint8_t nvm_bist__ctrl;
Charles MacNeill 5:89031b2f5316 161
Charles MacNeill 5:89031b2f5316 162 uint8_t nvm_bist__num_nvm_words;
Charles MacNeill 5:89031b2f5316 163
Charles MacNeill 5:89031b2f5316 164 uint8_t nvm_bist__start_address;
Charles MacNeill 5:89031b2f5316 165
Charles MacNeill 5:89031b2f5316 166 uint8_t host_if__status;
Charles MacNeill 5:89031b2f5316 167
Charles MacNeill 5:89031b2f5316 168 uint8_t pad_i2c_hv__config;
Charles MacNeill 5:89031b2f5316 169
Charles MacNeill 5:89031b2f5316 170 uint8_t pad_i2c_hv__extsup_config;
Charles MacNeill 5:89031b2f5316 171
Charles MacNeill 5:89031b2f5316 172 uint8_t gpio_hv_pad__ctrl;
Charles MacNeill 5:89031b2f5316 173
Charles MacNeill 5:89031b2f5316 174 uint8_t gpio_hv_mux__ctrl;
Charles MacNeill 5:89031b2f5316 175
Charles MacNeill 5:89031b2f5316 176 uint8_t gpio__tio_hv_status;
Charles MacNeill 5:89031b2f5316 177
Charles MacNeill 5:89031b2f5316 178 uint8_t gpio__fio_hv_status;
Charles MacNeill 5:89031b2f5316 179
Charles MacNeill 5:89031b2f5316 180 uint8_t ana_config__spad_sel_pswidth;
Charles MacNeill 5:89031b2f5316 181
Charles MacNeill 5:89031b2f5316 182 uint8_t ana_config__vcsel_pulse_width_offset;
Charles MacNeill 5:89031b2f5316 183
Charles MacNeill 5:89031b2f5316 184 uint8_t ana_config__fast_osc__config_ctrl;
Charles MacNeill 5:89031b2f5316 185
Charles MacNeill 5:89031b2f5316 186 uint8_t sigma_estimator__effective_pulse_width_ns;
Charles MacNeill 5:89031b2f5316 187
Charles MacNeill 5:89031b2f5316 188 uint8_t sigma_estimator__effective_ambient_width_ns;
Charles MacNeill 5:89031b2f5316 189
Charles MacNeill 5:89031b2f5316 190 uint8_t sigma_estimator__sigma_ref_mm;
Charles MacNeill 5:89031b2f5316 191
Charles MacNeill 5:89031b2f5316 192 uint8_t algo__crosstalk_compensation_valid_height_mm;
Charles MacNeill 5:89031b2f5316 193
Charles MacNeill 5:89031b2f5316 194 uint8_t spare_host_config__static_config_spare_0;
Charles MacNeill 5:89031b2f5316 195
Charles MacNeill 5:89031b2f5316 196 uint8_t spare_host_config__static_config_spare_1;
Charles MacNeill 5:89031b2f5316 197
Charles MacNeill 5:89031b2f5316 198 uint16_t algo__range_ignore_threshold_mcps;
Charles MacNeill 5:89031b2f5316 199
Charles MacNeill 5:89031b2f5316 200 uint8_t algo__range_ignore_valid_height_mm;
Charles MacNeill 5:89031b2f5316 201
Charles MacNeill 5:89031b2f5316 202 uint8_t algo__range_min_clip;
Charles MacNeill 5:89031b2f5316 203
Charles MacNeill 5:89031b2f5316 204 uint8_t algo__consistency_check__tolerance;
Charles MacNeill 5:89031b2f5316 205
Charles MacNeill 5:89031b2f5316 206 uint8_t spare_host_config__static_config_spare_2;
Charles MacNeill 5:89031b2f5316 207
Charles MacNeill 5:89031b2f5316 208 uint8_t sd_config__reset_stages_msb;
Charles MacNeill 5:89031b2f5316 209
Charles MacNeill 5:89031b2f5316 210 uint8_t sd_config__reset_stages_lsb;
Charles MacNeill 5:89031b2f5316 211
Charles MacNeill 5:89031b2f5316 212 } VL53LX_static_config_t;
Charles MacNeill 5:89031b2f5316 213
Charles MacNeill 5:89031b2f5316 214
Charles MacNeill 5:89031b2f5316 215
Charles MacNeill 5:89031b2f5316 216
Charles MacNeill 5:89031b2f5316 217 typedef struct {
Charles MacNeill 5:89031b2f5316 218 uint8_t gph_config__stream_count_update_value;
Charles MacNeill 5:89031b2f5316 219
Charles MacNeill 5:89031b2f5316 220 uint8_t global_config__stream_divider;
Charles MacNeill 5:89031b2f5316 221
Charles MacNeill 5:89031b2f5316 222 uint8_t system__interrupt_config_gpio;
Charles MacNeill 5:89031b2f5316 223
Charles MacNeill 5:89031b2f5316 224 uint8_t cal_config__vcsel_start;
Charles MacNeill 5:89031b2f5316 225
Charles MacNeill 5:89031b2f5316 226 uint16_t cal_config__repeat_rate;
Charles MacNeill 5:89031b2f5316 227
Charles MacNeill 5:89031b2f5316 228 uint8_t global_config__vcsel_width;
Charles MacNeill 5:89031b2f5316 229
Charles MacNeill 5:89031b2f5316 230 uint8_t phasecal_config__timeout_macrop;
Charles MacNeill 5:89031b2f5316 231
Charles MacNeill 5:89031b2f5316 232 uint8_t phasecal_config__target;
Charles MacNeill 5:89031b2f5316 233
Charles MacNeill 5:89031b2f5316 234 uint8_t phasecal_config__override;
Charles MacNeill 5:89031b2f5316 235
Charles MacNeill 5:89031b2f5316 236 uint8_t dss_config__roi_mode_control;
Charles MacNeill 5:89031b2f5316 237
Charles MacNeill 5:89031b2f5316 238 uint16_t system__thresh_rate_high;
Charles MacNeill 5:89031b2f5316 239
Charles MacNeill 5:89031b2f5316 240 uint16_t system__thresh_rate_low;
Charles MacNeill 5:89031b2f5316 241
Charles MacNeill 5:89031b2f5316 242 uint16_t dss_config__manual_effective_spads_select;
Charles MacNeill 5:89031b2f5316 243
Charles MacNeill 5:89031b2f5316 244 uint8_t dss_config__manual_block_select;
Charles MacNeill 5:89031b2f5316 245
Charles MacNeill 5:89031b2f5316 246 uint8_t dss_config__aperture_attenuation;
Charles MacNeill 5:89031b2f5316 247
Charles MacNeill 5:89031b2f5316 248 uint8_t dss_config__max_spads_limit;
Charles MacNeill 5:89031b2f5316 249
Charles MacNeill 5:89031b2f5316 250 uint8_t dss_config__min_spads_limit;
Charles MacNeill 5:89031b2f5316 251
Charles MacNeill 5:89031b2f5316 252 } VL53LX_general_config_t;
Charles MacNeill 5:89031b2f5316 253
Charles MacNeill 5:89031b2f5316 254
Charles MacNeill 5:89031b2f5316 255
Charles MacNeill 5:89031b2f5316 256
Charles MacNeill 5:89031b2f5316 257 typedef struct {
Charles MacNeill 5:89031b2f5316 258 uint8_t mm_config__timeout_macrop_a_hi;
Charles MacNeill 5:89031b2f5316 259
Charles MacNeill 5:89031b2f5316 260 uint8_t mm_config__timeout_macrop_a_lo;
Charles MacNeill 5:89031b2f5316 261
Charles MacNeill 5:89031b2f5316 262 uint8_t mm_config__timeout_macrop_b_hi;
Charles MacNeill 5:89031b2f5316 263
Charles MacNeill 5:89031b2f5316 264 uint8_t mm_config__timeout_macrop_b_lo;
Charles MacNeill 5:89031b2f5316 265
Charles MacNeill 5:89031b2f5316 266 uint8_t range_config__timeout_macrop_a_hi;
Charles MacNeill 5:89031b2f5316 267
Charles MacNeill 5:89031b2f5316 268 uint8_t range_config__timeout_macrop_a_lo;
Charles MacNeill 5:89031b2f5316 269
Charles MacNeill 5:89031b2f5316 270 uint8_t range_config__vcsel_period_a;
Charles MacNeill 5:89031b2f5316 271
Charles MacNeill 5:89031b2f5316 272 uint8_t range_config__timeout_macrop_b_hi;
Charles MacNeill 5:89031b2f5316 273
Charles MacNeill 5:89031b2f5316 274 uint8_t range_config__timeout_macrop_b_lo;
Charles MacNeill 5:89031b2f5316 275
Charles MacNeill 5:89031b2f5316 276 uint8_t range_config__vcsel_period_b;
Charles MacNeill 5:89031b2f5316 277
Charles MacNeill 5:89031b2f5316 278 uint16_t range_config__sigma_thresh;
Charles MacNeill 5:89031b2f5316 279
Charles MacNeill 5:89031b2f5316 280 uint16_t range_config__min_count_rate_rtn_limit_mcps;
Charles MacNeill 5:89031b2f5316 281
Charles MacNeill 5:89031b2f5316 282 uint8_t range_config__valid_phase_low;
Charles MacNeill 5:89031b2f5316 283
Charles MacNeill 5:89031b2f5316 284 uint8_t range_config__valid_phase_high;
Charles MacNeill 5:89031b2f5316 285
Charles MacNeill 5:89031b2f5316 286 uint32_t system__intermeasurement_period;
Charles MacNeill 5:89031b2f5316 287
Charles MacNeill 5:89031b2f5316 288 uint8_t system__fractional_enable;
Charles MacNeill 5:89031b2f5316 289
Charles MacNeill 5:89031b2f5316 290 } VL53LX_timing_config_t;
Charles MacNeill 5:89031b2f5316 291
Charles MacNeill 5:89031b2f5316 292
Charles MacNeill 5:89031b2f5316 293
Charles MacNeill 5:89031b2f5316 294
Charles MacNeill 5:89031b2f5316 295 typedef struct {
Charles MacNeill 5:89031b2f5316 296 uint8_t system__grouped_parameter_hold_0;
Charles MacNeill 5:89031b2f5316 297
Charles MacNeill 5:89031b2f5316 298 uint16_t system__thresh_high;
Charles MacNeill 5:89031b2f5316 299
Charles MacNeill 5:89031b2f5316 300 uint16_t system__thresh_low;
Charles MacNeill 5:89031b2f5316 301
Charles MacNeill 5:89031b2f5316 302 uint8_t system__enable_xtalk_per_quadrant;
Charles MacNeill 5:89031b2f5316 303
Charles MacNeill 5:89031b2f5316 304 uint8_t system__seed_config;
Charles MacNeill 5:89031b2f5316 305
Charles MacNeill 5:89031b2f5316 306 uint8_t sd_config__woi_sd0;
Charles MacNeill 5:89031b2f5316 307
Charles MacNeill 5:89031b2f5316 308 uint8_t sd_config__woi_sd1;
Charles MacNeill 5:89031b2f5316 309
Charles MacNeill 5:89031b2f5316 310 uint8_t sd_config__initial_phase_sd0;
Charles MacNeill 5:89031b2f5316 311
Charles MacNeill 5:89031b2f5316 312 uint8_t sd_config__initial_phase_sd1;
Charles MacNeill 5:89031b2f5316 313
Charles MacNeill 5:89031b2f5316 314 uint8_t system__grouped_parameter_hold_1;
Charles MacNeill 5:89031b2f5316 315
Charles MacNeill 5:89031b2f5316 316 uint8_t sd_config__first_order_select;
Charles MacNeill 5:89031b2f5316 317
Charles MacNeill 5:89031b2f5316 318 uint8_t sd_config__quantifier;
Charles MacNeill 5:89031b2f5316 319
Charles MacNeill 5:89031b2f5316 320 uint8_t roi_config__user_roi_centre_spad;
Charles MacNeill 5:89031b2f5316 321
Charles MacNeill 5:89031b2f5316 322 uint8_t roi_config__user_roi_requested_global_xy_size;
Charles MacNeill 5:89031b2f5316 323
Charles MacNeill 5:89031b2f5316 324 uint8_t system__sequence_config;
Charles MacNeill 5:89031b2f5316 325
Charles MacNeill 5:89031b2f5316 326 uint8_t system__grouped_parameter_hold;
Charles MacNeill 5:89031b2f5316 327
Charles MacNeill 5:89031b2f5316 328 } VL53LX_dynamic_config_t;
Charles MacNeill 5:89031b2f5316 329
Charles MacNeill 5:89031b2f5316 330
Charles MacNeill 5:89031b2f5316 331
Charles MacNeill 5:89031b2f5316 332
Charles MacNeill 5:89031b2f5316 333 typedef struct {
Charles MacNeill 5:89031b2f5316 334 uint8_t power_management__go1_power_force;
Charles MacNeill 5:89031b2f5316 335
Charles MacNeill 5:89031b2f5316 336 uint8_t system__stream_count_ctrl;
Charles MacNeill 5:89031b2f5316 337
Charles MacNeill 5:89031b2f5316 338 uint8_t firmware__enable;
Charles MacNeill 5:89031b2f5316 339
Charles MacNeill 5:89031b2f5316 340 uint8_t system__interrupt_clear;
Charles MacNeill 5:89031b2f5316 341
Charles MacNeill 5:89031b2f5316 342 uint8_t system__mode_start;
Charles MacNeill 5:89031b2f5316 343
Charles MacNeill 5:89031b2f5316 344 } VL53LX_system_control_t;
Charles MacNeill 5:89031b2f5316 345
Charles MacNeill 5:89031b2f5316 346
Charles MacNeill 5:89031b2f5316 347
Charles MacNeill 5:89031b2f5316 348
Charles MacNeill 5:89031b2f5316 349 typedef struct {
Charles MacNeill 5:89031b2f5316 350 uint8_t result__interrupt_status;
Charles MacNeill 5:89031b2f5316 351
Charles MacNeill 5:89031b2f5316 352 uint8_t result__range_status;
Charles MacNeill 5:89031b2f5316 353
Charles MacNeill 5:89031b2f5316 354 uint8_t result__report_status;
Charles MacNeill 5:89031b2f5316 355
Charles MacNeill 5:89031b2f5316 356 uint8_t result__stream_count;
Charles MacNeill 5:89031b2f5316 357
Charles MacNeill 5:89031b2f5316 358 uint16_t result__dss_actual_effective_spads_sd0;
Charles MacNeill 5:89031b2f5316 359
Charles MacNeill 5:89031b2f5316 360 uint16_t result__peak_signal_count_rate_mcps_sd0;
Charles MacNeill 5:89031b2f5316 361
Charles MacNeill 5:89031b2f5316 362 uint16_t result__ambient_count_rate_mcps_sd0;
Charles MacNeill 5:89031b2f5316 363
Charles MacNeill 5:89031b2f5316 364 uint16_t result__sigma_sd0;
Charles MacNeill 5:89031b2f5316 365
Charles MacNeill 5:89031b2f5316 366 uint16_t result__phase_sd0;
Charles MacNeill 5:89031b2f5316 367
Charles MacNeill 5:89031b2f5316 368 uint16_t result__final_crosstalk_corrected_range_mm_sd0;
Charles MacNeill 5:89031b2f5316 369
Charles MacNeill 5:89031b2f5316 370 uint16_t result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;
Charles MacNeill 5:89031b2f5316 371
Charles MacNeill 5:89031b2f5316 372 uint16_t result__mm_inner_actual_effective_spads_sd0;
Charles MacNeill 5:89031b2f5316 373
Charles MacNeill 5:89031b2f5316 374 uint16_t result__mm_outer_actual_effective_spads_sd0;
Charles MacNeill 5:89031b2f5316 375
Charles MacNeill 5:89031b2f5316 376 uint16_t result__avg_signal_count_rate_mcps_sd0;
Charles MacNeill 5:89031b2f5316 377
Charles MacNeill 5:89031b2f5316 378 uint16_t result__dss_actual_effective_spads_sd1;
Charles MacNeill 5:89031b2f5316 379
Charles MacNeill 5:89031b2f5316 380 uint16_t result__peak_signal_count_rate_mcps_sd1;
Charles MacNeill 5:89031b2f5316 381
Charles MacNeill 5:89031b2f5316 382 uint16_t result__ambient_count_rate_mcps_sd1;
Charles MacNeill 5:89031b2f5316 383
Charles MacNeill 5:89031b2f5316 384 uint16_t result__sigma_sd1;
Charles MacNeill 5:89031b2f5316 385
Charles MacNeill 5:89031b2f5316 386 uint16_t result__phase_sd1;
Charles MacNeill 5:89031b2f5316 387
Charles MacNeill 5:89031b2f5316 388 uint16_t result__final_crosstalk_corrected_range_mm_sd1;
Charles MacNeill 5:89031b2f5316 389
Charles MacNeill 5:89031b2f5316 390 uint16_t result__spare_0_sd1;
Charles MacNeill 5:89031b2f5316 391
Charles MacNeill 5:89031b2f5316 392 uint16_t result__spare_1_sd1;
Charles MacNeill 5:89031b2f5316 393
Charles MacNeill 5:89031b2f5316 394 uint16_t result__spare_2_sd1;
Charles MacNeill 5:89031b2f5316 395
Charles MacNeill 5:89031b2f5316 396 uint8_t result__spare_3_sd1;
Charles MacNeill 5:89031b2f5316 397
Charles MacNeill 5:89031b2f5316 398 uint8_t result__thresh_info;
Charles MacNeill 5:89031b2f5316 399
Charles MacNeill 5:89031b2f5316 400 } VL53LX_system_results_t;
Charles MacNeill 5:89031b2f5316 401
Charles MacNeill 5:89031b2f5316 402
Charles MacNeill 5:89031b2f5316 403
Charles MacNeill 5:89031b2f5316 404
Charles MacNeill 5:89031b2f5316 405 typedef struct {
Charles MacNeill 5:89031b2f5316 406 uint32_t result_core__ambient_window_events_sd0;
Charles MacNeill 5:89031b2f5316 407
Charles MacNeill 5:89031b2f5316 408 uint32_t result_core__ranging_total_events_sd0;
Charles MacNeill 5:89031b2f5316 409
Charles MacNeill 5:89031b2f5316 410 int32_t result_core__signal_total_events_sd0;
Charles MacNeill 5:89031b2f5316 411
Charles MacNeill 5:89031b2f5316 412 uint32_t result_core__total_periods_elapsed_sd0;
Charles MacNeill 5:89031b2f5316 413
Charles MacNeill 5:89031b2f5316 414 uint32_t result_core__ambient_window_events_sd1;
Charles MacNeill 5:89031b2f5316 415
Charles MacNeill 5:89031b2f5316 416 uint32_t result_core__ranging_total_events_sd1;
Charles MacNeill 5:89031b2f5316 417
Charles MacNeill 5:89031b2f5316 418 int32_t result_core__signal_total_events_sd1;
Charles MacNeill 5:89031b2f5316 419
Charles MacNeill 5:89031b2f5316 420 uint32_t result_core__total_periods_elapsed_sd1;
Charles MacNeill 5:89031b2f5316 421
Charles MacNeill 5:89031b2f5316 422 uint8_t result_core__spare_0;
Charles MacNeill 5:89031b2f5316 423
Charles MacNeill 5:89031b2f5316 424 } VL53LX_core_results_t;
Charles MacNeill 5:89031b2f5316 425
Charles MacNeill 5:89031b2f5316 426
Charles MacNeill 5:89031b2f5316 427
Charles MacNeill 5:89031b2f5316 428
Charles MacNeill 5:89031b2f5316 429 typedef struct {
Charles MacNeill 5:89031b2f5316 430 uint16_t phasecal_result__reference_phase;
Charles MacNeill 5:89031b2f5316 431
Charles MacNeill 5:89031b2f5316 432 uint8_t phasecal_result__vcsel_start;
Charles MacNeill 5:89031b2f5316 433
Charles MacNeill 5:89031b2f5316 434 uint8_t ref_spad_char_result__num_actual_ref_spads;
Charles MacNeill 5:89031b2f5316 435
Charles MacNeill 5:89031b2f5316 436 uint8_t ref_spad_char_result__ref_location;
Charles MacNeill 5:89031b2f5316 437
Charles MacNeill 5:89031b2f5316 438 uint8_t vhv_result__coldboot_status;
Charles MacNeill 5:89031b2f5316 439
Charles MacNeill 5:89031b2f5316 440 uint8_t vhv_result__search_result;
Charles MacNeill 5:89031b2f5316 441
Charles MacNeill 5:89031b2f5316 442 uint8_t vhv_result__latest_setting;
Charles MacNeill 5:89031b2f5316 443
Charles MacNeill 5:89031b2f5316 444 uint16_t result__osc_calibrate_val;
Charles MacNeill 5:89031b2f5316 445
Charles MacNeill 5:89031b2f5316 446 uint8_t ana_config__powerdown_go1;
Charles MacNeill 5:89031b2f5316 447
Charles MacNeill 5:89031b2f5316 448 uint8_t ana_config__ref_bg_ctrl;
Charles MacNeill 5:89031b2f5316 449
Charles MacNeill 5:89031b2f5316 450 uint8_t ana_config__regdvdd1v2_ctrl;
Charles MacNeill 5:89031b2f5316 451
Charles MacNeill 5:89031b2f5316 452 uint8_t ana_config__osc_slow_ctrl;
Charles MacNeill 5:89031b2f5316 453
Charles MacNeill 5:89031b2f5316 454 uint8_t test_mode__status;
Charles MacNeill 5:89031b2f5316 455
Charles MacNeill 5:89031b2f5316 456 uint8_t firmware__system_status;
Charles MacNeill 5:89031b2f5316 457
Charles MacNeill 5:89031b2f5316 458 uint8_t firmware__mode_status;
Charles MacNeill 5:89031b2f5316 459
Charles MacNeill 5:89031b2f5316 460 uint8_t firmware__secondary_mode_status;
Charles MacNeill 5:89031b2f5316 461
Charles MacNeill 5:89031b2f5316 462 uint16_t firmware__cal_repeat_rate_counter;
Charles MacNeill 5:89031b2f5316 463
Charles MacNeill 5:89031b2f5316 464 uint16_t gph__system__thresh_high;
Charles MacNeill 5:89031b2f5316 465
Charles MacNeill 5:89031b2f5316 466 uint16_t gph__system__thresh_low;
Charles MacNeill 5:89031b2f5316 467
Charles MacNeill 5:89031b2f5316 468 uint8_t gph__system__enable_xtalk_per_quadrant;
Charles MacNeill 5:89031b2f5316 469
Charles MacNeill 5:89031b2f5316 470 uint8_t gph__spare_0;
Charles MacNeill 5:89031b2f5316 471
Charles MacNeill 5:89031b2f5316 472 uint8_t gph__sd_config__woi_sd0;
Charles MacNeill 5:89031b2f5316 473
Charles MacNeill 5:89031b2f5316 474 uint8_t gph__sd_config__woi_sd1;
Charles MacNeill 5:89031b2f5316 475
Charles MacNeill 5:89031b2f5316 476 uint8_t gph__sd_config__initial_phase_sd0;
Charles MacNeill 5:89031b2f5316 477
Charles MacNeill 5:89031b2f5316 478 uint8_t gph__sd_config__initial_phase_sd1;
Charles MacNeill 5:89031b2f5316 479
Charles MacNeill 5:89031b2f5316 480 uint8_t gph__sd_config__first_order_select;
Charles MacNeill 5:89031b2f5316 481
Charles MacNeill 5:89031b2f5316 482 uint8_t gph__sd_config__quantifier;
Charles MacNeill 5:89031b2f5316 483
Charles MacNeill 5:89031b2f5316 484 uint8_t gph__roi_config__user_roi_centre_spad;
Charles MacNeill 5:89031b2f5316 485
Charles MacNeill 5:89031b2f5316 486 uint8_t gph__roi_config__user_roi_requested_global_xy_size;
Charles MacNeill 5:89031b2f5316 487
Charles MacNeill 5:89031b2f5316 488 uint8_t gph__system__sequence_config;
Charles MacNeill 5:89031b2f5316 489
Charles MacNeill 5:89031b2f5316 490 uint8_t gph__gph_id;
Charles MacNeill 5:89031b2f5316 491
Charles MacNeill 5:89031b2f5316 492 uint8_t system__interrupt_set;
Charles MacNeill 5:89031b2f5316 493
Charles MacNeill 5:89031b2f5316 494 uint8_t interrupt_manager__enables;
Charles MacNeill 5:89031b2f5316 495
Charles MacNeill 5:89031b2f5316 496 uint8_t interrupt_manager__clear;
Charles MacNeill 5:89031b2f5316 497
Charles MacNeill 5:89031b2f5316 498 uint8_t interrupt_manager__status;
Charles MacNeill 5:89031b2f5316 499
Charles MacNeill 5:89031b2f5316 500 uint8_t mcu_to_host_bank__wr_access_en;
Charles MacNeill 5:89031b2f5316 501
Charles MacNeill 5:89031b2f5316 502 uint8_t power_management__go1_reset_status;
Charles MacNeill 5:89031b2f5316 503
Charles MacNeill 5:89031b2f5316 504 uint8_t pad_startup_mode__value_ro;
Charles MacNeill 5:89031b2f5316 505
Charles MacNeill 5:89031b2f5316 506 uint8_t pad_startup_mode__value_ctrl;
Charles MacNeill 5:89031b2f5316 507
Charles MacNeill 5:89031b2f5316 508 uint32_t pll_period_us;
Charles MacNeill 5:89031b2f5316 509
Charles MacNeill 5:89031b2f5316 510 uint32_t interrupt_scheduler__data_out;
Charles MacNeill 5:89031b2f5316 511
Charles MacNeill 5:89031b2f5316 512 uint8_t nvm_bist__complete;
Charles MacNeill 5:89031b2f5316 513
Charles MacNeill 5:89031b2f5316 514 uint8_t nvm_bist__status;
Charles MacNeill 5:89031b2f5316 515
Charles MacNeill 5:89031b2f5316 516 } VL53LX_debug_results_t;
Charles MacNeill 5:89031b2f5316 517
Charles MacNeill 5:89031b2f5316 518
Charles MacNeill 5:89031b2f5316 519
Charles MacNeill 5:89031b2f5316 520
Charles MacNeill 5:89031b2f5316 521 typedef struct {
Charles MacNeill 5:89031b2f5316 522 uint8_t identification__model_id;
Charles MacNeill 5:89031b2f5316 523
Charles MacNeill 5:89031b2f5316 524 uint8_t identification__module_type;
Charles MacNeill 5:89031b2f5316 525
Charles MacNeill 5:89031b2f5316 526 uint8_t identification__revision_id;
Charles MacNeill 5:89031b2f5316 527
Charles MacNeill 5:89031b2f5316 528 uint16_t identification__module_id;
Charles MacNeill 5:89031b2f5316 529
Charles MacNeill 5:89031b2f5316 530 uint8_t ana_config__fast_osc__trim_max;
Charles MacNeill 5:89031b2f5316 531
Charles MacNeill 5:89031b2f5316 532 uint8_t ana_config__fast_osc__freq_set;
Charles MacNeill 5:89031b2f5316 533
Charles MacNeill 5:89031b2f5316 534 uint8_t ana_config__vcsel_trim;
Charles MacNeill 5:89031b2f5316 535
Charles MacNeill 5:89031b2f5316 536 uint8_t ana_config__vcsel_selion;
Charles MacNeill 5:89031b2f5316 537
Charles MacNeill 5:89031b2f5316 538 uint8_t ana_config__vcsel_selion_max;
Charles MacNeill 5:89031b2f5316 539
Charles MacNeill 5:89031b2f5316 540 uint8_t protected_laser_safety__lock_bit;
Charles MacNeill 5:89031b2f5316 541
Charles MacNeill 5:89031b2f5316 542 uint8_t laser_safety__key;
Charles MacNeill 5:89031b2f5316 543
Charles MacNeill 5:89031b2f5316 544 uint8_t laser_safety__key_ro;
Charles MacNeill 5:89031b2f5316 545
Charles MacNeill 5:89031b2f5316 546 uint8_t laser_safety__clip;
Charles MacNeill 5:89031b2f5316 547
Charles MacNeill 5:89031b2f5316 548 uint8_t laser_safety__mult;
Charles MacNeill 5:89031b2f5316 549
Charles MacNeill 5:89031b2f5316 550 uint8_t global_config__spad_enables_rtn_0;
Charles MacNeill 5:89031b2f5316 551
Charles MacNeill 5:89031b2f5316 552 uint8_t global_config__spad_enables_rtn_1;
Charles MacNeill 5:89031b2f5316 553
Charles MacNeill 5:89031b2f5316 554 uint8_t global_config__spad_enables_rtn_2;
Charles MacNeill 5:89031b2f5316 555
Charles MacNeill 5:89031b2f5316 556 uint8_t global_config__spad_enables_rtn_3;
Charles MacNeill 5:89031b2f5316 557
Charles MacNeill 5:89031b2f5316 558 uint8_t global_config__spad_enables_rtn_4;
Charles MacNeill 5:89031b2f5316 559
Charles MacNeill 5:89031b2f5316 560 uint8_t global_config__spad_enables_rtn_5;
Charles MacNeill 5:89031b2f5316 561
Charles MacNeill 5:89031b2f5316 562 uint8_t global_config__spad_enables_rtn_6;
Charles MacNeill 5:89031b2f5316 563
Charles MacNeill 5:89031b2f5316 564 uint8_t global_config__spad_enables_rtn_7;
Charles MacNeill 5:89031b2f5316 565
Charles MacNeill 5:89031b2f5316 566 uint8_t global_config__spad_enables_rtn_8;
Charles MacNeill 5:89031b2f5316 567
Charles MacNeill 5:89031b2f5316 568 uint8_t global_config__spad_enables_rtn_9;
Charles MacNeill 5:89031b2f5316 569
Charles MacNeill 5:89031b2f5316 570 uint8_t global_config__spad_enables_rtn_10;
Charles MacNeill 5:89031b2f5316 571
Charles MacNeill 5:89031b2f5316 572 uint8_t global_config__spad_enables_rtn_11;
Charles MacNeill 5:89031b2f5316 573
Charles MacNeill 5:89031b2f5316 574 uint8_t global_config__spad_enables_rtn_12;
Charles MacNeill 5:89031b2f5316 575
Charles MacNeill 5:89031b2f5316 576 uint8_t global_config__spad_enables_rtn_13;
Charles MacNeill 5:89031b2f5316 577
Charles MacNeill 5:89031b2f5316 578 uint8_t global_config__spad_enables_rtn_14;
Charles MacNeill 5:89031b2f5316 579
Charles MacNeill 5:89031b2f5316 580 uint8_t global_config__spad_enables_rtn_15;
Charles MacNeill 5:89031b2f5316 581
Charles MacNeill 5:89031b2f5316 582 uint8_t global_config__spad_enables_rtn_16;
Charles MacNeill 5:89031b2f5316 583
Charles MacNeill 5:89031b2f5316 584 uint8_t global_config__spad_enables_rtn_17;
Charles MacNeill 5:89031b2f5316 585
Charles MacNeill 5:89031b2f5316 586 uint8_t global_config__spad_enables_rtn_18;
Charles MacNeill 5:89031b2f5316 587
Charles MacNeill 5:89031b2f5316 588 uint8_t global_config__spad_enables_rtn_19;
Charles MacNeill 5:89031b2f5316 589
Charles MacNeill 5:89031b2f5316 590 uint8_t global_config__spad_enables_rtn_20;
Charles MacNeill 5:89031b2f5316 591
Charles MacNeill 5:89031b2f5316 592 uint8_t global_config__spad_enables_rtn_21;
Charles MacNeill 5:89031b2f5316 593
Charles MacNeill 5:89031b2f5316 594 uint8_t global_config__spad_enables_rtn_22;
Charles MacNeill 5:89031b2f5316 595
Charles MacNeill 5:89031b2f5316 596 uint8_t global_config__spad_enables_rtn_23;
Charles MacNeill 5:89031b2f5316 597
Charles MacNeill 5:89031b2f5316 598 uint8_t global_config__spad_enables_rtn_24;
Charles MacNeill 5:89031b2f5316 599
Charles MacNeill 5:89031b2f5316 600 uint8_t global_config__spad_enables_rtn_25;
Charles MacNeill 5:89031b2f5316 601
Charles MacNeill 5:89031b2f5316 602 uint8_t global_config__spad_enables_rtn_26;
Charles MacNeill 5:89031b2f5316 603
Charles MacNeill 5:89031b2f5316 604 uint8_t global_config__spad_enables_rtn_27;
Charles MacNeill 5:89031b2f5316 605
Charles MacNeill 5:89031b2f5316 606 uint8_t global_config__spad_enables_rtn_28;
Charles MacNeill 5:89031b2f5316 607
Charles MacNeill 5:89031b2f5316 608 uint8_t global_config__spad_enables_rtn_29;
Charles MacNeill 5:89031b2f5316 609
Charles MacNeill 5:89031b2f5316 610 uint8_t global_config__spad_enables_rtn_30;
Charles MacNeill 5:89031b2f5316 611
Charles MacNeill 5:89031b2f5316 612 uint8_t global_config__spad_enables_rtn_31;
Charles MacNeill 5:89031b2f5316 613
Charles MacNeill 5:89031b2f5316 614 uint8_t roi_config__mode_roi_centre_spad;
Charles MacNeill 5:89031b2f5316 615
Charles MacNeill 5:89031b2f5316 616 uint8_t roi_config__mode_roi_xy_size;
Charles MacNeill 5:89031b2f5316 617
Charles MacNeill 5:89031b2f5316 618 } VL53LX_nvm_copy_data_t;
Charles MacNeill 5:89031b2f5316 619
Charles MacNeill 5:89031b2f5316 620
Charles MacNeill 5:89031b2f5316 621
Charles MacNeill 5:89031b2f5316 622
Charles MacNeill 5:89031b2f5316 623 typedef struct {
Charles MacNeill 5:89031b2f5316 624 uint8_t prev_shadow_result__interrupt_status;
Charles MacNeill 5:89031b2f5316 625
Charles MacNeill 5:89031b2f5316 626 uint8_t prev_shadow_result__range_status;
Charles MacNeill 5:89031b2f5316 627
Charles MacNeill 5:89031b2f5316 628 uint8_t prev_shadow_result__report_status;
Charles MacNeill 5:89031b2f5316 629
Charles MacNeill 5:89031b2f5316 630 uint8_t prev_shadow_result__stream_count;
Charles MacNeill 5:89031b2f5316 631
Charles MacNeill 5:89031b2f5316 632 uint16_t prev_shadow_result__dss_actual_effective_spads_sd0;
Charles MacNeill 5:89031b2f5316 633
Charles MacNeill 5:89031b2f5316 634 uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd0;
Charles MacNeill 5:89031b2f5316 635
Charles MacNeill 5:89031b2f5316 636 uint16_t prev_shadow_result__ambient_count_rate_mcps_sd0;
Charles MacNeill 5:89031b2f5316 637
Charles MacNeill 5:89031b2f5316 638 uint16_t prev_shadow_result__sigma_sd0;
Charles MacNeill 5:89031b2f5316 639
Charles MacNeill 5:89031b2f5316 640 uint16_t prev_shadow_result__phase_sd0;
Charles MacNeill 5:89031b2f5316 641
Charles MacNeill 5:89031b2f5316 642 uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd0;
Charles MacNeill 5:89031b2f5316 643
Charles MacNeill 5:89031b2f5316 644 uint16_t
Charles MacNeill 5:89031b2f5316 645 psr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;
Charles MacNeill 5:89031b2f5316 646
Charles MacNeill 5:89031b2f5316 647 uint16_t prev_shadow_result__mm_inner_actual_effective_spads_sd0;
Charles MacNeill 5:89031b2f5316 648
Charles MacNeill 5:89031b2f5316 649 uint16_t prev_shadow_result__mm_outer_actual_effective_spads_sd0;
Charles MacNeill 5:89031b2f5316 650
Charles MacNeill 5:89031b2f5316 651 uint16_t prev_shadow_result__avg_signal_count_rate_mcps_sd0;
Charles MacNeill 5:89031b2f5316 652
Charles MacNeill 5:89031b2f5316 653 uint16_t prev_shadow_result__dss_actual_effective_spads_sd1;
Charles MacNeill 5:89031b2f5316 654
Charles MacNeill 5:89031b2f5316 655 uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd1;
Charles MacNeill 5:89031b2f5316 656
Charles MacNeill 5:89031b2f5316 657 uint16_t prev_shadow_result__ambient_count_rate_mcps_sd1;
Charles MacNeill 5:89031b2f5316 658
Charles MacNeill 5:89031b2f5316 659 uint16_t prev_shadow_result__sigma_sd1;
Charles MacNeill 5:89031b2f5316 660
Charles MacNeill 5:89031b2f5316 661 uint16_t prev_shadow_result__phase_sd1;
Charles MacNeill 5:89031b2f5316 662
Charles MacNeill 5:89031b2f5316 663 uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd1;
Charles MacNeill 5:89031b2f5316 664
Charles MacNeill 5:89031b2f5316 665 uint16_t prev_shadow_result__spare_0_sd1;
Charles MacNeill 5:89031b2f5316 666
Charles MacNeill 5:89031b2f5316 667 uint16_t prev_shadow_result__spare_1_sd1;
Charles MacNeill 5:89031b2f5316 668
Charles MacNeill 5:89031b2f5316 669 uint16_t prev_shadow_result__spare_2_sd1;
Charles MacNeill 5:89031b2f5316 670
Charles MacNeill 5:89031b2f5316 671 uint16_t prev_shadow_result__spare_3_sd1;
Charles MacNeill 5:89031b2f5316 672
Charles MacNeill 5:89031b2f5316 673 } VL53LX_prev_shadow_system_results_t;
Charles MacNeill 5:89031b2f5316 674
Charles MacNeill 5:89031b2f5316 675
Charles MacNeill 5:89031b2f5316 676
Charles MacNeill 5:89031b2f5316 677
Charles MacNeill 5:89031b2f5316 678 typedef struct {
Charles MacNeill 5:89031b2f5316 679 uint32_t prev_shadow_result_core__ambient_window_events_sd0;
Charles MacNeill 5:89031b2f5316 680
Charles MacNeill 5:89031b2f5316 681 uint32_t prev_shadow_result_core__ranging_total_events_sd0;
Charles MacNeill 5:89031b2f5316 682
Charles MacNeill 5:89031b2f5316 683 int32_t prev_shadow_result_core__signal_total_events_sd0;
Charles MacNeill 5:89031b2f5316 684
Charles MacNeill 5:89031b2f5316 685 uint32_t prev_shadow_result_core__total_periods_elapsed_sd0;
Charles MacNeill 5:89031b2f5316 686
Charles MacNeill 5:89031b2f5316 687 uint32_t prev_shadow_result_core__ambient_window_events_sd1;
Charles MacNeill 5:89031b2f5316 688
Charles MacNeill 5:89031b2f5316 689 uint32_t prev_shadow_result_core__ranging_total_events_sd1;
Charles MacNeill 5:89031b2f5316 690
Charles MacNeill 5:89031b2f5316 691 int32_t prev_shadow_result_core__signal_total_events_sd1;
Charles MacNeill 5:89031b2f5316 692
Charles MacNeill 5:89031b2f5316 693 uint32_t prev_shadow_result_core__total_periods_elapsed_sd1;
Charles MacNeill 5:89031b2f5316 694
Charles MacNeill 5:89031b2f5316 695 uint8_t prev_shadow_result_core__spare_0;
Charles MacNeill 5:89031b2f5316 696
Charles MacNeill 5:89031b2f5316 697 } VL53LX_prev_shadow_core_results_t;
Charles MacNeill 5:89031b2f5316 698
Charles MacNeill 5:89031b2f5316 699
Charles MacNeill 5:89031b2f5316 700
Charles MacNeill 5:89031b2f5316 701
Charles MacNeill 5:89031b2f5316 702 typedef struct {
Charles MacNeill 5:89031b2f5316 703 uint8_t result__debug_status;
Charles MacNeill 5:89031b2f5316 704
Charles MacNeill 5:89031b2f5316 705 uint8_t result__debug_stage;
Charles MacNeill 5:89031b2f5316 706
Charles MacNeill 5:89031b2f5316 707 } VL53LX_patch_debug_t;
Charles MacNeill 5:89031b2f5316 708
Charles MacNeill 5:89031b2f5316 709
Charles MacNeill 5:89031b2f5316 710
Charles MacNeill 5:89031b2f5316 711
Charles MacNeill 5:89031b2f5316 712 typedef struct {
Charles MacNeill 5:89031b2f5316 713 uint16_t gph__system__thresh_rate_high;
Charles MacNeill 5:89031b2f5316 714
Charles MacNeill 5:89031b2f5316 715 uint16_t gph__system__thresh_rate_low;
Charles MacNeill 5:89031b2f5316 716
Charles MacNeill 5:89031b2f5316 717 uint8_t gph__system__interrupt_config_gpio;
Charles MacNeill 5:89031b2f5316 718
Charles MacNeill 5:89031b2f5316 719 } VL53LX_gph_general_config_t;
Charles MacNeill 5:89031b2f5316 720
Charles MacNeill 5:89031b2f5316 721
Charles MacNeill 5:89031b2f5316 722
Charles MacNeill 5:89031b2f5316 723
Charles MacNeill 5:89031b2f5316 724 typedef struct {
Charles MacNeill 5:89031b2f5316 725 uint8_t gph__dss_config__roi_mode_control;
Charles MacNeill 5:89031b2f5316 726
Charles MacNeill 5:89031b2f5316 727 uint16_t gph__dss_config__manual_effective_spads_select;
Charles MacNeill 5:89031b2f5316 728
Charles MacNeill 5:89031b2f5316 729 uint8_t gph__dss_config__manual_block_select;
Charles MacNeill 5:89031b2f5316 730
Charles MacNeill 5:89031b2f5316 731 uint8_t gph__dss_config__max_spads_limit;
Charles MacNeill 5:89031b2f5316 732
Charles MacNeill 5:89031b2f5316 733 uint8_t gph__dss_config__min_spads_limit;
Charles MacNeill 5:89031b2f5316 734
Charles MacNeill 5:89031b2f5316 735 } VL53LX_gph_static_config_t;
Charles MacNeill 5:89031b2f5316 736
Charles MacNeill 5:89031b2f5316 737
Charles MacNeill 5:89031b2f5316 738
Charles MacNeill 5:89031b2f5316 739
Charles MacNeill 5:89031b2f5316 740 typedef struct {
Charles MacNeill 5:89031b2f5316 741 uint8_t gph__mm_config__timeout_macrop_a_hi;
Charles MacNeill 5:89031b2f5316 742
Charles MacNeill 5:89031b2f5316 743 uint8_t gph__mm_config__timeout_macrop_a_lo;
Charles MacNeill 5:89031b2f5316 744
Charles MacNeill 5:89031b2f5316 745 uint8_t gph__mm_config__timeout_macrop_b_hi;
Charles MacNeill 5:89031b2f5316 746
Charles MacNeill 5:89031b2f5316 747 uint8_t gph__mm_config__timeout_macrop_b_lo;
Charles MacNeill 5:89031b2f5316 748
Charles MacNeill 5:89031b2f5316 749 uint8_t gph__range_config__timeout_macrop_a_hi;
Charles MacNeill 5:89031b2f5316 750
Charles MacNeill 5:89031b2f5316 751 uint8_t gph__range_config__timeout_macrop_a_lo;
Charles MacNeill 5:89031b2f5316 752
Charles MacNeill 5:89031b2f5316 753 uint8_t gph__range_config__vcsel_period_a;
Charles MacNeill 5:89031b2f5316 754
Charles MacNeill 5:89031b2f5316 755 uint8_t gph__range_config__vcsel_period_b;
Charles MacNeill 5:89031b2f5316 756
Charles MacNeill 5:89031b2f5316 757 uint8_t gph__range_config__timeout_macrop_b_hi;
Charles MacNeill 5:89031b2f5316 758
Charles MacNeill 5:89031b2f5316 759 uint8_t gph__range_config__timeout_macrop_b_lo;
Charles MacNeill 5:89031b2f5316 760
Charles MacNeill 5:89031b2f5316 761 uint16_t gph__range_config__sigma_thresh;
Charles MacNeill 5:89031b2f5316 762
Charles MacNeill 5:89031b2f5316 763 uint16_t gph__range_config__min_count_rate_rtn_limit_mcps;
Charles MacNeill 5:89031b2f5316 764
Charles MacNeill 5:89031b2f5316 765 uint8_t gph__range_config__valid_phase_low;
Charles MacNeill 5:89031b2f5316 766
Charles MacNeill 5:89031b2f5316 767 uint8_t gph__range_config__valid_phase_high;
Charles MacNeill 5:89031b2f5316 768
Charles MacNeill 5:89031b2f5316 769 } VL53LX_gph_timing_config_t;
Charles MacNeill 5:89031b2f5316 770
Charles MacNeill 5:89031b2f5316 771
Charles MacNeill 5:89031b2f5316 772
Charles MacNeill 5:89031b2f5316 773
Charles MacNeill 5:89031b2f5316 774 typedef struct {
Charles MacNeill 5:89031b2f5316 775 uint8_t firmware__internal_stream_count_div;
Charles MacNeill 5:89031b2f5316 776
Charles MacNeill 5:89031b2f5316 777 uint8_t firmware__internal_stream_counter_val;
Charles MacNeill 5:89031b2f5316 778
Charles MacNeill 5:89031b2f5316 779 } VL53LX_fw_internal_t;
Charles MacNeill 5:89031b2f5316 780
Charles MacNeill 5:89031b2f5316 781
Charles MacNeill 5:89031b2f5316 782
Charles MacNeill 5:89031b2f5316 783
Charles MacNeill 5:89031b2f5316 784 typedef struct {
Charles MacNeill 5:89031b2f5316 785 uint8_t dss_calc__roi_ctrl;
Charles MacNeill 5:89031b2f5316 786
Charles MacNeill 5:89031b2f5316 787 uint8_t dss_calc__spare_1;
Charles MacNeill 5:89031b2f5316 788
Charles MacNeill 5:89031b2f5316 789 uint8_t dss_calc__spare_2;
Charles MacNeill 5:89031b2f5316 790
Charles MacNeill 5:89031b2f5316 791 uint8_t dss_calc__spare_3;
Charles MacNeill 5:89031b2f5316 792
Charles MacNeill 5:89031b2f5316 793 uint8_t dss_calc__spare_4;
Charles MacNeill 5:89031b2f5316 794
Charles MacNeill 5:89031b2f5316 795 uint8_t dss_calc__spare_5;
Charles MacNeill 5:89031b2f5316 796
Charles MacNeill 5:89031b2f5316 797 uint8_t dss_calc__spare_6;
Charles MacNeill 5:89031b2f5316 798
Charles MacNeill 5:89031b2f5316 799 uint8_t dss_calc__spare_7;
Charles MacNeill 5:89031b2f5316 800
Charles MacNeill 5:89031b2f5316 801 uint8_t dss_calc__user_roi_spad_en_0;
Charles MacNeill 5:89031b2f5316 802
Charles MacNeill 5:89031b2f5316 803 uint8_t dss_calc__user_roi_spad_en_1;
Charles MacNeill 5:89031b2f5316 804
Charles MacNeill 5:89031b2f5316 805 uint8_t dss_calc__user_roi_spad_en_2;
Charles MacNeill 5:89031b2f5316 806
Charles MacNeill 5:89031b2f5316 807 uint8_t dss_calc__user_roi_spad_en_3;
Charles MacNeill 5:89031b2f5316 808
Charles MacNeill 5:89031b2f5316 809 uint8_t dss_calc__user_roi_spad_en_4;
Charles MacNeill 5:89031b2f5316 810
Charles MacNeill 5:89031b2f5316 811 uint8_t dss_calc__user_roi_spad_en_5;
Charles MacNeill 5:89031b2f5316 812
Charles MacNeill 5:89031b2f5316 813 uint8_t dss_calc__user_roi_spad_en_6;
Charles MacNeill 5:89031b2f5316 814
Charles MacNeill 5:89031b2f5316 815 uint8_t dss_calc__user_roi_spad_en_7;
Charles MacNeill 5:89031b2f5316 816
Charles MacNeill 5:89031b2f5316 817 uint8_t dss_calc__user_roi_spad_en_8;
Charles MacNeill 5:89031b2f5316 818
Charles MacNeill 5:89031b2f5316 819 uint8_t dss_calc__user_roi_spad_en_9;
Charles MacNeill 5:89031b2f5316 820
Charles MacNeill 5:89031b2f5316 821 uint8_t dss_calc__user_roi_spad_en_10;
Charles MacNeill 5:89031b2f5316 822
Charles MacNeill 5:89031b2f5316 823 uint8_t dss_calc__user_roi_spad_en_11;
Charles MacNeill 5:89031b2f5316 824
Charles MacNeill 5:89031b2f5316 825 uint8_t dss_calc__user_roi_spad_en_12;
Charles MacNeill 5:89031b2f5316 826
Charles MacNeill 5:89031b2f5316 827 uint8_t dss_calc__user_roi_spad_en_13;
Charles MacNeill 5:89031b2f5316 828
Charles MacNeill 5:89031b2f5316 829 uint8_t dss_calc__user_roi_spad_en_14;
Charles MacNeill 5:89031b2f5316 830
Charles MacNeill 5:89031b2f5316 831 uint8_t dss_calc__user_roi_spad_en_15;
Charles MacNeill 5:89031b2f5316 832
Charles MacNeill 5:89031b2f5316 833 uint8_t dss_calc__user_roi_spad_en_16;
Charles MacNeill 5:89031b2f5316 834
Charles MacNeill 5:89031b2f5316 835 uint8_t dss_calc__user_roi_spad_en_17;
Charles MacNeill 5:89031b2f5316 836
Charles MacNeill 5:89031b2f5316 837 uint8_t dss_calc__user_roi_spad_en_18;
Charles MacNeill 5:89031b2f5316 838
Charles MacNeill 5:89031b2f5316 839 uint8_t dss_calc__user_roi_spad_en_19;
Charles MacNeill 5:89031b2f5316 840
Charles MacNeill 5:89031b2f5316 841 uint8_t dss_calc__user_roi_spad_en_20;
Charles MacNeill 5:89031b2f5316 842
Charles MacNeill 5:89031b2f5316 843 uint8_t dss_calc__user_roi_spad_en_21;
Charles MacNeill 5:89031b2f5316 844
Charles MacNeill 5:89031b2f5316 845 uint8_t dss_calc__user_roi_spad_en_22;
Charles MacNeill 5:89031b2f5316 846
Charles MacNeill 5:89031b2f5316 847 uint8_t dss_calc__user_roi_spad_en_23;
Charles MacNeill 5:89031b2f5316 848
Charles MacNeill 5:89031b2f5316 849 uint8_t dss_calc__user_roi_spad_en_24;
Charles MacNeill 5:89031b2f5316 850
Charles MacNeill 5:89031b2f5316 851 uint8_t dss_calc__user_roi_spad_en_25;
Charles MacNeill 5:89031b2f5316 852
Charles MacNeill 5:89031b2f5316 853 uint8_t dss_calc__user_roi_spad_en_26;
Charles MacNeill 5:89031b2f5316 854
Charles MacNeill 5:89031b2f5316 855 uint8_t dss_calc__user_roi_spad_en_27;
Charles MacNeill 5:89031b2f5316 856
Charles MacNeill 5:89031b2f5316 857 uint8_t dss_calc__user_roi_spad_en_28;
Charles MacNeill 5:89031b2f5316 858
Charles MacNeill 5:89031b2f5316 859 uint8_t dss_calc__user_roi_spad_en_29;
Charles MacNeill 5:89031b2f5316 860
Charles MacNeill 5:89031b2f5316 861 uint8_t dss_calc__user_roi_spad_en_30;
Charles MacNeill 5:89031b2f5316 862
Charles MacNeill 5:89031b2f5316 863 uint8_t dss_calc__user_roi_spad_en_31;
Charles MacNeill 5:89031b2f5316 864
Charles MacNeill 5:89031b2f5316 865 uint8_t dss_calc__user_roi_0;
Charles MacNeill 5:89031b2f5316 866
Charles MacNeill 5:89031b2f5316 867 uint8_t dss_calc__user_roi_1;
Charles MacNeill 5:89031b2f5316 868
Charles MacNeill 5:89031b2f5316 869 uint8_t dss_calc__mode_roi_0;
Charles MacNeill 5:89031b2f5316 870
Charles MacNeill 5:89031b2f5316 871 uint8_t dss_calc__mode_roi_1;
Charles MacNeill 5:89031b2f5316 872
Charles MacNeill 5:89031b2f5316 873 uint8_t sigma_estimator_calc__spare_0;
Charles MacNeill 5:89031b2f5316 874
Charles MacNeill 5:89031b2f5316 875 uint16_t vhv_result__peak_signal_rate_mcps;
Charles MacNeill 5:89031b2f5316 876
Charles MacNeill 5:89031b2f5316 877 uint32_t vhv_result__signal_total_events_ref;
Charles MacNeill 5:89031b2f5316 878
Charles MacNeill 5:89031b2f5316 879 uint16_t phasecal_result__phase_output_ref;
Charles MacNeill 5:89031b2f5316 880
Charles MacNeill 5:89031b2f5316 881 uint16_t dss_result__total_rate_per_spad;
Charles MacNeill 5:89031b2f5316 882
Charles MacNeill 5:89031b2f5316 883 uint8_t dss_result__enabled_blocks;
Charles MacNeill 5:89031b2f5316 884
Charles MacNeill 5:89031b2f5316 885 uint16_t dss_result__num_requested_spads;
Charles MacNeill 5:89031b2f5316 886
Charles MacNeill 5:89031b2f5316 887 uint16_t mm_result__inner_intersection_rate;
Charles MacNeill 5:89031b2f5316 888
Charles MacNeill 5:89031b2f5316 889 uint16_t mm_result__outer_complement_rate;
Charles MacNeill 5:89031b2f5316 890
Charles MacNeill 5:89031b2f5316 891 uint16_t mm_result__total_offset;
Charles MacNeill 5:89031b2f5316 892
Charles MacNeill 5:89031b2f5316 893 uint32_t xtalk_calc__xtalk_for_enabled_spads;
Charles MacNeill 5:89031b2f5316 894
Charles MacNeill 5:89031b2f5316 895 uint32_t xtalk_result__avg_xtalk_user_roi_kcps;
Charles MacNeill 5:89031b2f5316 896
Charles MacNeill 5:89031b2f5316 897 uint32_t xtalk_result__avg_xtalk_mm_inner_roi_kcps;
Charles MacNeill 5:89031b2f5316 898
Charles MacNeill 5:89031b2f5316 899 uint32_t xtalk_result__avg_xtalk_mm_outer_roi_kcps;
Charles MacNeill 5:89031b2f5316 900
Charles MacNeill 5:89031b2f5316 901 uint32_t range_result__accum_phase;
Charles MacNeill 5:89031b2f5316 902
Charles MacNeill 5:89031b2f5316 903 uint16_t range_result__offset_corrected_range;
Charles MacNeill 5:89031b2f5316 904
Charles MacNeill 5:89031b2f5316 905 } VL53LX_patch_results_t;
Charles MacNeill 5:89031b2f5316 906
Charles MacNeill 5:89031b2f5316 907
Charles MacNeill 5:89031b2f5316 908
Charles MacNeill 5:89031b2f5316 909
Charles MacNeill 5:89031b2f5316 910 typedef struct {
Charles MacNeill 5:89031b2f5316 911 uint8_t shadow_phasecal_result__vcsel_start;
Charles MacNeill 5:89031b2f5316 912
Charles MacNeill 5:89031b2f5316 913 uint8_t shadow_result__interrupt_status;
Charles MacNeill 5:89031b2f5316 914
Charles MacNeill 5:89031b2f5316 915 uint8_t shadow_result__range_status;
Charles MacNeill 5:89031b2f5316 916
Charles MacNeill 5:89031b2f5316 917 uint8_t shadow_result__report_status;
Charles MacNeill 5:89031b2f5316 918
Charles MacNeill 5:89031b2f5316 919 uint8_t shadow_result__stream_count;
Charles MacNeill 5:89031b2f5316 920
Charles MacNeill 5:89031b2f5316 921 uint16_t shadow_result__dss_actual_effective_spads_sd0;
Charles MacNeill 5:89031b2f5316 922
Charles MacNeill 5:89031b2f5316 923 uint16_t shadow_result__peak_signal_count_rate_mcps_sd0;
Charles MacNeill 5:89031b2f5316 924
Charles MacNeill 5:89031b2f5316 925 uint16_t shadow_result__ambient_count_rate_mcps_sd0;
Charles MacNeill 5:89031b2f5316 926
Charles MacNeill 5:89031b2f5316 927 uint16_t shadow_result__sigma_sd0;
Charles MacNeill 5:89031b2f5316 928
Charles MacNeill 5:89031b2f5316 929 uint16_t shadow_result__phase_sd0;
Charles MacNeill 5:89031b2f5316 930
Charles MacNeill 5:89031b2f5316 931 uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd0;
Charles MacNeill 5:89031b2f5316 932
Charles MacNeill 5:89031b2f5316 933 uint16_t
Charles MacNeill 5:89031b2f5316 934 shr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;
Charles MacNeill 5:89031b2f5316 935
Charles MacNeill 5:89031b2f5316 936 uint16_t shadow_result__mm_inner_actual_effective_spads_sd0;
Charles MacNeill 5:89031b2f5316 937
Charles MacNeill 5:89031b2f5316 938 uint16_t shadow_result__mm_outer_actual_effective_spads_sd0;
Charles MacNeill 5:89031b2f5316 939
Charles MacNeill 5:89031b2f5316 940 uint16_t shadow_result__avg_signal_count_rate_mcps_sd0;
Charles MacNeill 5:89031b2f5316 941
Charles MacNeill 5:89031b2f5316 942 uint16_t shadow_result__dss_actual_effective_spads_sd1;
Charles MacNeill 5:89031b2f5316 943
Charles MacNeill 5:89031b2f5316 944 uint16_t shadow_result__peak_signal_count_rate_mcps_sd1;
Charles MacNeill 5:89031b2f5316 945
Charles MacNeill 5:89031b2f5316 946 uint16_t shadow_result__ambient_count_rate_mcps_sd1;
Charles MacNeill 5:89031b2f5316 947
Charles MacNeill 5:89031b2f5316 948 uint16_t shadow_result__sigma_sd1;
Charles MacNeill 5:89031b2f5316 949
Charles MacNeill 5:89031b2f5316 950 uint16_t shadow_result__phase_sd1;
Charles MacNeill 5:89031b2f5316 951
Charles MacNeill 5:89031b2f5316 952 uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd1;
Charles MacNeill 5:89031b2f5316 953
Charles MacNeill 5:89031b2f5316 954 uint16_t shadow_result__spare_0_sd1;
Charles MacNeill 5:89031b2f5316 955
Charles MacNeill 5:89031b2f5316 956 uint16_t shadow_result__spare_1_sd1;
Charles MacNeill 5:89031b2f5316 957
Charles MacNeill 5:89031b2f5316 958 uint16_t shadow_result__spare_2_sd1;
Charles MacNeill 5:89031b2f5316 959
Charles MacNeill 5:89031b2f5316 960 uint8_t shadow_result__spare_3_sd1;
Charles MacNeill 5:89031b2f5316 961
Charles MacNeill 5:89031b2f5316 962 uint8_t shadow_result__thresh_info;
Charles MacNeill 5:89031b2f5316 963
Charles MacNeill 5:89031b2f5316 964 uint8_t shadow_phasecal_result__reference_phase_hi;
Charles MacNeill 5:89031b2f5316 965
Charles MacNeill 5:89031b2f5316 966 uint8_t shadow_phasecal_result__reference_phase_lo;
Charles MacNeill 5:89031b2f5316 967
Charles MacNeill 5:89031b2f5316 968 } VL53LX_shadow_system_results_t;
Charles MacNeill 5:89031b2f5316 969
Charles MacNeill 5:89031b2f5316 970
Charles MacNeill 5:89031b2f5316 971
Charles MacNeill 5:89031b2f5316 972
Charles MacNeill 5:89031b2f5316 973 typedef struct {
Charles MacNeill 5:89031b2f5316 974 uint32_t shadow_result_core__ambient_window_events_sd0;
Charles MacNeill 5:89031b2f5316 975
Charles MacNeill 5:89031b2f5316 976 uint32_t shadow_result_core__ranging_total_events_sd0;
Charles MacNeill 5:89031b2f5316 977
Charles MacNeill 5:89031b2f5316 978 int32_t shadow_result_core__signal_total_events_sd0;
Charles MacNeill 5:89031b2f5316 979
Charles MacNeill 5:89031b2f5316 980 uint32_t shadow_result_core__total_periods_elapsed_sd0;
Charles MacNeill 5:89031b2f5316 981
Charles MacNeill 5:89031b2f5316 982 uint32_t shadow_result_core__ambient_window_events_sd1;
Charles MacNeill 5:89031b2f5316 983
Charles MacNeill 5:89031b2f5316 984 uint32_t shadow_result_core__ranging_total_events_sd1;
Charles MacNeill 5:89031b2f5316 985
Charles MacNeill 5:89031b2f5316 986 int32_t shadow_result_core__signal_total_events_sd1;
Charles MacNeill 5:89031b2f5316 987
Charles MacNeill 5:89031b2f5316 988 uint32_t shadow_result_core__total_periods_elapsed_sd1;
Charles MacNeill 5:89031b2f5316 989
Charles MacNeill 5:89031b2f5316 990 uint8_t shadow_result_core__spare_0;
Charles MacNeill 5:89031b2f5316 991
Charles MacNeill 5:89031b2f5316 992 } VL53LX_shadow_core_results_t;
Charles MacNeill 5:89031b2f5316 993
Charles MacNeill 5:89031b2f5316 994
Charles MacNeill 5:89031b2f5316 995 #endif
Charles MacNeill 5:89031b2f5316 996
Charles MacNeill 5:89031b2f5316 997