vl53l1_register_structs.h

00001 
00002 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
00003 /******************************************************************************
00004  * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
00005 
00006  This file is part of VL53L1 and is dual licensed,
00007  either GPL-2.0+
00008  or 'BSD 3-clause "New" or "Revised" License' , at your option.
00009  ******************************************************************************
00010  */
00011 
00012 
00013 
00014 
00015 #ifndef _VL53L1_REGISTER_STRUCTS_H_
00016 #define _VL53L1_REGISTER_STRUCTS_H_
00017 
00018 #include "vl53l1_types.h"
00019 #include "vl53l1_register_map.h"
00020 
00021 #define VL53L1_STATIC_NVM_MANAGED_I2C_INDEX             \
00022     VL53L1_I2C_SLAVE__DEVICE_ADDRESS
00023 #define VL53L1_CUSTOMER_NVM_MANAGED_I2C_INDEX           \
00024     VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_0
00025 #define VL53L1_STATIC_CONFIG_I2C_INDEX                  \
00026     VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS
00027 #define VL53L1_GENERAL_CONFIG_I2C_INDEX                  \
00028     VL53L1_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE
00029 #define VL53L1_TIMING_CONFIG_I2C_INDEX                  \
00030     VL53L1_MM_CONFIG__TIMEOUT_MACROP_A_HI
00031 #define VL53L1_DYNAMIC_CONFIG_I2C_INDEX                 \
00032     VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD_0
00033 #define VL53L1_SYSTEM_CONTROL_I2C_INDEX                 \
00034     VL53L1_POWER_MANAGEMENT__GO1_POWER_FORCE
00035 #define VL53L1_SYSTEM_RESULTS_I2C_INDEX                 \
00036     VL53L1_RESULT__INTERRUPT_STATUS
00037 #define VL53L1_CORE_RESULTS_I2C_INDEX                   \
00038     VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
00039 #define VL53L1_DEBUG_RESULTS_I2C_INDEX                  \
00040     VL53L1_PHASECAL_RESULT__REFERENCE_PHASE
00041 #define VL53L1_NVM_COPY_DATA_I2C_INDEX                 \
00042     VL53L1_IDENTIFICATION__MODEL_ID
00043 #define VL53L1_PREV_SHADOW_SYSTEM_RESULTS_I2C_INDEX    \
00044     VL53L1_PREV_SHADOW_RESULT__INTERRUPT_STATUS
00045 #define VL53L1_PREV_SHADOW_CORE_RESULTS_I2C_INDEX      \
00046     VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
00047 #define VL53L1_PATCH_DEBUG_I2C_INDEX                   \
00048     VL53L1_RESULT__DEBUG_STATUS
00049 #define VL53L1_GPH_GENERAL_CONFIG_I2C_INDEX            \
00050     VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH
00051 #define VL53L1_GPH_STATIC_CONFIG_I2C_INDEX             \
00052     VL53L1_GPH__DSS_CONFIG__ROI_MODE_CONTROL
00053 #define VL53L1_GPH_TIMING_CONFIG_I2C_INDEX             \
00054     VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI
00055 #define VL53L1_FW_INTERNAL_I2C_INDEX                   \
00056     VL53L1_FIRMWARE__INTERNAL_STREAM_COUNT_DIV
00057 #define VL53L1_PATCH_RESULTS_I2C_INDEX                 \
00058     VL53L1_DSS_CALC__ROI_CTRL
00059 #define VL53L1_SHADOW_SYSTEM_RESULTS_I2C_INDEX         \
00060     VL53L1_SHADOW_PHASECAL_RESULT__VCSEL_START
00061 #define VL53L1_SHADOW_CORE_RESULTS_I2C_INDEX           \
00062     VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
00063 
00064 #define VL53L1_STATIC_NVM_MANAGED_I2C_SIZE_BYTES           11
00065 #define VL53L1_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES         23
00066 #define VL53L1_STATIC_CONFIG_I2C_SIZE_BYTES                32
00067 #define VL53L1_GENERAL_CONFIG_I2C_SIZE_BYTES               22
00068 #define VL53L1_TIMING_CONFIG_I2C_SIZE_BYTES                23
00069 #define VL53L1_DYNAMIC_CONFIG_I2C_SIZE_BYTES               18
00070 #define VL53L1_SYSTEM_CONTROL_I2C_SIZE_BYTES                5
00071 #define VL53L1_SYSTEM_RESULTS_I2C_SIZE_BYTES               44
00072 #define VL53L1_CORE_RESULTS_I2C_SIZE_BYTES                 33
00073 #define VL53L1_DEBUG_RESULTS_I2C_SIZE_BYTES                56
00074 #define VL53L1_NVM_COPY_DATA_I2C_SIZE_BYTES                49
00075 #define VL53L1_PREV_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES   44
00076 #define VL53L1_PREV_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES     33
00077 #define VL53L1_PATCH_DEBUG_I2C_SIZE_BYTES                   2
00078 #define VL53L1_GPH_GENERAL_CONFIG_I2C_SIZE_BYTES            5
00079 #define VL53L1_GPH_STATIC_CONFIG_I2C_SIZE_BYTES             6
00080 #define VL53L1_GPH_TIMING_CONFIG_I2C_SIZE_BYTES            16
00081 #define VL53L1_FW_INTERNAL_I2C_SIZE_BYTES                   2
00082 #define VL53L1_PATCH_RESULTS_I2C_SIZE_BYTES                90
00083 #define VL53L1_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES        82
00084 #define VL53L1_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES          33
00085 
00086 
00087 
00088 
00089 typedef struct {
00090     uint8_t   i2c_slave__device_address;
00091 
00092     uint8_t   ana_config__vhv_ref_sel_vddpix;
00093 
00094     uint8_t   ana_config__vhv_ref_sel_vquench;
00095 
00096     uint8_t   ana_config__reg_avdd1v2_sel;
00097 
00098     uint8_t   ana_config__fast_osc__trim;
00099 
00100     uint16_t  osc_measured__fast_osc__frequency;
00101 
00102     uint8_t   vhv_config__timeout_macrop_loop_bound;
00103 
00104     uint8_t   vhv_config__count_thresh;
00105 
00106     uint8_t   vhv_config__offset;
00107 
00108     uint8_t   vhv_config__init;
00109 
00110 } VL53L1_static_nvm_managed_t;
00111 
00112 
00113 
00114 
00115 typedef struct {
00116     uint8_t   global_config__spad_enables_ref_0;
00117 
00118     uint8_t   global_config__spad_enables_ref_1;
00119 
00120     uint8_t   global_config__spad_enables_ref_2;
00121 
00122     uint8_t   global_config__spad_enables_ref_3;
00123 
00124     uint8_t   global_config__spad_enables_ref_4;
00125 
00126     uint8_t   global_config__spad_enables_ref_5;
00127 
00128     uint8_t   global_config__ref_en_start_select;
00129 
00130     uint8_t   ref_spad_man__num_requested_ref_spads;
00131 
00132     uint8_t   ref_spad_man__ref_location;
00133 
00134     uint16_t  algo__crosstalk_compensation_plane_offset_kcps;
00135 
00136     int16_t   algo__crosstalk_compensation_x_plane_gradient_kcps;
00137 
00138     int16_t   algo__crosstalk_compensation_y_plane_gradient_kcps;
00139 
00140     uint16_t  ref_spad_char__total_rate_target_mcps;
00141 
00142     int16_t   algo__part_to_part_range_offset_mm;
00143 
00144     int16_t   mm_config__inner_offset_mm;
00145 
00146     int16_t   mm_config__outer_offset_mm;
00147 
00148 } VL53L1_customer_nvm_managed_t;
00149 
00150 
00151 
00152 
00153 typedef struct {
00154     uint16_t  dss_config__target_total_rate_mcps;
00155 
00156     uint8_t   debug__ctrl;
00157 
00158     uint8_t   test_mode__ctrl;
00159 
00160     uint8_t   clk_gating__ctrl;
00161 
00162     uint8_t   nvm_bist__ctrl;
00163 
00164     uint8_t   nvm_bist__num_nvm_words;
00165 
00166     uint8_t   nvm_bist__start_address;
00167 
00168     uint8_t   host_if__status;
00169 
00170     uint8_t   pad_i2c_hv__config;
00171 
00172     uint8_t   pad_i2c_hv__extsup_config;
00173 
00174     uint8_t   gpio_hv_pad__ctrl;
00175 
00176     uint8_t   gpio_hv_mux__ctrl;
00177 
00178     uint8_t   gpio__tio_hv_status;
00179 
00180     uint8_t   gpio__fio_hv_status;
00181 
00182     uint8_t   ana_config__spad_sel_pswidth;
00183 
00184     uint8_t   ana_config__vcsel_pulse_width_offset;
00185 
00186     uint8_t   ana_config__fast_osc__config_ctrl;
00187 
00188     uint8_t   sigma_estimator__effective_pulse_width_ns;
00189 
00190     uint8_t   sigma_estimator__effective_ambient_width_ns;
00191 
00192     uint8_t   sigma_estimator__sigma_ref_mm;
00193 
00194     uint8_t   algo__crosstalk_compensation_valid_height_mm;
00195 
00196     uint8_t   spare_host_config__static_config_spare_0;
00197 
00198     uint8_t   spare_host_config__static_config_spare_1;
00199 
00200     uint16_t  algo__range_ignore_threshold_mcps;
00201 
00202     uint8_t   algo__range_ignore_valid_height_mm;
00203 
00204     uint8_t   algo__range_min_clip;
00205 
00206     uint8_t   algo__consistency_check__tolerance;
00207 
00208     uint8_t   spare_host_config__static_config_spare_2;
00209 
00210     uint8_t   sd_config__reset_stages_msb;
00211 
00212     uint8_t   sd_config__reset_stages_lsb;
00213 
00214 } VL53L1_static_config_t;
00215 
00216 
00217 
00218 
00219 typedef struct {
00220     uint8_t   gph_config__stream_count_update_value;
00221 
00222     uint8_t   global_config__stream_divider;
00223 
00224     uint8_t   system__interrupt_config_gpio;
00225 
00226     uint8_t   cal_config__vcsel_start;
00227 
00228     uint16_t  cal_config__repeat_rate;
00229 
00230     uint8_t   global_config__vcsel_width;
00231 
00232     uint8_t   phasecal_config__timeout_macrop;
00233 
00234     uint8_t   phasecal_config__target;
00235 
00236     uint8_t   phasecal_config__override;
00237 
00238     uint8_t   dss_config__roi_mode_control;
00239 
00240     uint16_t  system__thresh_rate_high;
00241 
00242     uint16_t  system__thresh_rate_low;
00243 
00244     uint16_t  dss_config__manual_effective_spads_select;
00245 
00246     uint8_t   dss_config__manual_block_select;
00247 
00248     uint8_t   dss_config__aperture_attenuation;
00249 
00250     uint8_t   dss_config__max_spads_limit;
00251 
00252     uint8_t   dss_config__min_spads_limit;
00253 
00254 } VL53L1_general_config_t;
00255 
00256 
00257 
00258 
00259 typedef struct {
00260     uint8_t   mm_config__timeout_macrop_a_hi;
00261 
00262     uint8_t   mm_config__timeout_macrop_a_lo;
00263 
00264     uint8_t   mm_config__timeout_macrop_b_hi;
00265 
00266     uint8_t   mm_config__timeout_macrop_b_lo;
00267 
00268     uint8_t   range_config__timeout_macrop_a_hi;
00269 
00270     uint8_t   range_config__timeout_macrop_a_lo;
00271 
00272     uint8_t   range_config__vcsel_period_a;
00273 
00274     uint8_t   range_config__timeout_macrop_b_hi;
00275 
00276     uint8_t   range_config__timeout_macrop_b_lo;
00277 
00278     uint8_t   range_config__vcsel_period_b;
00279 
00280     uint16_t  range_config__sigma_thresh;
00281 
00282     uint16_t  range_config__min_count_rate_rtn_limit_mcps;
00283 
00284     uint8_t   range_config__valid_phase_low;
00285 
00286     uint8_t   range_config__valid_phase_high;
00287 
00288     uint32_t  system__intermeasurement_period;
00289 
00290     uint8_t   system__fractional_enable;
00291 
00292 } VL53L1_timing_config_t;
00293 
00294 
00295 
00296 
00297 typedef struct {
00298     uint8_t   system__grouped_parameter_hold_0;
00299 
00300     uint16_t  system__thresh_high;
00301 
00302     uint16_t  system__thresh_low;
00303 
00304     uint8_t   system__enable_xtalk_per_quadrant;
00305 
00306     uint8_t   system__seed_config;
00307 
00308     uint8_t   sd_config__woi_sd0;
00309 
00310     uint8_t   sd_config__woi_sd1;
00311 
00312     uint8_t   sd_config__initial_phase_sd0;
00313 
00314     uint8_t   sd_config__initial_phase_sd1;
00315 
00316     uint8_t   system__grouped_parameter_hold_1;
00317 
00318     uint8_t   sd_config__first_order_select;
00319 
00320     uint8_t   sd_config__quantifier;
00321 
00322     uint8_t   roi_config__user_roi_centre_spad;
00323 
00324     uint8_t   roi_config__user_roi_requested_global_xy_size;
00325 
00326     uint8_t   system__sequence_config;
00327 
00328     uint8_t   system__grouped_parameter_hold;
00329 
00330 } VL53L1_dynamic_config_t;
00331 
00332 
00333 
00334 
00335 typedef struct {
00336     uint8_t   power_management__go1_power_force;
00337 
00338     uint8_t   system__stream_count_ctrl;
00339 
00340     uint8_t   firmware__enable;
00341 
00342     uint8_t   system__interrupt_clear;
00343 
00344     uint8_t   system__mode_start;
00345 
00346 } VL53L1_system_control_t;
00347 
00348 
00349 
00350 
00351 typedef struct {
00352     uint8_t   result__interrupt_status;
00353 
00354     uint8_t   result__range_status;
00355 
00356     uint8_t   result__report_status;
00357 
00358     uint8_t   result__stream_count;
00359 
00360     uint16_t  result__dss_actual_effective_spads_sd0;
00361 
00362     uint16_t  result__peak_signal_count_rate_mcps_sd0;
00363 
00364     uint16_t  result__ambient_count_rate_mcps_sd0;
00365 
00366     uint16_t  result__sigma_sd0;
00367 
00368     uint16_t  result__phase_sd0;
00369 
00370     uint16_t  result__final_crosstalk_corrected_range_mm_sd0;
00371 
00372     uint16_t  result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;
00373 
00374     uint16_t  result__mm_inner_actual_effective_spads_sd0;
00375 
00376     uint16_t  result__mm_outer_actual_effective_spads_sd0;
00377 
00378     uint16_t  result__avg_signal_count_rate_mcps_sd0;
00379 
00380     uint16_t  result__dss_actual_effective_spads_sd1;
00381 
00382     uint16_t  result__peak_signal_count_rate_mcps_sd1;
00383 
00384     uint16_t  result__ambient_count_rate_mcps_sd1;
00385 
00386     uint16_t  result__sigma_sd1;
00387 
00388     uint16_t  result__phase_sd1;
00389 
00390     uint16_t  result__final_crosstalk_corrected_range_mm_sd1;
00391 
00392     uint16_t  result__spare_0_sd1;
00393 
00394     uint16_t  result__spare_1_sd1;
00395 
00396     uint16_t  result__spare_2_sd1;
00397 
00398     uint8_t   result__spare_3_sd1;
00399 
00400     uint8_t   result__thresh_info;
00401 
00402 } VL53L1_system_results_t;
00403 
00404 
00405 
00406 
00407 typedef struct {
00408     uint32_t  result_core__ambient_window_events_sd0;
00409 
00410     uint32_t  result_core__ranging_total_events_sd0;
00411 
00412     int32_t   result_core__signal_total_events_sd0;
00413 
00414     uint32_t  result_core__total_periods_elapsed_sd0;
00415 
00416     uint32_t  result_core__ambient_window_events_sd1;
00417 
00418     uint32_t  result_core__ranging_total_events_sd1;
00419 
00420     int32_t   result_core__signal_total_events_sd1;
00421 
00422     uint32_t  result_core__total_periods_elapsed_sd1;
00423 
00424     uint8_t   result_core__spare_0;
00425 
00426 } VL53L1_core_results_t;
00427 
00428 
00429 
00430 
00431 typedef struct {
00432     uint16_t  phasecal_result__reference_phase;
00433 
00434     uint8_t   phasecal_result__vcsel_start;
00435 
00436     uint8_t   ref_spad_char_result__num_actual_ref_spads;
00437 
00438     uint8_t   ref_spad_char_result__ref_location;
00439 
00440     uint8_t   vhv_result__coldboot_status;
00441 
00442     uint8_t   vhv_result__search_result;
00443 
00444     uint8_t   vhv_result__latest_setting;
00445 
00446     uint16_t  result__osc_calibrate_val;
00447 
00448     uint8_t   ana_config__powerdown_go1;
00449 
00450     uint8_t   ana_config__ref_bg_ctrl;
00451 
00452     uint8_t   ana_config__regdvdd1v2_ctrl;
00453 
00454     uint8_t   ana_config__osc_slow_ctrl;
00455 
00456     uint8_t   test_mode__status;
00457 
00458     uint8_t   firmware__system_status;
00459 
00460     uint8_t   firmware__mode_status;
00461 
00462     uint8_t   firmware__secondary_mode_status;
00463 
00464     uint16_t  firmware__cal_repeat_rate_counter;
00465 
00466     uint16_t  gph__system__thresh_high;
00467 
00468     uint16_t  gph__system__thresh_low;
00469 
00470     uint8_t   gph__system__enable_xtalk_per_quadrant;
00471 
00472     uint8_t   gph__spare_0;
00473 
00474     uint8_t   gph__sd_config__woi_sd0;
00475 
00476     uint8_t   gph__sd_config__woi_sd1;
00477 
00478     uint8_t   gph__sd_config__initial_phase_sd0;
00479 
00480     uint8_t   gph__sd_config__initial_phase_sd1;
00481 
00482     uint8_t   gph__sd_config__first_order_select;
00483 
00484     uint8_t   gph__sd_config__quantifier;
00485 
00486     uint8_t   gph__roi_config__user_roi_centre_spad;
00487 
00488     uint8_t   gph__roi_config__user_roi_requested_global_xy_size;
00489 
00490     uint8_t   gph__system__sequence_config;
00491 
00492     uint8_t   gph__gph_id;
00493 
00494     uint8_t   system__interrupt_set;
00495 
00496     uint8_t   interrupt_manager__enables;
00497 
00498     uint8_t   interrupt_manager__clear;
00499 
00500     uint8_t   interrupt_manager__status;
00501 
00502     uint8_t   mcu_to_host_bank__wr_access_en;
00503 
00504     uint8_t   power_management__go1_reset_status;
00505 
00506     uint8_t   pad_startup_mode__value_ro;
00507 
00508     uint8_t   pad_startup_mode__value_ctrl;
00509 
00510     uint32_t  pll_period_us;
00511 
00512     uint32_t  interrupt_scheduler__data_out;
00513 
00514     uint8_t   nvm_bist__complete;
00515 
00516     uint8_t   nvm_bist__status;
00517 
00518 } VL53L1_debug_results_t;
00519 
00520 
00521 
00522 
00523 typedef struct {
00524     uint8_t   identification__model_id;
00525 
00526     uint8_t   identification__module_type;
00527 
00528     uint8_t   identification__revision_id;
00529 
00530     uint16_t  identification__module_id;
00531 
00532     uint8_t   ana_config__fast_osc__trim_max;
00533 
00534     uint8_t   ana_config__fast_osc__freq_set;
00535 
00536     uint8_t   ana_config__vcsel_trim;
00537 
00538     uint8_t   ana_config__vcsel_selion;
00539 
00540     uint8_t   ana_config__vcsel_selion_max;
00541 
00542     uint8_t   protected_laser_safety__lock_bit;
00543 
00544     uint8_t   laser_safety__key;
00545 
00546     uint8_t   laser_safety__key_ro;
00547 
00548     uint8_t   laser_safety__clip;
00549 
00550     uint8_t   laser_safety__mult;
00551 
00552     uint8_t   global_config__spad_enables_rtn_0;
00553 
00554     uint8_t   global_config__spad_enables_rtn_1;
00555 
00556     uint8_t   global_config__spad_enables_rtn_2;
00557 
00558     uint8_t   global_config__spad_enables_rtn_3;
00559 
00560     uint8_t   global_config__spad_enables_rtn_4;
00561 
00562     uint8_t   global_config__spad_enables_rtn_5;
00563 
00564     uint8_t   global_config__spad_enables_rtn_6;
00565 
00566     uint8_t   global_config__spad_enables_rtn_7;
00567 
00568     uint8_t   global_config__spad_enables_rtn_8;
00569 
00570     uint8_t   global_config__spad_enables_rtn_9;
00571 
00572     uint8_t   global_config__spad_enables_rtn_10;
00573 
00574     uint8_t   global_config__spad_enables_rtn_11;
00575 
00576     uint8_t   global_config__spad_enables_rtn_12;
00577 
00578     uint8_t   global_config__spad_enables_rtn_13;
00579 
00580     uint8_t   global_config__spad_enables_rtn_14;
00581 
00582     uint8_t   global_config__spad_enables_rtn_15;
00583 
00584     uint8_t   global_config__spad_enables_rtn_16;
00585 
00586     uint8_t   global_config__spad_enables_rtn_17;
00587 
00588     uint8_t   global_config__spad_enables_rtn_18;
00589 
00590     uint8_t   global_config__spad_enables_rtn_19;
00591 
00592     uint8_t   global_config__spad_enables_rtn_20;
00593 
00594     uint8_t   global_config__spad_enables_rtn_21;
00595 
00596     uint8_t   global_config__spad_enables_rtn_22;
00597 
00598     uint8_t   global_config__spad_enables_rtn_23;
00599 
00600     uint8_t   global_config__spad_enables_rtn_24;
00601 
00602     uint8_t   global_config__spad_enables_rtn_25;
00603 
00604     uint8_t   global_config__spad_enables_rtn_26;
00605 
00606     uint8_t   global_config__spad_enables_rtn_27;
00607 
00608     uint8_t   global_config__spad_enables_rtn_28;
00609 
00610     uint8_t   global_config__spad_enables_rtn_29;
00611 
00612     uint8_t   global_config__spad_enables_rtn_30;
00613 
00614     uint8_t   global_config__spad_enables_rtn_31;
00615 
00616     uint8_t   roi_config__mode_roi_centre_spad;
00617 
00618     uint8_t   roi_config__mode_roi_xy_size;
00619 
00620 } VL53L1_nvm_copy_data_t;
00621 
00622 
00623 
00624 
00625 typedef struct {
00626     uint8_t   prev_shadow_result__interrupt_status;
00627 
00628     uint8_t   prev_shadow_result__range_status;
00629 
00630     uint8_t   prev_shadow_result__report_status;
00631 
00632     uint8_t   prev_shadow_result__stream_count;
00633 
00634     uint16_t  prev_shadow_result__dss_actual_effective_spads_sd0;
00635 
00636     uint16_t  prev_shadow_result__peak_signal_count_rate_mcps_sd0;
00637 
00638     uint16_t  prev_shadow_result__ambient_count_rate_mcps_sd0;
00639 
00640     uint16_t  prev_shadow_result__sigma_sd0;
00641 
00642     uint16_t  prev_shadow_result__phase_sd0;
00643 
00644     uint16_t  prev_shadow_result__final_crosstalk_corrected_range_mm_sd0;
00645 
00646     uint16_t
00647     psr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;
00648 
00649     uint16_t  prev_shadow_result__mm_inner_actual_effective_spads_sd0;
00650 
00651     uint16_t  prev_shadow_result__mm_outer_actual_effective_spads_sd0;
00652 
00653     uint16_t  prev_shadow_result__avg_signal_count_rate_mcps_sd0;
00654 
00655     uint16_t  prev_shadow_result__dss_actual_effective_spads_sd1;
00656 
00657     uint16_t  prev_shadow_result__peak_signal_count_rate_mcps_sd1;
00658 
00659     uint16_t  prev_shadow_result__ambient_count_rate_mcps_sd1;
00660 
00661     uint16_t  prev_shadow_result__sigma_sd1;
00662 
00663     uint16_t  prev_shadow_result__phase_sd1;
00664 
00665     uint16_t  prev_shadow_result__final_crosstalk_corrected_range_mm_sd1;
00666 
00667     uint16_t  prev_shadow_result__spare_0_sd1;
00668 
00669     uint16_t  prev_shadow_result__spare_1_sd1;
00670 
00671     uint16_t  prev_shadow_result__spare_2_sd1;
00672 
00673     uint16_t  prev_shadow_result__spare_3_sd1;
00674 
00675 } VL53L1_prev_shadow_system_results_t;
00676 
00677 
00678 
00679 
00680 typedef struct {
00681     uint32_t  prev_shadow_result_core__ambient_window_events_sd0;
00682 
00683     uint32_t  prev_shadow_result_core__ranging_total_events_sd0;
00684 
00685     int32_t   prev_shadow_result_core__signal_total_events_sd0;
00686 
00687     uint32_t  prev_shadow_result_core__total_periods_elapsed_sd0;
00688 
00689     uint32_t  prev_shadow_result_core__ambient_window_events_sd1;
00690 
00691     uint32_t  prev_shadow_result_core__ranging_total_events_sd1;
00692 
00693     int32_t   prev_shadow_result_core__signal_total_events_sd1;
00694 
00695     uint32_t  prev_shadow_result_core__total_periods_elapsed_sd1;
00696 
00697     uint8_t   prev_shadow_result_core__spare_0;
00698 
00699 } VL53L1_prev_shadow_core_results_t;
00700 
00701 
00702 
00703 
00704 typedef struct {
00705     uint8_t   result__debug_status;
00706 
00707     uint8_t   result__debug_stage;
00708 
00709 } VL53L1_patch_debug_t;
00710 
00711 
00712 
00713 
00714 typedef struct {
00715     uint16_t  gph__system__thresh_rate_high;
00716 
00717     uint16_t  gph__system__thresh_rate_low;
00718 
00719     uint8_t   gph__system__interrupt_config_gpio;
00720 
00721 } VL53L1_gph_general_config_t;
00722 
00723 
00724 
00725 
00726 typedef struct {
00727     uint8_t   gph__dss_config__roi_mode_control;
00728 
00729     uint16_t  gph__dss_config__manual_effective_spads_select;
00730 
00731     uint8_t   gph__dss_config__manual_block_select;
00732 
00733     uint8_t   gph__dss_config__max_spads_limit;
00734 
00735     uint8_t   gph__dss_config__min_spads_limit;
00736 
00737 } VL53L1_gph_static_config_t;
00738 
00739 
00740 
00741 
00742 typedef struct {
00743     uint8_t   gph__mm_config__timeout_macrop_a_hi;
00744 
00745     uint8_t   gph__mm_config__timeout_macrop_a_lo;
00746 
00747     uint8_t   gph__mm_config__timeout_macrop_b_hi;
00748 
00749     uint8_t   gph__mm_config__timeout_macrop_b_lo;
00750 
00751     uint8_t   gph__range_config__timeout_macrop_a_hi;
00752 
00753     uint8_t   gph__range_config__timeout_macrop_a_lo;
00754 
00755     uint8_t   gph__range_config__vcsel_period_a;
00756 
00757     uint8_t   gph__range_config__vcsel_period_b;
00758 
00759     uint8_t   gph__range_config__timeout_macrop_b_hi;
00760 
00761     uint8_t   gph__range_config__timeout_macrop_b_lo;
00762 
00763     uint16_t  gph__range_config__sigma_thresh;
00764 
00765     uint16_t  gph__range_config__min_count_rate_rtn_limit_mcps;
00766 
00767     uint8_t   gph__range_config__valid_phase_low;
00768 
00769     uint8_t   gph__range_config__valid_phase_high;
00770 
00771 } VL53L1_gph_timing_config_t;
00772 
00773 
00774 
00775 
00776 typedef struct {
00777     uint8_t   firmware__internal_stream_count_div;
00778 
00779     uint8_t   firmware__internal_stream_counter_val;
00780 
00781 } VL53L1_fw_internal_t;
00782 
00783 
00784 
00785 
00786 typedef struct {
00787     uint8_t   dss_calc__roi_ctrl;
00788 
00789     uint8_t   dss_calc__spare_1;
00790 
00791     uint8_t   dss_calc__spare_2;
00792 
00793     uint8_t   dss_calc__spare_3;
00794 
00795     uint8_t   dss_calc__spare_4;
00796 
00797     uint8_t   dss_calc__spare_5;
00798 
00799     uint8_t   dss_calc__spare_6;
00800 
00801     uint8_t   dss_calc__spare_7;
00802 
00803     uint8_t   dss_calc__user_roi_spad_en_0;
00804 
00805     uint8_t   dss_calc__user_roi_spad_en_1;
00806 
00807     uint8_t   dss_calc__user_roi_spad_en_2;
00808 
00809     uint8_t   dss_calc__user_roi_spad_en_3;
00810 
00811     uint8_t   dss_calc__user_roi_spad_en_4;
00812 
00813     uint8_t   dss_calc__user_roi_spad_en_5;
00814 
00815     uint8_t   dss_calc__user_roi_spad_en_6;
00816 
00817     uint8_t   dss_calc__user_roi_spad_en_7;
00818 
00819     uint8_t   dss_calc__user_roi_spad_en_8;
00820 
00821     uint8_t   dss_calc__user_roi_spad_en_9;
00822 
00823     uint8_t   dss_calc__user_roi_spad_en_10;
00824 
00825     uint8_t   dss_calc__user_roi_spad_en_11;
00826 
00827     uint8_t   dss_calc__user_roi_spad_en_12;
00828 
00829     uint8_t   dss_calc__user_roi_spad_en_13;
00830 
00831     uint8_t   dss_calc__user_roi_spad_en_14;
00832 
00833     uint8_t   dss_calc__user_roi_spad_en_15;
00834 
00835     uint8_t   dss_calc__user_roi_spad_en_16;
00836 
00837     uint8_t   dss_calc__user_roi_spad_en_17;
00838 
00839     uint8_t   dss_calc__user_roi_spad_en_18;
00840 
00841     uint8_t   dss_calc__user_roi_spad_en_19;
00842 
00843     uint8_t   dss_calc__user_roi_spad_en_20;
00844 
00845     uint8_t   dss_calc__user_roi_spad_en_21;
00846 
00847     uint8_t   dss_calc__user_roi_spad_en_22;
00848 
00849     uint8_t   dss_calc__user_roi_spad_en_23;
00850 
00851     uint8_t   dss_calc__user_roi_spad_en_24;
00852 
00853     uint8_t   dss_calc__user_roi_spad_en_25;
00854 
00855     uint8_t   dss_calc__user_roi_spad_en_26;
00856 
00857     uint8_t   dss_calc__user_roi_spad_en_27;
00858 
00859     uint8_t   dss_calc__user_roi_spad_en_28;
00860 
00861     uint8_t   dss_calc__user_roi_spad_en_29;
00862 
00863     uint8_t   dss_calc__user_roi_spad_en_30;
00864 
00865     uint8_t   dss_calc__user_roi_spad_en_31;
00866 
00867     uint8_t   dss_calc__user_roi_0;
00868 
00869     uint8_t   dss_calc__user_roi_1;
00870 
00871     uint8_t   dss_calc__mode_roi_0;
00872 
00873     uint8_t   dss_calc__mode_roi_1;
00874 
00875     uint8_t   sigma_estimator_calc__spare_0;
00876 
00877     uint16_t  vhv_result__peak_signal_rate_mcps;
00878 
00879     uint32_t  vhv_result__signal_total_events_ref;
00880 
00881     uint16_t  phasecal_result__phase_output_ref;
00882 
00883     uint16_t  dss_result__total_rate_per_spad;
00884 
00885     uint8_t   dss_result__enabled_blocks;
00886 
00887     uint16_t  dss_result__num_requested_spads;
00888 
00889     uint16_t  mm_result__inner_intersection_rate;
00890 
00891     uint16_t  mm_result__outer_complement_rate;
00892 
00893     uint16_t  mm_result__total_offset;
00894 
00895     uint32_t  xtalk_calc__xtalk_for_enabled_spads;
00896 
00897     uint32_t  xtalk_result__avg_xtalk_user_roi_kcps;
00898 
00899     uint32_t  xtalk_result__avg_xtalk_mm_inner_roi_kcps;
00900 
00901     uint32_t  xtalk_result__avg_xtalk_mm_outer_roi_kcps;
00902 
00903     uint32_t  range_result__accum_phase;
00904 
00905     uint16_t  range_result__offset_corrected_range;
00906 
00907 } VL53L1_patch_results_t;
00908 
00909 
00910 
00911 
00912 typedef struct {
00913     uint8_t   shadow_phasecal_result__vcsel_start;
00914 
00915     uint8_t   shadow_result__interrupt_status;
00916 
00917     uint8_t   shadow_result__range_status;
00918 
00919     uint8_t   shadow_result__report_status;
00920 
00921     uint8_t   shadow_result__stream_count;
00922 
00923     uint16_t  shadow_result__dss_actual_effective_spads_sd0;
00924 
00925     uint16_t  shadow_result__peak_signal_count_rate_mcps_sd0;
00926 
00927     uint16_t  shadow_result__ambient_count_rate_mcps_sd0;
00928 
00929     uint16_t  shadow_result__sigma_sd0;
00930 
00931     uint16_t  shadow_result__phase_sd0;
00932 
00933     uint16_t  shadow_result__final_crosstalk_corrected_range_mm_sd0;
00934 
00935     uint16_t
00936     shr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;
00937 
00938     uint16_t  shadow_result__mm_inner_actual_effective_spads_sd0;
00939 
00940     uint16_t  shadow_result__mm_outer_actual_effective_spads_sd0;
00941 
00942     uint16_t  shadow_result__avg_signal_count_rate_mcps_sd0;
00943 
00944     uint16_t  shadow_result__dss_actual_effective_spads_sd1;
00945 
00946     uint16_t  shadow_result__peak_signal_count_rate_mcps_sd1;
00947 
00948     uint16_t  shadow_result__ambient_count_rate_mcps_sd1;
00949 
00950     uint16_t  shadow_result__sigma_sd1;
00951 
00952     uint16_t  shadow_result__phase_sd1;
00953 
00954     uint16_t  shadow_result__final_crosstalk_corrected_range_mm_sd1;
00955 
00956     uint16_t  shadow_result__spare_0_sd1;
00957 
00958     uint16_t  shadow_result__spare_1_sd1;
00959 
00960     uint16_t  shadow_result__spare_2_sd1;
00961 
00962     uint8_t   shadow_result__spare_3_sd1;
00963 
00964     uint8_t   shadow_result__thresh_info;
00965 
00966     uint8_t   shadow_phasecal_result__reference_phase_hi;
00967 
00968     uint8_t   shadow_phasecal_result__reference_phase_lo;
00969 
00970 } VL53L1_shadow_system_results_t;
00971 
00972 
00973 
00974 
00975 typedef struct {
00976     uint32_t  shadow_result_core__ambient_window_events_sd0;
00977 
00978     uint32_t  shadow_result_core__ranging_total_events_sd0;
00979 
00980     int32_t   shadow_result_core__signal_total_events_sd0;
00981 
00982     uint32_t  shadow_result_core__total_periods_elapsed_sd0;
00983 
00984     uint32_t  shadow_result_core__ambient_window_events_sd1;
00985 
00986     uint32_t  shadow_result_core__ranging_total_events_sd1;
00987 
00988     int32_t   shadow_result_core__signal_total_events_sd1;
00989 
00990     uint32_t  shadow_result_core__total_periods_elapsed_sd1;
00991 
00992     uint8_t   shadow_result_core__spare_0;
00993 
00994 } VL53L1_shadow_core_results_t;
00995 
00996 
00997 #endif
00998 
00999