ST Expansion SW Team
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VL53L1
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Dependencies: X_NUCLEO_COMMON ST_INTERFACES
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vl53l1_register_map.h
00001 00002 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 00003 /****************************************************************************** 00004 * Copyright (c) 2020, STMicroelectronics - All Rights Reserved 00005 00006 This file is part of VL53L1 and is dual licensed, 00007 either GPL-2.0+ 00008 or 'BSD 3-clause "New" or "Revised" License' , at your option. 00009 ****************************************************************************** 00010 */ 00011 00012 00013 00014 00015 #ifndef _VL53L1_REGISTER_MAP_H_ 00016 #define _VL53L1_REGISTER_MAP_H_ 00017 00018 00019 00020 #define VL53L1_SOFT_RESET 0x0000 00021 00022 #define VL53L1_I2C_SLAVE__DEVICE_ADDRESS 0x0001 00023 00024 #define VL53L1_ANA_CONFIG__VHV_REF_SEL_VDDPIX 0x0002 00025 00026 #define VL53L1_ANA_CONFIG__VHV_REF_SEL_VQUENCH 0x0003 00027 00028 #define VL53L1_ANA_CONFIG__REG_AVDD1V2_SEL 0x0004 00029 00030 #define VL53L1_ANA_CONFIG__FAST_OSC__TRIM 0x0005 00031 00032 #define VL53L1_OSC_MEASURED__FAST_OSC__FREQUENCY 0x0006 00033 00034 #define VL53L1_OSC_MEASURED__FAST_OSC__FREQUENCY_HI 0x0006 00035 00036 #define VL53L1_OSC_MEASURED__FAST_OSC__FREQUENCY_LO 0x0007 00037 00038 #define VL53L1_VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND 0x0008 00039 00040 #define VL53L1_VHV_CONFIG__COUNT_THRESH 0x0009 00041 00042 #define VL53L1_VHV_CONFIG__OFFSET 0x000A 00043 00044 #define VL53L1_VHV_CONFIG__INIT 0x000B 00045 00046 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_0 0x000D 00047 00048 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_1 0x000E 00049 00050 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_2 0x000F 00051 00052 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_3 0x0010 00053 00054 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_4 0x0011 00055 00056 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_5 0x0012 00057 00058 #define VL53L1_GLOBAL_CONFIG__REF_EN_START_SELECT 0x0013 00059 00060 #define VL53L1_REF_SPAD_MAN__NUM_REQUESTED_REF_SPADS 0x0014 00061 00062 #define VL53L1_REF_SPAD_MAN__REF_LOCATION 0x0015 00063 00064 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x0016 00065 00066 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_HI 0x0016 00067 00068 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_LO 0x0017 00069 00070 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS 0x0018 00071 00072 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_HI 0x0018 00073 00074 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_LO 0x0019 00075 00076 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS 0x001A 00077 00078 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_HI 0x001A 00079 00080 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_LO 0x001B 00081 00082 #define VL53L1_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS 0x001C 00083 00084 #define VL53L1_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_HI 0x001C 00085 00086 #define VL53L1_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_LO 0x001D 00087 00088 #define VL53L1_ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x001E 00089 00090 #define VL53L1_ALGO__PART_TO_PART_RANGE_OFFSET_MM_HI 0x001E 00091 00092 #define VL53L1_ALGO__PART_TO_PART_RANGE_OFFSET_MM_LO 0x001F 00093 00094 #define VL53L1_MM_CONFIG__INNER_OFFSET_MM 0x0020 00095 00096 #define VL53L1_MM_CONFIG__INNER_OFFSET_MM_HI 0x0020 00097 00098 #define VL53L1_MM_CONFIG__INNER_OFFSET_MM_LO 0x0021 00099 00100 #define VL53L1_MM_CONFIG__OUTER_OFFSET_MM 0x0022 00101 00102 #define VL53L1_MM_CONFIG__OUTER_OFFSET_MM_HI 0x0022 00103 00104 #define VL53L1_MM_CONFIG__OUTER_OFFSET_MM_LO 0x0023 00105 00106 #define VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS 0x0024 00107 00108 #define VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_HI 0x0024 00109 00110 #define VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_LO 0x0025 00111 00112 #define VL53L1_DEBUG__CTRL 0x0026 00113 00114 #define VL53L1_TEST_MODE__CTRL 0x0027 00115 00116 #define VL53L1_CLK_GATING__CTRL 0x0028 00117 00118 #define VL53L1_NVM_BIST__CTRL 0x0029 00119 00120 #define VL53L1_NVM_BIST__NUM_NVM_WORDS 0x002A 00121 00122 #define VL53L1_NVM_BIST__START_ADDRESS 0x002B 00123 00124 #define VL53L1_HOST_IF__STATUS 0x002C 00125 00126 #define VL53L1_PAD_I2C_HV__CONFIG 0x002D 00127 00128 #define VL53L1_PAD_I2C_HV__EXTSUP_CONFIG 0x002E 00129 00130 #define VL53L1_GPIO_HV_PAD__CTRL 0x002F 00131 00132 #define VL53L1_GPIO_HV_MUX__CTRL 0x0030 00133 00134 #define VL53L1_GPIO__TIO_HV_STATUS 0x0031 00135 00136 #define VL53L1_GPIO__FIO_HV_STATUS 0x0032 00137 00138 #define VL53L1_ANA_CONFIG__SPAD_SEL_PSWIDTH 0x0033 00139 00140 #define VL53L1_ANA_CONFIG__VCSEL_PULSE_WIDTH_OFFSET 0x0034 00141 00142 #define VL53L1_ANA_CONFIG__FAST_OSC__CONFIG_CTRL 0x0035 00143 00144 #define VL53L1_SIGMA_ESTIMATOR__EFFECTIVE_PULSE_WIDTH_NS 0x0036 00145 00146 #define VL53L1_SIGMA_ESTIMATOR__EFFECTIVE_AMBIENT_WIDTH_NS 0x0037 00147 00148 #define VL53L1_SIGMA_ESTIMATOR__SIGMA_REF_MM 0x0038 00149 00150 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_VALID_HEIGHT_MM 0x0039 00151 00152 #define VL53L1_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_0 0x003A 00153 00154 #define VL53L1_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_1 0x003B 00155 00156 #define VL53L1_ALGO__RANGE_IGNORE_THRESHOLD_MCPS 0x003C 00157 00158 #define VL53L1_ALGO__RANGE_IGNORE_THRESHOLD_MCPS_HI 0x003C 00159 00160 #define VL53L1_ALGO__RANGE_IGNORE_THRESHOLD_MCPS_LO 0x003D 00161 00162 #define VL53L1_ALGO__RANGE_IGNORE_VALID_HEIGHT_MM 0x003E 00163 00164 #define VL53L1_ALGO__RANGE_MIN_CLIP 0x003F 00165 00166 #define VL53L1_ALGO__CONSISTENCY_CHECK__TOLERANCE 0x0040 00167 00168 #define VL53L1_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_2 0x0041 00169 00170 #define VL53L1_SD_CONFIG__RESET_STAGES_MSB 0x0042 00171 00172 #define VL53L1_SD_CONFIG__RESET_STAGES_LSB 0x0043 00173 00174 #define VL53L1_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE 0x0044 00175 00176 #define VL53L1_GLOBAL_CONFIG__STREAM_DIVIDER 0x0045 00177 00178 #define VL53L1_SYSTEM__INTERRUPT_CONFIG_GPIO 0x0046 00179 00180 #define VL53L1_CAL_CONFIG__VCSEL_START 0x0047 00181 00182 #define VL53L1_CAL_CONFIG__REPEAT_RATE 0x0048 00183 00184 #define VL53L1_CAL_CONFIG__REPEAT_RATE_HI 0x0048 00185 00186 #define VL53L1_CAL_CONFIG__REPEAT_RATE_LO 0x0049 00187 00188 #define VL53L1_GLOBAL_CONFIG__VCSEL_WIDTH 0x004A 00189 00190 #define VL53L1_PHASECAL_CONFIG__TIMEOUT_MACROP 0x004B 00191 00192 #define VL53L1_PHASECAL_CONFIG__TARGET 0x004C 00193 00194 #define VL53L1_PHASECAL_CONFIG__OVERRIDE 0x004D 00195 00196 #define VL53L1_DSS_CONFIG__ROI_MODE_CONTROL 0x004F 00197 00198 #define VL53L1_SYSTEM__THRESH_RATE_HIGH 0x0050 00199 00200 #define VL53L1_SYSTEM__THRESH_RATE_HIGH_HI 0x0050 00201 00202 #define VL53L1_SYSTEM__THRESH_RATE_HIGH_LO 0x0051 00203 00204 #define VL53L1_SYSTEM__THRESH_RATE_LOW 0x0052 00205 00206 #define VL53L1_SYSTEM__THRESH_RATE_LOW_HI 0x0052 00207 00208 #define VL53L1_SYSTEM__THRESH_RATE_LOW_LO 0x0053 00209 00210 #define VL53L1_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT 0x0054 00211 00212 #define VL53L1_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0054 00213 00214 #define VL53L1_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0055 00215 00216 #define VL53L1_DSS_CONFIG__MANUAL_BLOCK_SELECT 0x0056 00217 00218 #define VL53L1_DSS_CONFIG__APERTURE_ATTENUATION 0x0057 00219 00220 #define VL53L1_DSS_CONFIG__MAX_SPADS_LIMIT 0x0058 00221 00222 #define VL53L1_DSS_CONFIG__MIN_SPADS_LIMIT 0x0059 00223 00224 #define VL53L1_MM_CONFIG__TIMEOUT_MACROP_A_HI 0x005A 00225 00226 #define VL53L1_MM_CONFIG__TIMEOUT_MACROP_A_LO 0x005B 00227 00228 #define VL53L1_MM_CONFIG__TIMEOUT_MACROP_B_HI 0x005C 00229 00230 #define VL53L1_MM_CONFIG__TIMEOUT_MACROP_B_LO 0x005D 00231 00232 #define VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_A_HI 0x005E 00233 00234 #define VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_A_LO 0x005F 00235 00236 #define VL53L1_RANGE_CONFIG__VCSEL_PERIOD_A 0x0060 00237 00238 #define VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_B_HI 0x0061 00239 00240 #define VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_B_LO 0x0062 00241 00242 #define VL53L1_RANGE_CONFIG__VCSEL_PERIOD_B 0x0063 00243 00244 #define VL53L1_RANGE_CONFIG__SIGMA_THRESH 0x0064 00245 00246 #define VL53L1_RANGE_CONFIG__SIGMA_THRESH_HI 0x0064 00247 00248 #define VL53L1_RANGE_CONFIG__SIGMA_THRESH_LO 0x0065 00249 00250 #define VL53L1_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0066 00251 00252 #define VL53L1_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0066 00253 00254 #define VL53L1_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0067 00255 00256 #define VL53L1_RANGE_CONFIG__VALID_PHASE_LOW 0x0068 00257 00258 #define VL53L1_RANGE_CONFIG__VALID_PHASE_HIGH 0x0069 00259 00260 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD 0x006C 00261 00262 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD_3 0x006C 00263 00264 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD_2 0x006D 00265 00266 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD_1 0x006E 00267 00268 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD_0 0x006F 00269 00270 #define VL53L1_SYSTEM__FRACTIONAL_ENABLE 0x0070 00271 00272 #define VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD_0 0x0071 00273 00274 #define VL53L1_SYSTEM__THRESH_HIGH 0x0072 00275 00276 #define VL53L1_SYSTEM__THRESH_HIGH_HI 0x0072 00277 00278 #define VL53L1_SYSTEM__THRESH_HIGH_LO 0x0073 00279 00280 #define VL53L1_SYSTEM__THRESH_LOW 0x0074 00281 00282 #define VL53L1_SYSTEM__THRESH_LOW_HI 0x0074 00283 00284 #define VL53L1_SYSTEM__THRESH_LOW_LO 0x0075 00285 00286 #define VL53L1_SYSTEM__ENABLE_XTALK_PER_QUADRANT 0x0076 00287 00288 #define VL53L1_SYSTEM__SEED_CONFIG 0x0077 00289 00290 #define VL53L1_SD_CONFIG__WOI_SD0 0x0078 00291 00292 #define VL53L1_SD_CONFIG__WOI_SD1 0x0079 00293 00294 #define VL53L1_SD_CONFIG__INITIAL_PHASE_SD0 0x007A 00295 00296 #define VL53L1_SD_CONFIG__INITIAL_PHASE_SD1 0x007B 00297 00298 #define VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD_1 0x007C 00299 00300 #define VL53L1_SD_CONFIG__FIRST_ORDER_SELECT 0x007D 00301 00302 #define VL53L1_SD_CONFIG__QUANTIFIER 0x007E 00303 00304 #define VL53L1_ROI_CONFIG__USER_ROI_CENTRE_SPAD 0x007F 00305 00306 #define VL53L1_ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x0080 00307 00308 #define VL53L1_SYSTEM__SEQUENCE_CONFIG 0x0081 00309 00310 #define VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD 0x0082 00311 00312 #define VL53L1_POWER_MANAGEMENT__GO1_POWER_FORCE 0x0083 00313 00314 #define VL53L1_SYSTEM__STREAM_COUNT_CTRL 0x0084 00315 00316 #define VL53L1_FIRMWARE__ENABLE 0x0085 00317 00318 #define VL53L1_SYSTEM__INTERRUPT_CLEAR 0x0086 00319 00320 #define VL53L1_SYSTEM__MODE_START 0x0087 00321 00322 #define VL53L1_RESULT__INTERRUPT_STATUS 0x0088 00323 00324 #define VL53L1_RESULT__RANGE_STATUS 0x0089 00325 00326 #define VL53L1_RESULT__REPORT_STATUS 0x008A 00327 00328 #define VL53L1_RESULT__STREAM_COUNT 0x008B 00329 00330 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x008C 00331 00332 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x008C 00333 00334 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x008D 00335 00336 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x008E 00337 00338 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x008E 00339 00340 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x008F 00341 00342 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0090 00343 00344 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0090 00345 00346 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0091 00347 00348 #define VL53L1_RESULT__SIGMA_SD0 0x0092 00349 00350 #define VL53L1_RESULT__SIGMA_SD0_HI 0x0092 00351 00352 #define VL53L1_RESULT__SIGMA_SD0_LO 0x0093 00353 00354 #define VL53L1_RESULT__PHASE_SD0 0x0094 00355 00356 #define VL53L1_RESULT__PHASE_SD0_HI 0x0094 00357 00358 #define VL53L1_RESULT__PHASE_SD0_LO 0x0095 00359 00360 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0096 00361 00362 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0096 00363 00364 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0097 00365 00366 #define VL53L1_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0098 00367 00368 #define VL53L1__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0098 00369 00370 #define VL53L1___PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0099 00371 00372 #define VL53L1_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x009A 00373 00374 #define VL53L1_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x009A 00375 00376 #define VL53L1_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x009B 00377 00378 #define VL53L1_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x009C 00379 00380 #define VL53L1_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x009C 00381 00382 #define VL53L1_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x009D 00383 00384 #define VL53L1_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x009E 00385 00386 #define VL53L1_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x009E 00387 00388 #define VL53L1_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x009F 00389 00390 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x00A0 00391 00392 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x00A0 00393 00394 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x00A1 00395 00396 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x00A2 00397 00398 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x00A2 00399 00400 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x00A3 00401 00402 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x00A4 00403 00404 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x00A4 00405 00406 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x00A5 00407 00408 #define VL53L1_RESULT__SIGMA_SD1 0x00A6 00409 00410 #define VL53L1_RESULT__SIGMA_SD1_HI 0x00A6 00411 00412 #define VL53L1_RESULT__SIGMA_SD1_LO 0x00A7 00413 00414 #define VL53L1_RESULT__PHASE_SD1 0x00A8 00415 00416 #define VL53L1_RESULT__PHASE_SD1_HI 0x00A8 00417 00418 #define VL53L1_RESULT__PHASE_SD1_LO 0x00A9 00419 00420 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x00AA 00421 00422 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x00AA 00423 00424 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x00AB 00425 00426 #define VL53L1_RESULT__SPARE_0_SD1 0x00AC 00427 00428 #define VL53L1_RESULT__SPARE_0_SD1_HI 0x00AC 00429 00430 #define VL53L1_RESULT__SPARE_0_SD1_LO 0x00AD 00431 00432 #define VL53L1_RESULT__SPARE_1_SD1 0x00AE 00433 00434 #define VL53L1_RESULT__SPARE_1_SD1_HI 0x00AE 00435 00436 #define VL53L1_RESULT__SPARE_1_SD1_LO 0x00AF 00437 00438 #define VL53L1_RESULT__SPARE_2_SD1 0x00B0 00439 00440 #define VL53L1_RESULT__SPARE_2_SD1_HI 0x00B0 00441 00442 #define VL53L1_RESULT__SPARE_2_SD1_LO 0x00B1 00443 00444 #define VL53L1_RESULT__SPARE_3_SD1 0x00B2 00445 00446 #define VL53L1_RESULT__THRESH_INFO 0x00B3 00447 00448 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x00B4 00449 00450 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x00B4 00451 00452 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x00B5 00453 00454 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x00B6 00455 00456 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x00B7 00457 00458 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x00B8 00459 00460 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x00B8 00461 00462 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x00B9 00463 00464 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x00BA 00465 00466 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x00BB 00467 00468 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x00BC 00469 00470 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x00BC 00471 00472 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x00BD 00473 00474 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x00BE 00475 00476 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x00BF 00477 00478 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x00C0 00479 00480 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x00C0 00481 00482 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x00C1 00483 00484 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x00C2 00485 00486 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x00C3 00487 00488 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x00C4 00489 00490 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x00C4 00491 00492 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x00C5 00493 00494 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x00C6 00495 00496 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x00C7 00497 00498 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x00C8 00499 00500 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x00C8 00501 00502 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x00C9 00503 00504 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x00CA 00505 00506 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x00CB 00507 00508 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x00CC 00509 00510 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x00CC 00511 00512 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x00CD 00513 00514 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x00CE 00515 00516 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x00CF 00517 00518 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x00D0 00519 00520 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x00D0 00521 00522 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x00D1 00523 00524 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x00D2 00525 00526 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x00D3 00527 00528 #define VL53L1_RESULT_CORE__SPARE_0 0x00D4 00529 00530 #define VL53L1_PHASECAL_RESULT__REFERENCE_PHASE 0x00D6 00531 00532 #define VL53L1_PHASECAL_RESULT__REFERENCE_PHASE_HI 0x00D6 00533 00534 #define VL53L1_PHASECAL_RESULT__REFERENCE_PHASE_LO 0x00D7 00535 00536 #define VL53L1_PHASECAL_RESULT__VCSEL_START 0x00D8 00537 00538 #define VL53L1_REF_SPAD_CHAR_RESULT__NUM_ACTUAL_REF_SPADS 0x00D9 00539 00540 #define VL53L1_REF_SPAD_CHAR_RESULT__REF_LOCATION 0x00DA 00541 00542 #define VL53L1_VHV_RESULT__COLDBOOT_STATUS 0x00DB 00543 00544 #define VL53L1_VHV_RESULT__SEARCH_RESULT 0x00DC 00545 00546 #define VL53L1_VHV_RESULT__LATEST_SETTING 0x00DD 00547 00548 #define VL53L1_RESULT__OSC_CALIBRATE_VAL 0x00DE 00549 00550 #define VL53L1_RESULT__OSC_CALIBRATE_VAL_HI 0x00DE 00551 00552 #define VL53L1_RESULT__OSC_CALIBRATE_VAL_LO 0x00DF 00553 00554 #define VL53L1_ANA_CONFIG__POWERDOWN_GO1 0x00E0 00555 00556 #define VL53L1_ANA_CONFIG__REF_BG_CTRL 0x00E1 00557 00558 #define VL53L1_ANA_CONFIG__REGDVDD1V2_CTRL 0x00E2 00559 00560 #define VL53L1_ANA_CONFIG__OSC_SLOW_CTRL 0x00E3 00561 00562 #define VL53L1_TEST_MODE__STATUS 0x00E4 00563 00564 #define VL53L1_FIRMWARE__SYSTEM_STATUS 0x00E5 00565 00566 #define VL53L1_FIRMWARE__MODE_STATUS 0x00E6 00567 00568 #define VL53L1_FIRMWARE__SECONDARY_MODE_STATUS 0x00E7 00569 00570 #define VL53L1_FIRMWARE__CAL_REPEAT_RATE_COUNTER 0x00E8 00571 00572 #define VL53L1_FIRMWARE__CAL_REPEAT_RATE_COUNTER_HI 0x00E8 00573 00574 #define VL53L1_FIRMWARE__CAL_REPEAT_RATE_COUNTER_LO 0x00E9 00575 00576 #define VL53L1_FIRMWARE__HISTOGRAM_BIN 0x00EA 00577 00578 #define VL53L1_GPH__SYSTEM__THRESH_HIGH 0x00EC 00579 00580 #define VL53L1_GPH__SYSTEM__THRESH_HIGH_HI 0x00EC 00581 00582 #define VL53L1_GPH__SYSTEM__THRESH_HIGH_LO 0x00ED 00583 00584 #define VL53L1_GPH__SYSTEM__THRESH_LOW 0x00EE 00585 00586 #define VL53L1_GPH__SYSTEM__THRESH_LOW_HI 0x00EE 00587 00588 #define VL53L1_GPH__SYSTEM__THRESH_LOW_LO 0x00EF 00589 00590 #define VL53L1_GPH__SYSTEM__ENABLE_XTALK_PER_QUADRANT 0x00F0 00591 00592 #define VL53L1_GPH__SPARE_0 0x00F1 00593 00594 #define VL53L1_GPH__SD_CONFIG__WOI_SD0 0x00F2 00595 00596 #define VL53L1_GPH__SD_CONFIG__WOI_SD1 0x00F3 00597 00598 #define VL53L1_GPH__SD_CONFIG__INITIAL_PHASE_SD0 0x00F4 00599 00600 #define VL53L1_GPH__SD_CONFIG__INITIAL_PHASE_SD1 0x00F5 00601 00602 #define VL53L1_GPH__SD_CONFIG__FIRST_ORDER_SELECT 0x00F6 00603 00604 #define VL53L1_GPH__SD_CONFIG__QUANTIFIER 0x00F7 00605 00606 #define VL53L1_GPH__ROI_CONFIG__USER_ROI_CENTRE_SPAD 0x00F8 00607 00608 #define VL53L1_GPH__ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x00F9 00609 00610 #define VL53L1_GPH__SYSTEM__SEQUENCE_CONFIG 0x00FA 00611 00612 #define VL53L1_GPH__GPH_ID 0x00FB 00613 00614 #define VL53L1_SYSTEM__INTERRUPT_SET 0x00FC 00615 00616 #define VL53L1_INTERRUPT_MANAGER__ENABLES 0x00FD 00617 00618 #define VL53L1_INTERRUPT_MANAGER__CLEAR 0x00FE 00619 00620 #define VL53L1_INTERRUPT_MANAGER__STATUS 0x00FF 00621 00622 #define VL53L1_MCU_TO_HOST_BANK__WR_ACCESS_EN 0x0100 00623 00624 #define VL53L1_POWER_MANAGEMENT__GO1_RESET_STATUS 0x0101 00625 00626 #define VL53L1_PAD_STARTUP_MODE__VALUE_RO 0x0102 00627 00628 #define VL53L1_PAD_STARTUP_MODE__VALUE_CTRL 0x0103 00629 00630 #define VL53L1_PLL_PERIOD_US 0x0104 00631 00632 #define VL53L1_PLL_PERIOD_US_3 0x0104 00633 00634 #define VL53L1_PLL_PERIOD_US_2 0x0105 00635 00636 #define VL53L1_PLL_PERIOD_US_1 0x0106 00637 00638 #define VL53L1_PLL_PERIOD_US_0 0x0107 00639 00640 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT 0x0108 00641 00642 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT_3 0x0108 00643 00644 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT_2 0x0109 00645 00646 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT_1 0x010A 00647 00648 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT_0 0x010B 00649 00650 #define VL53L1_NVM_BIST__COMPLETE 0x010C 00651 00652 #define VL53L1_NVM_BIST__STATUS 0x010D 00653 00654 #define VL53L1_IDENTIFICATION__MODEL_ID 0x010F 00655 00656 #define VL53L1_IDENTIFICATION__MODULE_TYPE 0x0110 00657 00658 #define VL53L1_IDENTIFICATION__REVISION_ID 0x0111 00659 00660 #define VL53L1_IDENTIFICATION__MODULE_ID 0x0112 00661 00662 #define VL53L1_IDENTIFICATION__MODULE_ID_HI 0x0112 00663 00664 #define VL53L1_IDENTIFICATION__MODULE_ID_LO 0x0113 00665 00666 #define VL53L1_ANA_CONFIG__FAST_OSC__TRIM_MAX 0x0114 00667 00668 #define VL53L1_ANA_CONFIG__FAST_OSC__FREQ_SET 0x0115 00669 00670 #define VL53L1_ANA_CONFIG__VCSEL_TRIM 0x0116 00671 00672 #define VL53L1_ANA_CONFIG__VCSEL_SELION 0x0117 00673 00674 #define VL53L1_ANA_CONFIG__VCSEL_SELION_MAX 0x0118 00675 00676 #define VL53L1_PROTECTED_LASER_SAFETY__LOCK_BIT 0x0119 00677 00678 #define VL53L1_LASER_SAFETY__KEY 0x011A 00679 00680 #define VL53L1_LASER_SAFETY__KEY_RO 0x011B 00681 00682 #define VL53L1_LASER_SAFETY__CLIP 0x011C 00683 00684 #define VL53L1_LASER_SAFETY__MULT 0x011D 00685 00686 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_0 0x011E 00687 00688 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_1 0x011F 00689 00690 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_2 0x0120 00691 00692 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_3 0x0121 00693 00694 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_4 0x0122 00695 00696 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_5 0x0123 00697 00698 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_6 0x0124 00699 00700 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_7 0x0125 00701 00702 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_8 0x0126 00703 00704 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_9 0x0127 00705 00706 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_10 0x0128 00707 00708 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_11 0x0129 00709 00710 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_12 0x012A 00711 00712 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_13 0x012B 00713 00714 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_14 0x012C 00715 00716 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_15 0x012D 00717 00718 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_16 0x012E 00719 00720 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_17 0x012F 00721 00722 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_18 0x0130 00723 00724 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_19 0x0131 00725 00726 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_20 0x0132 00727 00728 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_21 0x0133 00729 00730 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_22 0x0134 00731 00732 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_23 0x0135 00733 00734 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_24 0x0136 00735 00736 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_25 0x0137 00737 00738 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_26 0x0138 00739 00740 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_27 0x0139 00741 00742 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_28 0x013A 00743 00744 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_29 0x013B 00745 00746 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_30 0x013C 00747 00748 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_31 0x013D 00749 00750 #define VL53L1_ROI_CONFIG__MODE_ROI_CENTRE_SPAD 0x013E 00751 00752 #define VL53L1_ROI_CONFIG__MODE_ROI_XY_SIZE 0x013F 00753 00754 #define VL53L1_GO2_HOST_BANK_ACCESS__OVERRIDE 0x0300 00755 00756 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND 0x0400 00757 00758 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND_3 0x0400 00759 00760 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND_2 0x0401 00761 00762 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND_1 0x0402 00763 00764 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND_0 0x0403 00765 00766 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER 0x0404 00767 00768 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER_3 0x0404 00769 00770 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER_2 0x0405 00771 00772 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER_1 0x0406 00773 00774 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER_0 0x0407 00775 00776 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI 0x0408 00777 00778 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI_3 0x0408 00779 00780 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI_2 0x0409 00781 00782 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI_1 0x040A 00783 00784 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI_0 0x040B 00785 00786 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO 0x040C 00787 00788 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO_3 0x040C 00789 00790 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO_2 0x040D 00791 00792 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO_1 0x040E 00793 00794 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO_0 0x040F 00795 00796 #define VL53L1_MCU_UTIL_MULTIPLIER__START 0x0410 00797 00798 #define VL53L1_MCU_UTIL_MULTIPLIER__STATUS 0x0411 00799 00800 #define VL53L1_MCU_UTIL_DIVIDER__START 0x0412 00801 00802 #define VL53L1_MCU_UTIL_DIVIDER__STATUS 0x0413 00803 00804 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND 0x0414 00805 00806 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND_3 0x0414 00807 00808 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND_2 0x0415 00809 00810 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND_1 0x0416 00811 00812 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND_0 0x0417 00813 00814 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR 0x0418 00815 00816 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR_3 0x0418 00817 00818 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR_2 0x0419 00819 00820 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR_1 0x041A 00821 00822 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR_0 0x041B 00823 00824 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT 0x041C 00825 00826 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT_3 0x041C 00827 00828 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT_2 0x041D 00829 00830 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT_1 0x041E 00831 00832 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT_0 0x041F 00833 00834 #define VL53L1_TIMER0__VALUE_IN 0x0420 00835 00836 #define VL53L1_TIMER0__VALUE_IN_3 0x0420 00837 00838 #define VL53L1_TIMER0__VALUE_IN_2 0x0421 00839 00840 #define VL53L1_TIMER0__VALUE_IN_1 0x0422 00841 00842 #define VL53L1_TIMER0__VALUE_IN_0 0x0423 00843 00844 #define VL53L1_TIMER1__VALUE_IN 0x0424 00845 00846 #define VL53L1_TIMER1__VALUE_IN_3 0x0424 00847 00848 #define VL53L1_TIMER1__VALUE_IN_2 0x0425 00849 00850 #define VL53L1_TIMER1__VALUE_IN_1 0x0426 00851 00852 #define VL53L1_TIMER1__VALUE_IN_0 0x0427 00853 00854 #define VL53L1_TIMER0__CTRL 0x0428 00855 00856 #define VL53L1_TIMER1__CTRL 0x0429 00857 00858 #define VL53L1_MCU_GENERAL_PURPOSE__GP_0 0x042C 00859 00860 #define VL53L1_MCU_GENERAL_PURPOSE__GP_1 0x042D 00861 00862 #define VL53L1_MCU_GENERAL_PURPOSE__GP_2 0x042E 00863 00864 #define VL53L1_MCU_GENERAL_PURPOSE__GP_3 0x042F 00865 00866 #define VL53L1_MCU_RANGE_CALC__CONFIG 0x0430 00867 00868 #define VL53L1_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE 0x0432 00869 00870 #define VL53L1_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_HI 0x0432 00871 00872 #define VL53L1_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_LO 0x0433 00873 00874 #define VL53L1_MCU_RANGE_CALC__SPARE_4 0x0434 00875 00876 #define VL53L1_MCU_RANGE_CALC__SPARE_4_3 0x0434 00877 00878 #define VL53L1_MCU_RANGE_CALC__SPARE_4_2 0x0435 00879 00880 #define VL53L1_MCU_RANGE_CALC__SPARE_4_1 0x0436 00881 00882 #define VL53L1_MCU_RANGE_CALC__SPARE_4_0 0x0437 00883 00884 #define VL53L1_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC 0x0438 00885 00886 #define VL53L1_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_HI 0x0438 00887 00888 #define VL53L1_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_LO 0x0439 00889 00890 #define VL53L1_MCU_RANGE_CALC__ALGO_VCSEL_PERIOD 0x043C 00891 00892 #define VL53L1_MCU_RANGE_CALC__SPARE_5 0x043D 00893 00894 #define VL53L1_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS 0x043E 00895 00896 #define VL53L1_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_HI 0x043E 00897 00898 #define VL53L1_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_LO 0x043F 00899 00900 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE 0x0440 00901 00902 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_3 0x0440 00903 00904 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_2 0x0441 00905 00906 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_1 0x0442 00907 00908 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_0 0x0443 00909 00910 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS 0x0444 00911 00912 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_3 0x0444 00913 00914 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_2 0x0445 00915 00916 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_1 0x0446 00917 00918 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_0 0x0447 00919 00920 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS 0x0448 00921 00922 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_3 0x0448 00923 00924 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_2 0x0449 00925 00926 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_1 0x044A 00927 00928 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_0 0x044B 00929 00930 #define VL53L1_MCU_RANGE_CALC__SPARE_6 0x044C 00931 00932 #define VL53L1_MCU_RANGE_CALC__SPARE_6_HI 0x044C 00933 00934 #define VL53L1_MCU_RANGE_CALC__SPARE_6_LO 0x044D 00935 00936 #define VL53L1_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD 0x044E 00937 00938 #define VL53L1_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_HI 0x044E 00939 00940 #define VL53L1_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_LO 0x044F 00941 00942 #define VL53L1_MCU_RANGE_CALC__NUM_SPADS 0x0450 00943 00944 #define VL53L1_MCU_RANGE_CALC__NUM_SPADS_HI 0x0450 00945 00946 #define VL53L1_MCU_RANGE_CALC__NUM_SPADS_LO 0x0451 00947 00948 #define VL53L1_MCU_RANGE_CALC__PHASE_OUTPUT 0x0452 00949 00950 #define VL53L1_MCU_RANGE_CALC__PHASE_OUTPUT_HI 0x0452 00951 00952 #define VL53L1_MCU_RANGE_CALC__PHASE_OUTPUT_LO 0x0453 00953 00954 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS 0x0454 00955 00956 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_3 0x0454 00957 00958 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_2 0x0455 00959 00960 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_1 0x0456 00961 00962 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_0 0x0457 00963 00964 #define VL53L1_MCU_RANGE_CALC__SPARE_7 0x0458 00965 00966 #define VL53L1_MCU_RANGE_CALC__SPARE_8 0x0459 00967 00968 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS 0x045A 00969 00970 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_HI 0x045A 00971 00972 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_LO 0x045B 00973 00974 #define VL53L1_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS 0x045C 00975 00976 #define VL53L1_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_HI 0x045C 00977 00978 #define VL53L1_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_LO 0x045D 00979 00980 #define VL53L1_MCU_RANGE_CALC__AMBIENT_RATE_MCPS 0x045E 00981 00982 #define VL53L1_MCU_RANGE_CALC__AMBIENT_RATE_MCPS_HI 0x045E 00983 00984 #define VL53L1_MCU_RANGE_CALC__AMBIENT_RATE_MCPS_LO 0x045F 00985 00986 #define VL53L1_MCU_RANGE_CALC__XTALK 0x0460 00987 00988 #define VL53L1_MCU_RANGE_CALC__XTALK_HI 0x0460 00989 00990 #define VL53L1_MCU_RANGE_CALC__XTALK_LO 0x0461 00991 00992 #define VL53L1_MCU_RANGE_CALC__CALC_STATUS 0x0462 00993 00994 #define VL53L1_MCU_RANGE_CALC__DEBUG 0x0463 00995 00996 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS 0x0464 00997 00998 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_HI 0x0464 00999 01000 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_LO 0x0465 01001 01002 #define VL53L1_MCU_RANGE_CALC__SPARE_0 0x0468 01003 01004 #define VL53L1_MCU_RANGE_CALC__SPARE_1 0x0469 01005 01006 #define VL53L1_MCU_RANGE_CALC__SPARE_2 0x046A 01007 01008 #define VL53L1_MCU_RANGE_CALC__SPARE_3 0x046B 01009 01010 #define VL53L1_PATCH__CTRL 0x0470 01011 01012 #define VL53L1_PATCH__JMP_ENABLES 0x0472 01013 01014 #define VL53L1_PATCH__JMP_ENABLES_HI 0x0472 01015 01016 #define VL53L1_PATCH__JMP_ENABLES_LO 0x0473 01017 01018 #define VL53L1_PATCH__DATA_ENABLES 0x0474 01019 01020 #define VL53L1_PATCH__DATA_ENABLES_HI 0x0474 01021 01022 #define VL53L1_PATCH__DATA_ENABLES_LO 0x0475 01023 01024 #define VL53L1_PATCH__OFFSET_0 0x0476 01025 01026 #define VL53L1_PATCH__OFFSET_0_HI 0x0476 01027 01028 #define VL53L1_PATCH__OFFSET_0_LO 0x0477 01029 01030 #define VL53L1_PATCH__OFFSET_1 0x0478 01031 01032 #define VL53L1_PATCH__OFFSET_1_HI 0x0478 01033 01034 #define VL53L1_PATCH__OFFSET_1_LO 0x0479 01035 01036 #define VL53L1_PATCH__OFFSET_2 0x047A 01037 01038 #define VL53L1_PATCH__OFFSET_2_HI 0x047A 01039 01040 #define VL53L1_PATCH__OFFSET_2_LO 0x047B 01041 01042 #define VL53L1_PATCH__OFFSET_3 0x047C 01043 01044 #define VL53L1_PATCH__OFFSET_3_HI 0x047C 01045 01046 #define VL53L1_PATCH__OFFSET_3_LO 0x047D 01047 01048 #define VL53L1_PATCH__OFFSET_4 0x047E 01049 01050 #define VL53L1_PATCH__OFFSET_4_HI 0x047E 01051 01052 #define VL53L1_PATCH__OFFSET_4_LO 0x047F 01053 01054 #define VL53L1_PATCH__OFFSET_5 0x0480 01055 01056 #define VL53L1_PATCH__OFFSET_5_HI 0x0480 01057 01058 #define VL53L1_PATCH__OFFSET_5_LO 0x0481 01059 01060 #define VL53L1_PATCH__OFFSET_6 0x0482 01061 01062 #define VL53L1_PATCH__OFFSET_6_HI 0x0482 01063 01064 #define VL53L1_PATCH__OFFSET_6_LO 0x0483 01065 01066 #define VL53L1_PATCH__OFFSET_7 0x0484 01067 01068 #define VL53L1_PATCH__OFFSET_7_HI 0x0484 01069 01070 #define VL53L1_PATCH__OFFSET_7_LO 0x0485 01071 01072 #define VL53L1_PATCH__OFFSET_8 0x0486 01073 01074 #define VL53L1_PATCH__OFFSET_8_HI 0x0486 01075 01076 #define VL53L1_PATCH__OFFSET_8_LO 0x0487 01077 01078 #define VL53L1_PATCH__OFFSET_9 0x0488 01079 01080 #define VL53L1_PATCH__OFFSET_9_HI 0x0488 01081 01082 #define VL53L1_PATCH__OFFSET_9_LO 0x0489 01083 01084 #define VL53L1_PATCH__OFFSET_10 0x048A 01085 01086 #define VL53L1_PATCH__OFFSET_10_HI 0x048A 01087 01088 #define VL53L1_PATCH__OFFSET_10_LO 0x048B 01089 01090 #define VL53L1_PATCH__OFFSET_11 0x048C 01091 01092 #define VL53L1_PATCH__OFFSET_11_HI 0x048C 01093 01094 #define VL53L1_PATCH__OFFSET_11_LO 0x048D 01095 01096 #define VL53L1_PATCH__OFFSET_12 0x048E 01097 01098 #define VL53L1_PATCH__OFFSET_12_HI 0x048E 01099 01100 #define VL53L1_PATCH__OFFSET_12_LO 0x048F 01101 01102 #define VL53L1_PATCH__OFFSET_13 0x0490 01103 01104 #define VL53L1_PATCH__OFFSET_13_HI 0x0490 01105 01106 #define VL53L1_PATCH__OFFSET_13_LO 0x0491 01107 01108 #define VL53L1_PATCH__OFFSET_14 0x0492 01109 01110 #define VL53L1_PATCH__OFFSET_14_HI 0x0492 01111 01112 #define VL53L1_PATCH__OFFSET_14_LO 0x0493 01113 01114 #define VL53L1_PATCH__OFFSET_15 0x0494 01115 01116 #define VL53L1_PATCH__OFFSET_15_HI 0x0494 01117 01118 #define VL53L1_PATCH__OFFSET_15_LO 0x0495 01119 01120 #define VL53L1_PATCH__ADDRESS_0 0x0496 01121 01122 #define VL53L1_PATCH__ADDRESS_0_HI 0x0496 01123 01124 #define VL53L1_PATCH__ADDRESS_0_LO 0x0497 01125 01126 #define VL53L1_PATCH__ADDRESS_1 0x0498 01127 01128 #define VL53L1_PATCH__ADDRESS_1_HI 0x0498 01129 01130 #define VL53L1_PATCH__ADDRESS_1_LO 0x0499 01131 01132 #define VL53L1_PATCH__ADDRESS_2 0x049A 01133 01134 #define VL53L1_PATCH__ADDRESS_2_HI 0x049A 01135 01136 #define VL53L1_PATCH__ADDRESS_2_LO 0x049B 01137 01138 #define VL53L1_PATCH__ADDRESS_3 0x049C 01139 01140 #define VL53L1_PATCH__ADDRESS_3_HI 0x049C 01141 01142 #define VL53L1_PATCH__ADDRESS_3_LO 0x049D 01143 01144 #define VL53L1_PATCH__ADDRESS_4 0x049E 01145 01146 #define VL53L1_PATCH__ADDRESS_4_HI 0x049E 01147 01148 #define VL53L1_PATCH__ADDRESS_4_LO 0x049F 01149 01150 #define VL53L1_PATCH__ADDRESS_5 0x04A0 01151 01152 #define VL53L1_PATCH__ADDRESS_5_HI 0x04A0 01153 01154 #define VL53L1_PATCH__ADDRESS_5_LO 0x04A1 01155 01156 #define VL53L1_PATCH__ADDRESS_6 0x04A2 01157 01158 #define VL53L1_PATCH__ADDRESS_6_HI 0x04A2 01159 01160 #define VL53L1_PATCH__ADDRESS_6_LO 0x04A3 01161 01162 #define VL53L1_PATCH__ADDRESS_7 0x04A4 01163 01164 #define VL53L1_PATCH__ADDRESS_7_HI 0x04A4 01165 01166 #define VL53L1_PATCH__ADDRESS_7_LO 0x04A5 01167 01168 #define VL53L1_PATCH__ADDRESS_8 0x04A6 01169 01170 #define VL53L1_PATCH__ADDRESS_8_HI 0x04A6 01171 01172 #define VL53L1_PATCH__ADDRESS_8_LO 0x04A7 01173 01174 #define VL53L1_PATCH__ADDRESS_9 0x04A8 01175 01176 #define VL53L1_PATCH__ADDRESS_9_HI 0x04A8 01177 01178 #define VL53L1_PATCH__ADDRESS_9_LO 0x04A9 01179 01180 #define VL53L1_PATCH__ADDRESS_10 0x04AA 01181 01182 #define VL53L1_PATCH__ADDRESS_10_HI 0x04AA 01183 01184 #define VL53L1_PATCH__ADDRESS_10_LO 0x04AB 01185 01186 #define VL53L1_PATCH__ADDRESS_11 0x04AC 01187 01188 #define VL53L1_PATCH__ADDRESS_11_HI 0x04AC 01189 01190 #define VL53L1_PATCH__ADDRESS_11_LO 0x04AD 01191 01192 #define VL53L1_PATCH__ADDRESS_12 0x04AE 01193 01194 #define VL53L1_PATCH__ADDRESS_12_HI 0x04AE 01195 01196 #define VL53L1_PATCH__ADDRESS_12_LO 0x04AF 01197 01198 #define VL53L1_PATCH__ADDRESS_13 0x04B0 01199 01200 #define VL53L1_PATCH__ADDRESS_13_HI 0x04B0 01201 01202 #define VL53L1_PATCH__ADDRESS_13_LO 0x04B1 01203 01204 #define VL53L1_PATCH__ADDRESS_14 0x04B2 01205 01206 #define VL53L1_PATCH__ADDRESS_14_HI 0x04B2 01207 01208 #define VL53L1_PATCH__ADDRESS_14_LO 0x04B3 01209 01210 #define VL53L1_PATCH__ADDRESS_15 0x04B4 01211 01212 #define VL53L1_PATCH__ADDRESS_15_HI 0x04B4 01213 01214 #define VL53L1_PATCH__ADDRESS_15_LO 0x04B5 01215 01216 #define VL53L1_SPI_ASYNC_MUX__CTRL 0x04C0 01217 01218 #define VL53L1_CLK__CONFIG 0x04C4 01219 01220 #define VL53L1_GPIO_LV_MUX__CTRL 0x04CC 01221 01222 #define VL53L1_GPIO_LV_PAD__CTRL 0x04CD 01223 01224 #define VL53L1_PAD_I2C_LV__CONFIG 0x04D0 01225 01226 #define VL53L1_PAD_STARTUP_MODE__VALUE_RO_GO1 0x04D4 01227 01228 #define VL53L1_HOST_IF__STATUS_GO1 0x04D5 01229 01230 #define VL53L1_MCU_CLK_GATING__CTRL 0x04D8 01231 01232 #define VL53L1_TEST__BIST_ROM_CTRL 0x04E0 01233 01234 #define VL53L1_TEST__BIST_ROM_RESULT 0x04E1 01235 01236 #define VL53L1_TEST__BIST_ROM_MCU_SIG 0x04E2 01237 01238 #define VL53L1_TEST__BIST_ROM_MCU_SIG_HI 0x04E2 01239 01240 #define VL53L1_TEST__BIST_ROM_MCU_SIG_LO 0x04E3 01241 01242 #define VL53L1_TEST__BIST_RAM_CTRL 0x04E4 01243 01244 #define VL53L1_TEST__BIST_RAM_RESULT 0x04E5 01245 01246 #define VL53L1_TEST__TMC 0x04E8 01247 01248 #define VL53L1_TEST__PLL_BIST_MIN_THRESHOLD 0x04F0 01249 01250 #define VL53L1_TEST__PLL_BIST_MIN_THRESHOLD_HI 0x04F0 01251 01252 #define VL53L1_TEST__PLL_BIST_MIN_THRESHOLD_LO 0x04F1 01253 01254 #define VL53L1_TEST__PLL_BIST_MAX_THRESHOLD 0x04F2 01255 01256 #define VL53L1_TEST__PLL_BIST_MAX_THRESHOLD_HI 0x04F2 01257 01258 #define VL53L1_TEST__PLL_BIST_MAX_THRESHOLD_LO 0x04F3 01259 01260 #define VL53L1_TEST__PLL_BIST_COUNT_OUT 0x04F4 01261 01262 #define VL53L1_TEST__PLL_BIST_COUNT_OUT_HI 0x04F4 01263 01264 #define VL53L1_TEST__PLL_BIST_COUNT_OUT_LO 0x04F5 01265 01266 #define VL53L1_TEST__PLL_BIST_GONOGO 0x04F6 01267 01268 #define VL53L1_TEST__PLL_BIST_CTRL 0x04F7 01269 01270 #define VL53L1_RANGING_CORE__DEVICE_ID 0x0680 01271 01272 #define VL53L1_RANGING_CORE__REVISION_ID 0x0681 01273 01274 #define VL53L1_RANGING_CORE__CLK_CTRL1 0x0683 01275 01276 #define VL53L1_RANGING_CORE__CLK_CTRL2 0x0684 01277 01278 #define VL53L1_RANGING_CORE__WOI_1 0x0685 01279 01280 #define VL53L1_RANGING_CORE__WOI_REF_1 0x0686 01281 01282 #define VL53L1_RANGING_CORE__START_RANGING 0x0687 01283 01284 #define VL53L1_RANGING_CORE__LOW_LIMIT_1 0x0690 01285 01286 #define VL53L1_RANGING_CORE__HIGH_LIMIT_1 0x0691 01287 01288 #define VL53L1_RANGING_CORE__LOW_LIMIT_REF_1 0x0692 01289 01290 #define VL53L1_RANGING_CORE__HIGH_LIMIT_REF_1 0x0693 01291 01292 #define VL53L1_RANGING_CORE__QUANTIFIER_1_MSB 0x0694 01293 01294 #define VL53L1_RANGING_CORE__QUANTIFIER_1_LSB 0x0695 01295 01296 #define VL53L1_RANGING_CORE__QUANTIFIER_REF_1_MSB 0x0696 01297 01298 #define VL53L1_RANGING_CORE__QUANTIFIER_REF_1_LSB 0x0697 01299 01300 #define VL53L1_RANGING_CORE__AMBIENT_OFFSET_1_MSB 0x0698 01301 01302 #define VL53L1_RANGING_CORE__AMBIENT_OFFSET_1_LSB 0x0699 01303 01304 #define VL53L1_RANGING_CORE__AMBIENT_OFFSET_REF_1_MSB 0x069A 01305 01306 #define VL53L1_RANGING_CORE__AMBIENT_OFFSET_REF_1_LSB 0x069B 01307 01308 #define VL53L1_RANGING_CORE__FILTER_STRENGTH_1 0x069C 01309 01310 #define VL53L1_RANGING_CORE__FILTER_STRENGTH_REF_1 0x069D 01311 01312 #define VL53L1_RANGING_CORE__SIGNAL_EVENT_LIMIT_1_MSB 0x069E 01313 01314 #define VL53L1_RANGING_CORE__SIGNAL_EVENT_LIMIT_1_LSB 0x069F 01315 01316 #define VL53L1_RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_MSB 0x06A0 01317 01318 #define VL53L1_RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_LSB 0x06A1 01319 01320 #define VL53L1_RANGING_CORE__TIMEOUT_OVERALL_PERIODS_MSB 0x06A4 01321 01322 #define VL53L1_RANGING_CORE__TIMEOUT_OVERALL_PERIODS_LSB 0x06A5 01323 01324 #define VL53L1_RANGING_CORE__INVERT_HW 0x06A6 01325 01326 #define VL53L1_RANGING_CORE__FORCE_HW 0x06A7 01327 01328 #define VL53L1_RANGING_CORE__STATIC_HW_VALUE 0x06A8 01329 01330 #define VL53L1_RANGING_CORE__FORCE_CONTINUOUS_AMBIENT 0x06A9 01331 01332 #define VL53L1_RANGING_CORE__TEST_PHASE_SELECT_TO_FILTER 0x06AA 01333 01334 #define VL53L1_RANGING_CORE__TEST_PHASE_SELECT_TO_TIMING_GEN 0x06AB 01335 01336 #define VL53L1_RANGING_CORE__INITIAL_PHASE_VALUE_1 0x06AC 01337 01338 #define VL53L1_RANGING_CORE__INITIAL_PHASE_VALUE_REF_1 0x06AD 01339 01340 #define VL53L1_RANGING_CORE__FORCE_UP_IN 0x06AE 01341 01342 #define VL53L1_RANGING_CORE__FORCE_DN_IN 0x06AF 01343 01344 #define VL53L1_RANGING_CORE__STATIC_UP_VALUE_1 0x06B0 01345 01346 #define VL53L1_RANGING_CORE__STATIC_UP_VALUE_REF_1 0x06B1 01347 01348 #define VL53L1_RANGING_CORE__STATIC_DN_VALUE_1 0x06B2 01349 01350 #define VL53L1_RANGING_CORE__STATIC_DN_VALUE_REF_1 0x06B3 01351 01352 #define VL53L1_RANGING_CORE__MONITOR_UP_DN 0x06B4 01353 01354 #define VL53L1_RANGING_CORE__INVERT_UP_DN 0x06B5 01355 01356 #define VL53L1_RANGING_CORE__CPUMP_1 0x06B6 01357 01358 #define VL53L1_RANGING_CORE__CPUMP_2 0x06B7 01359 01360 #define VL53L1_RANGING_CORE__CPUMP_3 0x06B8 01361 01362 #define VL53L1_RANGING_CORE__OSC_1 0x06B9 01363 01364 #define VL53L1_RANGING_CORE__PLL_1 0x06BB 01365 01366 #define VL53L1_RANGING_CORE__PLL_2 0x06BC 01367 01368 #define VL53L1_RANGING_CORE__REFERENCE_1 0x06BD 01369 01370 #define VL53L1_RANGING_CORE__REFERENCE_3 0x06BF 01371 01372 #define VL53L1_RANGING_CORE__REFERENCE_4 0x06C0 01373 01374 #define VL53L1_RANGING_CORE__REFERENCE_5 0x06C1 01375 01376 #define VL53L1_RANGING_CORE__REGAVDD1V2 0x06C3 01377 01378 #define VL53L1_RANGING_CORE__CALIB_1 0x06C4 01379 01380 #define VL53L1_RANGING_CORE__CALIB_2 0x06C5 01381 01382 #define VL53L1_RANGING_CORE__CALIB_3 0x06C6 01383 01384 #define VL53L1_RANGING_CORE__TST_MUX_SEL1 0x06C9 01385 01386 #define VL53L1_RANGING_CORE__TST_MUX_SEL2 0x06CA 01387 01388 #define VL53L1_RANGING_CORE__TST_MUX 0x06CB 01389 01390 #define VL53L1_RANGING_CORE__GPIO_OUT_TESTMUX 0x06CC 01391 01392 #define VL53L1_RANGING_CORE__CUSTOM_FE 0x06CD 01393 01394 #define VL53L1_RANGING_CORE__CUSTOM_FE_2 0x06CE 01395 01396 #define VL53L1_RANGING_CORE__SPAD_READOUT 0x06CF 01397 01398 #define VL53L1_RANGING_CORE__SPAD_READOUT_1 0x06D0 01399 01400 #define VL53L1_RANGING_CORE__SPAD_READOUT_2 0x06D1 01401 01402 #define VL53L1_RANGING_CORE__SPAD_PS 0x06D2 01403 01404 #define VL53L1_RANGING_CORE__LASER_SAFETY_2 0x06D4 01405 01406 #define VL53L1_RANGING_CORE__NVM_CTRL__MODE 0x0780 01407 01408 #define VL53L1_RANGING_CORE__NVM_CTRL__PDN 0x0781 01409 01410 #define VL53L1_RANGING_CORE__NVM_CTRL__PROGN 0x0782 01411 01412 #define VL53L1_RANGING_CORE__NVM_CTRL__READN 0x0783 01413 01414 #define VL53L1_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_MSB 0x0784 01415 01416 #define VL53L1_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_LSB 0x0785 01417 01418 #define VL53L1_RANGING_CORE__NVM_CTRL__HV_RISE_MSB 0x0786 01419 01420 #define VL53L1_RANGING_CORE__NVM_CTRL__HV_RISE_LSB 0x0787 01421 01422 #define VL53L1_RANGING_CORE__NVM_CTRL__HV_FALL_MSB 0x0788 01423 01424 #define VL53L1_RANGING_CORE__NVM_CTRL__HV_FALL_LSB 0x0789 01425 01426 #define VL53L1_RANGING_CORE__NVM_CTRL__TST 0x078A 01427 01428 #define VL53L1_RANGING_CORE__NVM_CTRL__TESTREAD 0x078B 01429 01430 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAIN_MMM 0x078C 01431 01432 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAIN_LMM 0x078D 01433 01434 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAIN_LLM 0x078E 01435 01436 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAIN_LLL 0x078F 01437 01438 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_MMM 0x0790 01439 01440 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_LMM 0x0791 01441 01442 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_LLM 0x0792 01443 01444 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_LLL 0x0793 01445 01446 #define VL53L1_RANGING_CORE__NVM_CTRL__ADDR 0x0794 01447 01448 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_ECC 0x0795 01449 01450 #define VL53L1_RANGING_CORE__RET_SPAD_EN_0 0x0796 01451 01452 #define VL53L1_RANGING_CORE__RET_SPAD_EN_1 0x0797 01453 01454 #define VL53L1_RANGING_CORE__RET_SPAD_EN_2 0x0798 01455 01456 #define VL53L1_RANGING_CORE__RET_SPAD_EN_3 0x0799 01457 01458 #define VL53L1_RANGING_CORE__RET_SPAD_EN_4 0x079A 01459 01460 #define VL53L1_RANGING_CORE__RET_SPAD_EN_5 0x079B 01461 01462 #define VL53L1_RANGING_CORE__RET_SPAD_EN_6 0x079C 01463 01464 #define VL53L1_RANGING_CORE__RET_SPAD_EN_7 0x079D 01465 01466 #define VL53L1_RANGING_CORE__RET_SPAD_EN_8 0x079E 01467 01468 #define VL53L1_RANGING_CORE__RET_SPAD_EN_9 0x079F 01469 01470 #define VL53L1_RANGING_CORE__RET_SPAD_EN_10 0x07A0 01471 01472 #define VL53L1_RANGING_CORE__RET_SPAD_EN_11 0x07A1 01473 01474 #define VL53L1_RANGING_CORE__RET_SPAD_EN_12 0x07A2 01475 01476 #define VL53L1_RANGING_CORE__RET_SPAD_EN_13 0x07A3 01477 01478 #define VL53L1_RANGING_CORE__RET_SPAD_EN_14 0x07A4 01479 01480 #define VL53L1_RANGING_CORE__RET_SPAD_EN_15 0x07A5 01481 01482 #define VL53L1_RANGING_CORE__RET_SPAD_EN_16 0x07A6 01483 01484 #define VL53L1_RANGING_CORE__RET_SPAD_EN_17 0x07A7 01485 01486 #define VL53L1_RANGING_CORE__SPAD_SHIFT_EN 0x07BA 01487 01488 #define VL53L1_RANGING_CORE__SPAD_DISABLE_CTRL 0x07BB 01489 01490 #define VL53L1_RANGING_CORE__SPAD_EN_SHIFT_OUT_DEBUG 0x07BC 01491 01492 #define VL53L1_RANGING_CORE__SPI_MODE 0x07BD 01493 01494 #define VL53L1_RANGING_CORE__GPIO_DIR 0x07BE 01495 01496 #define VL53L1_RANGING_CORE__VCSEL_PERIOD 0x0880 01497 01498 #define VL53L1_RANGING_CORE__VCSEL_START 0x0881 01499 01500 #define VL53L1_RANGING_CORE__VCSEL_STOP 0x0882 01501 01502 #define VL53L1_RANGING_CORE__VCSEL_1 0x0885 01503 01504 #define VL53L1_RANGING_CORE__VCSEL_STATUS 0x088D 01505 01506 #define VL53L1_RANGING_CORE__STATUS 0x0980 01507 01508 #define VL53L1_RANGING_CORE__LASER_CONTINUITY_STATE 0x0981 01509 01510 #define VL53L1_RANGING_CORE__RANGE_1_MMM 0x0982 01511 01512 #define VL53L1_RANGING_CORE__RANGE_1_LMM 0x0983 01513 01514 #define VL53L1_RANGING_CORE__RANGE_1_LLM 0x0984 01515 01516 #define VL53L1_RANGING_CORE__RANGE_1_LLL 0x0985 01517 01518 #define VL53L1_RANGING_CORE__RANGE_REF_1_MMM 0x0986 01519 01520 #define VL53L1_RANGING_CORE__RANGE_REF_1_LMM 0x0987 01521 01522 #define VL53L1_RANGING_CORE__RANGE_REF_1_LLM 0x0988 01523 01524 #define VL53L1_RANGING_CORE__RANGE_REF_1_LLL 0x0989 01525 01526 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_MMM 0x098A 01527 01528 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LMM 0x098B 01529 01530 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLM 0x098C 01531 01532 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLL 0x098D 01533 01534 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_1_MMM 0x098E 01535 01536 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LMM 0x098F 01537 01538 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLM 0x0990 01539 01540 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLL 0x0991 01541 01542 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_MMM 0x0992 01543 01544 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LMM 0x0993 01545 01546 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLM 0x0994 01547 01548 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLL 0x0995 01549 01550 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_MM 0x0996 01551 01552 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LM 0x0997 01553 01554 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LL 0x0998 01555 01556 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_MM 0x0999 01557 01558 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_LM 0x099A 01559 01560 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_LL 0x099B 01561 01562 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_MMM 0x099C 01563 01564 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LMM 0x099D 01565 01566 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLM 0x099E 01567 01568 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLL 0x099F 01569 01570 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_MMM 0x09A0 01571 01572 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LMM 0x09A1 01573 01574 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLM 0x09A2 01575 01576 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLL 0x09A3 01577 01578 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_MMM 0x09A4 01579 01580 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LMM 0x09A5 01581 01582 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLM 0x09A6 01583 01584 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLL 0x09A7 01585 01586 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_MM 0x09A8 01587 01588 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LM 0x09A9 01589 01590 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LL 0x09AA 01591 01592 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_REF_MM 0x09AB 01593 01594 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_REF_LM 0x09AC 01595 01596 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_REF_LL 0x09AD 01597 01598 #define VL53L1_RANGING_CORE__GPIO_CONFIG__A0 0x0A00 01599 01600 #define VL53L1_RANGING_CORE__RESET_CONTROL__A0 0x0A01 01601 01602 #define VL53L1_RANGING_CORE__INTR_MANAGER__A0 0x0A02 01603 01604 #define VL53L1_RANGING_CORE__POWER_FSM_TIME_OSC__A0 0x0A06 01605 01606 #define VL53L1_RANGING_CORE__VCSEL_ATEST__A0 0x0A07 01607 01608 #define VL53L1_RANGING_CORE__VCSEL_PERIOD_CLIPPED__A0 0x0A08 01609 01610 #define VL53L1_RANGING_CORE__VCSEL_STOP_CLIPPED__A0 0x0A09 01611 01612 #define VL53L1_RANGING_CORE__CALIB_2__A0 0x0A0A 01613 01614 #define VL53L1_RANGING_CORE__STOP_CONDITION__A0 0x0A0B 01615 01616 #define VL53L1_RANGING_CORE__STATUS_RESET__A0 0x0A0C 01617 01618 #define VL53L1_RANGING_CORE__READOUT_CFG__A0 0x0A0D 01619 01620 #define VL53L1_RANGING_CORE__WINDOW_SETTING__A0 0x0A0E 01621 01622 #define VL53L1_RANGING_CORE__VCSEL_DELAY__A0 0x0A1A 01623 01624 #define VL53L1_RANGING_CORE__REFERENCE_2__A0 0x0A1B 01625 01626 #define VL53L1_RANGING_CORE__REGAVDD1V2__A0 0x0A1D 01627 01628 #define VL53L1_RANGING_CORE__TST_MUX__A0 0x0A1F 01629 01630 #define VL53L1_RANGING_CORE__CUSTOM_FE_2__A0 0x0A20 01631 01632 #define VL53L1_RANGING_CORE__SPAD_READOUT__A0 0x0A21 01633 01634 #define VL53L1_RANGING_CORE__CPUMP_1__A0 0x0A22 01635 01636 #define VL53L1_RANGING_CORE__SPARE_REGISTER__A0 0x0A23 01637 01638 #define VL53L1_RANGING_CORE__VCSEL_CONT_STAGE5_BYPASS__A0 0x0A24 01639 01640 #define VL53L1_RANGING_CORE__RET_SPAD_EN_18 0x0A25 01641 01642 #define VL53L1_RANGING_CORE__RET_SPAD_EN_19 0x0A26 01643 01644 #define VL53L1_RANGING_CORE__RET_SPAD_EN_20 0x0A27 01645 01646 #define VL53L1_RANGING_CORE__RET_SPAD_EN_21 0x0A28 01647 01648 #define VL53L1_RANGING_CORE__RET_SPAD_EN_22 0x0A29 01649 01650 #define VL53L1_RANGING_CORE__RET_SPAD_EN_23 0x0A2A 01651 01652 #define VL53L1_RANGING_CORE__RET_SPAD_EN_24 0x0A2B 01653 01654 #define VL53L1_RANGING_CORE__RET_SPAD_EN_25 0x0A2C 01655 01656 #define VL53L1_RANGING_CORE__RET_SPAD_EN_26 0x0A2D 01657 01658 #define VL53L1_RANGING_CORE__RET_SPAD_EN_27 0x0A2E 01659 01660 #define VL53L1_RANGING_CORE__RET_SPAD_EN_28 0x0A2F 01661 01662 #define VL53L1_RANGING_CORE__RET_SPAD_EN_29 0x0A30 01663 01664 #define VL53L1_RANGING_CORE__RET_SPAD_EN_30 0x0A31 01665 01666 #define VL53L1_RANGING_CORE__RET_SPAD_EN_31 0x0A32 01667 01668 #define VL53L1_RANGING_CORE__REF_SPAD_EN_0__EWOK 0x0A33 01669 01670 #define VL53L1_RANGING_CORE__REF_SPAD_EN_1__EWOK 0x0A34 01671 01672 #define VL53L1_RANGING_CORE__REF_SPAD_EN_2__EWOK 0x0A35 01673 01674 #define VL53L1_RANGING_CORE__REF_SPAD_EN_3__EWOK 0x0A36 01675 01676 #define VL53L1_RANGING_CORE__REF_SPAD_EN_4__EWOK 0x0A37 01677 01678 #define VL53L1_RANGING_CORE__REF_SPAD_EN_5__EWOK 0x0A38 01679 01680 #define VL53L1_RANGING_CORE__REF_EN_START_SELECT 0x0A39 01681 01682 #define VL53L1_RANGING_CORE__REGDVDD1V2_ATEST__EWOK 0x0A41 01683 01684 #define VL53L1_SOFT_RESET_GO1 0x0B00 01685 01686 #define VL53L1_PRIVATE__PATCH_BASE_ADDR_RSLV 0x0E00 01687 01688 #define VL53L1_PREV_SHADOW_RESULT__INTERRUPT_STATUS 0x0ED0 01689 01690 #define VL53L1_PREV_SHADOW_RESULT__RANGE_STATUS 0x0ED1 01691 01692 #define VL53L1_PREV_SHADOW_RESULT__REPORT_STATUS 0x0ED2 01693 01694 #define VL53L1_PREV_SHADOW_RESULT__STREAM_COUNT 0x0ED3 01695 01696 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x0ED4 01697 01698 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0ED4 01699 01700 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0ED5 01701 01702 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x0ED6 01703 01704 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0ED6 01705 01706 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0ED7 01707 01708 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0ED8 01709 01710 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0ED8 01711 01712 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0ED9 01713 01714 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD0 0x0EDA 01715 01716 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD0_HI 0x0EDA 01717 01718 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD0_LO 0x0EDB 01719 01720 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD0 0x0EDC 01721 01722 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD0_HI 0x0EDC 01723 01724 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD0_LO 0x0EDD 01725 01726 #define VL53L1_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0EDE 01727 01728 #define VL53L1_PREV__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0EDE 01729 01730 #define VL53L1_PREV__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0EDF 01731 01732 #define VL53L1_PREV__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0EE0 01733 01734 #define VL53L1_PPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0EE0 01735 01736 #define VL53L1_PPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0EE1 01737 01738 #define VL53L1_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0EE2 01739 01740 #define VL53L1_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0EE2 01741 01742 #define VL53L1_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0EE3 01743 01744 #define VL53L1_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0EE4 01745 01746 #define VL53L1_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0EE4 01747 01748 #define VL53L1_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0EE5 01749 01750 #define VL53L1_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x0EE6 01751 01752 #define VL53L1_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0EE6 01753 01754 #define VL53L1_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0EE7 01755 01756 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x0EE8 01757 01758 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x0EE8 01759 01760 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x0EE9 01761 01762 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x0EEA 01763 01764 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x0EEA 01765 01766 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x0EEB 01767 01768 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x0EEC 01769 01770 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x0EEC 01771 01772 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x0EED 01773 01774 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD1 0x0EEE 01775 01776 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD1_HI 0x0EEE 01777 01778 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD1_LO 0x0EEF 01779 01780 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD1 0x0EF0 01781 01782 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD1_HI 0x0EF0 01783 01784 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD1_LO 0x0EF1 01785 01786 #define VL53L1_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x0EF2 01787 01788 #define VL53L1_PFINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x0EF2 01789 01790 #define VL53L1_PFINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x0EF3 01791 01792 #define VL53L1_PREV_SHADOW_RESULT__SPARE_0_SD1 0x0EF4 01793 01794 #define VL53L1_PREV_SHADOW_RESULT__SPARE_0_SD1_HI 0x0EF4 01795 01796 #define VL53L1_PREV_SHADOW_RESULT__SPARE_0_SD1_LO 0x0EF5 01797 01798 #define VL53L1_PREV_SHADOW_RESULT__SPARE_1_SD1 0x0EF6 01799 01800 #define VL53L1_PREV_SHADOW_RESULT__SPARE_1_SD1_HI 0x0EF6 01801 01802 #define VL53L1_PREV_SHADOW_RESULT__SPARE_1_SD1_LO 0x0EF7 01803 01804 #define VL53L1_PREV_SHADOW_RESULT__SPARE_2_SD1 0x0EF8 01805 01806 #define VL53L1_PREV_SHADOW_RESULT__SPARE_2_SD1_HI 0x0EF8 01807 01808 #define VL53L1_PREV_SHADOW_RESULT__SPARE_2_SD1_LO 0x0EF9 01809 01810 #define VL53L1_PREV_SHADOW_RESULT__SPARE_3_SD1 0x0EFA 01811 01812 #define VL53L1_PREV_SHADOW_RESULT__SPARE_3_SD1_HI 0x0EFA 01813 01814 #define VL53L1_PREV_SHADOW_RESULT__SPARE_3_SD1_LO 0x0EFB 01815 01816 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x0EFC 01817 01818 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x0EFC 01819 01820 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x0EFD 01821 01822 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x0EFE 01823 01824 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x0EFF 01825 01826 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x0F00 01827 01828 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x0F00 01829 01830 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x0F01 01831 01832 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x0F02 01833 01834 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x0F03 01835 01836 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x0F04 01837 01838 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x0F04 01839 01840 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x0F05 01841 01842 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x0F06 01843 01844 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x0F07 01845 01846 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x0F08 01847 01848 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x0F08 01849 01850 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x0F09 01851 01852 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x0F0A 01853 01854 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x0F0B 01855 01856 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x0F0C 01857 01858 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x0F0C 01859 01860 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x0F0D 01861 01862 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x0F0E 01863 01864 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x0F0F 01865 01866 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x0F10 01867 01868 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x0F10 01869 01870 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x0F11 01871 01872 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x0F12 01873 01874 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x0F13 01875 01876 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x0F14 01877 01878 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x0F14 01879 01880 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x0F15 01881 01882 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x0F16 01883 01884 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x0F17 01885 01886 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x0F18 01887 01888 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x0F18 01889 01890 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x0F19 01891 01892 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x0F1A 01893 01894 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x0F1B 01895 01896 #define VL53L1_PREV_SHADOW_RESULT_CORE__SPARE_0 0x0F1C 01897 01898 #define VL53L1_RESULT__DEBUG_STATUS 0x0F20 01899 01900 #define VL53L1_RESULT__DEBUG_STAGE 0x0F21 01901 01902 #define VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH 0x0F24 01903 01904 #define VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH_HI 0x0F24 01905 01906 #define VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH_LO 0x0F25 01907 01908 #define VL53L1_GPH__SYSTEM__THRESH_RATE_LOW 0x0F26 01909 01910 #define VL53L1_GPH__SYSTEM__THRESH_RATE_LOW_HI 0x0F26 01911 01912 #define VL53L1_GPH__SYSTEM__THRESH_RATE_LOW_LO 0x0F27 01913 01914 #define VL53L1_GPH__SYSTEM__INTERRUPT_CONFIG_GPIO 0x0F28 01915 01916 #define VL53L1_GPH__DSS_CONFIG__ROI_MODE_CONTROL 0x0F2F 01917 01918 #define VL53L1_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT 0x0F30 01919 01920 #define VL53L1_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0F30 01921 01922 #define VL53L1_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0F31 01923 01924 #define VL53L1_GPH__DSS_CONFIG__MANUAL_BLOCK_SELECT 0x0F32 01925 01926 #define VL53L1_GPH__DSS_CONFIG__MAX_SPADS_LIMIT 0x0F33 01927 01928 #define VL53L1_GPH__DSS_CONFIG__MIN_SPADS_LIMIT 0x0F34 01929 01930 #define VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI 0x0F36 01931 01932 #define VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_A_LO 0x0F37 01933 01934 #define VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_B_HI 0x0F38 01935 01936 #define VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_B_LO 0x0F39 01937 01938 #define VL53L1_GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_HI 0x0F3A 01939 01940 #define VL53L1_GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_LO 0x0F3B 01941 01942 #define VL53L1_GPH__RANGE_CONFIG__VCSEL_PERIOD_A 0x0F3C 01943 01944 #define VL53L1_GPH__RANGE_CONFIG__VCSEL_PERIOD_B 0x0F3D 01945 01946 #define VL53L1_GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_HI 0x0F3E 01947 01948 #define VL53L1_GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_LO 0x0F3F 01949 01950 #define VL53L1_GPH__RANGE_CONFIG__SIGMA_THRESH 0x0F40 01951 01952 #define VL53L1_GPH__RANGE_CONFIG__SIGMA_THRESH_HI 0x0F40 01953 01954 #define VL53L1_GPH__RANGE_CONFIG__SIGMA_THRESH_LO 0x0F41 01955 01956 #define VL53L1_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0F42 01957 01958 #define VL53L1_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0F42 01959 01960 #define VL53L1_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0F43 01961 01962 #define VL53L1_GPH__RANGE_CONFIG__VALID_PHASE_LOW 0x0F44 01963 01964 #define VL53L1_GPH__RANGE_CONFIG__VALID_PHASE_HIGH 0x0F45 01965 01966 #define VL53L1_FIRMWARE__INTERNAL_STREAM_COUNT_DIV 0x0F46 01967 01968 #define VL53L1_FIRMWARE__INTERNAL_STREAM_COUNTER_VAL 0x0F47 01969 01970 #define VL53L1_DSS_CALC__ROI_CTRL 0x0F54 01971 01972 #define VL53L1_DSS_CALC__SPARE_1 0x0F55 01973 01974 #define VL53L1_DSS_CALC__SPARE_2 0x0F56 01975 01976 #define VL53L1_DSS_CALC__SPARE_3 0x0F57 01977 01978 #define VL53L1_DSS_CALC__SPARE_4 0x0F58 01979 01980 #define VL53L1_DSS_CALC__SPARE_5 0x0F59 01981 01982 #define VL53L1_DSS_CALC__SPARE_6 0x0F5A 01983 01984 #define VL53L1_DSS_CALC__SPARE_7 0x0F5B 01985 01986 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_0 0x0F5C 01987 01988 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_1 0x0F5D 01989 01990 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_2 0x0F5E 01991 01992 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_3 0x0F5F 01993 01994 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_4 0x0F60 01995 01996 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_5 0x0F61 01997 01998 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_6 0x0F62 01999 02000 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_7 0x0F63 02001 02002 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_8 0x0F64 02003 02004 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_9 0x0F65 02005 02006 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_10 0x0F66 02007 02008 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_11 0x0F67 02009 02010 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_12 0x0F68 02011 02012 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_13 0x0F69 02013 02014 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_14 0x0F6A 02015 02016 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_15 0x0F6B 02017 02018 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_16 0x0F6C 02019 02020 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_17 0x0F6D 02021 02022 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_18 0x0F6E 02023 02024 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_19 0x0F6F 02025 02026 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_20 0x0F70 02027 02028 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_21 0x0F71 02029 02030 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_22 0x0F72 02031 02032 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_23 0x0F73 02033 02034 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_24 0x0F74 02035 02036 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_25 0x0F75 02037 02038 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_26 0x0F76 02039 02040 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_27 0x0F77 02041 02042 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_28 0x0F78 02043 02044 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_29 0x0F79 02045 02046 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_30 0x0F7A 02047 02048 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_31 0x0F7B 02049 02050 #define VL53L1_DSS_CALC__USER_ROI_0 0x0F7C 02051 02052 #define VL53L1_DSS_CALC__USER_ROI_1 0x0F7D 02053 02054 #define VL53L1_DSS_CALC__MODE_ROI_0 0x0F7E 02055 02056 #define VL53L1_DSS_CALC__MODE_ROI_1 0x0F7F 02057 02058 #define VL53L1_SIGMA_ESTIMATOR_CALC__SPARE_0 0x0F80 02059 02060 #define VL53L1_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS 0x0F82 02061 02062 #define VL53L1_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_HI 0x0F82 02063 02064 #define VL53L1_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_LO 0x0F83 02065 02066 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF 0x0F84 02067 02068 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_3 0x0F84 02069 02070 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_2 0x0F85 02071 02072 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_1 0x0F86 02073 02074 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_0 0x0F87 02075 02076 #define VL53L1_PHASECAL_RESULT__PHASE_OUTPUT_REF 0x0F88 02077 02078 #define VL53L1_PHASECAL_RESULT__PHASE_OUTPUT_REF_HI 0x0F88 02079 02080 #define VL53L1_PHASECAL_RESULT__PHASE_OUTPUT_REF_LO 0x0F89 02081 02082 #define VL53L1_DSS_RESULT__TOTAL_RATE_PER_SPAD 0x0F8A 02083 02084 #define VL53L1_DSS_RESULT__TOTAL_RATE_PER_SPAD_HI 0x0F8A 02085 02086 #define VL53L1_DSS_RESULT__TOTAL_RATE_PER_SPAD_LO 0x0F8B 02087 02088 #define VL53L1_DSS_RESULT__ENABLED_BLOCKS 0x0F8C 02089 02090 #define VL53L1_DSS_RESULT__NUM_REQUESTED_SPADS 0x0F8E 02091 02092 #define VL53L1_DSS_RESULT__NUM_REQUESTED_SPADS_HI 0x0F8E 02093 02094 #define VL53L1_DSS_RESULT__NUM_REQUESTED_SPADS_LO 0x0F8F 02095 02096 #define VL53L1_MM_RESULT__INNER_INTERSECTION_RATE 0x0F92 02097 02098 #define VL53L1_MM_RESULT__INNER_INTERSECTION_RATE_HI 0x0F92 02099 02100 #define VL53L1_MM_RESULT__INNER_INTERSECTION_RATE_LO 0x0F93 02101 02102 #define VL53L1_MM_RESULT__OUTER_COMPLEMENT_RATE 0x0F94 02103 02104 #define VL53L1_MM_RESULT__OUTER_COMPLEMENT_RATE_HI 0x0F94 02105 02106 #define VL53L1_MM_RESULT__OUTER_COMPLEMENT_RATE_LO 0x0F95 02107 02108 #define VL53L1_MM_RESULT__TOTAL_OFFSET 0x0F96 02109 02110 #define VL53L1_MM_RESULT__TOTAL_OFFSET_HI 0x0F96 02111 02112 #define VL53L1_MM_RESULT__TOTAL_OFFSET_LO 0x0F97 02113 02114 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS 0x0F98 02115 02116 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_3 0x0F98 02117 02118 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_2 0x0F99 02119 02120 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_1 0x0F9A 02121 02122 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_0 0x0F9B 02123 02124 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS 0x0F9C 02125 02126 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_3 0x0F9C 02127 02128 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_2 0x0F9D 02129 02130 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_1 0x0F9E 02131 02132 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_0 0x0F9F 02133 02134 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS 0x0FA0 02135 02136 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_3 0x0FA0 02137 02138 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_2 0x0FA1 02139 02140 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_1 0x0FA2 02141 02142 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_0 0x0FA3 02143 02144 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS 0x0FA4 02145 02146 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_3 0x0FA4 02147 02148 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_2 0x0FA5 02149 02150 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_1 0x0FA6 02151 02152 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_0 0x0FA7 02153 02154 #define VL53L1_RANGE_RESULT__ACCUM_PHASE 0x0FA8 02155 02156 #define VL53L1_RANGE_RESULT__ACCUM_PHASE_3 0x0FA8 02157 02158 #define VL53L1_RANGE_RESULT__ACCUM_PHASE_2 0x0FA9 02159 02160 #define VL53L1_RANGE_RESULT__ACCUM_PHASE_1 0x0FAA 02161 02162 #define VL53L1_RANGE_RESULT__ACCUM_PHASE_0 0x0FAB 02163 02164 #define VL53L1_RANGE_RESULT__OFFSET_CORRECTED_RANGE 0x0FAC 02165 02166 #define VL53L1_RANGE_RESULT__OFFSET_CORRECTED_RANGE_HI 0x0FAC 02167 02168 #define VL53L1_RANGE_RESULT__OFFSET_CORRECTED_RANGE_LO 0x0FAD 02169 02170 #define VL53L1_SHADOW_PHASECAL_RESULT__VCSEL_START 0x0FAE 02171 02172 #define VL53L1_SHADOW_RESULT__INTERRUPT_STATUS 0x0FB0 02173 02174 #define VL53L1_SHADOW_RESULT__RANGE_STATUS 0x0FB1 02175 02176 #define VL53L1_SHADOW_RESULT__REPORT_STATUS 0x0FB2 02177 02178 #define VL53L1_SHADOW_RESULT__STREAM_COUNT 0x0FB3 02179 02180 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FB4 02181 02182 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FB4 02183 02184 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FB5 02185 02186 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x0FB6 02187 02188 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0FB6 02189 02190 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0FB7 02191 02192 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0FB8 02193 02194 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0FB8 02195 02196 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0FB9 02197 02198 #define VL53L1_SHADOW_RESULT__SIGMA_SD0 0x0FBA 02199 02200 #define VL53L1_SHADOW_RESULT__SIGMA_SD0_HI 0x0FBA 02201 02202 #define VL53L1_SHADOW_RESULT__SIGMA_SD0_LO 0x0FBB 02203 02204 #define VL53L1_SHADOW_RESULT__PHASE_SD0 0x0FBC 02205 02206 #define VL53L1_SHADOW_RESULT__PHASE_SD0_HI 0x0FBC 02207 02208 #define VL53L1_SHADOW_RESULT__PHASE_SD0_LO 0x0FBD 02209 02210 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0FBE 02211 02212 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0FBE 02213 02214 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0FBF 02215 02216 #define VL53L1_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0FC0 02217 02218 #define VL53L1_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0FC0 02219 02220 #define VL53L1_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0FC1 02221 02222 #define VL53L1_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FC2 02223 02224 #define VL53L1_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FC2 02225 02226 #define VL53L1_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FC3 02227 02228 #define VL53L1_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FC4 02229 02230 #define VL53L1_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FC4 02231 02232 #define VL53L1_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FC5 02233 02234 #define VL53L1_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x0FC6 02235 02236 #define VL53L1_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0FC6 02237 02238 #define VL53L1_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0FC7 02239 02240 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x0FC8 02241 02242 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x0FC8 02243 02244 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x0FC9 02245 02246 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x0FCA 02247 02248 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x0FCA 02249 02250 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x0FCB 02251 02252 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x0FCC 02253 02254 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x0FCC 02255 02256 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x0FCD 02257 02258 #define VL53L1_SHADOW_RESULT__SIGMA_SD1 0x0FCE 02259 02260 #define VL53L1_SHADOW_RESULT__SIGMA_SD1_HI 0x0FCE 02261 02262 #define VL53L1_SHADOW_RESULT__SIGMA_SD1_LO 0x0FCF 02263 02264 #define VL53L1_SHADOW_RESULT__PHASE_SD1 0x0FD0 02265 02266 #define VL53L1_SHADOW_RESULT__PHASE_SD1_HI 0x0FD0 02267 02268 #define VL53L1_SHADOW_RESULT__PHASE_SD1_LO 0x0FD1 02269 02270 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x0FD2 02271 02272 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x0FD2 02273 02274 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x0FD3 02275 02276 #define VL53L1_SHADOW_RESULT__SPARE_0_SD1 0x0FD4 02277 02278 #define VL53L1_SHADOW_RESULT__SPARE_0_SD1_HI 0x0FD4 02279 02280 #define VL53L1_SHADOW_RESULT__SPARE_0_SD1_LO 0x0FD5 02281 02282 #define VL53L1_SHADOW_RESULT__SPARE_1_SD1 0x0FD6 02283 02284 #define VL53L1_SHADOW_RESULT__SPARE_1_SD1_HI 0x0FD6 02285 02286 #define VL53L1_SHADOW_RESULT__SPARE_1_SD1_LO 0x0FD7 02287 02288 #define VL53L1_SHADOW_RESULT__SPARE_2_SD1 0x0FD8 02289 02290 #define VL53L1_SHADOW_RESULT__SPARE_2_SD1_HI 0x0FD8 02291 02292 #define VL53L1_SHADOW_RESULT__SPARE_2_SD1_LO 0x0FD9 02293 02294 #define VL53L1_SHADOW_RESULT__SPARE_3_SD1 0x0FDA 02295 02296 #define VL53L1_SHADOW_RESULT__THRESH_INFO 0x0FDB 02297 02298 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x0FDC 02299 02300 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x0FDC 02301 02302 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x0FDD 02303 02304 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x0FDE 02305 02306 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x0FDF 02307 02308 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x0FE0 02309 02310 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x0FE0 02311 02312 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x0FE1 02313 02314 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x0FE2 02315 02316 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x0FE3 02317 02318 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x0FE4 02319 02320 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x0FE4 02321 02322 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x0FE5 02323 02324 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x0FE6 02325 02326 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x0FE7 02327 02328 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x0FE8 02329 02330 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x0FE8 02331 02332 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x0FE9 02333 02334 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x0FEA 02335 02336 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x0FEB 02337 02338 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x0FEC 02339 02340 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x0FEC 02341 02342 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x0FED 02343 02344 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x0FEE 02345 02346 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x0FEF 02347 02348 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x0FF0 02349 02350 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x0FF0 02351 02352 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x0FF1 02353 02354 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x0FF2 02355 02356 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x0FF3 02357 02358 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x0FF4 02359 02360 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x0FF4 02361 02362 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x0FF5 02363 02364 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x0FF6 02365 02366 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x0FF7 02367 02368 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x0FF8 02369 02370 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x0FF8 02371 02372 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x0FF9 02373 02374 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x0FFA 02375 02376 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x0FFB 02377 02378 #define VL53L1_SHADOW_RESULT_CORE__SPARE_0 0x0FFC 02379 02380 #define VL53L1_SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_HI 0x0FFE 02381 02382 #define VL53L1_SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_LO 0x0FFF 02383 02384 02385 02386 02387 02388 #endif 02389 02390
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