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Dependencies: X_NUCLEO_COMMON ST_INTERFACES
vl53l1_nvm_structs.h
00001 00002 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 00003 /****************************************************************************** 00004 * Copyright (c) 2020, STMicroelectronics - All Rights Reserved 00005 00006 This file is part of VL53L1 and is dual licensed, 00007 either GPL-2.0+ 00008 or 'BSD 3-clause "New" or "Revised" License' , at your option. 00009 ****************************************************************************** 00010 */ 00011 00012 00013 00014 00015 00016 00017 00018 #ifndef _VL53L1_NVM_STRUCTS_H_ 00019 #define _VL53L1_NVM_STRUCTS_H_ 00020 00021 00022 #ifdef __cplusplus 00023 extern "C" 00024 { 00025 #endif 00026 00027 #include "vl53l1_platform.h" 00028 #include "vl53l1_ll_def.h" 00029 00030 00031 00032 00033 typedef struct { 00034 00035 uint16_t result__actual_effective_rtn_spads; 00036 00037 uint8_t ref_spad_array__num_requested_ref_spads; 00038 00039 uint8_t ref_spad_array__ref_location; 00040 00041 uint16_t result__peak_signal_count_rate_rtn_mcps; 00042 00043 uint16_t result__ambient_count_rate_rtn_mcps; 00044 00045 uint16_t result__peak_signal_count_rate_ref_mcps; 00046 00047 uint16_t result__ambient_count_rate_ref_mcps; 00048 00049 uint16_t measured_distance_mm; 00050 00051 uint16_t measured_distance_stdev_mm; 00052 00053 00054 } VL53L1_decoded_nvm_fmt_range_data_t; 00055 00056 00057 00058 00059 typedef struct { 00060 00061 char nvm__fmt__fgc[19]; 00062 00063 uint8_t nvm__fmt__test_program_major; 00064 00065 uint8_t nvm__fmt__test_program_minor; 00066 00067 uint8_t nvm__fmt__map_major; 00068 00069 uint8_t nvm__fmt__map_minor; 00070 00071 uint8_t nvm__fmt__year; 00072 00073 uint8_t nvm__fmt__month; 00074 00075 uint8_t nvm__fmt__day; 00076 00077 uint8_t nvm__fmt__module_date_phase; 00078 00079 uint16_t nvm__fmt__time; 00080 00081 uint8_t nvm__fmt__tester_id; 00082 00083 uint8_t nvm__fmt__site_id; 00084 00085 uint8_t nvm__ews__test_program_major; 00086 00087 uint8_t nvm__ews__test_program_minor; 00088 00089 uint8_t nvm__ews__probe_card_major; 00090 00091 uint8_t nvm__ews__probe_card_minor; 00092 00093 uint8_t nvm__ews__tester_id; 00094 00095 00096 char nvm__ews__lot[8]; 00097 00098 uint8_t nvm__ews__wafer; 00099 00100 uint8_t nvm__ews__xcoord; 00101 00102 uint8_t nvm__ews__ycoord; 00103 00104 } VL53L1_decoded_nvm_fmt_info_t; 00105 00106 00107 00108 00109 typedef struct { 00110 00111 uint8_t nvm__ews__test_program_major; 00112 00113 uint8_t nvm__ews__test_program_minor; 00114 00115 uint8_t nvm__ews__probe_card_major; 00116 00117 uint8_t nvm__ews__probe_card_minor; 00118 00119 uint8_t nvm__ews__tester_id; 00120 00121 00122 char nvm__ews__lot[8]; 00123 00124 uint8_t nvm__ews__wafer; 00125 00126 uint8_t nvm__ews__xcoord; 00127 00128 uint8_t nvm__ews__ycoord; 00129 00130 00131 } VL53L1_decoded_nvm_ews_info_t; 00132 00133 00134 00135 00136 typedef struct { 00137 uint8_t nvm__identification_model_id; 00138 00139 uint8_t nvm__identification_module_type; 00140 00141 uint8_t nvm__identification_revision_id; 00142 00143 uint16_t nvm__identification_module_id; 00144 00145 uint8_t nvm__i2c_valid; 00146 00147 uint8_t nvm__i2c_device_address_ews; 00148 00149 uint16_t nvm__ews__fast_osc_frequency; 00150 00151 uint8_t nvm__ews__fast_osc_trim_max; 00152 00153 uint8_t nvm__ews__fast_osc_freq_set; 00154 00155 uint16_t nvm__ews__slow_osc_calibration; 00156 00157 uint16_t nvm__fmt__fast_osc_frequency; 00158 00159 uint8_t nvm__fmt__fast_osc_trim_max; 00160 00161 uint8_t nvm__fmt__fast_osc_freq_set; 00162 00163 uint16_t nvm__fmt__slow_osc_calibration; 00164 00165 uint8_t nvm__vhv_config_unlock; 00166 00167 uint8_t nvm__ref_selvddpix; 00168 00169 uint8_t nvm__ref_selvquench; 00170 00171 uint8_t nvm__regavdd1v2_sel; 00172 00173 uint8_t nvm__regdvdd1v2_sel; 00174 00175 uint8_t nvm__vhv_timeout__macrop; 00176 00177 uint8_t nvm__vhv_loop_bound; 00178 00179 uint8_t nvm__vhv_count_threshold; 00180 00181 uint8_t nvm__vhv_offset; 00182 00183 uint8_t nvm__vhv_init_enable; 00184 00185 uint8_t nvm__vhv_init_value; 00186 00187 uint8_t nvm__laser_safety_vcsel_trim_ll; 00188 00189 uint8_t nvm__laser_safety_vcsel_selion_ll; 00190 00191 uint8_t nvm__laser_safety_vcsel_selion_max_ll; 00192 00193 uint8_t nvm__laser_safety_mult_ll; 00194 00195 uint8_t nvm__laser_safety_clip_ll; 00196 00197 uint8_t nvm__laser_safety_vcsel_trim_ld; 00198 00199 uint8_t nvm__laser_safety_vcsel_selion_ld; 00200 00201 uint8_t nvm__laser_safety_vcsel_selion_max_ld; 00202 00203 uint8_t nvm__laser_safety_mult_ld; 00204 00205 uint8_t nvm__laser_safety_clip_ld; 00206 00207 uint8_t nvm__laser_safety_lock_byte; 00208 00209 uint8_t nvm__laser_safety_unlock_byte; 00210 00211 uint8_t nvm__ews__spad_enables_rtn[VL53L1_RTN_SPAD_BUFFER_SIZE]; 00212 00213 uint8_t nvm__ews__spad_enables_ref__loc1[VL53L1_REF_SPAD_BUFFER_SIZE]; 00214 00215 uint8_t nvm__ews__spad_enables_ref__loc2[VL53L1_REF_SPAD_BUFFER_SIZE]; 00216 00217 uint8_t nvm__ews__spad_enables_ref__loc3[VL53L1_REF_SPAD_BUFFER_SIZE]; 00218 00219 uint8_t nvm__fmt__spad_enables_rtn[VL53L1_RTN_SPAD_BUFFER_SIZE]; 00220 00221 uint8_t nvm__fmt__spad_enables_ref__loc1[VL53L1_REF_SPAD_BUFFER_SIZE]; 00222 00223 uint8_t nvm__fmt__spad_enables_ref__loc2[VL53L1_REF_SPAD_BUFFER_SIZE]; 00224 00225 uint8_t nvm__fmt__spad_enables_ref__loc3[VL53L1_REF_SPAD_BUFFER_SIZE]; 00226 00227 uint8_t nvm__fmt__roi_config__mode_roi_centre_spad; 00228 00229 uint8_t nvm__fmt__roi_config__mode_roi_x_size; 00230 00231 uint8_t nvm__fmt__roi_config__mode_roi_y_size; 00232 00233 uint8_t nvm__fmt__ref_spad_apply__num_requested_ref_spad; 00234 00235 uint8_t nvm__fmt__ref_spad_man__ref_location; 00236 00237 uint16_t nvm__fmt__mm_config__inner_offset_mm; 00238 00239 uint16_t nvm__fmt__mm_config__outer_offset_mm; 00240 00241 uint16_t nvm__fmt__algo_part_to_part_range_offset_mm; 00242 00243 uint16_t nvm__fmt__algo__crosstalk_compensation_plane_offset_kcps; 00244 00245 uint16_t nvm__fmt__algo__crosstalk_compensation_x_plane_gradient_kcps; 00246 00247 uint16_t nvm__fmt__algo__crosstalk_compensation_y_plane_gradient_kcps; 00248 00249 uint8_t nvm__fmt__spare__host_config__nvm_config_spare_0; 00250 00251 uint8_t nvm__fmt__spare__host_config__nvm_config_spare_1; 00252 00253 uint8_t nvm__customer_space_programmed; 00254 00255 uint8_t nvm__cust__i2c_device_address; 00256 00257 uint8_t nvm__cust__ref_spad_apply__num_requested_ref_spad; 00258 00259 uint8_t nvm__cust__ref_spad_man__ref_location; 00260 00261 uint16_t nvm__cust__mm_config__inner_offset_mm; 00262 00263 uint16_t nvm__cust__mm_config__outer_offset_mm; 00264 00265 uint16_t nvm__cust__algo_part_to_part_range_offset_mm; 00266 00267 uint16_t nvm__cust__algo__crosstalk_compensation_plane_offset_kcps; 00268 00269 uint16_t nvm__cust__algo__crosstalk_compensation_x_plane_gradient_kcps; 00270 00271 uint16_t nvm__cust__algo__crosstalk_compensation_y_plane_gradient_kcps; 00272 00273 uint8_t nvm__cust__spare__host_config__nvm_config_spare_0; 00274 00275 uint8_t nvm__cust__spare__host_config__nvm_config_spare_1; 00276 00277 00278 VL53L1_optical_centre_t fmt_optical_centre; 00279 VL53L1_cal_peak_rate_map_t fmt_peak_rate_map; 00280 VL53L1_additional_offset_cal_data_t fmt_add_offset_data; 00281 00282 VL53L1_decoded_nvm_fmt_range_data_t 00283 fmt_range_data[VL53L1_NVM_MAX_FMT_RANGE_DATA]; 00284 00285 VL53L1_decoded_nvm_fmt_info_t fmt_info; 00286 VL53L1_decoded_nvm_ews_info_t ews_info; 00287 00288 } VL53L1_decoded_nvm_data_t; 00289 00290 00291 00292 #ifdef __cplusplus 00293 } 00294 #endif 00295 00296 #endif 00297
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