vl53l1_ll_def.h

00001 
00002 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
00003 /******************************************************************************
00004  * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
00005 
00006  This file is part of VL53L1 and is dual licensed,
00007  either GPL-2.0+
00008  or 'BSD 3-clause "New" or "Revised" License' , at your option.
00009  ******************************************************************************
00010  */
00011 
00012 
00013 
00014 
00015 
00016 #ifndef _VL53L1_LL_DEF_H_
00017 #define _VL53L1_LL_DEF_H_
00018 
00019 #include "vl53l1_error_codes.h"
00020 #include "vl53l1_register_structs.h"
00021 #include "vl53l1_platform_user_config.h"
00022 #include "vl53l1_platform_user_defines.h"
00023 #include "vl53l1_hist_structs.h"
00024 #include "vl53l1_dmax_structs.h"
00025 #include "vl53l1_error_exceptions.h"
00026 
00027 #ifdef __cplusplus
00028 extern "C" {
00029 #endif
00030 
00031 
00032 
00033 
00034 #define VL53L1_LL_API_IMPLEMENTATION_VER_MAJOR       1
00035 
00036 #define VL53L1_LL_API_IMPLEMENTATION_VER_MINOR       1
00037 
00038 #define VL53L1_LL_API_IMPLEMENTATION_VER_SUB         48
00039 
00040 #define VL53L1_LL_API_IMPLEMENTATION_VER_REVISION   12224
00041 
00042 #define VL53L1_LL_API_IMPLEMENTATION_VER_STRING "1.1.48.12224"
00043 
00044 
00045 #define VL53L1_FIRMWARE_VER_MINIMUM         398
00046 #define VL53L1_FIRMWARE_VER_MAXIMUM         400
00047 
00048 
00049 
00050 
00051 #define VL53L1_LL_CALIBRATION_DATA_STRUCT_VERSION       0xECAB0102
00052 
00053 
00054 
00055 
00056 #define VL53L1_LL_ZONE_CALIBRATION_DATA_STRUCT_VERSION  0xECAE0101
00057 
00058 
00059 
00060 
00061 
00062 #define VL53L1_BIN_REC_SIZE 6
00063 
00064 #define VL53L1_TIMING_CONF_A_B_SIZE 2
00065 
00066 #define VL53L1_FRAME_WAIT_EVENT 6
00067 
00068 
00069 
00070 #define VL53L1_MAX_XTALK_RANGE_RESULTS        5
00071 
00072 
00073 #define VL53L1_MAX_OFFSET_RANGE_RESULTS       3
00074 
00075 
00076 #define VL53L1_NVM_MAX_FMT_RANGE_DATA         4
00077 
00078 
00079 #define VL53L1_NVM_PEAK_RATE_MAP_SAMPLES  25
00080 
00081 #define VL53L1_NVM_PEAK_RATE_MAP_WIDTH     5
00082 
00083 #define VL53L1_NVM_PEAK_RATE_MAP_HEIGHT     5
00084 
00085 
00086 
00087 
00088 #define VL53L1_ERROR_DEVICE_FIRMWARE_TOO_OLD           ((VL53L1_Error) - 80)
00089 
00090 #define VL53L1_ERROR_DEVICE_FIRMWARE_TOO_NEW           ((VL53L1_Error) - 85)
00091 
00092 #define VL53L1_ERROR_UNIT_TEST_FAIL                    ((VL53L1_Error) - 90)
00093 
00094 #define VL53L1_ERROR_FILE_READ_FAIL                    ((VL53L1_Error) - 95)
00095 
00096 #define VL53L1_ERROR_FILE_WRITE_FAIL                   ((VL53L1_Error) - 96)
00097 
00098 
00099 
00100 
00101 
00102 
00103 typedef struct {
00104     uint32_t     ll_revision;
00105     uint8_t      ll_major;
00106     uint8_t      ll_minor;
00107     uint8_t      ll_build;
00108 } VL53L1_ll_version_t;
00109 
00110 
00111 
00112 
00113 typedef struct {
00114 
00115     uint8_t    device_test_mode;
00116     uint8_t    VL53L1_p_009;
00117     uint32_t   timeout_us;
00118     uint16_t   target_count_rate_mcps;
00119 
00120     uint16_t   min_count_rate_limit_mcps;
00121 
00122     uint16_t   max_count_rate_limit_mcps;
00123 
00124 
00125 } VL53L1_refspadchar_config_t;
00126 
00127 
00128 
00129 
00130 typedef struct {
00131 
00132     uint16_t  dss_config__target_total_rate_mcps;
00133 
00134     uint32_t  phasecal_config_timeout_us;
00135 
00136     uint32_t  mm_config_timeout_us;
00137 
00138     uint32_t  range_config_timeout_us;
00139 
00140     uint8_t   num_of_samples;
00141 
00142     int16_t   algo__crosstalk_extract_min_valid_range_mm;
00143 
00144     int16_t   algo__crosstalk_extract_max_valid_range_mm;
00145 
00146     uint16_t  algo__crosstalk_extract_max_valid_rate_kcps;
00147 
00148     uint16_t  algo__crosstalk_extract_max_sigma_mm;
00149 
00150 
00151 } VL53L1_xtalkextract_config_t;
00152 
00153 
00154 
00155 
00156 typedef struct {
00157 
00158     uint16_t  dss_config__target_total_rate_mcps;
00159 
00160     uint32_t  phasecal_config_timeout_us;
00161 
00162     uint32_t  range_config_timeout_us;
00163 
00164     uint32_t  mm_config_timeout_us;
00165 
00166     uint8_t   pre_num_of_samples;
00167 
00168     uint8_t   mm1_num_of_samples;
00169 
00170     uint8_t   mm2_num_of_samples;
00171 
00172 
00173 } VL53L1_offsetcal_config_t;
00174 
00175 
00176 
00177 
00178 typedef struct {
00179 
00180     uint16_t   dss_config__target_total_rate_mcps;
00181 
00182     uint32_t   phasecal_config_timeout_us;
00183 
00184     uint32_t   mm_config_timeout_us;
00185 
00186     uint32_t   range_config_timeout_us;
00187 
00188     uint16_t   phasecal_num_of_samples;
00189 
00190     uint16_t   zone_num_of_samples;
00191 
00192 
00193 } VL53L1_zonecal_config_t;
00194 
00195 
00196 
00197 
00198 
00199 typedef struct {
00200 
00201     VL53L1_DeviceSscArray  array_select;
00202 
00203     uint8_t    VL53L1_p_009;
00204 
00205     uint8_t    vcsel_start;
00206 
00207     uint8_t    vcsel_width;
00208 
00209     uint32_t   timeout_us;
00210 
00211     uint16_t   rate_limit_mcps;
00212 
00213 
00214 } VL53L1_ssc_config_t;
00215 
00216 
00217 
00218 
00219 typedef struct {
00220 
00221 
00222     uint32_t  algo__crosstalk_compensation_plane_offset_kcps;
00223 
00224     int16_t   algo__crosstalk_compensation_x_plane_gradient_kcps;
00225 
00226     int16_t   algo__crosstalk_compensation_y_plane_gradient_kcps;
00227 
00228     uint32_t  nvm_default__crosstalk_compensation_plane_offset_kcps;
00229 
00230     int16_t   nvm_default__crosstalk_compensation_x_plane_gradient_kcps;
00231 
00232     int16_t   nvm_default__crosstalk_compensation_y_plane_gradient_kcps;
00233 
00234     uint8_t   global_crosstalk_compensation_enable;
00235 
00236     int16_t   histogram_mode_crosstalk_margin_kcps;
00237 
00238     int16_t   lite_mode_crosstalk_margin_kcps;
00239 
00240     uint8_t   crosstalk_range_ignore_threshold_mult;
00241 
00242     uint16_t  crosstalk_range_ignore_threshold_rate_mcps;
00243 
00244     int16_t   algo__crosstalk_detect_min_valid_range_mm;
00245 
00246     int16_t   algo__crosstalk_detect_max_valid_range_mm;
00247 
00248     uint16_t  algo__crosstalk_detect_max_valid_rate_kcps;
00249 
00250     uint16_t  algo__crosstalk_detect_max_sigma_mm;
00251 
00252 
00253 
00254 } VL53L1_xtalk_config_t;
00255 
00256 
00257 
00258 
00259 typedef struct {
00260 
00261 
00262     uint16_t  tp_tuning_parm_version;
00263 
00264     uint16_t  tp_tuning_parm_key_table_version;
00265 
00266     uint16_t  tp_tuning_parm_lld_version;
00267 
00268     uint8_t   tp_init_phase_rtn_lite_long;
00269 
00270     uint8_t   tp_init_phase_rtn_lite_med;
00271 
00272     uint8_t   tp_init_phase_rtn_lite_short;
00273 
00274     uint8_t   tp_init_phase_ref_lite_long;
00275 
00276     uint8_t   tp_init_phase_ref_lite_med;
00277 
00278     uint8_t   tp_init_phase_ref_lite_short;
00279 
00280 
00281     uint8_t   tp_init_phase_rtn_hist_long;
00282 
00283     uint8_t   tp_init_phase_rtn_hist_med;
00284 
00285     uint8_t   tp_init_phase_rtn_hist_short;
00286 
00287     uint8_t   tp_init_phase_ref_hist_long;
00288 
00289     uint8_t   tp_init_phase_ref_hist_med;
00290 
00291     uint8_t   tp_init_phase_ref_hist_short;
00292 
00293 
00294     uint8_t   tp_consistency_lite_phase_tolerance;
00295 
00296     uint8_t   tp_phasecal_target;
00297 
00298     uint16_t  tp_cal_repeat_rate;
00299 
00300     uint8_t   tp_lite_min_clip;
00301 
00302 
00303     uint16_t  tp_lite_long_sigma_thresh_mm;
00304 
00305     uint16_t  tp_lite_med_sigma_thresh_mm;
00306 
00307     uint16_t  tp_lite_short_sigma_thresh_mm;
00308 
00309 
00310     uint16_t  tp_lite_long_min_count_rate_rtn_mcps;
00311 
00312     uint16_t  tp_lite_med_min_count_rate_rtn_mcps;
00313 
00314     uint16_t  tp_lite_short_min_count_rate_rtn_mcps;
00315 
00316 
00317     uint8_t   tp_lite_sigma_est_pulse_width_ns;
00318 
00319     uint8_t   tp_lite_sigma_est_amb_width_ns;
00320 
00321     uint8_t   tp_lite_sigma_ref_mm;
00322 
00323     uint8_t   tp_lite_seed_cfg;
00324 
00325     uint8_t   tp_timed_seed_cfg;
00326 
00327 
00328     uint8_t   tp_lite_quantifier;
00329 
00330     uint8_t   tp_lite_first_order_select;
00331 
00332 
00333     uint16_t  tp_dss_target_lite_mcps;
00334 
00335     uint16_t  tp_dss_target_histo_mcps;
00336 
00337     uint16_t  tp_dss_target_histo_mz_mcps;
00338 
00339     uint16_t  tp_dss_target_timed_mcps;
00340 
00341     uint16_t  tp_dss_target_very_short_mcps;
00342 
00343 
00344     uint32_t  tp_phasecal_timeout_lite_us;
00345 
00346     uint32_t  tp_phasecal_timeout_hist_long_us;
00347 
00348     uint32_t  tp_phasecal_timeout_hist_med_us;
00349 
00350     uint32_t  tp_phasecal_timeout_hist_short_us;
00351 
00352 
00353     uint32_t  tp_phasecal_timeout_mz_long_us;
00354 
00355     uint32_t  tp_phasecal_timeout_mz_med_us;
00356 
00357     uint32_t  tp_phasecal_timeout_mz_short_us;
00358 
00359     uint32_t  tp_phasecal_timeout_timed_us;
00360 
00361 
00362     uint32_t  tp_mm_timeout_lite_us;
00363 
00364     uint32_t  tp_mm_timeout_histo_us;
00365 
00366     uint32_t  tp_mm_timeout_mz_us;
00367 
00368     uint32_t  tp_mm_timeout_timed_us;
00369 
00370     uint32_t  tp_mm_timeout_lpa_us;
00371 
00372 
00373     uint32_t  tp_range_timeout_lite_us;
00374 
00375     uint32_t  tp_range_timeout_histo_us;
00376 
00377     uint32_t  tp_range_timeout_mz_us;
00378 
00379     uint32_t  tp_range_timeout_timed_us;
00380 
00381     uint32_t  tp_range_timeout_lpa_us;
00382 
00383     uint32_t tp_phasecal_patch_power;
00384 
00385     uint8_t tp_hist_merge;
00386 
00387     uint32_t tp_reset_merge_threshold;
00388 
00389     uint8_t tp_hist_merge_max_size;
00390 
00391     uint8_t tp_uwr_enable;
00392     int16_t tp_uwr_med_z_1_min;
00393     int16_t tp_uwr_med_z_1_max;
00394     int16_t tp_uwr_med_z_2_min;
00395     int16_t tp_uwr_med_z_2_max;
00396     int16_t tp_uwr_med_z_3_min;
00397     int16_t tp_uwr_med_z_3_max;
00398     int16_t tp_uwr_med_z_4_min;
00399     int16_t tp_uwr_med_z_4_max;
00400     int16_t tp_uwr_med_z_5_min;
00401     int16_t tp_uwr_med_z_5_max;
00402     int16_t tp_uwr_med_z_6_min;
00403     int16_t tp_uwr_med_z_6_max;
00404     int16_t tp_uwr_med_corr_z_1_rangea;
00405     int16_t tp_uwr_med_corr_z_1_rangeb;
00406     int16_t tp_uwr_med_corr_z_2_rangea;
00407     int16_t tp_uwr_med_corr_z_2_rangeb;
00408     int16_t tp_uwr_med_corr_z_3_rangea;
00409     int16_t tp_uwr_med_corr_z_3_rangeb;
00410     int16_t tp_uwr_med_corr_z_4_rangea;
00411     int16_t tp_uwr_med_corr_z_4_rangeb;
00412     int16_t tp_uwr_med_corr_z_5_rangea;
00413     int16_t tp_uwr_med_corr_z_5_rangeb;
00414     int16_t tp_uwr_med_corr_z_6_rangea;
00415     int16_t tp_uwr_med_corr_z_6_rangeb;
00416     int16_t tp_uwr_lng_z_1_min;
00417     int16_t tp_uwr_lng_z_1_max;
00418     int16_t tp_uwr_lng_z_2_min;
00419     int16_t tp_uwr_lng_z_2_max;
00420     int16_t tp_uwr_lng_z_3_min;
00421     int16_t tp_uwr_lng_z_3_max;
00422     int16_t tp_uwr_lng_z_4_min;
00423     int16_t tp_uwr_lng_z_4_max;
00424     int16_t tp_uwr_lng_z_5_min;
00425     int16_t tp_uwr_lng_z_5_max;
00426     int16_t tp_uwr_lng_corr_z_1_rangea;
00427     int16_t tp_uwr_lng_corr_z_1_rangeb;
00428     int16_t tp_uwr_lng_corr_z_2_rangea;
00429     int16_t tp_uwr_lng_corr_z_2_rangeb;
00430     int16_t tp_uwr_lng_corr_z_3_rangea;
00431     int16_t tp_uwr_lng_corr_z_3_rangeb;
00432     int16_t tp_uwr_lng_corr_z_4_rangea;
00433     int16_t tp_uwr_lng_corr_z_4_rangeb;
00434     int16_t tp_uwr_lng_corr_z_5_rangea;
00435     int16_t tp_uwr_lng_corr_z_5_rangeb;
00436 
00437 } VL53L1_tuning_parm_storage_t;
00438 
00439 
00440 
00441 
00442 
00443 typedef struct {
00444 
00445     uint8_t   x_centre;
00446     uint8_t   y_centre;
00447 
00448 } VL53L1_optical_centre_t;
00449 
00450 
00451 
00452 
00453 typedef struct {
00454 
00455     uint8_t   x_centre;
00456     uint8_t   y_centre;
00457     uint8_t   width;
00458     uint8_t   height;
00459 
00460 } VL53L1_user_zone_t;
00461 
00462 
00463 
00464 
00465 typedef struct {
00466 
00467     uint8_t             max_zones;
00468     uint8_t             active_zones;
00469 
00470 
00471 
00472 VL53L1_histogram_config_t multizone_hist_cfg;
00473 
00474     VL53L1_user_zone_t user_zones[VL53L1_MAX_USER_ZONES];
00475 
00476 
00477     uint8_t bin_config[VL53L1_MAX_USER_ZONES];
00478 
00479 
00480 } VL53L1_zone_config_t;
00481 
00482 
00483 
00484 typedef struct {
00485 
00486 
00487     VL53L1_GPIO_Interrupt_Mode  intr_mode_distance;
00488 
00489 
00490     VL53L1_GPIO_Interrupt_Mode  intr_mode_rate;
00491 
00492 
00493     uint8_t             intr_new_measure_ready;
00494 
00495 
00496     uint8_t             intr_no_target;
00497 
00498 
00499     uint8_t             intr_combined_mode;
00500 
00501 
00502 
00503 
00504 
00505     uint16_t            threshold_distance_high;
00506 
00507 
00508     uint16_t            threshold_distance_low;
00509 
00510 
00511     uint16_t            threshold_rate_high;
00512 
00513 
00514     uint16_t            threshold_rate_low;
00515 
00516 } VL53L1_GPIO_interrupt_config_t;
00517 
00518 
00519 
00520 
00521 typedef struct {
00522 
00523 
00524     uint8_t     vhv_loop_bound;
00525 
00526 
00527     uint8_t     is_low_power_auto_mode;
00528 
00529 
00530     uint8_t     low_power_auto_range_count;
00531 
00532 
00533     uint8_t     saved_interrupt_config;
00534 
00535 
00536     uint8_t     saved_vhv_init;
00537 
00538 
00539     uint8_t     saved_vhv_timeout;
00540 
00541 
00542     uint8_t     first_run_phasecal_result;
00543 
00544 
00545     uint32_t    dss__total_rate_per_spad_mcps;
00546 
00547 
00548     uint16_t    dss__required_spads;
00549 
00550 } VL53L1_low_power_auto_data_t;
00551 
00552 
00553 
00554 
00555 
00556 
00557 
00558 typedef struct {
00559 
00560 
00561     uint8_t smudge_corr_enabled;
00562 
00563 
00564     uint8_t smudge_corr_apply_enabled;
00565 
00566 
00567     uint8_t smudge_corr_single_apply;
00568 
00569 
00570 
00571 
00572     uint16_t    smudge_margin;
00573 
00574 
00575     uint32_t    noise_margin;
00576 
00577 
00578     uint32_t    user_xtalk_offset_limit;
00579 
00580 
00581     uint8_t user_xtalk_offset_limit_hi;
00582 
00583 
00584     uint32_t    sample_limit;
00585 
00586 
00587     uint32_t    single_xtalk_delta;
00588 
00589 
00590     uint32_t    averaged_xtalk_delta;
00591 
00592 
00593     uint32_t    smudge_corr_clip_limit;
00594 
00595 
00596     uint32_t    smudge_corr_ambient_threshold;
00597 
00598 
00599     uint8_t scaler_calc_method;
00600 
00601 
00602     int16_t x_gradient_scaler;
00603 
00604 
00605     int16_t y_gradient_scaler;
00606 
00607 
00608     uint8_t user_scaler_set;
00609 
00610 
00611     uint32_t nodetect_ambient_threshold;
00612 
00613 
00614     uint32_t nodetect_sample_limit;
00615 
00616 
00617     uint32_t nodetect_xtalk_offset;
00618 
00619 
00620     uint16_t nodetect_min_range_mm;
00621 
00622 
00623     uint32_t max_smudge_factor;
00624 
00625 } VL53L1_smudge_corrector_config_t;
00626 
00627 
00628 
00629 typedef struct {
00630 
00631 
00632     uint32_t    current_samples;
00633 
00634 
00635     uint32_t    required_samples;
00636 
00637 
00638     uint64_t    accumulator;
00639 
00640 
00641     uint32_t    nodetect_counter;
00642 
00643 } VL53L1_smudge_corrector_internals_t;
00644 
00645 
00646 
00647 typedef struct {
00648 
00649 
00650     uint8_t smudge_corr_valid;
00651 
00652 
00653     uint8_t smudge_corr_clipped;
00654 
00655 
00656     uint8_t single_xtalk_delta_flag;
00657 
00658 
00659     uint8_t averaged_xtalk_delta_flag;
00660 
00661 
00662     uint8_t sample_limit_exceeded_flag;
00663 
00664 
00665     uint8_t gradient_zero_flag;
00666 
00667 
00668     uint8_t new_xtalk_applied_flag;
00669 
00670 
00671     uint32_t  algo__crosstalk_compensation_plane_offset_kcps;
00672 
00673 
00674     int16_t   algo__crosstalk_compensation_x_plane_gradient_kcps;
00675 
00676 
00677     int16_t   algo__crosstalk_compensation_y_plane_gradient_kcps;
00678 
00679 
00680 } VL53L1_smudge_corrector_data_t;
00681 
00682 
00683 
00684 
00685 
00686 typedef struct {
00687 
00688 
00689 
00690     uint8_t  range_id;
00691 
00692     uint32_t time_stamp;
00693 
00694     uint8_t  VL53L1_p_015;
00695 
00696     uint8_t  VL53L1_p_022;
00697 
00698     uint8_t  VL53L1_p_025;
00699 
00700     uint8_t  VL53L1_p_026;
00701 
00702     uint8_t  VL53L1_p_016;
00703 
00704     uint8_t  VL53L1_p_027;
00705 
00706 
00707     uint16_t   width;
00708 
00709     uint8_t    VL53L1_p_030;
00710 
00711 
00712     uint16_t   fast_osc_frequency;
00713 
00714     uint16_t   zero_distance_phase;
00715 
00716     uint16_t   VL53L1_p_006;
00717 
00718 
00719     uint32_t   total_periods_elapsed;
00720 
00721 
00722     uint32_t   peak_duration_us;
00723 
00724 
00725     uint32_t   woi_duration_us;
00726 
00727 
00728 
00729 
00730 
00731     uint32_t   VL53L1_p_020;
00732 
00733     uint32_t   VL53L1_p_021;
00734 
00735     int32_t    VL53L1_p_013;
00736 
00737 
00738 
00739 
00740     uint16_t    peak_signal_count_rate_mcps;
00741 
00742     uint16_t    avg_signal_count_rate_mcps;
00743 
00744     uint16_t    ambient_count_rate_mcps;
00745 
00746     uint16_t    total_rate_per_spad_mcps;
00747 
00748     uint32_t    VL53L1_p_012;
00749 
00750 
00751 
00752 
00753     uint16_t   VL53L1_p_005;
00754 
00755 
00756 
00757 
00758     uint16_t   VL53L1_p_028;
00759 
00760     uint16_t   VL53L1_p_014;
00761 
00762     uint16_t   VL53L1_p_029;
00763 
00764 
00765 
00766 
00767     int16_t    min_range_mm;
00768 
00769     int16_t    median_range_mm;
00770 
00771     int16_t    max_range_mm;
00772 
00773 
00774 
00775 
00776     uint8_t    range_status;
00777 
00778 } VL53L1_range_data_t;
00779 
00780 
00781 
00782 
00783 typedef struct {
00784 
00785     VL53L1_DeviceState     cfg_device_state;
00786 
00787     VL53L1_DeviceState     rd_device_state;
00788 
00789     uint8_t                zone_id;
00790 
00791     uint8_t                stream_count;
00792 
00793 
00794     int16_t                VL53L1_p_007[VL53L1_MAX_AMBIENT_DMAX_VALUES];
00795 
00796     int16_t                wrap_dmax_mm;
00797 
00798 
00799     uint8_t                device_status;
00800 
00801 
00802     uint8_t                max_results;
00803 
00804     uint8_t                active_results;
00805 
00806     VL53L1_range_data_t    VL53L1_p_002[VL53L1_MAX_RANGE_RESULTS];
00807 
00808     VL53L1_range_data_t    xmonitor;
00809 
00810     VL53L1_smudge_corrector_data_t smudge_corrector_data;
00811 
00812 
00813 
00814 } VL53L1_range_results_t;
00815 
00816 
00817 
00818 
00819 typedef struct {
00820 
00821     uint8_t    no_of_samples;
00822 
00823     uint32_t   rate_per_spad_kcps_sum;
00824 
00825     uint32_t   rate_per_spad_kcps_avg;
00826 
00827     int32_t    signal_total_events_sum;
00828 
00829     int32_t    signal_total_events_avg;
00830 
00831     uint32_t   sigma_mm_sum;
00832 
00833     uint32_t   sigma_mm_avg;
00834 
00835     uint32_t   median_phase_sum;
00836 
00837     uint32_t   median_phase_avg;
00838 
00839 
00840 } VL53L1_xtalk_range_data_t;
00841 
00842 
00843 
00844 
00845 typedef struct {
00846 
00847     VL53L1_Error                cal_status;
00848 
00849     uint8_t                     num_of_samples_status;
00850 
00851     uint8_t                     zero_samples_status;
00852 
00853     uint8_t                     max_sigma_status;
00854 
00855     uint8_t                     max_results;
00856 
00857     uint8_t                     active_results;
00858 
00859 
00860     VL53L1_xtalk_range_data_t
00861         VL53L1_p_002[VL53L1_MAX_XTALK_RANGE_RESULTS];
00862 
00863     VL53L1_histogram_bin_data_t central_histogram_sum;
00864 
00865     VL53L1_histogram_bin_data_t central_histogram_avg;
00866 
00867     uint8_t central_histogram__window_start;
00868 
00869     uint8_t central_histogram__window_end;
00870 
00871     VL53L1_histogram_bin_data_t
00872         histogram_avg_1[VL53L1_MAX_XTALK_RANGE_RESULTS];
00873 
00874     VL53L1_histogram_bin_data_t
00875         histogram_avg_2[VL53L1_MAX_XTALK_RANGE_RESULTS];
00876 
00877     VL53L1_histogram_bin_data_t
00878         xtalk_avg[VL53L1_MAX_XTALK_RANGE_RESULTS];
00879 
00880 
00881 } VL53L1_xtalk_range_results_t;
00882 
00883 
00884 
00885 
00886 typedef struct {
00887 
00888     uint8_t    preset_mode;
00889 
00890     uint8_t    dss_config__roi_mode_control;
00891 
00892     uint16_t   dss_config__manual_effective_spads_select;
00893 
00894     uint8_t    no_of_samples;
00895 
00896     uint32_t   effective_spads;
00897 
00898     uint32_t   peak_rate_mcps;
00899 
00900     uint32_t   VL53L1_p_005;
00901 
00902     int32_t    median_range_mm;
00903 
00904     int32_t    range_mm_offset;
00905 
00906 
00907 } VL53L1_offset_range_data_t;
00908 
00909 
00910 
00911 
00912 typedef struct {
00913 
00914     int16_t      cal_distance_mm;
00915 
00916     uint16_t     cal_reflectance_pc;
00917 
00918     VL53L1_Error cal_status;
00919 
00920     uint8_t      cal_report;
00921 
00922     uint8_t      max_results;
00923 
00924     uint8_t      active_results;
00925 
00926     VL53L1_offset_range_data_t
00927         VL53L1_p_002[VL53L1_MAX_OFFSET_RANGE_RESULTS];
00928 
00929 
00930 } VL53L1_offset_range_results_t;
00931 
00932 
00933 
00934 
00935 typedef struct {
00936 
00937     uint16_t  result__mm_inner_actual_effective_spads;
00938 
00939     uint16_t  result__mm_outer_actual_effective_spads;
00940 
00941     uint16_t  result__mm_inner_peak_signal_count_rtn_mcps;
00942 
00943     uint16_t  result__mm_outer_peak_signal_count_rtn_mcps;
00944 
00945 
00946 } VL53L1_additional_offset_cal_data_t;
00947 
00948 
00949 
00950 typedef struct {
00951     int16_t   short_a_offset_mm;
00952     int16_t   short_b_offset_mm;
00953     int16_t   medium_a_offset_mm;
00954     int16_t   medium_b_offset_mm;
00955     int16_t   long_a_offset_mm;
00956     int16_t   long_b_offset_mm;
00957 } VL53L1_per_vcsel_period_offset_cal_data_t;
00958 
00959 
00960 
00961 
00962 
00963 typedef struct {
00964 
00965     uint32_t   VL53L1_p_020;
00966 
00967     uint32_t   VL53L1_p_021;
00968 
00969     uint16_t   VL53L1_p_014;
00970 
00971     uint8_t    range_status;
00972 
00973 
00974 } VL53L1_object_data_t;
00975 
00976 
00977 
00978 
00979 typedef struct {
00980 
00981     VL53L1_DeviceState     cfg_device_state;
00982 
00983     VL53L1_DeviceState     rd_device_state;
00984 
00985     uint8_t                zone_id;
00986 
00987     uint8_t                stream_count;
00988 
00989     uint8_t                max_objects;
00990 
00991     uint8_t                active_objects;
00992 
00993     VL53L1_object_data_t   VL53L1_p_002[VL53L1_MAX_RANGE_RESULTS];
00994 
00995 
00996     VL53L1_object_data_t   xmonitor;
00997 
00998 
00999 } VL53L1_zone_objects_t;
01000 
01001 
01002 
01003 
01004 
01005 
01006 typedef struct {
01007 
01008     uint8_t                max_zones;
01009 
01010     uint8_t                active_zones;
01011 
01012     VL53L1_zone_objects_t VL53L1_p_002[VL53L1_MAX_USER_ZONES];
01013 
01014 
01015 } VL53L1_zone_results_t;
01016 
01017 
01018 
01019 
01020 typedef struct {
01021 
01022     VL53L1_DeviceState     rd_device_state;
01023 
01024 
01025     uint8_t  number_of_ambient_bins;
01026 
01027 
01028     uint16_t result__dss_actual_effective_spads;
01029 
01030     uint8_t  VL53L1_p_009;
01031 
01032     uint32_t total_periods_elapsed;
01033 
01034 
01035     int32_t  ambient_events_sum;
01036 
01037 
01038 } VL53L1_zone_hist_info_t;
01039 
01040 
01041 
01042 
01043 typedef struct {
01044 
01045     uint8_t                     max_zones;
01046 
01047     uint8_t                     active_zones;
01048 
01049     VL53L1_zone_hist_info_t     VL53L1_p_002[VL53L1_MAX_USER_ZONES];
01050 
01051 
01052 } VL53L1_zone_histograms_t;
01053 
01054 
01055 
01056 
01057 typedef struct {
01058 
01059     uint32_t   no_of_samples;
01060 
01061     uint32_t   effective_spads;
01062 
01063     uint32_t   peak_rate_mcps;
01064 
01065     uint32_t   VL53L1_p_014;
01066 
01067     uint32_t   VL53L1_p_005;
01068 
01069     int32_t    median_range_mm;
01070 
01071     int32_t    range_mm_offset;
01072 
01073 
01074 } VL53L1_zone_calibration_data_t;
01075 
01076 
01077 
01078 
01079 
01080 
01081 typedef struct {
01082 
01083     uint32_t                         struct_version;
01084 
01085     VL53L1_DevicePresetModes         preset_mode;
01086 
01087     VL53L1_DeviceZonePreset          zone_preset;
01088 
01089     int16_t                          cal_distance_mm;
01090 
01091     uint16_t                         cal_reflectance_pc;
01092 
01093     uint16_t                         phasecal_result__reference_phase;
01094 
01095     uint16_t                         zero_distance_phase;
01096 
01097     VL53L1_Error                     cal_status;
01098 
01099     uint8_t                          max_zones;
01100 
01101     uint8_t                          active_zones;
01102 
01103     VL53L1_zone_calibration_data_t   VL53L1_p_002[VL53L1_MAX_USER_ZONES];
01104 
01105 
01106 } VL53L1_zone_calibration_results_t;
01107 
01108 
01109 
01110 
01111 
01112 typedef struct {
01113 
01114     int16_t     cal_distance_mm;
01115 
01116     uint16_t    cal_reflectance_pc;
01117 
01118     uint16_t    max_samples;
01119 
01120     uint16_t    width;
01121 
01122     uint16_t    height;
01123 
01124     uint16_t    peak_rate_mcps[VL53L1_NVM_PEAK_RATE_MAP_SAMPLES];
01125 
01126 
01127 } VL53L1_cal_peak_rate_map_t;
01128 
01129 
01130 
01131 
01132 typedef struct {
01133 
01134     uint8_t      expected_stream_count;
01135 
01136     uint8_t      expected_gph_id;
01137 
01138     uint8_t      dss_mode;
01139 
01140     uint16_t     dss_requested_effective_spad_count;
01141 
01142     uint8_t      seed_cfg;
01143 
01144     uint8_t      initial_phase_seed;
01145 
01146 
01147     uint8_t  roi_config__user_roi_centre_spad;
01148 
01149     uint8_t  roi_config__user_roi_requested_global_xy_size;
01150 
01151 
01152 } VL53L1_zone_private_dyn_cfg_t;
01153 
01154 
01155 
01156 
01157 typedef struct {
01158 
01159     uint8_t                     max_zones;
01160 
01161     uint8_t                     active_zones;
01162 
01163     VL53L1_zone_private_dyn_cfg_t VL53L1_p_002[VL53L1_MAX_USER_ZONES];
01164 
01165 
01166 } VL53L1_zone_private_dyn_cfgs_t;
01167 
01168 
01169 
01170 typedef struct {
01171 
01172     uint32_t  algo__crosstalk_compensation_plane_offset_kcps;
01173 
01174     int16_t   algo__crosstalk_compensation_x_plane_gradient_kcps;
01175 
01176     int16_t   algo__crosstalk_compensation_y_plane_gradient_kcps;
01177 
01178     uint32_t  algo__xtalk_cpo_HistoMerge_kcps[VL53L1_BIN_REC_SIZE];
01179 
01180 
01181 } VL53L1_xtalk_calibration_results_t;
01182 
01183 
01184 
01185 
01186 typedef struct {
01187 
01188 
01189     uint32_t   sample_count;
01190 
01191 
01192     uint32_t   pll_period_mm;
01193 
01194 
01195     uint32_t   peak_duration_us_sum;
01196 
01197 
01198     uint32_t   effective_spad_count_sum;
01199 
01200 
01201     uint32_t   zero_distance_phase_sum;
01202 
01203 
01204     uint32_t   zero_distance_phase_avg;
01205 
01206 
01207     int32_t    event_scaler_sum;
01208 
01209 
01210     int32_t    event_scaler_avg;
01211 
01212 
01213     int32_t   signal_events_sum;
01214 
01215 
01216     uint32_t  xtalk_rate_kcps_per_spad;
01217 
01218 
01219     int32_t   xtalk_start_phase;
01220 
01221 
01222     int32_t   xtalk_end_phase;
01223 
01224 
01225     int32_t   xtalk_width_phase;
01226 
01227 
01228     int32_t   target_start_phase;
01229 
01230 
01231     int32_t   target_end_phase;
01232 
01233 
01234     int32_t   target_width_phase;
01235 
01236 
01237     int32_t   effective_width;
01238 
01239 
01240     int32_t   event_scaler;
01241 
01242 
01243     uint8_t   VL53L1_p_015;
01244 
01245 
01246     uint8_t   VL53L1_p_016;
01247 
01248 
01249     uint8_t   target_start;
01250 
01251 
01252     int32_t   max_shape_value;
01253 
01254 
01255     int32_t   bin_data_sums[VL53L1_XTALK_HISTO_BINS];
01256 
01257 } VL53L1_hist_xtalk_extract_data_t;
01258 
01259 
01260 
01261 
01262 typedef struct {
01263 
01264     uint16_t   standard_ranging_gain_factor;
01265 
01266     uint16_t   histogram_ranging_gain_factor;
01267 
01268 
01269 } VL53L1_gain_calibration_data_t;
01270 
01271 
01272 
01273 
01274 typedef struct {
01275 
01276     VL53L1_DeviceState   cfg_device_state;
01277 
01278     uint8_t   cfg_stream_count;
01279 
01280     uint8_t   cfg_internal_stream_count;
01281 
01282     uint8_t   cfg_internal_stream_count_val;
01283 
01284     uint8_t   cfg_gph_id;
01285 
01286     uint8_t   cfg_timing_status;
01287 
01288     uint8_t   cfg_zone_id;
01289 
01290 
01291     VL53L1_DeviceState   rd_device_state;
01292 
01293     uint8_t   rd_stream_count;
01294 
01295     uint8_t   rd_internal_stream_count;
01296 
01297     uint8_t   rd_internal_stream_count_val;
01298 
01299     uint8_t   rd_gph_id;
01300 
01301     uint8_t   rd_timing_status;
01302 
01303     uint8_t   rd_zone_id;
01304 
01305 
01306 } VL53L1_ll_driver_state_t;
01307 
01308 
01309 
01310 
01311 typedef struct {
01312 
01313     uint8_t   wait_method;
01314 
01315     VL53L1_DevicePresetModes        preset_mode;
01316 
01317     VL53L1_DeviceZonePreset         zone_preset;
01318 
01319     VL53L1_DeviceMeasurementModes   measurement_mode;
01320 
01321     VL53L1_OffsetCalibrationMode    offset_calibration_mode;
01322 
01323     VL53L1_OffsetCorrectionMode     offset_correction_mode;
01324 
01325     VL53L1_DeviceDmaxMode           dmax_mode;
01326 
01327     uint32_t  phasecal_config_timeout_us;
01328 
01329     uint32_t  mm_config_timeout_us;
01330 
01331     uint32_t  range_config_timeout_us;
01332 
01333     uint32_t  inter_measurement_period_ms;
01334 
01335     uint16_t  dss_config__target_total_rate_mcps;
01336 
01337     uint32_t  fw_ready_poll_duration_ms;
01338 
01339     uint8_t   fw_ready;
01340 
01341     uint8_t   debug_mode;
01342 
01343 
01344 
01345     VL53L1_ll_version_t                 version;
01346 
01347 
01348     VL53L1_ll_driver_state_t            ll_state;
01349 
01350 
01351     VL53L1_GPIO_interrupt_config_t      gpio_interrupt_config;
01352 
01353 
01354     VL53L1_customer_nvm_managed_t       customer;
01355     VL53L1_cal_peak_rate_map_t          cal_peak_rate_map;
01356     VL53L1_additional_offset_cal_data_t add_off_cal_data;
01357     VL53L1_dmax_calibration_data_t      fmt_dmax_cal;
01358     VL53L1_dmax_calibration_data_t      cust_dmax_cal;
01359     VL53L1_gain_calibration_data_t      gain_cal;
01360     VL53L1_user_zone_t                  mm_roi;
01361     VL53L1_optical_centre_t             optical_centre;
01362     VL53L1_zone_config_t                zone_cfg;
01363 
01364 
01365     VL53L1_tuning_parm_storage_t        tuning_parms;
01366 
01367 
01368     uint8_t rtn_good_spads[VL53L1_RTN_SPAD_BUFFER_SIZE];
01369 
01370 
01371     VL53L1_refspadchar_config_t         refspadchar;
01372     VL53L1_ssc_config_t                 ssc_cfg;
01373     VL53L1_hist_post_process_config_t   histpostprocess;
01374     VL53L1_hist_gen3_dmax_config_t      dmax_cfg;
01375     VL53L1_xtalkextract_config_t        xtalk_extract_cfg;
01376     VL53L1_xtalk_config_t               xtalk_cfg;
01377     VL53L1_offsetcal_config_t           offsetcal_cfg;
01378     VL53L1_zonecal_config_t             zonecal_cfg;
01379 
01380 
01381     VL53L1_static_nvm_managed_t         stat_nvm;
01382     VL53L1_histogram_config_t           hist_cfg;
01383     VL53L1_static_config_t              stat_cfg;
01384     VL53L1_general_config_t             gen_cfg;
01385     VL53L1_timing_config_t              tim_cfg;
01386     VL53L1_dynamic_config_t             dyn_cfg;
01387     VL53L1_system_control_t             sys_ctrl;
01388     VL53L1_system_results_t             sys_results;
01389     VL53L1_nvm_copy_data_t              nvm_copy_data;
01390 
01391 
01392     VL53L1_histogram_bin_data_t         hist_data;
01393     VL53L1_histogram_bin_data_t         hist_xtalk;
01394 
01395 
01396     VL53L1_xtalk_histogram_data_t       xtalk_shapes;
01397     VL53L1_xtalk_range_results_t        xtalk_results;
01398     VL53L1_xtalk_calibration_results_t  xtalk_cal;
01399     VL53L1_hist_xtalk_extract_data_t    xtalk_extract;
01400 
01401 
01402     VL53L1_offset_range_results_t       offset_results;
01403 
01404 
01405     VL53L1_core_results_t               core_results;
01406     VL53L1_debug_results_t              dbg_results;
01407 
01408     VL53L1_smudge_corrector_config_t    smudge_correct_config;
01409 
01410     VL53L1_smudge_corrector_internals_t smudge_corrector_internals;
01411 
01412 
01413 
01414 
01415     VL53L1_low_power_auto_data_t        low_power_auto_data;
01416 
01417 
01418 #ifdef PAL_EXTENDED
01419 
01420     VL53L1_patch_results_t                patch_results;
01421     VL53L1_shadow_core_results_t          shadow_core_results;
01422     VL53L1_shadow_system_results_t        shadow_sys_results;
01423     VL53L1_prev_shadow_core_results_t     prev_shadow_core_results;
01424     VL53L1_prev_shadow_system_results_t   prev_shadow_sys_results;
01425 #endif
01426     uint8_t  wArea1[1536];
01427     uint8_t  wArea2[512];
01428     VL53L1_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data;
01429 
01430     uint8_t bin_rec_pos;
01431 
01432     uint8_t pos_before_next_recom;
01433 
01434     int32_t multi_bins_rec[VL53L1_BIN_REC_SIZE]
01435         [VL53L1_TIMING_CONF_A_B_SIZE][VL53L1_HISTOGRAM_BUFFER_SIZE];
01436 
01437     int16_t PreviousRangeMilliMeter[VL53L1_MAX_RANGE_RESULTS];
01438     uint8_t PreviousRangeStatus[VL53L1_MAX_RANGE_RESULTS];
01439     uint8_t PreviousExtendedRange[VL53L1_MAX_RANGE_RESULTS];
01440     uint8_t PreviousStreamCount;
01441 
01442 } VL53L1_LLDriverData_t;
01443 
01444 
01445 
01446 
01447 typedef struct {
01448 
01449 
01450     VL53L1_range_results_t             range_results;
01451 
01452 
01453     VL53L1_zone_private_dyn_cfgs_t     zone_dyn_cfgs;
01454 
01455 
01456     VL53L1_zone_results_t              zone_results;
01457     VL53L1_zone_histograms_t           zone_hists;
01458     VL53L1_zone_calibration_results_t  zone_cal;
01459 
01460 } VL53L1_LLDriverResults_t;
01461 
01462 
01463 
01464 
01465 typedef struct {
01466 
01467     uint32_t                             struct_version;
01468     VL53L1_customer_nvm_managed_t        customer;
01469     VL53L1_dmax_calibration_data_t       fmt_dmax_cal;
01470     VL53L1_dmax_calibration_data_t       cust_dmax_cal;
01471     VL53L1_additional_offset_cal_data_t  add_off_cal_data;
01472     VL53L1_optical_centre_t              optical_centre;
01473     VL53L1_xtalk_histogram_data_t        xtalkhisto;
01474     VL53L1_gain_calibration_data_t       gain_cal;
01475     VL53L1_cal_peak_rate_map_t           cal_peak_rate_map;
01476     VL53L1_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data;
01477 
01478 } VL53L1_calibration_data_t;
01479 
01480 
01481 
01482 
01483 typedef struct {
01484 
01485     VL53L1_customer_nvm_managed_t        customer;
01486     VL53L1_xtalkextract_config_t         xtalk_extract_cfg;
01487     VL53L1_xtalk_config_t                xtalk_cfg;
01488     VL53L1_histogram_bin_data_t          hist_data;
01489     VL53L1_xtalk_histogram_data_t        xtalk_shapes;
01490     VL53L1_xtalk_range_results_t         xtalk_results;
01491 
01492 } VL53L1_xtalk_debug_data_t;
01493 
01494 
01495 
01496 
01497 typedef struct {
01498 
01499     VL53L1_customer_nvm_managed_t        customer;
01500     VL53L1_dmax_calibration_data_t       fmt_dmax_cal;
01501     VL53L1_dmax_calibration_data_t       cust_dmax_cal;
01502     VL53L1_additional_offset_cal_data_t  add_off_cal_data;
01503     VL53L1_offset_range_results_t        offset_results;
01504 
01505 } VL53L1_offset_debug_data_t;
01506 
01507 
01508 
01509 
01510 typedef struct {
01511     uint16_t        vl53l1_tuningparm_version;
01512     uint16_t        vl53l1_tuningparm_key_table_version;
01513     uint16_t        vl53l1_tuningparm_lld_version;
01514     uint8_t        vl53l1_tuningparm_hist_algo_select;
01515     uint8_t        vl53l1_tuningparm_hist_target_order;
01516     uint8_t        vl53l1_tuningparm_hist_filter_woi_0;
01517     uint8_t        vl53l1_tuningparm_hist_filter_woi_1;
01518     uint8_t        vl53l1_tuningparm_hist_amb_est_method;
01519     uint8_t        vl53l1_tuningparm_hist_amb_thresh_sigma_0;
01520     uint8_t        vl53l1_tuningparm_hist_amb_thresh_sigma_1;
01521     int32_t        vl53l1_tuningparm_hist_min_amb_thresh_events;
01522     uint16_t        vl53l1_tuningparm_hist_amb_events_scaler;
01523     uint16_t        vl53l1_tuningparm_hist_noise_threshold;
01524     int32_t        vl53l1_tuningparm_hist_signal_total_events_limit;
01525     uint8_t        vl53l1_tuningparm_hist_sigma_est_ref_mm;
01526     uint16_t        vl53l1_tuningparm_hist_sigma_thresh_mm;
01527     uint16_t        vl53l1_tuningparm_hist_gain_factor;
01528     uint8_t        vl53l1_tuningparm_consistency_hist_phase_tolerance;
01529     uint16_t  vl53l1_tuningparm_consistency_hist_min_max_tolerance_mm;
01530     uint8_t        vl53l1_tuningparm_consistency_hist_event_sigma;
01531     uint16_t  vl53l1_tuningparm_consistency_hist_event_sigma_min_spad_limit;
01532     uint8_t        vl53l1_tuningparm_initial_phase_rtn_histo_long_range;
01533     uint8_t        vl53l1_tuningparm_initial_phase_rtn_histo_med_range;
01534     uint8_t        vl53l1_tuningparm_initial_phase_rtn_histo_short_range;
01535     uint8_t        vl53l1_tuningparm_initial_phase_ref_histo_long_range;
01536     uint8_t        vl53l1_tuningparm_initial_phase_ref_histo_med_range;
01537     uint8_t        vl53l1_tuningparm_initial_phase_ref_histo_short_range;
01538     int16_t        vl53l1_tuningparm_xtalk_detect_min_valid_range_mm;
01539     int16_t        vl53l1_tuningparm_xtalk_detect_max_valid_range_mm;
01540     uint16_t        vl53l1_tuningparm_xtalk_detect_max_sigma_mm;
01541     uint16_t        vl53l1_tuningparm_xtalk_detect_min_max_tolerance;
01542     uint16_t        vl53l1_tuningparm_xtalk_detect_max_valid_rate_kcps;
01543     uint8_t        vl53l1_tuningparm_xtalk_detect_event_sigma;
01544     int16_t        vl53l1_tuningparm_hist_xtalk_margin_kcps;
01545     uint8_t        vl53l1_tuningparm_consistency_lite_phase_tolerance;
01546     uint8_t        vl53l1_tuningparm_phasecal_target;
01547     uint16_t        vl53l1_tuningparm_lite_cal_repeat_rate;
01548     uint16_t        vl53l1_tuningparm_lite_ranging_gain_factor;
01549     uint8_t        vl53l1_tuningparm_lite_min_clip_mm;
01550     uint16_t        vl53l1_tuningparm_lite_long_sigma_thresh_mm;
01551     uint16_t        vl53l1_tuningparm_lite_med_sigma_thresh_mm;
01552     uint16_t        vl53l1_tuningparm_lite_short_sigma_thresh_mm;
01553     uint16_t        vl53l1_tuningparm_lite_long_min_count_rate_rtn_mcps;
01554     uint16_t        vl53l1_tuningparm_lite_med_min_count_rate_rtn_mcps;
01555     uint16_t        vl53l1_tuningparm_lite_short_min_count_rate_rtn_mcps;
01556     uint8_t        vl53l1_tuningparm_lite_sigma_est_pulse_width;
01557     uint8_t        vl53l1_tuningparm_lite_sigma_est_amb_width_ns;
01558     uint8_t        vl53l1_tuningparm_lite_sigma_ref_mm;
01559     uint8_t        vl53l1_tuningparm_lite_rit_mult;
01560     uint8_t        vl53l1_tuningparm_lite_seed_config;
01561     uint8_t        vl53l1_tuningparm_lite_quantifier;
01562     uint8_t        vl53l1_tuningparm_lite_first_order_select;
01563     int16_t        vl53l1_tuningparm_lite_xtalk_margin_kcps;
01564     uint8_t        vl53l1_tuningparm_initial_phase_rtn_lite_long_range;
01565     uint8_t        vl53l1_tuningparm_initial_phase_rtn_lite_med_range;
01566     uint8_t        vl53l1_tuningparm_initial_phase_rtn_lite_short_range;
01567     uint8_t        vl53l1_tuningparm_initial_phase_ref_lite_long_range;
01568     uint8_t        vl53l1_tuningparm_initial_phase_ref_lite_med_range;
01569     uint8_t        vl53l1_tuningparm_initial_phase_ref_lite_short_range;
01570     uint8_t        vl53l1_tuningparm_timed_seed_config;
01571     uint8_t        vl53l1_tuningparm_dmax_cfg_signal_thresh_sigma;
01572     uint16_t        vl53l1_tuningparm_dmax_cfg_reflectance_array_0;
01573     uint16_t        vl53l1_tuningparm_dmax_cfg_reflectance_array_1;
01574     uint16_t        vl53l1_tuningparm_dmax_cfg_reflectance_array_2;
01575     uint16_t        vl53l1_tuningparm_dmax_cfg_reflectance_array_3;
01576     uint16_t        vl53l1_tuningparm_dmax_cfg_reflectance_array_4;
01577     uint8_t        vl53l1_tuningparm_vhv_loopbound;
01578     uint8_t        vl53l1_tuningparm_refspadchar_device_test_mode;
01579     uint8_t        vl53l1_tuningparm_refspadchar_vcsel_period;
01580     uint32_t        vl53l1_tuningparm_refspadchar_phasecal_timeout_us;
01581     uint16_t        vl53l1_tuningparm_refspadchar_target_count_rate_mcps;
01582     uint16_t        vl53l1_tuningparm_refspadchar_min_countrate_limit_mcps;
01583     uint16_t        vl53l1_tuningparm_refspadchar_max_countrate_limit_mcps;
01584     uint8_t        vl53l1_tuningparm_xtalk_extract_num_of_samples;
01585     int16_t        vl53l1_tuningparm_xtalk_extract_min_filter_thresh_mm;
01586     int16_t        vl53l1_tuningparm_xtalk_extract_max_filter_thresh_mm;
01587     uint16_t        vl53l1_tuningparm_xtalk_extract_dss_rate_mcps;
01588     uint32_t        vl53l1_tuningparm_xtalk_extract_phasecal_timeout_us;
01589     uint16_t        vl53l1_tuningparm_xtalk_extract_max_valid_rate_kcps;
01590     uint16_t        vl53l1_tuningparm_xtalk_extract_sigma_threshold_mm;
01591     uint32_t        vl53l1_tuningparm_xtalk_extract_dss_timeout_us;
01592     uint32_t        vl53l1_tuningparm_xtalk_extract_bin_timeout_us;
01593     uint16_t        vl53l1_tuningparm_offset_cal_dss_rate_mcps;
01594     uint32_t        vl53l1_tuningparm_offset_cal_phasecal_timeout_us;
01595     uint32_t        vl53l1_tuningparm_offset_cal_mm_timeout_us;
01596     uint32_t        vl53l1_tuningparm_offset_cal_range_timeout_us;
01597     uint8_t        vl53l1_tuningparm_offset_cal_pre_samples;
01598     uint8_t        vl53l1_tuningparm_offset_cal_mm1_samples;
01599     uint8_t        vl53l1_tuningparm_offset_cal_mm2_samples;
01600     uint16_t        vl53l1_tuningparm_zone_cal_dss_rate_mcps;
01601     uint32_t        vl53l1_tuningparm_zone_cal_phasecal_timeout_us;
01602     uint32_t        vl53l1_tuningparm_zone_cal_dss_timeout_us;
01603     uint16_t        vl53l1_tuningparm_zone_cal_phasecal_num_samples;
01604     uint32_t        vl53l1_tuningparm_zone_cal_range_timeout_us;
01605     uint16_t        vl53l1_tuningparm_zone_cal_zone_num_samples;
01606     uint8_t        vl53l1_tuningparm_spadmap_vcsel_period;
01607     uint8_t        vl53l1_tuningparm_spadmap_vcsel_start;
01608     uint16_t        vl53l1_tuningparm_spadmap_rate_limit_mcps;
01609     uint16_t  vl53l1_tuningparm_lite_dss_config_target_total_rate_mcps;
01610     uint16_t   vl53l1_tuningparm_ranging_dss_config_target_total_rate_mcps;
01611     uint16_t        vl53l1_tuningparm_mz_dss_config_target_total_rate_mcps;
01612     uint16_t     vl53l1_tuningparm_timed_dss_config_target_total_rate_mcps;
01613     uint32_t        vl53l1_tuningparm_lite_phasecal_config_timeout_us;
01614     uint32_t     vl53l1_tuningparm_ranging_long_phasecal_config_timeout_us;
01615     uint32_t      vl53l1_tuningparm_ranging_med_phasecal_config_timeout_us;
01616     uint32_t    vl53l1_tuningparm_ranging_short_phasecal_config_timeout_us;
01617     uint32_t        vl53l1_tuningparm_mz_long_phasecal_config_timeout_us;
01618     uint32_t        vl53l1_tuningparm_mz_med_phasecal_config_timeout_us;
01619     uint32_t        vl53l1_tuningparm_mz_short_phasecal_config_timeout_us;
01620     uint32_t        vl53l1_tuningparm_timed_phasecal_config_timeout_us;
01621     uint32_t        vl53l1_tuningparm_lite_mm_config_timeout_us;
01622     uint32_t        vl53l1_tuningparm_ranging_mm_config_timeout_us;
01623     uint32_t        vl53l1_tuningparm_mz_mm_config_timeout_us;
01624     uint32_t        vl53l1_tuningparm_timed_mm_config_timeout_us;
01625     uint32_t        vl53l1_tuningparm_lite_range_config_timeout_us;
01626     uint32_t        vl53l1_tuningparm_ranging_range_config_timeout_us;
01627     uint32_t        vl53l1_tuningparm_mz_range_config_timeout_us;
01628     uint32_t        vl53l1_tuningparm_timed_range_config_timeout_us;
01629     uint16_t        vl53l1_tuningparm_dynxtalk_smudge_margin;
01630     uint32_t        vl53l1_tuningparm_dynxtalk_noise_margin;
01631     uint32_t        vl53l1_tuningparm_dynxtalk_xtalk_offset_limit;
01632     uint8_t        vl53l1_tuningparm_dynxtalk_xtalk_offset_limit_hi;
01633     uint32_t        vl53l1_tuningparm_dynxtalk_sample_limit;
01634     uint32_t        vl53l1_tuningparm_dynxtalk_single_xtalk_delta;
01635     uint32_t        vl53l1_tuningparm_dynxtalk_averaged_xtalk_delta;
01636     uint32_t        vl53l1_tuningparm_dynxtalk_clip_limit;
01637     uint8_t        vl53l1_tuningparm_dynxtalk_scaler_calc_method;
01638     int16_t        vl53l1_tuningparm_dynxtalk_xgradient_scaler;
01639     int16_t        vl53l1_tuningparm_dynxtalk_ygradient_scaler;
01640     uint8_t        vl53l1_tuningparm_dynxtalk_user_scaler_set;
01641     uint8_t        vl53l1_tuningparm_dynxtalk_smudge_cor_single_apply;
01642     uint32_t        vl53l1_tuningparm_dynxtalk_xtalk_amb_threshold;
01643     uint32_t        vl53l1_tuningparm_dynxtalk_nodetect_amb_threshold_kcps;
01644     uint32_t        vl53l1_tuningparm_dynxtalk_nodetect_sample_limit;
01645     uint32_t        vl53l1_tuningparm_dynxtalk_nodetect_xtalk_offset_kcps;
01646     uint16_t        vl53l1_tuningparm_dynxtalk_nodetect_min_range_mm;
01647     uint8_t        vl53l1_tuningparm_lowpowerauto_vhv_loop_bound;
01648     uint32_t        vl53l1_tuningparm_lowpowerauto_mm_config_timeout_us;
01649     uint32_t        vl53l1_tuningparm_lowpowerauto_range_config_timeout_us;
01650     uint16_t        vl53l1_tuningparm_very_short_dss_rate_mcps;
01651     uint32_t        vl53l1_tuningparm_phasecal_patch_power;
01652 } VL53L1_tuning_parameters_t;
01653 
01654 
01655 
01656 
01657 
01658 typedef struct {
01659 
01660     uint16_t  target_reflectance_for_dmax[VL53L1_MAX_AMBIENT_DMAX_VALUES];
01661 
01662 } VL53L1_dmax_reflectance_array_t;
01663 
01664 
01665 
01666 
01667 typedef struct {
01668 
01669     uint8_t    spad_type;
01670 
01671     uint16_t   VL53L1_p_023;
01672 
01673     uint16_t   rate_data[VL53L1_NO_OF_SPAD_ENABLES];
01674 
01675     uint16_t    no_of_values;
01676 
01677     uint8_t    fractional_bits;
01678 
01679     uint8_t    error_status;
01680 
01681 
01682 } VL53L1_spad_rate_data_t;
01683 
01684 
01685 
01686 
01687 
01688 
01689 typedef struct {
01690 
01691     VL53L1_DevicePresetModes        preset_mode;
01692 
01693     VL53L1_DeviceZonePreset         zone_preset;
01694 
01695     VL53L1_DeviceMeasurementModes   measurement_mode;
01696 
01697     VL53L1_OffsetCalibrationMode    offset_calibration_mode;
01698 
01699     VL53L1_OffsetCorrectionMode     offset_correction_mode;
01700 
01701     VL53L1_DeviceDmaxMode           dmax_mode;
01702 
01703 
01704     uint32_t  phasecal_config_timeout_us;
01705 
01706     uint32_t  mm_config_timeout_us;
01707 
01708     uint32_t  range_config_timeout_us;
01709 
01710     uint32_t  inter_measurement_period_ms;
01711 
01712     uint16_t  dss_config__target_total_rate_mcps;
01713 
01714 
01715     VL53L1_histogram_bin_data_t    VL53L1_p_010;
01716 
01717 
01718 } VL53L1_additional_data_t;
01719 
01720 
01721 
01722 
01723 
01724 
01725 
01726 
01727 #define SUPPRESS_UNUSED_WARNING(x) \
01728     ((void) (x))
01729 
01730 
01731 #define IGNORE_STATUS(__FUNCTION_ID__, __ERROR_STATUS_CHECK__, __STATUS__) \
01732     do { \
01733         DISABLE_WARNINGS(); \
01734         if (__FUNCTION_ID__) { \
01735             if (__STATUS__ == __ERROR_STATUS_CHECK__) { \
01736                 __STATUS__ = VL53L1_ERROR_NONE; \
01737                 WARN_OVERRIDE_STATUS(__FUNCTION_ID__); \
01738             } \
01739         } \
01740         ENABLE_WARNINGS(); \
01741     } \
01742     while (0)
01743 
01744 #define VL53L1_COPYSTRING(str, ...) \
01745     (strncpy(str, ##__VA_ARGS__, VL53L1_MAX_STRING_LENGTH-1))
01746 
01747 #ifdef __cplusplus
01748 }
01749 #endif
01750 
01751 #endif
01752 
01753 
01754