vl53l1_hist_structs.h

00001 
00002 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
00003 /******************************************************************************
00004  * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
00005 
00006  This file is part of VL53L1 and is dual licensed,
00007  either GPL-2.0+
00008  or 'BSD 3-clause "New" or "Revised" License' , at your option.
00009  ******************************************************************************
00010  */
00011 
00012 
00013 
00014 
00015 
00016 #ifndef _VL53L1_HIST_STRUCTS_H_
00017 #define _VL53L1_HIST_STRUCTS_H_
00018 
00019 #include "vl53l1_ll_device.h"
00020 #include "vl53l1_dmax_structs.h"
00021 
00022 #ifdef __cplusplus
00023 extern "C"
00024 {
00025 #endif
00026 
00027 #define  VL53L1_MAX_BIN_SEQUENCE_LENGTH  6
00028 #define  VL53L1_MAX_BIN_SEQUENCE_CODE   15
00029 #define  VL53L1_HISTOGRAM_BUFFER_SIZE   24
00030 #define  VL53L1_XTALK_HISTO_BINS        12
00031 
00032 
00033 
00034 typedef struct {
00035 
00036     uint8_t                          histogram_config__spad_array_selection;
00037 
00038     uint8_t                          histogram_config__low_amb_even_bin_0_1;
00039     uint8_t                          histogram_config__low_amb_even_bin_2_3;
00040     uint8_t                          histogram_config__low_amb_even_bin_4_5;
00041 
00042     uint8_t                          histogram_config__low_amb_odd_bin_0_1;
00043     uint8_t                          histogram_config__low_amb_odd_bin_2_3;
00044     uint8_t                          histogram_config__low_amb_odd_bin_4_5;
00045 
00046     uint8_t                          histogram_config__mid_amb_even_bin_0_1;
00047     uint8_t                          histogram_config__mid_amb_even_bin_2_3;
00048     uint8_t                          histogram_config__mid_amb_even_bin_4_5;
00049 
00050     uint8_t                          histogram_config__mid_amb_odd_bin_0_1;
00051     uint8_t                          histogram_config__mid_amb_odd_bin_2;
00052     uint8_t                          histogram_config__mid_amb_odd_bin_3_4;
00053     uint8_t                          histogram_config__mid_amb_odd_bin_5;
00054 
00055     uint8_t                          histogram_config__user_bin_offset;
00056 
00057     uint8_t                     histogram_config__high_amb_even_bin_0_1;
00058     uint8_t                     histogram_config__high_amb_even_bin_2_3;
00059     uint8_t                     histogram_config__high_amb_even_bin_4_5;
00060 
00061     uint8_t                  histogram_config__high_amb_odd_bin_0_1;
00062     uint8_t                  histogram_config__high_amb_odd_bin_2_3;
00063     uint8_t                  histogram_config__high_amb_odd_bin_4_5;
00064 
00065     uint16_t                         histogram_config__amb_thresh_low;
00066 
00067     uint16_t                         histogram_config__amb_thresh_high;
00068 
00069 
00070 } VL53L1_histogram_config_t;
00071 
00072 
00073 
00074 
00075 typedef struct {
00076 
00077     VL53L1_HistAlgoSelect  hist_algo_select;
00078 
00079 
00080     VL53L1_HistTargetOrder hist_target_order;
00081 
00082 
00083     uint8_t   filter_woi0;
00084 
00085     uint8_t   filter_woi1;
00086 
00087 
00088     VL53L1_HistAmbEstMethod hist_amb_est_method;
00089 
00090     uint8_t   ambient_thresh_sigma0;
00091 
00092     uint8_t   ambient_thresh_sigma1;
00093 
00094 
00095 
00096     uint16_t  ambient_thresh_events_scaler;
00097 
00098 
00099 
00100     int32_t   min_ambient_thresh_events;
00101 
00102     uint16_t  noise_threshold;
00103 
00104 
00105     int32_t   signal_total_events_limit;
00106 
00107     uint8_t   sigma_estimator__sigma_ref_mm;
00108 
00109     uint16_t  sigma_thresh;
00110 
00111     int16_t   range_offset_mm;
00112 
00113     uint16_t  gain_factor;
00114 
00115 
00116     uint8_t   valid_phase_low;
00117 
00118     uint8_t   valid_phase_high;
00119 
00120     uint8_t   algo__consistency_check__phase_tolerance;
00121 
00122     uint8_t   algo__consistency_check__event_sigma;
00123 
00124 
00125 
00126     uint16_t  algo__consistency_check__event_min_spad_count;
00127 
00128 
00129 
00130     uint16_t  algo__consistency_check__min_max_tolerance;
00131 
00132 
00133     uint8_t   algo__crosstalk_compensation_enable;
00134 
00135     uint32_t  algo__crosstalk_compensation_plane_offset_kcps;
00136 
00137     int16_t   algo__crosstalk_compensation_x_plane_gradient_kcps;
00138 
00139     int16_t   algo__crosstalk_compensation_y_plane_gradient_kcps;
00140 
00141 
00142     int16_t   algo__crosstalk_detect_min_valid_range_mm;
00143 
00144     int16_t   algo__crosstalk_detect_max_valid_range_mm;
00145 
00146     uint16_t  algo__crosstalk_detect_max_valid_rate_kcps;
00147 
00148     uint16_t  algo__crosstalk_detect_max_sigma_mm;
00149 
00150 
00151 
00152     uint8_t   algo__crosstalk_detect_event_sigma;
00153 
00154 
00155 
00156     uint16_t  algo__crosstalk_detect_min_max_tolerance;
00157 
00158 
00159 } VL53L1_hist_post_process_config_t;
00160 
00161 
00162 
00163 typedef struct {
00164 
00165 
00166     VL53L1_DeviceState     cfg_device_state;
00167 
00168     VL53L1_DeviceState     rd_device_state;
00169 
00170 
00171     uint8_t  zone_id;
00172 
00173     uint32_t time_stamp;
00174 
00175 
00176     uint8_t  VL53L1_p_022;
00177 
00178     uint8_t  VL53L1_p_023;
00179 
00180     uint8_t  VL53L1_p_024;
00181 
00182     uint8_t  number_of_ambient_bins;
00183 
00184     uint8_t  bin_seq[VL53L1_MAX_BIN_SEQUENCE_LENGTH];
00185 
00186     uint8_t  bin_rep[VL53L1_MAX_BIN_SEQUENCE_LENGTH];
00187 
00188     int32_t  bin_data[VL53L1_HISTOGRAM_BUFFER_SIZE];
00189 
00190 
00191     uint8_t  result__interrupt_status;
00192 
00193     uint8_t  result__range_status;
00194 
00195     uint8_t  result__report_status;
00196 
00197     uint8_t  result__stream_count;
00198 
00199     uint16_t result__dss_actual_effective_spads;
00200 
00201 
00202     uint16_t phasecal_result__reference_phase;
00203 
00204     uint8_t  phasecal_result__vcsel_start;
00205 
00206     uint8_t  cal_config__vcsel_start;
00207 
00208     uint16_t vcsel_width;
00209 
00210     uint8_t  VL53L1_p_009;
00211 
00212     uint16_t VL53L1_p_019;
00213 
00214     uint32_t  total_periods_elapsed;
00215 
00216 
00217     uint32_t peak_duration_us;
00218 
00219     uint32_t woi_duration_us;
00220 
00221 
00222     int32_t  min_bin_value;
00223 
00224     int32_t  max_bin_value;
00225 
00226 
00227     uint16_t zero_distance_phase;
00228 
00229     uint8_t  number_of_ambient_samples;
00230 
00231     int32_t  ambient_events_sum;
00232 
00233     int32_t  VL53L1_p_004;
00234 
00235 
00236     uint8_t  roi_config__user_roi_centre_spad;
00237 
00238     uint8_t  roi_config__user_roi_requested_global_xy_size;
00239 
00240 
00241 } VL53L1_histogram_bin_data_t;
00242 
00243 
00244 
00245 
00246 typedef struct {
00247 
00248 
00249     uint8_t  zone_id;
00250 
00251     uint32_t time_stamp;
00252 
00253 
00254     uint8_t  VL53L1_p_022;
00255 
00256     uint8_t  VL53L1_p_023;
00257 
00258     uint8_t  VL53L1_p_024;
00259 
00260     uint32_t bin_data[VL53L1_XTALK_HISTO_BINS];
00261 
00262 
00263 
00264     uint16_t phasecal_result__reference_phase;
00265 
00266     uint8_t  phasecal_result__vcsel_start;
00267 
00268     uint8_t  cal_config__vcsel_start;
00269 
00270     uint16_t vcsel_width;
00271 
00272     uint16_t VL53L1_p_019;
00273 
00274     uint16_t zero_distance_phase;
00275 
00276 
00277 } VL53L1_xtalk_histogram_shape_t;
00278 
00279 
00280 
00281 
00282 typedef struct {
00283 
00284 
00285     VL53L1_xtalk_histogram_shape_t  xtalk_shape;
00286 
00287     VL53L1_histogram_bin_data_t     xtalk_hist_removed;
00288 
00289 } VL53L1_xtalk_histogram_data_t;
00290 
00291 
00292 
00293 
00294 #ifdef __cplusplus
00295 }
00296 #endif
00297 
00298 #endif
00299