SQC Systems Mbed / ML5238

ML5238

ml5238_reg.h@0:6a895c900427, 2019-04-15 (annotated)

Committer:
gscuttari
Date:
Mon Apr 15 10:20:43 2019 +0000
Revision:
0:6a895c900427
ML5238

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gscuttari 0:6a895c900427 1 /*****************************************************************************
gscuttari 0:6a895c900427 2 ml5238_reg.h
gscuttari 0:6a895c900427 3
gscuttari 0:6a895c900427 4 Copyright (C) 2019 SQC Systems s.r.l.
gscuttari 0:6a895c900427 5 All rights reserved.
gscuttari 0:6a895c900427 6
gscuttari 0:6a895c900427 7 SQC Systems shall not be liable for any direct, indirect,
gscuttari 0:6a895c900427 8 consequential or incidental damages arising from using or modifying this
gscuttari 0:6a895c900427 9 program.
gscuttari 0:6a895c900427 10
gscuttari 0:6a895c900427 11 History
gscuttari 0:6a895c900427 12 2019.03.19 ver.3.00
gscuttari 0:6a895c900427 13 2012.11.20 ver.2.00
gscuttari 0:6a895c900427 14 2012.09.13 ver.1.00
gscuttari 0:6a895c900427 15 ******************************************************************************/
gscuttari 0:6a895c900427 16 #ifndef _ML5238_REG_H_
gscuttari 0:6a895c900427 17 #define _ML5238_REG_H_
gscuttari 0:6a895c900427 18
gscuttari 0:6a895c900427 19 #define ML5238_NOOP (0x00u)
gscuttari 0:6a895c900427 20 #define ML5238_VMON (0x01u)
gscuttari 0:6a895c900427 21 #define ML5238_IMON (0x02u)
gscuttari 0:6a895c900427 22 #define ML5238_FET (0x03u)
gscuttari 0:6a895c900427 23 #define ML5238_PSENSE (0x04u)
gscuttari 0:6a895c900427 24 #define ML5238_RSENSE (0x05u)
gscuttari 0:6a895c900427 25 #define ML5238_POWER (0x06u)
gscuttari 0:6a895c900427 26 #define ML5238_STATUS (0x07u)
gscuttari 0:6a895c900427 27 #define ML5238_CBALH (0x08u)
gscuttari 0:6a895c900427 28 #define ML5238_CBALL (0x09u)
gscuttari 0:6a895c900427 29 #define ML5238_SETSC (0x0Au)
gscuttari 0:6a895c900427 30
gscuttari 0:6a895c900427 31 /**********************************
gscuttari 0:6a895c900427 32 NOOP(0x00)
gscuttari 0:6a895c900427 33 **********************************/
gscuttari 0:6a895c900427 34 #define NOOP_NO0 (0x01u)
gscuttari 0:6a895c900427 35 #define NOOP_NO1 (0x02u)
gscuttari 0:6a895c900427 36 #define NOOP_NO2 (0x04u)
gscuttari 0:6a895c900427 37 #define NOOP_NO3 (0x08u)
gscuttari 0:6a895c900427 38 #define NOOP_NO4 (0x10u)
gscuttari 0:6a895c900427 39 #define NOOP_NO5 (0x20u)
gscuttari 0:6a895c900427 40 #define NOOP_NO6 (0x40u)
gscuttari 0:6a895c900427 41 #define NOOP_NO7 (0x80u)
gscuttari 0:6a895c900427 42
gscuttari 0:6a895c900427 43 /**********************************
gscuttari 0:6a895c900427 44 VMON(0x01)
gscuttari 0:6a895c900427 45 **********************************/
gscuttari 0:6a895c900427 46 #define VMON_CN0 (0x01u)
gscuttari 0:6a895c900427 47 #define VMON_CN1 (0x02u)
gscuttari 0:6a895c900427 48 #define VMON_CN2 (0x04u)
gscuttari 0:6a895c900427 49 #define VMON_CN3 (0x08u)
gscuttari 0:6a895c900427 50 #define VMON_OUT (0x10u)
gscuttari 0:6a895c900427 51
gscuttari 0:6a895c900427 52 /**********************************
gscuttari 0:6a895c900427 53 IMON(0x02)
gscuttari 0:6a895c900427 54 **********************************/
gscuttari 0:6a895c900427 55 #define IMON_GIM (0x01u)
gscuttari 0:6a895c900427 56 #define IMON_ZERO (0x02u)
gscuttari 0:6a895c900427 57 #define IMON_GCAL0 (0x04u)
gscuttari 0:6a895c900427 58 #define IMON_GCAL1 (0x08u)
gscuttari 0:6a895c900427 59 #define IMON_OUT (0x10u)
gscuttari 0:6a895c900427 60
gscuttari 0:6a895c900427 61
gscuttari 0:6a895c900427 62 /**********************************
gscuttari 0:6a895c900427 63 FET(0x03)
gscuttari 0:6a895c900427 64 **********************************/
gscuttari 0:6a895c900427 65 #define FET_DF (0x01u)
gscuttari 0:6a895c900427 66 #define FET_CF (0x02u)
gscuttari 0:6a895c900427 67 #define FET_DRV (0x10u)
gscuttari 0:6a895c900427 68 #define RESET_ALL_FET (0x00u)
gscuttari 0:6a895c900427 69
gscuttari 0:6a895c900427 70
gscuttari 0:6a895c900427 71
gscuttari 0:6a895c900427 72 /**********************************
gscuttari 0:6a895c900427 73 PSENSE(0x04)
gscuttari 0:6a895c900427 74 **********************************/
gscuttari 0:6a895c900427 75 #define PSENSE_PSL (0x01u)
gscuttari 0:6a895c900427 76 #define PSENSE_RPSL (0x02u)
gscuttari 0:6a895c900427 77 #define PSENSE_IPSL (0x04u)
gscuttari 0:6a895c900427 78 #define PSENSE_EPSL (0x08u)
gscuttari 0:6a895c900427 79 #define PSENSE_PSH (0x10u)
gscuttari 0:6a895c900427 80 #define PSENSE_RPSH (0x20u)
gscuttari 0:6a895c900427 81 #define PSENSE_IPSH (0x40u)
gscuttari 0:6a895c900427 82 #define PSENSE_EPSH (0x80u)
gscuttari 0:6a895c900427 83
gscuttari 0:6a895c900427 84 /**********************************
gscuttari 0:6a895c900427 85 RSENSE(0x05)
gscuttari 0:6a895c900427 86 **********************************/
gscuttari 0:6a895c900427 87 #define RSENSE_RS (0x01u)
gscuttari 0:6a895c900427 88 #define RSENSE_RRS (0x02u)
gscuttari 0:6a895c900427 89 #define RSENSE_IRS (0x04u)
gscuttari 0:6a895c900427 90 #define RSENSE_ERS (0x08u)
gscuttari 0:6a895c900427 91 #define RSENSE_SC (0x10u)
gscuttari 0:6a895c900427 92 #define RSENSE_RSC (0x20u)
gscuttari 0:6a895c900427 93 #define RSENSE_ISC (0x40u)
gscuttari 0:6a895c900427 94 #define RSENSE_ESC (0x80u)
gscuttari 0:6a895c900427 95
gscuttari 0:6a895c900427 96 /**********************************
gscuttari 0:6a895c900427 97 POWER(0x06)
gscuttari 0:6a895c900427 98 **********************************/
gscuttari 0:6a895c900427 99 #define POWER_PSV (0x01u)
gscuttari 0:6a895c900427 100 #define POWER_PDWN (0x10u)
gscuttari 0:6a895c900427 101 #define POWER_PUPIN (0x80u)
gscuttari 0:6a895c900427 102
gscuttari 0:6a895c900427 103 /**********************************
gscuttari 0:6a895c900427 104 STATUS(0x07)
gscuttari 0:6a895c900427 105 **********************************/
gscuttari 0:6a895c900427 106 #define STATUS_DF (0x01u)
gscuttari 0:6a895c900427 107 #define STATUS_CF (0x02u)
gscuttari 0:6a895c900427 108 #define STATUS_PSV (0x04u)
gscuttari 0:6a895c900427 109 #define STATUS_INT (0x08u)
gscuttari 0:6a895c900427 110 #define STATUS_RPSL (0x10u)
gscuttari 0:6a895c900427 111 #define STATUS_RPSH (0x20u)
gscuttari 0:6a895c900427 112 #define STATUS_RRS (0x40u)
gscuttari 0:6a895c900427 113 #define STATUS_RSC (0x80u)
gscuttari 0:6a895c900427 114
gscuttari 0:6a895c900427 115 /**********************************
gscuttari 0:6a895c900427 116 CBALH(0x08)
gscuttari 0:6a895c900427 117 **********************************/
gscuttari 0:6a895c900427 118 #define CBALH_SW9 (0x01u)
gscuttari 0:6a895c900427 119 #define CBALH_SW10 (0x02u)
gscuttari 0:6a895c900427 120 #define CBALH_SW11 (0x04u)
gscuttari 0:6a895c900427 121 #define CBALH_SW12 (0x08u)
gscuttari 0:6a895c900427 122 #define CBALH_SW13 (0x10u)
gscuttari 0:6a895c900427 123 #define CBALH_SW14 (0x20u)
gscuttari 0:6a895c900427 124 #define CBALH_SW15 (0x40u)
gscuttari 0:6a895c900427 125 #define CBALH_SW16 (0x80u)
gscuttari 0:6a895c900427 126
gscuttari 0:6a895c900427 127 /**********************************
gscuttari 0:6a895c900427 128 CBALL(0x09)
gscuttari 0:6a895c900427 129 **********************************/
gscuttari 0:6a895c900427 130 #define CBALL_SW1 (0x01u)
gscuttari 0:6a895c900427 131 #define CBALL_SW2 (0x02u)
gscuttari 0:6a895c900427 132 #define CBALL_SW3 (0x04u)
gscuttari 0:6a895c900427 133 #define CBALL_SW4 (0x08u)
gscuttari 0:6a895c900427 134 #define CBALL_SW5 (0x10u)
gscuttari 0:6a895c900427 135 #define CBALL_SW6 (0x20u)
gscuttari 0:6a895c900427 136 #define CBALL_SW7 (0x40u)
gscuttari 0:6a895c900427 137 #define CBALL_SW8 (0x80u)
gscuttari 0:6a895c900427 138
gscuttari 0:6a895c900427 139 /**********************************
gscuttari 0:6a895c900427 140 SETSC(0x0A)
gscuttari 0:6a895c900427 141 **********************************/
gscuttari 0:6a895c900427 142 //0x00=33.3A 0x01=66.6A 0x10=100A 0x11=133.3A
gscuttari 0:6a895c900427 143 #define SETSC_SC0 (0x00u)
gscuttari 0:6a895c900427 144 #define SETSC_SC1 (0x01u)
gscuttari 0:6a895c900427 145 #define SETSC_SC2 (0x10u)
gscuttari 0:6a895c900427 146 #define SETSC_SC3 (0x11u)
gscuttari 0:6a895c900427 147
gscuttari 0:6a895c900427 148
gscuttari 0:6a895c900427 149 #endif /*_ML5238_REG_H_*/