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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/LPC11xx.h@20:4263a77256ae, 2013-09-10 (annotated)

Committer:
bogdanm
Date:
Tue Sep 10 15:14:19 2013 +0300
Revision:
20:4263a77256ae
Child:
28:4b07695ba953
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 20:4263a77256ae 1 /****************************************************************************
bogdanm 20:4263a77256ae 2 * $Id:: LPC11xx.h 9198 2012-05-29 usb00175 $
bogdanm 20:4263a77256ae 3 * Project: NXP LPC11xx software example
bogdanm 20:4263a77256ae 4 *
bogdanm 20:4263a77256ae 5 * Description:
bogdanm 20:4263a77256ae 6 * CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
bogdanm 20:4263a77256ae 7 * NXP LPC11xx Device Series
bogdanm 20:4263a77256ae 8
bogdanm 20:4263a77256ae 9 ****************************************************************************
bogdanm 20:4263a77256ae 10 * Software that is described herein is for illustrative purposes only
bogdanm 20:4263a77256ae 11 * which provides customers with programming information regarding the
bogdanm 20:4263a77256ae 12 * products. This software is supplied "AS IS" without any warranties.
bogdanm 20:4263a77256ae 13 * NXP Semiconductors assumes no responsibility or liability for the
bogdanm 20:4263a77256ae 14 * use of the software, conveys no license or title under any patent,
bogdanm 20:4263a77256ae 15 * copyright, or mask work right to the product. NXP Semiconductors
bogdanm 20:4263a77256ae 16 * reserves the right to make changes in the software without
bogdanm 20:4263a77256ae 17 * notification. NXP Semiconductors also make no representation or
bogdanm 20:4263a77256ae 18 * warranty that such application will be suitable for the specified
bogdanm 20:4263a77256ae 19 * use without further testing or modification.
bogdanm 20:4263a77256ae 20
bogdanm 20:4263a77256ae 21 * Permission to use, copy, modify, and distribute this software and its
bogdanm 20:4263a77256ae 22 * documentation is hereby granted, under NXP Semiconductors'
bogdanm 20:4263a77256ae 23 * relevant copyright in the software, without fee, provided that it
bogdanm 20:4263a77256ae 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm 20:4263a77256ae 25 * copyright, permission, and disclaimer notice must appear in all copies of
bogdanm 20:4263a77256ae 26 * this code.
bogdanm 20:4263a77256ae 27
bogdanm 20:4263a77256ae 28 ****************************************************************************/
bogdanm 20:4263a77256ae 29 #ifndef __LPC11xx_H__
bogdanm 20:4263a77256ae 30 #define __LPC11xx_H__
bogdanm 20:4263a77256ae 31
bogdanm 20:4263a77256ae 32 #ifdef __cplusplus
bogdanm 20:4263a77256ae 33 extern "C" {
bogdanm 20:4263a77256ae 34 #endif
bogdanm 20:4263a77256ae 35
bogdanm 20:4263a77256ae 36 /** @addtogroup LPC11xx_Definitions LPC11xx Definitions
bogdanm 20:4263a77256ae 37 This file defines all structures and symbols for LPC11xx:
bogdanm 20:4263a77256ae 38 - Registers and bitfields
bogdanm 20:4263a77256ae 39 - peripheral base address
bogdanm 20:4263a77256ae 40 - peripheral ID
bogdanm 20:4263a77256ae 41 - PIO definitions
bogdanm 20:4263a77256ae 42 @{
bogdanm 20:4263a77256ae 43 */
bogdanm 20:4263a77256ae 44
bogdanm 20:4263a77256ae 45
bogdanm 20:4263a77256ae 46 /******************************************************************************/
bogdanm 20:4263a77256ae 47 /* Processor and Core Peripherals */
bogdanm 20:4263a77256ae 48 /******************************************************************************/
bogdanm 20:4263a77256ae 49 /** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions
bogdanm 20:4263a77256ae 50 Configuration of the Cortex-M0 Processor and Core Peripherals
bogdanm 20:4263a77256ae 51 @{
bogdanm 20:4263a77256ae 52 */
bogdanm 20:4263a77256ae 53
bogdanm 20:4263a77256ae 54 /*
bogdanm 20:4263a77256ae 55 * ==========================================================================
bogdanm 20:4263a77256ae 56 * ---------- Interrupt Number Definition -----------------------------------
bogdanm 20:4263a77256ae 57 * ==========================================================================
bogdanm 20:4263a77256ae 58 */
bogdanm 20:4263a77256ae 59 typedef enum IRQn
bogdanm 20:4263a77256ae 60 {
bogdanm 20:4263a77256ae 61 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
bogdanm 20:4263a77256ae 62 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 20:4263a77256ae 63 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
bogdanm 20:4263a77256ae 64 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
bogdanm 20:4263a77256ae 65 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
bogdanm 20:4263a77256ae 66 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
bogdanm 20:4263a77256ae 67
bogdanm 20:4263a77256ae 68 /****** LPC11Cxx or LPC11xx Specific Interrupt Numbers *******************************************************/
bogdanm 20:4263a77256ae 69 WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
bogdanm 20:4263a77256ae 70 WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */
bogdanm 20:4263a77256ae 71 WAKEUP2_IRQn = 2,
bogdanm 20:4263a77256ae 72 WAKEUP3_IRQn = 3,
bogdanm 20:4263a77256ae 73 WAKEUP4_IRQn = 4,
bogdanm 20:4263a77256ae 74 WAKEUP5_IRQn = 5,
bogdanm 20:4263a77256ae 75 WAKEUP6_IRQn = 6,
bogdanm 20:4263a77256ae 76 WAKEUP7_IRQn = 7,
bogdanm 20:4263a77256ae 77 WAKEUP8_IRQn = 8,
bogdanm 20:4263a77256ae 78 WAKEUP9_IRQn = 9,
bogdanm 20:4263a77256ae 79 WAKEUP10_IRQn = 10,
bogdanm 20:4263a77256ae 80 WAKEUP11_IRQn = 11,
bogdanm 20:4263a77256ae 81 WAKEUP12_IRQn = 12,
bogdanm 20:4263a77256ae 82 CAN_IRQn = 13, /*!< CAN Interrupt */
bogdanm 20:4263a77256ae 83 SSP1_IRQn = 14, /*!< SSP1 Interrupt */
bogdanm 20:4263a77256ae 84 I2C_IRQn = 15, /*!< I2C Interrupt */
bogdanm 20:4263a77256ae 85 TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
bogdanm 20:4263a77256ae 86 TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
bogdanm 20:4263a77256ae 87 TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
bogdanm 20:4263a77256ae 88 TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
bogdanm 20:4263a77256ae 89 SSP0_IRQn = 20, /*!< SSP0 Interrupt */
bogdanm 20:4263a77256ae 90 UART_IRQn = 21, /*!< UART Interrupt */
bogdanm 20:4263a77256ae 91 Reserved0_IRQn = 22, /*!< Reserved Interrupt */
bogdanm 20:4263a77256ae 92 Reserved1_IRQn = 23,
bogdanm 20:4263a77256ae 93 ADC_IRQn = 24, /*!< A/D Converter Interrupt */
bogdanm 20:4263a77256ae 94 WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
bogdanm 20:4263a77256ae 95 BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
bogdanm 20:4263a77256ae 96 FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
bogdanm 20:4263a77256ae 97 EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */
bogdanm 20:4263a77256ae 98 EINT2_IRQn = 29, /*!< External Interrupt 2 Interrupt */
bogdanm 20:4263a77256ae 99 EINT1_IRQn = 30, /*!< External Interrupt 1 Interrupt */
bogdanm 20:4263a77256ae 100 EINT0_IRQn = 31, /*!< External Interrupt 0 Interrupt */
bogdanm 20:4263a77256ae 101 } IRQn_Type;
bogdanm 20:4263a77256ae 102
bogdanm 20:4263a77256ae 103 /*
bogdanm 20:4263a77256ae 104 * ==========================================================================
bogdanm 20:4263a77256ae 105 * ----------- Processor and Core Peripheral Section ------------------------
bogdanm 20:4263a77256ae 106 * ==========================================================================
bogdanm 20:4263a77256ae 107 */
bogdanm 20:4263a77256ae 108
bogdanm 20:4263a77256ae 109 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
bogdanm 20:4263a77256ae 110 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 20:4263a77256ae 111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
bogdanm 20:4263a77256ae 112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 20:4263a77256ae 113
bogdanm 20:4263a77256ae 114 /*@}*/ /* end of group LPC11xx_CMSIS */
bogdanm 20:4263a77256ae 115
bogdanm 20:4263a77256ae 116
bogdanm 20:4263a77256ae 117 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
bogdanm 20:4263a77256ae 118 #include "system_LPC11xx.h" /* System Header */
bogdanm 20:4263a77256ae 119
bogdanm 20:4263a77256ae 120
bogdanm 20:4263a77256ae 121 /******************************************************************************/
bogdanm 20:4263a77256ae 122 /* Device Specific Peripheral Registers structures */
bogdanm 20:4263a77256ae 123 /******************************************************************************/
bogdanm 20:4263a77256ae 124
bogdanm 20:4263a77256ae 125 #if defined ( __CC_ARM )
bogdanm 20:4263a77256ae 126 #pragma anon_unions
bogdanm 20:4263a77256ae 127 #endif
bogdanm 20:4263a77256ae 128
bogdanm 20:4263a77256ae 129 /*------------- System Control (SYSCON) --------------------------------------*/
bogdanm 20:4263a77256ae 130 /** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block
bogdanm 20:4263a77256ae 131 @{
bogdanm 20:4263a77256ae 132 */
bogdanm 20:4263a77256ae 133 typedef struct
bogdanm 20:4263a77256ae 134 {
bogdanm 20:4263a77256ae 135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
bogdanm 20:4263a77256ae 136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
bogdanm 20:4263a77256ae 137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
bogdanm 20:4263a77256ae 138 __I uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/ ) */
bogdanm 20:4263a77256ae 139 uint32_t RESERVED0[4];
bogdanm 20:4263a77256ae 140
bogdanm 20:4263a77256ae 141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
bogdanm 20:4263a77256ae 142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
bogdanm 20:4263a77256ae 143 __IO uint32_t IRCCTRL; /*!< Offset: 0x028 IRC control (R/W) */
bogdanm 20:4263a77256ae 144 uint32_t RESERVED1[1];
bogdanm 20:4263a77256ae 145 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/ ) */
bogdanm 20:4263a77256ae 146 uint32_t RESERVED2[3];
bogdanm 20:4263a77256ae 147 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
bogdanm 20:4263a77256ae 148 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
bogdanm 20:4263a77256ae 149 uint32_t RESERVED3[10];
bogdanm 20:4263a77256ae 150
bogdanm 20:4263a77256ae 151 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
bogdanm 20:4263a77256ae 152 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
bogdanm 20:4263a77256ae 153 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
bogdanm 20:4263a77256ae 154 uint32_t RESERVED4[1];
bogdanm 20:4263a77256ae 155
bogdanm 20:4263a77256ae 156 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
bogdanm 20:4263a77256ae 157 uint32_t RESERVED5[4];
bogdanm 20:4263a77256ae 158 __IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */
bogdanm 20:4263a77256ae 159 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x098 UART clock divider (R/W) */
bogdanm 20:4263a77256ae 160 __IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */
bogdanm 20:4263a77256ae 161 uint32_t RESERVED6[12];
bogdanm 20:4263a77256ae 162
bogdanm 20:4263a77256ae 163 __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 WDT clock source select (R/W) */
bogdanm 20:4263a77256ae 164 __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */
bogdanm 20:4263a77256ae 165 __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 WDT clock divider (R/W) */
bogdanm 20:4263a77256ae 166 uint32_t RESERVED8[1];
bogdanm 20:4263a77256ae 167 __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
bogdanm 20:4263a77256ae 168 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
bogdanm 20:4263a77256ae 169 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
bogdanm 20:4263a77256ae 170 uint32_t RESERVED9[5];
bogdanm 20:4263a77256ae 171
bogdanm 20:4263a77256ae 172 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
bogdanm 20:4263a77256ae 173 __IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */
bogdanm 20:4263a77256ae 174 uint32_t RESERVED10[18];
bogdanm 20:4263a77256ae 175 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
bogdanm 20:4263a77256ae 176 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
bogdanm 20:4263a77256ae 177
bogdanm 20:4263a77256ae 178 uint32_t RESERVED13[7];
bogdanm 20:4263a77256ae 179 __IO uint32_t NMISRC; /*!< Offset: 0x174 NMI source selection register (R/W) */
bogdanm 20:4263a77256ae 180 uint32_t RESERVED14[34];
bogdanm 20:4263a77256ae 181
bogdanm 20:4263a77256ae 182 __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */
bogdanm 20:4263a77256ae 183 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
bogdanm 20:4263a77256ae 184 __O uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 Start logic reset Register 0 ( /W) */
bogdanm 20:4263a77256ae 185 __I uint32_t STARTSRP0; /*!< Offset: 0x20C Start logic status Register 0 (R/) */
bogdanm 20:4263a77256ae 186 __IO uint32_t STARTAPRP1; /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */
bogdanm 20:4263a77256ae 187 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */
bogdanm 20:4263a77256ae 188 __O uint32_t STARTRSRP1CLR; /*!< Offset: 0x218 Start logic reset Register 0 ( /W). (LPC11UXX only) */
bogdanm 20:4263a77256ae 189 __IO uint32_t STARTSRP1; /*!< Offset: 0x21C Start logic status Register 0 (R/W). (LPC11UXX only) */
bogdanm 20:4263a77256ae 190 uint32_t RESERVED17[4];
bogdanm 20:4263a77256ae 191
bogdanm 20:4263a77256ae 192 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
bogdanm 20:4263a77256ae 193 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
bogdanm 20:4263a77256ae 194 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
bogdanm 20:4263a77256ae 195 uint32_t RESERVED15[110];
bogdanm 20:4263a77256ae 196 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
bogdanm 20:4263a77256ae 197 } LPC_SYSCON_TypeDef;
bogdanm 20:4263a77256ae 198 /*@}*/ /* end of group LPC11xx_SYSCON */
bogdanm 20:4263a77256ae 199
bogdanm 20:4263a77256ae 200
bogdanm 20:4263a77256ae 201 /*------------- Pin Connect Block (IOCON) --------------------------------*/
bogdanm 20:4263a77256ae 202 /** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block
bogdanm 20:4263a77256ae 203 @{
bogdanm 20:4263a77256ae 204 */
bogdanm 20:4263a77256ae 205 typedef struct
bogdanm 20:4263a77256ae 206 {
bogdanm 20:4263a77256ae 207 __IO uint32_t PIO2_6; /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */
bogdanm 20:4263a77256ae 208 uint32_t RESERVED0[1];
bogdanm 20:4263a77256ae 209 __IO uint32_t PIO2_0; /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */
bogdanm 20:4263a77256ae 210 __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0 (R/W) */
bogdanm 20:4263a77256ae 211 __IO uint32_t PIO0_1; /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */
bogdanm 20:4263a77256ae 212 __IO uint32_t PIO1_8; /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */
bogdanm 20:4263a77256ae 213 __IO uint32_t SSEL1_LOC; /*!< Offset: 0x018 IOCON SSEL1 location register (IOCON_SSEL1_LOC, address 0x4004 4018) */
bogdanm 20:4263a77256ae 214 __IO uint32_t PIO0_2; /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */
bogdanm 20:4263a77256ae 215
bogdanm 20:4263a77256ae 216 __IO uint32_t PIO2_7; /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */
bogdanm 20:4263a77256ae 217 __IO uint32_t PIO2_8; /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */
bogdanm 20:4263a77256ae 218 __IO uint32_t PIO2_1; /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */
bogdanm 20:4263a77256ae 219 __IO uint32_t PIO0_3; /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */
bogdanm 20:4263a77256ae 220 __IO uint32_t PIO0_4; /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */
bogdanm 20:4263a77256ae 221 __IO uint32_t PIO0_5; /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */
bogdanm 20:4263a77256ae 222 __IO uint32_t PIO1_9; /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */
bogdanm 20:4263a77256ae 223 __IO uint32_t PIO3_4; /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */
bogdanm 20:4263a77256ae 224
bogdanm 20:4263a77256ae 225 __IO uint32_t PIO2_4; /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */
bogdanm 20:4263a77256ae 226 __IO uint32_t PIO2_5; /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */
bogdanm 20:4263a77256ae 227 __IO uint32_t PIO3_5; /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */
bogdanm 20:4263a77256ae 228 __IO uint32_t PIO0_6; /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */
bogdanm 20:4263a77256ae 229 __IO uint32_t PIO0_7; /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */
bogdanm 20:4263a77256ae 230 __IO uint32_t PIO2_9; /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */
bogdanm 20:4263a77256ae 231 __IO uint32_t PIO2_10; /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */
bogdanm 20:4263a77256ae 232 __IO uint32_t PIO2_2; /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */
bogdanm 20:4263a77256ae 233
bogdanm 20:4263a77256ae 234 __IO uint32_t PIO0_8; /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */
bogdanm 20:4263a77256ae 235 __IO uint32_t PIO0_9; /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */
bogdanm 20:4263a77256ae 236 __IO uint32_t SWCLK_PIO0_10; /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */
bogdanm 20:4263a77256ae 237 __IO uint32_t PIO1_10; /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */
bogdanm 20:4263a77256ae 238 __IO uint32_t PIO2_11; /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */
bogdanm 20:4263a77256ae 239 __IO uint32_t R_PIO0_11; /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */
bogdanm 20:4263a77256ae 240 __IO uint32_t R_PIO1_0; /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */
bogdanm 20:4263a77256ae 241 __IO uint32_t R_PIO1_1; /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */
bogdanm 20:4263a77256ae 242
bogdanm 20:4263a77256ae 243 __IO uint32_t R_PIO1_2; /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */
bogdanm 20:4263a77256ae 244 __IO uint32_t PIO3_0; /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */
bogdanm 20:4263a77256ae 245 __IO uint32_t PIO3_1; /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */
bogdanm 20:4263a77256ae 246 __IO uint32_t PIO2_3; /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */
bogdanm 20:4263a77256ae 247 __IO uint32_t SWDIO_PIO1_3; /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */
bogdanm 20:4263a77256ae 248 __IO uint32_t PIO1_4; /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */
bogdanm 20:4263a77256ae 249 __IO uint32_t PIO1_11; /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */
bogdanm 20:4263a77256ae 250 __IO uint32_t PIO3_2; /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */
bogdanm 20:4263a77256ae 251
bogdanm 20:4263a77256ae 252 __IO uint32_t PIO1_5; /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */
bogdanm 20:4263a77256ae 253 __IO uint32_t PIO1_6; /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */
bogdanm 20:4263a77256ae 254 __IO uint32_t PIO1_7; /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */
bogdanm 20:4263a77256ae 255 __IO uint32_t PIO3_3; /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */
bogdanm 20:4263a77256ae 256 __IO uint32_t SCK_LOC; /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */
bogdanm 20:4263a77256ae 257 __IO uint32_t DSR_LOC; /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */
bogdanm 20:4263a77256ae 258 __IO uint32_t DCD_LOC; /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */
bogdanm 20:4263a77256ae 259 __IO uint32_t RI_LOC; /*!< Offset: 0x0BC RI pin location Register (R/W) */
bogdanm 20:4263a77256ae 260
bogdanm 20:4263a77256ae 261 __IO uint32_t CT16B0_CAP0_LOC; /*!< Offset: 0x0C0 IOCON CT16B0_CAP0 location register (IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0) */
bogdanm 20:4263a77256ae 262 __IO uint32_t SCK1_LOC; /*!< Offset: 0x0C4 IOCON SCK1 location register (IOCON_SCK1_LOC, address 0x4004 40C4) */
bogdanm 20:4263a77256ae 263 __IO uint32_t MISO1_LOC; /*!< Offset: 0x0C8 IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) */
bogdanm 20:4263a77256ae 264 __IO uint32_t MOSI1_LOC; /*!< Offset: 0x0CC IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) */
bogdanm 20:4263a77256ae 265 __IO uint32_t CT32B0_CAP0_LOC; /*!< Offset: 0x0D0 IOCON CT32B0_CAP0 location register (IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0) */
bogdanm 20:4263a77256ae 266 __IO uint32_t RXD_LOC; /*!< Offset: 0x0D4 IOCON RXD location register (IOCON_RXD_LOC, address 0x4004 40D4) */
bogdanm 20:4263a77256ae 267 } LPC_IOCON_TypeDef;
bogdanm 20:4263a77256ae 268 /*@}*/ /* end of group LPC11xx_IOCON */
bogdanm 20:4263a77256ae 269
bogdanm 20:4263a77256ae 270
bogdanm 20:4263a77256ae 271 /*------------- Power Management Unit (PMU) --------------------------*/
bogdanm 20:4263a77256ae 272 /** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit
bogdanm 20:4263a77256ae 273 @{
bogdanm 20:4263a77256ae 274 */
bogdanm 20:4263a77256ae 275 typedef struct
bogdanm 20:4263a77256ae 276 {
bogdanm 20:4263a77256ae 277 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
bogdanm 20:4263a77256ae 278 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
bogdanm 20:4263a77256ae 279 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
bogdanm 20:4263a77256ae 280 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
bogdanm 20:4263a77256ae 281 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
bogdanm 20:4263a77256ae 282 __IO uint32_t GPREG4; /*!< Offset: 0x014 General purpose Register 4 (R/W) */
bogdanm 20:4263a77256ae 283 } LPC_PMU_TypeDef;
bogdanm 20:4263a77256ae 284 /*@}*/ /* end of group LPC11xx_PMU */
bogdanm 20:4263a77256ae 285
bogdanm 20:4263a77256ae 286
bogdanm 20:4263a77256ae 287
bogdanm 20:4263a77256ae 288 // ------------------------------------------------------------------------------------------------
bogdanm 20:4263a77256ae 289 // ----- FLASHCTRL -----
bogdanm 20:4263a77256ae 290 // ------------------------------------------------------------------------------------------------
bogdanm 20:4263a77256ae 291
bogdanm 20:4263a77256ae 292 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
bogdanm 20:4263a77256ae 293 __I uint32_t RESERVED0[4];
bogdanm 20:4263a77256ae 294 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
bogdanm 20:4263a77256ae 295 __I uint32_t RESERVED1[3];
bogdanm 20:4263a77256ae 296 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
bogdanm 20:4263a77256ae 297 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
bogdanm 20:4263a77256ae 298 __I uint32_t RESERVED2[1];
bogdanm 20:4263a77256ae 299 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
bogdanm 20:4263a77256ae 300 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
bogdanm 20:4263a77256ae 301 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
bogdanm 20:4263a77256ae 302 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
bogdanm 20:4263a77256ae 303 __I uint32_t RESERVED3[1001];
bogdanm 20:4263a77256ae 304 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
bogdanm 20:4263a77256ae 305 __I uint32_t RESERVED4[1];
bogdanm 20:4263a77256ae 306 __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
bogdanm 20:4263a77256ae 307 } LPC_FLASHCTRL_Type;
bogdanm 20:4263a77256ae 308
bogdanm 20:4263a77256ae 309
bogdanm 20:4263a77256ae 310 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
bogdanm 20:4263a77256ae 311 /** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output
bogdanm 20:4263a77256ae 312 @{
bogdanm 20:4263a77256ae 313 */
bogdanm 20:4263a77256ae 314 typedef struct
bogdanm 20:4263a77256ae 315 {
bogdanm 20:4263a77256ae 316 union {
bogdanm 20:4263a77256ae 317 __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */
bogdanm 20:4263a77256ae 318 struct {
bogdanm 20:4263a77256ae 319 uint32_t RESERVED0[4095];
bogdanm 20:4263a77256ae 320 __IO uint32_t DATA; /*!< Offset: 0x3FFC Port data Register (R/W) */
bogdanm 20:4263a77256ae 321 };
bogdanm 20:4263a77256ae 322 };
bogdanm 20:4263a77256ae 323 uint32_t RESERVED1[4096];
bogdanm 20:4263a77256ae 324 __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction Register (R/W) */
bogdanm 20:4263a77256ae 325 __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense Register (R/W) */
bogdanm 20:4263a77256ae 326 __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */
bogdanm 20:4263a77256ae 327 __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event Register (R/W) */
bogdanm 20:4263a77256ae 328 __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask Register (R/W) */
bogdanm 20:4263a77256ae 329 __I uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */
bogdanm 20:4263a77256ae 330 __I uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */
bogdanm 20:4263a77256ae 331 __O uint32_t IC; /*!< Offset: 0x801C Interrupt clear Register (/W) */
bogdanm 20:4263a77256ae 332 } LPC_GPIO_TypeDef;
bogdanm 20:4263a77256ae 333 /*@}*/ /* end of group LPC11xx_GPIO */
bogdanm 20:4263a77256ae 334
bogdanm 20:4263a77256ae 335 /*------------- Timer (TMR) --------------------------------------------------*/
bogdanm 20:4263a77256ae 336 /** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer
bogdanm 20:4263a77256ae 337 @{
bogdanm 20:4263a77256ae 338 */
bogdanm 20:4263a77256ae 339 typedef struct
bogdanm 20:4263a77256ae 340 {
bogdanm 20:4263a77256ae 341 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
bogdanm 20:4263a77256ae 342 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
bogdanm 20:4263a77256ae 343 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
bogdanm 20:4263a77256ae 344 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
bogdanm 20:4263a77256ae 345 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
bogdanm 20:4263a77256ae 346 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
bogdanm 20:4263a77256ae 347 union {
bogdanm 20:4263a77256ae 348 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
bogdanm 20:4263a77256ae 349 struct{
bogdanm 20:4263a77256ae 350 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
bogdanm 20:4263a77256ae 351 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
bogdanm 20:4263a77256ae 352 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
bogdanm 20:4263a77256ae 353 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
bogdanm 20:4263a77256ae 354 };
bogdanm 20:4263a77256ae 355 };
bogdanm 20:4263a77256ae 356 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
bogdanm 20:4263a77256ae 357 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
bogdanm 20:4263a77256ae 358 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
bogdanm 20:4263a77256ae 359 uint32_t RESERVED1[2];
bogdanm 20:4263a77256ae 360 __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
bogdanm 20:4263a77256ae 361 uint32_t RESERVED2[12];
bogdanm 20:4263a77256ae 362 __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
bogdanm 20:4263a77256ae 363 __IO uint32_t PWMC; /*!< Offset: 0x074 PWM Control Register (R/W) */
bogdanm 20:4263a77256ae 364 } LPC_TMR_TypeDef;
bogdanm 20:4263a77256ae 365 /*@}*/ /* end of group LPC11xx_TMR */
bogdanm 20:4263a77256ae 366
bogdanm 20:4263a77256ae 367
bogdanm 20:4263a77256ae 368 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
bogdanm 20:4263a77256ae 369 /** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter
bogdanm 20:4263a77256ae 370 @{
bogdanm 20:4263a77256ae 371 */
bogdanm 20:4263a77256ae 372 typedef struct
bogdanm 20:4263a77256ae 373 {
bogdanm 20:4263a77256ae 374 union {
bogdanm 20:4263a77256ae 375 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
bogdanm 20:4263a77256ae 376 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
bogdanm 20:4263a77256ae 377 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
bogdanm 20:4263a77256ae 378 };
bogdanm 20:4263a77256ae 379 union {
bogdanm 20:4263a77256ae 380 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
bogdanm 20:4263a77256ae 381 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
bogdanm 20:4263a77256ae 382 };
bogdanm 20:4263a77256ae 383 union {
bogdanm 20:4263a77256ae 384 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
bogdanm 20:4263a77256ae 385 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
bogdanm 20:4263a77256ae 386 };
bogdanm 20:4263a77256ae 387 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
bogdanm 20:4263a77256ae 388 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
bogdanm 20:4263a77256ae 389 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
bogdanm 20:4263a77256ae 390 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
bogdanm 20:4263a77256ae 391 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
bogdanm 20:4263a77256ae 392 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
bogdanm 20:4263a77256ae 393 uint32_t RESERVED0;
bogdanm 20:4263a77256ae 394 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
bogdanm 20:4263a77256ae 395 uint32_t RESERVED1;
bogdanm 20:4263a77256ae 396 __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */
bogdanm 20:4263a77256ae 397 uint32_t RESERVED2[6];
bogdanm 20:4263a77256ae 398 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
bogdanm 20:4263a77256ae 399 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
bogdanm 20:4263a77256ae 400 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
bogdanm 20:4263a77256ae 401 __I uint32_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register (R) */
bogdanm 20:4263a77256ae 402 } LPC_UART_TypeDef;
bogdanm 20:4263a77256ae 403 /*@}*/ /* end of group LPC11xx_UART */
bogdanm 20:4263a77256ae 404
bogdanm 20:4263a77256ae 405
bogdanm 20:4263a77256ae 406 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
bogdanm 20:4263a77256ae 407 /** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port
bogdanm 20:4263a77256ae 408 @{
bogdanm 20:4263a77256ae 409 */
bogdanm 20:4263a77256ae 410 typedef struct
bogdanm 20:4263a77256ae 411 {
bogdanm 20:4263a77256ae 412 __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
bogdanm 20:4263a77256ae 413 __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
bogdanm 20:4263a77256ae 414 __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
bogdanm 20:4263a77256ae 415 __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
bogdanm 20:4263a77256ae 416 __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
bogdanm 20:4263a77256ae 417 __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
bogdanm 20:4263a77256ae 418 __I uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/) */
bogdanm 20:4263a77256ae 419 __I uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/) */
bogdanm 20:4263a77256ae 420 __O uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (/W) */
bogdanm 20:4263a77256ae 421 } LPC_SSP_TypeDef;
bogdanm 20:4263a77256ae 422 /*@}*/ /* end of group LPC11xx_SSP */
bogdanm 20:4263a77256ae 423
bogdanm 20:4263a77256ae 424
bogdanm 20:4263a77256ae 425 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
bogdanm 20:4263a77256ae 426 /** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface
bogdanm 20:4263a77256ae 427 @{
bogdanm 20:4263a77256ae 428 */
bogdanm 20:4263a77256ae 429 typedef struct
bogdanm 20:4263a77256ae 430 {
bogdanm 20:4263a77256ae 431 __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
bogdanm 20:4263a77256ae 432 __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
bogdanm 20:4263a77256ae 433 __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
bogdanm 20:4263a77256ae 434 __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
bogdanm 20:4263a77256ae 435 __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
bogdanm 20:4263a77256ae 436 __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
bogdanm 20:4263a77256ae 437 __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
bogdanm 20:4263a77256ae 438 __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
bogdanm 20:4263a77256ae 439 __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
bogdanm 20:4263a77256ae 440 __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
bogdanm 20:4263a77256ae 441 __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
bogdanm 20:4263a77256ae 442 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
bogdanm 20:4263a77256ae 443 __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
bogdanm 20:4263a77256ae 444 __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
bogdanm 20:4263a77256ae 445 __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
bogdanm 20:4263a77256ae 446 __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
bogdanm 20:4263a77256ae 447 } LPC_I2C_TypeDef;
bogdanm 20:4263a77256ae 448 /*@}*/ /* end of group LPC11xx_I2C */
bogdanm 20:4263a77256ae 449
bogdanm 20:4263a77256ae 450
bogdanm 20:4263a77256ae 451 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
bogdanm 20:4263a77256ae 452 /** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer
bogdanm 20:4263a77256ae 453 @{
bogdanm 20:4263a77256ae 454 */
bogdanm 20:4263a77256ae 455 typedef struct
bogdanm 20:4263a77256ae 456 {
bogdanm 20:4263a77256ae 457 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
bogdanm 20:4263a77256ae 458 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
bogdanm 20:4263a77256ae 459 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
bogdanm 20:4263a77256ae 460 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
bogdanm 20:4263a77256ae 461 uint32_t RESERVED0;
bogdanm 20:4263a77256ae 462 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
bogdanm 20:4263a77256ae 463 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
bogdanm 20:4263a77256ae 464 } LPC_WDT_TypeDef;
bogdanm 20:4263a77256ae 465 /*@}*/ /* end of group LPC11xx_WDT */
bogdanm 20:4263a77256ae 466
bogdanm 20:4263a77256ae 467
bogdanm 20:4263a77256ae 468 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
bogdanm 20:4263a77256ae 469 /** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter
bogdanm 20:4263a77256ae 470 @{
bogdanm 20:4263a77256ae 471 */
bogdanm 20:4263a77256ae 472 typedef struct
bogdanm 20:4263a77256ae 473 {
bogdanm 20:4263a77256ae 474 __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
bogdanm 20:4263a77256ae 475 __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
bogdanm 20:4263a77256ae 476 uint32_t RESERVED0;
bogdanm 20:4263a77256ae 477 __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
bogdanm 20:4263a77256ae 478 __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
bogdanm 20:4263a77256ae 479 __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
bogdanm 20:4263a77256ae 480 } LPC_ADC_TypeDef;
bogdanm 20:4263a77256ae 481 /*@}*/ /* end of group LPC11xx_ADC */
bogdanm 20:4263a77256ae 482
bogdanm 20:4263a77256ae 483
bogdanm 20:4263a77256ae 484 /*------------- CAN Controller (CAN) ----------------------------*/
bogdanm 20:4263a77256ae 485 /** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN)
bogdanm 20:4263a77256ae 486 @{
bogdanm 20:4263a77256ae 487 */
bogdanm 20:4263a77256ae 488 typedef struct
bogdanm 20:4263a77256ae 489 {
bogdanm 20:4263a77256ae 490 __IO uint32_t CNTL; /* 0x000 */
bogdanm 20:4263a77256ae 491 __IO uint32_t STAT;
bogdanm 20:4263a77256ae 492 __IO uint32_t EC;
bogdanm 20:4263a77256ae 493 __IO uint32_t BT;
bogdanm 20:4263a77256ae 494 __IO uint32_t INT;
bogdanm 20:4263a77256ae 495 __IO uint32_t TEST;
bogdanm 20:4263a77256ae 496 __IO uint32_t BRPE;
bogdanm 20:4263a77256ae 497 uint32_t RESERVED0;
bogdanm 20:4263a77256ae 498 __IO uint32_t IF1_CMDREQ; /* 0x020 */
bogdanm 20:4263a77256ae 499 __IO uint32_t IF1_CMDMSK;
bogdanm 20:4263a77256ae 500 __IO uint32_t IF1_MSK1;
bogdanm 20:4263a77256ae 501 __IO uint32_t IF1_MSK2;
bogdanm 20:4263a77256ae 502 __IO uint32_t IF1_ARB1;
bogdanm 20:4263a77256ae 503 __IO uint32_t IF1_ARB2;
bogdanm 20:4263a77256ae 504 __IO uint32_t IF1_MCTRL;
bogdanm 20:4263a77256ae 505 __IO uint32_t IF1_DA1;
bogdanm 20:4263a77256ae 506 __IO uint32_t IF1_DA2;
bogdanm 20:4263a77256ae 507 __IO uint32_t IF1_DB1;
bogdanm 20:4263a77256ae 508 __IO uint32_t IF1_DB2;
bogdanm 20:4263a77256ae 509 uint32_t RESERVED1[13];
bogdanm 20:4263a77256ae 510 __IO uint32_t IF2_CMDREQ; /* 0x080 */
bogdanm 20:4263a77256ae 511 __IO uint32_t IF2_CMDMSK;
bogdanm 20:4263a77256ae 512 __IO uint32_t IF2_MSK1;
bogdanm 20:4263a77256ae 513 __IO uint32_t IF2_MSK2;
bogdanm 20:4263a77256ae 514 __IO uint32_t IF2_ARB1;
bogdanm 20:4263a77256ae 515 __IO uint32_t IF2_ARB2;
bogdanm 20:4263a77256ae 516 __IO uint32_t IF2_MCTRL;
bogdanm 20:4263a77256ae 517 __IO uint32_t IF2_DA1;
bogdanm 20:4263a77256ae 518 __IO uint32_t IF2_DA2;
bogdanm 20:4263a77256ae 519 __IO uint32_t IF2_DB1;
bogdanm 20:4263a77256ae 520 __IO uint32_t IF2_DB2;
bogdanm 20:4263a77256ae 521 uint32_t RESERVED2[21];
bogdanm 20:4263a77256ae 522 __I uint32_t TXREQ1; /* 0x100 */
bogdanm 20:4263a77256ae 523 __I uint32_t TXREQ2;
bogdanm 20:4263a77256ae 524 uint32_t RESERVED3[6];
bogdanm 20:4263a77256ae 525 __I uint32_t ND1; /* 0x120 */
bogdanm 20:4263a77256ae 526 __I uint32_t ND2;
bogdanm 20:4263a77256ae 527 uint32_t RESERVED4[6];
bogdanm 20:4263a77256ae 528 __I uint32_t IR1; /* 0x140 */
bogdanm 20:4263a77256ae 529 __I uint32_t IR2;
bogdanm 20:4263a77256ae 530 uint32_t RESERVED5[6];
bogdanm 20:4263a77256ae 531 __I uint32_t MSGV1; /* 0x160 */
bogdanm 20:4263a77256ae 532 __I uint32_t MSGV2;
bogdanm 20:4263a77256ae 533 uint32_t RESERVED6[6];
bogdanm 20:4263a77256ae 534 __IO uint32_t CLKDIV; /* 0x180 */
bogdanm 20:4263a77256ae 535 } LPC_CAN_TypeDef;
bogdanm 20:4263a77256ae 536 /*@}*/ /* end of group LPC11xx_CAN */
bogdanm 20:4263a77256ae 537
bogdanm 20:4263a77256ae 538 #if defined ( __CC_ARM )
bogdanm 20:4263a77256ae 539 #pragma no_anon_unions
bogdanm 20:4263a77256ae 540 #endif
bogdanm 20:4263a77256ae 541
bogdanm 20:4263a77256ae 542 /******************************************************************************/
bogdanm 20:4263a77256ae 543 /* Peripheral memory map */
bogdanm 20:4263a77256ae 544 /******************************************************************************/
bogdanm 20:4263a77256ae 545 /* Base addresses */
bogdanm 20:4263a77256ae 546 #define LPC_FLASH_BASE (0x00000000UL)
bogdanm 20:4263a77256ae 547 #define LPC_RAM_BASE (0x10000000UL)
bogdanm 20:4263a77256ae 548 #define LPC_APB0_BASE (0x40000000UL)
bogdanm 20:4263a77256ae 549 #define LPC_AHB_BASE (0x50000000UL)
bogdanm 20:4263a77256ae 550
bogdanm 20:4263a77256ae 551 /* APB0 peripherals */
bogdanm 20:4263a77256ae 552 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
bogdanm 20:4263a77256ae 553 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
bogdanm 20:4263a77256ae 554 #define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
bogdanm 20:4263a77256ae 555 #define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
bogdanm 20:4263a77256ae 556 #define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
bogdanm 20:4263a77256ae 557 #define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
bogdanm 20:4263a77256ae 558 #define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
bogdanm 20:4263a77256ae 559 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
bogdanm 20:4263a77256ae 560 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
bogdanm 20:4263a77256ae 561 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x3C000)
bogdanm 20:4263a77256ae 562 #define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000)
bogdanm 20:4263a77256ae 563 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
bogdanm 20:4263a77256ae 564 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
bogdanm 20:4263a77256ae 565 #define LPC_CAN_BASE (LPC_APB0_BASE + 0x50000)
bogdanm 20:4263a77256ae 566 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000)
bogdanm 20:4263a77256ae 567
bogdanm 20:4263a77256ae 568 /* AHB peripherals */
bogdanm 20:4263a77256ae 569 #define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
bogdanm 20:4263a77256ae 570 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
bogdanm 20:4263a77256ae 571 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
bogdanm 20:4263a77256ae 572 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
bogdanm 20:4263a77256ae 573 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
bogdanm 20:4263a77256ae 574
bogdanm 20:4263a77256ae 575 /******************************************************************************/
bogdanm 20:4263a77256ae 576 /* Peripheral declaration */
bogdanm 20:4263a77256ae 577 /******************************************************************************/
bogdanm 20:4263a77256ae 578 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
bogdanm 20:4263a77256ae 579 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
bogdanm 20:4263a77256ae 580 #define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
bogdanm 20:4263a77256ae 581 #define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
bogdanm 20:4263a77256ae 582 #define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
bogdanm 20:4263a77256ae 583 #define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
bogdanm 20:4263a77256ae 584 #define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
bogdanm 20:4263a77256ae 585 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
bogdanm 20:4263a77256ae 586 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
bogdanm 20:4263a77256ae 587 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
bogdanm 20:4263a77256ae 588 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
bogdanm 20:4263a77256ae 589 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
bogdanm 20:4263a77256ae 590 #define LPC_CAN ((LPC_CAN_TypeDef *) LPC_CAN_BASE )
bogdanm 20:4263a77256ae 591 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
bogdanm 20:4263a77256ae 592 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
bogdanm 20:4263a77256ae 593 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
bogdanm 20:4263a77256ae 594 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
bogdanm 20:4263a77256ae 595 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
bogdanm 20:4263a77256ae 596 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
bogdanm 20:4263a77256ae 597
bogdanm 20:4263a77256ae 598 #ifdef __cplusplus
bogdanm 20:4263a77256ae 599 }
bogdanm 20:4263a77256ae 600 #endif
bogdanm 20:4263a77256ae 601
bogdanm 20:4263a77256ae 602 #endif /* __LPC11xx_H__ */