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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.h@168:9672193075cf, 2017-07-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Jul 06 15:42:05 2017 +0100
Revision:
168:9672193075cf
Parent:
161:2cc1468da177 
This updates the lib to the mbed lib v 146

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_adc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 168:9672193075cf 5 * @version V1.2.2
AnnaBridge 168:9672193075cf 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of ADC HAL extension module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 168:9672193075cf 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_ADC_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_ADC_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup ADC
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup ADC_Exported_Types ADC Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief Structure definition of ADC and regular group initialization
<> 144:ef7eb2e8f9f7 64 * @note Parameters of this structure are shared within 2 scopes:
<> 144:ef7eb2e8f9f7 65 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
<> 144:ef7eb2e8f9f7 66 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
<> 144:ef7eb2e8f9f7 67 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 68 * ADC state can be either:
<> 144:ef7eb2e8f9f7 69 * - For all parameters: ADC disabled
<> 144:ef7eb2e8f9f7 70 * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
<> 144:ef7eb2e8f9f7 71 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
<> 144:ef7eb2e8f9f7 72 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<> 144:ef7eb2e8f9f7 73 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75 typedef struct
<> 144:ef7eb2e8f9f7 76 {
<> 144:ef7eb2e8f9f7 77 uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
<> 144:ef7eb2e8f9f7 78 all the ADCs.
<> 144:ef7eb2e8f9f7 79 This parameter can be a value of @ref ADC_ClockPrescaler */
<> 144:ef7eb2e8f9f7 80 uint32_t Resolution; /*!< Configures the ADC resolution.
<> 144:ef7eb2e8f9f7 81 This parameter can be a value of @ref ADC_Resolution */
<> 144:ef7eb2e8f9f7 82 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
<> 144:ef7eb2e8f9f7 83 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
<> 144:ef7eb2e8f9f7 84 This parameter can be a value of @ref ADC_Data_Align */
<> 144:ef7eb2e8f9f7 85 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
<> 144:ef7eb2e8f9f7 86 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
<> 144:ef7eb2e8f9f7 87 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
<> 144:ef7eb2e8f9f7 88 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
<> 144:ef7eb2e8f9f7 89 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
<> 144:ef7eb2e8f9f7 90 Scan direction is upward: from rank1 to rank 'n'.
<> 161:2cc1468da177 91 This parameter can be a value of @ref ADC_Scan_mode.
<> 144:ef7eb2e8f9f7 92 This parameter can be set to ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 93 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
<> 144:ef7eb2e8f9f7 94 This parameter can be a value of @ref ADC_EOCSelection.
<> 144:ef7eb2e8f9f7 95 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
<> 144:ef7eb2e8f9f7 96 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
<> 144:ef7eb2e8f9f7 97 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
<> 144:ef7eb2e8f9f7 98 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
<> 144:ef7eb2e8f9f7 99 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
<> 144:ef7eb2e8f9f7 100 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
<> 144:ef7eb2e8f9f7 101 after the selected trigger occurred (software start or external trigger).
<> 144:ef7eb2e8f9f7 102 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 103 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<> 144:ef7eb2e8f9f7 104 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<> 144:ef7eb2e8f9f7 105 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
<> 144:ef7eb2e8f9f7 106 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<> 144:ef7eb2e8f9f7 107 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<> 144:ef7eb2e8f9f7 108 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<> 144:ef7eb2e8f9f7 109 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 110 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
<> 144:ef7eb2e8f9f7 111 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
<> 144:ef7eb2e8f9f7 112 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
<> 144:ef7eb2e8f9f7 113 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
<> 144:ef7eb2e8f9f7 114 If set to ADC_SOFTWARE_START, external triggers are disabled.
<> 144:ef7eb2e8f9f7 115 If set to external trigger source, triggering is on event rising edge by default.
<> 144:ef7eb2e8f9f7 116 This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
<> 144:ef7eb2e8f9f7 117 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
<> 144:ef7eb2e8f9f7 118 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
<> 144:ef7eb2e8f9f7 119 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
<> 144:ef7eb2e8f9f7 120 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
<> 144:ef7eb2e8f9f7 121 or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
<> 144:ef7eb2e8f9f7 122 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
<> 144:ef7eb2e8f9f7 123 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
<> 144:ef7eb2e8f9f7 124 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 125 }ADC_InitTypeDef;
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /**
<> 144:ef7eb2e8f9f7 130 * @brief Structure definition of ADC channel for regular group
<> 144:ef7eb2e8f9f7 131 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 132 * ADC can be either disabled or enabled without conversion on going on regular group.
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134 typedef struct
<> 144:ef7eb2e8f9f7 135 {
<> 144:ef7eb2e8f9f7 136 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
<> 144:ef7eb2e8f9f7 137 This parameter can be a value of @ref ADC_channels */
<> 144:ef7eb2e8f9f7 138 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
<> 161:2cc1468da177 139 This parameter must be a number between Min_Data = 1 and Max_Data = 16
<> 161:2cc1468da177 140 This parameter can be a value of @ref ADC_regular_rank */
<> 144:ef7eb2e8f9f7 141 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
<> 144:ef7eb2e8f9f7 142 Unit: ADC clock cycles
<> 144:ef7eb2e8f9f7 143 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
<> 144:ef7eb2e8f9f7 144 This parameter can be a value of @ref ADC_sampling_times
<> 144:ef7eb2e8f9f7 145 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<> 144:ef7eb2e8f9f7 146 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<> 144:ef7eb2e8f9f7 147 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<> 144:ef7eb2e8f9f7 148 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<> 144:ef7eb2e8f9f7 149 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
<> 144:ef7eb2e8f9f7 150 uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
<> 144:ef7eb2e8f9f7 151 }ADC_ChannelConfTypeDef;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @brief ADC Configuration multi-mode structure definition
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 typedef struct
<> 144:ef7eb2e8f9f7 157 {
<> 144:ef7eb2e8f9f7 158 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
<> 144:ef7eb2e8f9f7 159 This parameter can be a value of @ref ADC_analog_watchdog_selection */
<> 144:ef7eb2e8f9f7 160 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<> 144:ef7eb2e8f9f7 161 This parameter must be a 12-bit value. */
<> 144:ef7eb2e8f9f7 162 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<> 144:ef7eb2e8f9f7 163 This parameter must be a 12-bit value. */
<> 144:ef7eb2e8f9f7 164 uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
<> 144:ef7eb2e8f9f7 165 This parameter has an effect only if watchdog mode is configured on single channel
<> 144:ef7eb2e8f9f7 166 This parameter can be a value of @ref ADC_channels */
<> 144:ef7eb2e8f9f7 167 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
<> 144:ef7eb2e8f9f7 168 is interrupt mode or in polling mode.
<> 144:ef7eb2e8f9f7 169 This parameter can be set to ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 170 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
<> 144:ef7eb2e8f9f7 171 }ADC_AnalogWDGConfTypeDef;
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /**
<> 144:ef7eb2e8f9f7 174 * @brief HAL ADC state machine: ADC states definition (bitfields)
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 /* States of ADC global scope */
<> 144:ef7eb2e8f9f7 177 #define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 178 #define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
<> 144:ef7eb2e8f9f7 179 #define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
<> 144:ef7eb2e8f9f7 180 #define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* States of ADC errors */
<> 144:ef7eb2e8f9f7 183 #define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
<> 144:ef7eb2e8f9f7 184 #define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
<> 144:ef7eb2e8f9f7 185 #define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* States of ADC group regular */
<> 144:ef7eb2e8f9f7 188 #define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
<> 144:ef7eb2e8f9f7 189 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
<> 144:ef7eb2e8f9f7 190 #define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
<> 144:ef7eb2e8f9f7 191 #define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* States of ADC group injected */
<> 144:ef7eb2e8f9f7 194 #define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
<> 144:ef7eb2e8f9f7 195 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
<> 144:ef7eb2e8f9f7 196 #define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* States of ADC analog watchdogs */
<> 144:ef7eb2e8f9f7 199 #define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
<> 144:ef7eb2e8f9f7 200 #define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
<> 144:ef7eb2e8f9f7 201 #define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* States of ADC multi-mode */
<> 144:ef7eb2e8f9f7 204 #define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @brief ADC handle Structure definition
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210 typedef struct
<> 144:ef7eb2e8f9f7 211 {
<> 144:ef7eb2e8f9f7 212 ADC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 ADC_InitTypeDef Init; /*!< ADC required parameters */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 HAL_LockTypeDef Lock; /*!< ADC locking object */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 __IO uint32_t State; /*!< ADC communication state */
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 __IO uint32_t ErrorCode; /*!< ADC Error code */
<> 144:ef7eb2e8f9f7 225 }ADC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @}
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 231 /** @defgroup ADC_Exported_Constants ADC Exported Constants
<> 144:ef7eb2e8f9f7 232 * @{
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /** @defgroup ADC_Error_Code ADC Error Code
<> 144:ef7eb2e8f9f7 236 * @{
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
<> 144:ef7eb2e8f9f7 239 #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
<> 144:ef7eb2e8f9f7 240 enable/disable, erroneous state */
<> 144:ef7eb2e8f9f7 241 #define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
<> 144:ef7eb2e8f9f7 242 #define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @}
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
<> 144:ef7eb2e8f9f7 249 * @{
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 252 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
<> 144:ef7eb2e8f9f7 253 #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
<> 144:ef7eb2e8f9f7 254 #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @}
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
<> 144:ef7eb2e8f9f7 260 * @{
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 263 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
<> 144:ef7eb2e8f9f7 264 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
<> 144:ef7eb2e8f9f7 265 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
<> 144:ef7eb2e8f9f7 266 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
<> 144:ef7eb2e8f9f7 267 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
<> 144:ef7eb2e8f9f7 268 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
<> 144:ef7eb2e8f9f7 269 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
<> 144:ef7eb2e8f9f7 270 #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
<> 144:ef7eb2e8f9f7 271 #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
<> 144:ef7eb2e8f9f7 272 #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
<> 144:ef7eb2e8f9f7 273 #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
<> 144:ef7eb2e8f9f7 274 #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
<> 144:ef7eb2e8f9f7 275 #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
<> 144:ef7eb2e8f9f7 276 #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
<> 144:ef7eb2e8f9f7 277 #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @}
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /** @defgroup ADC_Resolution ADC Resolution
<> 144:ef7eb2e8f9f7 283 * @{
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 #define ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 286 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
<> 144:ef7eb2e8f9f7 287 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
<> 144:ef7eb2e8f9f7 288 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @}
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
<> 144:ef7eb2e8f9f7 294 * @{
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 297 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
<> 144:ef7eb2e8f9f7 298 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
<> 144:ef7eb2e8f9f7 299 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @}
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
<> 144:ef7eb2e8f9f7 305 * @{
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
<> 144:ef7eb2e8f9f7 308 /* compatibility with other STM32 devices. */
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 #define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 312 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
<> 144:ef7eb2e8f9f7 313 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
<> 144:ef7eb2e8f9f7 314 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 315 #define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
<> 144:ef7eb2e8f9f7 316 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 317 #define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
<> 144:ef7eb2e8f9f7 318 #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 319 #define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3)
<> 144:ef7eb2e8f9f7 320 #define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 321 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
<> 144:ef7eb2e8f9f7 322 #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 323 #define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
<> 144:ef7eb2e8f9f7 324 #define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL)
<> 144:ef7eb2e8f9f7 327 #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @}
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /** @defgroup ADC_Data_Align ADC Data Align
<> 144:ef7eb2e8f9f7 334 * @{
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 337 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @}
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341
<> 161:2cc1468da177 342 /** @defgroup ADC_Scan_mode ADC sequencer scan mode
<> 161:2cc1468da177 343 * @{
<> 161:2cc1468da177 344 */
<> 161:2cc1468da177 345 #define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */
<> 161:2cc1468da177 346 #define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */
<> 161:2cc1468da177 347 /**
<> 161:2cc1468da177 348 * @}
<> 161:2cc1468da177 349 */
<> 161:2cc1468da177 350
<> 161:2cc1468da177 351 /** @defgroup ADC_regular_rank ADC group regular sequencer rank
<> 161:2cc1468da177 352 * @{
<> 161:2cc1468da177 353 */
<> 161:2cc1468da177 354 #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */
<> 161:2cc1468da177 355 #define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */
<> 161:2cc1468da177 356 #define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */
<> 161:2cc1468da177 357 #define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */
<> 161:2cc1468da177 358 #define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */
<> 161:2cc1468da177 359 #define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */
<> 161:2cc1468da177 360 #define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */
<> 161:2cc1468da177 361 #define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */
<> 161:2cc1468da177 362 #define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */
<> 161:2cc1468da177 363 #define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */
<> 161:2cc1468da177 364 #define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */
<> 161:2cc1468da177 365 #define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */
<> 161:2cc1468da177 366 #define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */
<> 161:2cc1468da177 367 #define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */
<> 161:2cc1468da177 368 #define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */
<> 161:2cc1468da177 369 #define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */
<> 161:2cc1468da177 370 /**
<> 161:2cc1468da177 371 * @}
<> 161:2cc1468da177 372 */
<> 161:2cc1468da177 373
<> 144:ef7eb2e8f9f7 374 /** @defgroup ADC_channels ADC Common Channels
<> 144:ef7eb2e8f9f7 375 * @{
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377 #define ADC_CHANNEL_0 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 378 #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
<> 144:ef7eb2e8f9f7 379 #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
<> 144:ef7eb2e8f9f7 380 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
<> 144:ef7eb2e8f9f7 381 #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
<> 144:ef7eb2e8f9f7 382 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
<> 144:ef7eb2e8f9f7 383 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
<> 144:ef7eb2e8f9f7 384 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
<> 144:ef7eb2e8f9f7 385 #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
<> 144:ef7eb2e8f9f7 386 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
<> 144:ef7eb2e8f9f7 387 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
<> 144:ef7eb2e8f9f7 388 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
<> 144:ef7eb2e8f9f7 389 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
<> 144:ef7eb2e8f9f7 390 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
<> 144:ef7eb2e8f9f7 391 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
<> 144:ef7eb2e8f9f7 392 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
<> 144:ef7eb2e8f9f7 393 #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
<> 144:ef7eb2e8f9f7 394 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
<> 144:ef7eb2e8f9f7 395 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
<> 144:ef7eb2e8f9f7 398 #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
<> 144:ef7eb2e8f9f7 399 /**
<> 144:ef7eb2e8f9f7 400 * @}
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /** @defgroup ADC_sampling_times ADC Sampling Times
<> 144:ef7eb2e8f9f7 404 * @{
<> 144:ef7eb2e8f9f7 405 */
<> 144:ef7eb2e8f9f7 406 #define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 407 #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
<> 144:ef7eb2e8f9f7 408 #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
<> 144:ef7eb2e8f9f7 409 #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
<> 144:ef7eb2e8f9f7 410 #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
<> 144:ef7eb2e8f9f7 411 #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
<> 144:ef7eb2e8f9f7 412 #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
<> 144:ef7eb2e8f9f7 413 #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
<> 144:ef7eb2e8f9f7 414 /**
<> 144:ef7eb2e8f9f7 415 * @}
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /** @defgroup ADC_EOCSelection ADC EOC Selection
<> 144:ef7eb2e8f9f7 419 * @{
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421 #define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 422 #define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 423 #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */
<> 144:ef7eb2e8f9f7 424 /**
<> 144:ef7eb2e8f9f7 425 * @}
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /** @defgroup ADC_Event_type ADC Event Type
<> 144:ef7eb2e8f9f7 429 * @{
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
<> 144:ef7eb2e8f9f7 432 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
<> 144:ef7eb2e8f9f7 433 /**
<> 144:ef7eb2e8f9f7 434 * @}
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
<> 144:ef7eb2e8f9f7 438 * @{
<> 144:ef7eb2e8f9f7 439 */
<> 144:ef7eb2e8f9f7 440 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
<> 144:ef7eb2e8f9f7 441 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
<> 144:ef7eb2e8f9f7 442 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
<> 144:ef7eb2e8f9f7 443 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
<> 144:ef7eb2e8f9f7 444 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
<> 144:ef7eb2e8f9f7 445 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
<> 144:ef7eb2e8f9f7 446 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 447 /**
<> 144:ef7eb2e8f9f7 448 * @}
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
<> 144:ef7eb2e8f9f7 452 * @{
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454 #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
<> 144:ef7eb2e8f9f7 455 #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
<> 144:ef7eb2e8f9f7 456 #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
<> 144:ef7eb2e8f9f7 457 #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
<> 144:ef7eb2e8f9f7 458 /**
<> 144:ef7eb2e8f9f7 459 * @}
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /** @defgroup ADC_flags_definition ADC Flags Definition
<> 144:ef7eb2e8f9f7 463 * @{
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465 #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
<> 144:ef7eb2e8f9f7 466 #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
<> 144:ef7eb2e8f9f7 467 #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
<> 144:ef7eb2e8f9f7 468 #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
<> 144:ef7eb2e8f9f7 469 #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
<> 144:ef7eb2e8f9f7 470 #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
<> 144:ef7eb2e8f9f7 471 /**
<> 144:ef7eb2e8f9f7 472 * @}
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /** @defgroup ADC_channels_type ADC Channels Type
<> 144:ef7eb2e8f9f7 476 * @{
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478 #define ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 479 #define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */
<> 144:ef7eb2e8f9f7 480 #define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
<> 144:ef7eb2e8f9f7 481 /**
<> 144:ef7eb2e8f9f7 482 * @}
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /**
<> 144:ef7eb2e8f9f7 486 * @}
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 490 /** @defgroup ADC_Exported_Macros ADC Exported Macros
<> 144:ef7eb2e8f9f7 491 * @{
<> 144:ef7eb2e8f9f7 492 */
AnnaBridge 168:9672193075cf 493
<> 144:ef7eb2e8f9f7 494 /** @brief Reset ADC handle state
<> 144:ef7eb2e8f9f7 495 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 496 * @retval None
<> 144:ef7eb2e8f9f7 497 */
<> 144:ef7eb2e8f9f7 498 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /**
<> 144:ef7eb2e8f9f7 501 * @brief Enable the ADC peripheral.
<> 144:ef7eb2e8f9f7 502 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 503 * @retval None
<> 144:ef7eb2e8f9f7 504 */
<> 144:ef7eb2e8f9f7 505 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /**
<> 144:ef7eb2e8f9f7 508 * @brief Disable the ADC peripheral.
<> 144:ef7eb2e8f9f7 509 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 510 * @retval None
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /**
<> 144:ef7eb2e8f9f7 515 * @brief Enable the ADC end of conversion interrupt.
<> 144:ef7eb2e8f9f7 516 * @param __HANDLE__: specifies the ADC Handle.
<> 144:ef7eb2e8f9f7 517 * @param __INTERRUPT__: ADC Interrupt.
<> 144:ef7eb2e8f9f7 518 * @retval None
<> 144:ef7eb2e8f9f7 519 */
<> 144:ef7eb2e8f9f7 520 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /**
<> 144:ef7eb2e8f9f7 523 * @brief Disable the ADC end of conversion interrupt.
<> 144:ef7eb2e8f9f7 524 * @param __HANDLE__: specifies the ADC Handle.
<> 144:ef7eb2e8f9f7 525 * @param __INTERRUPT__: ADC interrupt.
<> 144:ef7eb2e8f9f7 526 * @retval None
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /** @brief Check if the specified ADC interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 531 * @param __HANDLE__: specifies the ADC Handle.
<> 144:ef7eb2e8f9f7 532 * @param __INTERRUPT__: specifies the ADC interrupt source to check.
<> 144:ef7eb2e8f9f7 533 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /**
<> 144:ef7eb2e8f9f7 538 * @brief Clear the ADC's pending flags.
<> 144:ef7eb2e8f9f7 539 * @param __HANDLE__: specifies the ADC Handle.
<> 144:ef7eb2e8f9f7 540 * @param __FLAG__: ADC flag.
<> 144:ef7eb2e8f9f7 541 * @retval None
<> 144:ef7eb2e8f9f7 542 */
<> 144:ef7eb2e8f9f7 543 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /**
<> 144:ef7eb2e8f9f7 546 * @brief Get the selected ADC's flag status.
<> 144:ef7eb2e8f9f7 547 * @param __HANDLE__: specifies the ADC Handle.
<> 144:ef7eb2e8f9f7 548 * @param __FLAG__: ADC flag.
<> 144:ef7eb2e8f9f7 549 * @retval None
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /**
<> 144:ef7eb2e8f9f7 554 * @}
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* Include ADC HAL Extension module */
<> 144:ef7eb2e8f9f7 558 #include "stm32f7xx_hal_adc_ex.h"
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 561 /** @addtogroup ADC_Exported_Functions
<> 144:ef7eb2e8f9f7 562 * @{
<> 144:ef7eb2e8f9f7 563 */
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /** @addtogroup ADC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 566 * @{
<> 144:ef7eb2e8f9f7 567 */
<> 144:ef7eb2e8f9f7 568 /* Initialization/de-initialization functions ***********************************/
<> 144:ef7eb2e8f9f7 569 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 570 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 571 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 572 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 573 /**
<> 144:ef7eb2e8f9f7 574 * @}
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /** @addtogroup ADC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 578 * @{
<> 144:ef7eb2e8f9f7 579 */
<> 144:ef7eb2e8f9f7 580 /* I/O operation functions ******************************************************/
<> 144:ef7eb2e8f9f7 581 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 582 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 583 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 588 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
<> 144:ef7eb2e8f9f7 593 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 598 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 599 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 600 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 601 /**
<> 144:ef7eb2e8f9f7 602 * @}
<> 144:ef7eb2e8f9f7 603 */
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /** @addtogroup ADC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 606 * @{
<> 144:ef7eb2e8f9f7 607 */
<> 144:ef7eb2e8f9f7 608 /* Peripheral Control functions *************************************************/
<> 144:ef7eb2e8f9f7 609 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
<> 144:ef7eb2e8f9f7 610 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
<> 144:ef7eb2e8f9f7 611 /**
<> 144:ef7eb2e8f9f7 612 * @}
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /** @addtogroup ADC_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 616 * @{
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618 /* Peripheral State functions ***************************************************/
<> 144:ef7eb2e8f9f7 619 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 620 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 621 /**
<> 144:ef7eb2e8f9f7 622 * @}
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /**
<> 144:ef7eb2e8f9f7 626 * @}
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 630 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 631 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 632 /** @defgroup ADC_Private_Constants ADC Private Constants
<> 144:ef7eb2e8f9f7 633 * @{
<> 144:ef7eb2e8f9f7 634 */
<> 144:ef7eb2e8f9f7 635 /* Delay for ADC stabilization time. */
<> 144:ef7eb2e8f9f7 636 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
<> 144:ef7eb2e8f9f7 637 /* Unit: us */
<> 144:ef7eb2e8f9f7 638 #define ADC_STAB_DELAY_US ((uint32_t) 3U)
<> 144:ef7eb2e8f9f7 639 /* Delay for temperature sensor stabilization time. */
<> 144:ef7eb2e8f9f7 640 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
<> 144:ef7eb2e8f9f7 641 /* Unit: us */
<> 144:ef7eb2e8f9f7 642 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
<> 144:ef7eb2e8f9f7 643 /**
<> 144:ef7eb2e8f9f7 644 * @}
<> 144:ef7eb2e8f9f7 645 */
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 648 /** @defgroup ADC_Private_Macros ADC Private Macros
<> 144:ef7eb2e8f9f7 649 * @{
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651 /* Macro reserved for internal HAL driver usage, not intended to be used in
<> 144:ef7eb2e8f9f7 652 code of final user */
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /**
<> 144:ef7eb2e8f9f7 655 * @brief Verification of ADC state: enabled or disabled
<> 144:ef7eb2e8f9f7 656 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 657 * @retval SET (ADC enabled) or RESET (ADC disabled)
<> 144:ef7eb2e8f9f7 658 */
<> 144:ef7eb2e8f9f7 659 #define ADC_IS_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 660 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
<> 144:ef7eb2e8f9f7 661 ) ? SET : RESET)
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /**
<> 144:ef7eb2e8f9f7 664 * @brief Test if conversion trigger of regular group is software start
<> 144:ef7eb2e8f9f7 665 * or external trigger.
<> 144:ef7eb2e8f9f7 666 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 667 * @retval SET (software start) or RESET (external trigger)
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
<> 144:ef7eb2e8f9f7 670 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /**
<> 144:ef7eb2e8f9f7 673 * @brief Test if conversion trigger of injected group is software start
<> 144:ef7eb2e8f9f7 674 * or external trigger.
<> 144:ef7eb2e8f9f7 675 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 676 * @retval SET (software start) or RESET (external trigger)
<> 144:ef7eb2e8f9f7 677 */
<> 144:ef7eb2e8f9f7 678 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
<> 144:ef7eb2e8f9f7 679 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /**
<> 144:ef7eb2e8f9f7 682 * @brief Simultaneously clears and sets specific bits of the handle State
<> 144:ef7eb2e8f9f7 683 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
<> 144:ef7eb2e8f9f7 684 * the first parameter is the ADC handle State, the second parameter is the
<> 144:ef7eb2e8f9f7 685 * bit field to clear, the third and last parameter is the bit field to set.
<> 144:ef7eb2e8f9f7 686 * @retval None
<> 144:ef7eb2e8f9f7 687 */
<> 144:ef7eb2e8f9f7 688 #define ADC_STATE_CLR_SET MODIFY_REG
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /**
<> 144:ef7eb2e8f9f7 691 * @brief Clear ADC error code (set it to error code: "no error")
<> 144:ef7eb2e8f9f7 692 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 693 * @retval None
<> 144:ef7eb2e8f9f7 694 */
<> 144:ef7eb2e8f9f7 695 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 696 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
<> 144:ef7eb2e8f9f7 697 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
<> 144:ef7eb2e8f9f7 698 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
<> 144:ef7eb2e8f9f7 699 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
<> 144:ef7eb2e8f9f7 700 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))
<> 144:ef7eb2e8f9f7 701 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
<> 144:ef7eb2e8f9f7 702 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
<> 144:ef7eb2e8f9f7 703 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
<> 144:ef7eb2e8f9f7 704 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
<> 144:ef7eb2e8f9f7 705 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
<> 144:ef7eb2e8f9f7 706 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
<> 144:ef7eb2e8f9f7 707 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
<> 144:ef7eb2e8f9f7 708 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
<> 144:ef7eb2e8f9f7 709 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
<> 144:ef7eb2e8f9f7 710 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
<> 144:ef7eb2e8f9f7 711 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
<> 144:ef7eb2e8f9f7 712 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
<> 144:ef7eb2e8f9f7 713 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
<> 144:ef7eb2e8f9f7 714 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
<> 144:ef7eb2e8f9f7 715 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
<> 144:ef7eb2e8f9f7 716 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))
<> 144:ef7eb2e8f9f7 717 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
<> 144:ef7eb2e8f9f7 718 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
<> 144:ef7eb2e8f9f7 719 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
<> 144:ef7eb2e8f9f7 720 ((__RESOLUTION__) == ADC_RESOLUTION_6B))
<> 144:ef7eb2e8f9f7 721 #define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
<> 144:ef7eb2e8f9f7 722 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
<> 144:ef7eb2e8f9f7 723 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
<> 144:ef7eb2e8f9f7 724 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
<> 144:ef7eb2e8f9f7 725 #define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
<> 144:ef7eb2e8f9f7 726 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
<> 144:ef7eb2e8f9f7 727 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
<> 144:ef7eb2e8f9f7 728 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
<> 144:ef7eb2e8f9f7 729 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) || \
<> 144:ef7eb2e8f9f7 730 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
<> 144:ef7eb2e8f9f7 731 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
<> 144:ef7eb2e8f9f7 732 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
<> 144:ef7eb2e8f9f7 733 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
<> 144:ef7eb2e8f9f7 734 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
<> 144:ef7eb2e8f9f7 735 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
<> 144:ef7eb2e8f9f7 736 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
<> 144:ef7eb2e8f9f7 737 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
<> 144:ef7eb2e8f9f7 738 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
<> 144:ef7eb2e8f9f7 739 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
<> 144:ef7eb2e8f9f7 740 ((__REGTRIG__) == ADC_SOFTWARE_START))
<> 144:ef7eb2e8f9f7 741 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
<> 161:2cc1468da177 742 ((__ALIGN__) == ADC_DATAALIGN_LEFT))
<> 161:2cc1468da177 743
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \
<> 144:ef7eb2e8f9f7 746 ((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \
<> 144:ef7eb2e8f9f7 747 ((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \
<> 144:ef7eb2e8f9f7 748 ((__TIME__) == ADC_SAMPLETIME_56CYCLES) || \
<> 144:ef7eb2e8f9f7 749 ((__TIME__) == ADC_SAMPLETIME_84CYCLES) || \
<> 144:ef7eb2e8f9f7 750 ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \
<> 144:ef7eb2e8f9f7 751 ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \
<> 144:ef7eb2e8f9f7 752 ((__TIME__) == ADC_SAMPLETIME_480CYCLES))
<> 144:ef7eb2e8f9f7 753 #define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) || \
<> 144:ef7eb2e8f9f7 754 ((__EOCSelection__) == ADC_EOC_SEQ_CONV) || \
<> 144:ef7eb2e8f9f7 755 ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))
<> 144:ef7eb2e8f9f7 756 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \
<> 144:ef7eb2e8f9f7 757 ((__EVENT__) == ADC_OVR_EVENT))
<> 144:ef7eb2e8f9f7 758 #define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
<> 144:ef7eb2e8f9f7 759 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
<> 144:ef7eb2e8f9f7 760 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
<> 144:ef7eb2e8f9f7 761 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
<> 144:ef7eb2e8f9f7 762 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
<> 144:ef7eb2e8f9f7 763 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
<> 144:ef7eb2e8f9f7 764 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))
<> 144:ef7eb2e8f9f7 765 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
<> 144:ef7eb2e8f9f7 766 ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
<> 144:ef7eb2e8f9f7 767 ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
<> 161:2cc1468da177 768
<> 161:2cc1468da177 769 #define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \
<> 161:2cc1468da177 770 ((__RANK__) == ADC_REGULAR_RANK_2 ) || \
<> 161:2cc1468da177 771 ((__RANK__) == ADC_REGULAR_RANK_3 ) || \
<> 161:2cc1468da177 772 ((__RANK__) == ADC_REGULAR_RANK_4 ) || \
<> 161:2cc1468da177 773 ((__RANK__) == ADC_REGULAR_RANK_5 ) || \
<> 161:2cc1468da177 774 ((__RANK__) == ADC_REGULAR_RANK_6 ) || \
<> 161:2cc1468da177 775 ((__RANK__) == ADC_REGULAR_RANK_7 ) || \
<> 161:2cc1468da177 776 ((__RANK__) == ADC_REGULAR_RANK_8 ) || \
<> 161:2cc1468da177 777 ((__RANK__) == ADC_REGULAR_RANK_9 ) || \
<> 161:2cc1468da177 778 ((__RANK__) == ADC_REGULAR_RANK_10) || \
<> 161:2cc1468da177 779 ((__RANK__) == ADC_REGULAR_RANK_11) || \
<> 161:2cc1468da177 780 ((__RANK__) == ADC_REGULAR_RANK_12) || \
<> 161:2cc1468da177 781 ((__RANK__) == ADC_REGULAR_RANK_13) || \
<> 161:2cc1468da177 782 ((__RANK__) == ADC_REGULAR_RANK_14) || \
<> 161:2cc1468da177 783 ((__RANK__) == ADC_REGULAR_RANK_15) || \
<> 161:2cc1468da177 784 ((__RANK__) == ADC_REGULAR_RANK_16))
<> 161:2cc1468da177 785
<> 161:2cc1468da177 786 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
<> 161:2cc1468da177 787 ((__SCAN_MODE__) == ADC_SCAN_ENABLE))
<> 161:2cc1468da177 788
<> 144:ef7eb2e8f9f7 789 #define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
<> 144:ef7eb2e8f9f7 790 #define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
<> 144:ef7eb2e8f9f7 791 #define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
<> 144:ef7eb2e8f9f7 792 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
<> 144:ef7eb2e8f9f7 793 ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
<> 144:ef7eb2e8f9f7 794 (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
<> 144:ef7eb2e8f9f7 795 (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
<> 144:ef7eb2e8f9f7 796 (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /**
<> 144:ef7eb2e8f9f7 799 * @brief Set ADC Regular channel sequence length.
<> 144:ef7eb2e8f9f7 800 * @param _NbrOfConversion_: Regular channel sequence length.
<> 144:ef7eb2e8f9f7 801 * @retval None
<> 144:ef7eb2e8f9f7 802 */
<> 144:ef7eb2e8f9f7 803 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /**
<> 144:ef7eb2e8f9f7 806 * @brief Set the ADC's sample time for channel numbers between 10 and 18.
<> 144:ef7eb2e8f9f7 807 * @param _SAMPLETIME_: Sample time parameter.
<> 144:ef7eb2e8f9f7 808 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 809 * @retval None
<> 144:ef7eb2e8f9f7 810 */
<> 144:ef7eb2e8f9f7 811 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /**
<> 144:ef7eb2e8f9f7 814 * @brief Set the ADC's sample time for channel numbers between 0 and 9.
<> 144:ef7eb2e8f9f7 815 * @param _SAMPLETIME_: Sample time parameter.
<> 144:ef7eb2e8f9f7 816 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 817 * @retval None
<> 144:ef7eb2e8f9f7 818 */
<> 144:ef7eb2e8f9f7 819 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /**
<> 144:ef7eb2e8f9f7 822 * @brief Set the selected regular channel rank for rank between 1 and 6.
<> 144:ef7eb2e8f9f7 823 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 824 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 825 * @retval None
<> 144:ef7eb2e8f9f7 826 */
<> 144:ef7eb2e8f9f7 827 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /**
<> 144:ef7eb2e8f9f7 830 * @brief Set the selected regular channel rank for rank between 7 and 12.
<> 144:ef7eb2e8f9f7 831 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 832 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 833 * @retval None
<> 144:ef7eb2e8f9f7 834 */
<> 144:ef7eb2e8f9f7 835 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /**
<> 144:ef7eb2e8f9f7 838 * @brief Set the selected regular channel rank for rank between 13 and 16.
<> 144:ef7eb2e8f9f7 839 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 840 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 841 * @retval None
<> 144:ef7eb2e8f9f7 842 */
<> 144:ef7eb2e8f9f7 843 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /**
<> 144:ef7eb2e8f9f7 846 * @brief Enable ADC continuous conversion mode.
<> 144:ef7eb2e8f9f7 847 * @param _CONTINUOUS_MODE_: Continuous mode.
<> 144:ef7eb2e8f9f7 848 * @retval None
<> 144:ef7eb2e8f9f7 849 */
<> 144:ef7eb2e8f9f7 850 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /**
<> 144:ef7eb2e8f9f7 853 * @brief Configures the number of discontinuous conversions for the regular group channels.
<> 144:ef7eb2e8f9f7 854 * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
<> 144:ef7eb2e8f9f7 855 * @retval None
<> 144:ef7eb2e8f9f7 856 */
<> 144:ef7eb2e8f9f7 857 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /**
<> 144:ef7eb2e8f9f7 860 * @brief Enable ADC scan mode.
<> 144:ef7eb2e8f9f7 861 * @param _SCANCONV_MODE_: Scan conversion mode.
<> 144:ef7eb2e8f9f7 862 * @retval None
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /**
<> 144:ef7eb2e8f9f7 867 * @brief Enable the ADC end of conversion selection.
<> 144:ef7eb2e8f9f7 868 * @param _EOCSelection_MODE_: End of conversion selection mode.
<> 144:ef7eb2e8f9f7 869 * @retval None
<> 144:ef7eb2e8f9f7 870 */
<> 144:ef7eb2e8f9f7 871 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /**
<> 144:ef7eb2e8f9f7 874 * @brief Enable the ADC DMA continuous request.
<> 144:ef7eb2e8f9f7 875 * @param _DMAContReq_MODE_: DMA continuous request mode.
<> 144:ef7eb2e8f9f7 876 * @retval None
<> 144:ef7eb2e8f9f7 877 */
<> 144:ef7eb2e8f9f7 878 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /**
<> 144:ef7eb2e8f9f7 881 * @brief Return resolution bits in CR1 register.
<> 144:ef7eb2e8f9f7 882 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 883 * @retval None
<> 144:ef7eb2e8f9f7 884 */
<> 144:ef7eb2e8f9f7 885 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /**
<> 144:ef7eb2e8f9f7 888 * @}
<> 144:ef7eb2e8f9f7 889 */
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 892 /** @defgroup ADC_Private_Functions ADC Private Functions
<> 144:ef7eb2e8f9f7 893 * @{
<> 144:ef7eb2e8f9f7 894 */
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 /**
<> 144:ef7eb2e8f9f7 897 * @}
<> 144:ef7eb2e8f9f7 898 */
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 /**
<> 144:ef7eb2e8f9f7 901 * @}
<> 144:ef7eb2e8f9f7 902 */
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /**
<> 144:ef7eb2e8f9f7 905 * @}
<> 144:ef7eb2e8f9f7 906 */
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 909 }
<> 144:ef7eb2e8f9f7 910 #endif
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 #endif /*__STM32F7xx_ADC_H */
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/