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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.c@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:: <>
Date:: Thu Feb 02 17:01:33 2017 +0000
Revision:: 157:ff67d9f36b67
Parent:: 149:156823d33999

This updates the lib to the mbed lib v135

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f3xx_hal_usart.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	157:ff67d9f36b67	5	* @version V1.4.0
<>	157:ff67d9f36b67	6	* @date 16-December-2016
<>	144:ef7eb2e8f9f7	7	* @brief USART HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter
<>	144:ef7eb2e8f9f7	10	* Peripheral (USART).
<>	144:ef7eb2e8f9f7	11	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	12	* + IO operation functions
<>	144:ef7eb2e8f9f7	13	* + Peripheral Control functions
<>	144:ef7eb2e8f9f7	14	* + Peripheral State and Error functions
<>	144:ef7eb2e8f9f7	15	*
<>	144:ef7eb2e8f9f7	16	@verbatim
<>	144:ef7eb2e8f9f7	17	===============================================================================
<>	144:ef7eb2e8f9f7	18	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	19	===============================================================================
<>	144:ef7eb2e8f9f7	20	[..]
<>	144:ef7eb2e8f9f7	21	The USART HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	22
<>	144:ef7eb2e8f9f7	23	(#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
<>	144:ef7eb2e8f9f7	24	(#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
<>	144:ef7eb2e8f9f7	25	(++) Enable the USARTx interface clock.
<>	144:ef7eb2e8f9f7	26	(++) USART pins configuration:
<>	144:ef7eb2e8f9f7	27	(+++) Enable the clock for the USART GPIOs.
<>	144:ef7eb2e8f9f7	28	(+++) Configure these USART pins as alternate function pull-up.
<>	144:ef7eb2e8f9f7	29	(++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
<>	144:ef7eb2e8f9f7	30	HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
<>	144:ef7eb2e8f9f7	31	(+++) Configure the USARTx interrupt priority.
<>	144:ef7eb2e8f9f7	32	(+++) Enable the NVIC USART IRQ handle.
<>	144:ef7eb2e8f9f7	33	(++) USART interrupts handling:
<>	144:ef7eb2e8f9f7	34	-@@- The specific USART interrupts (Transmission complete interrupt,
<>	144:ef7eb2e8f9f7	35	RXNE interrupt and Error Interrupts) will be managed using the macros
<>	144:ef7eb2e8f9f7	36	__HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
<>	144:ef7eb2e8f9f7	37	(++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
<>	144:ef7eb2e8f9f7	38	HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
<>	144:ef7eb2e8f9f7	39	(+++) Declare a DMA handle structure for the Tx/Rx channel.
<>	144:ef7eb2e8f9f7	40	(+++) Enable the DMAx interface clock.
<>	144:ef7eb2e8f9f7	41	(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<>	144:ef7eb2e8f9f7	42	(+++) Configure the DMA Tx/Rx channel.
<>	144:ef7eb2e8f9f7	43	(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
<>	144:ef7eb2e8f9f7	44	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
<>	144:ef7eb2e8f9f7	47	flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	(#) Initialize the USART registers by calling the HAL_USART_Init() API:
<>	157:ff67d9f36b67	50	(++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
<>	144:ef7eb2e8f9f7	51	by calling the customized HAL_USART_MspInit(&husart) API.
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	(#) Three operation modes are available within this driver :
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	* Polling mode IO operation *
<>	144:ef7eb2e8f9f7	56	=================================
<>	144:ef7eb2e8f9f7	57	[..]
<>	144:ef7eb2e8f9f7	58	(+) Send an amount of data in blocking mode using HAL_USART_Transmit()
<>	144:ef7eb2e8f9f7	59	(+) Receive an amount of data in blocking mode using HAL_USART_Receive()
<>	144:ef7eb2e8f9f7	60
<>	144:ef7eb2e8f9f7	61	* Interrupt mode IO operation *
<>	144:ef7eb2e8f9f7	62	===================================
<>	144:ef7eb2e8f9f7	63	[..]
<>	144:ef7eb2e8f9f7	64	(+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
<>	144:ef7eb2e8f9f7	65	(+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	66	add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
<>	144:ef7eb2e8f9f7	67	(+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	68	add his own code by customization of function pointer HAL_USART_TxCpltCallback
<>	144:ef7eb2e8f9f7	69	(+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
<>	144:ef7eb2e8f9f7	70	(+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	71	add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
<>	144:ef7eb2e8f9f7	72	(+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	73	add his own code by customization of function pointer HAL_USART_RxCpltCallback
<>	144:ef7eb2e8f9f7	74	(+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	75	add his own code by customization of function pointer HAL_USART_ErrorCallback
<>	144:ef7eb2e8f9f7	76
<>	144:ef7eb2e8f9f7	77	* DMA mode IO operation *
<>	144:ef7eb2e8f9f7	78	==============================
<>	144:ef7eb2e8f9f7	79	[..]
<>	144:ef7eb2e8f9f7	80	(+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
<>	144:ef7eb2e8f9f7	81	(+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	82	add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
<>	144:ef7eb2e8f9f7	83	(+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	84	add his own code by customization of function pointer HAL_USART_TxCpltCallback
<>	144:ef7eb2e8f9f7	85	(+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
<>	144:ef7eb2e8f9f7	86	(+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	87	add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
<>	144:ef7eb2e8f9f7	88	(+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	89	add his own code by customization of function pointer HAL_USART_RxCpltCallback
<>	144:ef7eb2e8f9f7	90	(+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	91	add his own code by customization of function pointer HAL_USART_ErrorCallback
<>	144:ef7eb2e8f9f7	92	(+) Pause the DMA Transfer using HAL_USART_DMAPause()
<>	144:ef7eb2e8f9f7	93	(+) Resume the DMA Transfer using HAL_USART_DMAResume()
<>	144:ef7eb2e8f9f7	94	(+) Stop the DMA Transfer using HAL_USART_DMAStop()
<>	144:ef7eb2e8f9f7	95
<>	144:ef7eb2e8f9f7	96	* USART HAL driver macros list *
<>	144:ef7eb2e8f9f7	97	=============================================
<>	144:ef7eb2e8f9f7	98	[..]
<>	144:ef7eb2e8f9f7	99	Below the list of most used macros in USART HAL driver.
<>	144:ef7eb2e8f9f7	100
<>	144:ef7eb2e8f9f7	101	(+) __HAL_USART_ENABLE: Enable the USART peripheral
<>	144:ef7eb2e8f9f7	102	(+) __HAL_USART_DISABLE: Disable the USART peripheral
<>	144:ef7eb2e8f9f7	103	(+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
<>	144:ef7eb2e8f9f7	104	(+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
<>	144:ef7eb2e8f9f7	105	(+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
<>	144:ef7eb2e8f9f7	106	(+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
<>	144:ef7eb2e8f9f7	107
<>	144:ef7eb2e8f9f7	108	[..]
<>	144:ef7eb2e8f9f7	109	(@) You can refer to the USART HAL driver header file for more useful macros
<>	157:ff67d9f36b67	110	[..]
<>	157:ff67d9f36b67	111	(@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
<>	157:ff67d9f36b67	112	HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
<>	157:ff67d9f36b67	113	HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
<>	144:ef7eb2e8f9f7	114
<>	144:ef7eb2e8f9f7	115	@endverbatim
<>	144:ef7eb2e8f9f7	116	******************************************************************************
<>	144:ef7eb2e8f9f7	117	* @attention
<>	144:ef7eb2e8f9f7	118	*
<>	144:ef7eb2e8f9f7	119	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	120	*
<>	144:ef7eb2e8f9f7	121	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	122	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	123	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	124	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	125	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	126	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	127	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	128	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	129	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	130	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	131	*
<>	144:ef7eb2e8f9f7	132	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	133	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	134	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	135	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	136	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	137	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	138	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	139	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	140	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	141	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	142	*
<>	144:ef7eb2e8f9f7	143	******************************************************************************
<>	144:ef7eb2e8f9f7	144	*/
<>	144:ef7eb2e8f9f7	145
<>	144:ef7eb2e8f9f7	146	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	147	#include "stm32f3xx_hal.h"
<>	144:ef7eb2e8f9f7	148
<>	144:ef7eb2e8f9f7	149	/** @addtogroup STM32F3xx_HAL_Driver
<>	144:ef7eb2e8f9f7	150	* @{
<>	144:ef7eb2e8f9f7	151	*/
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	/** @defgroup USART USART
<>	144:ef7eb2e8f9f7	154	* @brief USART HAL module driver
<>	144:ef7eb2e8f9f7	155	* @{
<>	144:ef7eb2e8f9f7	156	*/
<>	144:ef7eb2e8f9f7	157
<>	144:ef7eb2e8f9f7	158	#ifdef HAL_USART_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	159
<>	144:ef7eb2e8f9f7	160	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	161	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	162	/** @defgroup USART_Private_Constants USART Private Constants
<>	144:ef7eb2e8f9f7	163	* @{
<>	144:ef7eb2e8f9f7	164	*/
<>	157:ff67d9f36b67	165	#define USART_DUMMY_DATA ((uint16_t) 0xFFFFU) /!< USART transmitted dummy data /
<>	157:ff67d9f36b67	166	#define USART_TEACK_REACK_TIMEOUT ( 1000U) /!< USART TX or RX enable acknowledge time-out value /
<>	144:ef7eb2e8f9f7	167	#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M \| USART_CR1_PCE \| USART_CR1_PS \| \
<>	144:ef7eb2e8f9f7	168	USART_CR1_TE \| USART_CR1_RE \| USART_CR1_OVER8)) /!< USART CR1 fields of parameters set by USART_SetConfig API /
<>	144:ef7eb2e8f9f7	169	#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA \| USART_CR2_CPOL \| \
<>	144:ef7eb2e8f9f7	170	USART_CR2_CLKEN \| USART_CR2_LBCL \| USART_CR2_STOP)) /!< USART CR2 fields of parameters set by USART_SetConfig API /
<>	144:ef7eb2e8f9f7	171	/**
<>	144:ef7eb2e8f9f7	172	* @}
<>	144:ef7eb2e8f9f7	173	*/
<>	144:ef7eb2e8f9f7	174
<>	144:ef7eb2e8f9f7	175	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	176	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	177	/* Private function prototypes -----------------------------------------------*/
<>	157:ff67d9f36b67	178	/** @addtogroup USART_Private_Functions
<>	144:ef7eb2e8f9f7	179	* @{
<>	144:ef7eb2e8f9f7	180	*/
<>	157:ff67d9f36b67	181	static void USART_EndTransfer(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	182	static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	183	static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	184	static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	185	static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	186	static void USART_DMAError(DMA_HandleTypeDef *hdma);
<>	157:ff67d9f36b67	187	static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
<>	157:ff67d9f36b67	188	static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
<>	157:ff67d9f36b67	189	static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
<>	157:ff67d9f36b67	190	static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	191	static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	192	static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	193	static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	194	static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	195	static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	196	static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
<>	144:ef7eb2e8f9f7	197	/**
<>	144:ef7eb2e8f9f7	198	* @}
<>	144:ef7eb2e8f9f7	199	*/
<>	144:ef7eb2e8f9f7	200
<>	144:ef7eb2e8f9f7	201	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	202
<>	144:ef7eb2e8f9f7	203	/** @defgroup USART_Exported_Functions USART Exported Functions
<>	144:ef7eb2e8f9f7	204	* @{
<>	144:ef7eb2e8f9f7	205	*/
<>	144:ef7eb2e8f9f7	206
<>	144:ef7eb2e8f9f7	207	/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	208	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	209	*
<>	144:ef7eb2e8f9f7	210	@verbatim
<>	144:ef7eb2e8f9f7	211	===============================================================================
<>	144:ef7eb2e8f9f7	212	##### Initialization and Configuration functions #####
<>	144:ef7eb2e8f9f7	213	===============================================================================
<>	144:ef7eb2e8f9f7	214	[..]
<>	144:ef7eb2e8f9f7	215	This subsection provides a set of functions allowing to initialize the USART
<>	144:ef7eb2e8f9f7	216	in asynchronous and in synchronous modes.
<>	144:ef7eb2e8f9f7	217	(+) For the asynchronous mode only these parameters can be configured:
<>	144:ef7eb2e8f9f7	218	(++) Baud Rate
<>	144:ef7eb2e8f9f7	219	(++) Word Length
<>	144:ef7eb2e8f9f7	220	(++) Stop Bit
<>	144:ef7eb2e8f9f7	221	(++) Parity
<>	144:ef7eb2e8f9f7	222	(++) USART polarity
<>	144:ef7eb2e8f9f7	223	(++) USART phase
<>	144:ef7eb2e8f9f7	224	(++) USART LastBit
<>	144:ef7eb2e8f9f7	225	(++) Receiver/transmitter modes
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227	[..]
<>	144:ef7eb2e8f9f7	228	The HAL_USART_Init() function follows the USART synchronous configuration
<>	144:ef7eb2e8f9f7	229	procedure (details for the procedure are available in reference manual).
<>	144:ef7eb2e8f9f7	230
<>	144:ef7eb2e8f9f7	231	@endverbatim
<>	144:ef7eb2e8f9f7	232	* @{
<>	144:ef7eb2e8f9f7	233	*/
<>	144:ef7eb2e8f9f7	234
<>	144:ef7eb2e8f9f7	235	/*
<>	144:ef7eb2e8f9f7	236	Additional Table: If the parity is enabled, then the MSB bit of the data written
<>	144:ef7eb2e8f9f7	237	in the data register is transmitted but is changed by the parity bit.
<>	144:ef7eb2e8f9f7	238	According to device capability (support or not of 7-bit word length),
<>	144:ef7eb2e8f9f7	239	frame length is either defined by the M bit (8-bits or 9-bits)
<>	144:ef7eb2e8f9f7	240	or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
<>	144:ef7eb2e8f9f7	241	Possible USART frame formats are as listed in the following table:
<>	144:ef7eb2e8f9f7	242
<>	144:ef7eb2e8f9f7	243	Table 1. USART frame format.
<>	144:ef7eb2e8f9f7	244	+-----------------------------------------------------------------------+
<>	144:ef7eb2e8f9f7	245	\| M bit \| PCE bit \| USART frame \|
<>	144:ef7eb2e8f9f7	246	\|-------------------\|-----------\|---------------------------------------\|
<>	144:ef7eb2e8f9f7	247	\| 0 \| 0 \| \| SB \| 8-bit data \| STB \| \|
<>	144:ef7eb2e8f9f7	248	\|-------------------\|-----------\|---------------------------------------\|
<>	144:ef7eb2e8f9f7	249	\| 0 \| 1 \| \| SB \| 7-bit data \| PB \| STB \| \|
<>	144:ef7eb2e8f9f7	250	\|-------------------\|-----------\|---------------------------------------\|
<>	144:ef7eb2e8f9f7	251	\| 1 \| 0 \| \| SB \| 9-bit data \| STB \| \|
<>	144:ef7eb2e8f9f7	252	\|-------------------\|-----------\|---------------------------------------\|
<>	144:ef7eb2e8f9f7	253	\| 1 \| 1 \| \| SB \| 8-bit data \| PB \| STB \| \|
<>	144:ef7eb2e8f9f7	254	+-----------------------------------------------------------------------+
<>	144:ef7eb2e8f9f7	255	\| M1 bit \| M0 bit \| PCE bit \| USART frame \|
<>	144:ef7eb2e8f9f7	256	\|---------\|---------\|-----------\|---------------------------------------\|
<>	144:ef7eb2e8f9f7	257	\| 0 \| 0 \| 0 \| \| SB \| 8 bit data \| STB \| \|
<>	144:ef7eb2e8f9f7	258	\|---------\|---------\|-----------\|---------------------------------------\|
<>	144:ef7eb2e8f9f7	259	\| 0 \| 0 \| 1 \| \| SB \| 7 bit data \| PB \| STB \| \|
<>	144:ef7eb2e8f9f7	260	\|---------\|---------\|-----------\|---------------------------------------\|
<>	144:ef7eb2e8f9f7	261	\| 0 \| 1 \| 0 \| \| SB \| 9 bit data \| STB \| \|
<>	144:ef7eb2e8f9f7	262	\|---------\|---------\|-----------\|---------------------------------------\|
<>	144:ef7eb2e8f9f7	263	\| 0 \| 1 \| 1 \| \| SB \| 8 bit data \| PB \| STB \| \|
<>	144:ef7eb2e8f9f7	264	\|---------\|---------\|-----------\|---------------------------------------\|
<>	144:ef7eb2e8f9f7	265	\| 1 \| 0 \| 0 \| \| SB \| 7 bit data \| STB \| \|
<>	144:ef7eb2e8f9f7	266	\|---------\|---------\|-----------\|---------------------------------------\|
<>	144:ef7eb2e8f9f7	267	\| 1 \| 0 \| 1 \| \| SB \| 6 bit data \| PB \| STB \| \|
<>	144:ef7eb2e8f9f7	268	+-----------------------------------------------------------------------+
<>	144:ef7eb2e8f9f7	269
<>	144:ef7eb2e8f9f7	270	*/
<>	144:ef7eb2e8f9f7	271
<>	144:ef7eb2e8f9f7	272	/**
<>	157:ff67d9f36b67	273	* @brief Initialize the USART mode according to the specified
<>	144:ef7eb2e8f9f7	274	* parameters in the USART_InitTypeDef and initialize the associated handle.
<>	157:ff67d9f36b67	275	* @param husart USART handle.
<>	144:ef7eb2e8f9f7	276	* @retval HAL status
<>	144:ef7eb2e8f9f7	277	*/
<>	144:ef7eb2e8f9f7	278	HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	279	{
<>	144:ef7eb2e8f9f7	280	/* Check the USART handle allocation */
<>	144:ef7eb2e8f9f7	281	if(husart == NULL)
<>	144:ef7eb2e8f9f7	282	{
<>	144:ef7eb2e8f9f7	283	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	284	}
<>	144:ef7eb2e8f9f7	285
<>	144:ef7eb2e8f9f7	286	/* Check the parameters */
<>	144:ef7eb2e8f9f7	287	assert_param(IS_USART_INSTANCE(husart->Instance));
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	if(husart->State == HAL_USART_STATE_RESET)
<>	144:ef7eb2e8f9f7	290	{
<>	144:ef7eb2e8f9f7	291	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	292	husart->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	293
<>	144:ef7eb2e8f9f7	294	/* Init the low level hardware : GPIO, CLOCK */
<>	144:ef7eb2e8f9f7	295	HAL_USART_MspInit(husart);
<>	144:ef7eb2e8f9f7	296	}
<>	144:ef7eb2e8f9f7	297
<>	144:ef7eb2e8f9f7	298	husart->State = HAL_USART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	299
<>	144:ef7eb2e8f9f7	300	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	301	__HAL_USART_DISABLE(husart);
<>	144:ef7eb2e8f9f7	302
<>	144:ef7eb2e8f9f7	303	/* Set the Usart Communication parameters */
<>	144:ef7eb2e8f9f7	304	if (USART_SetConfig(husart) == HAL_ERROR)
<>	144:ef7eb2e8f9f7	305	{
<>	144:ef7eb2e8f9f7	306	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	307	}
<>	144:ef7eb2e8f9f7	308
<>	144:ef7eb2e8f9f7	309	/* In Synchronous mode, the following bits must be kept cleared:
<>	144:ef7eb2e8f9f7	310	- LINEN bit in the USART_CR2 register
<>	144:ef7eb2e8f9f7	311	- HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
<>	144:ef7eb2e8f9f7	312	husart->Instance->CR2 &= ~USART_CR2_LINEN;
<>	144:ef7eb2e8f9f7	313	husart->Instance->CR3 &= ~(USART_CR3_SCEN \| USART_CR3_HDSEL \| USART_CR3_IREN);
<>	144:ef7eb2e8f9f7	314
<>	144:ef7eb2e8f9f7	315	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	316	__HAL_USART_ENABLE(husart);
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	/* TEACK and/or REACK to check before moving husart->State to Ready */
<>	144:ef7eb2e8f9f7	319	return (USART_CheckIdleState(husart));
<>	144:ef7eb2e8f9f7	320	}
<>	144:ef7eb2e8f9f7	321
<>	144:ef7eb2e8f9f7	322	/**
<>	144:ef7eb2e8f9f7	323	* @brief DeInitialize the USART peripheral.
<>	157:ff67d9f36b67	324	* @param husart USART handle.
<>	144:ef7eb2e8f9f7	325	* @retval HAL status
<>	144:ef7eb2e8f9f7	326	*/
<>	144:ef7eb2e8f9f7	327	HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	328	{
<>	157:ff67d9f36b67	329	/* Check the USART handle allocation */
<>	144:ef7eb2e8f9f7	330	if(husart == NULL)
<>	144:ef7eb2e8f9f7	331	{
<>	144:ef7eb2e8f9f7	332	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	333	}
<>	144:ef7eb2e8f9f7	334
<>	144:ef7eb2e8f9f7	335	/* Check the parameters */
<>	144:ef7eb2e8f9f7	336	assert_param(IS_USART_INSTANCE(husart->Instance));
<>	144:ef7eb2e8f9f7	337
<>	144:ef7eb2e8f9f7	338	husart->State = HAL_USART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	339
<>	157:ff67d9f36b67	340	husart->Instance->CR1 = 0x0U;
<>	157:ff67d9f36b67	341	husart->Instance->CR2 = 0x0U;
<>	157:ff67d9f36b67	342	husart->Instance->CR3 = 0x0U;
<>	144:ef7eb2e8f9f7	343
<>	144:ef7eb2e8f9f7	344	/* DeInit the low level hardware */
<>	144:ef7eb2e8f9f7	345	HAL_USART_MspDeInit(husart);
<>	144:ef7eb2e8f9f7	346
<>	144:ef7eb2e8f9f7	347	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	348	husart->State = HAL_USART_STATE_RESET;
<>	144:ef7eb2e8f9f7	349
<>	144:ef7eb2e8f9f7	350	/* Process Unlock */
<>	144:ef7eb2e8f9f7	351	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	352
<>	144:ef7eb2e8f9f7	353	return HAL_OK;
<>	144:ef7eb2e8f9f7	354	}
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356	/**
<>	144:ef7eb2e8f9f7	357	* @brief Initialize the USART MSP.
<>	144:ef7eb2e8f9f7	358	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	359	* @retval None
<>	144:ef7eb2e8f9f7	360	*/
<>	157:ff67d9f36b67	361	__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	362	{
<>	144:ef7eb2e8f9f7	363	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	364	UNUSED(husart);
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	367	the HAL_USART_MspInit can be implemented in the user file
<>	144:ef7eb2e8f9f7	368	*/
<>	144:ef7eb2e8f9f7	369	}
<>	144:ef7eb2e8f9f7	370
<>	144:ef7eb2e8f9f7	371	/**
<>	144:ef7eb2e8f9f7	372	* @brief DeInitialize the USART MSP.
<>	144:ef7eb2e8f9f7	373	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	374	* @retval None
<>	144:ef7eb2e8f9f7	375	*/
<>	157:ff67d9f36b67	376	__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	377	{
<>	144:ef7eb2e8f9f7	378	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	379	UNUSED(husart);
<>	144:ef7eb2e8f9f7	380
<>	144:ef7eb2e8f9f7	381	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	382	the HAL_USART_MspDeInit can be implemented in the user file
<>	144:ef7eb2e8f9f7	383	*/
<>	144:ef7eb2e8f9f7	384	}
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	/**
<>	144:ef7eb2e8f9f7	387	* @}
<>	144:ef7eb2e8f9f7	388	*/
<>	144:ef7eb2e8f9f7	389
<>	144:ef7eb2e8f9f7	390	/** @defgroup USART_Exported_Functions_Group2 IO operation functions
<>	157:ff67d9f36b67	391	* @brief USART Transmit and Receive functions
<>	144:ef7eb2e8f9f7	392	*
<>	144:ef7eb2e8f9f7	393	@verbatim
<>	144:ef7eb2e8f9f7	394	===============================================================================
<>	144:ef7eb2e8f9f7	395	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	396	===============================================================================
<>	144:ef7eb2e8f9f7	397	[..] This subsection provides a set of functions allowing to manage the USART synchronous
<>	144:ef7eb2e8f9f7	398	data transfers.
<>	144:ef7eb2e8f9f7	399
<>	144:ef7eb2e8f9f7	400	[..] The USART supports master mode only: it cannot receive or send data related to an input
<>	144:ef7eb2e8f9f7	401	clock (SCLK is always an output).
<>	144:ef7eb2e8f9f7	402
<>	144:ef7eb2e8f9f7	403	(#) There are two modes of transfer:
<>	144:ef7eb2e8f9f7	404	(++) Blocking mode: The communication is performed in polling mode.
<>	144:ef7eb2e8f9f7	405	The HAL status of all data processing is returned by the same function
<>	144:ef7eb2e8f9f7	406	after finishing transfer.
<>	144:ef7eb2e8f9f7	407	(++) No-Blocking mode: The communication is performed using Interrupts
<>	144:ef7eb2e8f9f7	408	or DMA, These APIs return the HAL status.
<>	144:ef7eb2e8f9f7	409	The end of the data processing will be indicated through the
<>	144:ef7eb2e8f9f7	410	dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
<>	144:ef7eb2e8f9f7	411	using DMA mode.
<>	144:ef7eb2e8f9f7	412	The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
<>	144:ef7eb2e8f9f7	413	will be executed respectively at the end of the transmit or Receive process
<>	144:ef7eb2e8f9f7	414	The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	(#) Blocking mode APIs are :
<>	157:ff67d9f36b67	417	(++) HAL_USART_Transmit() in simplex mode
<>	144:ef7eb2e8f9f7	418	(++) HAL_USART_Receive() in full duplex receive only
<>	144:ef7eb2e8f9f7	419	(++) HAL_USART_TransmitReceive() in full duplex mode
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	(#) No-Blocking mode APIs with Interrupt are :
<>	157:ff67d9f36b67	422	(++) HAL_USART_Transmit_IT() in simplex mode
<>	144:ef7eb2e8f9f7	423	(++) HAL_USART_Receive_IT() in full duplex receive only
<>	144:ef7eb2e8f9f7	424	(++) HAL_USART_TransmitReceive_IT()in full duplex mode
<>	144:ef7eb2e8f9f7	425	(++) HAL_USART_IRQHandler()
<>	144:ef7eb2e8f9f7	426
<>	144:ef7eb2e8f9f7	427	(#) No-Blocking mode APIs with DMA are :
<>	157:ff67d9f36b67	428	(++) HAL_USART_Transmit_DMA() in simplex mode
<>	144:ef7eb2e8f9f7	429	(++) HAL_USART_Receive_DMA() in full duplex receive only
<>	144:ef7eb2e8f9f7	430	(++) HAL_USART_TransmitReceive_DMA() in full duplex mode
<>	144:ef7eb2e8f9f7	431	(++) HAL_USART_DMAPause()
<>	144:ef7eb2e8f9f7	432	(++) HAL_USART_DMAResume()
<>	144:ef7eb2e8f9f7	433	(++) HAL_USART_DMAStop()
<>	144:ef7eb2e8f9f7	434
<>	144:ef7eb2e8f9f7	435	(#) A set of Transfer Complete Callbacks are provided in No-Blocking mode:
<>	144:ef7eb2e8f9f7	436	(++) HAL_USART_TxCpltCallback()
<>	144:ef7eb2e8f9f7	437	(++) HAL_USART_RxCpltCallback()
<>	144:ef7eb2e8f9f7	438	(++) HAL_USART_TxHalfCpltCallback()
<>	144:ef7eb2e8f9f7	439	(++) HAL_USART_RxHalfCpltCallback()
<>	144:ef7eb2e8f9f7	440	(++) HAL_USART_ErrorCallback()
<>	144:ef7eb2e8f9f7	441	(++) HAL_USART_TxRxCpltCallback()
<>	144:ef7eb2e8f9f7	442
<>	157:ff67d9f36b67	443	(#) Non-Blocking mode transfers could be aborted using Abort API's :
<>	157:ff67d9f36b67	444	(++) HAL_USART_Abort()
<>	157:ff67d9f36b67	445	(++) HAL_USART_Abort_IT()
<>	157:ff67d9f36b67	446
<>	157:ff67d9f36b67	447	(#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
<>	157:ff67d9f36b67	448	(++) HAL_USART_AbortCpltCallback()
<>	157:ff67d9f36b67	449
<>	157:ff67d9f36b67	450	(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
<>	157:ff67d9f36b67	451	Errors are handled as follows :
<>	157:ff67d9f36b67	452	(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
<>	157:ff67d9f36b67	453	to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
<>	157:ff67d9f36b67	454	Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
<>	157:ff67d9f36b67	455	and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
<>	157:ff67d9f36b67	456	If user wants to abort it, Abort services should be called by user.
<>	157:ff67d9f36b67	457	(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
<>	157:ff67d9f36b67	458	This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
<>	157:ff67d9f36b67	459	Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
<>	157:ff67d9f36b67	460
<>	144:ef7eb2e8f9f7	461	@endverbatim
<>	144:ef7eb2e8f9f7	462	* @{
<>	144:ef7eb2e8f9f7	463	*/
<>	144:ef7eb2e8f9f7	464
<>	144:ef7eb2e8f9f7	465	/**
<>	144:ef7eb2e8f9f7	466	* @brief Simplex send an amount of data in blocking mode.
<>	157:ff67d9f36b67	467	* @param husart USART handle.
<>	157:ff67d9f36b67	468	* @param pTxData Pointer to data buffer.
<>	157:ff67d9f36b67	469	* @param Size Amount of data to be sent.
<>	157:ff67d9f36b67	470	* @param Timeout Timeout duration.
<>	144:ef7eb2e8f9f7	471	* @retval HAL status
<>	144:ef7eb2e8f9f7	472	*/
<>	144:ef7eb2e8f9f7	473	HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef husart, uint8_t pTxData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	474	{
<>	157:ff67d9f36b67	475	uint16_t* tmp=0U;
<>	157:ff67d9f36b67	476	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	477
<>	144:ef7eb2e8f9f7	478	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	479	{
<>	157:ff67d9f36b67	480	if((pTxData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	481	{
<>	144:ef7eb2e8f9f7	482	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	483	}
<>	144:ef7eb2e8f9f7	484
<>	144:ef7eb2e8f9f7	485	/* Process Locked */
<>	144:ef7eb2e8f9f7	486	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	487
<>	144:ef7eb2e8f9f7	488	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	489	husart->State = HAL_USART_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	490
<>	157:ff67d9f36b67	491	/* Init tickstart for timeout managment*/
<>	157:ff67d9f36b67	492	tickstart = HAL_GetTick();
<>	157:ff67d9f36b67	493
<>	144:ef7eb2e8f9f7	494	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	495	husart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	496
<>	144:ef7eb2e8f9f7	497	/* Check the remaining data to be sent */
<>	157:ff67d9f36b67	498	while(husart->TxXferCount > 0U)
<>	144:ef7eb2e8f9f7	499	{
<>	144:ef7eb2e8f9f7	500	husart->TxXferCount--;
<>	157:ff67d9f36b67	501	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	502	{
<>	144:ef7eb2e8f9f7	503	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	504	}
<>	144:ef7eb2e8f9f7	505	if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<>	144:ef7eb2e8f9f7	506	{
<>	144:ef7eb2e8f9f7	507	tmp = (uint16_t*) pTxData;
<>	157:ff67d9f36b67	508	husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<>	157:ff67d9f36b67	509	pTxData += 2U;
<>	144:ef7eb2e8f9f7	510	}
<>	144:ef7eb2e8f9f7	511	else
<>	144:ef7eb2e8f9f7	512	{
<>	157:ff67d9f36b67	513	husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);
<>	144:ef7eb2e8f9f7	514	}
<>	144:ef7eb2e8f9f7	515	}
<>	144:ef7eb2e8f9f7	516
<>	157:ff67d9f36b67	517	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	518	{
<>	144:ef7eb2e8f9f7	519	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	520	}
<>	144:ef7eb2e8f9f7	521
<>	157:ff67d9f36b67	522	/* At end of Tx process, restore husart->State to Ready */
<>	144:ef7eb2e8f9f7	523	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	524
<>	144:ef7eb2e8f9f7	525	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	526	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	527
<>	144:ef7eb2e8f9f7	528	return HAL_OK;
<>	144:ef7eb2e8f9f7	529	}
<>	144:ef7eb2e8f9f7	530	else
<>	144:ef7eb2e8f9f7	531	{
<>	144:ef7eb2e8f9f7	532	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	533	}
<>	144:ef7eb2e8f9f7	534	}
<>	144:ef7eb2e8f9f7	535
<>	144:ef7eb2e8f9f7	536	/**
<>	144:ef7eb2e8f9f7	537	* @brief Receive an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	538	* @note To receive synchronous data, dummy data are simultaneously transmitted.
<>	157:ff67d9f36b67	539	* @param husart USART handle.
<>	157:ff67d9f36b67	540	* @param pRxData Pointer to data buffer.
<>	157:ff67d9f36b67	541	* @param Size Amount of data to be received.
<>	157:ff67d9f36b67	542	* @param Timeout Timeout duration.
<>	144:ef7eb2e8f9f7	543	* @retval HAL status
<>	144:ef7eb2e8f9f7	544	*/
<>	144:ef7eb2e8f9f7	545	HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef husart, uint8_t pRxData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	546	{
<>	157:ff67d9f36b67	547	uint16_t* tmp=0U;
<>	144:ef7eb2e8f9f7	548	uint16_t uhMask;
<>	157:ff67d9f36b67	549	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	552	{
<>	157:ff67d9f36b67	553	if((pRxData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	554	{
<>	144:ef7eb2e8f9f7	555	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	556	}
<>	157:ff67d9f36b67	557
<>	144:ef7eb2e8f9f7	558	/* Process Locked */
<>	144:ef7eb2e8f9f7	559	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	560
<>	144:ef7eb2e8f9f7	561	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	562	husart->State = HAL_USART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	563
<>	157:ff67d9f36b67	564	/* Init tickstart for timeout managment*/
<>	157:ff67d9f36b67	565	tickstart = HAL_GetTick();
<>	157:ff67d9f36b67	566
<>	144:ef7eb2e8f9f7	567	husart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	568	husart->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	569
<>	144:ef7eb2e8f9f7	570	/* Computation of USART mask to apply to RDR register */
<>	144:ef7eb2e8f9f7	571	USART_MASK_COMPUTATION(husart);
<>	144:ef7eb2e8f9f7	572	uhMask = husart->Mask;
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	/* as long as data have to be received */
<>	157:ff67d9f36b67	575	while(husart->RxXferCount > 0U)
<>	144:ef7eb2e8f9f7	576	{
<>	144:ef7eb2e8f9f7	577	husart->RxXferCount--;
<>	144:ef7eb2e8f9f7	578
<>	144:ef7eb2e8f9f7	579	/* Wait until TC flag is set to send dummy byte in order to generate the
<>	144:ef7eb2e8f9f7	580	* clock for the slave to send data.
<>	144:ef7eb2e8f9f7	581	* Whatever the frame length (7, 8 or 9-bit long), the same dummy value
<>	144:ef7eb2e8f9f7	582	* can be written for all the cases. */
<>	157:ff67d9f36b67	583	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	584	{
<>	144:ef7eb2e8f9f7	585	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	586	}
<>	157:ff67d9f36b67	587	husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FFU);
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	/* Wait for RXNE Flag */
<>	157:ff67d9f36b67	590	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	591	{
<>	144:ef7eb2e8f9f7	592	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	593	}
<>	144:ef7eb2e8f9f7	594
<>	144:ef7eb2e8f9f7	595	if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<>	144:ef7eb2e8f9f7	596	{
<>	144:ef7eb2e8f9f7	597	tmp = (uint16_t*) pRxData ;
<>	144:ef7eb2e8f9f7	598	*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
<>	157:ff67d9f36b67	599	pRxData +=2U;
<>	144:ef7eb2e8f9f7	600	}
<>	144:ef7eb2e8f9f7	601	else
<>	144:ef7eb2e8f9f7	602	{
<>	144:ef7eb2e8f9f7	603	*pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
<>	144:ef7eb2e8f9f7	604	}
<>	144:ef7eb2e8f9f7	605	}
<>	144:ef7eb2e8f9f7	606
<>	157:ff67d9f36b67	607	/* At end of Rx process, restore husart->State to Ready */
<>	144:ef7eb2e8f9f7	608	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	609
<>	144:ef7eb2e8f9f7	610	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	611	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	612
<>	144:ef7eb2e8f9f7	613	return HAL_OK;
<>	144:ef7eb2e8f9f7	614	}
<>	144:ef7eb2e8f9f7	615	else
<>	144:ef7eb2e8f9f7	616	{
<>	144:ef7eb2e8f9f7	617	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	618	}
<>	144:ef7eb2e8f9f7	619	}
<>	144:ef7eb2e8f9f7	620
<>	144:ef7eb2e8f9f7	621	/**
<>	144:ef7eb2e8f9f7	622	* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
<>	157:ff67d9f36b67	623	* @param husart USART handle.
<>	157:ff67d9f36b67	624	* @param pTxData pointer to TX data buffer.
<>	157:ff67d9f36b67	625	* @param pRxData pointer to RX data buffer.
<>	157:ff67d9f36b67	626	* @param Size amount of data to be sent (same amount to be received).
<>	157:ff67d9f36b67	627	* @param Timeout Timeout duration.
<>	144:ef7eb2e8f9f7	628	* @retval HAL status
<>	144:ef7eb2e8f9f7	629	*/
<>	144:ef7eb2e8f9f7	630	HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef husart, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	631	{
<>	157:ff67d9f36b67	632	uint16_t* tmp=0U;
<>	144:ef7eb2e8f9f7	633	uint16_t uhMask;
<>	157:ff67d9f36b67	634	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	635
<>	144:ef7eb2e8f9f7	636	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	637	{
<>	157:ff67d9f36b67	638	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	639	{
<>	144:ef7eb2e8f9f7	640	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	641	}
<>	157:ff67d9f36b67	642
<>	144:ef7eb2e8f9f7	643	/* Process Locked */
<>	144:ef7eb2e8f9f7	644	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	645
<>	144:ef7eb2e8f9f7	646	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	647	husart->State = HAL_USART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	648
<>	157:ff67d9f36b67	649	/* Init tickstart for timeout managment*/
<>	157:ff67d9f36b67	650	tickstart = HAL_GetTick();
<>	157:ff67d9f36b67	651
<>	144:ef7eb2e8f9f7	652	husart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	653	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	654	husart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	655	husart->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	656
<>	144:ef7eb2e8f9f7	657	/* Computation of USART mask to apply to RDR register */
<>	144:ef7eb2e8f9f7	658	USART_MASK_COMPUTATION(husart);
<>	144:ef7eb2e8f9f7	659	uhMask = husart->Mask;
<>	144:ef7eb2e8f9f7	660
<>	144:ef7eb2e8f9f7	661	/* Check the remain data to be sent */
<>	157:ff67d9f36b67	662	while(husart->TxXferCount > 0U)
<>	144:ef7eb2e8f9f7	663	{
<>	144:ef7eb2e8f9f7	664	husart->TxXferCount--;
<>	144:ef7eb2e8f9f7	665	husart->RxXferCount--;
<>	144:ef7eb2e8f9f7	666
<>	144:ef7eb2e8f9f7	667	/* Wait until TC flag is set to send data */
<>	157:ff67d9f36b67	668	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	669	{
<>	144:ef7eb2e8f9f7	670	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	671	}
<>	144:ef7eb2e8f9f7	672	if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<>	144:ef7eb2e8f9f7	673	{
<>	144:ef7eb2e8f9f7	674	tmp = (uint16_t*) pTxData;
<>	144:ef7eb2e8f9f7	675	husart->Instance->TDR = (*tmp & uhMask);
<>	157:ff67d9f36b67	676	pTxData += 2U;
<>	144:ef7eb2e8f9f7	677	}
<>	144:ef7eb2e8f9f7	678	else
<>	144:ef7eb2e8f9f7	679	{
<>	144:ef7eb2e8f9f7	680	husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
<>	144:ef7eb2e8f9f7	681	}
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	/* Wait for RXNE Flag */
<>	157:ff67d9f36b67	684	if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	685	{
<>	144:ef7eb2e8f9f7	686	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	687	}
<>	144:ef7eb2e8f9f7	688
<>	144:ef7eb2e8f9f7	689	if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<>	144:ef7eb2e8f9f7	690	{
<>	144:ef7eb2e8f9f7	691	tmp = (uint16_t*) pRxData ;
<>	144:ef7eb2e8f9f7	692	*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
<>	157:ff67d9f36b67	693	pRxData +=2U;
<>	144:ef7eb2e8f9f7	694	}
<>	144:ef7eb2e8f9f7	695	else
<>	144:ef7eb2e8f9f7	696	{
<>	144:ef7eb2e8f9f7	697	*pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
<>	144:ef7eb2e8f9f7	698	}
<>	144:ef7eb2e8f9f7	699	}
<>	144:ef7eb2e8f9f7	700
<>	157:ff67d9f36b67	701	/* At end of TxRx process, restore husart->State to Ready */
<>	144:ef7eb2e8f9f7	702	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	703
<>	144:ef7eb2e8f9f7	704	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	705	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	706
<>	144:ef7eb2e8f9f7	707	return HAL_OK;
<>	144:ef7eb2e8f9f7	708	}
<>	144:ef7eb2e8f9f7	709	else
<>	144:ef7eb2e8f9f7	710	{
<>	144:ef7eb2e8f9f7	711	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	712	}
<>	144:ef7eb2e8f9f7	713	}
<>	144:ef7eb2e8f9f7	714
<>	144:ef7eb2e8f9f7	715	/**
<>	144:ef7eb2e8f9f7	716	* @brief Send an amount of data in interrupt mode.
<>	157:ff67d9f36b67	717	* @param husart USART handle.
<>	157:ff67d9f36b67	718	* @param pTxData pointer to data buffer.
<>	157:ff67d9f36b67	719	* @param Size amount of data to be sent.
<>	144:ef7eb2e8f9f7	720	* @retval HAL status
<>	144:ef7eb2e8f9f7	721	*/
<>	144:ef7eb2e8f9f7	722	HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef husart, uint8_t pTxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	723	{
<>	144:ef7eb2e8f9f7	724	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	725	{
<>	157:ff67d9f36b67	726	if((pTxData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	727	{
<>	144:ef7eb2e8f9f7	728	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	729	}
<>	144:ef7eb2e8f9f7	730
<>	144:ef7eb2e8f9f7	731	/* Process Locked */
<>	144:ef7eb2e8f9f7	732	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	733
<>	144:ef7eb2e8f9f7	734	husart->pTxBuffPtr = pTxData;
<>	144:ef7eb2e8f9f7	735	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	736	husart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	737
<>	144:ef7eb2e8f9f7	738	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	739	husart->State = HAL_USART_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	/* The USART Error Interrupts: (Frame error, noise error, overrun error)
<>	144:ef7eb2e8f9f7	742	are not managed by the USART Transmit Process to avoid the overrun interrupt
<>	144:ef7eb2e8f9f7	743	when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
<>	144:ef7eb2e8f9f7	744	to benefit for the frame error and noise interrupts the usart mode should be
<>	144:ef7eb2e8f9f7	745	configured only for transmit "USART_MODE_TX" */
<>	144:ef7eb2e8f9f7	746
<>	144:ef7eb2e8f9f7	747	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	748	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	/* Enable the USART Transmit Data Register Empty Interrupt */
<>	144:ef7eb2e8f9f7	751	__HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
<>	144:ef7eb2e8f9f7	752
<>	144:ef7eb2e8f9f7	753	return HAL_OK;
<>	144:ef7eb2e8f9f7	754	}
<>	144:ef7eb2e8f9f7	755	else
<>	144:ef7eb2e8f9f7	756	{
<>	144:ef7eb2e8f9f7	757	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	758	}
<>	144:ef7eb2e8f9f7	759	}
<>	144:ef7eb2e8f9f7	760
<>	144:ef7eb2e8f9f7	761	/**
<>	157:ff67d9f36b67	762	* @brief Receive an amount of data in interrupt mode.
<>	144:ef7eb2e8f9f7	763	* @note To receive synchronous data, dummy data are simultaneously transmitted.
<>	157:ff67d9f36b67	764	* @param husart USART handle.
<>	157:ff67d9f36b67	765	* @param pRxData pointer to data buffer.
<>	157:ff67d9f36b67	766	* @param Size amount of data to be received.
<>	144:ef7eb2e8f9f7	767	* @retval HAL status
<>	144:ef7eb2e8f9f7	768	*/
<>	144:ef7eb2e8f9f7	769	HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef husart, uint8_t pRxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	770	{
<>	144:ef7eb2e8f9f7	771	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	772	{
<>	157:ff67d9f36b67	773	if((pRxData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	774	{
<>	144:ef7eb2e8f9f7	775	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	776	}
<>	157:ff67d9f36b67	777
<>	144:ef7eb2e8f9f7	778	/* Process Locked */
<>	144:ef7eb2e8f9f7	779	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	780
<>	144:ef7eb2e8f9f7	781	husart->pRxBuffPtr = pRxData;
<>	144:ef7eb2e8f9f7	782	husart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	783	husart->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	784
<>	144:ef7eb2e8f9f7	785	USART_MASK_COMPUTATION(husart);
<>	144:ef7eb2e8f9f7	786
<>	144:ef7eb2e8f9f7	787	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	788	husart->State = HAL_USART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	789
<>	144:ef7eb2e8f9f7	790	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	791	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	792
<>	157:ff67d9f36b67	793	/* Enable the USART Parity Error and Data Register not empty Interrupts */
<>	157:ff67d9f36b67	794	SET_BIT(husart->Instance->CR1, USART_CR1_PEIE \| USART_CR1_RXNEIE);
<>	157:ff67d9f36b67	795
<>	157:ff67d9f36b67	796	/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	157:ff67d9f36b67	797	SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	/* Send dummy byte in order to generate the clock for the Slave to send the next data */
<>	144:ef7eb2e8f9f7	800	if(husart->Init.WordLength == USART_WORDLENGTH_9B)
<>	144:ef7eb2e8f9f7	801	{
<>	157:ff67d9f36b67	802	husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FFU);
<>	144:ef7eb2e8f9f7	803	}
<>	144:ef7eb2e8f9f7	804	else
<>	144:ef7eb2e8f9f7	805	{
<>	157:ff67d9f36b67	806	husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
<>	144:ef7eb2e8f9f7	807	}
<>	144:ef7eb2e8f9f7	808
<>	144:ef7eb2e8f9f7	809	return HAL_OK;
<>	144:ef7eb2e8f9f7	810	}
<>	144:ef7eb2e8f9f7	811	else
<>	144:ef7eb2e8f9f7	812	{
<>	144:ef7eb2e8f9f7	813	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	814	}
<>	144:ef7eb2e8f9f7	815	}
<>	144:ef7eb2e8f9f7	816
<>	144:ef7eb2e8f9f7	817	/**
<>	144:ef7eb2e8f9f7	818	* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
<>	157:ff67d9f36b67	819	* @param husart USART handle.
<>	157:ff67d9f36b67	820	* @param pTxData pointer to TX data buffer.
<>	157:ff67d9f36b67	821	* @param pRxData pointer to RX data buffer.
<>	157:ff67d9f36b67	822	* @param Size amount of data to be sent (same amount to be received).
<>	144:ef7eb2e8f9f7	823	* @retval HAL status
<>	144:ef7eb2e8f9f7	824	*/
<>	144:ef7eb2e8f9f7	825	HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef husart, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	826	{
<>	144:ef7eb2e8f9f7	827
<>	144:ef7eb2e8f9f7	828	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	829	{
<>	157:ff67d9f36b67	830	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	831	{
<>	144:ef7eb2e8f9f7	832	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	833	}
<>	157:ff67d9f36b67	834
<>	144:ef7eb2e8f9f7	835	/* Process Locked */
<>	144:ef7eb2e8f9f7	836	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	837
<>	144:ef7eb2e8f9f7	838	husart->pRxBuffPtr = pRxData;
<>	144:ef7eb2e8f9f7	839	husart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	840	husart->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	841	husart->pTxBuffPtr = pTxData;
<>	144:ef7eb2e8f9f7	842	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	843	husart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	844
<>	144:ef7eb2e8f9f7	845	/* Computation of USART mask to apply to RDR register */
<>	144:ef7eb2e8f9f7	846	USART_MASK_COMPUTATION(husart);
<>	144:ef7eb2e8f9f7	847
<>	144:ef7eb2e8f9f7	848	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	849	husart->State = HAL_USART_STATE_BUSY_TX_RX;
<>	144:ef7eb2e8f9f7	850
<>	144:ef7eb2e8f9f7	851	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	852	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	853
<>	157:ff67d9f36b67	854	/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	157:ff67d9f36b67	855	SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	856
<>	157:ff67d9f36b67	857	/* Enable the USART Parity Error and USART Data Register not empty Interrupts */
<>	157:ff67d9f36b67	858	SET_BIT(husart->Instance->CR1, USART_CR1_PEIE \| USART_CR1_RXNEIE);
<>	157:ff67d9f36b67	859
<>	144:ef7eb2e8f9f7	860	/* Enable the USART Transmit Data Register Empty Interrupt */
<>	157:ff67d9f36b67	861	SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
<>	144:ef7eb2e8f9f7	862
<>	144:ef7eb2e8f9f7	863	return HAL_OK;
<>	144:ef7eb2e8f9f7	864	}
<>	144:ef7eb2e8f9f7	865	else
<>	144:ef7eb2e8f9f7	866	{
<>	144:ef7eb2e8f9f7	867	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	868	}
<>	144:ef7eb2e8f9f7	869	}
<>	144:ef7eb2e8f9f7	870
<>	144:ef7eb2e8f9f7	871	/**
<>	144:ef7eb2e8f9f7	872	* @brief Send an amount of data in DMA mode.
<>	157:ff67d9f36b67	873	* @param husart USART handle.
<>	157:ff67d9f36b67	874	* @param pTxData pointer to data buffer.
<>	157:ff67d9f36b67	875	* @param Size amount of data to be sent.
<>	157:ff67d9f36b67	876	* @note This function starts a DMA transfer in interrupt mode meaning that
<>	144:ef7eb2e8f9f7	877	* DMA half transfer complete, DMA transfer complete and DMA transfer
<>	144:ef7eb2e8f9f7	878	* error interrupts are enabled
<>	144:ef7eb2e8f9f7	879	* @retval HAL status
<>	144:ef7eb2e8f9f7	880	*/
<>	144:ef7eb2e8f9f7	881	HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef husart, uint8_t pTxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	882	{
<>	157:ff67d9f36b67	883	uint32_t *tmp=0U;
<>	144:ef7eb2e8f9f7	884
<>	144:ef7eb2e8f9f7	885	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	886	{
<>	157:ff67d9f36b67	887	if((pTxData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	888	{
<>	144:ef7eb2e8f9f7	889	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	890	}
<>	157:ff67d9f36b67	891
<>	144:ef7eb2e8f9f7	892	/* Process Locked */
<>	144:ef7eb2e8f9f7	893	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	894
<>	144:ef7eb2e8f9f7	895	husart->pTxBuffPtr = pTxData;
<>	144:ef7eb2e8f9f7	896	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	897	husart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	898
<>	144:ef7eb2e8f9f7	899	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	900	husart->State = HAL_USART_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	901
<>	144:ef7eb2e8f9f7	902	/* Set the USART DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	903	husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
<>	144:ef7eb2e8f9f7	904
<>	144:ef7eb2e8f9f7	905	/* Set the USART DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	906	husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
<>	144:ef7eb2e8f9f7	907
<>	144:ef7eb2e8f9f7	908	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	909	husart->hdmatx->XferErrorCallback = USART_DMAError;
<>	144:ef7eb2e8f9f7	910
<>	144:ef7eb2e8f9f7	911	/* Enable the USART transmit DMA channel */
<>	144:ef7eb2e8f9f7	912	tmp = (uint32_t*)&pTxData;
<>	144:ef7eb2e8f9f7	913	HAL_DMA_Start_IT(husart->hdmatx, (uint32_t)tmp, (uint32_t)&husart->Instance->TDR, Size);
<>	144:ef7eb2e8f9f7	914
<>	144:ef7eb2e8f9f7	915	/* Clear the TC flag in the ICR register */
<>	144:ef7eb2e8f9f7	916	__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
<>	144:ef7eb2e8f9f7	917
<>	157:ff67d9f36b67	918	/* Process Unlocked */
<>	157:ff67d9f36b67	919	__HAL_UNLOCK(husart);
<>	157:ff67d9f36b67	920
<>	144:ef7eb2e8f9f7	921	/* Enable the DMA transfer for transmit request by setting the DMAT bit
<>	144:ef7eb2e8f9f7	922	in the USART CR3 register */
<>	157:ff67d9f36b67	923	SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	924
<>	144:ef7eb2e8f9f7	925	return HAL_OK;
<>	144:ef7eb2e8f9f7	926	}
<>	144:ef7eb2e8f9f7	927	else
<>	144:ef7eb2e8f9f7	928	{
<>	144:ef7eb2e8f9f7	929	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	930	}
<>	144:ef7eb2e8f9f7	931	}
<>	144:ef7eb2e8f9f7	932
<>	144:ef7eb2e8f9f7	933	/**
<>	144:ef7eb2e8f9f7	934	* @brief Receive an amount of data in DMA mode.
<>	157:ff67d9f36b67	935	* @param husart USART handle.
<>	157:ff67d9f36b67	936	* @param pRxData pointer to data buffer.
<>	157:ff67d9f36b67	937	* @param Size amount of data to be received.
<>	144:ef7eb2e8f9f7	938	* @note When the USART parity is enabled (PCE = 1), the received data contain
<>	157:ff67d9f36b67	939	* the parity bit (MSB position).
<>	144:ef7eb2e8f9f7	940	* @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
<>	157:ff67d9f36b67	941	* @note This function starts a DMA transfer in interrupt mode meaning that
<>	144:ef7eb2e8f9f7	942	* DMA half transfer complete, DMA transfer complete and DMA transfer
<>	144:ef7eb2e8f9f7	943	* error interrupts are enabled
<>	144:ef7eb2e8f9f7	944	* @retval HAL status
<>	144:ef7eb2e8f9f7	945	*/
<>	144:ef7eb2e8f9f7	946	HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef husart, uint8_t pRxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	947	{
<>	144:ef7eb2e8f9f7	948	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	949
<>	157:ff67d9f36b67	950	/* Check that a Rx process is not already ongoing */
<>	144:ef7eb2e8f9f7	951	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	952	{
<>	157:ff67d9f36b67	953	if((pRxData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	954	{
<>	144:ef7eb2e8f9f7	955	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	956	}
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958	/* Process Locked */
<>	144:ef7eb2e8f9f7	959	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	960
<>	144:ef7eb2e8f9f7	961	husart->pRxBuffPtr = pRxData;
<>	144:ef7eb2e8f9f7	962	husart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	963	husart->pTxBuffPtr = pRxData;
<>	144:ef7eb2e8f9f7	964	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	965
<>	144:ef7eb2e8f9f7	966	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	967	husart->State = HAL_USART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	968
<>	144:ef7eb2e8f9f7	969	/* Set the USART DMA Rx transfer complete callback */
<>	144:ef7eb2e8f9f7	970	husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
<>	144:ef7eb2e8f9f7	971
<>	144:ef7eb2e8f9f7	972	/* Set the USART DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	973	husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
<>	144:ef7eb2e8f9f7	974
<>	144:ef7eb2e8f9f7	975	/* Set the USART DMA Rx transfer error callback */
<>	144:ef7eb2e8f9f7	976	husart->hdmarx->XferErrorCallback = USART_DMAError;
<>	144:ef7eb2e8f9f7	977
<>	144:ef7eb2e8f9f7	978	/* Enable the USART receive DMA channel */
<>	144:ef7eb2e8f9f7	979	tmp = (uint32_t*)&pRxData;
<>	144:ef7eb2e8f9f7	980	HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, (uint32_t)tmp, Size);
<>	144:ef7eb2e8f9f7	981
<>	144:ef7eb2e8f9f7	982	/* Enable the USART transmit DMA channel: the transmit channel is used in order
<>	144:ef7eb2e8f9f7	983	to generate in the non-blocking mode the clock to the slave device,
<>	144:ef7eb2e8f9f7	984	this mode isn't a simplex receive mode but a full-duplex receive mode */
<>	157:ff67d9f36b67	985	/* Set the USART DMA Tx Complete and Error callback to Null */
<>	157:ff67d9f36b67	986	husart->hdmatx->XferErrorCallback = NULL;
<>	157:ff67d9f36b67	987	husart->hdmatx->XferHalfCpltCallback = NULL;
<>	157:ff67d9f36b67	988	husart->hdmatx->XferCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	989	HAL_DMA_Start_IT(husart->hdmatx, (uint32_t)tmp, (uint32_t)&husart->Instance->TDR, Size);
<>	144:ef7eb2e8f9f7	990
<>	157:ff67d9f36b67	991	/* Process Unlocked */
<>	157:ff67d9f36b67	992	__HAL_UNLOCK(husart);
<>	157:ff67d9f36b67	993
<>	157:ff67d9f36b67	994	/* Enable the USART Parity Error Interrupt */
<>	157:ff67d9f36b67	995	SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<>	157:ff67d9f36b67	996
<>	157:ff67d9f36b67	997	/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	157:ff67d9f36b67	998	SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	999
<>	144:ef7eb2e8f9f7	1000	/* Enable the DMA transfer for the receiver request by setting the DMAR bit
<>	144:ef7eb2e8f9f7	1001	in the USART CR3 register */
<>	157:ff67d9f36b67	1002	SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1003
<>	144:ef7eb2e8f9f7	1004	/* Enable the DMA transfer for transmit request by setting the DMAT bit
<>	144:ef7eb2e8f9f7	1005	in the USART CR3 register */
<>	157:ff67d9f36b67	1006	SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1007
<>	144:ef7eb2e8f9f7	1008	return HAL_OK;
<>	144:ef7eb2e8f9f7	1009	}
<>	144:ef7eb2e8f9f7	1010	else
<>	144:ef7eb2e8f9f7	1011	{
<>	144:ef7eb2e8f9f7	1012	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1013	}
<>	144:ef7eb2e8f9f7	1014	}
<>	144:ef7eb2e8f9f7	1015
<>	144:ef7eb2e8f9f7	1016	/**
<>	144:ef7eb2e8f9f7	1017	* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
<>	157:ff67d9f36b67	1018	* @param husart USART handle.
<>	157:ff67d9f36b67	1019	* @param pTxData pointer to TX data buffer.
<>	157:ff67d9f36b67	1020	* @param pRxData pointer to RX data buffer.
<>	157:ff67d9f36b67	1021	* @param Size amount of data to be received/sent.
<>	144:ef7eb2e8f9f7	1022	* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
<>	157:ff67d9f36b67	1023	* @note This function starts a 2 DMA transfers in interrupt mode meaning that
<>	144:ef7eb2e8f9f7	1024	* DMA half transfer complete, DMA transfer complete and DMA transfer
<>	144:ef7eb2e8f9f7	1025	* error interrupts are enabled
<>	144:ef7eb2e8f9f7	1026	* @retval HAL status
<>	144:ef7eb2e8f9f7	1027	*/
<>	144:ef7eb2e8f9f7	1028	HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef husart, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1029	{
<>	144:ef7eb2e8f9f7	1030	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	if(husart->State == HAL_USART_STATE_READY)
<>	144:ef7eb2e8f9f7	1033	{
<>	157:ff67d9f36b67	1034	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1035	{
<>	144:ef7eb2e8f9f7	1036	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1037	}
<>	157:ff67d9f36b67	1038
<>	144:ef7eb2e8f9f7	1039	/* Process Locked */
<>	144:ef7eb2e8f9f7	1040	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	1041
<>	144:ef7eb2e8f9f7	1042	husart->pRxBuffPtr = pRxData;
<>	144:ef7eb2e8f9f7	1043	husart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	1044	husart->pTxBuffPtr = pTxData;
<>	144:ef7eb2e8f9f7	1045	husart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1048	husart->State = HAL_USART_STATE_BUSY_TX_RX;
<>	144:ef7eb2e8f9f7	1049
<>	144:ef7eb2e8f9f7	1050	/* Set the USART DMA Rx transfer complete callback */
<>	144:ef7eb2e8f9f7	1051	husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
<>	144:ef7eb2e8f9f7	1052
<>	144:ef7eb2e8f9f7	1053	/* Set the USART DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1054	husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
<>	144:ef7eb2e8f9f7	1055
<>	144:ef7eb2e8f9f7	1056	/* Set the USART DMA Tx transfer complete callback */
<>	144:ef7eb2e8f9f7	1057	husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
<>	144:ef7eb2e8f9f7	1058
<>	144:ef7eb2e8f9f7	1059	/* Set the USART DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1060	husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
<>	144:ef7eb2e8f9f7	1061
<>	144:ef7eb2e8f9f7	1062	/* Set the USART DMA Tx transfer error callback */
<>	144:ef7eb2e8f9f7	1063	husart->hdmatx->XferErrorCallback = USART_DMAError;
<>	144:ef7eb2e8f9f7	1064
<>	144:ef7eb2e8f9f7	1065	/* Set the USART DMA Rx transfer error callback */
<>	144:ef7eb2e8f9f7	1066	husart->hdmarx->XferErrorCallback = USART_DMAError;
<>	144:ef7eb2e8f9f7	1067
<>	144:ef7eb2e8f9f7	1068	/* Enable the USART receive DMA channel */
<>	144:ef7eb2e8f9f7	1069	tmp = (uint32_t*)&pRxData;
<>	144:ef7eb2e8f9f7	1070	HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, (uint32_t)tmp, Size);
<>	144:ef7eb2e8f9f7	1071
<>	144:ef7eb2e8f9f7	1072	/* Enable the USART transmit DMA channel */
<>	144:ef7eb2e8f9f7	1073	tmp = (uint32_t*)&pTxData;
<>	144:ef7eb2e8f9f7	1074	HAL_DMA_Start_IT(husart->hdmatx, (uint32_t)tmp, (uint32_t)&husart->Instance->TDR, Size);
<>	144:ef7eb2e8f9f7	1075
<>	157:ff67d9f36b67	1076	/* Process Unlocked */
<>	157:ff67d9f36b67	1077	__HAL_UNLOCK(husart);
<>	157:ff67d9f36b67	1078
<>	157:ff67d9f36b67	1079	/* Enable the USART Parity Error Interrupt */
<>	157:ff67d9f36b67	1080	SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<>	157:ff67d9f36b67	1081
<>	157:ff67d9f36b67	1082	/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	157:ff67d9f36b67	1083	SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	1084
<>	144:ef7eb2e8f9f7	1085	/* Clear the TC flag in the ICR register */
<>	144:ef7eb2e8f9f7	1086	__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
<>	144:ef7eb2e8f9f7	1087
<>	144:ef7eb2e8f9f7	1088	/* Enable the DMA transfer for the receiver request by setting the DMAR bit
<>	144:ef7eb2e8f9f7	1089	in the USART CR3 register */
<>	157:ff67d9f36b67	1090	SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1091
<>	144:ef7eb2e8f9f7	1092	/* Enable the DMA transfer for transmit request by setting the DMAT bit
<>	144:ef7eb2e8f9f7	1093	in the USART CR3 register */
<>	157:ff67d9f36b67	1094	SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1095
<>	144:ef7eb2e8f9f7	1096	return HAL_OK;
<>	144:ef7eb2e8f9f7	1097	}
<>	144:ef7eb2e8f9f7	1098	else
<>	144:ef7eb2e8f9f7	1099	{
<>	144:ef7eb2e8f9f7	1100	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1101	}
<>	144:ef7eb2e8f9f7	1102	}
<>	144:ef7eb2e8f9f7	1103
<>	144:ef7eb2e8f9f7	1104	/**
<>	144:ef7eb2e8f9f7	1105	* @brief Pause the DMA Transfer.
<>	157:ff67d9f36b67	1106	* @param husart USART handle.
<>	144:ef7eb2e8f9f7	1107	* @retval HAL status
<>	144:ef7eb2e8f9f7	1108	*/
<>	144:ef7eb2e8f9f7	1109	HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1110	{
<>	144:ef7eb2e8f9f7	1111	/* Process Locked */
<>	144:ef7eb2e8f9f7	1112	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	1113
<>	157:ff67d9f36b67	1114	if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
<>	157:ff67d9f36b67	1115	(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
<>	144:ef7eb2e8f9f7	1116	{
<>	144:ef7eb2e8f9f7	1117	/* Disable the USART DMA Tx request */
<>	157:ff67d9f36b67	1118	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1119	}
<>	157:ff67d9f36b67	1120	else if( (husart->State == HAL_USART_STATE_BUSY_RX) \|\|
<>	157:ff67d9f36b67	1121	(husart->State == HAL_USART_STATE_BUSY_TX_RX) )
<>	144:ef7eb2e8f9f7	1122	{
<>	157:ff67d9f36b67	1123	if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
<>	157:ff67d9f36b67	1124	{
<>	157:ff67d9f36b67	1125	/* Disable the USART DMA Tx request */
<>	157:ff67d9f36b67	1126	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	1127	}
<>	157:ff67d9f36b67	1128	if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
<>	157:ff67d9f36b67	1129	{
<>	157:ff67d9f36b67	1130	/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	1131	CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<>	157:ff67d9f36b67	1132	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	1133
<>	157:ff67d9f36b67	1134	/* Disable the USART DMA Rx request */
<>	157:ff67d9f36b67	1135	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	1136	}
<>	144:ef7eb2e8f9f7	1137	}
<>	144:ef7eb2e8f9f7	1138
<>	144:ef7eb2e8f9f7	1139	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1140	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142	return HAL_OK;
<>	144:ef7eb2e8f9f7	1143	}
<>	144:ef7eb2e8f9f7	1144
<>	144:ef7eb2e8f9f7	1145	/**
<>	144:ef7eb2e8f9f7	1146	* @brief Resume the DMA Transfer.
<>	157:ff67d9f36b67	1147	* @param husart USART handle.
<>	144:ef7eb2e8f9f7	1148	* @retval HAL status
<>	144:ef7eb2e8f9f7	1149	*/
<>	144:ef7eb2e8f9f7	1150	HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1151	{
<>	144:ef7eb2e8f9f7	1152	/* Process Locked */
<>	144:ef7eb2e8f9f7	1153	__HAL_LOCK(husart);
<>	144:ef7eb2e8f9f7	1154
<>	144:ef7eb2e8f9f7	1155	if(husart->State == HAL_USART_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	1156	{
<>	144:ef7eb2e8f9f7	1157	/* Enable the USART DMA Tx request */
<>	157:ff67d9f36b67	1158	SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1159	}
<>	157:ff67d9f36b67	1160	else if( (husart->State == HAL_USART_STATE_BUSY_RX) \|\|
<>	157:ff67d9f36b67	1161	(husart->State == HAL_USART_STATE_BUSY_TX_RX) )
<>	144:ef7eb2e8f9f7	1162	{
<>	157:ff67d9f36b67	1163	/* Clear the Overrun flag before resuming the Rx transfer*/
<>	144:ef7eb2e8f9f7	1164	__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
<>	144:ef7eb2e8f9f7	1165
<>	157:ff67d9f36b67	1166	/* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	1167	SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<>	157:ff67d9f36b67	1168	SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1169
<>	144:ef7eb2e8f9f7	1170	/* Enable the USART DMA Rx request before the DMA Tx request */
<>	157:ff67d9f36b67	1171	SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1172
<>	144:ef7eb2e8f9f7	1173	/* Enable the USART DMA Tx request */
<>	157:ff67d9f36b67	1174	SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1175	}
<>	144:ef7eb2e8f9f7	1176
<>	144:ef7eb2e8f9f7	1177	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1178	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	1179
<>	144:ef7eb2e8f9f7	1180	return HAL_OK;
<>	144:ef7eb2e8f9f7	1181	}
<>	144:ef7eb2e8f9f7	1182
<>	144:ef7eb2e8f9f7	1183	/**
<>	144:ef7eb2e8f9f7	1184	* @brief Stop the DMA Transfer.
<>	157:ff67d9f36b67	1185	* @param husart USART handle.
<>	144:ef7eb2e8f9f7	1186	* @retval HAL status
<>	144:ef7eb2e8f9f7	1187	*/
<>	144:ef7eb2e8f9f7	1188	HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1189	{
<>	144:ef7eb2e8f9f7	1190	/* The Lock is not implemented on this API to allow the user application
<>	144:ef7eb2e8f9f7	1191	to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
<>	144:ef7eb2e8f9f7	1192	HAL_USART_TxHalfCpltCallback() / HAL_USART_RxHalfCpltCallback ():
<>	144:ef7eb2e8f9f7	1193	indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
<>	144:ef7eb2e8f9f7	1194	generated if the DMA transfer interruption occurs at the middle or at the end of the stream
<>	144:ef7eb2e8f9f7	1195	and the corresponding call back is executed.
<>	144:ef7eb2e8f9f7	1196	*/
<>	144:ef7eb2e8f9f7	1197
<>	144:ef7eb2e8f9f7	1198	/* Disable the USART Tx/Rx DMA requests */
<>	157:ff67d9f36b67	1199	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	1200	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1201
<>	144:ef7eb2e8f9f7	1202	/* Abort the USART DMA tx channel */
<>	144:ef7eb2e8f9f7	1203	if(husart->hdmatx != NULL)
<>	144:ef7eb2e8f9f7	1204	{
<>	144:ef7eb2e8f9f7	1205	HAL_DMA_Abort(husart->hdmatx);
<>	144:ef7eb2e8f9f7	1206	}
<>	144:ef7eb2e8f9f7	1207	/* Abort the USART DMA rx channel */
<>	144:ef7eb2e8f9f7	1208	if(husart->hdmarx != NULL)
<>	144:ef7eb2e8f9f7	1209	{
<>	144:ef7eb2e8f9f7	1210	HAL_DMA_Abort(husart->hdmarx);
<>	144:ef7eb2e8f9f7	1211	}
<>	144:ef7eb2e8f9f7	1212
<>	157:ff67d9f36b67	1213	USART_EndTransfer(husart);
<>	144:ef7eb2e8f9f7	1214	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	1215
<>	144:ef7eb2e8f9f7	1216	return HAL_OK;
<>	144:ef7eb2e8f9f7	1217	}
<>	144:ef7eb2e8f9f7	1218
<>	144:ef7eb2e8f9f7	1219	/**
<>	157:ff67d9f36b67	1220	* @brief Abort ongoing transfers (blocking mode).
<>	157:ff67d9f36b67	1221	* @param husart USART handle.
<>	157:ff67d9f36b67	1222	* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
<>	157:ff67d9f36b67	1223	* This procedure performs following operations :
<>	157:ff67d9f36b67	1224	* - Disable USART Interrupts (Tx and Rx)
<>	157:ff67d9f36b67	1225	* - Disable the DMA transfer in the peripheral register (if enabled)
<>	157:ff67d9f36b67	1226	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<>	157:ff67d9f36b67	1227	* - Set handle State to READY
<>	157:ff67d9f36b67	1228	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<>	157:ff67d9f36b67	1229	* @retval HAL status
<>	157:ff67d9f36b67	1230	*/
<>	157:ff67d9f36b67	1231	HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
<>	157:ff67d9f36b67	1232	{
<>	157:ff67d9f36b67	1233	/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	1234	CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE \| USART_CR1_TXEIE \| USART_CR1_TCIE));
<>	157:ff67d9f36b67	1235	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	1236
<>	157:ff67d9f36b67	1237	/* Disable the USART DMA Tx request if enabled */
<>	157:ff67d9f36b67	1238	if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
<>	157:ff67d9f36b67	1239	{
<>	157:ff67d9f36b67	1240	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	1241
<>	157:ff67d9f36b67	1242	/* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
<>	157:ff67d9f36b67	1243	if(husart->hdmatx != NULL)
<>	157:ff67d9f36b67	1244	{
<>	157:ff67d9f36b67	1245	/* Set the USART DMA Abort callback to Null.
<>	157:ff67d9f36b67	1246	No call back execution at end of DMA abort procedure */
<>	157:ff67d9f36b67	1247	husart->hdmatx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1248
<>	157:ff67d9f36b67	1249	HAL_DMA_Abort(husart->hdmatx);
<>	157:ff67d9f36b67	1250	}
<>	157:ff67d9f36b67	1251	}
<>	157:ff67d9f36b67	1252
<>	157:ff67d9f36b67	1253	/* Disable the USART DMA Rx request if enabled */
<>	157:ff67d9f36b67	1254	if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
<>	157:ff67d9f36b67	1255	{
<>	157:ff67d9f36b67	1256	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	1257
<>	157:ff67d9f36b67	1258	/* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
<>	157:ff67d9f36b67	1259	if(husart->hdmarx != NULL)
<>	157:ff67d9f36b67	1260	{
<>	157:ff67d9f36b67	1261	/* Set the USART DMA Abort callback to Null.
<>	157:ff67d9f36b67	1262	No call back execution at end of DMA abort procedure */
<>	157:ff67d9f36b67	1263	husart->hdmarx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1264
<>	157:ff67d9f36b67	1265	HAL_DMA_Abort(husart->hdmarx);
<>	157:ff67d9f36b67	1266	}
<>	157:ff67d9f36b67	1267	}
<>	157:ff67d9f36b67	1268
<>	157:ff67d9f36b67	1269	/* Reset Tx and Rx transfer counters */
<>	157:ff67d9f36b67	1270	husart->TxXferCount = 0U;
<>	157:ff67d9f36b67	1271	husart->RxXferCount = 0U;
<>	157:ff67d9f36b67	1272
<>	157:ff67d9f36b67	1273	/* Clear the Error flags in the ICR register */
<>	157:ff67d9f36b67	1274	__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF \| USART_CLEAR_NEF \| USART_CLEAR_PEF \| USART_CLEAR_FEF);
<>	157:ff67d9f36b67	1275
<>	157:ff67d9f36b67	1276	/* Restore husart->State to Ready */
<>	157:ff67d9f36b67	1277	husart->State = HAL_USART_STATE_READY;
<>	157:ff67d9f36b67	1278
<>	157:ff67d9f36b67	1279	/* Reset Handle ErrorCode to No Error */
<>	157:ff67d9f36b67	1280	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	157:ff67d9f36b67	1281
<>	157:ff67d9f36b67	1282	return HAL_OK;
<>	157:ff67d9f36b67	1283	}
<>	157:ff67d9f36b67	1284
<>	157:ff67d9f36b67	1285	/**
<>	157:ff67d9f36b67	1286	* @brief Abort ongoing transfers (Interrupt mode).
<>	157:ff67d9f36b67	1287	* @param husart USART handle.
<>	157:ff67d9f36b67	1288	* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
<>	157:ff67d9f36b67	1289	* This procedure performs following operations :
<>	157:ff67d9f36b67	1290	* - Disable USART Interrupts (Tx and Rx)
<>	157:ff67d9f36b67	1291	* - Disable the DMA transfer in the peripheral register (if enabled)
<>	157:ff67d9f36b67	1292	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<>	157:ff67d9f36b67	1293	* - Set handle State to READY
<>	157:ff67d9f36b67	1294	* - At abort completion, call user abort complete callback
<>	157:ff67d9f36b67	1295	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<>	157:ff67d9f36b67	1296	* considered as completed only when user abort complete callback is executed (not when exiting function).
<>	157:ff67d9f36b67	1297	* @retval HAL status
<>	157:ff67d9f36b67	1298	*/
<>	157:ff67d9f36b67	1299	HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
<>	157:ff67d9f36b67	1300	{
<>	157:ff67d9f36b67	1301	uint32_t abortcplt = 1U;
<>	157:ff67d9f36b67	1302
<>	157:ff67d9f36b67	1303	/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	1304	CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE \| USART_CR1_TXEIE \| USART_CR1_TCIE));
<>	157:ff67d9f36b67	1305	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	1306
<>	157:ff67d9f36b67	1307	/* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
<>	157:ff67d9f36b67	1308	before any call to DMA Abort functions */
<>	157:ff67d9f36b67	1309	/* DMA Tx Handle is valid */
<>	157:ff67d9f36b67	1310	if(husart->hdmatx != NULL)
<>	157:ff67d9f36b67	1311	{
<>	157:ff67d9f36b67	1312	/* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
<>	157:ff67d9f36b67	1313	Otherwise, set it to NULL */
<>	157:ff67d9f36b67	1314	if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
<>	157:ff67d9f36b67	1315	{
<>	157:ff67d9f36b67	1316	husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
<>	157:ff67d9f36b67	1317	}
<>	157:ff67d9f36b67	1318	else
<>	157:ff67d9f36b67	1319	{
<>	157:ff67d9f36b67	1320	husart->hdmatx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1321	}
<>	157:ff67d9f36b67	1322	}
<>	157:ff67d9f36b67	1323	/* DMA Rx Handle is valid */
<>	157:ff67d9f36b67	1324	if(husart->hdmarx != NULL)
<>	157:ff67d9f36b67	1325	{
<>	157:ff67d9f36b67	1326	/* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
<>	157:ff67d9f36b67	1327	Otherwise, set it to NULL */
<>	157:ff67d9f36b67	1328	if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
<>	157:ff67d9f36b67	1329	{
<>	157:ff67d9f36b67	1330	husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
<>	157:ff67d9f36b67	1331	}
<>	157:ff67d9f36b67	1332	else
<>	157:ff67d9f36b67	1333	{
<>	157:ff67d9f36b67	1334	husart->hdmarx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1335	}
<>	157:ff67d9f36b67	1336	}
<>	157:ff67d9f36b67	1337
<>	157:ff67d9f36b67	1338	/* Disable the USART DMA Tx request if enabled */
<>	157:ff67d9f36b67	1339	if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
<>	157:ff67d9f36b67	1340	{
<>	157:ff67d9f36b67	1341	/* Disable DMA Tx at USART level */
<>	157:ff67d9f36b67	1342	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	1343
<>	157:ff67d9f36b67	1344	/* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
<>	157:ff67d9f36b67	1345	if(husart->hdmatx != NULL)
<>	157:ff67d9f36b67	1346	{
<>	157:ff67d9f36b67	1347	/* USART Tx DMA Abort callback has already been initialised :
<>	157:ff67d9f36b67	1348	will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
<>	157:ff67d9f36b67	1349
<>	157:ff67d9f36b67	1350	/* Abort DMA TX */
<>	157:ff67d9f36b67	1351	if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
<>	157:ff67d9f36b67	1352	{
<>	157:ff67d9f36b67	1353	husart->hdmatx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1354	}
<>	157:ff67d9f36b67	1355	else
<>	157:ff67d9f36b67	1356	{
<>	157:ff67d9f36b67	1357	abortcplt = 0U;
<>	157:ff67d9f36b67	1358	}
<>	157:ff67d9f36b67	1359	}
<>	157:ff67d9f36b67	1360	}
<>	157:ff67d9f36b67	1361
<>	157:ff67d9f36b67	1362	/* Disable the USART DMA Rx request if enabled */
<>	157:ff67d9f36b67	1363	if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
<>	157:ff67d9f36b67	1364	{
<>	157:ff67d9f36b67	1365	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	1366
<>	157:ff67d9f36b67	1367	/* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
<>	157:ff67d9f36b67	1368	if(husart->hdmarx != NULL)
<>	157:ff67d9f36b67	1369	{
<>	157:ff67d9f36b67	1370	/* USART Rx DMA Abort callback has already been initialised :
<>	157:ff67d9f36b67	1371	will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
<>	157:ff67d9f36b67	1372
<>	157:ff67d9f36b67	1373	/* Abort DMA RX */
<>	157:ff67d9f36b67	1374	if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
<>	157:ff67d9f36b67	1375	{
<>	157:ff67d9f36b67	1376	husart->hdmarx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1377	abortcplt = 1U;
<>	157:ff67d9f36b67	1378	}
<>	157:ff67d9f36b67	1379	else
<>	157:ff67d9f36b67	1380	{
<>	157:ff67d9f36b67	1381	abortcplt = 0U;
<>	157:ff67d9f36b67	1382	}
<>	157:ff67d9f36b67	1383	}
<>	157:ff67d9f36b67	1384	}
<>	157:ff67d9f36b67	1385
<>	157:ff67d9f36b67	1386	/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
<>	157:ff67d9f36b67	1387	if (abortcplt == 1U)
<>	157:ff67d9f36b67	1388	{
<>	157:ff67d9f36b67	1389	/* Reset Tx and Rx transfer counters */
<>	157:ff67d9f36b67	1390	husart->TxXferCount = 0U;
<>	157:ff67d9f36b67	1391	husart->RxXferCount = 0U;
<>	157:ff67d9f36b67	1392
<>	157:ff67d9f36b67	1393	/* Reset errorCode */
<>	157:ff67d9f36b67	1394	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	157:ff67d9f36b67	1395
<>	157:ff67d9f36b67	1396	/* Clear the Error flags in the ICR register */
<>	157:ff67d9f36b67	1397	__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF \| USART_CLEAR_NEF \| USART_CLEAR_PEF \| USART_CLEAR_FEF);
<>	157:ff67d9f36b67	1398
<>	157:ff67d9f36b67	1399	/* Restore husart->State to Ready */
<>	157:ff67d9f36b67	1400	husart->State = HAL_USART_STATE_READY;
<>	157:ff67d9f36b67	1401
<>	157:ff67d9f36b67	1402	/* As no DMA to be aborted, call directly user Abort complete callback */
<>	157:ff67d9f36b67	1403	HAL_USART_AbortCpltCallback(husart);
<>	157:ff67d9f36b67	1404	}
<>	157:ff67d9f36b67	1405
<>	157:ff67d9f36b67	1406	return HAL_OK;
<>	157:ff67d9f36b67	1407	}
<>	157:ff67d9f36b67	1408
<>	157:ff67d9f36b67	1409	/**
<>	144:ef7eb2e8f9f7	1410	* @brief Handle USART interrupt request.
<>	157:ff67d9f36b67	1411	* @param husart USART handle.
<>	144:ef7eb2e8f9f7	1412	* @retval None
<>	144:ef7eb2e8f9f7	1413	*/
<>	144:ef7eb2e8f9f7	1414	void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1415	{
<>	157:ff67d9f36b67	1416	uint32_t isrflags = READ_REG(husart->Instance->ISR);
<>	157:ff67d9f36b67	1417	uint32_t cr1its = READ_REG(husart->Instance->CR1);
<>	157:ff67d9f36b67	1418	uint32_t cr3its;
<>	157:ff67d9f36b67	1419	uint32_t errorflags;
<>	144:ef7eb2e8f9f7	1420
<>	157:ff67d9f36b67	1421	/* If no error occurs */
<>	157:ff67d9f36b67	1422	errorflags = (isrflags & (uint32_t)(USART_ISR_PE \| USART_ISR_FE \| USART_ISR_ORE \| USART_ISR_NE));
<>	157:ff67d9f36b67	1423	if (errorflags == RESET)
<>	144:ef7eb2e8f9f7	1424	{
<>	157:ff67d9f36b67	1425	/* USART in mode Receiver ---------------------------------------------------*/
<>	157:ff67d9f36b67	1426	if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<>	144:ef7eb2e8f9f7	1427	{
<>	157:ff67d9f36b67	1428	if(husart->State == HAL_USART_STATE_BUSY_RX)
<>	157:ff67d9f36b67	1429	{
<>	157:ff67d9f36b67	1430	USART_Receive_IT(husart);
<>	157:ff67d9f36b67	1431	}
<>	157:ff67d9f36b67	1432	else
<>	157:ff67d9f36b67	1433	{
<>	157:ff67d9f36b67	1434	USART_TransmitReceive_IT(husart);
<>	157:ff67d9f36b67	1435	}
<>	157:ff67d9f36b67	1436	return;
<>	144:ef7eb2e8f9f7	1437	}
<>	144:ef7eb2e8f9f7	1438	}
<>	144:ef7eb2e8f9f7	1439
<>	157:ff67d9f36b67	1440	/* If some errors occur */
<>	157:ff67d9f36b67	1441	cr3its = READ_REG(husart->Instance->CR3);
<>	157:ff67d9f36b67	1442	if( (errorflags != RESET)
<>	157:ff67d9f36b67	1443	&& ( ((cr3its & USART_CR3_EIE) != RESET)
<>	157:ff67d9f36b67	1444	\|\| ((cr1its & (USART_CR1_RXNEIE \| USART_CR1_PEIE)) != RESET)) )
<>	157:ff67d9f36b67	1445	{
<>	157:ff67d9f36b67	1446	/* USART parity error interrupt occurred -------------------------------------*/
<>	157:ff67d9f36b67	1447	if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
<>	157:ff67d9f36b67	1448	{
<>	157:ff67d9f36b67	1449	__HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
<>	157:ff67d9f36b67	1450
<>	157:ff67d9f36b67	1451	husart->ErrorCode \|= HAL_USART_ERROR_PE;
<>	157:ff67d9f36b67	1452	}
<>	157:ff67d9f36b67	1453
<>	157:ff67d9f36b67	1454	/* USART frame error interrupt occurred --------------------------------------*/
<>	157:ff67d9f36b67	1455	if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<>	157:ff67d9f36b67	1456	{
<>	157:ff67d9f36b67	1457	__HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
<>	157:ff67d9f36b67	1458
<>	157:ff67d9f36b67	1459	husart->ErrorCode \|= HAL_USART_ERROR_FE;
<>	157:ff67d9f36b67	1460	}
<>	157:ff67d9f36b67	1461
<>	157:ff67d9f36b67	1462	/* USART noise error interrupt occurred --------------------------------------*/
<>	157:ff67d9f36b67	1463	if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<>	157:ff67d9f36b67	1464	{
<>	157:ff67d9f36b67	1465	__HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
<>	157:ff67d9f36b67	1466
<>	157:ff67d9f36b67	1467	husart->ErrorCode \|= HAL_USART_ERROR_NE;
<>	157:ff67d9f36b67	1468	}
<>	157:ff67d9f36b67	1469
<>	157:ff67d9f36b67	1470	/* USART Over-Run interrupt occurred -----------------------------------------*/
<>	157:ff67d9f36b67	1471	if(((isrflags & USART_ISR_ORE) != RESET) &&
<>	157:ff67d9f36b67	1472	(((cr1its & USART_CR1_RXNEIE) != RESET) \|\| ((cr3its & USART_CR3_EIE) != RESET)))
<>	157:ff67d9f36b67	1473	{
<>	157:ff67d9f36b67	1474	__HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
<>	157:ff67d9f36b67	1475
<>	157:ff67d9f36b67	1476	husart->ErrorCode \|= HAL_USART_ERROR_ORE;
<>	157:ff67d9f36b67	1477	}
<>	157:ff67d9f36b67	1478
<>	157:ff67d9f36b67	1479	/* Call USART Error Call back function if need be --------------------------*/
<>	157:ff67d9f36b67	1480	if(husart->ErrorCode != HAL_USART_ERROR_NONE)
<>	157:ff67d9f36b67	1481	{
<>	157:ff67d9f36b67	1482	/* USART in mode Receiver ---------------------------------------------------*/
<>	157:ff67d9f36b67	1483	if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<>	157:ff67d9f36b67	1484	{
<>	157:ff67d9f36b67	1485	if(husart->State == HAL_USART_STATE_BUSY_RX)
<>	157:ff67d9f36b67	1486	{
<>	157:ff67d9f36b67	1487	USART_Receive_IT(husart);
<>	157:ff67d9f36b67	1488	}
<>	157:ff67d9f36b67	1489	else
<>	157:ff67d9f36b67	1490	{
<>	157:ff67d9f36b67	1491	USART_TransmitReceive_IT(husart);
<>	157:ff67d9f36b67	1492	}
<>	157:ff67d9f36b67	1493	}
<>	157:ff67d9f36b67	1494
<>	157:ff67d9f36b67	1495	/* If Overrun error occurs, or if any error occurs in DMA mode reception,
<>	157:ff67d9f36b67	1496	consider error as blocking */
<>	157:ff67d9f36b67	1497	if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) \|\|
<>	157:ff67d9f36b67	1498	(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
<>	157:ff67d9f36b67	1499	{
<>	157:ff67d9f36b67	1500	/* Blocking error : transfer is aborted
<>	157:ff67d9f36b67	1501	Set the USART state ready to be able to start again the process,
<>	157:ff67d9f36b67	1502	Disable Interrupts, and disable DMA requests, if ongoing */
<>	157:ff67d9f36b67	1503	USART_EndTransfer(husart);
<>	157:ff67d9f36b67	1504
<>	157:ff67d9f36b67	1505	/* Disable the USART DMA Rx request if enabled */
<>	157:ff67d9f36b67	1506	if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
<>	157:ff67d9f36b67	1507	{
<>	157:ff67d9f36b67	1508	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR \| USART_CR3_DMAR);
<>	157:ff67d9f36b67	1509
<>	157:ff67d9f36b67	1510	/* Abort the USART DMA Tx channel */
<>	157:ff67d9f36b67	1511	if(husart->hdmatx != NULL)
<>	157:ff67d9f36b67	1512	{
<>	157:ff67d9f36b67	1513	/* Set the USART Tx DMA Abort callback to NULL : no callback
<>	157:ff67d9f36b67	1514	executed at end of DMA abort procedure */
<>	157:ff67d9f36b67	1515	husart->hdmatx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1516
<>	157:ff67d9f36b67	1517	/* Abort DMA TX */
<>	157:ff67d9f36b67	1518	HAL_DMA_Abort_IT(husart->hdmatx);
<>	157:ff67d9f36b67	1519	}
<>	157:ff67d9f36b67	1520
<>	157:ff67d9f36b67	1521	/* Abort the USART DMA Rx channel */
<>	157:ff67d9f36b67	1522	if(husart->hdmarx != NULL)
<>	157:ff67d9f36b67	1523	{
<>	157:ff67d9f36b67	1524	/* Set the USART Rx DMA Abort callback :
<>	157:ff67d9f36b67	1525	will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
<>	157:ff67d9f36b67	1526	husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
<>	157:ff67d9f36b67	1527
<>	157:ff67d9f36b67	1528	/* Abort DMA RX */
<>	157:ff67d9f36b67	1529	if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
<>	157:ff67d9f36b67	1530	{
<>	157:ff67d9f36b67	1531	/* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
<>	157:ff67d9f36b67	1532	husart->hdmarx->XferAbortCallback(husart->hdmarx);
<>	157:ff67d9f36b67	1533	}
<>	157:ff67d9f36b67	1534	}
<>	157:ff67d9f36b67	1535	else
<>	157:ff67d9f36b67	1536	{
<>	157:ff67d9f36b67	1537	/* Call user error callback */
<>	157:ff67d9f36b67	1538	HAL_USART_ErrorCallback(husart);
<>	157:ff67d9f36b67	1539	}
<>	157:ff67d9f36b67	1540	}
<>	157:ff67d9f36b67	1541	else
<>	157:ff67d9f36b67	1542	{
<>	157:ff67d9f36b67	1543	/* Call user error callback */
<>	157:ff67d9f36b67	1544	HAL_USART_ErrorCallback(husart);
<>	157:ff67d9f36b67	1545	}
<>	157:ff67d9f36b67	1546	}
<>	157:ff67d9f36b67	1547	else
<>	157:ff67d9f36b67	1548	{
<>	157:ff67d9f36b67	1549	/* Non Blocking error : transfer could go on.
<>	157:ff67d9f36b67	1550	Error is notified to user through user error callback */
<>	157:ff67d9f36b67	1551	HAL_USART_ErrorCallback(husart);
<>	157:ff67d9f36b67	1552	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	157:ff67d9f36b67	1553	}
<>	157:ff67d9f36b67	1554	}
<>	157:ff67d9f36b67	1555	return;
<>	157:ff67d9f36b67	1556
<>	157:ff67d9f36b67	1557	} /* End if some error occurs */
<>	157:ff67d9f36b67	1558
<>	157:ff67d9f36b67	1559
<>	157:ff67d9f36b67	1560	/* USART in mode Transmitter ------------------------------------------------*/
<>	157:ff67d9f36b67	1561	if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
<>	144:ef7eb2e8f9f7	1562	{
<>	144:ef7eb2e8f9f7	1563	if(husart->State == HAL_USART_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	1564	{
<>	144:ef7eb2e8f9f7	1565	USART_Transmit_IT(husart);
<>	144:ef7eb2e8f9f7	1566	}
<>	144:ef7eb2e8f9f7	1567	else
<>	144:ef7eb2e8f9f7	1568	{
<>	144:ef7eb2e8f9f7	1569	USART_TransmitReceive_IT(husart);
<>	144:ef7eb2e8f9f7	1570	}
<>	157:ff67d9f36b67	1571	return;
<>	144:ef7eb2e8f9f7	1572	}
<>	144:ef7eb2e8f9f7	1573
<>	144:ef7eb2e8f9f7	1574	/* USART in mode Transmitter (transmission end) -----------------------------*/
<>	157:ff67d9f36b67	1575	if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
<>	144:ef7eb2e8f9f7	1576	{
<>	144:ef7eb2e8f9f7	1577	USART_EndTransmit_IT(husart);
<>	157:ff67d9f36b67	1578	return;
<>	144:ef7eb2e8f9f7	1579	}
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	}
<>	144:ef7eb2e8f9f7	1582
<>	144:ef7eb2e8f9f7	1583	/**
<>	144:ef7eb2e8f9f7	1584	* @brief Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	1585	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	1586	* @retval None
<>	144:ef7eb2e8f9f7	1587	*/
<>	144:ef7eb2e8f9f7	1588	__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1589	{
<>	144:ef7eb2e8f9f7	1590	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1591	UNUSED(husart);
<>	144:ef7eb2e8f9f7	1592
<>	144:ef7eb2e8f9f7	1593	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1594	the HAL_USART_TxCpltCallback can be implemented in the user file.
<>	144:ef7eb2e8f9f7	1595	*/
<>	144:ef7eb2e8f9f7	1596	}
<>	144:ef7eb2e8f9f7	1597
<>	144:ef7eb2e8f9f7	1598	/**
<>	144:ef7eb2e8f9f7	1599	* @brief Tx Half Transfer completed callback.
<>	157:ff67d9f36b67	1600	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	1601	* @retval None
<>	144:ef7eb2e8f9f7	1602	*/
<>	157:ff67d9f36b67	1603	__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1604	{
<>	144:ef7eb2e8f9f7	1605	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1606	UNUSED(husart);
<>	144:ef7eb2e8f9f7	1607
<>	144:ef7eb2e8f9f7	1608	/* NOTE: This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1609	the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
<>	144:ef7eb2e8f9f7	1610	*/
<>	144:ef7eb2e8f9f7	1611	}
<>	144:ef7eb2e8f9f7	1612
<>	144:ef7eb2e8f9f7	1613	/**
<>	144:ef7eb2e8f9f7	1614	* @brief Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	1615	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	1616	* @retval None
<>	144:ef7eb2e8f9f7	1617	*/
<>	144:ef7eb2e8f9f7	1618	__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1619	{
<>	144:ef7eb2e8f9f7	1620	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1621	UNUSED(husart);
<>	144:ef7eb2e8f9f7	1622
<>	144:ef7eb2e8f9f7	1623	/* NOTE: This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1624	the HAL_USART_RxCpltCallback can be implemented in the user file.
<>	144:ef7eb2e8f9f7	1625	*/
<>	144:ef7eb2e8f9f7	1626	}
<>	144:ef7eb2e8f9f7	1627
<>	144:ef7eb2e8f9f7	1628	/**
<>	144:ef7eb2e8f9f7	1629	* @brief Rx Half Transfer completed callback.
<>	144:ef7eb2e8f9f7	1630	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	1631	* @retval None
<>	144:ef7eb2e8f9f7	1632	*/
<>	144:ef7eb2e8f9f7	1633	__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1634	{
<>	144:ef7eb2e8f9f7	1635	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1636	UNUSED(husart);
<>	144:ef7eb2e8f9f7	1637
<>	144:ef7eb2e8f9f7	1638	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1639	the HAL_USART_RxHalfCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	1640	*/
<>	144:ef7eb2e8f9f7	1641	}
<>	144:ef7eb2e8f9f7	1642
<>	144:ef7eb2e8f9f7	1643	/**
<>	144:ef7eb2e8f9f7	1644	* @brief Tx/Rx Transfers completed callback for the non-blocking process.
<>	157:ff67d9f36b67	1645	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	1646	* @retval None
<>	144:ef7eb2e8f9f7	1647	*/
<>	144:ef7eb2e8f9f7	1648	__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1649	{
<>	144:ef7eb2e8f9f7	1650	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1651	UNUSED(husart);
<>	144:ef7eb2e8f9f7	1652
<>	144:ef7eb2e8f9f7	1653	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1654	the HAL_USART_TxRxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	1655	*/
<>	144:ef7eb2e8f9f7	1656	}
<>	144:ef7eb2e8f9f7	1657
<>	144:ef7eb2e8f9f7	1658	/**
<>	144:ef7eb2e8f9f7	1659	* @brief USART error callback.
<>	144:ef7eb2e8f9f7	1660	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	1661	* @retval None
<>	144:ef7eb2e8f9f7	1662	*/
<>	144:ef7eb2e8f9f7	1663	__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1664	{
<>	144:ef7eb2e8f9f7	1665	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1666	UNUSED(husart);
<>	144:ef7eb2e8f9f7	1667
<>	144:ef7eb2e8f9f7	1668	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1669	the HAL_USART_ErrorCallback can be implemented in the user file.
<>	144:ef7eb2e8f9f7	1670	*/
<>	144:ef7eb2e8f9f7	1671	}
<>	144:ef7eb2e8f9f7	1672
<>	144:ef7eb2e8f9f7	1673	/**
<>	157:ff67d9f36b67	1674	* @brief USART Abort Complete callback.
<>	157:ff67d9f36b67	1675	* @param husart USART handle.
<>	157:ff67d9f36b67	1676	* @retval None
<>	157:ff67d9f36b67	1677	*/
<>	157:ff67d9f36b67	1678	__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
<>	157:ff67d9f36b67	1679	{
<>	157:ff67d9f36b67	1680	/* Prevent unused argument(s) compilation warning */
<>	157:ff67d9f36b67	1681	UNUSED(husart);
<>	157:ff67d9f36b67	1682
<>	157:ff67d9f36b67	1683	/* NOTE : This function should not be modified, when the callback is needed,
<>	157:ff67d9f36b67	1684	the HAL_USART_AbortCpltCallback can be implemented in the user file.
<>	157:ff67d9f36b67	1685	*/
<>	157:ff67d9f36b67	1686	}
<>	157:ff67d9f36b67	1687
<>	157:ff67d9f36b67	1688	/**
<>	144:ef7eb2e8f9f7	1689	* @}
<>	144:ef7eb2e8f9f7	1690	*/
<>	144:ef7eb2e8f9f7	1691
<>	144:ef7eb2e8f9f7	1692	/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Error functions
<>	144:ef7eb2e8f9f7	1693	* @brief USART Peripheral State and Error functions
<>	144:ef7eb2e8f9f7	1694	*
<>	144:ef7eb2e8f9f7	1695	@verbatim
<>	144:ef7eb2e8f9f7	1696	==============================================================================
<>	144:ef7eb2e8f9f7	1697	##### Peripheral State and Error functions #####
<>	144:ef7eb2e8f9f7	1698	==============================================================================
<>	144:ef7eb2e8f9f7	1699	[..]
<>	144:ef7eb2e8f9f7	1700	This subsection provides functions allowing to :
<>	144:ef7eb2e8f9f7	1701	(+) Return the USART handle state
<>	144:ef7eb2e8f9f7	1702	(+) Return the USART handle error code
<>	144:ef7eb2e8f9f7	1703
<>	144:ef7eb2e8f9f7	1704	@endverbatim
<>	144:ef7eb2e8f9f7	1705	* @{
<>	144:ef7eb2e8f9f7	1706	*/
<>	144:ef7eb2e8f9f7	1707
<>	144:ef7eb2e8f9f7	1708
<>	144:ef7eb2e8f9f7	1709	/**
<>	144:ef7eb2e8f9f7	1710	* @brief Return the USART handle state.
<>	144:ef7eb2e8f9f7	1711	* @param husart : pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1712	* the configuration information for the specified USART.
<>	144:ef7eb2e8f9f7	1713	* @retval USART handle state
<>	144:ef7eb2e8f9f7	1714	*/
<>	144:ef7eb2e8f9f7	1715	HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1716	{
<>	144:ef7eb2e8f9f7	1717	return husart->State;
<>	144:ef7eb2e8f9f7	1718	}
<>	144:ef7eb2e8f9f7	1719
<>	144:ef7eb2e8f9f7	1720	/**
<>	144:ef7eb2e8f9f7	1721	* @brief Return the USART error code.
<>	144:ef7eb2e8f9f7	1722	* @param husart : pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1723	* the configuration information for the specified USART.
<>	144:ef7eb2e8f9f7	1724	* @retval USART handle Error Code
<>	144:ef7eb2e8f9f7	1725	*/
<>	144:ef7eb2e8f9f7	1726	uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	1727	{
<>	144:ef7eb2e8f9f7	1728	return husart->ErrorCode;
<>	144:ef7eb2e8f9f7	1729	}
<>	144:ef7eb2e8f9f7	1730
<>	144:ef7eb2e8f9f7	1731	/**
<>	144:ef7eb2e8f9f7	1732	* @}
<>	144:ef7eb2e8f9f7	1733	*/
<>	144:ef7eb2e8f9f7	1734
<>	144:ef7eb2e8f9f7	1735	/**
<>	144:ef7eb2e8f9f7	1736	* @}
<>	144:ef7eb2e8f9f7	1737	*/
<>	144:ef7eb2e8f9f7	1738
<>	144:ef7eb2e8f9f7	1739	/** @defgroup USART_Private_Functions USART Private Functions
<>	144:ef7eb2e8f9f7	1740	* @brief USART Private functions
<>	144:ef7eb2e8f9f7	1741	*
<>	144:ef7eb2e8f9f7	1742	@verbatim
<>	144:ef7eb2e8f9f7	1743	[..]
<>	144:ef7eb2e8f9f7	1744	This subsection provides a set of functions allowing to control the USART.
<>	144:ef7eb2e8f9f7	1745	(+) USART_SetConfig() API is used to set the USART communication parameters.
<>	144:ef7eb2e8f9f7	1746	(+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization
<>	144:ef7eb2e8f9f7	1747
<>	144:ef7eb2e8f9f7	1748	@endverbatim
<>	144:ef7eb2e8f9f7	1749	* @{
<>	144:ef7eb2e8f9f7	1750	*/
<>	157:ff67d9f36b67	1751	/**
<>	157:ff67d9f36b67	1752	* @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion).
<>	157:ff67d9f36b67	1753	* @param husart USART handle.
<>	157:ff67d9f36b67	1754	* @retval None
<>	157:ff67d9f36b67	1755	*/
<>	157:ff67d9f36b67	1756	static void USART_EndTransfer(USART_HandleTypeDef *husart)
<>	157:ff67d9f36b67	1757	{
<>	157:ff67d9f36b67	1758	/* Disable TXEIE and TCIE interrupts */
<>	157:ff67d9f36b67	1759	/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	1760	CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE \| USART_CR1_TCIE \| USART_CR1_RXNEIE \| USART_CR1_PEIE));
<>	157:ff67d9f36b67	1761	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	1762
<>	157:ff67d9f36b67	1763	/* At end of process, restore husart->State to Ready */
<>	157:ff67d9f36b67	1764	husart->State = HAL_USART_STATE_READY;
<>	157:ff67d9f36b67	1765	}
<>	157:ff67d9f36b67	1766
<>	157:ff67d9f36b67	1767	/**
<>	157:ff67d9f36b67	1768	* @brief DMA USART transmit process complete callback.
<>	157:ff67d9f36b67	1769	* @param hdma DMA handle.
<>	157:ff67d9f36b67	1770	* @retval None
<>	157:ff67d9f36b67	1771	*/
<>	157:ff67d9f36b67	1772	static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1773	{
<>	157:ff67d9f36b67	1774	USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	1775
<>	157:ff67d9f36b67	1776	/* DMA Normal mode */
<>	157:ff67d9f36b67	1777	if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<>	157:ff67d9f36b67	1778	{
<>	157:ff67d9f36b67	1779	husart->TxXferCount = 0U;
<>	157:ff67d9f36b67	1780
<>	157:ff67d9f36b67	1781	if(husart->State == HAL_USART_STATE_BUSY_TX)
<>	157:ff67d9f36b67	1782	{
<>	157:ff67d9f36b67	1783	/* Disable the DMA transfer for transmit request by resetting the DMAT bit
<>	157:ff67d9f36b67	1784	in the USART CR3 register */
<>	157:ff67d9f36b67	1785	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	1786
<>	157:ff67d9f36b67	1787	/* Enable the USART Transmit Complete Interrupt */
<>	157:ff67d9f36b67	1788	__HAL_USART_ENABLE_IT(husart, USART_IT_TC);
<>	157:ff67d9f36b67	1789	}
<>	157:ff67d9f36b67	1790	}
<>	157:ff67d9f36b67	1791	/* DMA Circular mode */
<>	157:ff67d9f36b67	1792	else
<>	157:ff67d9f36b67	1793	{
<>	157:ff67d9f36b67	1794	if(husart->State == HAL_USART_STATE_BUSY_TX)
<>	157:ff67d9f36b67	1795	{
<>	157:ff67d9f36b67	1796	HAL_USART_TxCpltCallback(husart);
<>	157:ff67d9f36b67	1797	}
<>	157:ff67d9f36b67	1798	}
<>	157:ff67d9f36b67	1799	}
<>	157:ff67d9f36b67	1800
<>	157:ff67d9f36b67	1801	/**
<>	157:ff67d9f36b67	1802	* @brief DMA USART transmit process half complete callback.
<>	157:ff67d9f36b67	1803	* @param hdma DMA handle.
<>	157:ff67d9f36b67	1804	* @retval None
<>	157:ff67d9f36b67	1805	*/
<>	157:ff67d9f36b67	1806	static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1807	{
<>	157:ff67d9f36b67	1808	USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	1809
<>	157:ff67d9f36b67	1810	HAL_USART_TxHalfCpltCallback(husart);
<>	157:ff67d9f36b67	1811	}
<>	157:ff67d9f36b67	1812
<>	157:ff67d9f36b67	1813	/**
<>	157:ff67d9f36b67	1814	* @brief DMA USART receive process complete callback.
<>	157:ff67d9f36b67	1815	* @param hdma DMA handle.
<>	157:ff67d9f36b67	1816	* @retval None
<>	157:ff67d9f36b67	1817	*/
<>	157:ff67d9f36b67	1818	static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1819	{
<>	157:ff67d9f36b67	1820	USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	1821
<>	157:ff67d9f36b67	1822	/* DMA Normal mode */
<>	157:ff67d9f36b67	1823	if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<>	157:ff67d9f36b67	1824	{
<>	157:ff67d9f36b67	1825	husart->RxXferCount = 0U;
<>	157:ff67d9f36b67	1826
<>	157:ff67d9f36b67	1827	/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	157:ff67d9f36b67	1828	CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<>	157:ff67d9f36b67	1829	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	1830
<>	157:ff67d9f36b67	1831	/* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
<>	157:ff67d9f36b67	1832	in USART CR3 register */
<>	157:ff67d9f36b67	1833	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<>	157:ff67d9f36b67	1834	/* similarly, disable the DMA TX transfer that was started to provide the
<>	157:ff67d9f36b67	1835	clock to the slave device */
<>	157:ff67d9f36b67	1836	CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<>	157:ff67d9f36b67	1837
<>	157:ff67d9f36b67	1838	if(husart->State == HAL_USART_STATE_BUSY_RX)
<>	157:ff67d9f36b67	1839	{
<>	157:ff67d9f36b67	1840	HAL_USART_RxCpltCallback(husart);
<>	157:ff67d9f36b67	1841	}
<>	157:ff67d9f36b67	1842	/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
<>	157:ff67d9f36b67	1843	else
<>	157:ff67d9f36b67	1844	{
<>	157:ff67d9f36b67	1845	HAL_USART_TxRxCpltCallback(husart);
<>	157:ff67d9f36b67	1846	}
<>	157:ff67d9f36b67	1847	husart->State= HAL_USART_STATE_READY;
<>	157:ff67d9f36b67	1848	}
<>	157:ff67d9f36b67	1849	/* DMA circular mode */
<>	157:ff67d9f36b67	1850	else
<>	157:ff67d9f36b67	1851	{
<>	157:ff67d9f36b67	1852	if(husart->State == HAL_USART_STATE_BUSY_RX)
<>	157:ff67d9f36b67	1853	{
<>	157:ff67d9f36b67	1854	HAL_USART_RxCpltCallback(husart);
<>	157:ff67d9f36b67	1855	}
<>	157:ff67d9f36b67	1856	/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
<>	157:ff67d9f36b67	1857	else
<>	157:ff67d9f36b67	1858	{
<>	157:ff67d9f36b67	1859	HAL_USART_TxRxCpltCallback(husart);
<>	157:ff67d9f36b67	1860	}
<>	157:ff67d9f36b67	1861	}
<>	157:ff67d9f36b67	1862
<>	157:ff67d9f36b67	1863	}
<>	157:ff67d9f36b67	1864
<>	157:ff67d9f36b67	1865	/**
<>	157:ff67d9f36b67	1866	* @brief DMA USART receive process half complete callback.
<>	157:ff67d9f36b67	1867	* @param hdma DMA handle.
<>	157:ff67d9f36b67	1868	* @retval None
<>	157:ff67d9f36b67	1869	*/
<>	157:ff67d9f36b67	1870	static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1871	{
<>	157:ff67d9f36b67	1872	USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	1873
<>	157:ff67d9f36b67	1874	HAL_USART_RxHalfCpltCallback(husart);
<>	157:ff67d9f36b67	1875	}
<>	157:ff67d9f36b67	1876
<>	157:ff67d9f36b67	1877	/**
<>	157:ff67d9f36b67	1878	* @brief DMA USART communication error callback.
<>	157:ff67d9f36b67	1879	* @param hdma: DMA handle.
<>	157:ff67d9f36b67	1880	* @retval None
<>	157:ff67d9f36b67	1881	*/
<>	157:ff67d9f36b67	1882	static void USART_DMAError(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1883	{
<>	157:ff67d9f36b67	1884	USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	1885
<>	157:ff67d9f36b67	1886	husart->RxXferCount = 0U;
<>	157:ff67d9f36b67	1887	husart->TxXferCount = 0U;
<>	157:ff67d9f36b67	1888	USART_EndTransfer(husart);
<>	157:ff67d9f36b67	1889
<>	157:ff67d9f36b67	1890	husart->ErrorCode \|= HAL_USART_ERROR_DMA;
<>	157:ff67d9f36b67	1891	husart->State= HAL_USART_STATE_READY;
<>	157:ff67d9f36b67	1892
<>	157:ff67d9f36b67	1893	HAL_USART_ErrorCallback(husart);
<>	157:ff67d9f36b67	1894	}
<>	157:ff67d9f36b67	1895
<>	157:ff67d9f36b67	1896	/**
<>	157:ff67d9f36b67	1897	* @brief DMA USART communication abort callback, when initiated by HAL services on Error
<>	157:ff67d9f36b67	1898	* (To be called at end of DMA Abort procedure following error occurrence).
<>	157:ff67d9f36b67	1899	* @param hdma DMA handle.
<>	157:ff67d9f36b67	1900	* @retval None
<>	157:ff67d9f36b67	1901	*/
<>	157:ff67d9f36b67	1902	static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1903	{
<>	157:ff67d9f36b67	1904	USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
<>	157:ff67d9f36b67	1905	husart->RxXferCount = 0U;
<>	157:ff67d9f36b67	1906	husart->TxXferCount = 0U;
<>	157:ff67d9f36b67	1907
<>	157:ff67d9f36b67	1908	HAL_USART_ErrorCallback(husart);
<>	157:ff67d9f36b67	1909	}
<>	157:ff67d9f36b67	1910
<>	157:ff67d9f36b67	1911	/**
<>	157:ff67d9f36b67	1912	* @brief DMA USART Tx communication abort callback, when initiated by user
<>	157:ff67d9f36b67	1913	* (To be called at end of DMA Tx Abort procedure following user abort request).
<>	157:ff67d9f36b67	1914	* @note When this callback is executed, User Abort complete call back is called only if no
<>	157:ff67d9f36b67	1915	* Abort still ongoing for Rx DMA Handle.
<>	157:ff67d9f36b67	1916	* @param hdma DMA handle.
<>	157:ff67d9f36b67	1917	* @retval None
<>	157:ff67d9f36b67	1918	*/
<>	157:ff67d9f36b67	1919	static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1920	{
<>	157:ff67d9f36b67	1921	USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
<>	157:ff67d9f36b67	1922
<>	157:ff67d9f36b67	1923	husart->hdmatx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1924
<>	157:ff67d9f36b67	1925	/* Check if an Abort process is still ongoing */
<>	157:ff67d9f36b67	1926	if(husart->hdmarx != NULL)
<>	157:ff67d9f36b67	1927	{
<>	157:ff67d9f36b67	1928	if(husart->hdmarx->XferAbortCallback != NULL)
<>	157:ff67d9f36b67	1929	{
<>	157:ff67d9f36b67	1930	return;
<>	157:ff67d9f36b67	1931	}
<>	157:ff67d9f36b67	1932	}
<>	157:ff67d9f36b67	1933
<>	157:ff67d9f36b67	1934	/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
<>	157:ff67d9f36b67	1935	husart->TxXferCount = 0U;
<>	157:ff67d9f36b67	1936	husart->RxXferCount = 0U;
<>	157:ff67d9f36b67	1937
<>	157:ff67d9f36b67	1938	/* Reset errorCode */
<>	157:ff67d9f36b67	1939	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	157:ff67d9f36b67	1940
<>	157:ff67d9f36b67	1941	/* Clear the Error flags in the ICR register */
<>	157:ff67d9f36b67	1942	__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF \| USART_CLEAR_NEF \| USART_CLEAR_PEF \| USART_CLEAR_FEF);
<>	157:ff67d9f36b67	1943
<>	157:ff67d9f36b67	1944	/* Restore husart->State to Ready */
<>	157:ff67d9f36b67	1945	husart->State = HAL_USART_STATE_READY;
<>	157:ff67d9f36b67	1946
<>	157:ff67d9f36b67	1947	/* Call user Abort complete callback */
<>	157:ff67d9f36b67	1948	HAL_USART_AbortCpltCallback(husart);
<>	157:ff67d9f36b67	1949	}
<>	157:ff67d9f36b67	1950
<>	157:ff67d9f36b67	1951
<>	157:ff67d9f36b67	1952	/**
<>	157:ff67d9f36b67	1953	* @brief DMA USART Rx communication abort callback, when initiated by user
<>	157:ff67d9f36b67	1954	* (To be called at end of DMA Rx Abort procedure following user abort request).
<>	157:ff67d9f36b67	1955	* @note When this callback is executed, User Abort complete call back is called only if no
<>	157:ff67d9f36b67	1956	* Abort still ongoing for Tx DMA Handle.
<>	157:ff67d9f36b67	1957	* @param hdma DMA handle.
<>	157:ff67d9f36b67	1958	* @retval None
<>	157:ff67d9f36b67	1959	*/
<>	157:ff67d9f36b67	1960	static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
<>	157:ff67d9f36b67	1961	{
<>	157:ff67d9f36b67	1962	USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
<>	157:ff67d9f36b67	1963
<>	157:ff67d9f36b67	1964	husart->hdmarx->XferAbortCallback = NULL;
<>	157:ff67d9f36b67	1965
<>	157:ff67d9f36b67	1966	/* Check if an Abort process is still ongoing */
<>	157:ff67d9f36b67	1967	if(husart->hdmatx != NULL)
<>	157:ff67d9f36b67	1968	{
<>	157:ff67d9f36b67	1969	if(husart->hdmatx->XferAbortCallback != NULL)
<>	157:ff67d9f36b67	1970	{
<>	157:ff67d9f36b67	1971	return;
<>	157:ff67d9f36b67	1972	}
<>	157:ff67d9f36b67	1973	}
<>	157:ff67d9f36b67	1974
<>	157:ff67d9f36b67	1975	/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
<>	157:ff67d9f36b67	1976	husart->TxXferCount = 0U;
<>	157:ff67d9f36b67	1977	husart->RxXferCount = 0U;
<>	157:ff67d9f36b67	1978
<>	157:ff67d9f36b67	1979	/* Reset errorCode */
<>	157:ff67d9f36b67	1980	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	157:ff67d9f36b67	1981
<>	157:ff67d9f36b67	1982	/* Clear the Error flags in the ICR register */
<>	157:ff67d9f36b67	1983	__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF \| USART_CLEAR_NEF \| USART_CLEAR_PEF \| USART_CLEAR_FEF);
<>	157:ff67d9f36b67	1984
<>	157:ff67d9f36b67	1985	/* Restore husart->State to Ready */
<>	157:ff67d9f36b67	1986	husart->State = HAL_USART_STATE_READY;
<>	157:ff67d9f36b67	1987
<>	157:ff67d9f36b67	1988	/* Call user Abort complete callback */
<>	157:ff67d9f36b67	1989	HAL_USART_AbortCpltCallback(husart);
<>	157:ff67d9f36b67	1990	}
<>	157:ff67d9f36b67	1991
<>	157:ff67d9f36b67	1992
<>	157:ff67d9f36b67	1993	/**
<>	157:ff67d9f36b67	1994	* @brief Handle USART Communication Timeout.
<>	157:ff67d9f36b67	1995	* @param husart USART handle.
<>	157:ff67d9f36b67	1996	* @param Flag Specifies the USART flag to check.
<>	157:ff67d9f36b67	1997	* @param Status the Flag status (SET or RESET).
<>	157:ff67d9f36b67	1998	* @param Tickstart Tick start value
<>	157:ff67d9f36b67	1999	* @param Timeout timeout duration.
<>	157:ff67d9f36b67	2000	* @retval HAL status
<>	157:ff67d9f36b67	2001	*/
<>	157:ff67d9f36b67	2002	static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
<>	157:ff67d9f36b67	2003	{
<>	157:ff67d9f36b67	2004	/* Wait until flag is set */
<>	157:ff67d9f36b67	2005	while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
<>	157:ff67d9f36b67	2006	{
<>	157:ff67d9f36b67	2007	/* Check for the Timeout */
<>	157:ff67d9f36b67	2008	if(Timeout != HAL_MAX_DELAY)
<>	157:ff67d9f36b67	2009	{
<>	157:ff67d9f36b67	2010	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	157:ff67d9f36b67	2011	{
<>	157:ff67d9f36b67	2012	/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<>	157:ff67d9f36b67	2013	CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE \| USART_CR1_TXEIE));
<>	157:ff67d9f36b67	2014	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	157:ff67d9f36b67	2015
<>	157:ff67d9f36b67	2016	husart->State= HAL_USART_STATE_READY;
<>	157:ff67d9f36b67	2017
<>	157:ff67d9f36b67	2018	/* Process Unlocked */
<>	157:ff67d9f36b67	2019	__HAL_UNLOCK(husart);
<>	157:ff67d9f36b67	2020
<>	157:ff67d9f36b67	2021	return HAL_TIMEOUT;
<>	157:ff67d9f36b67	2022	}
<>	157:ff67d9f36b67	2023	}
<>	157:ff67d9f36b67	2024	}
<>	157:ff67d9f36b67	2025	return HAL_OK;
<>	157:ff67d9f36b67	2026	}
<>	157:ff67d9f36b67	2027
<>	144:ef7eb2e8f9f7	2028
<>	144:ef7eb2e8f9f7	2029	/**
<>	144:ef7eb2e8f9f7	2030	* @brief Configure the USART peripheral.
<>	144:ef7eb2e8f9f7	2031	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	2032	* @retval HAL status
<>	144:ef7eb2e8f9f7	2033	*/
<>	144:ef7eb2e8f9f7	2034	static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	2035	{
<>	157:ff67d9f36b67	2036	uint32_t tmpreg = 0x0U;
<>	144:ef7eb2e8f9f7	2037	USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
<>	144:ef7eb2e8f9f7	2038	HAL_StatusTypeDef ret = HAL_OK;
<>	157:ff67d9f36b67	2039	uint16_t brrtemp = 0x0000U;
<>	157:ff67d9f36b67	2040	uint16_t usartdiv = 0x0000U;
<>	144:ef7eb2e8f9f7	2041
<>	144:ef7eb2e8f9f7	2042	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2043	assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
<>	144:ef7eb2e8f9f7	2044	assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
<>	144:ef7eb2e8f9f7	2045	assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
<>	144:ef7eb2e8f9f7	2046	assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	2047	assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
<>	144:ef7eb2e8f9f7	2048	assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
<>	144:ef7eb2e8f9f7	2049	assert_param(IS_USART_PARITY(husart->Init.Parity));
<>	144:ef7eb2e8f9f7	2050	assert_param(IS_USART_MODE(husart->Init.Mode));
<>	144:ef7eb2e8f9f7	2051
<>	144:ef7eb2e8f9f7	2052
<>	144:ef7eb2e8f9f7	2053	/-------------------------- USART CR1 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	2054	/* Clear M, PCE, PS, TE and RE bits and configure
<>	144:ef7eb2e8f9f7	2055	* the USART Word Length, Parity and Mode:
<>	144:ef7eb2e8f9f7	2056	* set the M bits according to husart->Init.WordLength value
<>	144:ef7eb2e8f9f7	2057	* set PCE and PS bits according to husart->Init.Parity value
<>	144:ef7eb2e8f9f7	2058	* set TE and RE bits according to husart->Init.Mode value
<>	144:ef7eb2e8f9f7	2059	* force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
<>	144:ef7eb2e8f9f7	2060	tmpreg = (uint32_t)husart->Init.WordLength \| husart->Init.Parity \| husart->Init.Mode \| USART_CR1_OVER8;
<>	144:ef7eb2e8f9f7	2061	MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
<>	144:ef7eb2e8f9f7	2062
<>	144:ef7eb2e8f9f7	2063	/---------------------------- USART CR2 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	2064	/* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
<>	144:ef7eb2e8f9f7	2065	* set CPOL bit according to husart->Init.CLKPolarity value
<>	144:ef7eb2e8f9f7	2066	* set CPHA bit according to husart->Init.CLKPhase value
<>	144:ef7eb2e8f9f7	2067	* set LBCL bit according to husart->Init.CLKLastBit value
<>	144:ef7eb2e8f9f7	2068	* set STOP[13:12] bits according to husart->Init.StopBits value */
<>	144:ef7eb2e8f9f7	2069	tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
<>	144:ef7eb2e8f9f7	2070	tmpreg \|= ((uint32_t)husart->Init.CLKPolarity \| (uint32_t)husart->Init.CLKPhase);
<>	144:ef7eb2e8f9f7	2071	tmpreg \|= ((uint32_t)husart->Init.CLKLastBit \| (uint32_t)husart->Init.StopBits);
<>	144:ef7eb2e8f9f7	2072	MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
<>	144:ef7eb2e8f9f7	2073
<>	144:ef7eb2e8f9f7	2074	/-------------------------- USART CR3 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	2075	/* no CR3 register configuration */
<>	144:ef7eb2e8f9f7	2076
<>	144:ef7eb2e8f9f7	2077	/-------------------------- USART BRR Configuration -----------------------/
<>	144:ef7eb2e8f9f7	2078	/* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
<>	144:ef7eb2e8f9f7	2079	USART_GETCLOCKSOURCE(husart, clocksource);
<>	144:ef7eb2e8f9f7	2080	switch (clocksource)
<>	144:ef7eb2e8f9f7	2081	{
<>	144:ef7eb2e8f9f7	2082	case USART_CLOCKSOURCE_PCLK1:
<>	157:ff67d9f36b67	2083	usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
<>	144:ef7eb2e8f9f7	2084	break;
<>	144:ef7eb2e8f9f7	2085	case USART_CLOCKSOURCE_PCLK2:
<>	157:ff67d9f36b67	2086	usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
<>	144:ef7eb2e8f9f7	2087	break;
<>	144:ef7eb2e8f9f7	2088	case USART_CLOCKSOURCE_HSI:
<>	157:ff67d9f36b67	2089	usartdiv = (uint16_t)(((2U*HSI_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
<>	144:ef7eb2e8f9f7	2090	break;
<>	144:ef7eb2e8f9f7	2091	case USART_CLOCKSOURCE_SYSCLK:
<>	157:ff67d9f36b67	2092	usartdiv = (uint16_t)(((2U*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
<>	144:ef7eb2e8f9f7	2093	break;
<>	144:ef7eb2e8f9f7	2094	case USART_CLOCKSOURCE_LSE:
<>	157:ff67d9f36b67	2095	usartdiv = (uint16_t)(((2U*LSE_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
<>	144:ef7eb2e8f9f7	2096	break;
<>	144:ef7eb2e8f9f7	2097	case USART_CLOCKSOURCE_UNDEFINED:
<>	144:ef7eb2e8f9f7	2098	default:
<>	144:ef7eb2e8f9f7	2099	ret = HAL_ERROR;
<>	144:ef7eb2e8f9f7	2100	break;
<>	144:ef7eb2e8f9f7	2101	}
<>	144:ef7eb2e8f9f7	2102
<>	157:ff67d9f36b67	2103	brrtemp = usartdiv & 0xFFF0U;
<>	157:ff67d9f36b67	2104	brrtemp \|= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
<>	144:ef7eb2e8f9f7	2105	husart->Instance->BRR = brrtemp;
<>	144:ef7eb2e8f9f7	2106
<>	144:ef7eb2e8f9f7	2107	return ret;
<>	144:ef7eb2e8f9f7	2108	}
<>	144:ef7eb2e8f9f7	2109
<>	144:ef7eb2e8f9f7	2110	/**
<>	144:ef7eb2e8f9f7	2111	* @brief Check the USART Idle State.
<>	144:ef7eb2e8f9f7	2112	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	2113	* @retval HAL status
<>	144:ef7eb2e8f9f7	2114	*/
<>	144:ef7eb2e8f9f7	2115	static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	2116	{
<>	157:ff67d9f36b67	2117	uint32_t tickstart = 0U;
<>	157:ff67d9f36b67	2118
<>	144:ef7eb2e8f9f7	2119	/* Initialize the USART ErrorCode */
<>	144:ef7eb2e8f9f7	2120	husart->ErrorCode = HAL_USART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2121
<>	157:ff67d9f36b67	2122	/* Init tickstart for timeout managment*/
<>	157:ff67d9f36b67	2123	tickstart = HAL_GetTick();
<>	157:ff67d9f36b67	2124
<>	144:ef7eb2e8f9f7	2125	/* Check if the Transmitter is enabled */
<>	144:ef7eb2e8f9f7	2126	if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
<>	144:ef7eb2e8f9f7	2127	{
<>	144:ef7eb2e8f9f7	2128	/* Wait until TEACK flag is set */
<>	157:ff67d9f36b67	2129	if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
<>	144:ef7eb2e8f9f7	2130	{
<>	144:ef7eb2e8f9f7	2131	/* Timeout Occured */
<>	144:ef7eb2e8f9f7	2132	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2133	}
<>	144:ef7eb2e8f9f7	2134	}
<>	144:ef7eb2e8f9f7	2135
<>	144:ef7eb2e8f9f7	2136	/* REACK bit in ISR is checked only when available (not to be checked on all instances).
<>	144:ef7eb2e8f9f7	2137	Bit is defined only for USART instances supporting WakeUp from Stop Mode feature.
<>	144:ef7eb2e8f9f7	2138	*/
<>	144:ef7eb2e8f9f7	2139	if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(husart->Instance))
<>	144:ef7eb2e8f9f7	2140	{
<>	144:ef7eb2e8f9f7	2141	/* Check if the Receiver is enabled */
<>	144:ef7eb2e8f9f7	2142	if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
<>	144:ef7eb2e8f9f7	2143	{
<>	144:ef7eb2e8f9f7	2144	/* Wait until REACK flag is set */
<>	157:ff67d9f36b67	2145	if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
<>	144:ef7eb2e8f9f7	2146	{
<>	144:ef7eb2e8f9f7	2147	/* Timeout occurred */
<>	144:ef7eb2e8f9f7	2148	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2149	}
<>	144:ef7eb2e8f9f7	2150	}
<>	144:ef7eb2e8f9f7	2151	}
<>	144:ef7eb2e8f9f7	2152
<>	144:ef7eb2e8f9f7	2153	/* Initialize the USART state*/
<>	144:ef7eb2e8f9f7	2154	husart->State= HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	2155
<>	144:ef7eb2e8f9f7	2156	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2157	__HAL_UNLOCK(husart);
<>	144:ef7eb2e8f9f7	2158
<>	144:ef7eb2e8f9f7	2159	return HAL_OK;
<>	144:ef7eb2e8f9f7	2160	}
<>	144:ef7eb2e8f9f7	2161
<>	144:ef7eb2e8f9f7	2162
<>	144:ef7eb2e8f9f7	2163	/**
<>	144:ef7eb2e8f9f7	2164	* @brief Simplex send an amount of data in non-blocking mode.
<>	144:ef7eb2e8f9f7	2165	* @note Function called under interruption only, once
<>	144:ef7eb2e8f9f7	2166	* interruptions have been enabled by HAL_USART_Transmit_IT().
<>	144:ef7eb2e8f9f7	2167	* @note The USART errors are not managed to avoid the overrun error.
<>	157:ff67d9f36b67	2168	* @param husart USART handle.
<>	144:ef7eb2e8f9f7	2169	* @retval HAL status
<>	144:ef7eb2e8f9f7	2170	*/
<>	144:ef7eb2e8f9f7	2171	static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	2172	{
<>	157:ff67d9f36b67	2173	uint16_t* tmp=0U;
<>	144:ef7eb2e8f9f7	2174
<>	157:ff67d9f36b67	2175	/* Check that a Tx process is ongoing */
<>	144:ef7eb2e8f9f7	2176	if(husart->State == HAL_USART_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	2177	{
<>	144:ef7eb2e8f9f7	2178
<>	157:ff67d9f36b67	2179	if(husart->TxXferCount == 0U)
<>	144:ef7eb2e8f9f7	2180	{
<>	144:ef7eb2e8f9f7	2181	/* Disable the USART Transmit data register empty interrupt */
<>	144:ef7eb2e8f9f7	2182	__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
<>	144:ef7eb2e8f9f7	2183
<>	144:ef7eb2e8f9f7	2184	/* Enable the USART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	2185	__HAL_USART_ENABLE_IT(husart, USART_IT_TC);
<>	144:ef7eb2e8f9f7	2186
<>	144:ef7eb2e8f9f7	2187	return HAL_OK;
<>	144:ef7eb2e8f9f7	2188	}
<>	144:ef7eb2e8f9f7	2189	else
<>	144:ef7eb2e8f9f7	2190	{
<>	144:ef7eb2e8f9f7	2191	if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<>	144:ef7eb2e8f9f7	2192	{
<>	144:ef7eb2e8f9f7	2193	tmp = (uint16_t*) husart->pTxBuffPtr;
<>	157:ff67d9f36b67	2194	husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<>	157:ff67d9f36b67	2195	husart->pTxBuffPtr += 2U;
<>	144:ef7eb2e8f9f7	2196	}
<>	144:ef7eb2e8f9f7	2197	else
<>	144:ef7eb2e8f9f7	2198	{
<>	157:ff67d9f36b67	2199	husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU);
<>	144:ef7eb2e8f9f7	2200	}
<>	144:ef7eb2e8f9f7	2201
<>	144:ef7eb2e8f9f7	2202	husart->TxXferCount--;
<>	144:ef7eb2e8f9f7	2203
<>	144:ef7eb2e8f9f7	2204	return HAL_OK;
<>	144:ef7eb2e8f9f7	2205	}
<>	144:ef7eb2e8f9f7	2206	}
<>	144:ef7eb2e8f9f7	2207	else
<>	144:ef7eb2e8f9f7	2208	{
<>	144:ef7eb2e8f9f7	2209	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2210	}
<>	144:ef7eb2e8f9f7	2211	}
<>	144:ef7eb2e8f9f7	2212
<>	144:ef7eb2e8f9f7	2213
<>	144:ef7eb2e8f9f7	2214	/**
<>	144:ef7eb2e8f9f7	2215	* @brief Wraps up transmission in non-blocking mode.
<>	157:ff67d9f36b67	2216	* @param husart Pointer to a USART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2217	* the configuration information for the specified USART module.
<>	144:ef7eb2e8f9f7	2218	* @retval HAL status
<>	144:ef7eb2e8f9f7	2219	*/
<>	144:ef7eb2e8f9f7	2220	static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	2221	{
<>	144:ef7eb2e8f9f7	2222	/* Disable the USART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	2223	__HAL_USART_DISABLE_IT(husart, USART_IT_TC);
<>	144:ef7eb2e8f9f7	2224
<>	144:ef7eb2e8f9f7	2225	/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	2226	__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
<>	144:ef7eb2e8f9f7	2227
<>	157:ff67d9f36b67	2228	/* Tx process is ended, restore husart->State to Ready */
<>	144:ef7eb2e8f9f7	2229	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	2230
<>	144:ef7eb2e8f9f7	2231	HAL_USART_TxCpltCallback(husart);
<>	144:ef7eb2e8f9f7	2232
<>	144:ef7eb2e8f9f7	2233	return HAL_OK;
<>	144:ef7eb2e8f9f7	2234	}
<>	144:ef7eb2e8f9f7	2235
<>	144:ef7eb2e8f9f7	2236
<>	144:ef7eb2e8f9f7	2237	/**
<>	144:ef7eb2e8f9f7	2238	* @brief Simplex receive an amount of data in non-blocking mode.
<>	144:ef7eb2e8f9f7	2239	* @note Function called under interruption only, once
<>	144:ef7eb2e8f9f7	2240	* interruptions have been enabled by HAL_USART_Receive_IT().
<>	157:ff67d9f36b67	2241	* @param husart USART handle
<>	144:ef7eb2e8f9f7	2242	* @retval HAL status
<>	144:ef7eb2e8f9f7	2243	*/
<>	144:ef7eb2e8f9f7	2244	static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	2245	{
<>	157:ff67d9f36b67	2246	uint16_t* tmp=0U;
<>	144:ef7eb2e8f9f7	2247	uint16_t uhMask = husart->Mask;
<>	144:ef7eb2e8f9f7	2248
<>	144:ef7eb2e8f9f7	2249	if(husart->State == HAL_USART_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	2250	{
<>	144:ef7eb2e8f9f7	2251
<>	144:ef7eb2e8f9f7	2252	if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<>	144:ef7eb2e8f9f7	2253	{
<>	144:ef7eb2e8f9f7	2254	tmp = (uint16_t*) husart->pRxBuffPtr;
<>	144:ef7eb2e8f9f7	2255	*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
<>	157:ff67d9f36b67	2256	husart->pRxBuffPtr += 2U;
<>	144:ef7eb2e8f9f7	2257	}
<>	144:ef7eb2e8f9f7	2258	else
<>	144:ef7eb2e8f9f7	2259	{
<>	144:ef7eb2e8f9f7	2260	*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
<>	144:ef7eb2e8f9f7	2261	}
<>	144:ef7eb2e8f9f7	2262
<>	144:ef7eb2e8f9f7	2263	/* Send dummy byte in order to generate the clock for the Slave to Send the next data */
<>	157:ff67d9f36b67	2264	husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
<>	144:ef7eb2e8f9f7	2265
<>	157:ff67d9f36b67	2266	if(--husart->RxXferCount == 0U)
<>	144:ef7eb2e8f9f7	2267	{
<>	157:ff67d9f36b67	2268	/* Disable the USART Parity Error Interrupt and RXNE interrupt*/
<>	157:ff67d9f36b67	2269	CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
<>	144:ef7eb2e8f9f7	2270
<>	144:ef7eb2e8f9f7	2271	/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	157:ff67d9f36b67	2272	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	2273
<>	157:ff67d9f36b67	2274	/* Rx process is completed, restore husart->State to Ready */
<>	144:ef7eb2e8f9f7	2275	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	2276
<>	144:ef7eb2e8f9f7	2277	HAL_USART_RxCpltCallback(husart);
<>	144:ef7eb2e8f9f7	2278
<>	144:ef7eb2e8f9f7	2279	return HAL_OK;
<>	144:ef7eb2e8f9f7	2280	}
<>	144:ef7eb2e8f9f7	2281
<>	144:ef7eb2e8f9f7	2282	return HAL_OK;
<>	144:ef7eb2e8f9f7	2283	}
<>	144:ef7eb2e8f9f7	2284	else
<>	144:ef7eb2e8f9f7	2285	{
<>	144:ef7eb2e8f9f7	2286	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2287	}
<>	144:ef7eb2e8f9f7	2288	}
<>	144:ef7eb2e8f9f7	2289
<>	144:ef7eb2e8f9f7	2290	/**
<>	144:ef7eb2e8f9f7	2291	* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
<>	144:ef7eb2e8f9f7	2292	* @note Function called under interruption only, once
<>	144:ef7eb2e8f9f7	2293	* interruptions have been enabled by HAL_USART_TransmitReceive_IT().
<>	144:ef7eb2e8f9f7	2294	* @param husart: USART handle.
<>	144:ef7eb2e8f9f7	2295	* @retval HAL status
<>	144:ef7eb2e8f9f7	2296	*/
<>	144:ef7eb2e8f9f7	2297	static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
<>	144:ef7eb2e8f9f7	2298	{
<>	157:ff67d9f36b67	2299	uint16_t* tmp=0U;
<>	144:ef7eb2e8f9f7	2300	uint16_t uhMask = husart->Mask;
<>	144:ef7eb2e8f9f7	2301
<>	144:ef7eb2e8f9f7	2302	if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
<>	144:ef7eb2e8f9f7	2303	{
<>	144:ef7eb2e8f9f7	2304
<>	157:ff67d9f36b67	2305	if(husart->TxXferCount != 0x00U)
<>	144:ef7eb2e8f9f7	2306	{
<>	144:ef7eb2e8f9f7	2307	if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
<>	144:ef7eb2e8f9f7	2308	{
<>	144:ef7eb2e8f9f7	2309	if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<>	144:ef7eb2e8f9f7	2310	{
<>	144:ef7eb2e8f9f7	2311	tmp = (uint16_t*) husart->pTxBuffPtr;
<>	144:ef7eb2e8f9f7	2312	husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
<>	157:ff67d9f36b67	2313	husart->pTxBuffPtr += 2U;
<>	144:ef7eb2e8f9f7	2314	}
<>	144:ef7eb2e8f9f7	2315	else
<>	144:ef7eb2e8f9f7	2316	{
<>	144:ef7eb2e8f9f7	2317	husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
<>	144:ef7eb2e8f9f7	2318	}
<>	144:ef7eb2e8f9f7	2319	husart->TxXferCount--;
<>	144:ef7eb2e8f9f7	2320
<>	144:ef7eb2e8f9f7	2321	/* Check the latest data transmitted */
<>	157:ff67d9f36b67	2322	if(husart->TxXferCount == 0U)
<>	144:ef7eb2e8f9f7	2323	{
<>	144:ef7eb2e8f9f7	2324	__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
<>	144:ef7eb2e8f9f7	2325	}
<>	144:ef7eb2e8f9f7	2326	}
<>	144:ef7eb2e8f9f7	2327	}
<>	144:ef7eb2e8f9f7	2328
<>	157:ff67d9f36b67	2329	if(husart->RxXferCount != 0x00U)
<>	144:ef7eb2e8f9f7	2330	{
<>	144:ef7eb2e8f9f7	2331	if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
<>	144:ef7eb2e8f9f7	2332	{
<>	144:ef7eb2e8f9f7	2333	if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<>	144:ef7eb2e8f9f7	2334	{
<>	144:ef7eb2e8f9f7	2335	tmp = (uint16_t*) husart->pRxBuffPtr;
<>	144:ef7eb2e8f9f7	2336	*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
<>	157:ff67d9f36b67	2337	husart->pRxBuffPtr += 2U;
<>	144:ef7eb2e8f9f7	2338	}
<>	144:ef7eb2e8f9f7	2339	else
<>	144:ef7eb2e8f9f7	2340	{
<>	144:ef7eb2e8f9f7	2341	*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
<>	144:ef7eb2e8f9f7	2342	}
<>	144:ef7eb2e8f9f7	2343	husart->RxXferCount--;
<>	144:ef7eb2e8f9f7	2344	}
<>	144:ef7eb2e8f9f7	2345	}
<>	144:ef7eb2e8f9f7	2346
<>	144:ef7eb2e8f9f7	2347	/* Check the latest data received */
<>	157:ff67d9f36b67	2348	if(husart->RxXferCount == 0U)
<>	144:ef7eb2e8f9f7	2349	{
<>	157:ff67d9f36b67	2350	/* Disable the USART Parity Error Interrupt and RXNE interrupt*/
<>	157:ff67d9f36b67	2351	CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
<>	144:ef7eb2e8f9f7	2352
<>	144:ef7eb2e8f9f7	2353	/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<>	157:ff67d9f36b67	2354	CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	2355
<>	157:ff67d9f36b67	2356	/* Rx process is completed, restore husart->State to Ready */
<>	144:ef7eb2e8f9f7	2357	husart->State = HAL_USART_STATE_READY;
<>	144:ef7eb2e8f9f7	2358
<>	144:ef7eb2e8f9f7	2359	HAL_USART_TxRxCpltCallback(husart);
<>	144:ef7eb2e8f9f7	2360
<>	144:ef7eb2e8f9f7	2361	return HAL_OK;
<>	144:ef7eb2e8f9f7	2362	}
<>	144:ef7eb2e8f9f7	2363
<>	144:ef7eb2e8f9f7	2364	return HAL_OK;
<>	144:ef7eb2e8f9f7	2365	}
<>	144:ef7eb2e8f9f7	2366	else
<>	144:ef7eb2e8f9f7	2367	{
<>	144:ef7eb2e8f9f7	2368	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2369	}
<>	144:ef7eb2e8f9f7	2370	}
<>	144:ef7eb2e8f9f7	2371
<>	144:ef7eb2e8f9f7	2372	/**
<>	144:ef7eb2e8f9f7	2373	* @}
<>	144:ef7eb2e8f9f7	2374	*/
<>	144:ef7eb2e8f9f7	2375
<>	144:ef7eb2e8f9f7	2376	#endif /* HAL_USART_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	2377	/**
<>	144:ef7eb2e8f9f7	2378	* @}
<>	144:ef7eb2e8f9f7	2379	*/
<>	144:ef7eb2e8f9f7	2380
<>	144:ef7eb2e8f9f7	2381	/**
<>	144:ef7eb2e8f9f7	2382	* @}
<>	144:ef7eb2e8f9f7	2383	*/
<>	144:ef7eb2e8f9f7	2384
<>	144:ef7eb2e8f9f7	2385	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	29 Nov 2017
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