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targets/TARGET_ARM_SSG/TARGET_BEETLE/spi_api.c@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
160:d5399cc887bb
Child:
170:19eb464bc2be
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include <math.h>
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 19 #include "spi_def.h"
<> 144:ef7eb2e8f9f7 20 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 21 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 22 #include "mbed_error.h"
<> 160:d5399cc887bb 23 #include "mbed_wait_api.h"
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 /*
<> 144:ef7eb2e8f9f7 26 * Driver private data structure that should not be shared by multiple
<> 144:ef7eb2e8f9f7 27 * instances of the driver (same driver for multiple instances of the IP)
<> 144:ef7eb2e8f9f7 28 */
<> 144:ef7eb2e8f9f7 29 typedef struct {
<> 144:ef7eb2e8f9f7 30 uint32_t size; /* size of an SPI frame in bits: can be 8 or 16 */
<> 144:ef7eb2e8f9f7 31 } private_spi_t;
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 static const PinMap PinMap_SPI_SCLK[] = {
<> 144:ef7eb2e8f9f7 34 {SHIELD_SPI_SCK , SPI_0, 0},
<> 144:ef7eb2e8f9f7 35 {ADC_SPI_SCK , SPI_1, 0},
<> 144:ef7eb2e8f9f7 36 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 37 };
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 static const PinMap PinMap_SPI_MOSI[] = {
<> 144:ef7eb2e8f9f7 40 {SHIELD_SPI_MOSI, SPI_0, 0},
<> 144:ef7eb2e8f9f7 41 {ADC_SPI_MOSI, SPI_1, 0},
<> 144:ef7eb2e8f9f7 42 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 43 };
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 static const PinMap PinMap_SPI_MISO[] = {
<> 144:ef7eb2e8f9f7 46 {SHIELD_SPI_MISO, SPI_0, 0},
<> 144:ef7eb2e8f9f7 47 {ADC_SPI_MISO, SPI_1, 0},
<> 144:ef7eb2e8f9f7 48 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 49 };
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 static const PinMap PinMap_SPI_SSEL[] = {
<> 144:ef7eb2e8f9f7 52 {SHIELD_SPI_nCS, SPI_0, 0},
<> 144:ef7eb2e8f9f7 53 {ADC_SPI_nCS, SPI_1, 0},
<> 144:ef7eb2e8f9f7 54 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 55 };
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*
<> 144:ef7eb2e8f9f7 58 * Retrieve the private data of the instance related to a given IP
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60 static private_spi_t* get_spi_private(spi_t *obj) {
<> 144:ef7eb2e8f9f7 61 static private_spi_t data0, data1;
<> 144:ef7eb2e8f9f7 62 /*
<> 144:ef7eb2e8f9f7 63 * Select which instance to give using the base
<> 144:ef7eb2e8f9f7 64 * address of registers
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 switch ((intptr_t)obj->spi) {
<> 144:ef7eb2e8f9f7 67 case SPI0_BASE:
<> 144:ef7eb2e8f9f7 68 return &data0;
<> 144:ef7eb2e8f9f7 69 case SPI1_BASE:
<> 144:ef7eb2e8f9f7 70 return &data1;
<> 144:ef7eb2e8f9f7 71 default:
<> 144:ef7eb2e8f9f7 72 error("SPI driver private data structure not found for this registers base address");
<> 144:ef7eb2e8f9f7 73 return (void*)0;
<> 144:ef7eb2e8f9f7 74 }
<> 144:ef7eb2e8f9f7 75 }
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 void spi_init(spi_t *obj, PinName mosi,
<> 144:ef7eb2e8f9f7 78 PinName miso, PinName sclk, PinName ssel) {
<> 144:ef7eb2e8f9f7 79 // determine the SPI to use
<> 144:ef7eb2e8f9f7 80 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 81 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 82 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 83 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 84 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 144:ef7eb2e8f9f7 85 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 144:ef7eb2e8f9f7 86 obj->spi = (SPI_TypeDef*)pinmap_merge(spi_data, spi_cntl);
<> 144:ef7eb2e8f9f7 87 if ((int)obj->spi == NC) {
<> 144:ef7eb2e8f9f7 88 error("SPI pinout mapping failed");
<> 144:ef7eb2e8f9f7 89 }
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /* Set default format and frequency */
<> 144:ef7eb2e8f9f7 92 if (ssel == NC) {
<> 144:ef7eb2e8f9f7 93 spi_format(obj, 8, 0, 0); // 8 bits, mode SPI_MSB, master
<> 144:ef7eb2e8f9f7 94 } else {
<> 144:ef7eb2e8f9f7 95 spi_format(obj, 8, 0, 1); // 8 bits, mode SPI_LSB, slave
<> 144:ef7eb2e8f9f7 96 }
<> 144:ef7eb2e8f9f7 97 spi_frequency(obj, 1562500);
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Pin out the spi pins */
<> 144:ef7eb2e8f9f7 100 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 101 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 102 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 103 if (ssel != NC) {
<> 144:ef7eb2e8f9f7 104 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 105 }
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /*
<> 144:ef7eb2e8f9f7 108 * Set desired enabled IRQs:
<> 144:ef7eb2e8f9f7 109 * MF: Mode Fail
<> 144:ef7eb2e8f9f7 110 * TF: TX FIFO Full
<> 144:ef7eb2e8f9f7 111 * TNF: TX FIFO Not Full
<> 144:ef7eb2e8f9f7 112 * RNE: RX FIFO Not Empty
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114 uint32_t irqs = (IRQ_ENABLE_MFE | IRQ_ENABLE_TFE
<> 144:ef7eb2e8f9f7 115 | IRQ_ENABLE_TNFE | IRQ_ENABLE_RNEE);
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /*
<> 144:ef7eb2e8f9f7 118 * Enable:
<> 144:ef7eb2e8f9f7 119 * - Master mode
<> 144:ef7eb2e8f9f7 120 * - Manual start mode
<> 144:ef7eb2e8f9f7 121 * - Manual chip select
<> 144:ef7eb2e8f9f7 122 * - Peripheral select decode
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124 obj->spi->CONFIG |= (CONFIG_MSEL | CONFIG_MSE
<> 144:ef7eb2e8f9f7 125 /*| CONFIG_MCSE | CONFIG_PSD*/);
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Set all peripheral select lines high - these should be unused */
<> 144:ef7eb2e8f9f7 128 obj->spi->CONFIG |= 0x00000; //CONFIG_PCSL;
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 obj->spi->IRQ_ENABLE = irqs;
<> 144:ef7eb2e8f9f7 131 obj->spi->IRQ_DISABLE = ~irqs;
<> 144:ef7eb2e8f9f7 132 obj->spi->SPI_ENABLE |= SPI_ENABLE_SPIE;
<> 144:ef7eb2e8f9f7 133 }
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 void spi_free(spi_t *obj) {
<> 144:ef7eb2e8f9f7 136 }
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 void spi_format(spi_t *obj, int bits, int mode, int slave) {
<> 144:ef7eb2e8f9f7 139 private_spi_t *private_spi = get_spi_private(obj);
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 obj->spi->SPI_ENABLE &= ~SPI_ENABLE_SPIE;
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /*
<> 144:ef7eb2e8f9f7 144 * The mbed API specifies 'bits' as being 4-16 per frame. This
<> 144:ef7eb2e8f9f7 145 * controller supports only 8 or 16 bit frames. Therefore we will
<> 144:ef7eb2e8f9f7 146 * assume 8 bits and, if anything larger is specified, we will use
<> 144:ef7eb2e8f9f7 147 * 16 bits.
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149 obj->spi->CONFIG &= ~CONFIG_TWS; /* 00 = 8 bit frame */
<> 144:ef7eb2e8f9f7 150 private_spi->size = 8;
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 if (bits > 8) {
<> 144:ef7eb2e8f9f7 153 switch (bits) {
<> 144:ef7eb2e8f9f7 154 case 16:
<> 144:ef7eb2e8f9f7 155 private_spi->size = 16;
<> 144:ef7eb2e8f9f7 156 break;
<> 144:ef7eb2e8f9f7 157 default:
<> 144:ef7eb2e8f9f7 158 obj->spi->CONFIG |= CONFIG_TWS_1; /* 01 = 16 bit frame */
<> 144:ef7eb2e8f9f7 159 break;
<> 144:ef7eb2e8f9f7 160 }
<> 144:ef7eb2e8f9f7 161 }
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 switch (mode) {
<> 144:ef7eb2e8f9f7 164 default:
<> 144:ef7eb2e8f9f7 165 case 0:
<> 144:ef7eb2e8f9f7 166 obj->spi->CONFIG &= ~CONFIG_CPOL;
<> 144:ef7eb2e8f9f7 167 obj->spi->CONFIG &= ~CONFIG_CPHA;
<> 144:ef7eb2e8f9f7 168 break;
<> 144:ef7eb2e8f9f7 169 case 1:
<> 144:ef7eb2e8f9f7 170 obj->spi->CONFIG &= ~CONFIG_CPOL;
<> 144:ef7eb2e8f9f7 171 obj->spi->CONFIG |= CONFIG_CPHA;
<> 144:ef7eb2e8f9f7 172 break;
<> 144:ef7eb2e8f9f7 173 case 2:
<> 144:ef7eb2e8f9f7 174 obj->spi->CONFIG |= CONFIG_CPOL;
<> 144:ef7eb2e8f9f7 175 obj->spi->CONFIG &= ~CONFIG_CPHA;
<> 144:ef7eb2e8f9f7 176 break;
<> 144:ef7eb2e8f9f7 177 case 3:
<> 144:ef7eb2e8f9f7 178 obj->spi->CONFIG |= CONFIG_CPOL;
<> 144:ef7eb2e8f9f7 179 obj->spi->CONFIG |= CONFIG_CPHA;
<> 144:ef7eb2e8f9f7 180 break;
<> 144:ef7eb2e8f9f7 181 }
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 obj->spi->SPI_ENABLE |= SPI_ENABLE_SPIE;
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 void spi_frequency(spi_t *obj, int hz) {
<> 144:ef7eb2e8f9f7 187 /*
<> 144:ef7eb2e8f9f7 188 * Valid frequencies are derived from a 25MHz peripheral clock.
<> 144:ef7eb2e8f9f7 189 * Frequency | Divisor | MBRD Value | Hz
<> 144:ef7eb2e8f9f7 190 * 12.0 MHz 2 000 12000000
<> 144:ef7eb2e8f9f7 191 * 6.0 MHz 4 001 6000000
<> 144:ef7eb2e8f9f7 192 * 3.0 MHz 8 010 3000000
<> 144:ef7eb2e8f9f7 193 * 1.5 MHz 16 011 1500000
<> 144:ef7eb2e8f9f7 194 * 750.0 KHz 32 100 750000
<> 144:ef7eb2e8f9f7 195 * 375.0 KHz 64 101 375000
<> 144:ef7eb2e8f9f7 196 * 187.500 KHz 128 110 187500
<> 144:ef7eb2e8f9f7 197 * 93.750 KHz 256 111 93750
<> 144:ef7eb2e8f9f7 198 */
<> 144:ef7eb2e8f9f7 199 int valid_frequencies[] = {12000000, 6000000, 3000000, 1500000,
<> 144:ef7eb2e8f9f7 200 750000, 375000, 187500, 93750};
<> 144:ef7eb2e8f9f7 201 uint16_t mbrd_value = 0;
<> 144:ef7eb2e8f9f7 202 uint32_t config = (obj->spi->CONFIG & ~CONFIG_MBRD);
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Store the index of the minimum supported frequency */
<> 144:ef7eb2e8f9f7 205 uint32_t index = 7;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 for (int i = 0; i < 8; i++) {
<> 144:ef7eb2e8f9f7 208 if (hz >= valid_frequencies[i]) {
<> 144:ef7eb2e8f9f7 209 /*
<> 144:ef7eb2e8f9f7 210 * Store the index of the closest lower or equal supported
<> 144:ef7eb2e8f9f7 211 * frequency.
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 index = i;
<> 144:ef7eb2e8f9f7 214 break;
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 mbrd_value++;
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /*
<> 144:ef7eb2e8f9f7 221 * Set the selected frequency. If the frequency is below the minimum
<> 144:ef7eb2e8f9f7 222 * supported the driver sets the minumum.
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 config |= index << CONFIG_MBRD_SHIFT;
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /*
<> 144:ef7eb2e8f9f7 227 * If the specified frequency didn't match any of the valid frequencies
<> 144:ef7eb2e8f9f7 228 * then leave CONFIG_MBRD to the closest lower frequency supported.
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 obj->spi->CONFIG = config;
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 int spi_master_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 234 private_spi_t *private_spi = get_spi_private(obj);
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 int data = 0;
<> 144:ef7eb2e8f9f7 237 if(private_spi->size == 16) {
<> 144:ef7eb2e8f9f7 238 obj->spi->TX_DATA = (uint8_t)((value >> 8) & TX_DATA_TDATA);
<> 144:ef7eb2e8f9f7 239 obj->spi->TX_DATA = (uint8_t)(value & TX_DATA_TDATA);
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /* Manually trigger start */
<> 144:ef7eb2e8f9f7 242 obj->spi->CONFIG |= CONFIG_MSC;
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 while(!(obj->spi->IRQ_STATUS & IRQ_STATUS_TNF))
<> 144:ef7eb2e8f9f7 245 continue;
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 data = (obj->spi->RX_DATA & RX_DATA_RDATA) << 8;
<> 144:ef7eb2e8f9f7 248 data = data | (obj->spi->RX_DATA & RX_DATA_RDATA);
<> 144:ef7eb2e8f9f7 249 } else {
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 obj->spi->TX_DATA = (uint16_t)(value & TX_DATA_TDATA);
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Manually trigger start */
<> 144:ef7eb2e8f9f7 254 obj->spi->CONFIG |= CONFIG_MSC;
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 while(!(obj->spi->IRQ_STATUS & IRQ_STATUS_TNF))
<> 144:ef7eb2e8f9f7 257 continue;
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 data = obj->spi->RX_DATA & RX_DATA_RDATA;
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 return data;
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
AnnaBridge 167:e84263d55307 265 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
AnnaBridge 167:e84263d55307 266 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 167:e84263d55307 267
AnnaBridge 167:e84263d55307 268 for (int i = 0; i < total; i++) {
AnnaBridge 167:e84263d55307 269 char out = (i < tx_length) ? tx_buffer[i] : 0xff;
AnnaBridge 167:e84263d55307 270 char in = spi_master_write(obj, out);
AnnaBridge 167:e84263d55307 271 if (i < rx_length) {
AnnaBridge 167:e84263d55307 272 rx_buffer[i] = in;
AnnaBridge 167:e84263d55307 273 }
AnnaBridge 167:e84263d55307 274 }
AnnaBridge 167:e84263d55307 275
AnnaBridge 167:e84263d55307 276 return total;
AnnaBridge 167:e84263d55307 277 }
AnnaBridge 167:e84263d55307 278
<> 144:ef7eb2e8f9f7 279 uint8_t spi_get_module(spi_t *obj) {
<> 144:ef7eb2e8f9f7 280 return obj->spi->MID;
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 int spi_busy(spi_t *obj) {
<> 144:ef7eb2e8f9f7 284 return 0;
<> 144:ef7eb2e8f9f7 285 }