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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 83:a036322b8637
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f7xx_hal_adc.h |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.0.1 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 25-June-2015 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file of ADC HAL extension module. |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * @attention |
| bogdanm | 0:9b334a45a8ff | 10 | * |
| bogdanm | 0:9b334a45a8ff | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 12 | * |
| bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 23 | * |
| bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 34 | * |
| bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 36 | */ |
| bogdanm | 0:9b334a45a8ff | 37 | |
| bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32F7xx_ADC_H |
| bogdanm | 0:9b334a45a8ff | 40 | #define __STM32F7xx_ADC_H |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 44 | #endif |
| bogdanm | 0:9b334a45a8ff | 45 | |
| bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 47 | #include "stm32f7xx_hal_def.h" |
| bogdanm | 0:9b334a45a8ff | 48 | |
| bogdanm | 0:9b334a45a8ff | 49 | /** @addtogroup STM32F7xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 50 | * @{ |
| bogdanm | 0:9b334a45a8ff | 51 | */ |
| bogdanm | 0:9b334a45a8ff | 52 | |
| bogdanm | 0:9b334a45a8ff | 53 | /** @addtogroup ADC |
| bogdanm | 0:9b334a45a8ff | 54 | * @{ |
| bogdanm | 0:9b334a45a8ff | 55 | */ |
| bogdanm | 0:9b334a45a8ff | 56 | |
| bogdanm | 0:9b334a45a8ff | 57 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 58 | /** @defgroup ADC_Exported_Types ADC Exported Types |
| bogdanm | 0:9b334a45a8ff | 59 | * @{ |
| bogdanm | 0:9b334a45a8ff | 60 | */ |
| bogdanm | 0:9b334a45a8ff | 61 | |
| bogdanm | 0:9b334a45a8ff | 62 | /** |
| bogdanm | 0:9b334a45a8ff | 63 | * @brief HAL State structures definition |
| bogdanm | 0:9b334a45a8ff | 64 | */ |
| bogdanm | 0:9b334a45a8ff | 65 | typedef enum |
| bogdanm | 0:9b334a45a8ff | 66 | { |
| bogdanm | 0:9b334a45a8ff | 67 | HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ |
| bogdanm | 0:9b334a45a8ff | 68 | HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ |
| bogdanm | 0:9b334a45a8ff | 69 | HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
| bogdanm | 0:9b334a45a8ff | 70 | HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ |
| bogdanm | 0:9b334a45a8ff | 71 | HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */ |
| bogdanm | 0:9b334a45a8ff | 72 | HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */ |
| bogdanm | 0:9b334a45a8ff | 73 | HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
| bogdanm | 0:9b334a45a8ff | 74 | HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ |
| bogdanm | 0:9b334a45a8ff | 75 | HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ |
| bogdanm | 0:9b334a45a8ff | 76 | HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */ |
| bogdanm | 0:9b334a45a8ff | 77 | HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */ |
| bogdanm | 0:9b334a45a8ff | 78 | HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */ |
| bogdanm | 0:9b334a45a8ff | 79 | HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */ |
| bogdanm | 0:9b334a45a8ff | 80 | |
| bogdanm | 0:9b334a45a8ff | 81 | }HAL_ADC_StateTypeDef; |
| bogdanm | 0:9b334a45a8ff | 82 | |
| bogdanm | 0:9b334a45a8ff | 83 | /** |
| bogdanm | 0:9b334a45a8ff | 84 | * @brief ADC Init structure definition |
| bogdanm | 0:9b334a45a8ff | 85 | */ |
| bogdanm | 0:9b334a45a8ff | 86 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 87 | { |
| bogdanm | 0:9b334a45a8ff | 88 | uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for |
| bogdanm | 0:9b334a45a8ff | 89 | all the ADCs. |
| bogdanm | 0:9b334a45a8ff | 90 | This parameter can be a value of @ref ADC_ClockPrescaler */ |
| bogdanm | 0:9b334a45a8ff | 91 | uint32_t Resolution; /*!< Configures the ADC resolution dual mode. |
| bogdanm | 0:9b334a45a8ff | 92 | This parameter can be a value of @ref ADC_Resolution */ |
| bogdanm | 0:9b334a45a8ff | 93 | uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. |
| bogdanm | 0:9b334a45a8ff | 94 | This parameter can be a value of @ref ADC_data_align */ |
| bogdanm | 0:9b334a45a8ff | 95 | uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or |
| bogdanm | 0:9b334a45a8ff | 96 | Single (one channel) mode. |
| bogdanm | 0:9b334a45a8ff | 97 | This parameter can be set to ENABLE or DISABLE */ |
| bogdanm | 0:9b334a45a8ff | 98 | uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set |
| bogdanm | 0:9b334a45a8ff | 99 | at the end of single channel conversion or at the end of all conversions. |
| bogdanm | 0:9b334a45a8ff | 100 | This parameter can be a value of @ref ADC_EOCSelection */ |
| bogdanm | 0:9b334a45a8ff | 101 | uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode. |
| bogdanm | 0:9b334a45a8ff | 102 | This parameter can be set to ENABLE or DISABLE. */ |
| bogdanm | 0:9b334a45a8ff | 103 | uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode. |
| bogdanm | 0:9b334a45a8ff | 104 | This parameter can be set to ENABLE or DISABLE. */ |
| bogdanm | 0:9b334a45a8ff | 105 | uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for |
| bogdanm | 0:9b334a45a8ff | 106 | regular channel group. |
| bogdanm | 0:9b334a45a8ff | 107 | This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ |
| bogdanm | 0:9b334a45a8ff | 108 | uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not |
| bogdanm | 0:9b334a45a8ff | 109 | for regular channels. |
| bogdanm | 0:9b334a45a8ff | 110 | This parameter can be set to ENABLE or DISABLE. */ |
| bogdanm | 0:9b334a45a8ff | 111 | uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done |
| bogdanm | 0:9b334a45a8ff | 112 | using the sequencer for regular channel group. |
| bogdanm | 0:9b334a45a8ff | 113 | This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ |
| bogdanm | 0:9b334a45a8ff | 114 | uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. |
| bogdanm | 0:9b334a45a8ff | 115 | If set to ADC_SOFTWARE_START, external triggers are disabled. |
| bogdanm | 0:9b334a45a8ff | 116 | This parameter can be a value of @ref ADC_External_trigger_Source_Regular |
| bogdanm | 0:9b334a45a8ff | 117 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 0:9b334a45a8ff | 118 | uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. |
| bogdanm | 0:9b334a45a8ff | 119 | If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. |
| bogdanm | 0:9b334a45a8ff | 120 | This parameter can be a value of @ref ADC_External_trigger_edge_Regular |
| bogdanm | 0:9b334a45a8ff | 121 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 0:9b334a45a8ff | 122 | }ADC_InitTypeDef; |
| bogdanm | 0:9b334a45a8ff | 123 | |
| bogdanm | 0:9b334a45a8ff | 124 | /** |
| bogdanm | 0:9b334a45a8ff | 125 | * @brief ADC handle Structure definition |
| bogdanm | 0:9b334a45a8ff | 126 | */ |
| bogdanm | 0:9b334a45a8ff | 127 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 128 | { |
| bogdanm | 0:9b334a45a8ff | 129 | ADC_TypeDef *Instance; /*!< Register base address */ |
| bogdanm | 0:9b334a45a8ff | 130 | |
| bogdanm | 0:9b334a45a8ff | 131 | ADC_InitTypeDef Init; /*!< ADC required parameters */ |
| bogdanm | 0:9b334a45a8ff | 132 | |
| bogdanm | 0:9b334a45a8ff | 133 | __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ |
| bogdanm | 0:9b334a45a8ff | 134 | |
| bogdanm | 0:9b334a45a8ff | 135 | DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
| bogdanm | 0:9b334a45a8ff | 136 | |
| bogdanm | 0:9b334a45a8ff | 137 | HAL_LockTypeDef Lock; /*!< ADC locking object */ |
| bogdanm | 0:9b334a45a8ff | 138 | |
| bogdanm | 0:9b334a45a8ff | 139 | __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ |
| bogdanm | 0:9b334a45a8ff | 140 | |
| bogdanm | 0:9b334a45a8ff | 141 | __IO uint32_t ErrorCode; /*!< ADC Error code */ |
| bogdanm | 0:9b334a45a8ff | 142 | }ADC_HandleTypeDef; |
| bogdanm | 0:9b334a45a8ff | 143 | |
| bogdanm | 0:9b334a45a8ff | 144 | /** |
| bogdanm | 0:9b334a45a8ff | 145 | * @brief ADC Configuration regular Channel structure definition |
| bogdanm | 0:9b334a45a8ff | 146 | */ |
| bogdanm | 0:9b334a45a8ff | 147 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 148 | { |
| bogdanm | 0:9b334a45a8ff | 149 | uint32_t Channel; /*!< The ADC channel to configure. |
| bogdanm | 0:9b334a45a8ff | 150 | This parameter can be a value of @ref ADC_channels */ |
| bogdanm | 0:9b334a45a8ff | 151 | uint32_t Rank; /*!< The rank in the regular group sequencer. |
| bogdanm | 0:9b334a45a8ff | 152 | This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ |
| bogdanm | 0:9b334a45a8ff | 153 | uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel. |
| bogdanm | 0:9b334a45a8ff | 154 | This parameter can be a value of @ref ADC_sampling_times */ |
| bogdanm | 0:9b334a45a8ff | 155 | uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ |
| bogdanm | 0:9b334a45a8ff | 156 | }ADC_ChannelConfTypeDef; |
| bogdanm | 0:9b334a45a8ff | 157 | |
| bogdanm | 0:9b334a45a8ff | 158 | /** |
| bogdanm | 0:9b334a45a8ff | 159 | * @brief ADC Configuration multi-mode structure definition |
| bogdanm | 0:9b334a45a8ff | 160 | */ |
| bogdanm | 0:9b334a45a8ff | 161 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 162 | { |
| bogdanm | 0:9b334a45a8ff | 163 | uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. |
| bogdanm | 0:9b334a45a8ff | 164 | This parameter can be a value of @ref ADC_analog_watchdog_selection */ |
| bogdanm | 0:9b334a45a8ff | 165 | uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| bogdanm | 0:9b334a45a8ff | 166 | This parameter must be a 12-bit value. */ |
| bogdanm | 0:9b334a45a8ff | 167 | uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| bogdanm | 0:9b334a45a8ff | 168 | This parameter must be a 12-bit value. */ |
| bogdanm | 0:9b334a45a8ff | 169 | uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. |
| bogdanm | 0:9b334a45a8ff | 170 | This parameter has an effect only if watchdog mode is configured on single channel |
| bogdanm | 0:9b334a45a8ff | 171 | This parameter can be a value of @ref ADC_channels */ |
| bogdanm | 0:9b334a45a8ff | 172 | uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured |
| bogdanm | 0:9b334a45a8ff | 173 | is interrupt mode or in polling mode. |
| bogdanm | 0:9b334a45a8ff | 174 | This parameter can be set to ENABLE or DISABLE */ |
| bogdanm | 0:9b334a45a8ff | 175 | uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ |
| bogdanm | 0:9b334a45a8ff | 176 | }ADC_AnalogWDGConfTypeDef; |
| bogdanm | 0:9b334a45a8ff | 177 | /** |
| bogdanm | 0:9b334a45a8ff | 178 | * @} |
| bogdanm | 0:9b334a45a8ff | 179 | */ |
| bogdanm | 0:9b334a45a8ff | 180 | |
| bogdanm | 0:9b334a45a8ff | 181 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 182 | |
| bogdanm | 0:9b334a45a8ff | 183 | /** @defgroup ADC_Exported_Constants ADC Exported Constants |
| bogdanm | 0:9b334a45a8ff | 184 | * @{ |
| bogdanm | 0:9b334a45a8ff | 185 | */ |
| bogdanm | 0:9b334a45a8ff | 186 | |
| bogdanm | 0:9b334a45a8ff | 187 | |
| bogdanm | 0:9b334a45a8ff | 188 | /** @defgroup ADC_Error_Code ADC Error Code |
| bogdanm | 0:9b334a45a8ff | 189 | * @{ |
| bogdanm | 0:9b334a45a8ff | 190 | */ |
| bogdanm | 0:9b334a45a8ff | 191 | |
| bogdanm | 0:9b334a45a8ff | 192 | #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ |
| bogdanm | 0:9b334a45a8ff | 193 | #define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */ |
| bogdanm | 0:9b334a45a8ff | 194 | #define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */ |
| bogdanm | 0:9b334a45a8ff | 195 | /** |
| bogdanm | 0:9b334a45a8ff | 196 | * @} |
| bogdanm | 0:9b334a45a8ff | 197 | */ |
| bogdanm | 0:9b334a45a8ff | 198 | |
| bogdanm | 0:9b334a45a8ff | 199 | |
| bogdanm | 0:9b334a45a8ff | 200 | /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler |
| bogdanm | 0:9b334a45a8ff | 201 | * @{ |
| bogdanm | 0:9b334a45a8ff | 202 | */ |
| bogdanm | 0:9b334a45a8ff | 203 | #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 204 | #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) |
| bogdanm | 0:9b334a45a8ff | 205 | #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) |
| bogdanm | 0:9b334a45a8ff | 206 | #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) |
| bogdanm | 0:9b334a45a8ff | 207 | /** |
| bogdanm | 0:9b334a45a8ff | 208 | * @} |
| bogdanm | 0:9b334a45a8ff | 209 | */ |
| bogdanm | 0:9b334a45a8ff | 210 | |
| bogdanm | 0:9b334a45a8ff | 211 | /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases |
| bogdanm | 0:9b334a45a8ff | 212 | * @{ |
| bogdanm | 0:9b334a45a8ff | 213 | */ |
| bogdanm | 0:9b334a45a8ff | 214 | #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 215 | #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) |
| bogdanm | 0:9b334a45a8ff | 216 | #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) |
| bogdanm | 0:9b334a45a8ff | 217 | #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) |
| bogdanm | 0:9b334a45a8ff | 218 | #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) |
| bogdanm | 0:9b334a45a8ff | 219 | #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) |
| bogdanm | 0:9b334a45a8ff | 220 | #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) |
| bogdanm | 0:9b334a45a8ff | 221 | #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) |
| bogdanm | 0:9b334a45a8ff | 222 | #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) |
| bogdanm | 0:9b334a45a8ff | 223 | #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) |
| bogdanm | 0:9b334a45a8ff | 224 | #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) |
| bogdanm | 0:9b334a45a8ff | 225 | #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) |
| bogdanm | 0:9b334a45a8ff | 226 | #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) |
| bogdanm | 0:9b334a45a8ff | 227 | #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) |
| bogdanm | 0:9b334a45a8ff | 228 | #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) |
| bogdanm | 0:9b334a45a8ff | 229 | #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) |
| bogdanm | 0:9b334a45a8ff | 230 | /** |
| bogdanm | 0:9b334a45a8ff | 231 | * @} |
| bogdanm | 0:9b334a45a8ff | 232 | */ |
| bogdanm | 0:9b334a45a8ff | 233 | |
| bogdanm | 0:9b334a45a8ff | 234 | /** @defgroup ADC_Resolution ADC Resolution |
| bogdanm | 0:9b334a45a8ff | 235 | * @{ |
| bogdanm | 0:9b334a45a8ff | 236 | */ |
| bogdanm | 0:9b334a45a8ff | 237 | #define ADC_RESOLUTION_12B ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 238 | #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) |
| bogdanm | 0:9b334a45a8ff | 239 | #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) |
| bogdanm | 0:9b334a45a8ff | 240 | #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) |
| bogdanm | 0:9b334a45a8ff | 241 | /** |
| bogdanm | 0:9b334a45a8ff | 242 | * @} |
| bogdanm | 0:9b334a45a8ff | 243 | */ |
| bogdanm | 0:9b334a45a8ff | 244 | |
| bogdanm | 0:9b334a45a8ff | 245 | /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular |
| bogdanm | 0:9b334a45a8ff | 246 | * @{ |
| bogdanm | 0:9b334a45a8ff | 247 | */ |
| bogdanm | 0:9b334a45a8ff | 248 | #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 249 | #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) |
| bogdanm | 0:9b334a45a8ff | 250 | #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) |
| bogdanm | 0:9b334a45a8ff | 251 | #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) |
| bogdanm | 0:9b334a45a8ff | 252 | /** |
| bogdanm | 0:9b334a45a8ff | 253 | * @} |
| bogdanm | 0:9b334a45a8ff | 254 | */ |
| bogdanm | 0:9b334a45a8ff | 255 | |
| bogdanm | 0:9b334a45a8ff | 256 | /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular |
| bogdanm | 0:9b334a45a8ff | 257 | * @{ |
| bogdanm | 0:9b334a45a8ff | 258 | */ |
| bogdanm | 0:9b334a45a8ff | 259 | /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */ |
| bogdanm | 0:9b334a45a8ff | 260 | /* compatibility with other STM32 devices. */ |
| bogdanm | 0:9b334a45a8ff | 261 | #define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 262 | #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) |
| bogdanm | 0:9b334a45a8ff | 263 | #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) |
| bogdanm | 0:9b334a45a8ff | 264 | #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
| bogdanm | 0:9b334a45a8ff | 265 | #define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2) |
| bogdanm | 0:9b334a45a8ff | 266 | #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) |
| bogdanm | 0:9b334a45a8ff | 267 | #define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) |
| bogdanm | 0:9b334a45a8ff | 268 | #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
| bogdanm | 0:9b334a45a8ff | 269 | #define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3) |
| bogdanm | 0:9b334a45a8ff | 270 | #define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) |
| bogdanm | 0:9b334a45a8ff | 271 | #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) |
| bogdanm | 0:9b334a45a8ff | 272 | #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
| bogdanm | 0:9b334a45a8ff | 273 | #define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) |
| bogdanm | 0:9b334a45a8ff | 274 | #define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) |
| bogdanm | 0:9b334a45a8ff | 275 | |
| bogdanm | 0:9b334a45a8ff | 276 | #define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL) |
| bogdanm | 0:9b334a45a8ff | 277 | #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1) |
| bogdanm | 0:9b334a45a8ff | 278 | /** |
| bogdanm | 0:9b334a45a8ff | 279 | * @} |
| bogdanm | 0:9b334a45a8ff | 280 | */ |
| bogdanm | 0:9b334a45a8ff | 281 | |
| bogdanm | 0:9b334a45a8ff | 282 | /** @defgroup ADC_data_align ADC Data Align |
| bogdanm | 0:9b334a45a8ff | 283 | * @{ |
| bogdanm | 0:9b334a45a8ff | 284 | */ |
| bogdanm | 0:9b334a45a8ff | 285 | #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 286 | #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) |
| bogdanm | 0:9b334a45a8ff | 287 | /** |
| bogdanm | 0:9b334a45a8ff | 288 | * @} |
| bogdanm | 0:9b334a45a8ff | 289 | */ |
| bogdanm | 0:9b334a45a8ff | 290 | |
| bogdanm | 0:9b334a45a8ff | 291 | /** @defgroup ADC_channels ADC Common Channels |
| bogdanm | 0:9b334a45a8ff | 292 | * @{ |
| bogdanm | 0:9b334a45a8ff | 293 | */ |
| bogdanm | 0:9b334a45a8ff | 294 | #define ADC_CHANNEL_0 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 295 | #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) |
| bogdanm | 0:9b334a45a8ff | 296 | #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) |
| bogdanm | 0:9b334a45a8ff | 297 | #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
| bogdanm | 0:9b334a45a8ff | 298 | #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) |
| bogdanm | 0:9b334a45a8ff | 299 | #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) |
| bogdanm | 0:9b334a45a8ff | 300 | #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) |
| bogdanm | 0:9b334a45a8ff | 301 | #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
| bogdanm | 0:9b334a45a8ff | 302 | #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) |
| bogdanm | 0:9b334a45a8ff | 303 | #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) |
| bogdanm | 0:9b334a45a8ff | 304 | #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) |
| bogdanm | 0:9b334a45a8ff | 305 | #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
| bogdanm | 0:9b334a45a8ff | 306 | #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) |
| bogdanm | 0:9b334a45a8ff | 307 | #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) |
| bogdanm | 0:9b334a45a8ff | 308 | #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) |
| bogdanm | 0:9b334a45a8ff | 309 | #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
| bogdanm | 0:9b334a45a8ff | 310 | #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) |
| bogdanm | 0:9b334a45a8ff | 311 | #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) |
| bogdanm | 0:9b334a45a8ff | 312 | #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) |
| bogdanm | 0:9b334a45a8ff | 313 | |
| bogdanm | 0:9b334a45a8ff | 314 | #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) |
| bogdanm | 0:9b334a45a8ff | 315 | #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) |
| bogdanm | 0:9b334a45a8ff | 316 | /** |
| bogdanm | 0:9b334a45a8ff | 317 | * @} |
| bogdanm | 0:9b334a45a8ff | 318 | */ |
| bogdanm | 0:9b334a45a8ff | 319 | |
| bogdanm | 0:9b334a45a8ff | 320 | /** @defgroup ADC_sampling_times ADC Sampling Times |
| bogdanm | 0:9b334a45a8ff | 321 | * @{ |
| bogdanm | 0:9b334a45a8ff | 322 | */ |
| bogdanm | 0:9b334a45a8ff | 323 | #define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 324 | #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) |
| bogdanm | 0:9b334a45a8ff | 325 | #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) |
| bogdanm | 0:9b334a45a8ff | 326 | #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) |
| bogdanm | 0:9b334a45a8ff | 327 | #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) |
| bogdanm | 0:9b334a45a8ff | 328 | #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) |
| bogdanm | 0:9b334a45a8ff | 329 | #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) |
| bogdanm | 0:9b334a45a8ff | 330 | #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) |
| bogdanm | 0:9b334a45a8ff | 331 | /** |
| bogdanm | 0:9b334a45a8ff | 332 | * @} |
| bogdanm | 0:9b334a45a8ff | 333 | */ |
| bogdanm | 0:9b334a45a8ff | 334 | |
| bogdanm | 0:9b334a45a8ff | 335 | /** @defgroup ADC_EOCSelection ADC EOC Selection |
| bogdanm | 0:9b334a45a8ff | 336 | * @{ |
| bogdanm | 0:9b334a45a8ff | 337 | */ |
| bogdanm | 0:9b334a45a8ff | 338 | #define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 339 | #define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001) |
| bogdanm | 0:9b334a45a8ff | 340 | #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */ |
| bogdanm | 0:9b334a45a8ff | 341 | /** |
| bogdanm | 0:9b334a45a8ff | 342 | * @} |
| bogdanm | 0:9b334a45a8ff | 343 | */ |
| bogdanm | 0:9b334a45a8ff | 344 | |
| bogdanm | 0:9b334a45a8ff | 345 | /** @defgroup ADC_Event_type ADC Event Type |
| bogdanm | 0:9b334a45a8ff | 346 | * @{ |
| bogdanm | 0:9b334a45a8ff | 347 | */ |
| bogdanm | 0:9b334a45a8ff | 348 | #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) |
| bogdanm | 0:9b334a45a8ff | 349 | #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) |
| bogdanm | 0:9b334a45a8ff | 350 | /** |
| bogdanm | 0:9b334a45a8ff | 351 | * @} |
| bogdanm | 0:9b334a45a8ff | 352 | */ |
| bogdanm | 0:9b334a45a8ff | 353 | |
| bogdanm | 0:9b334a45a8ff | 354 | /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection |
| bogdanm | 0:9b334a45a8ff | 355 | * @{ |
| bogdanm | 0:9b334a45a8ff | 356 | */ |
| bogdanm | 0:9b334a45a8ff | 357 | #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) |
| bogdanm | 0:9b334a45a8ff | 358 | #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) |
| bogdanm | 0:9b334a45a8ff | 359 | #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
| bogdanm | 0:9b334a45a8ff | 360 | #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) |
| bogdanm | 0:9b334a45a8ff | 361 | #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) |
| bogdanm | 0:9b334a45a8ff | 362 | #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
| bogdanm | 0:9b334a45a8ff | 363 | #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 364 | /** |
| bogdanm | 0:9b334a45a8ff | 365 | * @} |
| bogdanm | 0:9b334a45a8ff | 366 | */ |
| bogdanm | 0:9b334a45a8ff | 367 | |
| bogdanm | 0:9b334a45a8ff | 368 | /** @defgroup ADC_interrupts_definition ADC Interrupts Definition |
| bogdanm | 0:9b334a45a8ff | 369 | * @{ |
| bogdanm | 0:9b334a45a8ff | 370 | */ |
| bogdanm | 0:9b334a45a8ff | 371 | #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) |
| bogdanm | 0:9b334a45a8ff | 372 | #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) |
| bogdanm | 0:9b334a45a8ff | 373 | #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) |
| bogdanm | 0:9b334a45a8ff | 374 | #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) |
| bogdanm | 0:9b334a45a8ff | 375 | /** |
| bogdanm | 0:9b334a45a8ff | 376 | * @} |
| bogdanm | 0:9b334a45a8ff | 377 | */ |
| bogdanm | 0:9b334a45a8ff | 378 | |
| bogdanm | 0:9b334a45a8ff | 379 | /** @defgroup ADC_flags_definition ADC Flags Definition |
| bogdanm | 0:9b334a45a8ff | 380 | * @{ |
| bogdanm | 0:9b334a45a8ff | 381 | */ |
| bogdanm | 0:9b334a45a8ff | 382 | #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) |
| bogdanm | 0:9b334a45a8ff | 383 | #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) |
| bogdanm | 0:9b334a45a8ff | 384 | #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) |
| bogdanm | 0:9b334a45a8ff | 385 | #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) |
| bogdanm | 0:9b334a45a8ff | 386 | #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) |
| bogdanm | 0:9b334a45a8ff | 387 | #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) |
| bogdanm | 0:9b334a45a8ff | 388 | /** |
| bogdanm | 0:9b334a45a8ff | 389 | * @} |
| bogdanm | 0:9b334a45a8ff | 390 | */ |
| bogdanm | 0:9b334a45a8ff | 391 | |
| bogdanm | 0:9b334a45a8ff | 392 | /** @defgroup ADC_channels_type ADC Channels Type |
| bogdanm | 0:9b334a45a8ff | 393 | * @{ |
| bogdanm | 0:9b334a45a8ff | 394 | */ |
| bogdanm | 0:9b334a45a8ff | 395 | #define ADC_ALL_CHANNELS ((uint32_t)0x00000001) |
| bogdanm | 0:9b334a45a8ff | 396 | #define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */ |
| bogdanm | 0:9b334a45a8ff | 397 | #define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */ |
| bogdanm | 0:9b334a45a8ff | 398 | /** |
| bogdanm | 0:9b334a45a8ff | 399 | * @} |
| bogdanm | 0:9b334a45a8ff | 400 | */ |
| bogdanm | 0:9b334a45a8ff | 401 | |
| bogdanm | 0:9b334a45a8ff | 402 | /** |
| bogdanm | 0:9b334a45a8ff | 403 | * @} |
| bogdanm | 0:9b334a45a8ff | 404 | */ |
| bogdanm | 0:9b334a45a8ff | 405 | |
| bogdanm | 0:9b334a45a8ff | 406 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 407 | /** @defgroup ADC_Exported_Macros ADC Exported Macros |
| bogdanm | 0:9b334a45a8ff | 408 | * @{ |
| bogdanm | 0:9b334a45a8ff | 409 | */ |
| bogdanm | 0:9b334a45a8ff | 410 | |
| bogdanm | 0:9b334a45a8ff | 411 | /** @brief Reset ADC handle state |
| bogdanm | 0:9b334a45a8ff | 412 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 413 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 414 | */ |
| bogdanm | 0:9b334a45a8ff | 415 | #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
| bogdanm | 0:9b334a45a8ff | 416 | |
| bogdanm | 0:9b334a45a8ff | 417 | /** |
| bogdanm | 0:9b334a45a8ff | 418 | * @brief Enable the ADC peripheral. |
| bogdanm | 0:9b334a45a8ff | 419 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 420 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 421 | */ |
| bogdanm | 0:9b334a45a8ff | 422 | #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) |
| bogdanm | 0:9b334a45a8ff | 423 | |
| bogdanm | 0:9b334a45a8ff | 424 | /** |
| bogdanm | 0:9b334a45a8ff | 425 | * @brief Disable the ADC peripheral. |
| bogdanm | 0:9b334a45a8ff | 426 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 427 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 428 | */ |
| bogdanm | 0:9b334a45a8ff | 429 | #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) |
| bogdanm | 0:9b334a45a8ff | 430 | |
| bogdanm | 0:9b334a45a8ff | 431 | /** |
| bogdanm | 0:9b334a45a8ff | 432 | * @brief Enable the ADC end of conversion interrupt. |
| bogdanm | 0:9b334a45a8ff | 433 | * @param __HANDLE__: specifies the ADC Handle. |
| bogdanm | 0:9b334a45a8ff | 434 | * @param __INTERRUPT__: ADC Interrupt. |
| bogdanm | 0:9b334a45a8ff | 435 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 436 | */ |
| bogdanm | 0:9b334a45a8ff | 437 | #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 438 | |
| bogdanm | 0:9b334a45a8ff | 439 | /** |
| bogdanm | 0:9b334a45a8ff | 440 | * @brief Disable the ADC end of conversion interrupt. |
| bogdanm | 0:9b334a45a8ff | 441 | * @param __HANDLE__: specifies the ADC Handle. |
| bogdanm | 0:9b334a45a8ff | 442 | * @param __INTERRUPT__: ADC interrupt. |
| bogdanm | 0:9b334a45a8ff | 443 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 444 | */ |
| bogdanm | 0:9b334a45a8ff | 445 | #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 446 | |
| bogdanm | 0:9b334a45a8ff | 447 | /** @brief Check if the specified ADC interrupt source is enabled or disabled. |
| bogdanm | 0:9b334a45a8ff | 448 | * @param __HANDLE__: specifies the ADC Handle. |
| bogdanm | 0:9b334a45a8ff | 449 | * @param __INTERRUPT__: specifies the ADC interrupt source to check. |
| bogdanm | 0:9b334a45a8ff | 450 | * @retval The new state of __IT__ (TRUE or FALSE). |
| bogdanm | 0:9b334a45a8ff | 451 | */ |
| bogdanm | 0:9b334a45a8ff | 452 | #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 453 | |
| bogdanm | 0:9b334a45a8ff | 454 | /** |
| bogdanm | 0:9b334a45a8ff | 455 | * @brief Clear the ADC's pending flags. |
| bogdanm | 0:9b334a45a8ff | 456 | * @param __HANDLE__: specifies the ADC Handle. |
| bogdanm | 0:9b334a45a8ff | 457 | * @param __FLAG__: ADC flag. |
| bogdanm | 0:9b334a45a8ff | 458 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 459 | */ |
| bogdanm | 0:9b334a45a8ff | 460 | #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 461 | |
| bogdanm | 0:9b334a45a8ff | 462 | /** |
| bogdanm | 0:9b334a45a8ff | 463 | * @brief Get the selected ADC's flag status. |
| bogdanm | 0:9b334a45a8ff | 464 | * @param __HANDLE__: specifies the ADC Handle. |
| bogdanm | 0:9b334a45a8ff | 465 | * @param __FLAG__: ADC flag. |
| bogdanm | 0:9b334a45a8ff | 466 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 467 | */ |
| bogdanm | 0:9b334a45a8ff | 468 | #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 469 | |
| bogdanm | 0:9b334a45a8ff | 470 | /** |
| bogdanm | 0:9b334a45a8ff | 471 | * @} |
| bogdanm | 0:9b334a45a8ff | 472 | */ |
| bogdanm | 0:9b334a45a8ff | 473 | |
| bogdanm | 0:9b334a45a8ff | 474 | /* Include ADC HAL Extension module */ |
| bogdanm | 0:9b334a45a8ff | 475 | #include "stm32f7xx_hal_adc_ex.h" |
| bogdanm | 0:9b334a45a8ff | 476 | |
| bogdanm | 0:9b334a45a8ff | 477 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 478 | /** @addtogroup ADC_Exported_Functions |
| bogdanm | 0:9b334a45a8ff | 479 | * @{ |
| bogdanm | 0:9b334a45a8ff | 480 | */ |
| bogdanm | 0:9b334a45a8ff | 481 | |
| bogdanm | 0:9b334a45a8ff | 482 | /** @addtogroup ADC_Exported_Functions_Group1 |
| bogdanm | 0:9b334a45a8ff | 483 | * @{ |
| bogdanm | 0:9b334a45a8ff | 484 | */ |
| bogdanm | 0:9b334a45a8ff | 485 | /* Initialization/de-initialization functions ***********************************/ |
| bogdanm | 0:9b334a45a8ff | 486 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 487 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
| bogdanm | 0:9b334a45a8ff | 488 | void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 489 | void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 490 | /** |
| bogdanm | 0:9b334a45a8ff | 491 | * @} |
| bogdanm | 0:9b334a45a8ff | 492 | */ |
| bogdanm | 0:9b334a45a8ff | 493 | |
| bogdanm | 0:9b334a45a8ff | 494 | /** @addtogroup ADC_Exported_Functions_Group2 |
| bogdanm | 0:9b334a45a8ff | 495 | * @{ |
| bogdanm | 0:9b334a45a8ff | 496 | */ |
| bogdanm | 0:9b334a45a8ff | 497 | /* I/O operation functions ******************************************************/ |
| bogdanm | 0:9b334a45a8ff | 498 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 499 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 500 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 501 | |
| bogdanm | 0:9b334a45a8ff | 502 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 503 | |
| bogdanm | 0:9b334a45a8ff | 504 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 505 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 506 | |
| bogdanm | 0:9b334a45a8ff | 507 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 508 | |
| bogdanm | 0:9b334a45a8ff | 509 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
| bogdanm | 0:9b334a45a8ff | 510 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 511 | |
| bogdanm | 0:9b334a45a8ff | 512 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 513 | |
| bogdanm | 0:9b334a45a8ff | 514 | void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 515 | void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 516 | void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 517 | void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
| bogdanm | 0:9b334a45a8ff | 518 | /** |
| bogdanm | 0:9b334a45a8ff | 519 | * @} |
| bogdanm | 0:9b334a45a8ff | 520 | */ |
| bogdanm | 0:9b334a45a8ff | 521 | |
| bogdanm | 0:9b334a45a8ff | 522 | /** @addtogroup ADC_Exported_Functions_Group3 |
| bogdanm | 0:9b334a45a8ff | 523 | * @{ |
| bogdanm | 0:9b334a45a8ff | 524 | */ |
| bogdanm | 0:9b334a45a8ff | 525 | /* Peripheral Control functions *************************************************/ |
| bogdanm | 0:9b334a45a8ff | 526 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); |
| bogdanm | 0:9b334a45a8ff | 527 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); |
| bogdanm | 0:9b334a45a8ff | 528 | /** |
| bogdanm | 0:9b334a45a8ff | 529 | * @} |
| bogdanm | 0:9b334a45a8ff | 530 | */ |
| bogdanm | 0:9b334a45a8ff | 531 | |
| bogdanm | 0:9b334a45a8ff | 532 | /** @addtogroup ADC_Exported_Functions_Group4 |
| bogdanm | 0:9b334a45a8ff | 533 | * @{ |
| bogdanm | 0:9b334a45a8ff | 534 | */ |
| bogdanm | 0:9b334a45a8ff | 535 | /* Peripheral State functions ***************************************************/ |
| bogdanm | 0:9b334a45a8ff | 536 | HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); |
| bogdanm | 0:9b334a45a8ff | 537 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
| bogdanm | 0:9b334a45a8ff | 538 | /** |
| bogdanm | 0:9b334a45a8ff | 539 | * @} |
| bogdanm | 0:9b334a45a8ff | 540 | */ |
| bogdanm | 0:9b334a45a8ff | 541 | |
| bogdanm | 0:9b334a45a8ff | 542 | /** |
| bogdanm | 0:9b334a45a8ff | 543 | * @} |
| bogdanm | 0:9b334a45a8ff | 544 | */ |
| bogdanm | 0:9b334a45a8ff | 545 | |
| bogdanm | 0:9b334a45a8ff | 546 | /* Private types -------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 547 | /* Private variables ---------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 548 | /* Private constants ---------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 549 | /** @defgroup ADC_Private_Constants ADC Private Constants |
| bogdanm | 0:9b334a45a8ff | 550 | * @{ |
| bogdanm | 0:9b334a45a8ff | 551 | */ |
| bogdanm | 0:9b334a45a8ff | 552 | /* Delay for ADC stabilization time. */ |
| bogdanm | 0:9b334a45a8ff | 553 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
| bogdanm | 0:9b334a45a8ff | 554 | /* Unit: us */ |
| bogdanm | 0:9b334a45a8ff | 555 | #define ADC_STAB_DELAY_US ((uint32_t) 3) |
| bogdanm | 0:9b334a45a8ff | 556 | /* Delay for temperature sensor stabilization time. */ |
| bogdanm | 0:9b334a45a8ff | 557 | /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
| bogdanm | 0:9b334a45a8ff | 558 | /* Unit: us */ |
| bogdanm | 0:9b334a45a8ff | 559 | #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) |
| bogdanm | 0:9b334a45a8ff | 560 | /** |
| bogdanm | 0:9b334a45a8ff | 561 | * @} |
| bogdanm | 0:9b334a45a8ff | 562 | */ |
| bogdanm | 0:9b334a45a8ff | 563 | |
| bogdanm | 0:9b334a45a8ff | 564 | /* Private macros ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 565 | /** @defgroup ADC_Private_Macros ADC Private Macros |
| bogdanm | 0:9b334a45a8ff | 566 | * @{ |
| bogdanm | 0:9b334a45a8ff | 567 | */ |
| bogdanm | 0:9b334a45a8ff | 568 | #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ |
| bogdanm | 0:9b334a45a8ff | 569 | ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ |
| bogdanm | 0:9b334a45a8ff | 570 | ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ |
| bogdanm | 0:9b334a45a8ff | 571 | ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8)) |
| bogdanm | 0:9b334a45a8ff | 572 | #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 573 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 574 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 575 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 576 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 577 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 578 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 579 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 580 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 581 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 582 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 583 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 584 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 585 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 586 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 587 | ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES)) |
| bogdanm | 0:9b334a45a8ff | 588 | #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ |
| bogdanm | 0:9b334a45a8ff | 589 | ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ |
| bogdanm | 0:9b334a45a8ff | 590 | ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ |
| bogdanm | 0:9b334a45a8ff | 591 | ((__RESOLUTION__) == ADC_RESOLUTION_6B)) |
| bogdanm | 0:9b334a45a8ff | 592 | #define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ |
| bogdanm | 0:9b334a45a8ff | 593 | ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ |
| bogdanm | 0:9b334a45a8ff | 594 | ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ |
| bogdanm | 0:9b334a45a8ff | 595 | ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) |
| bogdanm | 0:9b334a45a8ff | 596 | #define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ |
| bogdanm | 0:9b334a45a8ff | 597 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ |
| bogdanm | 0:9b334a45a8ff | 598 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ |
| bogdanm | 0:9b334a45a8ff | 599 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ |
| bogdanm | 0:9b334a45a8ff | 600 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) || \ |
| bogdanm | 0:9b334a45a8ff | 601 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ |
| bogdanm | 0:9b334a45a8ff | 602 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ |
| bogdanm | 0:9b334a45a8ff | 603 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ |
| bogdanm | 0:9b334a45a8ff | 604 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \ |
| bogdanm | 0:9b334a45a8ff | 605 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ |
| bogdanm | 0:9b334a45a8ff | 606 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ |
| bogdanm | 0:9b334a45a8ff | 607 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ |
| bogdanm | 0:9b334a45a8ff | 608 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ |
| bogdanm | 0:9b334a45a8ff | 609 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ |
| bogdanm | 0:9b334a45a8ff | 610 | ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ |
| bogdanm | 0:9b334a45a8ff | 611 | ((__REGTRIG__) == ADC_SOFTWARE_START)) |
| bogdanm | 0:9b334a45a8ff | 612 | #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ |
| bogdanm | 0:9b334a45a8ff | 613 | ((__ALIGN__) == ADC_DATAALIGN_LEFT)) |
| bogdanm | 0:9b334a45a8ff | 614 | |
| bogdanm | 0:9b334a45a8ff | 615 | #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 616 | ((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 617 | ((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 618 | ((__TIME__) == ADC_SAMPLETIME_56CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 619 | ((__TIME__) == ADC_SAMPLETIME_84CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 620 | ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 621 | ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \ |
| bogdanm | 0:9b334a45a8ff | 622 | ((__TIME__) == ADC_SAMPLETIME_480CYCLES)) |
| bogdanm | 0:9b334a45a8ff | 623 | #define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) || \ |
| bogdanm | 0:9b334a45a8ff | 624 | ((__EOCSelection__) == ADC_EOC_SEQ_CONV) || \ |
| bogdanm | 0:9b334a45a8ff | 625 | ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV)) |
| bogdanm | 0:9b334a45a8ff | 626 | #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \ |
| bogdanm | 0:9b334a45a8ff | 627 | ((__EVENT__) == ADC_OVR_EVENT)) |
| bogdanm | 0:9b334a45a8ff | 628 | #define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
| bogdanm | 0:9b334a45a8ff | 629 | ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ |
| bogdanm | 0:9b334a45a8ff | 630 | ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ |
| bogdanm | 0:9b334a45a8ff | 631 | ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ |
| bogdanm | 0:9b334a45a8ff | 632 | ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ |
| bogdanm | 0:9b334a45a8ff | 633 | ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ |
| bogdanm | 0:9b334a45a8ff | 634 | ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE)) |
| bogdanm | 0:9b334a45a8ff | 635 | #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ |
| bogdanm | 0:9b334a45a8ff | 636 | ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ |
| bogdanm | 0:9b334a45a8ff | 637 | ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) |
| bogdanm | 0:9b334a45a8ff | 638 | #define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF)) |
| bogdanm | 0:9b334a45a8ff | 639 | #define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16))) |
| bogdanm | 0:9b334a45a8ff | 640 | #define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16))) |
| bogdanm | 0:9b334a45a8ff | 641 | #define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8))) |
| bogdanm | 0:9b334a45a8ff | 642 | #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ |
| bogdanm | 0:9b334a45a8ff | 643 | ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \ |
| bogdanm | 0:9b334a45a8ff | 644 | (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \ |
| bogdanm | 0:9b334a45a8ff | 645 | (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \ |
| bogdanm | 0:9b334a45a8ff | 646 | (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F)))) |
| bogdanm | 0:9b334a45a8ff | 647 | |
| bogdanm | 0:9b334a45a8ff | 648 | /** |
| bogdanm | 0:9b334a45a8ff | 649 | * @brief Set ADC Regular channel sequence length. |
| bogdanm | 0:9b334a45a8ff | 650 | * @param _NbrOfConversion_: Regular channel sequence length. |
| bogdanm | 0:9b334a45a8ff | 651 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 652 | */ |
| bogdanm | 0:9b334a45a8ff | 653 | #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20) |
| bogdanm | 0:9b334a45a8ff | 654 | |
| bogdanm | 0:9b334a45a8ff | 655 | /** |
| bogdanm | 0:9b334a45a8ff | 656 | * @brief Set the ADC's sample time for channel numbers between 10 and 18. |
| bogdanm | 0:9b334a45a8ff | 657 | * @param _SAMPLETIME_: Sample time parameter. |
| bogdanm | 0:9b334a45a8ff | 658 | * @param _CHANNELNB_: Channel number. |
| bogdanm | 0:9b334a45a8ff | 659 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 660 | */ |
| bogdanm | 0:9b334a45a8ff | 661 | #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10))) |
| bogdanm | 0:9b334a45a8ff | 662 | |
| bogdanm | 0:9b334a45a8ff | 663 | /** |
| bogdanm | 0:9b334a45a8ff | 664 | * @brief Set the ADC's sample time for channel numbers between 0 and 9. |
| bogdanm | 0:9b334a45a8ff | 665 | * @param _SAMPLETIME_: Sample time parameter. |
| bogdanm | 0:9b334a45a8ff | 666 | * @param _CHANNELNB_: Channel number. |
| bogdanm | 0:9b334a45a8ff | 667 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 668 | */ |
| bogdanm | 0:9b334a45a8ff | 669 | #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_))))) |
| bogdanm | 0:9b334a45a8ff | 670 | |
| bogdanm | 0:9b334a45a8ff | 671 | /** |
| bogdanm | 0:9b334a45a8ff | 672 | * @brief Set the selected regular channel rank for rank between 1 and 6. |
| bogdanm | 0:9b334a45a8ff | 673 | * @param _CHANNELNB_: Channel number. |
| bogdanm | 0:9b334a45a8ff | 674 | * @param _RANKNB_: Rank number. |
| bogdanm | 0:9b334a45a8ff | 675 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 676 | */ |
| bogdanm | 0:9b334a45a8ff | 677 | #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1))) |
| bogdanm | 0:9b334a45a8ff | 678 | |
| bogdanm | 0:9b334a45a8ff | 679 | /** |
| bogdanm | 0:9b334a45a8ff | 680 | * @brief Set the selected regular channel rank for rank between 7 and 12. |
| bogdanm | 0:9b334a45a8ff | 681 | * @param _CHANNELNB_: Channel number. |
| bogdanm | 0:9b334a45a8ff | 682 | * @param _RANKNB_: Rank number. |
| bogdanm | 0:9b334a45a8ff | 683 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 684 | */ |
| bogdanm | 0:9b334a45a8ff | 685 | #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7))) |
| bogdanm | 0:9b334a45a8ff | 686 | |
| bogdanm | 0:9b334a45a8ff | 687 | /** |
| bogdanm | 0:9b334a45a8ff | 688 | * @brief Set the selected regular channel rank for rank between 13 and 16. |
| bogdanm | 0:9b334a45a8ff | 689 | * @param _CHANNELNB_: Channel number. |
| bogdanm | 0:9b334a45a8ff | 690 | * @param _RANKNB_: Rank number. |
| bogdanm | 0:9b334a45a8ff | 691 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 692 | */ |
| bogdanm | 0:9b334a45a8ff | 693 | #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13))) |
| bogdanm | 0:9b334a45a8ff | 694 | |
| bogdanm | 0:9b334a45a8ff | 695 | /** |
| bogdanm | 0:9b334a45a8ff | 696 | * @brief Enable ADC continuous conversion mode. |
| bogdanm | 0:9b334a45a8ff | 697 | * @param _CONTINUOUS_MODE_: Continuous mode. |
| bogdanm | 0:9b334a45a8ff | 698 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 699 | */ |
| bogdanm | 0:9b334a45a8ff | 700 | #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1) |
| bogdanm | 0:9b334a45a8ff | 701 | |
| bogdanm | 0:9b334a45a8ff | 702 | /** |
| bogdanm | 0:9b334a45a8ff | 703 | * @brief Configures the number of discontinuous conversions for the regular group channels. |
| bogdanm | 0:9b334a45a8ff | 704 | * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions. |
| bogdanm | 0:9b334a45a8ff | 705 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 706 | */ |
| bogdanm | 0:9b334a45a8ff | 707 | #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) |
| bogdanm | 0:9b334a45a8ff | 708 | |
| bogdanm | 0:9b334a45a8ff | 709 | /** |
| bogdanm | 0:9b334a45a8ff | 710 | * @brief Enable ADC scan mode. |
| bogdanm | 0:9b334a45a8ff | 711 | * @param _SCANCONV_MODE_: Scan conversion mode. |
| bogdanm | 0:9b334a45a8ff | 712 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 713 | */ |
| bogdanm | 0:9b334a45a8ff | 714 | #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8) |
| bogdanm | 0:9b334a45a8ff | 715 | |
| bogdanm | 0:9b334a45a8ff | 716 | /** |
| bogdanm | 0:9b334a45a8ff | 717 | * @brief Enable the ADC end of conversion selection. |
| bogdanm | 0:9b334a45a8ff | 718 | * @param _EOCSelection_MODE_: End of conversion selection mode. |
| bogdanm | 0:9b334a45a8ff | 719 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 720 | */ |
| bogdanm | 0:9b334a45a8ff | 721 | #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10) |
| bogdanm | 0:9b334a45a8ff | 722 | |
| bogdanm | 0:9b334a45a8ff | 723 | /** |
| bogdanm | 0:9b334a45a8ff | 724 | * @brief Enable the ADC DMA continuous request. |
| bogdanm | 0:9b334a45a8ff | 725 | * @param _DMAContReq_MODE_: DMA continuous request mode. |
| bogdanm | 0:9b334a45a8ff | 726 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 727 | */ |
| bogdanm | 0:9b334a45a8ff | 728 | #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9) |
| bogdanm | 0:9b334a45a8ff | 729 | |
| bogdanm | 0:9b334a45a8ff | 730 | /** |
| bogdanm | 0:9b334a45a8ff | 731 | * @brief Return resolution bits in CR1 register. |
| bogdanm | 0:9b334a45a8ff | 732 | * @param __HANDLE__: ADC handle |
| bogdanm | 0:9b334a45a8ff | 733 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 734 | */ |
| bogdanm | 0:9b334a45a8ff | 735 | #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) |
| bogdanm | 0:9b334a45a8ff | 736 | |
| bogdanm | 0:9b334a45a8ff | 737 | /** |
| bogdanm | 0:9b334a45a8ff | 738 | * @} |
| bogdanm | 0:9b334a45a8ff | 739 | */ |
| bogdanm | 0:9b334a45a8ff | 740 | |
| bogdanm | 0:9b334a45a8ff | 741 | /* Private functions ---------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 742 | /** @defgroup ADC_Private_Functions ADC Private Functions |
| bogdanm | 0:9b334a45a8ff | 743 | * @{ |
| bogdanm | 0:9b334a45a8ff | 744 | */ |
| bogdanm | 0:9b334a45a8ff | 745 | |
| bogdanm | 0:9b334a45a8ff | 746 | /** |
| bogdanm | 0:9b334a45a8ff | 747 | * @} |
| bogdanm | 0:9b334a45a8ff | 748 | */ |
| bogdanm | 0:9b334a45a8ff | 749 | |
| bogdanm | 0:9b334a45a8ff | 750 | /** |
| bogdanm | 0:9b334a45a8ff | 751 | * @} |
| bogdanm | 0:9b334a45a8ff | 752 | */ |
| bogdanm | 0:9b334a45a8ff | 753 | |
| bogdanm | 0:9b334a45a8ff | 754 | /** |
| bogdanm | 0:9b334a45a8ff | 755 | * @} |
| bogdanm | 0:9b334a45a8ff | 756 | */ |
| bogdanm | 0:9b334a45a8ff | 757 | |
| bogdanm | 0:9b334a45a8ff | 758 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 759 | } |
| bogdanm | 0:9b334a45a8ff | 760 | #endif |
| bogdanm | 0:9b334a45a8ff | 761 | |
| bogdanm | 0:9b334a45a8ff | 762 | #endif /*__STM32F7xx_ADC_H */ |
| bogdanm | 0:9b334a45a8ff | 763 | |
| bogdanm | 0:9b334a45a8ff | 764 | |
| bogdanm | 0:9b334a45a8ff | 765 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |