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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.h@178:7b4eb50f6890, 2017-11-29 (annotated)

Committer:
misodengaku
Date:
Wed Nov 29 06:30:35 2017 +0000
Revision:
178:7b4eb50f6890
Parent:
168:9672193075cf 
sco-evb-01 patch

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_rcc_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 168:9672193075cf 5 * @version V1.2.2
AnnaBridge 168:9672193075cf 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of RCC HAL Extension module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 168:9672193075cf 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_HAL_RCC_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_HAL_RCC_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup RCCEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief RCC PLL configuration structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t PLLState; /*!< The new state of the PLL.
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref RCC_PLL_Config */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
<> 144:ef7eb2e8f9f7 71 This parameter must be a value of @ref RCC_PLL_Clock_Source */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
<> 144:ef7eb2e8f9f7 74 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
<> 144:ef7eb2e8f9f7 77 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
<> 144:ef7eb2e8f9f7 80 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
<> 144:ef7eb2e8f9f7 83 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
<> 144:ef7eb2e8f9f7 84 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 85 uint32_t PLLR; /*!< PLLR: Division factor for DSI clock.
<> 144:ef7eb2e8f9f7 86 This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
<> 144:ef7eb2e8f9f7 87 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 }RCC_PLLInitTypeDef;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /**
<> 144:ef7eb2e8f9f7 92 * @brief PLLI2S Clock structure definition
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94 typedef struct
<> 144:ef7eb2e8f9f7 95 {
<> 144:ef7eb2e8f9f7 96 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
<> 144:ef7eb2e8f9f7 97 This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<> 144:ef7eb2e8f9f7 98 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
<> 144:ef7eb2e8f9f7 101 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<> 144:ef7eb2e8f9f7 102 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
<> 144:ef7eb2e8f9f7 105 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 106 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
<> 144:ef7eb2e8f9f7 107
<> 157:ff67d9f36b67 108 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
<> 157:ff67d9f36b67 109 defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 110 uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
<> 144:ef7eb2e8f9f7 111 This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
<> 144:ef7eb2e8f9f7 112 This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
<> 157:ff67d9f36b67 113 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 114 }RCC_PLLI2SInitTypeDef;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @brief PLLSAI Clock structure definition
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 typedef struct
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
<> 144:ef7eb2e8f9f7 122 This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<> 144:ef7eb2e8f9f7 123 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
<> 144:ef7eb2e8f9f7 126 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 127 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
<> 157:ff67d9f36b67 128
<> 157:ff67d9f36b67 129 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
<> 157:ff67d9f36b67 130 defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 131 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
<> 144:ef7eb2e8f9f7 132 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<> 144:ef7eb2e8f9f7 133 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
<> 157:ff67d9f36b67 134 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 157:ff67d9f36b67 135
<> 144:ef7eb2e8f9f7 136 uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
<> 144:ef7eb2e8f9f7 137 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
<> 144:ef7eb2e8f9f7 138 This parameter will be used only when PLLSAI is disabled */
<> 144:ef7eb2e8f9f7 139 }RCC_PLLSAIInitTypeDef;
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /**
<> 144:ef7eb2e8f9f7 142 * @brief RCC extended clocks structure definition
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144 typedef struct
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 147 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
<> 144:ef7eb2e8f9f7 150 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
<> 144:ef7eb2e8f9f7 153 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
<> 144:ef7eb2e8f9f7 156 This parameter must be a number between Min_Data = 1 and Max_Data = 32
<> 144:ef7eb2e8f9f7 157 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
<> 144:ef7eb2e8f9f7 160 This parameter must be a number between Min_Data = 1 and Max_Data = 32
<> 144:ef7eb2e8f9f7 161 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
<> 144:ef7eb2e8f9f7 164 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.
<> 144:ef7eb2e8f9f7 167 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.
<> 144:ef7eb2e8f9f7 170 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
<> 144:ef7eb2e8f9f7 173 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 176 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 179 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 182 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 uint32_t Usart2ClockSelection; /*!< USART2 clock source
<> 144:ef7eb2e8f9f7 185 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 uint32_t Usart3ClockSelection; /*!< USART3 clock source
<> 144:ef7eb2e8f9f7 188 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 uint32_t Uart4ClockSelection; /*!< UART4 clock source
<> 144:ef7eb2e8f9f7 191 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 uint32_t Uart5ClockSelection; /*!< UART5 clock source
<> 144:ef7eb2e8f9f7 194 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 uint32_t Usart6ClockSelection; /*!< USART6 clock source
<> 144:ef7eb2e8f9f7 197 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 uint32_t Uart7ClockSelection; /*!< UART7 clock source
<> 144:ef7eb2e8f9f7 200 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 uint32_t Uart8ClockSelection; /*!< UART8 clock source
<> 144:ef7eb2e8f9f7 203 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 206 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
<> 144:ef7eb2e8f9f7 209 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
<> 144:ef7eb2e8f9f7 212 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 uint32_t I2c4ClockSelection; /*!< I2C4 clock source
<> 144:ef7eb2e8f9f7 215 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
<> 144:ef7eb2e8f9f7 218 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 uint32_t CecClockSelection; /*!< CEC clock source
<> 144:ef7eb2e8f9f7 221 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
<> 144:ef7eb2e8f9f7 224 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source
<> 144:ef7eb2e8f9f7 227 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
<> 144:ef7eb2e8f9f7 228
<> 161:2cc1468da177 229 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 230 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 231 uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source
<> 144:ef7eb2e8f9f7 232 This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */
<> 161:2cc1468da177 233 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 234
<> 161:2cc1468da177 235 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 236 uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source
<> 144:ef7eb2e8f9f7 237 This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source
<> 144:ef7eb2e8f9f7 240 This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */
<> 144:ef7eb2e8f9f7 241 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 242 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @}
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 248 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
<> 144:ef7eb2e8f9f7 249 * @{
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
<> 144:ef7eb2e8f9f7 253 * @{
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 256 #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 257 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 258 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 259 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 260 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 261 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 262 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 263 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 264 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 265 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 266 #define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 267 #define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 268 #define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 269 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 270 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 271 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 272 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 273 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 274 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 275 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 276 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 277 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 278 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 279 #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 280 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U)
<> 161:2cc1468da177 281 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 282 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 283 #define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U)
<> 161:2cc1468da177 284 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 285 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 286 #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 287 #define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U)
<> 157:ff67d9f36b67 288 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /**
<> 144:ef7eb2e8f9f7 291 * @}
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293
<> 157:ff67d9f36b67 294 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
<> 157:ff67d9f36b67 295 defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 296 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
<> 144:ef7eb2e8f9f7 297 * @{
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 #define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 300 #define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 301 #define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 302 #define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U)
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @}
<> 144:ef7eb2e8f9f7 305 */
<> 157:ff67d9f36b67 306 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
<> 144:ef7eb2e8f9f7 309 * @{
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 312 #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 313 #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 314 #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U)
<> 144:ef7eb2e8f9f7 315 /**
<> 144:ef7eb2e8f9f7 316 * @}
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
<> 144:ef7eb2e8f9f7 320 * @{
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 323 #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
<> 144:ef7eb2e8f9f7 324 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
<> 144:ef7eb2e8f9f7 325 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
<> 144:ef7eb2e8f9f7 326 /**
<> 144:ef7eb2e8f9f7 327 * @}
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
<> 144:ef7eb2e8f9f7 331 * @{
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 334 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /**
<> 144:ef7eb2e8f9f7 337 * @}
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
<> 144:ef7eb2e8f9f7 342 * @{
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344 #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 345 #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
<> 144:ef7eb2e8f9f7 346 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
<> 144:ef7eb2e8f9f7 347 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 348 #define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL
<> 144:ef7eb2e8f9f7 349 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @}
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
<> 144:ef7eb2e8f9f7 355 * @{
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357 #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 358 #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
<> 144:ef7eb2e8f9f7 359 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
<> 144:ef7eb2e8f9f7 360 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 361 #define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL
<> 144:ef7eb2e8f9f7 362 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 363 /**
<> 144:ef7eb2e8f9f7 364 * @}
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
<> 144:ef7eb2e8f9f7 368 * @{
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 371 #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
<> 144:ef7eb2e8f9f7 372 /**
<> 144:ef7eb2e8f9f7 373 * @}
<> 144:ef7eb2e8f9f7 374 */
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
<> 144:ef7eb2e8f9f7 377 * @{
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 380 #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
<> 144:ef7eb2e8f9f7 381 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
<> 144:ef7eb2e8f9f7 382 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @}
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
<> 144:ef7eb2e8f9f7 388 * @{
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 391 #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
<> 144:ef7eb2e8f9f7 392 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
<> 144:ef7eb2e8f9f7 393 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
<> 144:ef7eb2e8f9f7 394 /**
<> 144:ef7eb2e8f9f7 395 * @}
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
<> 144:ef7eb2e8f9f7 399 * @{
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 402 #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
<> 144:ef7eb2e8f9f7 403 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
<> 144:ef7eb2e8f9f7 404 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
<> 144:ef7eb2e8f9f7 405 /**
<> 144:ef7eb2e8f9f7 406 * @}
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
<> 144:ef7eb2e8f9f7 410 * @{
<> 144:ef7eb2e8f9f7 411 */
<> 144:ef7eb2e8f9f7 412 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 413 #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
<> 144:ef7eb2e8f9f7 414 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
<> 144:ef7eb2e8f9f7 415 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
<> 144:ef7eb2e8f9f7 416 /**
<> 144:ef7eb2e8f9f7 417 * @}
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
<> 144:ef7eb2e8f9f7 421 * @{
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 424 #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
<> 144:ef7eb2e8f9f7 425 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
<> 144:ef7eb2e8f9f7 426 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
<> 144:ef7eb2e8f9f7 427 /**
<> 144:ef7eb2e8f9f7 428 * @}
<> 144:ef7eb2e8f9f7 429 */
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
<> 144:ef7eb2e8f9f7 432 * @{
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434 #define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 435 #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
<> 144:ef7eb2e8f9f7 436 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
<> 144:ef7eb2e8f9f7 437 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
<> 144:ef7eb2e8f9f7 438 /**
<> 144:ef7eb2e8f9f7 439 * @}
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
<> 144:ef7eb2e8f9f7 443 * @{
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 446 #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
<> 144:ef7eb2e8f9f7 447 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
<> 144:ef7eb2e8f9f7 448 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
<> 144:ef7eb2e8f9f7 449 /**
<> 144:ef7eb2e8f9f7 450 * @}
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
<> 144:ef7eb2e8f9f7 454 * @{
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 457 #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
<> 144:ef7eb2e8f9f7 458 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
<> 144:ef7eb2e8f9f7 459 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
<> 144:ef7eb2e8f9f7 460 /**
<> 144:ef7eb2e8f9f7 461 * @}
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
<> 144:ef7eb2e8f9f7 465 * @{
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 468 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
<> 144:ef7eb2e8f9f7 469 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
<> 144:ef7eb2e8f9f7 470 /**
<> 144:ef7eb2e8f9f7 471 * @}
<> 144:ef7eb2e8f9f7 472 */
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
<> 144:ef7eb2e8f9f7 475 * @{
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 478 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
<> 144:ef7eb2e8f9f7 479 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /**
<> 144:ef7eb2e8f9f7 482 * @}
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
<> 144:ef7eb2e8f9f7 486 * @{
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 489 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
<> 144:ef7eb2e8f9f7 490 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
<> 144:ef7eb2e8f9f7 491 /**
<> 144:ef7eb2e8f9f7 492 * @}
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
<> 144:ef7eb2e8f9f7 496 * @{
<> 144:ef7eb2e8f9f7 497 */
<> 144:ef7eb2e8f9f7 498 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 499 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
<> 144:ef7eb2e8f9f7 500 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
<> 144:ef7eb2e8f9f7 501 /**
<> 144:ef7eb2e8f9f7 502 * @}
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
<> 144:ef7eb2e8f9f7 506 * @{
<> 144:ef7eb2e8f9f7 507 */
<> 161:2cc1468da177 508 #define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 509 #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
<> 144:ef7eb2e8f9f7 510 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
<> 144:ef7eb2e8f9f7 511 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /**
<> 144:ef7eb2e8f9f7 514 * @}
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
<> 144:ef7eb2e8f9f7 518 * @{
<> 144:ef7eb2e8f9f7 519 */
<> 144:ef7eb2e8f9f7 520 #define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 521 #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
<> 144:ef7eb2e8f9f7 522 /**
<> 144:ef7eb2e8f9f7 523 * @}
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
<> 144:ef7eb2e8f9f7 527 * @{
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529 #define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 530 #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
<> 144:ef7eb2e8f9f7 531 /**
<> 144:ef7eb2e8f9f7 532 * @}
<> 144:ef7eb2e8f9f7 533 */
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
<> 144:ef7eb2e8f9f7 536 * @{
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538 #define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 539 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
<> 144:ef7eb2e8f9f7 540 /**
<> 144:ef7eb2e8f9f7 541 * @}
<> 144:ef7eb2e8f9f7 542 */
<> 144:ef7eb2e8f9f7 543
<> 161:2cc1468da177 544 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 545 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 546 /** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source
<> 144:ef7eb2e8f9f7 547 * @{
<> 144:ef7eb2e8f9f7 548 */
<> 144:ef7eb2e8f9f7 549 #define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 550 #define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL
<> 144:ef7eb2e8f9f7 551 /**
<> 144:ef7eb2e8f9f7 552 * @}
<> 161:2cc1468da177 553 */
<> 161:2cc1468da177 554 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 555
<> 161:2cc1468da177 556 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 557 /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source
<> 144:ef7eb2e8f9f7 558 * @{
<> 144:ef7eb2e8f9f7 559 */
<> 161:2cc1468da177 560 #define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 561 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL
<> 144:ef7eb2e8f9f7 562 /**
<> 144:ef7eb2e8f9f7 563 * @}
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source
<> 144:ef7eb2e8f9f7 567 * @{
<> 144:ef7eb2e8f9f7 568 */
<> 144:ef7eb2e8f9f7 569 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 570 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL
<> 144:ef7eb2e8f9f7 571 /**
<> 144:ef7eb2e8f9f7 572 * @}
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 #if defined (STM32F769xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 577 /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
<> 144:ef7eb2e8f9f7 578 * @{
<> 144:ef7eb2e8f9f7 579 */
<> 144:ef7eb2e8f9f7 580 #define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 581 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL)
<> 144:ef7eb2e8f9f7 582 /**
<> 144:ef7eb2e8f9f7 583 * @}
<> 144:ef7eb2e8f9f7 584 */
<> 144:ef7eb2e8f9f7 585 #endif /* STM32F769xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /**
<> 144:ef7eb2e8f9f7 588 * @}
<> 144:ef7eb2e8f9f7 589 */
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 592 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
<> 144:ef7eb2e8f9f7 593 * @{
<> 144:ef7eb2e8f9f7 594 */
<> 144:ef7eb2e8f9f7 595 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
<> 144:ef7eb2e8f9f7 596 * @brief Enables or disables the AHB/APB peripheral clock.
<> 144:ef7eb2e8f9f7 597 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 598 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 599 * using it.
<> 144:ef7eb2e8f9f7 600 * @{
<> 144:ef7eb2e8f9f7 601 */
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /** @brief Enables or disables the AHB1 peripheral clock.
<> 144:ef7eb2e8f9f7 604 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 605 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 606 * using it.
<> 144:ef7eb2e8f9f7 607 */
<> 144:ef7eb2e8f9f7 608 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 609 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 610 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
<> 144:ef7eb2e8f9f7 611 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 612 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
<> 144:ef7eb2e8f9f7 613 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 614 } while(0)
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 617 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 618 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
<> 144:ef7eb2e8f9f7 619 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 620 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
<> 144:ef7eb2e8f9f7 621 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 622 } while(0)
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 625 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 626 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
<> 144:ef7eb2e8f9f7 627 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 628 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
<> 144:ef7eb2e8f9f7 629 UNUSED(tmpreg); \
<> 161:2cc1468da177 630 } while(0)
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 633 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 634 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
<> 144:ef7eb2e8f9f7 635 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 636 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
<> 144:ef7eb2e8f9f7 637 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 638 } while(0)
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 641 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 642 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
<> 144:ef7eb2e8f9f7 643 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 644 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
<> 144:ef7eb2e8f9f7 645 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 646 } while(0)
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 649 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 650 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
<> 144:ef7eb2e8f9f7 651 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 652 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
<> 144:ef7eb2e8f9f7 653 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 654 } while(0)
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 657 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 658 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
<> 144:ef7eb2e8f9f7 659 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 660 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
<> 144:ef7eb2e8f9f7 661 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 662 } while(0)
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 665 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 666 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
<> 144:ef7eb2e8f9f7 667 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 668 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
<> 144:ef7eb2e8f9f7 669 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 670 } while(0)
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 673 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 674 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
<> 144:ef7eb2e8f9f7 675 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 676 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
<> 144:ef7eb2e8f9f7 677 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 678 } while(0)
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 681 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 682 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
<> 144:ef7eb2e8f9f7 683 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 684 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
<> 144:ef7eb2e8f9f7 685 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 686 } while(0)
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 689 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 690 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
<> 144:ef7eb2e8f9f7 691 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 692 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
<> 144:ef7eb2e8f9f7 693 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 694 } while(0)
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 697 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 698 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
<> 144:ef7eb2e8f9f7 699 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 700 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
<> 144:ef7eb2e8f9f7 701 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 702 } while(0)
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 705 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 706 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
<> 144:ef7eb2e8f9f7 707 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 708 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
<> 144:ef7eb2e8f9f7 709 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 710 } while(0)
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 713 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 714 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
<> 144:ef7eb2e8f9f7 715 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 716 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
<> 144:ef7eb2e8f9f7 717 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 718 } while(0)
<> 144:ef7eb2e8f9f7 719
<> 161:2cc1468da177 720 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 721 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 722 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 723 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 724 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
<> 144:ef7eb2e8f9f7 725 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 726 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
<> 144:ef7eb2e8f9f7 727 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 728 } while(0)
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 731 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 732 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
<> 144:ef7eb2e8f9f7 733 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 734 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
<> 144:ef7eb2e8f9f7 735 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 736 } while(0)
<> 161:2cc1468da177 737
<> 161:2cc1468da177 738 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
<> 161:2cc1468da177 739 __IO uint32_t tmpreg; \
<> 161:2cc1468da177 740 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
<> 161:2cc1468da177 741 /* Delay after an RCC peripheral clock enabling */ \
<> 161:2cc1468da177 742 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
<> 161:2cc1468da177 743 UNUSED(tmpreg); \
<> 161:2cc1468da177 744 } while(0)
<> 161:2cc1468da177 745 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
<> 144:ef7eb2e8f9f7 748 #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
<> 144:ef7eb2e8f9f7 749 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
<> 144:ef7eb2e8f9f7 750 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
<> 144:ef7eb2e8f9f7 751 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
<> 144:ef7eb2e8f9f7 752 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
<> 144:ef7eb2e8f9f7 753 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
<> 144:ef7eb2e8f9f7 754 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
<> 144:ef7eb2e8f9f7 755 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
<> 144:ef7eb2e8f9f7 756 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
<> 144:ef7eb2e8f9f7 757 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
<> 144:ef7eb2e8f9f7 758 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
<> 144:ef7eb2e8f9f7 759 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
<> 144:ef7eb2e8f9f7 760 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
<> 161:2cc1468da177 761 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 762 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 763 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
<> 144:ef7eb2e8f9f7 764 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
<> 161:2cc1468da177 765 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
<> 161:2cc1468da177 766 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 767
<> 161:2cc1468da177 768 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 769 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 770 /**
<> 144:ef7eb2e8f9f7 771 * @brief Enable ETHERNET clock.
<> 144:ef7eb2e8f9f7 772 */
<> 144:ef7eb2e8f9f7 773 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 774 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 775 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
<> 144:ef7eb2e8f9f7 776 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 777 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
<> 144:ef7eb2e8f9f7 778 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 779 } while(0)
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 782 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 783 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
<> 144:ef7eb2e8f9f7 784 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 785 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
<> 144:ef7eb2e8f9f7 786 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 787 } while(0)
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 790 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 791 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
<> 144:ef7eb2e8f9f7 792 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 793 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
<> 144:ef7eb2e8f9f7 794 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 795 } while(0)
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 798 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 799 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
<> 144:ef7eb2e8f9f7 800 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 801 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
<> 144:ef7eb2e8f9f7 802 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 803 } while(0)
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 806 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
<> 144:ef7eb2e8f9f7 807 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
<> 144:ef7eb2e8f9f7 808 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
<> 144:ef7eb2e8f9f7 809 } while(0)
<> 144:ef7eb2e8f9f7 810 /**
<> 144:ef7eb2e8f9f7 811 * @brief Disable ETHERNET clock.
<> 144:ef7eb2e8f9f7 812 */
<> 144:ef7eb2e8f9f7 813 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
<> 144:ef7eb2e8f9f7 814 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
<> 144:ef7eb2e8f9f7 815 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
<> 144:ef7eb2e8f9f7 816 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
<> 144:ef7eb2e8f9f7 817 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
<> 144:ef7eb2e8f9f7 818 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
<> 144:ef7eb2e8f9f7 819 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
<> 144:ef7eb2e8f9f7 820 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
<> 144:ef7eb2e8f9f7 821 } while(0)
<> 161:2cc1468da177 822 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /** @brief Enable or disable the AHB2 peripheral clock.
<> 144:ef7eb2e8f9f7 825 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 826 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 827 * using it.
<> 144:ef7eb2e8f9f7 828 */
<> 161:2cc1468da177 829 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 830 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 831 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 832 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 833 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
<> 144:ef7eb2e8f9f7 834 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 835 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
<> 144:ef7eb2e8f9f7 836 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 837 } while(0)
<> 161:2cc1468da177 838 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
<> 161:2cc1468da177 839 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 842 #define __HAL_RCC_JPEG_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 843 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 844 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
<> 144:ef7eb2e8f9f7 845 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 846 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
<> 144:ef7eb2e8f9f7 847 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 848 } while(0)
<> 144:ef7eb2e8f9f7 849 #define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))
<> 144:ef7eb2e8f9f7 850 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 853 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 854 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
<> 144:ef7eb2e8f9f7 855 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 856 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
<> 144:ef7eb2e8f9f7 857 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 858 } while(0)
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 861 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 862 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
<> 144:ef7eb2e8f9f7 863 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 864 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
<> 144:ef7eb2e8f9f7 865 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 866 __HAL_RCC_SYSCFG_CLK_ENABLE();\
<> 144:ef7eb2e8f9f7 867 } while(0)
<> 161:2cc1468da177 868
<> 144:ef7eb2e8f9f7 869 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
<> 144:ef7eb2e8f9f7 872 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 873 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 874 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 875 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
<> 144:ef7eb2e8f9f7 876 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 877 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
<> 144:ef7eb2e8f9f7 878 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 879 } while(0)
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 882 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 883 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
<> 144:ef7eb2e8f9f7 884 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 885 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
<> 144:ef7eb2e8f9f7 886 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 887 } while(0)
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
<> 144:ef7eb2e8f9f7 890 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
<> 144:ef7eb2e8f9f7 891 #endif /* STM32F756x || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 892
<> 161:2cc1468da177 893 #if defined(STM32F732xx) || defined (STM32F733xx)
<> 161:2cc1468da177 894 #define __HAL_RCC_AES_CLK_ENABLE() do { \
<> 161:2cc1468da177 895 __IO uint32_t tmpreg; \
<> 161:2cc1468da177 896 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
<> 161:2cc1468da177 897 /* Delay after an RCC peripheral clock enabling */ \
<> 161:2cc1468da177 898 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
<> 161:2cc1468da177 899 UNUSED(tmpreg); \
<> 161:2cc1468da177 900 } while(0)
<> 161:2cc1468da177 901
<> 161:2cc1468da177 902 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
<> 161:2cc1468da177 903 #endif /* STM32F732xx || STM32F733xx */
<> 161:2cc1468da177 904
<> 144:ef7eb2e8f9f7 905 /** @brief Enables or disables the AHB3 peripheral clock.
<> 144:ef7eb2e8f9f7 906 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 907 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 908 * using it.
<> 144:ef7eb2e8f9f7 909 */
<> 144:ef7eb2e8f9f7 910 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 911 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 912 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
<> 144:ef7eb2e8f9f7 913 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 914 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
<> 144:ef7eb2e8f9f7 915 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 916 } while(0)
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 919 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 920 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
<> 144:ef7eb2e8f9f7 921 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 922 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
<> 144:ef7eb2e8f9f7 923 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 924 } while(0)
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
<> 144:ef7eb2e8f9f7 927 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<> 144:ef7eb2e8f9f7 930 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 931 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 932 * using it.
<> 144:ef7eb2e8f9f7 933 */
<> 144:ef7eb2e8f9f7 934 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 935 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 936 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<> 144:ef7eb2e8f9f7 937 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 938 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<> 144:ef7eb2e8f9f7 939 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 940 } while(0)
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 943 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 944 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
<> 144:ef7eb2e8f9f7 945 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 946 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
<> 144:ef7eb2e8f9f7 947 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 948 } while(0)
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 951 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 952 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
<> 144:ef7eb2e8f9f7 953 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 954 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
<> 144:ef7eb2e8f9f7 955 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 956 } while(0)
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 959 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 960 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
<> 144:ef7eb2e8f9f7 961 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 962 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
<> 144:ef7eb2e8f9f7 963 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 964 } while(0)
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 967 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 968 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<> 144:ef7eb2e8f9f7 969 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 970 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<> 144:ef7eb2e8f9f7 971 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 972 } while(0)
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 975 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 976 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<> 144:ef7eb2e8f9f7 977 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 978 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<> 144:ef7eb2e8f9f7 979 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 980 } while(0)
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 983 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 984 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
<> 144:ef7eb2e8f9f7 985 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 986 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
<> 144:ef7eb2e8f9f7 987 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 988 } while(0)
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 991 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 992 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
<> 144:ef7eb2e8f9f7 993 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 994 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
<> 144:ef7eb2e8f9f7 995 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 996 } while(0)
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 999 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1000 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
<> 144:ef7eb2e8f9f7 1001 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1002 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
<> 144:ef7eb2e8f9f7 1003 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1004 } while(0)
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1007 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1008 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
<> 144:ef7eb2e8f9f7 1009 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1010 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
<> 144:ef7eb2e8f9f7 1011 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1012 } while(0)
<> 144:ef7eb2e8f9f7 1013
<> 161:2cc1468da177 1014 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
<> 161:2cc1468da177 1015 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
<> 161:2cc1468da177 1016 defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1017 #define __HAL_RCC_RTC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1018 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1019 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
<> 144:ef7eb2e8f9f7 1020 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1021 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
<> 144:ef7eb2e8f9f7 1022 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1023 } while(0)
<> 161:2cc1468da177 1024 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
<> 161:2cc1468da177 1025 STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1026
<> 161:2cc1468da177 1027 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1028 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1029 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1030 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
<> 144:ef7eb2e8f9f7 1031 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1032 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
<> 144:ef7eb2e8f9f7 1033 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1034 } while(0)
<> 144:ef7eb2e8f9f7 1035 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1038 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1039 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<> 144:ef7eb2e8f9f7 1040 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1041 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<> 144:ef7eb2e8f9f7 1042 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1043 } while(0)
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1046 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1047 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
<> 144:ef7eb2e8f9f7 1048 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1049 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
<> 144:ef7eb2e8f9f7 1050 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1051 } while(0)
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1054 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1055 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<> 144:ef7eb2e8f9f7 1056 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1057 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<> 144:ef7eb2e8f9f7 1058 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1059 } while(0)
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1062 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1063 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<> 144:ef7eb2e8f9f7 1064 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1065 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<> 144:ef7eb2e8f9f7 1066 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1067 } while(0)
<> 144:ef7eb2e8f9f7 1068
<> 144:ef7eb2e8f9f7 1069 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1070 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1071 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
<> 144:ef7eb2e8f9f7 1072 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1073 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
<> 144:ef7eb2e8f9f7 1074 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1075 } while(0)
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1078 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1079 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
<> 144:ef7eb2e8f9f7 1080 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1081 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
<> 144:ef7eb2e8f9f7 1082 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1083 } while(0)
<> 144:ef7eb2e8f9f7 1084
<> 144:ef7eb2e8f9f7 1085 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1086 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1087 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<> 144:ef7eb2e8f9f7 1088 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1089 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<> 144:ef7eb2e8f9f7 1090 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1091 } while(0)
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1094 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1095 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<> 144:ef7eb2e8f9f7 1096 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1097 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<> 144:ef7eb2e8f9f7 1098 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1099 } while(0)
<> 144:ef7eb2e8f9f7 1100
<> 144:ef7eb2e8f9f7 1101 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1102 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1103 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
<> 144:ef7eb2e8f9f7 1104 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1105 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
<> 144:ef7eb2e8f9f7 1106 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1107 } while(0)
<> 161:2cc1468da177 1108
<> 144:ef7eb2e8f9f7 1109 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1110 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1111 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
<> 144:ef7eb2e8f9f7 1112 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1113 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
<> 144:ef7eb2e8f9f7 1114 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1115 } while(0)
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1118 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1119 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<> 144:ef7eb2e8f9f7 1120 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1121 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<> 144:ef7eb2e8f9f7 1122 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1123 } while(0)
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1126 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1127 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
<> 144:ef7eb2e8f9f7 1128 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1129 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
<> 144:ef7eb2e8f9f7 1130 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1131 } while(0)
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1134 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1135 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
<> 144:ef7eb2e8f9f7 1136 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1137 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
<> 144:ef7eb2e8f9f7 1138 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1139 } while(0)
<> 161:2cc1468da177 1140
<> 161:2cc1468da177 1141 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1142 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 1143 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
<> 161:2cc1468da177 1144 __IO uint32_t tmpreg; \
<> 161:2cc1468da177 1145 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
<> 161:2cc1468da177 1146 /* Delay after an RCC peripheral clock enabling */ \
<> 161:2cc1468da177 1147 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
<> 161:2cc1468da177 1148 UNUSED(tmpreg); \
<> 161:2cc1468da177 1149 } while(0)
<> 161:2cc1468da177 1150
<> 161:2cc1468da177 1151 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
<> 161:2cc1468da177 1152 __IO uint32_t tmpreg; \
<> 161:2cc1468da177 1153 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
<> 161:2cc1468da177 1154 /* Delay after an RCC peripheral clock enabling */ \
<> 161:2cc1468da177 1155 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
<> 161:2cc1468da177 1156 UNUSED(tmpreg); \
<> 161:2cc1468da177 1157 } while(0)
<> 161:2cc1468da177 1158
<> 161:2cc1468da177 1159 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
<> 161:2cc1468da177 1160 __IO uint32_t tmpreg; \
<> 161:2cc1468da177 1161 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
<> 161:2cc1468da177 1162 /* Delay after an RCC peripheral clock enabling */ \
<> 161:2cc1468da177 1163 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
<> 161:2cc1468da177 1164 UNUSED(tmpreg); \
<> 161:2cc1468da177 1165 } while(0)
<> 161:2cc1468da177 1166
<> 161:2cc1468da177 1167 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
<> 161:2cc1468da177 1168 __IO uint32_t tmpreg; \
<> 161:2cc1468da177 1169 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
<> 161:2cc1468da177 1170 /* Delay after an RCC peripheral clock enabling */ \
<> 161:2cc1468da177 1171 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
<> 161:2cc1468da177 1172 UNUSED(tmpreg); \
<> 161:2cc1468da177 1173 } while(0)
<> 161:2cc1468da177 1174 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
<> 144:ef7eb2e8f9f7 1177 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
<> 144:ef7eb2e8f9f7 1178 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
<> 144:ef7eb2e8f9f7 1179 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
<> 144:ef7eb2e8f9f7 1180 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
<> 144:ef7eb2e8f9f7 1181 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
<> 144:ef7eb2e8f9f7 1182 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
<> 144:ef7eb2e8f9f7 1183 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
<> 144:ef7eb2e8f9f7 1184 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
<> 144:ef7eb2e8f9f7 1185 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
<> 161:2cc1468da177 1186 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
<> 161:2cc1468da177 1187 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
<> 161:2cc1468da177 1188 defined (STM32F779xx)
<> 161:2cc1468da177 1189 #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))
<> 161:2cc1468da177 1190 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
<> 161:2cc1468da177 1191 STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1192 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1193 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
<> 144:ef7eb2e8f9f7 1194 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1195 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
<> 144:ef7eb2e8f9f7 1196 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
<> 144:ef7eb2e8f9f7 1197 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
<> 144:ef7eb2e8f9f7 1198 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
<> 144:ef7eb2e8f9f7 1199 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
<> 144:ef7eb2e8f9f7 1200 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
<> 144:ef7eb2e8f9f7 1201 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
<> 144:ef7eb2e8f9f7 1202 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
<> 144:ef7eb2e8f9f7 1203 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
<> 144:ef7eb2e8f9f7 1204 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
<> 144:ef7eb2e8f9f7 1205 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
<> 144:ef7eb2e8f9f7 1206 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
<> 144:ef7eb2e8f9f7 1207 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
<> 161:2cc1468da177 1208 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1209 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 1210 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
<> 161:2cc1468da177 1211 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
<> 161:2cc1468da177 1212 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
<> 161:2cc1468da177 1213 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
<> 161:2cc1468da177 1214 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1215
<> 144:ef7eb2e8f9f7 1216 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<> 144:ef7eb2e8f9f7 1217 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1218 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1219 * using it.
<> 144:ef7eb2e8f9f7 1220 */
<> 144:ef7eb2e8f9f7 1221 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1222 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1223 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
<> 144:ef7eb2e8f9f7 1224 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1225 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
<> 144:ef7eb2e8f9f7 1226 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1227 } while(0)
<> 144:ef7eb2e8f9f7 1228
<> 144:ef7eb2e8f9f7 1229 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1230 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1231 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
<> 144:ef7eb2e8f9f7 1232 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1233 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
<> 144:ef7eb2e8f9f7 1234 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1235 } while(0)
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1238 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1239 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<> 144:ef7eb2e8f9f7 1240 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1241 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<> 144:ef7eb2e8f9f7 1242 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1243 } while(0)
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1246 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1247 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
<> 144:ef7eb2e8f9f7 1248 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1249 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
<> 144:ef7eb2e8f9f7 1250 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1251 } while(0)
<> 144:ef7eb2e8f9f7 1252
<> 161:2cc1468da177 1253 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1254 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1255 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1256 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1257 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
<> 144:ef7eb2e8f9f7 1258 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1259 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
<> 144:ef7eb2e8f9f7 1260 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1261 } while(0)
<> 161:2cc1468da177 1262 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1263
<> 144:ef7eb2e8f9f7 1264 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1265 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1266 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<> 144:ef7eb2e8f9f7 1267 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1268 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<> 144:ef7eb2e8f9f7 1269 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1270 } while(0)
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1273 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1274 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
<> 144:ef7eb2e8f9f7 1275 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1276 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
<> 144:ef7eb2e8f9f7 1277 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1278 } while(0)
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1281 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1282 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
<> 144:ef7eb2e8f9f7 1283 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1284 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
<> 144:ef7eb2e8f9f7 1285 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1286 } while(0)
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1289 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1290 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
<> 144:ef7eb2e8f9f7 1291 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1292 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
<> 144:ef7eb2e8f9f7 1293 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1294 } while(0)
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1297 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1298 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<> 144:ef7eb2e8f9f7 1299 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1300 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<> 144:ef7eb2e8f9f7 1301 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1302 } while(0)
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1305 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1306 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
<> 144:ef7eb2e8f9f7 1307 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1308 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
<> 144:ef7eb2e8f9f7 1309 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1310 } while(0)
<> 144:ef7eb2e8f9f7 1311
<> 144:ef7eb2e8f9f7 1312 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1313 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1314 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
<> 144:ef7eb2e8f9f7 1315 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1316 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
<> 144:ef7eb2e8f9f7 1317 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1318 } while(0)
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1321 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1322 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
<> 144:ef7eb2e8f9f7 1323 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1324 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
<> 144:ef7eb2e8f9f7 1325 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1326 } while(0)
<> 144:ef7eb2e8f9f7 1327
<> 144:ef7eb2e8f9f7 1328 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1329 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1330 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
<> 144:ef7eb2e8f9f7 1331 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1332 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
<> 144:ef7eb2e8f9f7 1333 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1334 } while(0)
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1337 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1338 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
<> 144:ef7eb2e8f9f7 1339 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1340 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
<> 144:ef7eb2e8f9f7 1341 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1342 } while(0)
<> 144:ef7eb2e8f9f7 1343
<> 144:ef7eb2e8f9f7 1344 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1345 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1346 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
<> 144:ef7eb2e8f9f7 1347 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1348 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
<> 144:ef7eb2e8f9f7 1349 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1350 } while(0)
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1353 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1354 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
<> 144:ef7eb2e8f9f7 1355 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1356 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
<> 144:ef7eb2e8f9f7 1357 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1358 } while(0)
<> 144:ef7eb2e8f9f7 1359
<> 144:ef7eb2e8f9f7 1360 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1361 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1362 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
<> 144:ef7eb2e8f9f7 1363 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1364 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
<> 144:ef7eb2e8f9f7 1365 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1366 } while(0)
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1369 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1370 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1371 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
<> 144:ef7eb2e8f9f7 1372 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1373 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
<> 144:ef7eb2e8f9f7 1374 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1375 } while(0)
<> 144:ef7eb2e8f9f7 1376 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1377
<> 144:ef7eb2e8f9f7 1378 #if defined (STM32F769xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1379 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1380 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1381 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
<> 144:ef7eb2e8f9f7 1382 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1383 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
<> 144:ef7eb2e8f9f7 1384 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1385 } while(0)
<> 144:ef7eb2e8f9f7 1386 #endif /* STM32F769xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1387
<> 144:ef7eb2e8f9f7 1388 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1389 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1390 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1391 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
<> 144:ef7eb2e8f9f7 1392 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1393 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
<> 144:ef7eb2e8f9f7 1394 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1395 } while(0)
<> 144:ef7eb2e8f9f7 1396
<> 144:ef7eb2e8f9f7 1397 #define __HAL_RCC_MDIO_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1398 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1399 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
<> 144:ef7eb2e8f9f7 1400 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1401 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
<> 144:ef7eb2e8f9f7 1402 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1403 } while(0)
<> 144:ef7eb2e8f9f7 1404 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1405 #if defined (STM32F723xx) || defined (STM32F733xx)
<> 161:2cc1468da177 1406 #define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \
<> 161:2cc1468da177 1407 __IO uint32_t tmpreg; \
<> 161:2cc1468da177 1408 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\
<> 161:2cc1468da177 1409 /* Delay after an RCC peripheral clock enabling */ \
<> 161:2cc1468da177 1410 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\
<> 161:2cc1468da177 1411 UNUSED(tmpreg); \
<> 161:2cc1468da177 1412 } while(0)
<> 161:2cc1468da177 1413 #endif /* STM32F723xx || STM32F733xx */
<> 144:ef7eb2e8f9f7 1414
<> 144:ef7eb2e8f9f7 1415 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
<> 144:ef7eb2e8f9f7 1416 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
<> 144:ef7eb2e8f9f7 1417 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
<> 144:ef7eb2e8f9f7 1418 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
<> 161:2cc1468da177 1419 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1420 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1421 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))
<> 161:2cc1468da177 1422 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1423 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
<> 144:ef7eb2e8f9f7 1424 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
<> 144:ef7eb2e8f9f7 1425 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
<> 144:ef7eb2e8f9f7 1426 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
<> 144:ef7eb2e8f9f7 1427 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
<> 144:ef7eb2e8f9f7 1428 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
<> 144:ef7eb2e8f9f7 1429 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
<> 144:ef7eb2e8f9f7 1430 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
<> 144:ef7eb2e8f9f7 1431 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
<> 144:ef7eb2e8f9f7 1432 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
<> 144:ef7eb2e8f9f7 1433 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
<> 144:ef7eb2e8f9f7 1434 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
<> 144:ef7eb2e8f9f7 1435 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
<> 144:ef7eb2e8f9f7 1436 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1437 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
<> 144:ef7eb2e8f9f7 1438 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1439 #if defined (STM32F769xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1440 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
<> 144:ef7eb2e8f9f7 1441 #endif /* STM32F769xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1442 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 1443 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
<> 161:2cc1468da177 1444 #define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))
<> 144:ef7eb2e8f9f7 1445 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1446 #if defined (STM32F723xx) || defined (STM32F733xx)
<> 161:2cc1468da177 1447 #define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN))
<> 161:2cc1468da177 1448 #endif /* STM32F723xx || STM32F733xx */
<> 144:ef7eb2e8f9f7 1449
<> 144:ef7eb2e8f9f7 1450 /**
<> 144:ef7eb2e8f9f7 1451 * @}
<> 144:ef7eb2e8f9f7 1452 */
<> 144:ef7eb2e8f9f7 1453
<> 144:ef7eb2e8f9f7 1454
<> 144:ef7eb2e8f9f7 1455 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 1456 * @brief Get the enable or disable status of the AHB/APB peripheral clock.
<> 144:ef7eb2e8f9f7 1457 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1458 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1459 * using it.
<> 144:ef7eb2e8f9f7 1460 * @{
<> 144:ef7eb2e8f9f7 1461 */
<> 144:ef7eb2e8f9f7 1462
<> 144:ef7eb2e8f9f7 1463 /** @brief Get the enable or disable status of the AHB1 peripheral clock.
<> 144:ef7eb2e8f9f7 1464 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1465 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1466 * using it.
<> 144:ef7eb2e8f9f7 1467 */
<> 144:ef7eb2e8f9f7 1468 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
<> 144:ef7eb2e8f9f7 1469 #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
<> 144:ef7eb2e8f9f7 1470 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1471 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
<> 144:ef7eb2e8f9f7 1472 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
<> 144:ef7eb2e8f9f7 1473 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
<> 144:ef7eb2e8f9f7 1474 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
<> 144:ef7eb2e8f9f7 1475 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
<> 144:ef7eb2e8f9f7 1476 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
<> 144:ef7eb2e8f9f7 1477 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
<> 144:ef7eb2e8f9f7 1478 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
<> 144:ef7eb2e8f9f7 1479 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
<> 144:ef7eb2e8f9f7 1480 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
<> 144:ef7eb2e8f9f7 1481 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
<> 161:2cc1468da177 1482 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1483 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1484 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
<> 144:ef7eb2e8f9f7 1485 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
<> 161:2cc1468da177 1486 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
<> 161:2cc1468da177 1487 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
<> 144:ef7eb2e8f9f7 1490 #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
<> 144:ef7eb2e8f9f7 1491 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1492 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
<> 144:ef7eb2e8f9f7 1493 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
<> 144:ef7eb2e8f9f7 1494 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
<> 144:ef7eb2e8f9f7 1495 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
<> 144:ef7eb2e8f9f7 1496 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
<> 144:ef7eb2e8f9f7 1497 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
<> 144:ef7eb2e8f9f7 1498 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
<> 144:ef7eb2e8f9f7 1499 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
<> 144:ef7eb2e8f9f7 1500 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
<> 144:ef7eb2e8f9f7 1501 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
<> 144:ef7eb2e8f9f7 1502 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
<> 161:2cc1468da177 1503 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1504 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1505 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
<> 144:ef7eb2e8f9f7 1506 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
<> 161:2cc1468da177 1507 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
<> 161:2cc1468da177 1508 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1509
<> 161:2cc1468da177 1510 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1511 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1512 /**
<> 144:ef7eb2e8f9f7 1513 * @brief Enable ETHERNET clock.
<> 144:ef7eb2e8f9f7 1514 */
<> 144:ef7eb2e8f9f7 1515 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
<> 144:ef7eb2e8f9f7 1516 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
<> 144:ef7eb2e8f9f7 1517 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
<> 144:ef7eb2e8f9f7 1518 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
<> 144:ef7eb2e8f9f7 1519 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
<> 144:ef7eb2e8f9f7 1520 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
<> 144:ef7eb2e8f9f7 1521 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
<> 144:ef7eb2e8f9f7 1522
<> 144:ef7eb2e8f9f7 1523 /**
<> 144:ef7eb2e8f9f7 1524 * @brief Disable ETHERNET clock.
<> 144:ef7eb2e8f9f7 1525 */
<> 144:ef7eb2e8f9f7 1526 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
<> 144:ef7eb2e8f9f7 1527 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
<> 144:ef7eb2e8f9f7 1528 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
<> 144:ef7eb2e8f9f7 1529 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
<> 144:ef7eb2e8f9f7 1530 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
<> 144:ef7eb2e8f9f7 1531 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
<> 144:ef7eb2e8f9f7 1532 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
<> 161:2cc1468da177 1533 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1534
<> 144:ef7eb2e8f9f7 1535 /** @brief Get the enable or disable status of the AHB2 peripheral clock.
<> 144:ef7eb2e8f9f7 1536 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1537 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1538 * using it.
<> 144:ef7eb2e8f9f7 1539 */
<> 144:ef7eb2e8f9f7 1540 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
<> 144:ef7eb2e8f9f7 1541 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
<> 144:ef7eb2e8f9f7 1542
<> 144:ef7eb2e8f9f7 1543 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
<> 144:ef7eb2e8f9f7 1544 #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
<> 144:ef7eb2e8f9f7 1545
<> 144:ef7eb2e8f9f7 1546 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1547 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
<> 144:ef7eb2e8f9f7 1548 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
<> 144:ef7eb2e8f9f7 1549 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
<> 144:ef7eb2e8f9f7 1550 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
<> 144:ef7eb2e8f9f7 1551 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1552
<> 161:2cc1468da177 1553 #if defined(STM32F732xx) || defined (STM32F733xx)
<> 161:2cc1468da177 1554 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
<> 161:2cc1468da177 1555 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
<> 161:2cc1468da177 1556 #endif /* STM32F732xx || STM32F733xx */
<> 161:2cc1468da177 1557
<> 161:2cc1468da177 1558 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1559 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 1560 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
<> 161:2cc1468da177 1561 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
<> 161:2cc1468da177 1562 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1563
<> 144:ef7eb2e8f9f7 1564 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1565 #define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)
<> 144:ef7eb2e8f9f7 1566 #define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)
<> 144:ef7eb2e8f9f7 1567 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1568
<> 144:ef7eb2e8f9f7 1569 /** @brief Get the enable or disable status of the AHB3 peripheral clock.
<> 144:ef7eb2e8f9f7 1570 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1571 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1572 * using it.
<> 144:ef7eb2e8f9f7 1573 */
<> 144:ef7eb2e8f9f7 1574 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
<> 144:ef7eb2e8f9f7 1575 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
<> 144:ef7eb2e8f9f7 1576
<> 144:ef7eb2e8f9f7 1577 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
<> 144:ef7eb2e8f9f7 1578 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 /** @brief Get the enable or disable status of the APB1 peripheral clock.
<> 144:ef7eb2e8f9f7 1581 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1582 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1583 * using it.
<> 144:ef7eb2e8f9f7 1584 */
<> 144:ef7eb2e8f9f7 1585 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1586 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
<> 144:ef7eb2e8f9f7 1587 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
<> 144:ef7eb2e8f9f7 1588 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
<> 144:ef7eb2e8f9f7 1589 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
<> 144:ef7eb2e8f9f7 1590 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
<> 144:ef7eb2e8f9f7 1591 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
<> 144:ef7eb2e8f9f7 1592 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
<> 144:ef7eb2e8f9f7 1593 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
<> 144:ef7eb2e8f9f7 1594 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1595 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1596 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
<> 144:ef7eb2e8f9f7 1597 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1598 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1599 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
<> 144:ef7eb2e8f9f7 1600 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1601 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
<> 144:ef7eb2e8f9f7 1602 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
<> 144:ef7eb2e8f9f7 1603 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
<> 144:ef7eb2e8f9f7 1604 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1605 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1606 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
<> 144:ef7eb2e8f9f7 1607 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1608 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
<> 144:ef7eb2e8f9f7 1609 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
<> 144:ef7eb2e8f9f7 1610 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1613 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
<> 144:ef7eb2e8f9f7 1614 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
<> 144:ef7eb2e8f9f7 1615 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
<> 144:ef7eb2e8f9f7 1616 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
<> 144:ef7eb2e8f9f7 1617 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
<> 144:ef7eb2e8f9f7 1618 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
<> 144:ef7eb2e8f9f7 1619 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
<> 144:ef7eb2e8f9f7 1620 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
<> 144:ef7eb2e8f9f7 1621 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1622 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1623 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
<> 144:ef7eb2e8f9f7 1624 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1625 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1626 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
<> 144:ef7eb2e8f9f7 1627 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1628 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
<> 144:ef7eb2e8f9f7 1629 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
<> 144:ef7eb2e8f9f7 1630 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
<> 144:ef7eb2e8f9f7 1631 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1632 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1633 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
<> 144:ef7eb2e8f9f7 1634 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1635 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
<> 144:ef7eb2e8f9f7 1636 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
<> 144:ef7eb2e8f9f7 1637 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
<> 161:2cc1468da177 1638 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1639 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 1640 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
<> 161:2cc1468da177 1641 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
<> 161:2cc1468da177 1642 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
<> 161:2cc1468da177 1643 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
<> 161:2cc1468da177 1644
<> 161:2cc1468da177 1645 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
<> 161:2cc1468da177 1646 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
<> 161:2cc1468da177 1647 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
<> 161:2cc1468da177 1648 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
<> 161:2cc1468da177 1649 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1650
<> 161:2cc1468da177 1651 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
<> 161:2cc1468da177 1652 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
<> 161:2cc1468da177 1653 defined (STM32F779xx)
<> 161:2cc1468da177 1654 #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)
<> 161:2cc1468da177 1655 #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)
<> 161:2cc1468da177 1656 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
<> 161:2cc1468da177 1657 STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1658
<> 144:ef7eb2e8f9f7 1659 /** @brief Get the enable or disable status of the APB2 peripheral clock.
<> 144:ef7eb2e8f9f7 1660 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1661 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1662 * using it.
<> 144:ef7eb2e8f9f7 1663 */
<> 144:ef7eb2e8f9f7 1664 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1665 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
<> 144:ef7eb2e8f9f7 1666 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1667 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
<> 144:ef7eb2e8f9f7 1668 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1669 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1670 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
<> 144:ef7eb2e8f9f7 1671 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1672 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1673 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
<> 144:ef7eb2e8f9f7 1674 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
<> 144:ef7eb2e8f9f7 1675 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
<> 144:ef7eb2e8f9f7 1676 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
<> 144:ef7eb2e8f9f7 1677 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
<> 144:ef7eb2e8f9f7 1678 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
<> 144:ef7eb2e8f9f7 1679 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1680 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1681 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1682 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
<> 144:ef7eb2e8f9f7 1683 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1684 #if defined (STM32F769xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1685 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
<> 144:ef7eb2e8f9f7 1686 #endif /* STM32F769xx || STM32F779xx */
<> 161:2cc1468da177 1687 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1688 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1689 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)
<> 161:2cc1468da177 1690 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1691 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 1692 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1693 #define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)
<> 144:ef7eb2e8f9f7 1694 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1695 #if defined (STM32F723xx) || defined (STM32F733xx)
<> 161:2cc1468da177 1696 #define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET)
<> 161:2cc1468da177 1697 #endif /* STM32F723xx || STM32F733xx */
<> 161:2cc1468da177 1698
<> 144:ef7eb2e8f9f7 1699 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1700 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
<> 144:ef7eb2e8f9f7 1701 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1702 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
<> 144:ef7eb2e8f9f7 1703 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1704 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1705 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
<> 144:ef7eb2e8f9f7 1706 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1707 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1708 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
<> 144:ef7eb2e8f9f7 1709 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
<> 144:ef7eb2e8f9f7 1710 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
<> 144:ef7eb2e8f9f7 1711 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
<> 144:ef7eb2e8f9f7 1712 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
<> 144:ef7eb2e8f9f7 1713 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
<> 144:ef7eb2e8f9f7 1714 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1715 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1716 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1717 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
<> 144:ef7eb2e8f9f7 1718 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1719 #if defined (STM32F769xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1720 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
<> 144:ef7eb2e8f9f7 1721 #endif /* STM32F769xx || STM32F779xx */
<> 161:2cc1468da177 1722 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1723 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1724 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)
<> 161:2cc1468da177 1725 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1726 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 1727 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1728 #define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)
<> 144:ef7eb2e8f9f7 1729 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1730 #if defined (STM32F723xx) || defined (STM32F733xx)
<> 161:2cc1468da177 1731 #define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET)
<> 161:2cc1468da177 1732 #endif /* STM32F723xx || STM32F733xx */
<> 161:2cc1468da177 1733
<> 144:ef7eb2e8f9f7 1734 /**
<> 144:ef7eb2e8f9f7 1735 * @}
<> 144:ef7eb2e8f9f7 1736 */
<> 144:ef7eb2e8f9f7 1737
<> 144:ef7eb2e8f9f7 1738 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
<> 144:ef7eb2e8f9f7 1739 * @brief Forces or releases AHB/APB peripheral reset.
<> 144:ef7eb2e8f9f7 1740 * @{
<> 144:ef7eb2e8f9f7 1741 */
<> 144:ef7eb2e8f9f7 1742
<> 144:ef7eb2e8f9f7 1743 /** @brief Force or release AHB1 peripheral reset.
<> 144:ef7eb2e8f9f7 1744 */
<> 144:ef7eb2e8f9f7 1745 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
<> 144:ef7eb2e8f9f7 1746 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
<> 144:ef7eb2e8f9f7 1747 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
<> 144:ef7eb2e8f9f7 1748 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
<> 144:ef7eb2e8f9f7 1749 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
<> 144:ef7eb2e8f9f7 1750 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
<> 144:ef7eb2e8f9f7 1751 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
<> 144:ef7eb2e8f9f7 1752 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
<> 144:ef7eb2e8f9f7 1753 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
<> 144:ef7eb2e8f9f7 1754 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
<> 144:ef7eb2e8f9f7 1755 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
<> 144:ef7eb2e8f9f7 1756
<> 144:ef7eb2e8f9f7 1757 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
<> 144:ef7eb2e8f9f7 1758 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
<> 144:ef7eb2e8f9f7 1759 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
<> 144:ef7eb2e8f9f7 1760 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
<> 144:ef7eb2e8f9f7 1761 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
<> 144:ef7eb2e8f9f7 1762 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
<> 144:ef7eb2e8f9f7 1763 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
<> 144:ef7eb2e8f9f7 1764 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
<> 144:ef7eb2e8f9f7 1765 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
<> 144:ef7eb2e8f9f7 1766 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
<> 144:ef7eb2e8f9f7 1767 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
<> 161:2cc1468da177 1768
<> 161:2cc1468da177 1769 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1770 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 1771 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
<> 161:2cc1468da177 1772 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
<> 161:2cc1468da177 1773 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
<> 161:2cc1468da177 1774 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
<> 161:2cc1468da177 1775
<> 161:2cc1468da177 1776 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
<> 161:2cc1468da177 1777 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
<> 144:ef7eb2e8f9f7 1778 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
<> 144:ef7eb2e8f9f7 1779 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
<> 161:2cc1468da177 1780 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1781
<> 144:ef7eb2e8f9f7 1782 /** @brief Force or release AHB2 peripheral reset.
<> 144:ef7eb2e8f9f7 1783 */
<> 144:ef7eb2e8f9f7 1784 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1785 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
<> 144:ef7eb2e8f9f7 1786 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
<> 144:ef7eb2e8f9f7 1787
<> 144:ef7eb2e8f9f7 1788 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
<> 144:ef7eb2e8f9f7 1789 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
<> 144:ef7eb2e8f9f7 1790 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
<> 144:ef7eb2e8f9f7 1791
<> 144:ef7eb2e8f9f7 1792 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1793 #define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST))
<> 144:ef7eb2e8f9f7 1794 #define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))
<> 144:ef7eb2e8f9f7 1795 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1796
<> 144:ef7eb2e8f9f7 1797 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1798 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
<> 144:ef7eb2e8f9f7 1799 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
<> 144:ef7eb2e8f9f7 1800 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
<> 144:ef7eb2e8f9f7 1801 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
<> 144:ef7eb2e8f9f7 1802 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1803
<> 161:2cc1468da177 1804 #if defined(STM32F732xx) || defined (STM32F733xx)
<> 161:2cc1468da177 1805 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))
<> 161:2cc1468da177 1806 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
<> 161:2cc1468da177 1807 #endif /* STM32F732xx || STM32F733xx */
<> 161:2cc1468da177 1808
<> 161:2cc1468da177 1809 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1810 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 1811 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
<> 161:2cc1468da177 1812 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
<> 161:2cc1468da177 1813 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1814
<> 144:ef7eb2e8f9f7 1815 /** @brief Force or release AHB3 peripheral reset
<> 144:ef7eb2e8f9f7 1816 */
<> 144:ef7eb2e8f9f7 1817 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1818 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
<> 144:ef7eb2e8f9f7 1819 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
<> 144:ef7eb2e8f9f7 1820
<> 144:ef7eb2e8f9f7 1821 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
<> 144:ef7eb2e8f9f7 1822 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
<> 144:ef7eb2e8f9f7 1823 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
<> 144:ef7eb2e8f9f7 1824
<> 144:ef7eb2e8f9f7 1825 /** @brief Force or release APB1 peripheral reset.
<> 144:ef7eb2e8f9f7 1826 */
<> 144:ef7eb2e8f9f7 1827 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
<> 144:ef7eb2e8f9f7 1828 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
<> 144:ef7eb2e8f9f7 1829 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
<> 144:ef7eb2e8f9f7 1830 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
<> 144:ef7eb2e8f9f7 1831 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
<> 144:ef7eb2e8f9f7 1832 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
<> 144:ef7eb2e8f9f7 1833 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
<> 144:ef7eb2e8f9f7 1834 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
<> 144:ef7eb2e8f9f7 1835 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
<> 144:ef7eb2e8f9f7 1836 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
<> 144:ef7eb2e8f9f7 1837 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1838 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
<> 144:ef7eb2e8f9f7 1839 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1840 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
<> 144:ef7eb2e8f9f7 1841 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
<> 144:ef7eb2e8f9f7 1842 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
<> 144:ef7eb2e8f9f7 1843 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
<> 144:ef7eb2e8f9f7 1844 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
<> 144:ef7eb2e8f9f7 1845 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
<> 144:ef7eb2e8f9f7 1846 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
<> 144:ef7eb2e8f9f7 1847 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
<> 144:ef7eb2e8f9f7 1848 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
<> 144:ef7eb2e8f9f7 1849 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
<> 144:ef7eb2e8f9f7 1850 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
<> 144:ef7eb2e8f9f7 1851 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
<> 144:ef7eb2e8f9f7 1852 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
<> 144:ef7eb2e8f9f7 1853
<> 144:ef7eb2e8f9f7 1854 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
<> 144:ef7eb2e8f9f7 1855 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
<> 144:ef7eb2e8f9f7 1856 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
<> 144:ef7eb2e8f9f7 1857 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
<> 144:ef7eb2e8f9f7 1858 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
<> 144:ef7eb2e8f9f7 1859 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
<> 144:ef7eb2e8f9f7 1860 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
<> 144:ef7eb2e8f9f7 1861 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
<> 144:ef7eb2e8f9f7 1862 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
<> 144:ef7eb2e8f9f7 1863 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
<> 144:ef7eb2e8f9f7 1864 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1865 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
<> 144:ef7eb2e8f9f7 1866 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1867 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
<> 144:ef7eb2e8f9f7 1868 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
<> 144:ef7eb2e8f9f7 1869 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
<> 144:ef7eb2e8f9f7 1870 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
<> 144:ef7eb2e8f9f7 1871 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
<> 144:ef7eb2e8f9f7 1872 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
<> 144:ef7eb2e8f9f7 1873 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
<> 144:ef7eb2e8f9f7 1874 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
<> 144:ef7eb2e8f9f7 1875 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
<> 144:ef7eb2e8f9f7 1876 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
<> 144:ef7eb2e8f9f7 1877 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
<> 144:ef7eb2e8f9f7 1878 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
<> 144:ef7eb2e8f9f7 1879 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
<> 144:ef7eb2e8f9f7 1880
<> 161:2cc1468da177 1881 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1882 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 1883 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
<> 161:2cc1468da177 1884 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
<> 161:2cc1468da177 1885 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
<> 161:2cc1468da177 1886 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
<> 161:2cc1468da177 1887
<> 161:2cc1468da177 1888 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
<> 161:2cc1468da177 1889 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
<> 161:2cc1468da177 1890 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
<> 161:2cc1468da177 1891 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
<> 161:2cc1468da177 1892 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1893
<> 144:ef7eb2e8f9f7 1894 /** @brief Force or release APB2 peripheral reset.
<> 144:ef7eb2e8f9f7 1895 */
<> 144:ef7eb2e8f9f7 1896 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
<> 144:ef7eb2e8f9f7 1897 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
<> 144:ef7eb2e8f9f7 1898 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
<> 144:ef7eb2e8f9f7 1899 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
<> 144:ef7eb2e8f9f7 1900 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
<> 144:ef7eb2e8f9f7 1901 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
<> 144:ef7eb2e8f9f7 1902 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
<> 144:ef7eb2e8f9f7 1903 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
<> 144:ef7eb2e8f9f7 1904 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
<> 144:ef7eb2e8f9f7 1905 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
<> 144:ef7eb2e8f9f7 1906 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
<> 144:ef7eb2e8f9f7 1907 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
<> 144:ef7eb2e8f9f7 1908 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
<> 144:ef7eb2e8f9f7 1909 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
<> 144:ef7eb2e8f9f7 1910 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
<> 144:ef7eb2e8f9f7 1911 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1912 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
<> 144:ef7eb2e8f9f7 1913 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1914 #if defined (STM32F723xx) || defined (STM32F733xx)
<> 161:2cc1468da177 1915 #define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST))
<> 161:2cc1468da177 1916 #endif /* STM32F723xx || STM32F733xx */
<> 144:ef7eb2e8f9f7 1917
<> 144:ef7eb2e8f9f7 1918 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
<> 144:ef7eb2e8f9f7 1919 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
<> 144:ef7eb2e8f9f7 1920 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
<> 144:ef7eb2e8f9f7 1921 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
<> 144:ef7eb2e8f9f7 1922 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
<> 144:ef7eb2e8f9f7 1923 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
<> 144:ef7eb2e8f9f7 1924 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
<> 144:ef7eb2e8f9f7 1925 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
<> 144:ef7eb2e8f9f7 1926 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
<> 144:ef7eb2e8f9f7 1927 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
<> 144:ef7eb2e8f9f7 1928 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
<> 144:ef7eb2e8f9f7 1929 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
<> 144:ef7eb2e8f9f7 1930 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
<> 144:ef7eb2e8f9f7 1931 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
<> 144:ef7eb2e8f9f7 1932 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
<> 144:ef7eb2e8f9f7 1933 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1934 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
<> 144:ef7eb2e8f9f7 1935 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1936 #if defined (STM32F723xx) || defined (STM32F733xx)
<> 161:2cc1468da177 1937 #define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST))
<> 161:2cc1468da177 1938 #endif /* STM32F723xx || STM32F733xx */
<> 144:ef7eb2e8f9f7 1939
<> 144:ef7eb2e8f9f7 1940 #if defined (STM32F769xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1941 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
<> 144:ef7eb2e8f9f7 1942 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
<> 144:ef7eb2e8f9f7 1943 #endif /* STM32F769xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1944
<> 161:2cc1468da177 1945 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 1946 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 1947 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST))
<> 161:2cc1468da177 1948 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))
<> 161:2cc1468da177 1949 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1950
<> 144:ef7eb2e8f9f7 1951 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 1952 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
<> 144:ef7eb2e8f9f7 1953 #define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST))
<> 144:ef7eb2e8f9f7 1954 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
<> 144:ef7eb2e8f9f7 1955 #define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))
<> 144:ef7eb2e8f9f7 1956 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1957 /**
<> 144:ef7eb2e8f9f7 1958 * @}
<> 144:ef7eb2e8f9f7 1959 */
<> 144:ef7eb2e8f9f7 1960
<> 144:ef7eb2e8f9f7 1961 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
<> 144:ef7eb2e8f9f7 1962 * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 1963 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 1964 * power consumption.
<> 144:ef7eb2e8f9f7 1965 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 1966 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 1967 * @{
<> 144:ef7eb2e8f9f7 1968 */
<> 144:ef7eb2e8f9f7 1969
<> 144:ef7eb2e8f9f7 1970 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 1971 */
<> 144:ef7eb2e8f9f7 1972 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
<> 144:ef7eb2e8f9f7 1973 #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
<> 144:ef7eb2e8f9f7 1974 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
<> 144:ef7eb2e8f9f7 1975 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
<> 144:ef7eb2e8f9f7 1976 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
<> 144:ef7eb2e8f9f7 1977 #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
<> 144:ef7eb2e8f9f7 1978 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
<> 144:ef7eb2e8f9f7 1979 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
<> 144:ef7eb2e8f9f7 1980 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
<> 144:ef7eb2e8f9f7 1981 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
<> 144:ef7eb2e8f9f7 1982 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
<> 144:ef7eb2e8f9f7 1983 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
<> 144:ef7eb2e8f9f7 1984 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
<> 144:ef7eb2e8f9f7 1985 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
<> 144:ef7eb2e8f9f7 1986 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
<> 144:ef7eb2e8f9f7 1987 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
<> 144:ef7eb2e8f9f7 1988 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
<> 144:ef7eb2e8f9f7 1989 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
<> 144:ef7eb2e8f9f7 1990
<> 144:ef7eb2e8f9f7 1991 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
<> 144:ef7eb2e8f9f7 1992 #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
<> 144:ef7eb2e8f9f7 1993 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
<> 144:ef7eb2e8f9f7 1994 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
<> 144:ef7eb2e8f9f7 1995 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
<> 144:ef7eb2e8f9f7 1996 #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
<> 144:ef7eb2e8f9f7 1997 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
<> 144:ef7eb2e8f9f7 1998 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
<> 144:ef7eb2e8f9f7 1999 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
<> 144:ef7eb2e8f9f7 2000 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
<> 144:ef7eb2e8f9f7 2001 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
<> 144:ef7eb2e8f9f7 2002 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
<> 144:ef7eb2e8f9f7 2003 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
<> 144:ef7eb2e8f9f7 2004 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
<> 144:ef7eb2e8f9f7 2005 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
<> 144:ef7eb2e8f9f7 2006 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
<> 144:ef7eb2e8f9f7 2007 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
<> 144:ef7eb2e8f9f7 2008 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
<> 161:2cc1468da177 2009
<> 161:2cc1468da177 2010 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 2011 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 2012 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
<> 161:2cc1468da177 2013 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
<> 161:2cc1468da177 2014 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
<> 161:2cc1468da177 2015 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
<> 161:2cc1468da177 2016 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
<> 161:2cc1468da177 2017 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
<> 161:2cc1468da177 2018 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
<> 161:2cc1468da177 2019
<> 161:2cc1468da177 2020 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
<> 161:2cc1468da177 2021 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
<> 161:2cc1468da177 2022 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
<> 161:2cc1468da177 2023 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
<> 161:2cc1468da177 2024 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
<> 144:ef7eb2e8f9f7 2025 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
<> 144:ef7eb2e8f9f7 2026 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
<> 161:2cc1468da177 2027 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2028
<> 144:ef7eb2e8f9f7 2029 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 2030 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 2031 * power consumption.
<> 144:ef7eb2e8f9f7 2032 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 2033 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 2034 */
<> 161:2cc1468da177 2035 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 2036 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2037 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
<> 144:ef7eb2e8f9f7 2038 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
<> 161:2cc1468da177 2039 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2040
<> 144:ef7eb2e8f9f7 2041 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2042 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN))
<> 144:ef7eb2e8f9f7 2043 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))
<> 144:ef7eb2e8f9f7 2044 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2045
<> 144:ef7eb2e8f9f7 2046 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
<> 144:ef7eb2e8f9f7 2047 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
<> 144:ef7eb2e8f9f7 2048
<> 144:ef7eb2e8f9f7 2049 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
<> 144:ef7eb2e8f9f7 2050 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
<> 144:ef7eb2e8f9f7 2051
<> 144:ef7eb2e8f9f7 2052 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2053 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
<> 144:ef7eb2e8f9f7 2054 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
<> 144:ef7eb2e8f9f7 2055
<> 144:ef7eb2e8f9f7 2056 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
<> 144:ef7eb2e8f9f7 2057 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
<> 144:ef7eb2e8f9f7 2058 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 2059
<> 161:2cc1468da177 2060 #if defined(STM32F732xx) || defined (STM32F733xx)
<> 161:2cc1468da177 2061 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))
<> 161:2cc1468da177 2062 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
<> 161:2cc1468da177 2063 #endif /* STM32F732xx || STM32F733xx */
<> 144:ef7eb2e8f9f7 2064
<> 144:ef7eb2e8f9f7 2065 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 2066 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 2067 * power consumption.
<> 144:ef7eb2e8f9f7 2068 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 2069 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 2070 */
<> 144:ef7eb2e8f9f7 2071 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
<> 144:ef7eb2e8f9f7 2072 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
<> 144:ef7eb2e8f9f7 2073
<> 144:ef7eb2e8f9f7 2074 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
<> 144:ef7eb2e8f9f7 2075 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
<> 144:ef7eb2e8f9f7 2076
<> 144:ef7eb2e8f9f7 2077 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 2078 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 2079 * power consumption.
<> 144:ef7eb2e8f9f7 2080 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 2081 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 2082 */
<> 144:ef7eb2e8f9f7 2083 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
<> 144:ef7eb2e8f9f7 2084 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
<> 144:ef7eb2e8f9f7 2085 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
<> 144:ef7eb2e8f9f7 2086 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
<> 144:ef7eb2e8f9f7 2087 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
<> 144:ef7eb2e8f9f7 2088 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
<> 144:ef7eb2e8f9f7 2089 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
<> 144:ef7eb2e8f9f7 2090 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
<> 144:ef7eb2e8f9f7 2091 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
<> 144:ef7eb2e8f9f7 2092 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
<> 144:ef7eb2e8f9f7 2093 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2094 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
<> 144:ef7eb2e8f9f7 2095 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2096 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
<> 144:ef7eb2e8f9f7 2097 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
<> 144:ef7eb2e8f9f7 2098 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
<> 144:ef7eb2e8f9f7 2099 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
<> 144:ef7eb2e8f9f7 2100 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
<> 144:ef7eb2e8f9f7 2101 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
<> 144:ef7eb2e8f9f7 2102 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
<> 144:ef7eb2e8f9f7 2103 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
<> 144:ef7eb2e8f9f7 2104 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
<> 144:ef7eb2e8f9f7 2105 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
<> 144:ef7eb2e8f9f7 2106 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
<> 144:ef7eb2e8f9f7 2107 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
<> 144:ef7eb2e8f9f7 2108 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
<> 144:ef7eb2e8f9f7 2109
<> 144:ef7eb2e8f9f7 2110 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
<> 144:ef7eb2e8f9f7 2111 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
<> 144:ef7eb2e8f9f7 2112 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
<> 144:ef7eb2e8f9f7 2113 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
<> 144:ef7eb2e8f9f7 2114 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
<> 144:ef7eb2e8f9f7 2115 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
<> 144:ef7eb2e8f9f7 2116 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
<> 144:ef7eb2e8f9f7 2117 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
<> 144:ef7eb2e8f9f7 2118 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
<> 144:ef7eb2e8f9f7 2119 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
<> 144:ef7eb2e8f9f7 2120 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2121 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
<> 144:ef7eb2e8f9f7 2122 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2123 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
<> 144:ef7eb2e8f9f7 2124 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
<> 144:ef7eb2e8f9f7 2125 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
<> 144:ef7eb2e8f9f7 2126 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
<> 144:ef7eb2e8f9f7 2127 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
<> 144:ef7eb2e8f9f7 2128 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
<> 144:ef7eb2e8f9f7 2129 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
<> 144:ef7eb2e8f9f7 2130 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
<> 144:ef7eb2e8f9f7 2131 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
<> 144:ef7eb2e8f9f7 2132 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
<> 144:ef7eb2e8f9f7 2133 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
<> 144:ef7eb2e8f9f7 2134 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
<> 144:ef7eb2e8f9f7 2135 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
<> 144:ef7eb2e8f9f7 2136
<> 161:2cc1468da177 2137 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
<> 161:2cc1468da177 2138 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
<> 161:2cc1468da177 2139 defined (STM32F779xx)
<> 161:2cc1468da177 2140 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN))
<> 161:2cc1468da177 2141 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))
<> 161:2cc1468da177 2142 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
<> 161:2cc1468da177 2143 STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 2144
<> 161:2cc1468da177 2145 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 2146 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 2147 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
<> 161:2cc1468da177 2148 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
<> 161:2cc1468da177 2149 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
<> 161:2cc1468da177 2150 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
<> 161:2cc1468da177 2151
<> 161:2cc1468da177 2152 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
<> 161:2cc1468da177 2153 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
<> 161:2cc1468da177 2154 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
<> 161:2cc1468da177 2155 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
<> 161:2cc1468da177 2156 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 2157
<> 144:ef7eb2e8f9f7 2158 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 2159 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 2160 * power consumption.
<> 144:ef7eb2e8f9f7 2161 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 2162 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 2163 */
<> 144:ef7eb2e8f9f7 2164 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
<> 144:ef7eb2e8f9f7 2165 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
<> 144:ef7eb2e8f9f7 2166 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
<> 144:ef7eb2e8f9f7 2167 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
<> 144:ef7eb2e8f9f7 2168 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
<> 144:ef7eb2e8f9f7 2169 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
<> 144:ef7eb2e8f9f7 2170 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
<> 144:ef7eb2e8f9f7 2171 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
<> 144:ef7eb2e8f9f7 2172 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
<> 144:ef7eb2e8f9f7 2173 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
<> 144:ef7eb2e8f9f7 2174 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
<> 144:ef7eb2e8f9f7 2175 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
<> 144:ef7eb2e8f9f7 2176 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
<> 144:ef7eb2e8f9f7 2177 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
<> 144:ef7eb2e8f9f7 2178 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
<> 144:ef7eb2e8f9f7 2179 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
<> 144:ef7eb2e8f9f7 2180 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2181 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
<> 144:ef7eb2e8f9f7 2182 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2183
<> 144:ef7eb2e8f9f7 2184 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
<> 144:ef7eb2e8f9f7 2185 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
<> 144:ef7eb2e8f9f7 2186 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
<> 144:ef7eb2e8f9f7 2187 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
<> 144:ef7eb2e8f9f7 2188 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
<> 144:ef7eb2e8f9f7 2189 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
<> 144:ef7eb2e8f9f7 2190 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
<> 144:ef7eb2e8f9f7 2191 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
<> 144:ef7eb2e8f9f7 2192 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
<> 144:ef7eb2e8f9f7 2193 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
<> 144:ef7eb2e8f9f7 2194 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
<> 144:ef7eb2e8f9f7 2195 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
<> 144:ef7eb2e8f9f7 2196 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
<> 144:ef7eb2e8f9f7 2197 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
<> 144:ef7eb2e8f9f7 2198 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
<> 144:ef7eb2e8f9f7 2199 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
<> 144:ef7eb2e8f9f7 2200 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2201 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
<> 144:ef7eb2e8f9f7 2202 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2203 #if defined (STM32F769xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2204 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
<> 144:ef7eb2e8f9f7 2205 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
<> 144:ef7eb2e8f9f7 2206 #endif /* STM32F769xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2207 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2208 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
<> 144:ef7eb2e8f9f7 2209 #define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN))
<> 144:ef7eb2e8f9f7 2210 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
<> 144:ef7eb2e8f9f7 2211 #define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))
<> 144:ef7eb2e8f9f7 2212 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 2213 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 2214 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 2215 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN))
<> 161:2cc1468da177 2216 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))
<> 161:2cc1468da177 2217 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 2218
<> 161:2cc1468da177 2219 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 2220 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 2221 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
<> 161:2cc1468da177 2222 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
<> 161:2cc1468da177 2223 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2224 /**
<> 144:ef7eb2e8f9f7 2225 * @}
<> 144:ef7eb2e8f9f7 2226 */
<> 144:ef7eb2e8f9f7 2227
<> 144:ef7eb2e8f9f7 2228 /** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
<> 144:ef7eb2e8f9f7 2229 * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 2230 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 2231 * power consumption.
<> 144:ef7eb2e8f9f7 2232 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 2233 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 2234 * @{
<> 144:ef7eb2e8f9f7 2235 */
<> 144:ef7eb2e8f9f7 2236
<> 144:ef7eb2e8f9f7 2237 /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 2238 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 2239 * power consumption.
<> 144:ef7eb2e8f9f7 2240 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 2241 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 2242 */
<> 144:ef7eb2e8f9f7 2243 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2244 #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2245 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2246 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2247 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2248 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2249 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2250 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2251 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2252 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2253 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2254 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2255 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2256 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2257 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2258 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2259 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2260 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2261
<> 144:ef7eb2e8f9f7 2262 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2263 #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2264 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2265 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2266 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2267 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2268 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2269 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2270 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2271 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2272 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2273 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2274 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2275 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2276 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2277 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2278 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2279 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
<> 161:2cc1468da177 2280
<> 161:2cc1468da177 2281 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 2282 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 2283 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
<> 161:2cc1468da177 2284 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
<> 161:2cc1468da177 2285 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
<> 161:2cc1468da177 2286 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
<> 161:2cc1468da177 2287 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
<> 161:2cc1468da177 2288 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
<> 161:2cc1468da177 2289 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
<> 161:2cc1468da177 2290
<> 161:2cc1468da177 2291 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
<> 161:2cc1468da177 2292 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
<> 161:2cc1468da177 2293 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
<> 161:2cc1468da177 2294 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
<> 161:2cc1468da177 2295 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2296 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2297 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
<> 161:2cc1468da177 2298 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2299
<> 144:ef7eb2e8f9f7 2300 /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 2301 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 2302 * power consumption.
<> 144:ef7eb2e8f9f7 2303 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 2304 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 2305 */
<> 161:2cc1468da177 2306 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 2307 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2308 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2309 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
<> 161:2cc1468da177 2310 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2311
<> 144:ef7eb2e8f9f7 2312 #if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2313 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2314 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2315 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2316
<> 144:ef7eb2e8f9f7 2317 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2318 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2319
<> 144:ef7eb2e8f9f7 2320 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2321 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2322
<> 144:ef7eb2e8f9f7 2323 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2324 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2325 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2326
<> 144:ef7eb2e8f9f7 2327 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2328 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2329 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 2330
<> 161:2cc1468da177 2331 #if defined(STM32F732xx) || defined (STM32F733xx)
<> 161:2cc1468da177 2332 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET)
<> 161:2cc1468da177 2333 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET)
<> 161:2cc1468da177 2334 #endif /* STM32F732xx || STM32F733xx */
<> 144:ef7eb2e8f9f7 2335
<> 144:ef7eb2e8f9f7 2336 /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 2337 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 2338 * power consumption.
<> 144:ef7eb2e8f9f7 2339 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 2340 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 2341 */
<> 144:ef7eb2e8f9f7 2342 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2343 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2344
<> 144:ef7eb2e8f9f7 2345 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2346 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2347
<> 144:ef7eb2e8f9f7 2348 /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 2349 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 2350 * power consumption.
<> 144:ef7eb2e8f9f7 2351 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 2352 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 2353 */
<> 144:ef7eb2e8f9f7 2354 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2355 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2356 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2357 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2358 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2359 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2360 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2361 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2362 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2363 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
<> 161:2cc1468da177 2364 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
<> 161:2cc1468da177 2365 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
<> 161:2cc1468da177 2366 defined (STM32F779xx)
<> 161:2cc1468da177 2367 #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)
<> 161:2cc1468da177 2368 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
<> 161:2cc1468da177 2369 STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2370 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2371 #define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2372 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2373 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2374 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2375 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2376 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2377 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2378 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2379 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2380 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2381 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2382 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2383 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2384 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2385 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2386
<> 144:ef7eb2e8f9f7 2387 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2388 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2389 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2390 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2391 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2392 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2393 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2394 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2395 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2396 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
<> 161:2cc1468da177 2397 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
<> 161:2cc1468da177 2398 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
<> 161:2cc1468da177 2399 defined (STM32F779xx)
<> 161:2cc1468da177 2400 #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)
<> 161:2cc1468da177 2401 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
<> 161:2cc1468da177 2402 STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2403 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2404 #define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2405 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2406 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2407 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2408 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2409 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2410 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2411 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2412 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2413 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2414 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2415 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2416 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2417 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2418 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2419
<> 161:2cc1468da177 2420 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 2421 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 2422 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
<> 161:2cc1468da177 2423 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
<> 161:2cc1468da177 2424 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
<> 161:2cc1468da177 2425 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
<> 161:2cc1468da177 2426
<> 161:2cc1468da177 2427 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
<> 161:2cc1468da177 2428 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
<> 161:2cc1468da177 2429 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
<> 161:2cc1468da177 2430 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
<> 161:2cc1468da177 2431 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 2432
<> 144:ef7eb2e8f9f7 2433 /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 2434 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 2435 * power consumption.
<> 144:ef7eb2e8f9f7 2436 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 2437 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 2438 */
<> 144:ef7eb2e8f9f7 2439 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2440 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2441 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2442 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2443 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2444 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2445 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2446 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2447 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2448 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2449 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2450 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2451 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2452 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2453 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2454 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2455 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2456 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2457 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2458 #if defined (STM32F769xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2459 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2460 #endif /* STM32F769xx || STM32F779xx */
<> 161:2cc1468da177 2461 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 2462 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 2463 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)
<> 161:2cc1468da177 2464 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2465 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2466 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2467 #define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)
<> 144:ef7eb2e8f9f7 2468 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2469
<> 144:ef7eb2e8f9f7 2470 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2471 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2472 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2473 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2474 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2475 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2476 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2477 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2478 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2479 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2480 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2481 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2482 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2483 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2484 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2485 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2486 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2487 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2488 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2489 #if defined (STM32F769xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2490 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2491 #endif /* STM32F769xx || STM32F779xx */
<> 161:2cc1468da177 2492 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 2493 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 2494 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)
<> 161:2cc1468da177 2495 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2496 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2497 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2498 #define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)
<> 144:ef7eb2e8f9f7 2499 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 2500
<> 161:2cc1468da177 2501 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 2502 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 2503 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
<> 161:2cc1468da177 2504 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
<> 161:2cc1468da177 2505 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2506 /**
<> 144:ef7eb2e8f9f7 2507 * @}
<> 144:ef7eb2e8f9f7 2508 */
<> 144:ef7eb2e8f9f7 2509
<> 144:ef7eb2e8f9f7 2510 /*------------------------------- PLL Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 2511 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2512 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
<> 144:ef7eb2e8f9f7 2513 * @note This function must be used only when the main PLL is disabled.
<> 144:ef7eb2e8f9f7 2514 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
<> 144:ef7eb2e8f9f7 2515 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2516 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
<> 144:ef7eb2e8f9f7 2517 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
<> 144:ef7eb2e8f9f7 2518 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
<> 144:ef7eb2e8f9f7 2519 * @param __PLLM__: specifies the division factor for PLL VCO input clock
<> 144:ef7eb2e8f9f7 2520 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
<> 144:ef7eb2e8f9f7 2521 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
<> 144:ef7eb2e8f9f7 2522 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
<> 144:ef7eb2e8f9f7 2523 * of 2 MHz to limit PLL jitter.
<> 144:ef7eb2e8f9f7 2524 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
<> 144:ef7eb2e8f9f7 2525 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<> 144:ef7eb2e8f9f7 2526 * @note You have to set the PLLN parameter correctly to ensure that the VCO
<> 144:ef7eb2e8f9f7 2527 * output frequency is between 100 and 432 MHz.
<> 144:ef7eb2e8f9f7 2528 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
<> 144:ef7eb2e8f9f7 2529 * This parameter must be a number in the range {2, 4, 6, or 8}.
<> 144:ef7eb2e8f9f7 2530 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
<> 144:ef7eb2e8f9f7 2531 * the System clock frequency.
<> 144:ef7eb2e8f9f7 2532 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
<> 144:ef7eb2e8f9f7 2533 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 2534 * @note If the USB OTG FS is used in your application, you have to set the
<> 144:ef7eb2e8f9f7 2535 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
<> 144:ef7eb2e8f9f7 2536 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
<> 144:ef7eb2e8f9f7 2537 * correctly.
<> 144:ef7eb2e8f9f7 2538 * @param __PLLR__: specifies the division factor for DSI clock
<> 144:ef7eb2e8f9f7 2539 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<> 144:ef7eb2e8f9f7 2540 */
<> 144:ef7eb2e8f9f7 2541 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
<> 144:ef7eb2e8f9f7 2542 (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
<> 144:ef7eb2e8f9f7 2543 ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
<> 144:ef7eb2e8f9f7 2544 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
<> 144:ef7eb2e8f9f7 2545 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \
<> 144:ef7eb2e8f9f7 2546 ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
<> 144:ef7eb2e8f9f7 2547 #else
<> 144:ef7eb2e8f9f7 2548 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
<> 144:ef7eb2e8f9f7 2549 * @note This function must be used only when the main PLL is disabled.
<> 144:ef7eb2e8f9f7 2550 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
<> 144:ef7eb2e8f9f7 2551 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2552 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
<> 144:ef7eb2e8f9f7 2553 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
<> 144:ef7eb2e8f9f7 2554 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
<> 144:ef7eb2e8f9f7 2555 * @param __PLLM__: specifies the division factor for PLL VCO input clock
<> 144:ef7eb2e8f9f7 2556 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
<> 144:ef7eb2e8f9f7 2557 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
<> 144:ef7eb2e8f9f7 2558 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
<> 144:ef7eb2e8f9f7 2559 * of 2 MHz to limit PLL jitter.
<> 144:ef7eb2e8f9f7 2560 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
<> 144:ef7eb2e8f9f7 2561 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<> 144:ef7eb2e8f9f7 2562 * @note You have to set the PLLN parameter correctly to ensure that the VCO
<> 144:ef7eb2e8f9f7 2563 * output frequency is between 100 and 432 MHz.
<> 144:ef7eb2e8f9f7 2564 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
<> 144:ef7eb2e8f9f7 2565 * This parameter must be a number in the range {2, 4, 6, or 8}.
<> 144:ef7eb2e8f9f7 2566 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
<> 144:ef7eb2e8f9f7 2567 * the System clock frequency.
<> 144:ef7eb2e8f9f7 2568 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
<> 144:ef7eb2e8f9f7 2569 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 2570 * @note If the USB OTG FS is used in your application, you have to set the
<> 144:ef7eb2e8f9f7 2571 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
<> 144:ef7eb2e8f9f7 2572 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
<> 144:ef7eb2e8f9f7 2573 * correctly.
<> 144:ef7eb2e8f9f7 2574 */
<> 144:ef7eb2e8f9f7 2575 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
<> 144:ef7eb2e8f9f7 2576 (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
<> 144:ef7eb2e8f9f7 2577 ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
<> 144:ef7eb2e8f9f7 2578 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
<> 144:ef7eb2e8f9f7 2579 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
<> 144:ef7eb2e8f9f7 2580 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2581 /*---------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 2582
<> 144:ef7eb2e8f9f7 2583 /** @brief Macro to configure the Timers clocks prescalers
<> 144:ef7eb2e8f9f7 2584 * @param __PRESC__ : specifies the Timers clocks prescalers selection
<> 144:ef7eb2e8f9f7 2585 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2586 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
<> 144:ef7eb2e8f9f7 2587 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
<> 144:ef7eb2e8f9f7 2588 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
<> 144:ef7eb2e8f9f7 2589 * division by 4 or more.
<> 144:ef7eb2e8f9f7 2590 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
<> 144:ef7eb2e8f9f7 2591 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
<> 144:ef7eb2e8f9f7 2592 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
<> 144:ef7eb2e8f9f7 2593 * to division by 8 or more.
<> 144:ef7eb2e8f9f7 2594 */
<> 144:ef7eb2e8f9f7 2595 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
<> 144:ef7eb2e8f9f7 2596 RCC->DCKCFGR1 |= (__PRESC__); \
<> 144:ef7eb2e8f9f7 2597 }while(0)
<> 144:ef7eb2e8f9f7 2598
<> 144:ef7eb2e8f9f7 2599 /** @brief Macros to Enable or Disable the PLLISAI.
<> 144:ef7eb2e8f9f7 2600 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
<> 144:ef7eb2e8f9f7 2601 */
<> 144:ef7eb2e8f9f7 2602 #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
<> 144:ef7eb2e8f9f7 2603 #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
<> 144:ef7eb2e8f9f7 2604
<> 161:2cc1468da177 2605 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx)
<> 161:2cc1468da177 2606 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
<> 161:2cc1468da177 2607 * @note This function must be used only when the PLLSAI is disabled.
<> 161:2cc1468da177 2608 * @note PLLSAI clock source is common with the main PLL (configured in
<> 161:2cc1468da177 2609 * RCC_PLLConfig function )
<> 161:2cc1468da177 2610 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
<> 161:2cc1468da177 2611 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<> 161:2cc1468da177 2612 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
<> 161:2cc1468da177 2613 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
<> 161:2cc1468da177 2614 * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
<> 161:2cc1468da177 2615 * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
<> 161:2cc1468da177 2616 * @param __PLLSAIQ__: specifies the division factor for SAI clock
<> 161:2cc1468da177 2617 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<> 161:2cc1468da177 2618 */
<> 161:2cc1468da177 2619 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \
<> 161:2cc1468da177 2620 (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
<> 161:2cc1468da177 2621 ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
<> 161:2cc1468da177 2622 ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)))
<> 161:2cc1468da177 2623
<> 161:2cc1468da177 2624 /** @brief Macro to configure the PLLI2S clock multiplication and division factors.
<> 161:2cc1468da177 2625 * @note This macro must be used only when the PLLI2S is disabled.
<> 161:2cc1468da177 2626 * @note PLLI2S clock source is common with the main PLL (configured in
<> 161:2cc1468da177 2627 * HAL_RCC_ClockConfig() API)
<> 161:2cc1468da177 2628 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
<> 161:2cc1468da177 2629 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<> 161:2cc1468da177 2630 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
<> 161:2cc1468da177 2631 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
<> 161:2cc1468da177 2632 * @param __PLLI2SQ__: specifies the division factor for SAI clock.
<> 161:2cc1468da177 2633 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<> 161:2cc1468da177 2634 * @param __PLLI2SR__: specifies the division factor for I2S clock
<> 161:2cc1468da177 2635 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<> 161:2cc1468da177 2636 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
<> 161:2cc1468da177 2637 * on the I2S clock frequency.
<> 161:2cc1468da177 2638 */
<> 161:2cc1468da177 2639 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
<> 161:2cc1468da177 2640 (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
<> 161:2cc1468da177 2641 ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
<> 161:2cc1468da177 2642 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
<> 161:2cc1468da177 2643 #else
<> 144:ef7eb2e8f9f7 2644 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
<> 144:ef7eb2e8f9f7 2645 * @note This function must be used only when the PLLSAI is disabled.
<> 144:ef7eb2e8f9f7 2646 * @note PLLSAI clock source is common with the main PLL (configured in
<> 144:ef7eb2e8f9f7 2647 * RCC_PLLConfig function )
<> 144:ef7eb2e8f9f7 2648 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
<> 144:ef7eb2e8f9f7 2649 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<> 144:ef7eb2e8f9f7 2650 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
<> 144:ef7eb2e8f9f7 2651 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
<> 144:ef7eb2e8f9f7 2652 * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
<> 144:ef7eb2e8f9f7 2653 * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
<> 144:ef7eb2e8f9f7 2654 * @param __PLLSAIQ__: specifies the division factor for SAI clock
<> 144:ef7eb2e8f9f7 2655 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 2656 * @param __PLLSAIR__: specifies the division factor for LTDC clock
<> 144:ef7eb2e8f9f7 2657 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<> 144:ef7eb2e8f9f7 2658 */
<> 144:ef7eb2e8f9f7 2659 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
<> 144:ef7eb2e8f9f7 2660 (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
<> 144:ef7eb2e8f9f7 2661 ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
<> 144:ef7eb2e8f9f7 2662 ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\
<> 144:ef7eb2e8f9f7 2663 ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
<> 144:ef7eb2e8f9f7 2664
<> 144:ef7eb2e8f9f7 2665 /** @brief Macro to configure the PLLI2S clock multiplication and division factors.
<> 144:ef7eb2e8f9f7 2666 * @note This macro must be used only when the PLLI2S is disabled.
<> 144:ef7eb2e8f9f7 2667 * @note PLLI2S clock source is common with the main PLL (configured in
<> 144:ef7eb2e8f9f7 2668 * HAL_RCC_ClockConfig() API)
<> 144:ef7eb2e8f9f7 2669 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
<> 144:ef7eb2e8f9f7 2670 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<> 144:ef7eb2e8f9f7 2671 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
<> 144:ef7eb2e8f9f7 2672 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
<> 144:ef7eb2e8f9f7 2673 * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
<> 144:ef7eb2e8f9f7 2674 * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
<> 144:ef7eb2e8f9f7 2675 * @param __PLLI2SQ__: specifies the division factor for SAI clock.
<> 144:ef7eb2e8f9f7 2676 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 2677 * @param __PLLI2SR__: specifies the division factor for I2S clock
<> 144:ef7eb2e8f9f7 2678 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<> 144:ef7eb2e8f9f7 2679 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
<> 144:ef7eb2e8f9f7 2680 * on the I2S clock frequency.
<> 144:ef7eb2e8f9f7 2681 */
<> 144:ef7eb2e8f9f7 2682 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
<> 144:ef7eb2e8f9f7 2683 (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
<> 144:ef7eb2e8f9f7 2684 ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
<> 144:ef7eb2e8f9f7 2685 ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
<> 144:ef7eb2e8f9f7 2686 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
<> 161:2cc1468da177 2687 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */
<> 144:ef7eb2e8f9f7 2688
<> 144:ef7eb2e8f9f7 2689 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
<> 144:ef7eb2e8f9f7 2690 * @note This function must be called before enabling the PLLI2S.
<> 144:ef7eb2e8f9f7 2691 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
<> 144:ef7eb2e8f9f7 2692 * This parameter must be a number between 1 and 32.
<> 144:ef7eb2e8f9f7 2693 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
<> 144:ef7eb2e8f9f7 2694 */
<> 144:ef7eb2e8f9f7 2695 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
<> 144:ef7eb2e8f9f7 2696
<> 144:ef7eb2e8f9f7 2697 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
<> 144:ef7eb2e8f9f7 2698 * @note This function must be called before enabling the PLLSAI.
<> 144:ef7eb2e8f9f7 2699 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
<> 144:ef7eb2e8f9f7 2700 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
<> 144:ef7eb2e8f9f7 2701 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
<> 144:ef7eb2e8f9f7 2702 */
<> 144:ef7eb2e8f9f7 2703 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
<> 144:ef7eb2e8f9f7 2704
<> 161:2cc1468da177 2705 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 2706 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 2707 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
<> 144:ef7eb2e8f9f7 2708 * @note This function must be called before enabling the PLLSAI.
<> 144:ef7eb2e8f9f7 2709 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
<> 144:ef7eb2e8f9f7 2710 * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
<> 144:ef7eb2e8f9f7 2711 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
<> 144:ef7eb2e8f9f7 2712 */
<> 144:ef7eb2e8f9f7 2713 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
<> 144:ef7eb2e8f9f7 2714 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
<> 161:2cc1468da177 2715 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 2716
<> 144:ef7eb2e8f9f7 2717 /** @brief Macro to configure SAI1 clock source selection.
<> 144:ef7eb2e8f9f7 2718 * @note This function must be called before enabling PLLSAI, PLLI2S and
<> 144:ef7eb2e8f9f7 2719 * the SAI clock.
<> 144:ef7eb2e8f9f7 2720 * @param __SOURCE__: specifies the SAI1 clock source.
<> 144:ef7eb2e8f9f7 2721 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2722 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
<> 144:ef7eb2e8f9f7 2723 * as SAI1 clock.
<> 144:ef7eb2e8f9f7 2724 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
<> 144:ef7eb2e8f9f7 2725 * as SAI1 clock.
<> 144:ef7eb2e8f9f7 2726 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
<> 144:ef7eb2e8f9f7 2727 * used as SAI1 clock.
<> 144:ef7eb2e8f9f7 2728 * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
<> 144:ef7eb2e8f9f7 2729 * used as SAI1 clock.
<> 144:ef7eb2e8f9f7 2730 * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
<> 144:ef7eb2e8f9f7 2731 */
<> 144:ef7eb2e8f9f7 2732 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
<> 144:ef7eb2e8f9f7 2733 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
<> 144:ef7eb2e8f9f7 2734
<> 144:ef7eb2e8f9f7 2735 /** @brief Macro to get the SAI1 clock source.
<> 144:ef7eb2e8f9f7 2736 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 2737 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
<> 144:ef7eb2e8f9f7 2738 * as SAI1 clock.
<> 144:ef7eb2e8f9f7 2739 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
<> 144:ef7eb2e8f9f7 2740 * as SAI1 clock.
<> 144:ef7eb2e8f9f7 2741 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
<> 144:ef7eb2e8f9f7 2742 * used as SAI1 clock.
<> 144:ef7eb2e8f9f7 2743 * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
<> 144:ef7eb2e8f9f7 2744 * used as SAI1 clock.
<> 144:ef7eb2e8f9f7 2745 * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
<> 144:ef7eb2e8f9f7 2746 */
<> 144:ef7eb2e8f9f7 2747 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
<> 144:ef7eb2e8f9f7 2748
<> 144:ef7eb2e8f9f7 2749
<> 144:ef7eb2e8f9f7 2750 /** @brief Macro to configure SAI2 clock source selection.
<> 144:ef7eb2e8f9f7 2751 * @note This function must be called before enabling PLLSAI, PLLI2S and
<> 144:ef7eb2e8f9f7 2752 * the SAI clock.
<> 144:ef7eb2e8f9f7 2753 * @param __SOURCE__: specifies the SAI2 clock source.
<> 144:ef7eb2e8f9f7 2754 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2755 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
<> 144:ef7eb2e8f9f7 2756 * as SAI2 clock.
<> 144:ef7eb2e8f9f7 2757 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
<> 144:ef7eb2e8f9f7 2758 * as SAI2 clock.
<> 144:ef7eb2e8f9f7 2759 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
<> 144:ef7eb2e8f9f7 2760 * used as SAI2 clock.
<> 144:ef7eb2e8f9f7 2761 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
<> 144:ef7eb2e8f9f7 2762 * used as SAI2 clock.
<> 144:ef7eb2e8f9f7 2763 * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
<> 144:ef7eb2e8f9f7 2764 */
<> 144:ef7eb2e8f9f7 2765 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
<> 144:ef7eb2e8f9f7 2766 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
<> 144:ef7eb2e8f9f7 2767
<> 144:ef7eb2e8f9f7 2768
<> 144:ef7eb2e8f9f7 2769 /** @brief Macro to get the SAI2 clock source.
<> 144:ef7eb2e8f9f7 2770 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 2771 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
<> 144:ef7eb2e8f9f7 2772 * as SAI2 clock.
<> 144:ef7eb2e8f9f7 2773 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
<> 144:ef7eb2e8f9f7 2774 * as SAI2 clock.
<> 144:ef7eb2e8f9f7 2775 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
<> 144:ef7eb2e8f9f7 2776 * used as SAI2 clock.
<> 144:ef7eb2e8f9f7 2777 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
<> 144:ef7eb2e8f9f7 2778 * used as SAI2 clock.
<> 144:ef7eb2e8f9f7 2779 * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
<> 144:ef7eb2e8f9f7 2780 */
<> 144:ef7eb2e8f9f7 2781 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
<> 144:ef7eb2e8f9f7 2782
<> 144:ef7eb2e8f9f7 2783
<> 144:ef7eb2e8f9f7 2784 /** @brief Enable PLLSAI_RDY interrupt.
<> 144:ef7eb2e8f9f7 2785 */
<> 144:ef7eb2e8f9f7 2786 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
<> 144:ef7eb2e8f9f7 2787
<> 144:ef7eb2e8f9f7 2788 /** @brief Disable PLLSAI_RDY interrupt.
<> 144:ef7eb2e8f9f7 2789 */
<> 144:ef7eb2e8f9f7 2790 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
<> 144:ef7eb2e8f9f7 2791
<> 144:ef7eb2e8f9f7 2792 /** @brief Clear the PLLSAI RDY interrupt pending bits.
<> 144:ef7eb2e8f9f7 2793 */
<> 144:ef7eb2e8f9f7 2794 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
<> 144:ef7eb2e8f9f7 2795
<> 144:ef7eb2e8f9f7 2796 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 2797 * @retval The new state (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 2798 */
<> 144:ef7eb2e8f9f7 2799 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
<> 144:ef7eb2e8f9f7 2800
<> 144:ef7eb2e8f9f7 2801 /** @brief Check PLLSAI RDY flag is set or not.
<> 144:ef7eb2e8f9f7 2802 * @retval The new state (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 2803 */
<> 144:ef7eb2e8f9f7 2804 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
<> 144:ef7eb2e8f9f7 2805
<> 144:ef7eb2e8f9f7 2806 /** @brief Macro to Get I2S clock source selection.
<> 144:ef7eb2e8f9f7 2807 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 2808 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
<> 144:ef7eb2e8f9f7 2809 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
<> 144:ef7eb2e8f9f7 2810 */
<> 144:ef7eb2e8f9f7 2811 #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
<> 144:ef7eb2e8f9f7 2812
<> 144:ef7eb2e8f9f7 2813 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
<> 144:ef7eb2e8f9f7 2814 *
<> 144:ef7eb2e8f9f7 2815 * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
<> 144:ef7eb2e8f9f7 2816 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2817 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
<> 144:ef7eb2e8f9f7 2818 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
<> 144:ef7eb2e8f9f7 2819 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
<> 144:ef7eb2e8f9f7 2820 */
<> 144:ef7eb2e8f9f7 2821 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 2822 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 2823
<> 144:ef7eb2e8f9f7 2824 /** @brief Macro to get the I2C1 clock source.
<> 144:ef7eb2e8f9f7 2825 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 2826 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
<> 144:ef7eb2e8f9f7 2827 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
<> 144:ef7eb2e8f9f7 2828 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
<> 144:ef7eb2e8f9f7 2829 */
<> 144:ef7eb2e8f9f7 2830 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
<> 144:ef7eb2e8f9f7 2831
<> 144:ef7eb2e8f9f7 2832 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
<> 144:ef7eb2e8f9f7 2833 *
<> 144:ef7eb2e8f9f7 2834 * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
<> 144:ef7eb2e8f9f7 2835 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2836 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
<> 144:ef7eb2e8f9f7 2837 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
<> 144:ef7eb2e8f9f7 2838 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
<> 144:ef7eb2e8f9f7 2839 */
<> 144:ef7eb2e8f9f7 2840 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 2841 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 2842
<> 144:ef7eb2e8f9f7 2843 /** @brief Macro to get the I2C2 clock source.
<> 144:ef7eb2e8f9f7 2844 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 2845 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
<> 144:ef7eb2e8f9f7 2846 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
<> 144:ef7eb2e8f9f7 2847 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
<> 144:ef7eb2e8f9f7 2848 */
<> 144:ef7eb2e8f9f7 2849 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
<> 144:ef7eb2e8f9f7 2850
<> 144:ef7eb2e8f9f7 2851 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
<> 144:ef7eb2e8f9f7 2852 *
<> 144:ef7eb2e8f9f7 2853 * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
<> 144:ef7eb2e8f9f7 2854 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2855 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
<> 144:ef7eb2e8f9f7 2856 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
<> 144:ef7eb2e8f9f7 2857 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
<> 144:ef7eb2e8f9f7 2858 */
<> 144:ef7eb2e8f9f7 2859 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 2860 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 2861
<> 144:ef7eb2e8f9f7 2862 /** @brief macro to get the I2C3 clock source.
<> 144:ef7eb2e8f9f7 2863 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 2864 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
<> 144:ef7eb2e8f9f7 2865 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
<> 144:ef7eb2e8f9f7 2866 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
<> 144:ef7eb2e8f9f7 2867 */
<> 144:ef7eb2e8f9f7 2868 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
<> 144:ef7eb2e8f9f7 2869
<> 144:ef7eb2e8f9f7 2870 /** @brief Macro to configure the I2C4 clock (I2C4CLK).
<> 144:ef7eb2e8f9f7 2871 *
<> 144:ef7eb2e8f9f7 2872 * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
<> 144:ef7eb2e8f9f7 2873 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2874 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
<> 144:ef7eb2e8f9f7 2875 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
<> 144:ef7eb2e8f9f7 2876 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
<> 144:ef7eb2e8f9f7 2877 */
<> 144:ef7eb2e8f9f7 2878 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 2879 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 2880
<> 144:ef7eb2e8f9f7 2881 /** @brief macro to get the I2C4 clock source.
<> 144:ef7eb2e8f9f7 2882 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 2883 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
<> 144:ef7eb2e8f9f7 2884 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
<> 144:ef7eb2e8f9f7 2885 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
<> 144:ef7eb2e8f9f7 2886 */
<> 144:ef7eb2e8f9f7 2887 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
<> 144:ef7eb2e8f9f7 2888
<> 144:ef7eb2e8f9f7 2889 /** @brief Macro to configure the USART1 clock (USART1CLK).
<> 144:ef7eb2e8f9f7 2890 *
<> 144:ef7eb2e8f9f7 2891 * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
<> 144:ef7eb2e8f9f7 2892 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2893 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
<> 144:ef7eb2e8f9f7 2894 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
<> 144:ef7eb2e8f9f7 2895 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
<> 144:ef7eb2e8f9f7 2896 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
<> 144:ef7eb2e8f9f7 2897 */
<> 144:ef7eb2e8f9f7 2898 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 2899 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 2900
<> 144:ef7eb2e8f9f7 2901 /** @brief macro to get the USART1 clock source.
<> 144:ef7eb2e8f9f7 2902 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 2903 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
<> 144:ef7eb2e8f9f7 2904 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
<> 144:ef7eb2e8f9f7 2905 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
<> 144:ef7eb2e8f9f7 2906 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
<> 144:ef7eb2e8f9f7 2907 */
<> 144:ef7eb2e8f9f7 2908 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
<> 144:ef7eb2e8f9f7 2909
<> 144:ef7eb2e8f9f7 2910 /** @brief Macro to configure the USART2 clock (USART2CLK).
<> 144:ef7eb2e8f9f7 2911 *
<> 144:ef7eb2e8f9f7 2912 * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
<> 144:ef7eb2e8f9f7 2913 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2914 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
<> 144:ef7eb2e8f9f7 2915 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
<> 144:ef7eb2e8f9f7 2916 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
<> 144:ef7eb2e8f9f7 2917 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
<> 144:ef7eb2e8f9f7 2918 */
<> 144:ef7eb2e8f9f7 2919 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 2920 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 2921
<> 144:ef7eb2e8f9f7 2922 /** @brief macro to get the USART2 clock source.
<> 144:ef7eb2e8f9f7 2923 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 2924 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
<> 144:ef7eb2e8f9f7 2925 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
<> 144:ef7eb2e8f9f7 2926 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
<> 144:ef7eb2e8f9f7 2927 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
<> 144:ef7eb2e8f9f7 2928 */
<> 144:ef7eb2e8f9f7 2929 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
<> 144:ef7eb2e8f9f7 2930
<> 144:ef7eb2e8f9f7 2931 /** @brief Macro to configure the USART3 clock (USART3CLK).
<> 144:ef7eb2e8f9f7 2932 *
<> 144:ef7eb2e8f9f7 2933 * @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
<> 144:ef7eb2e8f9f7 2934 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2935 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
<> 144:ef7eb2e8f9f7 2936 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
<> 144:ef7eb2e8f9f7 2937 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
<> 144:ef7eb2e8f9f7 2938 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
<> 144:ef7eb2e8f9f7 2939 */
<> 144:ef7eb2e8f9f7 2940 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 2941 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 2942
<> 144:ef7eb2e8f9f7 2943 /** @brief macro to get the USART3 clock source.
<> 144:ef7eb2e8f9f7 2944 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 2945 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
<> 144:ef7eb2e8f9f7 2946 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
<> 144:ef7eb2e8f9f7 2947 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
<> 144:ef7eb2e8f9f7 2948 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
<> 144:ef7eb2e8f9f7 2949 */
<> 144:ef7eb2e8f9f7 2950 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
<> 144:ef7eb2e8f9f7 2951
<> 144:ef7eb2e8f9f7 2952 /** @brief Macro to configure the UART4 clock (UART4CLK).
<> 144:ef7eb2e8f9f7 2953 *
<> 144:ef7eb2e8f9f7 2954 * @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
<> 144:ef7eb2e8f9f7 2955 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2956 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
<> 144:ef7eb2e8f9f7 2957 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
<> 144:ef7eb2e8f9f7 2958 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
<> 144:ef7eb2e8f9f7 2959 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
<> 144:ef7eb2e8f9f7 2960 */
<> 144:ef7eb2e8f9f7 2961 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 2962 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 2963
<> 144:ef7eb2e8f9f7 2964 /** @brief macro to get the UART4 clock source.
<> 144:ef7eb2e8f9f7 2965 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 2966 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
<> 144:ef7eb2e8f9f7 2967 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
<> 144:ef7eb2e8f9f7 2968 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
<> 144:ef7eb2e8f9f7 2969 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
<> 144:ef7eb2e8f9f7 2970 */
<> 144:ef7eb2e8f9f7 2971 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
<> 144:ef7eb2e8f9f7 2972
<> 144:ef7eb2e8f9f7 2973 /** @brief Macro to configure the UART5 clock (UART5CLK).
<> 144:ef7eb2e8f9f7 2974 *
<> 144:ef7eb2e8f9f7 2975 * @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
<> 144:ef7eb2e8f9f7 2976 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2977 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
<> 144:ef7eb2e8f9f7 2978 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
<> 144:ef7eb2e8f9f7 2979 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
<> 144:ef7eb2e8f9f7 2980 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
<> 144:ef7eb2e8f9f7 2981 */
<> 144:ef7eb2e8f9f7 2982 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 2983 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 2984
<> 144:ef7eb2e8f9f7 2985 /** @brief macro to get the UART5 clock source.
<> 144:ef7eb2e8f9f7 2986 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 2987 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
<> 144:ef7eb2e8f9f7 2988 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
<> 144:ef7eb2e8f9f7 2989 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
<> 144:ef7eb2e8f9f7 2990 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
<> 144:ef7eb2e8f9f7 2991 */
<> 144:ef7eb2e8f9f7 2992 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
<> 144:ef7eb2e8f9f7 2993
<> 144:ef7eb2e8f9f7 2994 /** @brief Macro to configure the USART6 clock (USART6CLK).
<> 144:ef7eb2e8f9f7 2995 *
<> 144:ef7eb2e8f9f7 2996 * @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
<> 144:ef7eb2e8f9f7 2997 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2998 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
<> 144:ef7eb2e8f9f7 2999 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
<> 144:ef7eb2e8f9f7 3000 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
<> 144:ef7eb2e8f9f7 3001 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
<> 144:ef7eb2e8f9f7 3002 */
<> 144:ef7eb2e8f9f7 3003 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 3004 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 3005
<> 144:ef7eb2e8f9f7 3006 /** @brief macro to get the USART6 clock source.
<> 144:ef7eb2e8f9f7 3007 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 3008 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
<> 144:ef7eb2e8f9f7 3009 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
<> 144:ef7eb2e8f9f7 3010 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
<> 144:ef7eb2e8f9f7 3011 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
<> 144:ef7eb2e8f9f7 3012 */
<> 144:ef7eb2e8f9f7 3013 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
<> 144:ef7eb2e8f9f7 3014
<> 144:ef7eb2e8f9f7 3015 /** @brief Macro to configure the UART7 clock (UART7CLK).
<> 144:ef7eb2e8f9f7 3016 *
<> 144:ef7eb2e8f9f7 3017 * @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
<> 144:ef7eb2e8f9f7 3018 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3019 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
<> 144:ef7eb2e8f9f7 3020 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
<> 144:ef7eb2e8f9f7 3021 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
<> 144:ef7eb2e8f9f7 3022 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
<> 144:ef7eb2e8f9f7 3023 */
<> 144:ef7eb2e8f9f7 3024 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 3025 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 3026
<> 144:ef7eb2e8f9f7 3027 /** @brief macro to get the UART7 clock source.
<> 144:ef7eb2e8f9f7 3028 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 3029 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
<> 144:ef7eb2e8f9f7 3030 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
<> 144:ef7eb2e8f9f7 3031 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
<> 144:ef7eb2e8f9f7 3032 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
<> 144:ef7eb2e8f9f7 3033 */
<> 144:ef7eb2e8f9f7 3034 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
<> 144:ef7eb2e8f9f7 3035
<> 144:ef7eb2e8f9f7 3036 /** @brief Macro to configure the UART8 clock (UART8CLK).
<> 144:ef7eb2e8f9f7 3037 *
<> 144:ef7eb2e8f9f7 3038 * @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
<> 144:ef7eb2e8f9f7 3039 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3040 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
<> 144:ef7eb2e8f9f7 3041 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
<> 144:ef7eb2e8f9f7 3042 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
<> 144:ef7eb2e8f9f7 3043 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
<> 144:ef7eb2e8f9f7 3044 */
<> 144:ef7eb2e8f9f7 3045 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 3046 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 3047
<> 144:ef7eb2e8f9f7 3048 /** @brief macro to get the UART8 clock source.
<> 144:ef7eb2e8f9f7 3049 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 3050 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
<> 144:ef7eb2e8f9f7 3051 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
<> 144:ef7eb2e8f9f7 3052 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
<> 144:ef7eb2e8f9f7 3053 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
<> 144:ef7eb2e8f9f7 3054 */
<> 144:ef7eb2e8f9f7 3055 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
<> 144:ef7eb2e8f9f7 3056
<> 144:ef7eb2e8f9f7 3057 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
<> 144:ef7eb2e8f9f7 3058 *
<> 144:ef7eb2e8f9f7 3059 * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
<> 144:ef7eb2e8f9f7 3060 * This parameter can be one of the following values:
<> 161:2cc1468da177 3061 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
<> 144:ef7eb2e8f9f7 3062 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
<> 144:ef7eb2e8f9f7 3063 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
<> 144:ef7eb2e8f9f7 3064 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
<> 144:ef7eb2e8f9f7 3065 */
<> 144:ef7eb2e8f9f7 3066 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 3067 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 3068
<> 144:ef7eb2e8f9f7 3069 /** @brief macro to get the LPTIM1 clock source.
<> 144:ef7eb2e8f9f7 3070 * @retval The clock source can be one of the following values:
<> 161:2cc1468da177 3071 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
<> 144:ef7eb2e8f9f7 3072 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
<> 144:ef7eb2e8f9f7 3073 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
<> 144:ef7eb2e8f9f7 3074 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
<> 144:ef7eb2e8f9f7 3075 */
<> 144:ef7eb2e8f9f7 3076 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
<> 144:ef7eb2e8f9f7 3077
<> 144:ef7eb2e8f9f7 3078 /** @brief Macro to configure the CEC clock (CECCLK).
<> 144:ef7eb2e8f9f7 3079 *
<> 144:ef7eb2e8f9f7 3080 * @param __CEC_CLKSOURCE__: specifies the CEC clock source.
<> 144:ef7eb2e8f9f7 3081 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3082 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
<> 144:ef7eb2e8f9f7 3083 * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
<> 144:ef7eb2e8f9f7 3084 */
<> 144:ef7eb2e8f9f7 3085 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 3086 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 3087
<> 144:ef7eb2e8f9f7 3088 /** @brief macro to get the CEC clock source.
<> 144:ef7eb2e8f9f7 3089 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 3090 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
<> 144:ef7eb2e8f9f7 3091 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
<> 144:ef7eb2e8f9f7 3092 */
<> 144:ef7eb2e8f9f7 3093 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
<> 144:ef7eb2e8f9f7 3094
<> 144:ef7eb2e8f9f7 3095 /** @brief Macro to configure the CLK48 source (CLK48CLK).
<> 144:ef7eb2e8f9f7 3096 *
<> 144:ef7eb2e8f9f7 3097 * @param __CLK48_SOURCE__: specifies the CLK48 clock source.
<> 144:ef7eb2e8f9f7 3098 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3099 * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
<> 144:ef7eb2e8f9f7 3100 * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
<> 144:ef7eb2e8f9f7 3101 */
<> 144:ef7eb2e8f9f7 3102 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
<> 144:ef7eb2e8f9f7 3103 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
<> 144:ef7eb2e8f9f7 3104
<> 144:ef7eb2e8f9f7 3105 /** @brief macro to get the CLK48 source.
<> 144:ef7eb2e8f9f7 3106 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 3107 * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
<> 144:ef7eb2e8f9f7 3108 * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
<> 144:ef7eb2e8f9f7 3109 */
<> 144:ef7eb2e8f9f7 3110 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
<> 144:ef7eb2e8f9f7 3111
<> 144:ef7eb2e8f9f7 3112 /** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
<> 144:ef7eb2e8f9f7 3113 *
<> 144:ef7eb2e8f9f7 3114 * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
<> 144:ef7eb2e8f9f7 3115 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3116 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
<> 144:ef7eb2e8f9f7 3117 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
<> 144:ef7eb2e8f9f7 3118 */
<> 144:ef7eb2e8f9f7 3119 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 3120 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 3121
<> 144:ef7eb2e8f9f7 3122 /** @brief macro to get the SDMMC1 clock source.
<> 144:ef7eb2e8f9f7 3123 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 3124 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
<> 144:ef7eb2e8f9f7 3125 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
<> 144:ef7eb2e8f9f7 3126 */
<> 144:ef7eb2e8f9f7 3127 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
<> 144:ef7eb2e8f9f7 3128
<> 161:2cc1468da177 3129 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 3130 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 3131 /** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK).
<> 144:ef7eb2e8f9f7 3132 * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source.
<> 144:ef7eb2e8f9f7 3133 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3134 * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
<> 144:ef7eb2e8f9f7 3135 * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
<> 144:ef7eb2e8f9f7 3136 */
<> 144:ef7eb2e8f9f7 3137 #define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 3138 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 3139
<> 144:ef7eb2e8f9f7 3140 /** @brief macro to get the SDMMC2 clock source.
<> 144:ef7eb2e8f9f7 3141 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 3142 * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
<> 144:ef7eb2e8f9f7 3143 * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
<> 144:ef7eb2e8f9f7 3144 */
<> 144:ef7eb2e8f9f7 3145 #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))
<> 161:2cc1468da177 3146 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 3147
<> 161:2cc1468da177 3148 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 3149 /** @brief Macro to configure the DFSDM1 clock
<> 144:ef7eb2e8f9f7 3150 * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
<> 144:ef7eb2e8f9f7 3151 * This parameter can be one of the following values:
<> 161:2cc1468da177 3152 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock
<> 144:ef7eb2e8f9f7 3153 * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock
<> 144:ef7eb2e8f9f7 3154 */
<> 144:ef7eb2e8f9f7 3155 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 3156 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 3157
<> 144:ef7eb2e8f9f7 3158 /** @brief Macro to get the DFSDM1 clock source.
<> 144:ef7eb2e8f9f7 3159 * @retval The clock source can be one of the following values:
<> 161:2cc1468da177 3160 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM1 clock
<> 144:ef7eb2e8f9f7 3161 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock
<> 144:ef7eb2e8f9f7 3162 */
<> 144:ef7eb2e8f9f7 3163 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))
<> 144:ef7eb2e8f9f7 3164
<> 144:ef7eb2e8f9f7 3165 /** @brief Macro to configure the DFSDM1 Audio clock
<> 144:ef7eb2e8f9f7 3166 * @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source.
<> 144:ef7eb2e8f9f7 3167 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3168 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
<> 144:ef7eb2e8f9f7 3169 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
<> 144:ef7eb2e8f9f7 3170 */
<> 144:ef7eb2e8f9f7 3171 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 3172 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 3173
<> 144:ef7eb2e8f9f7 3174 /** @brief Macro to get the DFSDM1 Audio clock source.
<> 144:ef7eb2e8f9f7 3175 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 3176 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
<> 144:ef7eb2e8f9f7 3177 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
<> 144:ef7eb2e8f9f7 3178 */
<> 144:ef7eb2e8f9f7 3179 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL)))
<> 144:ef7eb2e8f9f7 3180 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 3181
<> 144:ef7eb2e8f9f7 3182 #if defined (STM32F769xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 3183 /** @brief Macro to configure the DSI clock.
<> 144:ef7eb2e8f9f7 3184 * @param __DSI_CLKSOURCE__: specifies the DSI clock source.
<> 144:ef7eb2e8f9f7 3185 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3186 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
<> 144:ef7eb2e8f9f7 3187 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
<> 144:ef7eb2e8f9f7 3188 */
<> 144:ef7eb2e8f9f7 3189 #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))
<> 144:ef7eb2e8f9f7 3190
<> 144:ef7eb2e8f9f7 3191 /** @brief Macro to Get the DSI clock.
<> 144:ef7eb2e8f9f7 3192 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 3193 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
<> 144:ef7eb2e8f9f7 3194 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
<> 144:ef7eb2e8f9f7 3195 */
<> 144:ef7eb2e8f9f7 3196 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL))
<> 144:ef7eb2e8f9f7 3197 #endif /* STM32F769xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 3198 /**
<> 144:ef7eb2e8f9f7 3199 * @}
<> 144:ef7eb2e8f9f7 3200 */
<> 144:ef7eb2e8f9f7 3201
<> 144:ef7eb2e8f9f7 3202 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 3203 /** @addtogroup RCCEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 3204 * @{
<> 144:ef7eb2e8f9f7 3205 */
<> 144:ef7eb2e8f9f7 3206 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
<> 144:ef7eb2e8f9f7 3207 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
<> 144:ef7eb2e8f9f7 3208 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
<> 144:ef7eb2e8f9f7 3209
<> 144:ef7eb2e8f9f7 3210 /**
<> 144:ef7eb2e8f9f7 3211 * @}
<> 144:ef7eb2e8f9f7 3212 */
<> 144:ef7eb2e8f9f7 3213 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 3214 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
<> 144:ef7eb2e8f9f7 3215 * @{
<> 144:ef7eb2e8f9f7 3216 */
<> 144:ef7eb2e8f9f7 3217 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
<> 144:ef7eb2e8f9f7 3218 * @{
<> 144:ef7eb2e8f9f7 3219 */
<> 144:ef7eb2e8f9f7 3220 #if defined(STM32F756xx) || defined(STM32F746xx)
<> 144:ef7eb2e8f9f7 3221 #define IS_RCC_PERIPHCLOCK(SELECTION) \
<> 144:ef7eb2e8f9f7 3222 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
<> 144:ef7eb2e8f9f7 3223 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
<> 144:ef7eb2e8f9f7 3224 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
<> 144:ef7eb2e8f9f7 3225 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
<> 144:ef7eb2e8f9f7 3226 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
<> 144:ef7eb2e8f9f7 3227 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
<> 144:ef7eb2e8f9f7 3228 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
<> 144:ef7eb2e8f9f7 3229 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
<> 144:ef7eb2e8f9f7 3230 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
<> 144:ef7eb2e8f9f7 3231 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
<> 144:ef7eb2e8f9f7 3232 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
<> 144:ef7eb2e8f9f7 3233 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
<> 144:ef7eb2e8f9f7 3234 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
<> 144:ef7eb2e8f9f7 3235 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
<> 144:ef7eb2e8f9f7 3236 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
<> 144:ef7eb2e8f9f7 3237 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
<> 144:ef7eb2e8f9f7 3238 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
<> 144:ef7eb2e8f9f7 3239 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
<> 144:ef7eb2e8f9f7 3240 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
<> 144:ef7eb2e8f9f7 3241 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
<> 144:ef7eb2e8f9f7 3242 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
<> 144:ef7eb2e8f9f7 3243 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
<> 144:ef7eb2e8f9f7 3244 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 3245 #elif defined(STM32F745xx)
<> 144:ef7eb2e8f9f7 3246 #define IS_RCC_PERIPHCLOCK(SELECTION) \
<> 144:ef7eb2e8f9f7 3247 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
<> 144:ef7eb2e8f9f7 3248 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
<> 144:ef7eb2e8f9f7 3249 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
<> 144:ef7eb2e8f9f7 3250 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
<> 144:ef7eb2e8f9f7 3251 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
<> 144:ef7eb2e8f9f7 3252 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
<> 144:ef7eb2e8f9f7 3253 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
<> 144:ef7eb2e8f9f7 3254 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
<> 144:ef7eb2e8f9f7 3255 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
<> 144:ef7eb2e8f9f7 3256 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
<> 144:ef7eb2e8f9f7 3257 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
<> 144:ef7eb2e8f9f7 3258 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
<> 144:ef7eb2e8f9f7 3259 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
<> 144:ef7eb2e8f9f7 3260 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
<> 144:ef7eb2e8f9f7 3261 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
<> 144:ef7eb2e8f9f7 3262 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
<> 144:ef7eb2e8f9f7 3263 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
<> 144:ef7eb2e8f9f7 3264 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
<> 144:ef7eb2e8f9f7 3265 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
<> 144:ef7eb2e8f9f7 3266 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
<> 144:ef7eb2e8f9f7 3267 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
<> 144:ef7eb2e8f9f7 3268 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 3269 #elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 3270 #define IS_RCC_PERIPHCLOCK(SELECTION) \
<> 144:ef7eb2e8f9f7 3271 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
<> 144:ef7eb2e8f9f7 3272 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
<> 144:ef7eb2e8f9f7 3273 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
<> 144:ef7eb2e8f9f7 3274 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
<> 144:ef7eb2e8f9f7 3275 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
<> 144:ef7eb2e8f9f7 3276 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
<> 144:ef7eb2e8f9f7 3277 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
<> 144:ef7eb2e8f9f7 3278 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
<> 144:ef7eb2e8f9f7 3279 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
<> 144:ef7eb2e8f9f7 3280 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
<> 144:ef7eb2e8f9f7 3281 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
<> 144:ef7eb2e8f9f7 3282 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
<> 144:ef7eb2e8f9f7 3283 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
<> 144:ef7eb2e8f9f7 3284 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
<> 144:ef7eb2e8f9f7 3285 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
<> 144:ef7eb2e8f9f7 3286 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
<> 144:ef7eb2e8f9f7 3287 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
<> 144:ef7eb2e8f9f7 3288 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
<> 144:ef7eb2e8f9f7 3289 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
<> 144:ef7eb2e8f9f7 3290 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
<> 144:ef7eb2e8f9f7 3291 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
<> 144:ef7eb2e8f9f7 3292 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
<> 144:ef7eb2e8f9f7 3293 (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
<> 144:ef7eb2e8f9f7 3294 (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
<> 144:ef7eb2e8f9f7 3295 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
<> 144:ef7eb2e8f9f7 3296 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 3297 #elif defined (STM32F765xx)
<> 144:ef7eb2e8f9f7 3298 #define IS_RCC_PERIPHCLOCK(SELECTION) \
<> 144:ef7eb2e8f9f7 3299 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
<> 144:ef7eb2e8f9f7 3300 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
<> 144:ef7eb2e8f9f7 3301 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
<> 144:ef7eb2e8f9f7 3302 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
<> 144:ef7eb2e8f9f7 3303 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
<> 144:ef7eb2e8f9f7 3304 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
<> 144:ef7eb2e8f9f7 3305 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
<> 144:ef7eb2e8f9f7 3306 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
<> 144:ef7eb2e8f9f7 3307 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
<> 144:ef7eb2e8f9f7 3308 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
<> 144:ef7eb2e8f9f7 3309 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
<> 144:ef7eb2e8f9f7 3310 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
<> 144:ef7eb2e8f9f7 3311 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
<> 144:ef7eb2e8f9f7 3312 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
<> 144:ef7eb2e8f9f7 3313 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
<> 144:ef7eb2e8f9f7 3314 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
<> 144:ef7eb2e8f9f7 3315 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
<> 144:ef7eb2e8f9f7 3316 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
<> 144:ef7eb2e8f9f7 3317 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
<> 144:ef7eb2e8f9f7 3318 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
<> 144:ef7eb2e8f9f7 3319 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
<> 144:ef7eb2e8f9f7 3320 (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
<> 144:ef7eb2e8f9f7 3321 (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
<> 144:ef7eb2e8f9f7 3322 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
<> 144:ef7eb2e8f9f7 3323 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<> 161:2cc1468da177 3324 #elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx)
<> 161:2cc1468da177 3325 #define IS_RCC_PERIPHCLOCK(SELECTION) \
<> 161:2cc1468da177 3326 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
<> 161:2cc1468da177 3327 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
<> 161:2cc1468da177 3328 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
<> 161:2cc1468da177 3329 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
<> 161:2cc1468da177 3330 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
<> 161:2cc1468da177 3331 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
<> 161:2cc1468da177 3332 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
<> 161:2cc1468da177 3333 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
<> 161:2cc1468da177 3334 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
<> 161:2cc1468da177 3335 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
<> 161:2cc1468da177 3336 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
<> 161:2cc1468da177 3337 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
<> 161:2cc1468da177 3338 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
<> 161:2cc1468da177 3339 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
<> 161:2cc1468da177 3340 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
<> 161:2cc1468da177 3341 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
<> 161:2cc1468da177 3342 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
<> 161:2cc1468da177 3343 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
<> 161:2cc1468da177 3344 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
<> 161:2cc1468da177 3345 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<> 161:2cc1468da177 3346 #endif /* STM32F746xx || STM32F756xx */
<> 144:ef7eb2e8f9f7 3347 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
<> 161:2cc1468da177 3348 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
<> 161:2cc1468da177 3349 defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 3350 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
<> 144:ef7eb2e8f9f7 3351 ((VALUE) == RCC_PLLI2SP_DIV4) ||\
<> 144:ef7eb2e8f9f7 3352 ((VALUE) == RCC_PLLI2SP_DIV6) ||\
<> 161:2cc1468da177 3353 ((VALUE) == RCC_PLLI2SP_DIV8))
<> 161:2cc1468da177 3354 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 3355 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
<> 144:ef7eb2e8f9f7 3356 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
<> 144:ef7eb2e8f9f7 3357
<> 144:ef7eb2e8f9f7 3358 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
<> 144:ef7eb2e8f9f7 3359 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
<> 144:ef7eb2e8f9f7 3360 ((VALUE) == RCC_PLLSAIP_DIV4) ||\
<> 144:ef7eb2e8f9f7 3361 ((VALUE) == RCC_PLLSAIP_DIV6) ||\
<> 144:ef7eb2e8f9f7 3362 ((VALUE) == RCC_PLLSAIP_DIV8))
<> 144:ef7eb2e8f9f7 3363 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
<> 144:ef7eb2e8f9f7 3364 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
<> 144:ef7eb2e8f9f7 3365
<> 144:ef7eb2e8f9f7 3366 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
<> 144:ef7eb2e8f9f7 3367
<> 144:ef7eb2e8f9f7 3368 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
<> 144:ef7eb2e8f9f7 3369
<> 144:ef7eb2e8f9f7 3370 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
<> 144:ef7eb2e8f9f7 3371 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
<> 144:ef7eb2e8f9f7 3372 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
<> 144:ef7eb2e8f9f7 3373 ((VALUE) == RCC_PLLSAIDIVR_16))
<> 144:ef7eb2e8f9f7 3374 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
<> 144:ef7eb2e8f9f7 3375 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
<> 144:ef7eb2e8f9f7 3376
<> 144:ef7eb2e8f9f7 3377 #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 3378 ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
<> 144:ef7eb2e8f9f7 3379
<> 144:ef7eb2e8f9f7 3380 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 3381 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
<> 144:ef7eb2e8f9f7 3382 #define IS_RCC_USART1CLKSOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3383 (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
<> 144:ef7eb2e8f9f7 3384 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 3385 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 3386 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 3387
<> 144:ef7eb2e8f9f7 3388 #define IS_RCC_USART2CLKSOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3389 (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 3390 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 3391 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 3392 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 3393 #define IS_RCC_USART3CLKSOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3394 (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 3395 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 3396 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 3397 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 3398
<> 144:ef7eb2e8f9f7 3399 #define IS_RCC_UART4CLKSOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3400 (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 3401 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 3402 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 3403 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 3404
<> 144:ef7eb2e8f9f7 3405 #define IS_RCC_UART5CLKSOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3406 (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 3407 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 3408 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 3409 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 3410
<> 144:ef7eb2e8f9f7 3411 #define IS_RCC_USART6CLKSOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3412 (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \
<> 144:ef7eb2e8f9f7 3413 ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 3414 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 3415 ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 3416
<> 144:ef7eb2e8f9f7 3417 #define IS_RCC_UART7CLKSOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3418 (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 3419 ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 3420 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 3421 ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 3422
<> 144:ef7eb2e8f9f7 3423 #define IS_RCC_UART8CLKSOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3424 (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 3425 ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 3426 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 3427 ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 3428 #define IS_RCC_I2C1CLKSOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3429 (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 3430 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
<> 144:ef7eb2e8f9f7 3431 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 3432 #define IS_RCC_I2C2CLKSOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3433 (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 3434 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
<> 144:ef7eb2e8f9f7 3435 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 3436
<> 144:ef7eb2e8f9f7 3437 #define IS_RCC_I2C3CLKSOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3438 (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 3439 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
<> 144:ef7eb2e8f9f7 3440 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 3441 #define IS_RCC_I2C4CLKSOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3442 (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 3443 ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
<> 144:ef7eb2e8f9f7 3444 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 3445 #define IS_RCC_LPTIM1CLK(SOURCE) \
<> 161:2cc1468da177 3446 (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 3447 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
<> 144:ef7eb2e8f9f7 3448 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 3449 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
<> 144:ef7eb2e8f9f7 3450 #define IS_RCC_CLK48SOURCE(SOURCE) \
<> 144:ef7eb2e8f9f7 3451 (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
<> 144:ef7eb2e8f9f7 3452 ((SOURCE) == RCC_CLK48SOURCE_PLL))
<> 144:ef7eb2e8f9f7 3453 #define IS_RCC_TIMPRES(VALUE) \
<> 144:ef7eb2e8f9f7 3454 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
<> 144:ef7eb2e8f9f7 3455 ((VALUE) == RCC_TIMPRES_ACTIVATED))
<> 144:ef7eb2e8f9f7 3456
<> 161:2cc1468da177 3457 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\
<> 161:2cc1468da177 3458 defined (STM32F746xx) || defined (STM32F756xx)
<> 144:ef7eb2e8f9f7 3459 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
<> 144:ef7eb2e8f9f7 3460 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
<> 144:ef7eb2e8f9f7 3461 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
<> 144:ef7eb2e8f9f7 3462 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
<> 144:ef7eb2e8f9f7 3463 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
<> 144:ef7eb2e8f9f7 3464 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
<> 161:2cc1468da177 3465 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx */
<> 144:ef7eb2e8f9f7 3466
<> 144:ef7eb2e8f9f7 3467 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 3468 #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
<> 144:ef7eb2e8f9f7 3469
<> 144:ef7eb2e8f9f7 3470 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
<> 144:ef7eb2e8f9f7 3471 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
<> 144:ef7eb2e8f9f7 3472 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \
<> 144:ef7eb2e8f9f7 3473 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))
<> 144:ef7eb2e8f9f7 3474
<> 144:ef7eb2e8f9f7 3475 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
<> 144:ef7eb2e8f9f7 3476 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
<> 144:ef7eb2e8f9f7 3477 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \
<> 144:ef7eb2e8f9f7 3478 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
<> 144:ef7eb2e8f9f7 3479
<> 161:2cc1468da177 3480 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
<> 144:ef7eb2e8f9f7 3481 ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))
<> 144:ef7eb2e8f9f7 3482
<> 144:ef7eb2e8f9f7 3483 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \
<> 144:ef7eb2e8f9f7 3484 ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))
<> 144:ef7eb2e8f9f7 3485 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 3486
<> 161:2cc1468da177 3487 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 161:2cc1468da177 3488 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 161:2cc1468da177 3489 #define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \
<> 161:2cc1468da177 3490 ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))
<> 161:2cc1468da177 3491 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 3492
<> 144:ef7eb2e8f9f7 3493 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 3494 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\
<> 144:ef7eb2e8f9f7 3495 ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
<> 144:ef7eb2e8f9f7 3496 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 3497
<> 144:ef7eb2e8f9f7 3498 /**
<> 144:ef7eb2e8f9f7 3499 * @}
<> 144:ef7eb2e8f9f7 3500 */
<> 144:ef7eb2e8f9f7 3501
<> 144:ef7eb2e8f9f7 3502 /**
<> 144:ef7eb2e8f9f7 3503 * @}
<> 144:ef7eb2e8f9f7 3504 */
<> 144:ef7eb2e8f9f7 3505
<> 144:ef7eb2e8f9f7 3506 /**
<> 144:ef7eb2e8f9f7 3507 * @}
<> 144:ef7eb2e8f9f7 3508 */
<> 144:ef7eb2e8f9f7 3509
<> 144:ef7eb2e8f9f7 3510 /**
<> 144:ef7eb2e8f9f7 3511 * @}
<> 144:ef7eb2e8f9f7 3512 */
<> 144:ef7eb2e8f9f7 3513 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 3514 }
<> 144:ef7eb2e8f9f7 3515 #endif
<> 144:ef7eb2e8f9f7 3516
<> 144:ef7eb2e8f9f7 3517 #endif /* __STM32F7xx_HAL_RCC_EX_H */
<> 144:ef7eb2e8f9f7 3518
<> 144:ef7eb2e8f9f7 3519 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/