stm32f4xx_bluenrg_shield_bsp.h

00001 #ifndef __BLUENRG_SHIELD_BRP_H_
00002 #define __BLUENRG_SHIELD_BRP_H_
00003 /* Includes ------------------------------------------------------------------*/
00004 #include "cube_hal.h"
00005 #include "gp_timer.h"
00006 
00007 /* SPI communication details between Nucleo F4 and BlueNRG shield */
00008 
00009 // SPI Instance
00010 #define BNRG_SPI_INSTANCE               SPI1
00011 #define BNRG_SPI_CLK_ENABLE()           __SPI1_CLK_ENABLE()
00012 
00013 // SPI Configuration
00014 #define BNRG_SPI_MODE                   SPI_MODE_MASTER
00015 #define BNRG_SPI_DIRECTION              SPI_DIRECTION_2LINES
00016 #define BNRG_SPI_DATASIZE               SPI_DATASIZE_8BIT
00017 #define BNRG_SPI_CLKPOLARITY            SPI_POLARITY_LOW
00018 #define BNRG_SPI_CLKPHASE               SPI_PHASE_1EDGE
00019 #define BNRG_SPI_NSS                    SPI_NSS_SOFT
00020 #define BNRG_SPI_FIRSTBIT               SPI_FIRSTBIT_MSB
00021 #define BNRG_SPI_TIMODE                 SPI_TIMODE_DISABLED
00022 #define BNRG_SPI_CRCPOLYNOMIAL          7
00023 #define BNRG_SPI_BAUDRATEPRESCALER      SPI_BAUDRATEPRESCALER_4
00024 #define BNRG_SPI_CRCCALCULATION         SPI_CRCCALCULATION_DISABLED
00025 
00026 // SPI Reset Pin: PA.8
00027 #define BNRG_SPI_RESET_PIN              GPIO_PIN_8
00028 #define BNRG_SPI_RESET_MODE             GPIO_MODE_OUTPUT_PP
00029 #define BNRG_SPI_RESET_PULL             GPIO_NOPULL
00030 #define BNRG_SPI_RESET_SPEED            GPIO_SPEED_LOW
00031 #define BNRG_SPI_RESET_ALTERNATE        0
00032 #define BNRG_SPI_RESET_PORT             GPIOA
00033 #define BNRG_SPI_RESET_CLK_ENABLE()     __GPIOA_CLK_ENABLE()
00034 
00035 #ifdef USE_PA5
00036 // SPI Clock (SCLK): PA.5
00037 #define BNRG_SPI_SCLK_PIN               GPIO_PIN_5
00038 #define BNRG_SPI_SCLK_MODE              GPIO_MODE_AF_PP
00039 #define BNRG_SPI_SCLK_PULL              GPIO_PULLDOWN
00040 #define BNRG_SPI_SCLK_SPEED             GPIO_SPEED_HIGH
00041 #define BNRG_SPI_SCLK_ALTERNATE         GPIO_AF5_SPI1
00042 #define BNRG_SPI_SCLK_PORT              GPIOA
00043 #define BNRG_SPI_SCLK_CLK_ENABLE()      __GPIOA_CLK_ENABLE()
00044 
00045 #else //USE_PA5
00046 
00047 // Alternative setting for SCLK: PB.3
00048 #define BNRG_SPI_SCLK_PIN               GPIO_PIN_3
00049 #define BNRG_SPI_SCLK_MODE              GPIO_MODE_AF_PP
00050 #define BNRG_SPI_SCLK_PULL              GPIO_PULLUP // or GPIO_PULLDOWN?
00051 #define BNRG_SPI_SCLK_SPEED             GPIO_SPEED_HIGH
00052 #define BNRG_SPI_SCLK_ALTERNATE         GPIO_AF5_SPI1
00053 #define BNRG_SPI_SCLK_PORT              GPIOB
00054 #define BNRG_SPI_SCLK_CLK_ENABLE()      __GPIOB_CLK_ENABLE()
00055 
00056 #endif //USE_PA5
00057 
00058 // MISO (Master Input Slave Output): PA.6
00059 #define BNRG_SPI_MISO_PIN               GPIO_PIN_6
00060 #define BNRG_SPI_MISO_MODE              GPIO_MODE_AF_PP
00061 #define BNRG_SPI_MISO_PULL              GPIO_PULLDOWN
00062 #define BNRG_SPI_MISO_SPEED             GPIO_SPEED_HIGH
00063 #define BNRG_SPI_MISO_ALTERNATE         GPIO_AF5_SPI1
00064 #define BNRG_SPI_MISO_PORT              GPIOA
00065 #define BNRG_SPI_MISO_CLK_ENABLE()      __GPIOA_CLK_ENABLE()
00066 
00067 
00068 // MOSI (Master Output Slave Input): PA.7
00069 #define BNRG_SPI_MOSI_PIN           GPIO_PIN_7
00070 #define BNRG_SPI_MOSI_MODE          GPIO_MODE_AF_PP
00071 #define BNRG_SPI_MOSI_PULL          GPIO_PULLUP
00072 #define BNRG_SPI_MOSI_SPEED         GPIO_SPEED_HIGH
00073 #define BNRG_SPI_MOSI_ALTERNATE     GPIO_AF5_SPI1
00074 #define BNRG_SPI_MOSI_PORT          GPIOA
00075 #define BNRG_SPI_MOSI_CLK_ENABLE()  __GPIOA_CLK_ENABLE()
00076 
00077 // NSS/CSN/CS: PA.1
00078 #define BNRG_SPI_CS_PIN             GPIO_PIN_1
00079 #define BNRG_SPI_CS_MODE            GPIO_MODE_OUTPUT_PP
00080 #define BNRG_SPI_CS_PULL            GPIO_NOPULL
00081 #define BNRG_SPI_CS_SPEED           GPIO_SPEED_HIGH
00082 #define BNRG_SPI_CS_ALTERNATE       0
00083 #define BNRG_SPI_CS_PORT            GPIOA
00084 #define BNRG_SPI_CS_CLK_ENABLE()    __GPIOA_CLK_ENABLE()
00085 
00086 // IRQ: PA.0
00087 #define BNRG_SPI_IRQ_PIN            GPIO_PIN_0
00088 #define BNRG_SPI_IRQ_MODE           GPIO_MODE_IT_RISING
00089 #define BNRG_SPI_IRQ_PULL           GPIO_NOPULL
00090 #define BNRG_SPI_IRQ_SPEED          GPIO_SPEED_HIGH
00091 #define BNRG_SPI_IRQ_ALTERNATE      0
00092 #define BNRG_SPI_IRQ_PORT           GPIOA
00093 #define BNRG_SPI_IRQ_CLK_ENABLE()   __GPIOA_CLK_ENABLE()
00094 
00095 // EXTI External Interrupt for SPI
00096 // NOTE: if you change the IRQ pin remember to update the EXTI definitions below
00097 #define BNRG_SPI_EXTI_IRQn          EXTI0_IRQn
00098 #define BNRG_SPI_EXTI_IRQHandler    EXTI0_IRQHandler
00099 #define BNRG_SPI_EXTI_PIN           BNRG_SPI_IRQ_PIN
00100 #define BNRG_SPI_EXTI_PORT          BNRG_SPI_IRQ_PORT
00101 
00102 /* Exported functions --------------------------------------------------------*/
00103 void BNRG_SPI_Init(void);
00104 void BlueNRG_RST(void);
00105 int32_t BlueNRG_SPI_Read_All(SPI_HandleTypeDef *hspi,
00106                              uint8_t *buffer,
00107                              uint8_t buff_size);
00108 int32_t BlueNRG_SPI_Write(SPI_HandleTypeDef *hspi,
00109                           uint8_t* data1,
00110                           uint8_t* data2,
00111                           uint8_t Nb_bytes1,
00112                           uint8_t Nb_bytes2);
00113 void Hal_Write_Serial(const void* data1, const void* data2, tHalInt32 n_bytes1, tHalInt32 n_bytes2);
00114 void Enable_SPI_IRQ(void);
00115 void Disable_SPI_IRQ(void);
00116 void Clear_SPI_IRQ(void);
00117 void Clear_SPI_EXTI_Flag(void);
00118 
00119 #endif //_BLUENRG_SHIELD_BRP_H_