Robotique FIP / Mbed 2 deprecated FIP_REV1

ble

Dependencies:   HC_SR04_Ultrasonic_Library Servo mbed

Fork of FIP_REV1 by Robotique FIP

BlueNRG_F4_BSP/inc/stm32f4xx_bluenrg_shield_bsp.h@4:69a35a56ac48, 2015-07-09 (annotated)

Committer:
julientiron
Date:
Thu Jul 09 13:33:36 2015 +0000
Revision:
4:69a35a56ac48
Parent:
0:3d641e170a74 
BLE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
julientiron 0:3d641e170a74 1 #ifndef __BLUENRG_SHIELD_BRP_H_
julientiron 0:3d641e170a74 2 #define __BLUENRG_SHIELD_BRP_H_
julientiron 0:3d641e170a74 3 /* Includes ------------------------------------------------------------------*/
julientiron 0:3d641e170a74 4 #include "cube_hal.h"
julientiron 0:3d641e170a74 5 #include "gp_timer.h"
julientiron 0:3d641e170a74 6
julientiron 0:3d641e170a74 7 /* SPI communication details between Nucleo F4 and BlueNRG shield */
julientiron 0:3d641e170a74 8
julientiron 0:3d641e170a74 9 // SPI Instance
julientiron 0:3d641e170a74 10 #define BNRG_SPI_INSTANCE SPI1
julientiron 0:3d641e170a74 11 #define BNRG_SPI_CLK_ENABLE() __SPI1_CLK_ENABLE()
julientiron 0:3d641e170a74 12
julientiron 0:3d641e170a74 13 // SPI Configuration
julientiron 0:3d641e170a74 14 #define BNRG_SPI_MODE SPI_MODE_MASTER
julientiron 0:3d641e170a74 15 #define BNRG_SPI_DIRECTION SPI_DIRECTION_2LINES
julientiron 0:3d641e170a74 16 #define BNRG_SPI_DATASIZE SPI_DATASIZE_8BIT
julientiron 0:3d641e170a74 17 #define BNRG_SPI_CLKPOLARITY SPI_POLARITY_LOW
julientiron 0:3d641e170a74 18 #define BNRG_SPI_CLKPHASE SPI_PHASE_1EDGE
julientiron 0:3d641e170a74 19 #define BNRG_SPI_NSS SPI_NSS_SOFT
julientiron 0:3d641e170a74 20 #define BNRG_SPI_FIRSTBIT SPI_FIRSTBIT_MSB
julientiron 0:3d641e170a74 21 #define BNRG_SPI_TIMODE SPI_TIMODE_DISABLED
julientiron 0:3d641e170a74 22 #define BNRG_SPI_CRCPOLYNOMIAL 7
julientiron 0:3d641e170a74 23 #define BNRG_SPI_BAUDRATEPRESCALER SPI_BAUDRATEPRESCALER_4
julientiron 0:3d641e170a74 24 #define BNRG_SPI_CRCCALCULATION SPI_CRCCALCULATION_DISABLED
julientiron 0:3d641e170a74 25
julientiron 0:3d641e170a74 26 // SPI Reset Pin: PA.8
julientiron 0:3d641e170a74 27 #define BNRG_SPI_RESET_PIN GPIO_PIN_8
julientiron 0:3d641e170a74 28 #define BNRG_SPI_RESET_MODE GPIO_MODE_OUTPUT_PP
julientiron 0:3d641e170a74 29 #define BNRG_SPI_RESET_PULL GPIO_NOPULL
julientiron 0:3d641e170a74 30 #define BNRG_SPI_RESET_SPEED GPIO_SPEED_LOW
julientiron 0:3d641e170a74 31 #define BNRG_SPI_RESET_ALTERNATE 0
julientiron 0:3d641e170a74 32 #define BNRG_SPI_RESET_PORT GPIOA
julientiron 0:3d641e170a74 33 #define BNRG_SPI_RESET_CLK_ENABLE() __GPIOA_CLK_ENABLE()
julientiron 0:3d641e170a74 34
julientiron 0:3d641e170a74 35 #ifdef USE_PA5
julientiron 0:3d641e170a74 36 // SPI Clock (SCLK): PA.5
julientiron 0:3d641e170a74 37 #define BNRG_SPI_SCLK_PIN GPIO_PIN_5
julientiron 0:3d641e170a74 38 #define BNRG_SPI_SCLK_MODE GPIO_MODE_AF_PP
julientiron 0:3d641e170a74 39 #define BNRG_SPI_SCLK_PULL GPIO_PULLDOWN
julientiron 0:3d641e170a74 40 #define BNRG_SPI_SCLK_SPEED GPIO_SPEED_HIGH
julientiron 0:3d641e170a74 41 #define BNRG_SPI_SCLK_ALTERNATE GPIO_AF5_SPI1
julientiron 0:3d641e170a74 42 #define BNRG_SPI_SCLK_PORT GPIOA
julientiron 0:3d641e170a74 43 #define BNRG_SPI_SCLK_CLK_ENABLE() __GPIOA_CLK_ENABLE()
julientiron 0:3d641e170a74 44
julientiron 0:3d641e170a74 45 #else //USE_PA5
julientiron 0:3d641e170a74 46
julientiron 0:3d641e170a74 47 // Alternative setting for SCLK: PB.3
julientiron 0:3d641e170a74 48 #define BNRG_SPI_SCLK_PIN GPIO_PIN_3
julientiron 0:3d641e170a74 49 #define BNRG_SPI_SCLK_MODE GPIO_MODE_AF_PP
julientiron 0:3d641e170a74 50 #define BNRG_SPI_SCLK_PULL GPIO_PULLUP // or GPIO_PULLDOWN?
julientiron 0:3d641e170a74 51 #define BNRG_SPI_SCLK_SPEED GPIO_SPEED_HIGH
julientiron 0:3d641e170a74 52 #define BNRG_SPI_SCLK_ALTERNATE GPIO_AF5_SPI1
julientiron 0:3d641e170a74 53 #define BNRG_SPI_SCLK_PORT GPIOB
julientiron 0:3d641e170a74 54 #define BNRG_SPI_SCLK_CLK_ENABLE() __GPIOB_CLK_ENABLE()
julientiron 0:3d641e170a74 55
julientiron 0:3d641e170a74 56 #endif //USE_PA5
julientiron 0:3d641e170a74 57
julientiron 0:3d641e170a74 58 // MISO (Master Input Slave Output): PA.6
julientiron 0:3d641e170a74 59 #define BNRG_SPI_MISO_PIN GPIO_PIN_6
julientiron 0:3d641e170a74 60 #define BNRG_SPI_MISO_MODE GPIO_MODE_AF_PP
julientiron 0:3d641e170a74 61 #define BNRG_SPI_MISO_PULL GPIO_PULLDOWN
julientiron 0:3d641e170a74 62 #define BNRG_SPI_MISO_SPEED GPIO_SPEED_HIGH
julientiron 0:3d641e170a74 63 #define BNRG_SPI_MISO_ALTERNATE GPIO_AF5_SPI1
julientiron 0:3d641e170a74 64 #define BNRG_SPI_MISO_PORT GPIOA
julientiron 0:3d641e170a74 65 #define BNRG_SPI_MISO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
julientiron 0:3d641e170a74 66
julientiron 0:3d641e170a74 67
julientiron 0:3d641e170a74 68 // MOSI (Master Output Slave Input): PA.7
julientiron 0:3d641e170a74 69 #define BNRG_SPI_MOSI_PIN GPIO_PIN_7
julientiron 0:3d641e170a74 70 #define BNRG_SPI_MOSI_MODE GPIO_MODE_AF_PP
julientiron 0:3d641e170a74 71 #define BNRG_SPI_MOSI_PULL GPIO_PULLUP
julientiron 0:3d641e170a74 72 #define BNRG_SPI_MOSI_SPEED GPIO_SPEED_HIGH
julientiron 0:3d641e170a74 73 #define BNRG_SPI_MOSI_ALTERNATE GPIO_AF5_SPI1
julientiron 0:3d641e170a74 74 #define BNRG_SPI_MOSI_PORT GPIOA
julientiron 0:3d641e170a74 75 #define BNRG_SPI_MOSI_CLK_ENABLE() __GPIOA_CLK_ENABLE()
julientiron 0:3d641e170a74 76
julientiron 0:3d641e170a74 77 // NSS/CSN/CS: PA.1
julientiron 0:3d641e170a74 78 #define BNRG_SPI_CS_PIN GPIO_PIN_1
julientiron 0:3d641e170a74 79 #define BNRG_SPI_CS_MODE GPIO_MODE_OUTPUT_PP
julientiron 0:3d641e170a74 80 #define BNRG_SPI_CS_PULL GPIO_NOPULL
julientiron 0:3d641e170a74 81 #define BNRG_SPI_CS_SPEED GPIO_SPEED_HIGH
julientiron 0:3d641e170a74 82 #define BNRG_SPI_CS_ALTERNATE 0
julientiron 0:3d641e170a74 83 #define BNRG_SPI_CS_PORT GPIOA
julientiron 0:3d641e170a74 84 #define BNRG_SPI_CS_CLK_ENABLE() __GPIOA_CLK_ENABLE()
julientiron 0:3d641e170a74 85
julientiron 0:3d641e170a74 86 // IRQ: PA.0
julientiron 0:3d641e170a74 87 #define BNRG_SPI_IRQ_PIN GPIO_PIN_0
julientiron 0:3d641e170a74 88 #define BNRG_SPI_IRQ_MODE GPIO_MODE_IT_RISING
julientiron 0:3d641e170a74 89 #define BNRG_SPI_IRQ_PULL GPIO_NOPULL
julientiron 0:3d641e170a74 90 #define BNRG_SPI_IRQ_SPEED GPIO_SPEED_HIGH
julientiron 0:3d641e170a74 91 #define BNRG_SPI_IRQ_ALTERNATE 0
julientiron 0:3d641e170a74 92 #define BNRG_SPI_IRQ_PORT GPIOA
julientiron 0:3d641e170a74 93 #define BNRG_SPI_IRQ_CLK_ENABLE() __GPIOA_CLK_ENABLE()
julientiron 0:3d641e170a74 94
julientiron 0:3d641e170a74 95 // EXTI External Interrupt for SPI
julientiron 0:3d641e170a74 96 // NOTE: if you change the IRQ pin remember to update the EXTI definitions below
julientiron 0:3d641e170a74 97 #define BNRG_SPI_EXTI_IRQn EXTI0_IRQn
julientiron 0:3d641e170a74 98 #define BNRG_SPI_EXTI_IRQHandler EXTI0_IRQHandler
julientiron 0:3d641e170a74 99 #define BNRG_SPI_EXTI_PIN BNRG_SPI_IRQ_PIN
julientiron 0:3d641e170a74 100 #define BNRG_SPI_EXTI_PORT BNRG_SPI_IRQ_PORT
julientiron 0:3d641e170a74 101
julientiron 0:3d641e170a74 102 /* Exported functions --------------------------------------------------------*/
julientiron 0:3d641e170a74 103 void BNRG_SPI_Init(void);
julientiron 0:3d641e170a74 104 void BlueNRG_RST(void);
julientiron 0:3d641e170a74 105 int32_t BlueNRG_SPI_Read_All(SPI_HandleTypeDef *hspi,
julientiron 0:3d641e170a74 106 uint8_t *buffer,
julientiron 0:3d641e170a74 107 uint8_t buff_size);
julientiron 0:3d641e170a74 108 int32_t BlueNRG_SPI_Write(SPI_HandleTypeDef *hspi,
julientiron 0:3d641e170a74 109 uint8_t* data1,
julientiron 0:3d641e170a74 110 uint8_t* data2,
julientiron 0:3d641e170a74 111 uint8_t Nb_bytes1,
julientiron 0:3d641e170a74 112 uint8_t Nb_bytes2);
julientiron 0:3d641e170a74 113 void Hal_Write_Serial(const void* data1, const void* data2, tHalInt32 n_bytes1, tHalInt32 n_bytes2);
julientiron 0:3d641e170a74 114 void Enable_SPI_IRQ(void);
julientiron 0:3d641e170a74 115 void Disable_SPI_IRQ(void);
julientiron 0:3d641e170a74 116 void Clear_SPI_IRQ(void);
julientiron 0:3d641e170a74 117 void Clear_SPI_EXTI_Flag(void);
julientiron 0:3d641e170a74 118
julientiron 0:3d641e170a74 119 #endif //_BLUENRG_SHIELD_BRP_H_