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mbed-src-bmd-200
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Dependents: mbed_blinky-bmd-200 bmd-200_accel_demo firstRig
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Revision 584:3c14cb9b87c5, committed 2015-07-02
- Comitter:
- mbed_official
- Date:
- Thu Jul 02 16:15:09 2015 +0100
- Parent:
- 583:53297373a894
- Child:
- 585:39197bcd20f2
- Commit message:
- Synchronized with git revision 213caf296f26963a7bea129b8ec4f33bbd1e6588
Full URL: https://github.com/mbedmicro/mbed/commit/213caf296f26963a7bea129b8ec4f33bbd1e6588/
commit of mps2
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,725 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* @file CMSDK_CM0.h
+* @brief CMSIS Core Peripheral Access Layer Header File for
+* CMSDK_CM0 Device
+* @version V3.02
+* @date 15. November 2013
+*
+* @note configured for CM7 without FPU
+*
+*******************************************************************************/
+
+
+#ifndef CMSDK_CM0_H
+#define CMSDK_CM0_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+
+
+
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+
+/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */
+ UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
+ UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
+ UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
+ UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
+ UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
+ UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
+ PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */
+ PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */
+ TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
+ TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
+ DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
+ SPI_IRQn = 11, /* SPI Interrupt */
+ UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
+ ETHERNET_IRQn = 13, /* Ethernet Interrupt */
+ I2S_IRQn = 14, /* I2S Interrupt */
+ TSC_IRQn = 15, /* Touch Screen Interrupt */
+// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
+ PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
+ PORT0_1_IRQn = 17, /* There are 16 pins in total */
+ PORT0_2_IRQn = 18,
+ PORT0_3_IRQn = 19,
+ PORT0_4_IRQn = 20,
+ PORT0_5_IRQn = 21,
+ PORT0_6_IRQn = 22,
+ PORT0_7_IRQn = 23,
+ PORT0_8_IRQn = 24,
+ PORT0_9_IRQn = 25,
+ PORT0_10_IRQn = 26,
+ PORT0_11_IRQn = 27,
+ PORT0_12_IRQn = 28,
+ PORT0_13_IRQn = 29,
+ PORT0_14_IRQn = 30,
+ PORT0_15_IRQn = 31,
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* -------- Configuration of the Cortex-M0 Processor and Core Peripherals ------- */
+#define __CM0_REV 0x0000 /* Core revision r0p0 */
+#define __MPU_PRESENT 0 /* MPU present or not */
+#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+
+#include <core_cm0.h> /* Processor and core peripherals */
+#include "system_CMSDK_CM0.h" /* System Header */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined ( __CC_ARM )
+ #pragma push
+#pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
+ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
+ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
+ };
+ __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
+
+} CMSDK_UART_TypeDef;
+
+/* CMSDK_UART DATA Register Definitions */
+
+#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
+#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
+
+#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
+#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
+
+#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
+#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
+
+#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
+#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
+
+#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
+#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
+
+#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
+#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
+
+#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
+#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
+#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
+#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
+#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
+#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
+
+#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
+#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
+
+#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
+#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
+#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
+#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
+#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
+
+#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
+#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
+
+
+/*----------------------------- Timer (TIMER) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
+ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
+ };
+
+} CMSDK_TIMER_TypeDef;
+
+/* CMSDK_TIMER CTRL Register Definitions */
+
+#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
+#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
+
+#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
+#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
+
+#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
+#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
+
+#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
+#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
+
+#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
+#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
+
+#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
+#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
+
+#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
+#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
+
+#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
+#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
+
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
+ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
+ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
+ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
+ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
+ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
+ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
+ uint32_t RESERVED0;
+ __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
+ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
+ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
+ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
+ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
+ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
+ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
+ uint32_t RESERVED1[945];
+ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
+ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
+} CMSDK_DUALTIMER_BOTH_TypeDef;
+
+#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
+#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
+#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
+
+#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
+#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
+#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
+
+
+typedef struct
+{
+ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
+ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
+ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
+ __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
+ __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
+ __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
+ __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
+} CMSDK_DUALTIMER_SINGLE_TypeDef;
+
+#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
+#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
+#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
+
+
+/*-------------------- General Purpose Input Output (GPIO) -------------------*/
+typedef struct
+{
+ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
+ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
+ __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
+ __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
+ __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
+ __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
+ __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
+ __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
+ __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
+ __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
+ __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
+ };
+ uint32_t RESERVED1[241];
+ __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
+ __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
+} CMSDK_GPIO_TypeDef;
+
+#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
+#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
+
+#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
+#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
+
+#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
+#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
+
+#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
+#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
+
+#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
+#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
+
+#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
+#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
+
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+typedef struct
+{
+ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
+ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
+ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
+ __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
+ __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
+} CMSDK_SYSCON_TypeDef;
+
+#define CMSDK_SYSCON_REMAP_Pos 0
+#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
+
+#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
+#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
+
+#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
+#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
+#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
+#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
+#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
+#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
+
+#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
+#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
+
+#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
+#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
+
+#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
+#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
+
+
+/*------------- PL230 uDMA (PL230) --------------------------------------*/
+typedef struct
+{
+ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
+ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
+ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
+ __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
+ __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
+ __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
+ __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
+ __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
+ __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
+ __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
+ __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
+ __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
+ __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
+ __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
+ __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
+ __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
+ uint32_t RESERVED0[3];
+ __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
+
+} CMSDK_PL230_TypeDef;
+
+#define PL230_DMA_CHNL_BITS 0
+
+#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
+#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
+#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
+
+#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
+#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
+
+#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
+#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
+
+#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
+#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
+#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
+#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
+#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
+
+#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
+#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
+
+#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
+#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
+#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
+
+#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
+#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
+
+#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
+#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
+
+#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
+#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
+
+#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
+#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
+
+#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
+#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
+
+#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
+#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
+
+#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
+#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
+
+#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
+#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
+
+#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
+#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
+
+#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
+#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
+
+#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
+#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
+
+#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
+#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
+
+
+/*------------------- Watchdog ----------------------------------------------*/
+typedef struct
+{
+
+ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
+ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
+ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
+ __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
+ __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
+ __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
+ uint32_t RESERVED0[762];
+ __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
+ uint32_t RESERVED1[191];
+ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
+ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
+}CMSDK_WATCHDOG_TypeDef;
+
+#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
+#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
+
+#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
+#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
+
+#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
+#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
+
+#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
+#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
+
+#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
+#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
+
+#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
+#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
+
+#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
+#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
+
+#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
+#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
+
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined ( __CC_ARM )
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+/* Peripheral and SRAM base address */
+#define CMSDK_FLASH_BASE (0x00000000UL)
+#define CMSDK_SRAM_BASE (0x20000000UL)
+#define CMSDK_PERIPH_BASE (0x40000000UL)
+
+#define CMSDK_RAM_BASE (0x20000000UL)
+#define CMSDK_APB_BASE (0x40000000UL)
+#define CMSDK_AHB_BASE (0x40010000UL)
+
+/* APB peripherals */
+#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
+#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
+#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
+#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
+#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
+#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
+#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
+#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
+#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
+#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
+
+/* AHB peripherals */
+#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
+#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
+#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
+#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
+#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
+#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
+#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
+#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
+#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
+#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
+#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
+#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
+#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
+#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
+#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
+#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
+#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
+#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
+#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CMSDK_M0_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,595 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* File: smm_mps2.h
+* Release: Version 1.0
+*******************************************************************************/
+
+#ifndef __SMM_MPS2_H
+#define __SMM_MPS2_H
+
+#include "peripherallink.h" /* device specific header file */
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/******************************************************************************/
+/* FPGA System Register declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
+ // [31:2] : Reserved
+ // [1:0] : LEDs
+ uint32_t RESERVED1[1];
+ __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
+ // [31:2] : Reserved
+ // [1:0] : Buttons
+ uint32_t RESERVED2[1];
+ __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
+ __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
+ __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
+ // Increments when 32-bit prescale counter reach zero
+ uint32_t RESERVED3[1];
+ __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
+ // Bit[31:0] : reload value for prescale counter
+ __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
+ // current value of the pre-scaler counter
+ // The Cycle Up Counter increment when the prescale down counter reach 0
+ // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+ uint32_t RESERVED4[9];
+ __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
+ // [31:7] : Reserved
+ // [6] : CLCD_BL_CTRL
+ // [5] : CLCD_RD
+ // [4] : CLCD_RS
+ // [3] : CLCD_RESET
+ // [2] : RESERVED
+ // [1] : SPI_nSS
+ // [0] : CLCD_CS
+} MPS2_FPGAIO_TypeDef;
+
+// MISC register bit definitions
+
+#define CLCD_CS_Pos 0
+#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
+#define SPI_nSS_Pos 1
+#define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
+#define CLCD_RESET_Pos 3
+#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
+#define CLCD_RS_Pos 4
+#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
+#define CLCD_RD_Pos 5
+#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
+#define CLCD_BL_Pos 6
+#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
+
+/******************************************************************************/
+/* SCC Register declaration */
+/******************************************************************************/
+
+typedef struct //
+{
+ __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
+ // [31:1] : Reserved
+ // [0] 1 : REMAP BlockRam to ZBT
+ __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
+ // [31:8] : Reserved
+ // [7:0] : MCC LEDs
+ uint32_t RESERVED0[1];
+ __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
+ // [31:8] : Reserved
+ // [7:0] : These bits indicate state of the MCC switches
+ __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
+ // [31:4] : Reserved
+ // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
+ uint32_t RESERVED1[35];
+ __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
+ // [31:0] : Data
+ __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
+ // [31:0] : Data
+ __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
+ // [31] : Start (generates interrupt on write to this bit)
+ // [30] : R/W access
+ // [29:26] : Reserved
+ // [25:20] : Function value
+ // [19:12] : Reserved
+ // [11:0] : Device (value of 0/1/2 for supported clocks)
+ __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
+ // [31:2] : Reserved
+ // [1] : Error
+ // [0] : Complete
+ __IO uint32_t RESERVED2[20];
+ __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
+ // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
+ // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
+ // [15:1] : Reserved
+ // [0] : This bit indicates if all enabled DLLs are locked
+ uint32_t RESERVED3[957];
+ __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
+ // [31:24] : FPGA build number
+ // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
+ // [19:11] : Reserved
+ // [10] : if “1” SCC_SW register has been implemented
+ // [9] : if “1” SCC_LED register has been implemented
+ // [8] : if “1” DLL lock register has been implemented
+ // [7:0] : number of SCC configuration register
+ __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
+ // [31:24] : Implementer ID: 0x41 = ARM
+ // [23:20] : Application note IP variant number
+ // [19:16] : IP Architecture: 0x4 =AHB
+ // [15:4] : Primary part number: 386 = AN386
+ // [3:0] : Application note IP revision number
+} MPS2_SCC_TypeDef;
+
+
+/******************************************************************************/
+/* SSP Peripheral declaration */
+/******************************************************************************/
+
+typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
+{
+ __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
+ // [31:16] : Reserved
+ // [15:8] : Serial clock rate
+ // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
+ // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
+ // [5:4] : Frame format
+ // [3:0] : Data Size Select
+ __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
+ // [31:4] : Reserved
+ // [3] : Slave-mode output disable
+ // [2] : Master or slave mode select
+ // [1] : Synchronous serial port enable
+ // [0] : Loop back mode
+ __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
+ // [31:16] : Reserved
+ // [15:0] : Transmit/Receive FIFO
+ __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
+ // [31:5] : Reserved
+ // [4] : PrimeCell SSP busy flag
+ // [3] : Receive FIFO full
+ // [2] : Receive FIFO not empty
+ // [1] : Transmit FIFO not full
+ // [0] : Transmit FIFO empty
+ __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
+ // [31:8] : Reserved
+ // [8:0] : Clock prescale divisor
+ __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
+ // [31:4] : Reserved
+ // [3] : Transmit FIFO interrupt mask
+ // [2] : Receive FIFO interrupt mask
+ // [1] : Receive timeout interrupt mask
+ // [0] : Receive overrun interrupt mask
+ __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
+ // [31:4] : Reserved
+ // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
+ // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
+ // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
+ // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
+ __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
+ // [31:4] : Reserved
+ // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
+ // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
+ // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
+ // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
+ __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
+ // [31:2] : Reserved
+ // [1] : Clears the SSPRTINTR interrupt
+ // [0] : Clears the SSPRORINTR interrupt
+ __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
+ // [31:2] : Reserved
+ // [1] : Transmit DMA Enable
+ // [0] : Receive DMA Enable
+} MPS2_SSP_TypeDef;
+
+
+// SSP_CR0 Control register 0
+#define SSP_CR0_DSS_Pos 0 // Data Size Select
+#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
+#define SSP_CR0_FRF_Pos 4 // Frame Format Select
+#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
+#define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
+#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
+#define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
+#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
+#define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
+#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
+
+#define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
+#define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
+#define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
+#define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
+
+// SSP_CR1 Control register 1
+#define SSP_CR1_LBM_Pos 0 // Loop Back Mode
+#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
+#define SSP_CR1_SSE_Pos 1 // Serial port enable
+#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
+#define SSP_CR1_MS_Pos 2 // Master or Slave mode
+#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
+#define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
+#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
+
+// SSP_SR Status register
+#define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
+#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
+#define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
+#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
+#define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
+#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
+#define SSP_SR_RFF_Pos 3 // Receive FIFO full
+#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
+#define SSP_SR_BSY_Pos 4 // Busy
+#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
+
+// SSP_CPSR Clock prescale register
+#define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
+#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
+
+#define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
+
+// SSPIMSC Interrupt mask set and clear register
+#define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
+#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
+#define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
+#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
+#define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
+#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
+#define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
+#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
+
+// SSPRIS Raw interrupt status register
+#define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
+#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
+#define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
+#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
+#define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
+#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
+#define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
+#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
+
+// SSPMIS Masked interrupt status register
+#define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
+#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
+#define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
+#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
+#define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
+#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
+#define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
+#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
+
+// SSPICR Interrupt clear register
+#define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
+#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
+#define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
+#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
+
+// SSPDMACR DMA control register
+#define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
+#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
+#define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
+#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
+
+/******************************************************************************/
+/* Audio and Touch Screen (I2C) Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ union {
+ __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
+ __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
+ };
+ __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
+} MPS2_I2C_TypeDef;
+
+#define SDA 1 << 1
+#define SCL 1 << 0
+
+
+/******************************************************************************/
+/* Audio I2S Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ /*!< Offset: 0x000 CONTROL Register (R/W) */
+ __IO uint32_t CONTROL; // <h> CONTROL </h>
+ // <o.0> TX Enable
+ // <0=> TX disabled
+ // <1=> TX enabled
+ // <o.1> TX IRQ Enable
+ // <0=> TX IRQ disabled
+ // <1=> TX IRQ enabled
+ // <o.2> RX Enable
+ // <0=> RX disabled
+ // <1=> RX enabled
+ // <o.3> RX IRQ Enable
+ // <0=> RX IRQ disabled
+ // <1=> RX IRQ enabled
+ // <o.10..8> TX Buffer Water Level
+ // <0=> / IRQ triggers when any space available
+ // <1=> / IRQ triggers when more than 1 space available
+ // <2=> / IRQ triggers when more than 2 space available
+ // <3=> / IRQ triggers when more than 3 space available
+ // <4=> Undefined!
+ // <5=> Undefined!
+ // <6=> Undefined!
+ // <7=> Undefined!
+ // <o.14..12> RX Buffer Water Level
+ // <0=> Undefined!
+ // <1=> / IRQ triggers when less than 1 space available
+ // <2=> / IRQ triggers when less than 2 space available
+ // <3=> / IRQ triggers when less than 3 space available
+ // <4=> / IRQ triggers when less than 4 space available
+ // <5=> Undefined!
+ // <6=> Undefined!
+ // <7=> Undefined!
+ // <o.16> FIFO reset
+ // <0=> Normal operation
+ // <1=> FIFO reset
+ // <o.17> Audio Codec reset
+ // <0=> Normal operation
+ // <1=> Assert audio Codec reset
+ /*!< Offset: 0x004 STATUS Register (R/ ) */
+ __I uint32_t STATUS; // <h> STATUS </h>
+ // <o.0> TX Buffer alert
+ // <0=> TX buffer don't need service yet
+ // <1=> TX buffer need service
+ // <o.1> RX Buffer alert
+ // <0=> RX buffer don't need service yet
+ // <1=> RX buffer need service
+ // <o.2> TX Buffer Empty
+ // <0=> TX buffer have data
+ // <1=> TX buffer empty
+ // <o.3> TX Buffer Full
+ // <0=> TX buffer not full
+ // <1=> TX buffer full
+ // <o.4> RX Buffer Empty
+ // <0=> RX buffer have data
+ // <1=> RX buffer empty
+ // <o.5> RX Buffer Full
+ // <0=> RX buffer not full
+ // <1=> RX buffer full
+ union {
+ /*!< Offset: 0x008 Error Status Register (R/ ) */
+ __I uint32_t ERROR; // <h> ERROR </h>
+ // <o.0> TX error
+ // <0=> Okay
+ // <1=> TX overrun/underrun
+ // <o.1> RX error
+ // <0=> Okay
+ // <1=> RX overrun/underrun
+ /*!< Offset: 0x008 Error Clear Register ( /W) */
+ __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
+ // <o.0> TX error
+ // <0=> Okay
+ // <1=> Clear TX error
+ // <o.1> RX error
+ // <0=> Okay
+ // <1=> Clear RX error
+ };
+ /*!< Offset: 0x00C Divide ratio Register (R/W) */
+ __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
+ // <o.9..0> TX error (default 0x80)
+ /*!< Offset: 0x010 Transmit Buffer ( /W) */
+ __O uint32_t TXBUF; // <h> Transmit buffer </h>
+ // <o.15..0> Right channel
+ // <o.31..16> Left channel
+ /*!< Offset: 0x014 Receive Buffer (R/ ) */
+ __I uint32_t RXBUF; // <h> Receive buffer </h>
+ // <o.15..0> Right channel
+ // <o.31..16> Left channel
+ uint32_t RESERVED1[186];
+ __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
+ // <o.0> ITEN
+ // <0=> Normal operation
+ // <1=> Integration Test mode enable
+ __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
+ // <o.0> SDIN
+ __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
+ // <o.0> SDOUT
+ // <o.1> SCLK
+ // <o.2> LRCK
+ // <o.3> IRQOUT
+} MPS2_I2S_TypeDef;
+
+#define I2S_CONTROL_TXEN_Pos 0
+#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
+
+#define I2S_CONTROL_TXIRQEN_Pos 1
+#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
+
+#define I2S_CONTROL_RXEN_Pos 2
+#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
+
+#define I2S_CONTROL_RXIRQEN_Pos 3
+#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
+
+#define I2S_CONTROL_TXWLVL_Pos 8
+#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
+
+#define I2S_CONTROL_RXWLVL_Pos 12
+#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
+/* FIFO reset*/
+#define I2S_CONTROL_FIFORST_Pos 16
+#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
+/* Codec reset*/
+#define I2S_CONTROL_CODECRST_Pos 17
+#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
+
+#define I2S_STATUS_TXIRQ_Pos 0
+#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
+
+#define I2S_STATUS_RXIRQ_Pos 1
+#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
+
+#define I2S_STATUS_TXEmpty_Pos 2
+#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
+
+#define I2S_STATUS_TXFull_Pos 3
+#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
+
+#define I2S_STATUS_RXEmpty_Pos 4
+#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
+
+#define I2S_STATUS_RXFull_Pos 5
+#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
+
+#define I2S_ERROR_TXERR_Pos 0
+#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
+
+#define I2S_ERROR_RXERR_Pos 1
+#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
+
+/******************************************************************************/
+/* SMSC9220 Register Definitions */
+/******************************************************************************/
+
+typedef struct // SMSC LAN9220
+{
+__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
+ uint32_t RESERVED1[0x7];
+__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
+ uint32_t RESERVED2[0x7];
+
+__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
+__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
+__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
+__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
+
+__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
+__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
+__IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
+__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
+ uint32_t RESERVED3; // Reserved for future use (offset 0x60)
+__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
+__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
+__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
+__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
+__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
+__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
+__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
+__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
+__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
+__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
+__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
+__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
+ uint32_t RESERVED4; // Reserved for future use (offset 0x94)
+__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
+__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
+__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
+__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
+__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
+__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
+__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
+__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
+
+} SMSC9220_TypeDef;
+
+// SMSC9220 MAC Registers Indices
+#define SMSC9220_MAC_CR 0x1
+#define SMSC9220_MAC_ADDRH 0x2
+#define SMSC9220_MAC_ADDRL 0x3
+#define SMSC9220_MAC_HASHH 0x4
+#define SMSC9220_MAC_HASHL 0x5
+#define SMSC9220_MAC_MII_ACC 0x6
+#define SMSC9220_MAC_MII_DATA 0x7
+#define SMSC9220_MAC_FLOW 0x8
+#define SMSC9220_MAC_VLAN1 0x9
+#define SMSC9220_MAC_VLAN2 0xA
+#define SMSC9220_MAC_WUFF 0xB
+#define SMSC9220_MAC_WUCSR 0xC
+
+// SMSC9220 PHY Registers Indices
+#define SMSC9220_PHY_BCONTROL 0x0
+#define SMSC9220_PHY_BSTATUS 0x1
+#define SMSC9220_PHY_ID1 0x2
+#define SMSC9220_PHY_ID2 0x3
+#define SMSC9220_PHY_ANEG_ADV 0x4
+#define SMSC9220_PHY_ANEG_LPA 0x5
+#define SMSC9220_PHY_ANEG_EXP 0x6
+#define SMSC9220_PHY_MCONTROL 0x17
+#define SMSC9220_PHY_MSTATUS 0x18
+#define SMSC9220_PHY_CSINDICATE 0x27
+#define SMSC9220_PHY_INTSRC 0x29
+#define SMSC9220_PHY_INTMASK 0x30
+#define SMSC9220_PHY_CS 0x31
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+
+#define MPS2_SSP1_BASE (0x40020000ul) /* User SSP Base Address */
+#define MPS2_SSP0_BASE (0x40021000ul) /* CLCD SSP Base Address */
+#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
+#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
+#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
+#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
+#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
+
+#ifdef CORTEX_M7
+#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
+#else
+#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
+#endif
+
+#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
+#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+
+#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
+#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
+#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
+#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
+#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
+#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
+#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
+#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
+
+/******************************************************************************/
+/* General Function Definitions */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/* General MACRO Definitions */
+/******************************************************************************/
+
+
+
+#endif /* __SMM_MPS2_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,47 @@
+;* MPS2 CMSIS Library
+;*
+;* Copyright (c) 2006-2015 ARM Limited
+;* All rights reserved.
+;*
+;* Redistribution and use in source and binary forms, with or without
+;* modification, are permitted provided that the following conditions are met:
+;*
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;*
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;*
+;* 3. Neither the name of the copyright holder nor the names of its contributors
+;* may be used to endorse or promote products derived from this software without
+;* specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
+;*
+; *************************************************************
+; *** Scatter-Loading Description File ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00400000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/startup_MPS2.s Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,271 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Core Device Startup File for +; * CMSDK_CM0 Device +; * @version V3.02 +; * @date 04. February 2015 +; * +; * @note +; * Copyright (C) 2015 ARM Limited. All rights reserved. +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2015 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler + DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler + DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler + DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler + DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler + DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler + DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler + DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler + DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + EXPORT PORT0_8_Handler [WEAK] + EXPORT PORT0_9_Handler [WEAK] + EXPORT PORT0_10_Handler [WEAK] + EXPORT PORT0_11_Handler [WEAK] + EXPORT PORT0_12_Handler [WEAK] + EXPORT PORT0_13_Handler [WEAK] + EXPORT PORT0_14_Handler [WEAK] + EXPORT PORT0_15_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler +PORT0_8_Handler +PORT0_9_Handler +PORT0_10_Handler +PORT0_11_Handler +PORT0_12_Handler +PORT0_13_Handler +PORT0_14_Handler +PORT0_15_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,42 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in MPS2 specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_CM0.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,54 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* CMSIS-style functionality to support dynamic vectors
+*******************************************************************************/
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ // int i;
+ // Space for dynamic vectors, initialised to allocate in R/W
+ static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
+
+ // Set the vector
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ // We can always read vectors at 0x0, as the addresses are remapped
+ uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
+
+ // Return the vector
+ return vectors[IRQn + 16];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,54 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* CMSIS-style functionality to support dynamic vectors
+*******************************************************************************/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,53 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* Name: Device.h +* Purpose: Include the correct device header file +*******************************************************************************/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_CM0 + #include "CMSDK_CM0.h" /* device specific header file */ +#elif defined CMSDK_CM0plus + #include "CMSDK_CM0plus.h" /* device specific header file */ +#elif defined CMSDK_CM3 + #include "CMSDK_CM3.h" /* device specific header file */ +#elif defined CMSDK_CM4 + #include "CMSDK_CM4.h" /* device specific header file */ +#elif defined CMSDK_CM7 + #include "CMSDK_CM7.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,92 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* @file system_CMSDK_CM0.c
+* @brief CMSIS Device System Source File for
+* CMSDK_M0 Device
+* @version V3.02
+* @date 15. November 2013
+*
+* @note
+*
+*******************************************************************************/
+
+
+#include "CMSDK_CM0.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (50000000UL) /* Oscillator frequency */
+
+#define __SYSTEM_CLOCK (__XTAL / 2)
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate (void)
+{
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,80 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+*******************************************************************************
+* @file system_CMSDK_CM0.h
+* @brief CMSIS Device Peripheral Access Layer Header File for
+* CMSDK_CM0 Device
+* @version V3.02
+* @date 15. March 2013
+*
+* @note
+*
+******************************************************************************/
+
+
+#ifndef SYSTEM_CMSDK_CM0_H
+#define SYSTEM_CMSDK_CM0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CMSDK_CM0_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,726 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* @file CMSDK_CM0plus.h
+* @brief CMSIS Core Peripheral Access Layer Header File for
+* CMSDK_CM0plus Device
+* @version V3.02
+* @date 15. November 2013
+*
+* @note configured for CM7 without FPU
+*
+*******************************************************************************/
+
+
+#ifndef CMSDK_CM0plus_H
+#define CMSDK_CM0plus_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/* ------------------- Cortex-M0+ Processor Exceptions Numbers ------------------ */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+
+
+
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+
+/* ---------------------- CMSDK_CM0plus Specific Interrupt Numbers -------------- */
+ UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
+ UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
+ UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
+ UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
+ UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
+ UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
+ PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */
+ PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */
+ TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
+ TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
+ DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
+ SPI_IRQn = 11, /* SPI Interrupt */
+ UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
+ ETHERNET_IRQn = 13, /* Ethernet Interrupt */
+ I2S_IRQn = 14, /* I2S Interrupt */
+ TSC_IRQn = 15, /* Touch Screen Interrupt */
+// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
+ PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
+ PORT0_1_IRQn = 17, /* There are 16 pins in total */
+ PORT0_2_IRQn = 18,
+ PORT0_3_IRQn = 19,
+ PORT0_4_IRQn = 20,
+ PORT0_5_IRQn = 21,
+ PORT0_6_IRQn = 22,
+ PORT0_7_IRQn = 23,
+ PORT0_8_IRQn = 24,
+ PORT0_9_IRQn = 25,
+ PORT0_10_IRQn = 26,
+ PORT0_11_IRQn = 27,
+ PORT0_12_IRQn = 28,
+ PORT0_13_IRQn = 29,
+ PORT0_14_IRQn = 30,
+ PORT0_15_IRQn = 31,
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* -------- Configuration of the Cortex-M0+ Processor and Core Peripherals ------ */
+#define __CM0PLUS_REV 0x0000 /* Core revision r0p0 */
+#define __MPU_PRESENT 1 /* MPU present or not */
+#define __VTOR_PRESENT 1 /* VTOR present or not */
+#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+
+#include <core_cm0plus.h> /* Processor and core peripherals */
+#include "system_CMSDK_CM0plus.h" /* System Header */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined ( __CC_ARM )
+ #pragma push
+#pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
+ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
+ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
+ };
+ __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
+
+} CMSDK_UART_TypeDef;
+
+/* CMSDK_UART DATA Register Definitions */
+
+#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
+#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
+
+#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
+#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
+
+#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
+#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
+
+#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
+#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
+
+#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
+#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
+
+#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
+#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
+
+#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
+#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
+#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
+#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
+#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
+#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
+
+#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
+#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
+
+#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
+#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
+#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
+#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
+#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
+
+#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
+#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
+
+
+/*----------------------------- Timer (TIMER) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
+ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
+ };
+
+} CMSDK_TIMER_TypeDef;
+
+/* CMSDK_TIMER CTRL Register Definitions */
+
+#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
+#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
+
+#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
+#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
+
+#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
+#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
+
+#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
+#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
+
+#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
+#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
+
+#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
+#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
+
+#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
+#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
+
+#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
+#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
+
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
+ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
+ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
+ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
+ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
+ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
+ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
+ uint32_t RESERVED0;
+ __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
+ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
+ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
+ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
+ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
+ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
+ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
+ uint32_t RESERVED1[945];
+ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
+ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
+} CMSDK_DUALTIMER_BOTH_TypeDef;
+
+#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
+#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
+#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
+
+#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
+#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
+#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
+
+
+typedef struct
+{
+ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
+ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
+ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
+ __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
+ __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
+ __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
+ __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
+} CMSDK_DUALTIMER_SINGLE_TypeDef;
+
+#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
+#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
+#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
+
+
+/*-------------------- General Purpose Input Output (GPIO) -------------------*/
+typedef struct
+{
+ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
+ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
+ __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
+ __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
+ __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
+ __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
+ __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
+ __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
+ __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
+ __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
+ __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
+ };
+ uint32_t RESERVED1[241];
+ __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
+ __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
+} CMSDK_GPIO_TypeDef;
+
+#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
+#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
+
+#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
+#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
+
+#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
+#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
+
+#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
+#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
+
+#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
+#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
+
+#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
+#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
+
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+typedef struct
+{
+ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
+ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
+ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
+ __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
+ __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
+} CMSDK_SYSCON_TypeDef;
+
+#define CMSDK_SYSCON_REMAP_Pos 0
+#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
+
+#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
+#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
+
+#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
+#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
+#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
+#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
+#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
+#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
+
+#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
+#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
+
+#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
+#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
+
+#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
+#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
+
+
+/*------------- PL230 uDMA (PL230) --------------------------------------*/
+typedef struct
+{
+ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
+ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
+ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
+ __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
+ __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
+ __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
+ __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
+ __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
+ __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
+ __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
+ __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
+ __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
+ __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
+ __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
+ __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
+ __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
+ uint32_t RESERVED0[3];
+ __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
+
+} CMSDK_PL230_TypeDef;
+
+#define PL230_DMA_CHNL_BITS 0
+
+#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
+#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
+#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
+
+#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
+#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
+
+#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
+#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
+
+#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
+#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
+#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
+#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
+#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
+
+#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
+#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
+
+#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
+#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
+#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
+
+#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
+#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
+
+#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
+#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
+
+#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
+#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
+
+#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
+#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
+
+#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
+#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
+
+#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
+#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
+
+#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
+#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
+
+#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
+#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
+
+#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
+#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
+
+#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
+#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
+
+#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
+#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
+
+#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
+#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
+
+
+/*------------------- Watchdog ----------------------------------------------*/
+typedef struct
+{
+
+ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
+ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
+ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
+ __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
+ __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
+ __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
+ uint32_t RESERVED0[762];
+ __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
+ uint32_t RESERVED1[191];
+ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
+ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
+}CMSDK_WATCHDOG_TypeDef;
+
+#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
+#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
+
+#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
+#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
+
+#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
+#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
+
+#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
+#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
+
+#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
+#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
+
+#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
+#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
+
+#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
+#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
+
+#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
+#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
+
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined ( __CC_ARM )
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+/* Peripheral and SRAM base address */
+#define CMSDK_FLASH_BASE (0x00000000UL)
+#define CMSDK_SRAM_BASE (0x20000000UL)
+#define CMSDK_PERIPH_BASE (0x40000000UL)
+
+#define CMSDK_RAM_BASE (0x20000000UL)
+#define CMSDK_APB_BASE (0x40000000UL)
+#define CMSDK_AHB_BASE (0x40010000UL)
+
+/* APB peripherals */
+#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
+#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
+#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
+#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
+#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
+#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
+#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
+#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
+#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
+#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
+
+/* AHB peripherals */
+#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
+#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
+#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
+#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
+#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
+#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
+#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
+#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
+#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
+#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
+#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
+#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
+#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
+#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
+#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
+#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
+#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
+#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
+#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CMSDK_CM0plus_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,595 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* File: smm_mps2.h
+* Release: Version 1.0
+*******************************************************************************/
+
+#ifndef __SMM_MPS2_H
+#define __SMM_MPS2_H
+
+#include "peripherallink.h" /* device specific header file */
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/******************************************************************************/
+/* FPGA System Register declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
+ // [31:2] : Reserved
+ // [1:0] : LEDs
+ uint32_t RESERVED1[1];
+ __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
+ // [31:2] : Reserved
+ // [1:0] : Buttons
+ uint32_t RESERVED2[1];
+ __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
+ __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
+ __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
+ // Increments when 32-bit prescale counter reach zero
+ uint32_t RESERVED3[1];
+ __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
+ // Bit[31:0] : reload value for prescale counter
+ __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
+ // current value of the pre-scaler counter
+ // The Cycle Up Counter increment when the prescale down counter reach 0
+ // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+ uint32_t RESERVED4[9];
+ __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
+ // [31:7] : Reserved
+ // [6] : CLCD_BL_CTRL
+ // [5] : CLCD_RD
+ // [4] : CLCD_RS
+ // [3] : CLCD_RESET
+ // [2] : RESERVED
+ // [1] : SPI_nSS
+ // [0] : CLCD_CS
+} MPS2_FPGAIO_TypeDef;
+
+// MISC register bit definitions
+
+#define CLCD_CS_Pos 0
+#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
+#define SPI_nSS_Pos 1
+#define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
+#define CLCD_RESET_Pos 3
+#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
+#define CLCD_RS_Pos 4
+#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
+#define CLCD_RD_Pos 5
+#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
+#define CLCD_BL_Pos 6
+#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
+
+/******************************************************************************/
+/* SCC Register declaration */
+/******************************************************************************/
+
+typedef struct //
+{
+ __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
+ // [31:1] : Reserved
+ // [0] 1 : REMAP BlockRam to ZBT
+ __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
+ // [31:8] : Reserved
+ // [7:0] : MCC LEDs
+ uint32_t RESERVED0[1];
+ __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
+ // [31:8] : Reserved
+ // [7:0] : These bits indicate state of the MCC switches
+ __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
+ // [31:4] : Reserved
+ // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
+ uint32_t RESERVED1[35];
+ __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
+ // [31:0] : Data
+ __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
+ // [31:0] : Data
+ __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
+ // [31] : Start (generates interrupt on write to this bit)
+ // [30] : R/W access
+ // [29:26] : Reserved
+ // [25:20] : Function value
+ // [19:12] : Reserved
+ // [11:0] : Device (value of 0/1/2 for supported clocks)
+ __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
+ // [31:2] : Reserved
+ // [1] : Error
+ // [0] : Complete
+ __IO uint32_t RESERVED2[20];
+ __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
+ // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
+ // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
+ // [15:1] : Reserved
+ // [0] : This bit indicates if all enabled DLLs are locked
+ uint32_t RESERVED3[957];
+ __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
+ // [31:24] : FPGA build number
+ // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
+ // [19:11] : Reserved
+ // [10] : if “1” SCC_SW register has been implemented
+ // [9] : if “1” SCC_LED register has been implemented
+ // [8] : if “1” DLL lock register has been implemented
+ // [7:0] : number of SCC configuration register
+ __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
+ // [31:24] : Implementer ID: 0x41 = ARM
+ // [23:20] : Application note IP variant number
+ // [19:16] : IP Architecture: 0x4 =AHB
+ // [15:4] : Primary part number: 386 = AN386
+ // [3:0] : Application note IP revision number
+} MPS2_SCC_TypeDef;
+
+
+/******************************************************************************/
+/* SSP Peripheral declaration */
+/******************************************************************************/
+
+typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
+{
+ __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
+ // [31:16] : Reserved
+ // [15:8] : Serial clock rate
+ // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
+ // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
+ // [5:4] : Frame format
+ // [3:0] : Data Size Select
+ __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
+ // [31:4] : Reserved
+ // [3] : Slave-mode output disable
+ // [2] : Master or slave mode select
+ // [1] : Synchronous serial port enable
+ // [0] : Loop back mode
+ __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
+ // [31:16] : Reserved
+ // [15:0] : Transmit/Receive FIFO
+ __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
+ // [31:5] : Reserved
+ // [4] : PrimeCell SSP busy flag
+ // [3] : Receive FIFO full
+ // [2] : Receive FIFO not empty
+ // [1] : Transmit FIFO not full
+ // [0] : Transmit FIFO empty
+ __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
+ // [31:8] : Reserved
+ // [8:0] : Clock prescale divisor
+ __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
+ // [31:4] : Reserved
+ // [3] : Transmit FIFO interrupt mask
+ // [2] : Receive FIFO interrupt mask
+ // [1] : Receive timeout interrupt mask
+ // [0] : Receive overrun interrupt mask
+ __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
+ // [31:4] : Reserved
+ // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
+ // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
+ // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
+ // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
+ __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
+ // [31:4] : Reserved
+ // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
+ // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
+ // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
+ // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
+ __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
+ // [31:2] : Reserved
+ // [1] : Clears the SSPRTINTR interrupt
+ // [0] : Clears the SSPRORINTR interrupt
+ __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
+ // [31:2] : Reserved
+ // [1] : Transmit DMA Enable
+ // [0] : Receive DMA Enable
+} MPS2_SSP_TypeDef;
+
+
+// SSP_CR0 Control register 0
+#define SSP_CR0_DSS_Pos 0 // Data Size Select
+#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
+#define SSP_CR0_FRF_Pos 4 // Frame Format Select
+#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
+#define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
+#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
+#define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
+#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
+#define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
+#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
+
+#define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
+#define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
+#define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
+#define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
+
+// SSP_CR1 Control register 1
+#define SSP_CR1_LBM_Pos 0 // Loop Back Mode
+#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
+#define SSP_CR1_SSE_Pos 1 // Serial port enable
+#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
+#define SSP_CR1_MS_Pos 2 // Master or Slave mode
+#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
+#define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
+#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
+
+// SSP_SR Status register
+#define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
+#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
+#define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
+#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
+#define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
+#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
+#define SSP_SR_RFF_Pos 3 // Receive FIFO full
+#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
+#define SSP_SR_BSY_Pos 4 // Busy
+#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
+
+// SSP_CPSR Clock prescale register
+#define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
+#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
+
+#define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
+
+// SSPIMSC Interrupt mask set and clear register
+#define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
+#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
+#define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
+#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
+#define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
+#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
+#define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
+#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
+
+// SSPRIS Raw interrupt status register
+#define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
+#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
+#define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
+#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
+#define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
+#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
+#define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
+#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
+
+// SSPMIS Masked interrupt status register
+#define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
+#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
+#define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
+#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
+#define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
+#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
+#define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
+#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
+
+// SSPICR Interrupt clear register
+#define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
+#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
+#define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
+#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
+
+// SSPDMACR DMA control register
+#define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
+#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
+#define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
+#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
+
+/******************************************************************************/
+/* Audio and Touch Screen (I2C) Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ union {
+ __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
+ __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
+ };
+ __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
+} MPS2_I2C_TypeDef;
+
+#define SDA 1 << 1
+#define SCL 1 << 0
+
+
+/******************************************************************************/
+/* Audio I2S Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ /*!< Offset: 0x000 CONTROL Register (R/W) */
+ __IO uint32_t CONTROL; // <h> CONTROL </h>
+ // <o.0> TX Enable
+ // <0=> TX disabled
+ // <1=> TX enabled
+ // <o.1> TX IRQ Enable
+ // <0=> TX IRQ disabled
+ // <1=> TX IRQ enabled
+ // <o.2> RX Enable
+ // <0=> RX disabled
+ // <1=> RX enabled
+ // <o.3> RX IRQ Enable
+ // <0=> RX IRQ disabled
+ // <1=> RX IRQ enabled
+ // <o.10..8> TX Buffer Water Level
+ // <0=> / IRQ triggers when any space available
+ // <1=> / IRQ triggers when more than 1 space available
+ // <2=> / IRQ triggers when more than 2 space available
+ // <3=> / IRQ triggers when more than 3 space available
+ // <4=> Undefined!
+ // <5=> Undefined!
+ // <6=> Undefined!
+ // <7=> Undefined!
+ // <o.14..12> RX Buffer Water Level
+ // <0=> Undefined!
+ // <1=> / IRQ triggers when less than 1 space available
+ // <2=> / IRQ triggers when less than 2 space available
+ // <3=> / IRQ triggers when less than 3 space available
+ // <4=> / IRQ triggers when less than 4 space available
+ // <5=> Undefined!
+ // <6=> Undefined!
+ // <7=> Undefined!
+ // <o.16> FIFO reset
+ // <0=> Normal operation
+ // <1=> FIFO reset
+ // <o.17> Audio Codec reset
+ // <0=> Normal operation
+ // <1=> Assert audio Codec reset
+ /*!< Offset: 0x004 STATUS Register (R/ ) */
+ __I uint32_t STATUS; // <h> STATUS </h>
+ // <o.0> TX Buffer alert
+ // <0=> TX buffer don't need service yet
+ // <1=> TX buffer need service
+ // <o.1> RX Buffer alert
+ // <0=> RX buffer don't need service yet
+ // <1=> RX buffer need service
+ // <o.2> TX Buffer Empty
+ // <0=> TX buffer have data
+ // <1=> TX buffer empty
+ // <o.3> TX Buffer Full
+ // <0=> TX buffer not full
+ // <1=> TX buffer full
+ // <o.4> RX Buffer Empty
+ // <0=> RX buffer have data
+ // <1=> RX buffer empty
+ // <o.5> RX Buffer Full
+ // <0=> RX buffer not full
+ // <1=> RX buffer full
+ union {
+ /*!< Offset: 0x008 Error Status Register (R/ ) */
+ __I uint32_t ERROR; // <h> ERROR </h>
+ // <o.0> TX error
+ // <0=> Okay
+ // <1=> TX overrun/underrun
+ // <o.1> RX error
+ // <0=> Okay
+ // <1=> RX overrun/underrun
+ /*!< Offset: 0x008 Error Clear Register ( /W) */
+ __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
+ // <o.0> TX error
+ // <0=> Okay
+ // <1=> Clear TX error
+ // <o.1> RX error
+ // <0=> Okay
+ // <1=> Clear RX error
+ };
+ /*!< Offset: 0x00C Divide ratio Register (R/W) */
+ __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
+ // <o.9..0> TX error (default 0x80)
+ /*!< Offset: 0x010 Transmit Buffer ( /W) */
+ __O uint32_t TXBUF; // <h> Transmit buffer </h>
+ // <o.15..0> Right channel
+ // <o.31..16> Left channel
+ /*!< Offset: 0x014 Receive Buffer (R/ ) */
+ __I uint32_t RXBUF; // <h> Receive buffer </h>
+ // <o.15..0> Right channel
+ // <o.31..16> Left channel
+ uint32_t RESERVED1[186];
+ __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
+ // <o.0> ITEN
+ // <0=> Normal operation
+ // <1=> Integration Test mode enable
+ __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
+ // <o.0> SDIN
+ __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
+ // <o.0> SDOUT
+ // <o.1> SCLK
+ // <o.2> LRCK
+ // <o.3> IRQOUT
+} MPS2_I2S_TypeDef;
+
+#define I2S_CONTROL_TXEN_Pos 0
+#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
+
+#define I2S_CONTROL_TXIRQEN_Pos 1
+#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
+
+#define I2S_CONTROL_RXEN_Pos 2
+#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
+
+#define I2S_CONTROL_RXIRQEN_Pos 3
+#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
+
+#define I2S_CONTROL_TXWLVL_Pos 8
+#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
+
+#define I2S_CONTROL_RXWLVL_Pos 12
+#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
+/* FIFO reset*/
+#define I2S_CONTROL_FIFORST_Pos 16
+#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
+/* Codec reset*/
+#define I2S_CONTROL_CODECRST_Pos 17
+#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
+
+#define I2S_STATUS_TXIRQ_Pos 0
+#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
+
+#define I2S_STATUS_RXIRQ_Pos 1
+#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
+
+#define I2S_STATUS_TXEmpty_Pos 2
+#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
+
+#define I2S_STATUS_TXFull_Pos 3
+#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
+
+#define I2S_STATUS_RXEmpty_Pos 4
+#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
+
+#define I2S_STATUS_RXFull_Pos 5
+#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
+
+#define I2S_ERROR_TXERR_Pos 0
+#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
+
+#define I2S_ERROR_RXERR_Pos 1
+#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
+
+/******************************************************************************/
+/* SMSC9220 Register Definitions */
+/******************************************************************************/
+
+typedef struct // SMSC LAN9220
+{
+__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
+ uint32_t RESERVED1[0x7];
+__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
+ uint32_t RESERVED2[0x7];
+
+__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
+__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
+__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
+__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
+
+__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
+__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
+__IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
+__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
+ uint32_t RESERVED3; // Reserved for future use (offset 0x60)
+__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
+__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
+__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
+__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
+__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
+__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
+__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
+__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
+__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
+__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
+__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
+__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
+ uint32_t RESERVED4; // Reserved for future use (offset 0x94)
+__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
+__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
+__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
+__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
+__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
+__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
+__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
+__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
+
+} SMSC9220_TypeDef;
+
+// SMSC9220 MAC Registers Indices
+#define SMSC9220_MAC_CR 0x1
+#define SMSC9220_MAC_ADDRH 0x2
+#define SMSC9220_MAC_ADDRL 0x3
+#define SMSC9220_MAC_HASHH 0x4
+#define SMSC9220_MAC_HASHL 0x5
+#define SMSC9220_MAC_MII_ACC 0x6
+#define SMSC9220_MAC_MII_DATA 0x7
+#define SMSC9220_MAC_FLOW 0x8
+#define SMSC9220_MAC_VLAN1 0x9
+#define SMSC9220_MAC_VLAN2 0xA
+#define SMSC9220_MAC_WUFF 0xB
+#define SMSC9220_MAC_WUCSR 0xC
+
+// SMSC9220 PHY Registers Indices
+#define SMSC9220_PHY_BCONTROL 0x0
+#define SMSC9220_PHY_BSTATUS 0x1
+#define SMSC9220_PHY_ID1 0x2
+#define SMSC9220_PHY_ID2 0x3
+#define SMSC9220_PHY_ANEG_ADV 0x4
+#define SMSC9220_PHY_ANEG_LPA 0x5
+#define SMSC9220_PHY_ANEG_EXP 0x6
+#define SMSC9220_PHY_MCONTROL 0x17
+#define SMSC9220_PHY_MSTATUS 0x18
+#define SMSC9220_PHY_CSINDICATE 0x27
+#define SMSC9220_PHY_INTSRC 0x29
+#define SMSC9220_PHY_INTMASK 0x30
+#define SMSC9220_PHY_CS 0x31
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+
+#define MPS2_SSP1_BASE (0x40020000ul) /* User SSP Base Address */
+#define MPS2_SSP0_BASE (0x40021000ul) /* CLCD SSP Base Address */
+#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
+#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
+#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
+#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
+#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
+
+#ifdef CORTEX_M7
+#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
+#else
+#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
+#endif
+
+#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
+#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+
+#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
+#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
+#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
+#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
+#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
+#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
+#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
+#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
+
+/******************************************************************************/
+/* General Function Definitions */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/* General MACRO Definitions */
+/******************************************************************************/
+
+
+
+#endif /* __SMM_MPS2_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/MPS2.sct Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,47 @@
+;* MPS2 CMSIS Library
+;*
+;* Copyright (c) 2006-2015 ARM Limited
+;* All rights reserved.
+;*
+;* Redistribution and use in source and binary forms, with or without
+;* modification, are permitted provided that the following conditions are met:
+;*
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;*
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;*
+;* 3. Neither the name of the copyright holder nor the names of its contributors
+;* may be used to endorse or promote products derived from this software without
+;* specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
+;*
+; *************************************************************
+; *** Scatter-Loading Description File ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00400000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/startup_MPS2.s Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,271 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Core Device Startup File for +; * CMSDK_CM0 Device +; * @version V3.02 +; * @date 15. November 2013 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2013 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler + DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler + DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler + DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler + DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler + DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler + DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler + DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler + DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + EXPORT PORT0_8_Handler [WEAK] + EXPORT PORT0_9_Handler [WEAK] + EXPORT PORT0_10_Handler [WEAK] + EXPORT PORT0_11_Handler [WEAK] + EXPORT PORT0_12_Handler [WEAK] + EXPORT PORT0_13_Handler [WEAK] + EXPORT PORT0_14_Handler [WEAK] + EXPORT PORT0_15_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler +PORT0_8_Handler +PORT0_9_Handler +PORT0_10_Handler +PORT0_11_Handler +PORT0_12_Handler +PORT0_13_Handler +PORT0_14_Handler +PORT0_15_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,42 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in MPS2 specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_CM0plus.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,54 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* CMSIS-style functionality to support dynamic vectors
+*******************************************************************************/
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ // int i;
+ // Space for dynamic vectors, initialised to allocate in R/W
+ static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
+
+ // Set the vector
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ // We can always read vectors at 0x0, as the addresses are remapped
+ uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
+
+ // Return the vector
+ return vectors[IRQn + 16];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,54 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* CMSIS-style functionality to support dynamic vectors
+*******************************************************************************/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/peripherallink.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,53 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* Name: Device.h +* Purpose: Include the correct device header file +*******************************************************************************/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_CM0 + #include "CMSDK_CM0.h" /* device specific header file */ +#elif defined CMSDK_CM0plus + #include "CMSDK_CM0plus.h" /* device specific header file */ +#elif defined CMSDK_CM3 + #include "CMSDK_CM3.h" /* device specific header file */ +#elif defined CMSDK_CM4 + #include "CMSDK_CM4.h" /* device specific header file */ +#elif defined CMSDK_CM7 + #include "CMSDK_CM7.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,93 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* @file system_CMSDK_CM0plus.c
+* @brief CMSIS Device System Source File for
+* CMSDK_M0 Device
+* @version V3.02
+* @date 15. November 2013
+*
+* @note
+*
+*******************************************************************************/
+
+
+
+#include "CMSDK_CM0plus.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (50000000UL) /* Oscillator frequency */
+
+#define __SYSTEM_CLOCK (__XTAL / 2)
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate (void)
+{
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,80 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+*******************************************************************************
+* @file system_CMSDK_CM0plus.h
+* @brief CMSIS Device Peripheral Access Layer Header File for
+* CMSDK_CM0plus Device
+* @version V3.02
+* @date 15. March 2013
+*
+* @note
+*
+******************************************************************************/
+
+
+#ifndef SYSTEM_CMSDK_CM0plus_H
+#define SYSTEM_CMSDK_CM0plus_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CMSDK_CM0plus_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,725 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* @file CMSDK_CM3.h
+* @brief CMSIS Core Peripheral Access Layer Header File for
+* CMSDK_CM3 Device
+* @version V3.02
+* @date 15. November 2013
+*
+* @note configured for CM7 without FPU
+*
+*******************************************************************************/
+
+
+#ifndef CMSDK_CM3_H
+#define CMSDK_CM3_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+
+/* ---------------------- CMSDK_CM3 Specific Interrupt Numbers ------------------ */
+ UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
+ UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
+ UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
+ UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
+ UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
+ UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
+ PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */
+ PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */
+ TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
+ TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
+ DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
+ SPI_IRQn = 11, /* SPI Interrupt */
+ UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
+ ETHERNET_IRQn = 13, /* Ethernet Interrupt */
+ I2S_IRQn = 14, /* I2S Interrupt */
+ TSC_IRQn = 15, /* Touch Screen Interrupt */
+// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
+ PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
+ PORT0_1_IRQn = 17, /* There are 16 pins in total */
+ PORT0_2_IRQn = 18,
+ PORT0_3_IRQn = 19,
+ PORT0_4_IRQn = 20,
+ PORT0_5_IRQn = 21,
+ PORT0_6_IRQn = 22,
+ PORT0_7_IRQn = 23,
+ PORT0_8_IRQn = 24,
+ PORT0_9_IRQn = 25,
+ PORT0_10_IRQn = 26,
+ PORT0_11_IRQn = 27,
+ PORT0_12_IRQn = 28,
+ PORT0_13_IRQn = 29,
+ PORT0_14_IRQn = 30,
+ PORT0_15_IRQn = 31,
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
+#define __CM3_REV 0x0201 /* Core revision r2p1 */
+#define __MPU_PRESENT 1 /* MPU present or not */
+#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+
+#include <core_cm3.h> /* Processor and core peripherals */
+#include "system_CMSDK_CM3.h" /* System Header */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined ( __CC_ARM )
+ #pragma push
+#pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
+ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
+ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
+ };
+ __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
+
+} CMSDK_UART_TypeDef;
+
+/* CMSDK_UART DATA Register Definitions */
+
+#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
+#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
+
+#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
+#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
+
+#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
+#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
+
+#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
+#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
+
+#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
+#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
+
+#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
+#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
+
+#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
+#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
+#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
+#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
+#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
+#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
+
+#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
+#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
+
+#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
+#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
+#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
+#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
+#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
+
+#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
+#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
+
+
+/*----------------------------- Timer (TIMER) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
+ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
+ };
+
+} CMSDK_TIMER_TypeDef;
+
+/* CMSDK_TIMER CTRL Register Definitions */
+
+#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
+#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
+
+#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
+#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
+
+#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
+#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
+
+#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
+#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
+
+#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
+#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
+
+#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
+#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
+
+#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
+#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
+
+#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
+#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
+
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
+ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
+ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
+ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
+ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
+ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
+ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
+ uint32_t RESERVED0;
+ __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
+ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
+ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
+ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
+ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
+ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
+ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
+ uint32_t RESERVED1[945];
+ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
+ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
+} CMSDK_DUALTIMER_BOTH_TypeDef;
+
+#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
+#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
+#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
+
+#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
+#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
+#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
+
+
+typedef struct
+{
+ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
+ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
+ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
+ __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
+ __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
+ __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
+ __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
+} CMSDK_DUALTIMER_SINGLE_TypeDef;
+
+#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
+#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
+#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
+
+
+/*-------------------- General Purpose Input Output (GPIO) -------------------*/
+typedef struct
+{
+ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
+ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
+ __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
+ __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
+ __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
+ __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
+ __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
+ __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
+ __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
+ __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
+ __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
+ };
+ uint32_t RESERVED1[241];
+ __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
+ __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
+} CMSDK_GPIO_TypeDef;
+
+#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
+#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
+
+#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
+#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
+
+#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
+#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
+
+#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
+#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
+
+#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
+#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
+
+#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
+#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
+
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+typedef struct
+{
+ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
+ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
+ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
+ __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
+ __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
+} CMSDK_SYSCON_TypeDef;
+
+#define CMSDK_SYSCON_REMAP_Pos 0
+#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
+
+#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
+#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
+
+#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
+#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
+#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
+#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
+#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
+#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
+
+#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
+#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
+
+#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
+#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
+
+#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
+#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
+
+
+/*------------- PL230 uDMA (PL230) --------------------------------------*/
+typedef struct
+{
+ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
+ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
+ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
+ __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
+ __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
+ __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
+ __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
+ __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
+ __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
+ __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
+ __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
+ __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
+ __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
+ __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
+ __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
+ __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
+ uint32_t RESERVED0[3];
+ __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
+
+} CMSDK_PL230_TypeDef;
+
+#define PL230_DMA_CHNL_BITS 0
+
+#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
+#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
+#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
+
+#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
+#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
+
+#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
+#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
+
+#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
+#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
+#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
+#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
+#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
+
+#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
+#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
+
+#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
+#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
+#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
+
+#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
+#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
+
+#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
+#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
+
+#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
+#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
+
+#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
+#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
+
+#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
+#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
+
+#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
+#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
+
+#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
+#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
+
+#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
+#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
+
+#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
+#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
+
+#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
+#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
+
+#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
+#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
+
+#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
+#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
+
+
+/*------------------- Watchdog ----------------------------------------------*/
+typedef struct
+{
+
+ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
+ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
+ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
+ __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
+ __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
+ __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
+ uint32_t RESERVED0[762];
+ __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
+ uint32_t RESERVED1[191];
+ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
+ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
+}CMSDK_WATCHDOG_TypeDef;
+
+#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
+#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
+
+#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
+#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
+
+#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
+#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
+
+#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
+#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
+
+#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
+#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
+
+#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
+#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
+
+#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
+#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
+
+#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
+#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
+
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined ( __CC_ARM )
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+/* Peripheral and SRAM base address */
+#define CMSDK_FLASH_BASE (0x00000000UL)
+#define CMSDK_SRAM_BASE (0x20000000UL)
+#define CMSDK_PERIPH_BASE (0x40000000UL)
+
+#define CMSDK_RAM_BASE (0x20000000UL)
+#define CMSDK_APB_BASE (0x40000000UL)
+#define CMSDK_AHB_BASE (0x40010000UL)
+
+/* APB peripherals */
+#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
+#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
+#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
+#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
+#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
+#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
+#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
+#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
+#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
+#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
+
+/* AHB peripherals */
+#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
+#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
+#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
+#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
+#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
+#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
+#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
+#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
+#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
+#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
+#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
+#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
+#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
+#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
+#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
+#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
+#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
+#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
+#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CMSDK_CM3_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,595 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* File: smm_mps2.h
+* Release: Version 1.0
+*******************************************************************************/
+
+#ifndef __SMM_MPS2_H
+#define __SMM_MPS2_H
+
+#include "peripherallink.h" /* device specific header file */
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/******************************************************************************/
+/* FPGA System Register declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
+ // [31:2] : Reserved
+ // [1:0] : LEDs
+ uint32_t RESERVED1[1];
+ __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
+ // [31:2] : Reserved
+ // [1:0] : Buttons
+ uint32_t RESERVED2[1];
+ __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
+ __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
+ __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
+ // Increments when 32-bit prescale counter reach zero
+ uint32_t RESERVED3[1];
+ __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
+ // Bit[31:0] : reload value for prescale counter
+ __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
+ // current value of the pre-scaler counter
+ // The Cycle Up Counter increment when the prescale down counter reach 0
+ // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+ uint32_t RESERVED4[9];
+ __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
+ // [31:7] : Reserved
+ // [6] : CLCD_BL_CTRL
+ // [5] : CLCD_RD
+ // [4] : CLCD_RS
+ // [3] : CLCD_RESET
+ // [2] : RESERVED
+ // [1] : SPI_nSS
+ // [0] : CLCD_CS
+} MPS2_FPGAIO_TypeDef;
+
+// MISC register bit definitions
+
+#define CLCD_CS_Pos 0
+#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
+#define SPI_nSS_Pos 1
+#define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
+#define CLCD_RESET_Pos 3
+#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
+#define CLCD_RS_Pos 4
+#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
+#define CLCD_RD_Pos 5
+#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
+#define CLCD_BL_Pos 6
+#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
+
+/******************************************************************************/
+/* SCC Register declaration */
+/******************************************************************************/
+
+typedef struct //
+{
+ __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
+ // [31:1] : Reserved
+ // [0] 1 : REMAP BlockRam to ZBT
+ __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
+ // [31:8] : Reserved
+ // [7:0] : MCC LEDs
+ uint32_t RESERVED0[1];
+ __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
+ // [31:8] : Reserved
+ // [7:0] : These bits indicate state of the MCC switches
+ __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
+ // [31:4] : Reserved
+ // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
+ uint32_t RESERVED1[35];
+ __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
+ // [31:0] : Data
+ __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
+ // [31:0] : Data
+ __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
+ // [31] : Start (generates interrupt on write to this bit)
+ // [30] : R/W access
+ // [29:26] : Reserved
+ // [25:20] : Function value
+ // [19:12] : Reserved
+ // [11:0] : Device (value of 0/1/2 for supported clocks)
+ __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
+ // [31:2] : Reserved
+ // [1] : Error
+ // [0] : Complete
+ __IO uint32_t RESERVED2[20];
+ __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
+ // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
+ // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
+ // [15:1] : Reserved
+ // [0] : This bit indicates if all enabled DLLs are locked
+ uint32_t RESERVED3[957];
+ __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
+ // [31:24] : FPGA build number
+ // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
+ // [19:11] : Reserved
+ // [10] : if “1” SCC_SW register has been implemented
+ // [9] : if “1” SCC_LED register has been implemented
+ // [8] : if “1” DLL lock register has been implemented
+ // [7:0] : number of SCC configuration register
+ __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
+ // [31:24] : Implementer ID: 0x41 = ARM
+ // [23:20] : Application note IP variant number
+ // [19:16] : IP Architecture: 0x4 =AHB
+ // [15:4] : Primary part number: 386 = AN386
+ // [3:0] : Application note IP revision number
+} MPS2_SCC_TypeDef;
+
+
+/******************************************************************************/
+/* SSP Peripheral declaration */
+/******************************************************************************/
+
+typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
+{
+ __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
+ // [31:16] : Reserved
+ // [15:8] : Serial clock rate
+ // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
+ // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
+ // [5:4] : Frame format
+ // [3:0] : Data Size Select
+ __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
+ // [31:4] : Reserved
+ // [3] : Slave-mode output disable
+ // [2] : Master or slave mode select
+ // [1] : Synchronous serial port enable
+ // [0] : Loop back mode
+ __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
+ // [31:16] : Reserved
+ // [15:0] : Transmit/Receive FIFO
+ __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
+ // [31:5] : Reserved
+ // [4] : PrimeCell SSP busy flag
+ // [3] : Receive FIFO full
+ // [2] : Receive FIFO not empty
+ // [1] : Transmit FIFO not full
+ // [0] : Transmit FIFO empty
+ __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
+ // [31:8] : Reserved
+ // [8:0] : Clock prescale divisor
+ __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
+ // [31:4] : Reserved
+ // [3] : Transmit FIFO interrupt mask
+ // [2] : Receive FIFO interrupt mask
+ // [1] : Receive timeout interrupt mask
+ // [0] : Receive overrun interrupt mask
+ __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
+ // [31:4] : Reserved
+ // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
+ // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
+ // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
+ // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
+ __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
+ // [31:4] : Reserved
+ // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
+ // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
+ // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
+ // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
+ __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
+ // [31:2] : Reserved
+ // [1] : Clears the SSPRTINTR interrupt
+ // [0] : Clears the SSPRORINTR interrupt
+ __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
+ // [31:2] : Reserved
+ // [1] : Transmit DMA Enable
+ // [0] : Receive DMA Enable
+} MPS2_SSP_TypeDef;
+
+
+// SSP_CR0 Control register 0
+#define SSP_CR0_DSS_Pos 0 // Data Size Select
+#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
+#define SSP_CR0_FRF_Pos 4 // Frame Format Select
+#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
+#define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
+#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
+#define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
+#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
+#define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
+#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
+
+#define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
+#define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
+#define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
+#define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
+
+// SSP_CR1 Control register 1
+#define SSP_CR1_LBM_Pos 0 // Loop Back Mode
+#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
+#define SSP_CR1_SSE_Pos 1 // Serial port enable
+#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
+#define SSP_CR1_MS_Pos 2 // Master or Slave mode
+#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
+#define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
+#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
+
+// SSP_SR Status register
+#define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
+#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
+#define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
+#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
+#define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
+#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
+#define SSP_SR_RFF_Pos 3 // Receive FIFO full
+#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
+#define SSP_SR_BSY_Pos 4 // Busy
+#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
+
+// SSP_CPSR Clock prescale register
+#define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
+#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
+
+#define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
+
+// SSPIMSC Interrupt mask set and clear register
+#define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
+#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
+#define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
+#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
+#define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
+#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
+#define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
+#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
+
+// SSPRIS Raw interrupt status register
+#define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
+#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
+#define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
+#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
+#define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
+#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
+#define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
+#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
+
+// SSPMIS Masked interrupt status register
+#define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
+#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
+#define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
+#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
+#define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
+#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
+#define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
+#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
+
+// SSPICR Interrupt clear register
+#define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
+#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
+#define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
+#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
+
+// SSPDMACR DMA control register
+#define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
+#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
+#define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
+#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
+
+/******************************************************************************/
+/* Audio and Touch Screen (I2C) Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ union {
+ __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
+ __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
+ };
+ __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
+} MPS2_I2C_TypeDef;
+
+#define SDA 1 << 1
+#define SCL 1 << 0
+
+
+/******************************************************************************/
+/* Audio I2S Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ /*!< Offset: 0x000 CONTROL Register (R/W) */
+ __IO uint32_t CONTROL; // <h> CONTROL </h>
+ // <o.0> TX Enable
+ // <0=> TX disabled
+ // <1=> TX enabled
+ // <o.1> TX IRQ Enable
+ // <0=> TX IRQ disabled
+ // <1=> TX IRQ enabled
+ // <o.2> RX Enable
+ // <0=> RX disabled
+ // <1=> RX enabled
+ // <o.3> RX IRQ Enable
+ // <0=> RX IRQ disabled
+ // <1=> RX IRQ enabled
+ // <o.10..8> TX Buffer Water Level
+ // <0=> / IRQ triggers when any space available
+ // <1=> / IRQ triggers when more than 1 space available
+ // <2=> / IRQ triggers when more than 2 space available
+ // <3=> / IRQ triggers when more than 3 space available
+ // <4=> Undefined!
+ // <5=> Undefined!
+ // <6=> Undefined!
+ // <7=> Undefined!
+ // <o.14..12> RX Buffer Water Level
+ // <0=> Undefined!
+ // <1=> / IRQ triggers when less than 1 space available
+ // <2=> / IRQ triggers when less than 2 space available
+ // <3=> / IRQ triggers when less than 3 space available
+ // <4=> / IRQ triggers when less than 4 space available
+ // <5=> Undefined!
+ // <6=> Undefined!
+ // <7=> Undefined!
+ // <o.16> FIFO reset
+ // <0=> Normal operation
+ // <1=> FIFO reset
+ // <o.17> Audio Codec reset
+ // <0=> Normal operation
+ // <1=> Assert audio Codec reset
+ /*!< Offset: 0x004 STATUS Register (R/ ) */
+ __I uint32_t STATUS; // <h> STATUS </h>
+ // <o.0> TX Buffer alert
+ // <0=> TX buffer don't need service yet
+ // <1=> TX buffer need service
+ // <o.1> RX Buffer alert
+ // <0=> RX buffer don't need service yet
+ // <1=> RX buffer need service
+ // <o.2> TX Buffer Empty
+ // <0=> TX buffer have data
+ // <1=> TX buffer empty
+ // <o.3> TX Buffer Full
+ // <0=> TX buffer not full
+ // <1=> TX buffer full
+ // <o.4> RX Buffer Empty
+ // <0=> RX buffer have data
+ // <1=> RX buffer empty
+ // <o.5> RX Buffer Full
+ // <0=> RX buffer not full
+ // <1=> RX buffer full
+ union {
+ /*!< Offset: 0x008 Error Status Register (R/ ) */
+ __I uint32_t ERROR; // <h> ERROR </h>
+ // <o.0> TX error
+ // <0=> Okay
+ // <1=> TX overrun/underrun
+ // <o.1> RX error
+ // <0=> Okay
+ // <1=> RX overrun/underrun
+ /*!< Offset: 0x008 Error Clear Register ( /W) */
+ __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
+ // <o.0> TX error
+ // <0=> Okay
+ // <1=> Clear TX error
+ // <o.1> RX error
+ // <0=> Okay
+ // <1=> Clear RX error
+ };
+ /*!< Offset: 0x00C Divide ratio Register (R/W) */
+ __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
+ // <o.9..0> TX error (default 0x80)
+ /*!< Offset: 0x010 Transmit Buffer ( /W) */
+ __O uint32_t TXBUF; // <h> Transmit buffer </h>
+ // <o.15..0> Right channel
+ // <o.31..16> Left channel
+ /*!< Offset: 0x014 Receive Buffer (R/ ) */
+ __I uint32_t RXBUF; // <h> Receive buffer </h>
+ // <o.15..0> Right channel
+ // <o.31..16> Left channel
+ uint32_t RESERVED1[186];
+ __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
+ // <o.0> ITEN
+ // <0=> Normal operation
+ // <1=> Integration Test mode enable
+ __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
+ // <o.0> SDIN
+ __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
+ // <o.0> SDOUT
+ // <o.1> SCLK
+ // <o.2> LRCK
+ // <o.3> IRQOUT
+} MPS2_I2S_TypeDef;
+
+#define I2S_CONTROL_TXEN_Pos 0
+#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
+
+#define I2S_CONTROL_TXIRQEN_Pos 1
+#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
+
+#define I2S_CONTROL_RXEN_Pos 2
+#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
+
+#define I2S_CONTROL_RXIRQEN_Pos 3
+#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
+
+#define I2S_CONTROL_TXWLVL_Pos 8
+#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
+
+#define I2S_CONTROL_RXWLVL_Pos 12
+#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
+/* FIFO reset*/
+#define I2S_CONTROL_FIFORST_Pos 16
+#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
+/* Codec reset*/
+#define I2S_CONTROL_CODECRST_Pos 17
+#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
+
+#define I2S_STATUS_TXIRQ_Pos 0
+#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
+
+#define I2S_STATUS_RXIRQ_Pos 1
+#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
+
+#define I2S_STATUS_TXEmpty_Pos 2
+#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
+
+#define I2S_STATUS_TXFull_Pos 3
+#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
+
+#define I2S_STATUS_RXEmpty_Pos 4
+#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
+
+#define I2S_STATUS_RXFull_Pos 5
+#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
+
+#define I2S_ERROR_TXERR_Pos 0
+#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
+
+#define I2S_ERROR_RXERR_Pos 1
+#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
+
+/******************************************************************************/
+/* SMSC9220 Register Definitions */
+/******************************************************************************/
+
+typedef struct // SMSC LAN9220
+{
+__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
+ uint32_t RESERVED1[0x7];
+__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
+ uint32_t RESERVED2[0x7];
+
+__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
+__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
+__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
+__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
+
+__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
+__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
+__IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
+__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
+ uint32_t RESERVED3; // Reserved for future use (offset 0x60)
+__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
+__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
+__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
+__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
+__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
+__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
+__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
+__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
+__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
+__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
+__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
+__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
+ uint32_t RESERVED4; // Reserved for future use (offset 0x94)
+__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
+__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
+__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
+__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
+__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
+__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
+__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
+__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
+
+} SMSC9220_TypeDef;
+
+// SMSC9220 MAC Registers Indices
+#define SMSC9220_MAC_CR 0x1
+#define SMSC9220_MAC_ADDRH 0x2
+#define SMSC9220_MAC_ADDRL 0x3
+#define SMSC9220_MAC_HASHH 0x4
+#define SMSC9220_MAC_HASHL 0x5
+#define SMSC9220_MAC_MII_ACC 0x6
+#define SMSC9220_MAC_MII_DATA 0x7
+#define SMSC9220_MAC_FLOW 0x8
+#define SMSC9220_MAC_VLAN1 0x9
+#define SMSC9220_MAC_VLAN2 0xA
+#define SMSC9220_MAC_WUFF 0xB
+#define SMSC9220_MAC_WUCSR 0xC
+
+// SMSC9220 PHY Registers Indices
+#define SMSC9220_PHY_BCONTROL 0x0
+#define SMSC9220_PHY_BSTATUS 0x1
+#define SMSC9220_PHY_ID1 0x2
+#define SMSC9220_PHY_ID2 0x3
+#define SMSC9220_PHY_ANEG_ADV 0x4
+#define SMSC9220_PHY_ANEG_LPA 0x5
+#define SMSC9220_PHY_ANEG_EXP 0x6
+#define SMSC9220_PHY_MCONTROL 0x17
+#define SMSC9220_PHY_MSTATUS 0x18
+#define SMSC9220_PHY_CSINDICATE 0x27
+#define SMSC9220_PHY_INTSRC 0x29
+#define SMSC9220_PHY_INTMASK 0x30
+#define SMSC9220_PHY_CS 0x31
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+
+#define MPS2_SSP1_BASE (0x40020000ul) /* User SSP Base Address */
+#define MPS2_SSP0_BASE (0x40021000ul) /* CLCD SSP Base Address */
+#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
+#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
+#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
+#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
+#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
+
+#ifdef CORTEX_M7
+#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
+#else
+#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
+#endif
+
+#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
+#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+
+#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
+#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
+#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
+#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
+#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
+#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
+#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
+#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
+
+/******************************************************************************/
+/* General Function Definitions */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/* General MACRO Definitions */
+/******************************************************************************/
+
+
+
+#endif /* __SMM_MPS2_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,47 @@
+;* MPS2 CMSIS Library
+;*
+;* Copyright (c) 2006-2015 ARM Limited
+;* All rights reserved.
+;*
+;* Redistribution and use in source and binary forms, with or without
+;* modification, are permitted provided that the following conditions are met:
+;*
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;*
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;*
+;* 3. Neither the name of the copyright holder nor the names of its contributors
+;* may be used to endorse or promote products derived from this software without
+;* specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
+;*
+; *************************************************************
+; *** Scatter-Loading Description File ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00400000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/startup_MPS2.s Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,291 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM3.s +; * @brief CMSIS Core Device Startup File for +; * CMSDK_CM3 Device +; * @version V3.02 +; * @date 15. November 2013 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2013 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler + DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler + DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler + DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler + DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler + DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler + DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler + DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler + DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + EXPORT PORT0_8_Handler [WEAK] + EXPORT PORT0_9_Handler [WEAK] + EXPORT PORT0_10_Handler [WEAK] + EXPORT PORT0_11_Handler [WEAK] + EXPORT PORT0_12_Handler [WEAK] + EXPORT PORT0_13_Handler [WEAK] + EXPORT PORT0_14_Handler [WEAK] + EXPORT PORT0_15_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler +PORT0_8_Handler +PORT0_9_Handler +PORT0_10_Handler +PORT0_11_Handler +PORT0_12_Handler +PORT0_13_Handler +PORT0_14_Handler +PORT0_15_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,42 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in MPS2 specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_CM3.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,58 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* CMSIS-style functionality to support dynamic vectors
+*******************************************************************************/
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,54 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* CMSIS-style functionality to support dynamic vectors
+*******************************************************************************/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/peripherallink.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,53 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* Name: Device.h +* Purpose: Include the correct device header file +*******************************************************************************/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_CM0 + #include "CMSDK_CM0.h" /* device specific header file */ +#elif defined CMSDK_CM0plus + #include "CMSDK_CM0plus.h" /* device specific header file */ +#elif defined CMSDK_CM3 + #include "CMSDK_CM3.h" /* device specific header file */ +#elif defined CMSDK_CM4 + #include "CMSDK_CM4.h" /* device specific header file */ +#elif defined CMSDK_CM7 + #include "CMSDK_CM7.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,97 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* @file system_CMSDK_CM3.c
+* @brief CMSIS Device System Source File for
+* CMSDK_M3 Device
+* @version V3.02
+* @date 15. November 2013
+*
+* @note
+*
+*******************************************************************************/
+
+
+
+#include "CMSDK_CM3.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (50000000UL) /* Oscillator frequency */
+
+#define __SYSTEM_CLOCK (__XTAL / 2)
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate (void)
+{
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,80 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+*******************************************************************************
+* @file system_CMSDK_CM3.h
+* @brief CMSIS Device Peripheral Access Layer Header File for
+* CMSDK_CM3 Device
+* @version V3.02
+* @date 15. March 2013
+*
+* @note
+*
+******************************************************************************/
+
+
+#ifndef SYSTEM_CMSDK_CM3_H
+#define SYSTEM_CMSDK_CM3_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CMSDK_CM3_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,1325 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* @file CMSDK_CM4.h
+* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
+* Device CMSDK_CM4
+* @version V3.01
+* @date 06. March 2012
+*
+* @note configured for CM7 without FPU
+*
+*******************************************************************************/
+
+
+#ifndef CMSDK_CM4_H
+#define CMSDK_CM4_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup CMSDK_CM4_Definitions CMSDK_CM4 Definitions
+ This file defines all structures and symbols for CMSDK_CM4:
+ - registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - Peripheral definitions
+ @{
+*/
+
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup CMSDK_CM4_CMSIS Device CMSIS Definitions
+ Configuration of the Cortex-M4 Processor and Core Peripherals
+ @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** CMSDK Specific Interrupt Numbers *******************************************************/
+ UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
+ UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
+ UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
+ UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
+ UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
+ UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
+// UARTRX3_IRQn = 6, /*!< UART 2 RX Interrupt //only used in extended version */
+// UARTTX3_IRQn = 7, /*!< UART 2 TX Interrupt //only used in extended version */
+ PORT0_ALL_IRQn = 6, /*!< Port 1 combined Interrupt */
+ PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
+ TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
+ TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
+ DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
+ SPI_IRQn = 11, /*!< SPI Interrupt */
+ UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
+ ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
+ I2S_IRQn = 14, /*!< I2S Interrupt */
+ TSC_IRQn = 15, /* Touch Screen Interrupt */
+// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
+ PORT0_0_IRQn = 16, /*!< All P0 I/O pins can be used as interrupt source. */
+ PORT0_1_IRQn = 17, /*!< There are 16 pins in total */
+ PORT0_2_IRQn = 18,
+ PORT0_3_IRQn = 19,
+ PORT0_4_IRQn = 20,
+ PORT0_5_IRQn = 21,
+ PORT0_6_IRQn = 22,
+ PORT0_7_IRQn = 23,
+ PORT0_8_IRQn = 24,
+ PORT0_9_IRQn = 25,
+ PORT0_10_IRQn = 26,
+ PORT0_11_IRQn = 27,
+ PORT0_12_IRQn = 28,
+ PORT0_13_IRQn = 29,
+ PORT0_14_IRQn = 30,
+ PORT0_15_IRQn = 31,
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M4 Processor and Core Peripherals */
+#define __CM4_REV 0x0001 /*!< Core Revision r0p1 */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+
+/*@}*/ /* end of group CMSDK_CM4_CMSIS */
+
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_CMSDK_CM4.h" /* CMSDK_CM4 System include file */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+/** @addtogroup CMSDK_CM4_Peripherals CMSDK_CM4 Peripherals
+ CMSDK_CM4 Device Specific Peripheral registers structures
+ @{
+*/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+/** @addtogroup CMSDK_UART CMSDK Universal Asynchronous Receiver/Transmitter
+ memory mapped structure for CMSDK_UART
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
+ __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
+ __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
+ union {
+ __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
+ __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
+ };
+ __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
+
+} CMSDK_UART_TypeDef;
+
+/* CMSDK_UART DATA Register Definitions */
+
+#define CMSDK_UART_DATA_Pos 0 /*!< CMSDK_UART_DATA_Pos: DATA Position */
+#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /*!< CMSDK_UART DATA: DATA Mask */
+
+#define CMSDK_UART_STATE_RXOR_Pos 3 /*!< CMSDK_UART STATE: RXOR Position */
+#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /*!< CMSDK_UART STATE: RXOR Mask */
+
+#define CMSDK_UART_STATE_TXOR_Pos 2 /*!< CMSDK_UART STATE: TXOR Position */
+#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /*!< CMSDK_UART STATE: TXOR Mask */
+
+#define CMSDK_UART_STATE_RXBF_Pos 1 /*!< CMSDK_UART STATE: RXBF Position */
+#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /*!< CMSDK_UART STATE: RXBF Mask */
+
+#define CMSDK_UART_STATE_TXBF_Pos 0 /*!< CMSDK_UART STATE: TXBF Position */
+#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /*!< CMSDK_UART STATE: TXBF Mask */
+
+#define CMSDK_UART_CTRL_HSTM_Pos 6 /*!< CMSDK_UART CTRL: HSTM Position */
+#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /*!< CMSDK_UART CTRL: HSTM Mask */
+
+#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /*!< CMSDK_UART CTRL: RXORIRQEN Position */
+#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /*!< CMSDK_UART CTRL: RXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /*!< CMSDK_UART CTRL: TXORIRQEN Position */
+#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /*!< CMSDK_UART CTRL: TXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /*!< CMSDK_UART CTRL: RXIRQEN Position */
+#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /*!< CMSDK_UART CTRL: RXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /*!< CMSDK_UART CTRL: TXIRQEN Position */
+#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /*!< CMSDK_UART CTRL: TXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXEN_Pos 1 /*!< CMSDK_UART CTRL: RXEN Position */
+#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /*!< CMSDK_UART CTRL: RXEN Mask */
+
+#define CMSDK_UART_CTRL_TXEN_Pos 0 /*!< CMSDK_UART CTRL: TXEN Position */
+#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /*!< CMSDK_UART CTRL: TXEN Mask */
+
+#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /*!< CMSDK_UART CTRL: RXORIRQ Position */
+#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /*!< CMSDK_UART CTRL: RXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /*!< CMSDK_UART CTRL: TXORIRQ Position */
+#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /*!< CMSDK_UART CTRL: TXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /*!< CMSDK_UART CTRL: RXIRQ Position */
+#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /*!< CMSDK_UART CTRL: RXIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /*!< CMSDK_UART CTRL: TXIRQ Position */
+#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /*!< CMSDK_UART CTRL: TXIRQ Mask */
+
+#define CMSDK_UART_BAUDDIV_Pos 0 /*!< CMSDK_UART BAUDDIV: BAUDDIV Position */
+#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /*!< CMSDK_UART BAUDDIV: BAUDDIV Mask */
+
+/*@}*/ /* end of group CMSDK_UART */
+
+
+/*----------------------------- Timer (TIMER) -------------------------------*/
+/** @addtogroup CMSDK_TIMER CMSDK Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */
+ __IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */
+ __IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */
+ union {
+ __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
+ __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
+ };
+
+} CMSDK_TIMER_TypeDef;
+
+/* CMSDK_TIMER CTRL Register Definitions */
+
+#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /*!< CMSDK_TIMER CTRL: IRQEN Position */
+#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /*!< CMSDK_TIMER CTRL: IRQEN Mask */
+
+#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /*!< CMSDK_TIMER CTRL: SELEXTCLK Position */
+#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /*!< CMSDK_TIMER CTRL: SELEXTCLK Mask */
+
+#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /*!< CMSDK_TIMER CTRL: SELEXTEN Position */
+#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /*!< CMSDK_TIMER CTRL: SELEXTEN Mask */
+
+#define CMSDK_TIMER_CTRL_EN_Pos 0 /*!< CMSDK_TIMER CTRL: EN Position */
+#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /*!< CMSDK_TIMER CTRL: EN Mask */
+
+#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /*!< CMSDK_TIMER VALUE: CURRENT Position */
+#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /*!< CMSDK_TIMER VALUE: CURRENT Mask */
+
+#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /*!< CMSDK_TIMER RELOAD: RELOAD Position */
+#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /*!< CMSDK_TIMER RELOAD: RELOAD Mask */
+
+#define CMSDK_TIMER_INTSTATUS_Pos 0 /*!< CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
+#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /*!< CMSDK_TIMER INTSTATUS: INTSTATUSMask */
+
+#define CMSDK_TIMER_INTCLEAR_Pos 0 /*!< CMSDK_TIMER INTCLEAR: INTCLEAR Position */
+#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /*!< CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
+
+/*@}*/ /* end of group CMSDK_TIMER */
+
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+// <g> Timer (TIM)
+
+/** @addtogroup CMSDK_DualTIMER CMSDK Dual Timer
+ @{
+*/
+
+typedef struct
+{
+ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
+ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
+ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
+ // <o.7> TimerEn: Timer Enable
+ // <o.6> TimerMode: Timer Mode
+ // <0=> Freerunning-mode
+ // <1=> Periodic mode
+ // <o.5> IntEnable: Interrupt Enable
+ // <o.2..3> TimerPre: Timer Prescale
+ // <0=> / 1
+ // <1=> / 16
+ // <2=> / 256
+ // <3=> Undefined!
+ // <o.1> TimerSize: Timer Size
+ // <0=> 16-bit counter
+ // <1=> 32-bit counter
+ // <o.0> OneShot: One-shoot mode
+ // <0=> Wrapping mode
+ // <1=> One-shot mode
+ // </h>
+ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
+ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
+ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
+ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
+ uint32_t RESERVED0;
+ __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
+ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
+ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
+ // <o.7> TimerEn: Timer Enable
+ // <o.6> TimerMode: Timer Mode
+ // <0=> Freerunning-mode
+ // <1=> Periodic mode
+ // <o.5> IntEnable: Interrupt Enable
+ // <o.2..3> TimerPre: Timer Prescale
+ // <0=> / 1
+ // <1=> / 16
+ // <2=> / 256
+ // <3=> Undefined!
+ // <o.1> TimerSize: Timer Size
+ // <0=> 16-bit counter
+ // <1=> 32-bit counter
+ // <o.0> OneShot: One-shoot mode
+ // <0=> Wrapping mode
+ // <1=> One-shot mode
+ // </h>
+ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
+ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
+ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
+ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
+ uint32_t RESERVED1[945];
+ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
+ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
+} CMSDK_DUALTIMER_BOTH_TypeDef;
+
+#define CMSDK_DUALTIMER1_LOAD_Pos 0 /*!< CMSDK_DUALTIMER1 LOAD: LOAD Position */
+#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /*!< CMSDK_DUALTIMER1 LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER1_VALUE_Pos 0 /*!< CMSDK_DUALTIMER1 VALUE: VALUE Position */
+#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /*!< CMSDK_DUALTIMER1 VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /*!< CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /*!< CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
+
+#define CMSDK_DUALTIMER2_LOAD_Pos 0 /*!< CMSDK_DUALTIMER2 LOAD: LOAD Position */
+#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /*!< CMSDK_DUALTIMER2 LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER2_VALUE_Pos 0 /*!< CMSDK_DUALTIMER2 VALUE: VALUE Position */
+#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /*!< CMSDK_DUALTIMER2 VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /*!< CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
+
+typedef struct
+{
+ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
+ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
+ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
+ // <o.7> TimerEn: Timer Enable
+ // <o.6> TimerMode: Timer Mode
+ // <0=> Freerunning-mode
+ // <1=> Periodic mode
+ // <o.5> IntEnable: Interrupt Enable
+ // <o.2..3> TimerPre: Timer Prescale
+ // <0=> / 1
+ // <1=> / 16
+ // <2=> / 256
+ // <3=> Undefined!
+ // <o.1> TimerSize: Timer Size
+ // <0=> 16-bit counter
+ // <1=> 32-bit counter
+ // <o.0> OneShot: One-shoot mode
+ // <0=> Wrapping mode
+ // <1=> One-shot mode
+ // </h>
+ __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
+ __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
+ __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
+ __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
+} CMSDK_DUALTIMER_SINGLE_TypeDef;
+
+#define CMSDK_DUALTIMER_LOAD_Pos 0 /*!< CMSDK_DUALTIMER LOAD: LOAD Position */
+#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /*!< CMSDK_DUALTIMER LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER_VALUE_Pos 0 /*!< CMSDK_DUALTIMER VALUE: VALUE Position */
+#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /*!< CMSDK_DUALTIMER VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /*!< CMSDK_DUALTIMER INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /*!< CMSDK_DUALTIMER BGLOAD: Background Load Mask */
+
+/*@}*/ /* end of group CMSDK_DualTIMER */
+
+
+/*-------------------- General Purpose Input Output (GPIO) -------------------*/
+/** @addtogroup CMSDK_GPIO CMSDK GPIO
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
+ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
+ __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
+ __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
+ __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
+ __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
+ __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
+ __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
+ __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
+ __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
+ __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
+ };
+ uint32_t RESERVED1[241];
+ __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
+ __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
+} CMSDK_GPIO_TypeDef;
+
+#define CMSDK_GPIO_DATA_Pos 0 /*!< CMSDK_GPIO DATA: DATA Position */
+#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /*!< CMSDK_GPIO DATA: DATA Mask */
+
+#define CMSDK_GPIO_DATAOUT_Pos 0 /*!< CMSDK_GPIO DATAOUT: DATAOUT Position */
+#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /*!< CMSDK_GPIO DATAOUT: DATAOUT Mask */
+
+#define CMSDK_GPIO_OUTENSET_Pos 0 /*!< CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /*!< CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_OUTENCLR_Pos 0 /*!< CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /*!< CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_INTENSET_Pos 0 /*!< CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /*!< CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTENCLR_Pos 0 /*!< CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /*!< CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTTYPESET_Pos 0 /*!< CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /*!< CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTTYPECLR_Pos 0 /*!< CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /*!< CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTPOLSET_Pos 0 /*!< CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /*!< CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTPOLCLR_Pos 0 /*!< CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /*!< CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTSTATUS_Pos 0 /*!< CMSDK_GPIO INTSTATUS: INTSTATUS Position */
+#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /*!< CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
+
+#define CMSDK_GPIO_INTCLEAR_Pos 0 /*!< CMSDK_GPIO INTCLEAR: INTCLEAR Position */
+#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /*!< CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
+
+#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /*!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
+#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /*!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
+
+#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /*!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
+#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /*!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
+
+/*@}*/ /* end of group CMSDK_GPIO */
+
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+/** @addtogroup CMSDK_SYSCON CMSDK System Control
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
+ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
+ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
+ __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
+ __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
+} CMSDK_SYSCON_TypeDef;
+
+#define CMSDK_SYSCON_REMAP_Pos 0
+#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /*!< CMSDK_SYSCON MEME_CTRL: REMAP Mask */
+
+#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
+#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /*!< CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
+
+#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
+#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /*!< CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
+#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /*!< CMSDK_SYSCON EMICTRL: SIZE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
+#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /*!< CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
+#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /*!< CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
+#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /*!< CMSDK_SYSCON EMICTRL: READCYCLE Mask */
+
+#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
+#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /*!< CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
+
+#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
+#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /*!< CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
+
+#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
+#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /*!< CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
+
+/*@}*/ /* end of group CMSDK_SYSCON */
+
+/*------------- PL230 uDMA (PL230) --------------------------------------*/
+/** @addtogroup CMSDK_PL230 CMSDK uDMA controller
+ @{
+*/
+typedef struct
+{
+ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
+ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
+ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
+ __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
+ __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
+ __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
+ __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
+ __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
+ __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
+ __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
+ __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
+ __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
+ __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
+ __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
+ __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
+ __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
+ uint32_t RESERVED0[3];
+ __IO uint32_t ERR_CLR; /* Offset: 0x04C (R/W) Bus Error Clear Register */
+
+} CMSDK_PL230_TypeDef;
+
+#define PL230_DMA_CHNL_BITS 0
+
+#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /*!< CMSDK_PL230 DMA STATUS: MSTREN Position */
+#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /*!< CMSDK_PL230 DMA STATUS: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /*!< CMSDK_PL230 DMA STATUS: STATE Position */
+#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /*!< CMSDK_PL230 DMA STATUS: STATE Mask */
+
+#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /*!< CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
+#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /*!< CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
+
+#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /*!< CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
+#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /*!< CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
+
+#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /*!< CMSDK_PL230 DMA CFG: MSTREN Position */
+#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /*!< CMSDK_PL230 DMA CFG: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /*!< CMSDK_PL230 DMA CFG: CPCCACHE Position */
+#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /*!< CMSDK_PL230 DMA CFG: CPCCACHE Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /*!< CMSDK_PL230 DMA CFG: CPCBUF Position */
+#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /*!< CMSDK_PL230 DMA CFG: CPCBUF Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /*!< CMSDK_PL230 DMA CFG: CPCPRIV Position */
+#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /*!< CMSDK_PL230 DMA CFG: CPCPRIV Mask */
+
+#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /*!< CMSDK_PL230 STATUS: BASE_PTR Position */
+#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /*!< CMSDK_PL230 STATUS: BASE_PTR Mask */
+
+#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /*!< CMSDK_PL230 STATUS: MSTREN Position */
+#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /*!< CMSDK_PL230 STATUS: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /*!< CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
+#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /*!< CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
+
+#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /*!< CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
+#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /*!< CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
+
+#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /*!< CMSDK_PL230 CHNL_USEBURST: SET Position */
+#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /*!< CMSDK_PL230 CHNL_USEBURST: SET Mask */
+
+#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_USEBURST: CLR Position */
+#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /*!< CMSDK_PL230 CHNL_USEBURST: CLR Mask */
+
+#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /*!< CMSDK_PL230 CHNL_REQ_MASK: SET Position */
+#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /*!< CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
+
+#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
+#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /*!< CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
+
+#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /*!< CMSDK_PL230 CHNL_ENABLE: SET Position */
+#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /*!< CMSDK_PL230 CHNL_ENABLE: SET Mask */
+
+#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_ENABLE: CLR Position */
+#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /*!< CMSDK_PL230 CHNL_ENABLE: CLR Mask */
+
+#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /*!< CMSDK_PL230 CHNL_PRI_ALT: SET Position */
+#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /*!< CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
+
+#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
+#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /*!< CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
+
+#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /*!< CMSDK_PL230 CHNL_PRIORITY: SET Position */
+#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /*!< CMSDK_PL230 CHNL_PRIORITY: SET Mask */
+
+#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_PRIORITY: CLR Position */
+#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /*!< CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
+
+#define CMSDK_PL230_ERR_CLR_Pos 0 /*!< CMSDK_PL230 ERR: CLR Position */
+#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /*!< CMSDK_PL230 ERR: CLR Mask */
+
+
+/*@}*/ /* end of group CMSDK_PL230 */
+
+
+/*------------- PrimeCell UART (PL110) --------------------------------------*/
+/** @addtogroup CMSDK_PL110 CMSDK PrimeCell UART
+ @{
+*/
+
+typedef struct
+{
+ __IO uint32_t UARTDR; // <h> Data
+ // <o.11> OE: Overrun error <r>
+ // <o.10> BE: Break error <r>
+ // <o.9> PE: Parity error <r>
+ // <o.8> FE: Framing error <r>
+ // <o.0..7> DATA: Received or Transmitting data (0..255)
+ // </h>
+ union {
+ __I uint32_t UARTRSR; // <h> Receive Status <r>
+ // <o.3> OE: Overrun error <r>
+ // <o.2> BE: Break error <r>
+ // <o.1> PE: Parity error <r>
+ // <o.0> FE: Framing error <r>
+ // </h>
+ __O uint32_t UARTECR; // <h> Error Clear <w>
+ // <o.3> OE: Overrun error <w>
+ // <o.2> BE: Break error <w>
+ // <o.1> PE: Parity error <w>
+ // <o.0> FE: Framing error <w>
+ // </h>
+ };
+ uint32_t RESERVED0[4];
+ __IO uint32_t UARTFR; // <h> Flags <r>
+ // <o.8> RI: Ring indicator <r>
+ // <o.7> TXFE: Transmit FIFO empty <r>
+ // <o.6> RXFF: Receive FIFO full <r>
+ // <o.5> TXFF: Transmit FIFO full <r>
+ // <o.4> RXFE: Receive FIFO empty <r>
+ // <o.3> BUSY: UART busy <r>
+ // <o.2> DCD: Data carrier detect <r>
+ // <o.1> DSR: Data set ready <r>
+ // <o.0> CTS: Clear to send <r>
+ // </h>
+ uint32_t RESERVED1;
+ __IO uint32_t UARTILPR; // <h> IrDA Low-power Counter
+ // <o.0..7> ILPDVSR: 8-bit low-power divisor value (0..255)
+ // </h>
+ __IO uint32_t UARTIBRD; // <h> Integer Baud Rate
+ // <o.0..15> BAUD DIVINT: Integer baud rate divisor (0..65535)
+ // </h>
+ __IO uint32_t UARTFBRD; // <h> Fractional Baud Rate
+ // <o.0..5> BAUD DIVFRAC: Fractional baud rate divisor (0..63)
+ // </h>
+ __IO uint32_t UARTLCR_H; // <h> Line Control
+ // <o.8> SPS: Stick parity select
+ // <o.5..6> WLEN: Word length
+ // <0=> 5 bits
+ // <1=> 6 bits
+ // <2=> 7 bits
+ // <3=> 8 bits
+ // <o.4> FEN: Enable FIFOs
+ // <o.3> STP2: Two stop bits select
+ // <o.2> EPS: Even parity select
+ // <o.1> PEN: Parity enable
+ // <o.0> BRK: Send break
+ // </h>
+ __IO uint32_t UARTCR; // <h> Control
+ // <o.15> CTSEn: CTS hardware flow control enable
+ // <o.14> RTSEn: RTS hardware flow control enable
+ // <o.13> Out2: Complement of Out2 modem status output
+ // <o.12> Out1: Complement of Out1 modem status output
+ // <o.11> RTS: Request to send
+ // <o.10> DTR: Data transmit ready
+ // <o.9> RXE: Receive enable
+ // <o.8> TXE: Transmit enable
+ // <o.7> LBE: Loop-back enable
+ // <o.2> SIRLP: IrDA SIR low power mode
+ // <o.1> SIREN: SIR enable
+ // <o.0> UARTEN: UART enable
+ // </h>
+ __IO uint32_t UARTIFLS; // <h> Interrupt FIFO Level Select
+ // <o.3..5> RXIFLSEL: Receive interrupt FIFO level select
+ // <0=> >= 1/8 full
+ // <1=> >= 1/4 full
+ // <2=> >= 1/2 full
+ // <3=> >= 3/4 full
+ // <4=> >= 7/8 full
+ // <5=> reserved
+ // <6=> reserved
+ // <7=> reserved
+ // <o.0..2> TXIFLSEL: Transmit interrupt FIFO level select
+ // <0=> <= 1/8 full
+ // <1=> <= 1/4 full
+ // <2=> <= 1/2 full
+ // <3=> <= 3/4 full
+ // <4=> <= 7/8 full
+ // <5=> reserved
+ // <6=> reserved
+ // <7=> reserved
+ // </h>
+ __IO uint32_t UARTIMSC; // <h> Interrupt Mask Set / Clear
+ // <o.10> OEIM: Overrun error interrupt mask
+ // <o.9> BEIM: Break error interrupt mask
+ // <o.8> PEIM: Parity error interrupt mask
+ // <o.7> FEIM: Framing error interrupt mask
+ // <o.6> RTIM: Receive interrupt mask
+ // <o.5> TXIM: Transmit interrupt mask
+ // <o.4> RXIM: Receive interrupt mask
+ // <o.3> DSRMIM: nUARTDSR modem interrupt mask
+ // <o.2> DCDMIM: nUARTDCD modem interrupt mask
+ // <o.1> CTSMIM: nUARTCTS modem interrupt mask
+ // <o.0> RIMIM: nUARTRI modem interrupt mask
+ // </h>
+ __IO uint32_t UARTRIS; // <h> Raw Interrupt Status <r>
+ // <o.10> OERIS: Overrun error interrupt status <r>
+ // <o.9> BERIS: Break error interrupt status <r>
+ // <o.8> PERIS: Parity error interrupt status <r>
+ // <o.7> FERIS: Framing error interrupt status <r>
+ // <o.6> RTRIS: Receive timeout interrupt status <r>
+ // <o.5> TXRIS: Transmit interrupt status <r>
+ // <o.4> RXRIS: Receive interrupt status <r>
+ // <o.3> DSRRMIS: nUARTDSR modem interrupt status <r>
+ // <o.2> DCDRMIS: nUARTDCD modem interrupt status <r>
+ // <o.1> CTSRMIS: nUARTCTS modem interrupt status <r>
+ // <o.0> RIRMIS: nUARTRI modem interrupt status <r>
+ // </h>
+ __IO uint32_t UARTMIS; // <h> Masked Interrupt Status <r>
+ // <o.10> OEMIS: Overrun error masked interrupt status <r>
+ // <o.9> BEMIS: Break error masked interrupt status <r>
+ // <o.8> PEMIS: Parity error masked interrupt status <r>
+ // <o.7> FEMIS: Framing error masked interrupt status <r>
+ // <o.6> RTMIS: Receive timeout masked interrupt status <r>
+ // <o.5> TXMIS: Transmit masked interrupt status <r>
+ // <o.4> RXMIS: Receive masked interrupt status <r>
+ // <o.3> DSRMMIS: nUARTDSR modem masked interrupt status <r>
+ // <o.2> DCDMMIS: nUARTDCD modem masked interrupt status <r>
+ // <o.1> CTSMMIS: nUARTCTS modem masked interrupt status <r>
+ // <o.0> RIMMIS: nUARTRI modem masked interrupt status <r>
+ // </h>
+ __O uint32_t UARTICR; // <h> Interrupt Clear <w>
+ // <o.10> OEIC: Overrun error interrupt clear <w>
+ // <o.9> BEIC: Break error interrupt clear <w>
+ // <o.8> PEIC: Parity error interrupt clear <w>
+ // <o.7> FEIC: Framing error interrupt clear <w>
+ // <o.6> RTIC: Receive timeout interrupt clear <w>
+ // <o.5> TXIC: Transmit interrupt clear <w>
+ // <o.4> RXIC: Receive interrupt clear <w>
+ // <o.3> DSRMIC: nUARTDSR modem interrupt clear <w>
+ // <o.2> DCDMIC: nUARTDCD modem interrupt clear <w>
+ // <o.1> CTSMIC: nUARTCTS modem interrupt clear <w>
+ // <o.0> RIMIC: nUARTRI modem interrupt clear <w>
+ // </h>
+ __IO uint32_t UARTDMACR; // <h> DMA Control
+ // <o.2> DMAONERR: DMA on error
+ // <o.1> TXDMAE: Transmit DMA enable
+ // <o.0> RXDMAE: Receive DMA enable
+ // </h>
+} PL110_UART_TypeDef;
+
+#define CMSDK_PL110_DATAOVRRUN_Pos 11 /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Position */
+#define CMSDK_PL110_DATAOVRRUN_Msk (0x1ul << CMSDK_PL110_DATAOVRRUN_Pos) /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Mask */
+
+#define CMSDK_PL110_DATABREAKERR_Pos 10 /*!< CMSDK_PL110 DATABREAKERR: Data Break Error Position */
+#define CMSDK_PL110_DATABREAKERR_Msk (0x1ul << CMSDK_PL110_DATABREAKERR_Pos) /*!< CMSDK_PL110 DATABREAKERR: Data Break Error Mask */
+
+#define CMSDK_PL110_DATAPARITYERR_Pos 9 /*!< CMSDK_PL110 DATAPARITYERR: Data Parity Error Position */
+#define CMSDK_PL110_DATAPARITYERR_Msk (0x1ul << CMSDK_PL110_DATAPARITYERR_Pos) /*!< CMSDK_PL110 DATAPARITYERR: Data Parity Error Mask */
+
+#define CMSDK_PL110_DATAFRAMEERR_Pos 8 /*!< CMSDK_PL110 DATAFRAMEERR: Data Frame Error Position */
+#define CMSDK_PL110_DATAFRAMEERR_Msk (0x1ul << CMSDK_PL110_DATAFRAMEERR_Pos) /*!< CMSDK_PL110 DATAFRAMEERR: Data Frame Error Mask */
+
+#define CMSDK_PL110_RECOVRRUN_Pos 3 /*!< CMSDK_PL110 RECOVRRUN: Receive Overrun Position */
+#define CMSDK_PL110_RECOVRRUN_Msk (0x1ul << CMSDK_PL110_RECOVRRUN_Pos) /*!< CMSDK_PL110 RECOVRRUN: Receive Overrun Mask */
+
+#define CMSDK_PL110_RECBREAKERR_Pos 2 /*!< CMSDK_PL110 RECBREAKERR: Receive Break Error Position */
+#define CMSDK_PL110_RECBREAKERR_Msk (0x1ul << CMSDK_PL110_RECBREAKERR_Pos) /*!< CMSDK_PL110 RECBREAKERR: Receive Break Error Mask */
+
+#define CMSDK_PL110_RECPARITYERR_Pos 1 /*!< CMSDK_PL110 RECPARITYERR: Receive Parity Error Position */
+#define CMSDK_PL110_RECPARITYERR_Msk (0x1ul << CMSDK_PL110_RECPARITYERR_Pos) /*!< CMSDK_PL110 RECPARITYERR: Receive Parity Error Mask */
+
+#define CMSDK_PL110_RECFRAMEERR_Pos 0 /*!< CMSDK_PL110 RECFRAMEERR: Receive Frame Error Position */
+#define CMSDK_PL110_RECFRAMEERR_Msk (0x1ul << CMSDK_PL110_RECFRAMEERR_Pos) /*!< CMSDK_PL110 RECFRAMEERR: Receive Frame Error Mask */
+
+#define CMSDK_PL110_ERRCLROVRRUN_Pos 3 /*!< CMSDK_PL110 ERRCLROVRRUN: Clear Overrun Position */
+#define CMSDK_PL110_ERRCLROVRRUN_Msk (0x1ul << CMSDK_PL110_ERRCLROVRRUN_Pos) /*!< CMSDK_PL110 ERRCLROVRRUN: Clear Overrun Mask */
+
+#define CMSDK_PL110_ERRCLRBREAKERR_Pos 2 /*!< CMSDK_PL110 ERRCLRBREAKERR: Clear Break Error Position */
+#define CMSDK_PL110_ERRCLRBREAKERR_Msk (0x1ul << CMSDK_PL110_ERRCLRBREAKERR_Pos) /*!< CMSDK_PL110 ERRCLRBREAKERR: Clear Break Error Mask */
+
+#define CMSDK_PL110_ERRCLRPARITYERR_Pos 1 /*!< CMSDK_PL110 ERRCLRPARITYERR: Clear Parity Error Position */
+#define CMSDK_PL110_ERRCLRPARITYERR_Msk (0x1ul << CMSDK_PL110_ERRCLRPARITYERR_Pos) /*!< CMSDK_PL110 ERRCLRPARITYERR: Clear Parity Error Mask */
+
+#define CMSDK_PL110_ERRCLRFRAMEERR_Pos 0 /*!< CMSDK_PL110 ERRCLRFRAMEERR: Clear Frame Error Position */
+#define CMSDK_PL110_ERRCLRFRAMEERR_Msk (0x1ul << CMSDK_PL110_ERRCLRFRAMEERR_Pos) /*!< CMSDK_PL110 ERRCLRFRAMEERR: Clear Frame Error Mask */
+
+#define CMSDK_PL110_FLAG_RINGIND_Pos 8 /*!< CMSDK_PL110 FLAG_RINGIND: Ring Indicator Position */
+#define CMSDK_PL110_FLAG_RINGIND_Msk (0x1ul << CMSDK_PL110_FLAG_RINGIND_Pos) /*!< CMSDK_PL110 FLAG_RINGIND: Ring Indicator Mask */
+
+#define CMSDK_PL110_FLAG_TXFEMPTY_Pos 7 /*!< CMSDK_PL110 FLAG_TXFEMPTY: Transmit FIFO Empty Position */
+#define CMSDK_PL110_FLAG_TXFEMPTY_Msk (0x1ul << CMSDK_PL110_FLAG_TXFEMPTY_Pos) /*!< CMSDK_PL110 FLAG_TXFEMPTY: Transmit FIFO Empty Mask */
+
+#define CMSDK_PL110_FLAG_RXFFULL_Pos 6 /*!< CMSDK_PL110 FLAG_RXFFULL: Receive FIFO Full Position */
+#define CMSDK_PL110_FLAG_RXFFULL_Msk (0x1ul << CMSDK_PL110_FLAG_RXFFULL_Pos) /*!< CMSDK_PL110 FLAG_RXFFULL: Receive FIFO Full Mask */
+
+#define CMSDK_PL110_FLAG_TXFFULL_Pos 5 /*!< CMSDK_PL110 FLAG_TXFFULL: Transmit FIFO Full Position */
+#define CMSDK_PL110_FLAG_TXFFULL_Msk (0x1ul << CMSDK_PL110_FLAG_TXFFULL_Pos) /*!< CMSDK_PL110 FLAG_TXFFULL: Transmit FIFO Full Mask */
+
+#define CMSDK_PL110_FLAG_RXFEMPTY_Pos 4 /*!< CMSDK_PL110 FLAG_RXFEMPTY: Receive FIFO Empty Position */
+#define CMSDK_PL110_FLAG_RXFEMPTY_Msk (0x1ul << CMSDK_PL110_FLAG_RXFEMPTY_Pos) /*!< CMSDK_PL110 FLAG_RXFEMPTY: Receive FIFO Empty Mask */
+
+#define CMSDK_PL110_FLAG_UARTBUSY_Pos 3 /*!< CMSDK_PL110 FLAG_UARTBUSY: UART Busy Position */
+#define CMSDK_PL110_FLAG_UARTBUSY_Msk (0x1ul << CMSDK_PL110_FLAG_UARTBUSY_Pos) /*!< CMSDK_PL110 FLAG_UARTBUSY: UART Busy Mask */
+
+#define CMSDK_PL110_FLAG_CARRIERDETECT_Pos 2 /*!< CMSDK_PL110 FLAG_CARRIERDETECT: Carrier Detect Position */
+#define CMSDK_PL110_FLAG_CARRIERDETECT_Msk (0x1ul << CMSDK_PL110_FLAG_CARRIERDETECT_Pos) /*!< CMSDK_PL110 FLAG_CARRIERDETECT: Carrier Detect Mask */
+
+#define CMSDK_PL110_FLAG_DATASETREADY_Pos 1 /*!< CMSDK_PL110 FLAG_DATASETREADY: Data Set Ready Position */
+#define CMSDK_PL110_FLAG_DATASETREADY_Msk (0x1ul << CMSDK_PL110_FLAG_DATASETREADY_Pos) /*!< CMSDK_PL110 FLAG_DATASETREADY: Data Set Ready Mask */
+
+#define CMSDK_PL110_FLAG_CLR2SEND_Pos 0 /*!< CMSDK_PL110 FLAG_CLR2SEND: Clear To Send Position */
+#define CMSDK_PL110_FLAG_CLR2SEND_Msk (0x1ul << CMSDK_PL110_FLAG_CLR2SEND_Pos) /*!< CMSDK_PL110 FLAG_CLR2SEND: Clear To Send Mask */
+
+#define CMSDK_PL110_IRDALOWPOWERCOUNT_Pos 0 /*!< CMSDK_PL110 IRDALOWPOWERCOUNT: IrDA 8-bit low-power divisor value Position */
+#define CMSDK_PL110_IRDALOWPOWERCOUNT_Msk (0xFFul << CMSDK_PL110_IRDALOWPOWERCOUNT_Pos) /*!< CMSDK_PL110 IRDALOWPOWERCOUNT: IrDA 8-bit low-power divisor value Mask */
+
+#define CMSDK_PL110_INTDIVIDER_Pos 0 /*!< CMSDK_PL110 INTDIVIDER: Integer Divider Position */
+#define CMSDK_PL110_INTDIVIDER_Msk (0xFFFFul << CMSDK_PL110_INTDIVIDER_Pos) /*!< CMSDK_PL110 INTDIVIDER: Integer Divider Mask */
+
+#define CMSDK_PL110_FRACTDIVIDER_Pos 0 /*!< CMSDK_PL110 FRACTDIVIDER: Fractional Divider Position */
+#define CMSDK_PL110_FRACTDIVIDER_Msk (0x3Ful << CMSDK_PL110_FRACTDIVIDER_Pos) /*!< CMSDK_PL110 FRACTDIVIDER: Fractional Divider Mask */
+
+#define CMSDK_PL110_STICKPARITYSEL_Pos 8 /*!< CMSDK_PL110 STICKPARITYSEL: Stick parity select Position */
+#define CMSDK_PL110_STICKPARITYSEL_Msk (0x1ul << CMSDK_PL110_STICKPARITYSEL_Pos) /*!< CMSDK_PL110 STICKPARITYSEL: Stick parity select Mask */
+
+#define CMSDK_PL110_WORDLEN_Pos 5 /*!< CMSDK_PL110 WORDLEN: Word Length Select Position */
+#define CMSDK_PL110_WORDLEN_Msk (0x3ul << CMSDK_PL110_WORDLEN_Pos) /*!< CMSDK_PL110 WORDLEN: Word Length Select Mask */
+
+#define CMSDK_PL110_ENFIFOS_Pos 4 /*!< CMSDK_PL110 ENFIFOS: Enable FIFOs Position */
+#define CMSDK_PL110_ENFIFOS_Msk (0x1ul << CMSDK_PL110_ENFIFOS_Pos) /*!< CMSDK_PL110 ENFIFOS: Enable FIFOs Mask */
+
+#define CMSDK_PL110_2STOPBITS_Pos 3 /*!< CMSDK_PL110 2STOPBITS: Two Stop Bits Select Position */
+#define CMSDK_PL110_2STOPBITS_Msk (0x1ul << CMSDK_PL110_2STOPBITS_Pos) /*!< CMSDK_PL110 2STOPBITS: Two Stop Bits Select Mask */
+
+#define CMSDK_PL110_EVENPARITY_Pos 2 /*!< CMSDK_PL110 EVENPARITY: Even Parity Select Position */
+#define CMSDK_PL110_EVENPARITY_Msk (0x1ul << CMSDK_PL110_EVENPARITY_Pos) /*!< CMSDK_PL110 EVENPARITY: Even Parity Select Mask */
+
+#define CMSDK_PL110_PARITYEN_Pos 1 /*!< CMSDK_PL110 PARITYEN: Parity Enable Position */
+#define CMSDK_PL110_PARITYEN_Msk (0x1ul << CMSDK_PL110_PARITYEN_Pos) /*!< CMSDK_PL110 PARITYEN: Parity Enable Mask */
+
+#define CMSDK_PL110_SENDBREAK_Pos 0 /*!< CMSDK_PL110 SENDBREAK: Send Break Position */
+#define CMSDK_PL110_SENDBREAK_Msk (0x1ul << CMSDK_PL110_SENDBREAK_Pos) /*!< CMSDK_PL110 SENDBREAK: Send Break Mask */
+
+#define CMSDK_PL110_CTS_FLOWCTRL_Pos 15 /*!< CMSDK_PL110 CTS_FLOWCTRL: Enable CTS Flow Control Position */
+#define CMSDK_PL110_CTS_FLOWCTRL_Msk (0x1ul << CMSDK_PL110_CTS_FLOWCTRL_Pos) /*!< CMSDK_PL110 CTS_FLOWCTRL: Enable CTS Flow Control Mask */
+
+#define CMSDK_PL110_RTS_FLOWCTRL_Pos 14 /*!< CMSDK_PL110 RTS_FLOWCTRL: Enable RTS Flow Control Position */
+#define CMSDK_PL110_RTS_FLOWCTRL_Msk (0x1ul << CMSDK_PL110_RTS_FLOWCTRL_Pos) /*!< CMSDK_PL110 RTS_FLOWCTRL: Enable RTS Flow Control Mask */
+
+#define CMSDK_PL110_OUT2_Pos 13 /*!< CMSDK_PL110 OUT2: Complement of Out2 modem status output Position */
+#define CMSDK_PL110_OUT2_Msk (0x1ul << CMSDK_PL110_OUT2_Pos) /*!< CMSDK_PL110 OUT2: Complement of Out2 modem status output Mask */
+
+#define CMSDK_PL110_OUT1_Pos 12 /*!< CMSDK_PL110 OUT1: Complement of Out1 modem status output Position */
+#define CMSDK_PL110_OUT1_Msk (0x1ul << CMSDK_PL110_OUT1_Pos) /*!< CMSDK_PL110 OUT1: Complement of Out1 modem status output Mask */
+
+#define CMSDK_PL110_REQ2SEND_Pos 11 /*!< CMSDK_PL110 REQ2SEND: Request To Send Position */
+#define CMSDK_PL110_REQ2SEND_Msk (0x1ul << CMSDK_PL110_REQ2SEND_Pos) /*!< CMSDK_PL110 REQ2SEND: Request To Send Mask */
+
+#define CMSDK_PL110_DATATRANSREADY_Pos 10 /*!< CMSDK_PL110 DATATRANSREADY: Transmit Ready Position */
+#define CMSDK_PL110_DATATRANSREADY_Msk (0x1ul << CMSDK_PL110_DATATRANSREADY_Pos) /*!< CMSDK_PL110 DATATRANSREADY: Transmit Ready Mask */
+
+#define CMSDK_PL110_RXEN_Pos 9 /*!< CMSDK_PL110 RXEN: Receive Enable Position */
+#define CMSDK_PL110_RXEN_Msk (0x1ul << CMSDK_PL110_RXEN_Pos) /*!< CMSDK_PL110 RXEN: Receive Enable Mask */
+
+#define CMSDK_PL110_TXEN_Pos 8 /*!< CMSDK_PL110 TXEN: Transmit Enable Position */
+#define CMSDK_PL110_TXEN_Msk (0x1ul << CMSDK_PL110_TXEN_Pos) /*!< CMSDK_PL110 TXEN: Transmit Enable Mask */
+
+#define CMSDK_PL110_LOOPBACKEN_Pos 7 /*!< CMSDK_PL110 LOOPBACKEN: Loopback Enable Position */
+#define CMSDK_PL110_LOOPBACKEN_Msk (0x1ul << CMSDK_PL110_LOOPBACKEN_Pos) /*!< CMSDK_PL110 LOOPBACKEN: Loopback Enable Mask */
+
+#define CMSDK_PL110_IRDASIRLPM_Pos 2 /*!< CMSDK_PL110 IRDASIRLPM: IRDA SIR Low Power Position */
+#define CMSDK_PL110_IRDASIRLPM_Msk (0x1ul << CMSDK_PL110_IRDASIRLPM_Pos) /*!< CMSDK_PL110 IRDASIRLPM: IRDA SIR Low Power Mask */
+
+#define CMSDK_PL110_SIREN_Pos 1 /*!< CMSDK_PL110 SIREN: SIR Enable Position */
+#define CMSDK_PL110_SIREN_Msk (0x1ul << CMSDK_PL110_SIREN_Pos) /*!< CMSDK_PL110 SIREN: SIR Enable Mask */
+
+#define CMSDK_PL110_UARTEN_Pos 0 /*!< CMSDK_PL110 UARTEN: UART Enable Position */
+#define CMSDK_PL110_UARTEN_Msk (0x1ul << CMSDK_PL110_UARTEN_Pos) /*!< CMSDK_PL110 UARTEN: UART Enable Mask */
+
+#define CMSDK_PL110_RECINTFIFOLEVEL_Pos 3 /*!< CMSDK_PL110 RECINTFIFOLEVEL: Set Receive Int FIFO Level Position */
+#define CMSDK_PL110_RECINTFIFOLEVEL_Msk (0x7ul << CMSDK_PL110_RECINTFIFOLEVEL_Pos) /*!< CMSDK_PL110 RECINTFIFOLEVEL: Set Receive Int FIFO Level Mask */
+
+#define CMSDK_PL110_TRANSINTFIFOLEVEL_Pos 0 /*!< CMSDK_PL110 TRANSINTFIFOLEVEL: Set Transmit Int FIFO Level Position */
+#define CMSDK_PL110_TRANSINTFIFOLEVEL_Msk (0x7ul << CMSDK_PL110_TRANSINTFIFOLEVEL_Pos) /*!< CMSDK_PL110 TRANSINTFIFOLEVEL: Set Transmit Int FIFO Level Mask */
+
+#define CMSDK_PL110_SETMASK_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 SETMASK_OVRRUNERRINT: Set Overrun Error Int Mask Position */
+#define CMSDK_PL110_SETMASK_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 SETMASK_OVRRUNERRINT: Set Overrun Error Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 SETMASK_BREAKERRINT: Set Break Error Int Mask Position */
+#define CMSDK_PL110_SETMASK_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_BREAKERRINT_Pos) /*!< CMSDK_PL110 SETMASK_BREAKERRINT: Set Break Error Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 SETMASK_PARITYERRINT: Set Parity Error Int Mask Position */
+#define CMSDK_PL110_SETMASK_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_PARITYERRINT_Pos) /*!< CMSDK_PL110 SETMASK_PARITYERRINT: Set Parity Error Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 SETMASK_FRAMEERRINT: Set Frame Error Int Mask Position */
+#define CMSDK_PL110_SETMASK_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_FRAMEERRINT_Pos) /*!< CMSDK_PL110 SETMASK_FRAMEERRINT: Set Frame Error Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 SETMASK_RECTRANSINT: Set Transmit Receive Comb Int Mask Position */
+#define CMSDK_PL110_SETMASK_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_SETMASK_RECTRANSINT_Pos) /*!< CMSDK_PL110 SETMASK_RECTRANSINT: Set Transmit Receive Comb Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_TRANSINT_Pos 5 /*!< CMSDK_PL110 SETMASK_TRANSINT: Set Transmit Int Mask Position */
+#define CMSDK_PL110_SETMASK_TRANSINT_Msk (0x1ul << CMSDK_PL110_SETMASK_TRANSINT_Pos) /*!< CMSDK_PL110 SETMASK_TRANSINT: Set Transmit Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_RECINT_Pos 4 /*!< CMSDK_PL110 SETMASK_RECINT: Set Receive Int Mask Position */
+#define CMSDK_PL110_SETMASK_RECINT_Msk (0x1ul << CMSDK_PL110_SETMASK_RECINT_Pos) /*!< CMSDK_PL110 SETMASK_RECINT: Set Receive Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 SETMASK_UART_DSRMODINT: Set Data Set Ready Modem Int Mask Position */
+#define CMSDK_PL110_SETMASK_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_DSRMODINT: Set Data Set Ready Modem Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 SETMASK_UART_DCDMODINT: Set Data Carrier Detect Modem Int Mask Position */
+#define CMSDK_PL110_SETMASK_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_DCDMODINT: Set Data Carrier Detect Modem Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 SETMASK_UART_CTSMODINT: Set Clear To Send Modem Int Mask Position */
+#define CMSDK_PL110_SETMASK_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_CTSMODINT: Set Clear To Send Modem Int Mask Mask */
+
+#define CMSDK_PL110_SETMASK_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 SETMASK_UART_RIMODINT: Set nUARTRI Modem Int Mask Position */
+#define CMSDK_PL110_SETMASK_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_RIMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_RIMODINT: Set nUARTRI Modem Int Mask Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 RAWINTSTAT_OVRRUNERRINT: Raw Overrun Error Int Status Mask Position */
+#define CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_OVRRUNERRINT: Raw Overrun Error Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 RAWINTSTAT_BREAKERRINT: Raw Break Error Int Status Mask Position */
+#define CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_BREAKERRINT: Raw Break Error Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 RAWINTSTAT_PARITYERRINT: Raw Parity Error Int Status Mask Position */
+#define CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_PARITYERRINT: Raw Parity Error Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 RAWINTSTAT_FRAMEERRINT: Raw Frame Error Int Status Mask Position */
+#define CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_FRAMEERRINT: Raw Frame Error Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 RAWINTSTAT_RECTRANSINT: Raw Transmit Receive Comb Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_RECTRANSINT: Raw Transmit Receive Comb Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_TRANSINT_Pos 5 /*!< CMSDK_PL110 RAWINTSTAT_TRANSINT: Raw Transmit Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_TRANSINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_TRANSINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_TRANSINT: Raw Transmit Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_RECINT_Pos 4 /*!< CMSDK_PL110 RAWINTSTAT_RECINT: Raw Receive Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_RECINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_RECINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_RECINT: Raw Receive Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 RAWINTSTAT_UART_DSRMODINT: Raw Data Set Ready Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UARTD_SRMODINT: Raw Data Set Ready Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 RAWINTSTAT_UART_DCDMODINT: Raw Data Carrier Detect Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_DCDMODINT: Raw Data Carrier Detect Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 RAWINTSTAT_UART_CTSMODINT: Raw Clear To Send Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_CTSMODINT: Raw Clear To Send Int Status Mask */
+
+#define CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 RAWINTSTAT_UART_RIMODINT: Raw nUARTRI Modem Int Status Position */
+#define CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_RIMODINT: Raw nUARTRI Modem Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 MSKINTSTAT_OVRRUNERRINT: Masked Overrun Error Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_OVRRUNERRINT: Masked Overrun Error Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 MSKINTSTAT_BREAKERRINT: Masked Break Error Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_BREAKERRINT: Masked Break Error Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 MSKINTSTAT_PARITYERRINT: Masked Parity Error Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_PARITYERRINT: Masked Parity Error Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 MSKINTSTAT_FRAMEERRINT: Masked Frame Error Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_FRAMEERRINT: Masked Frame Error Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 MSKINTSTAT_RECTRANSINT: Masked Transmit Receive Comb Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_RECTRANSINT: Masked Transmit Receive Comb Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_TRANSINT_Pos 5 /*!< CMSDK_PL110 MSKINTSTAT_TRANSINT: Masked Transmit Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_TRANSINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_TRANSINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_TRANSINT: Masked Transmit Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_RECINT_Pos 4 /*!< CMSDK_PL110 MSKINTSTAT_RECINT: Masked Receive Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_RECINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_RECINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_RECINT: Masked Receive Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 MSKINTSTAT_UART_DSRMODINT: Masked Data Set Ready Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_DSRMODINT: Masked Data Set Ready Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 MSKINTSTAT_UART_DCDMODINT: Masked Data Carrier Detect Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_DCDMODINT: Masked Data Carrier Detect Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 MSKINTSTAT_UART_CTSMODINT: Masked Clear To Send Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_CTSMODINT: Masked Clear To Send Int Status Mask */
+
+#define CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 MSKINTSTAT_UART_RIMODINT: Masked nUARTRI Modem Int Status Position */
+#define CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_RIMODINT: Masked nUARTRI Modem Int Status Mask */
+
+#define CMSDK_PL110_INTCLR_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 INTCLR_OVRRUNERRINT: Clear Overrun Error Int Position */
+#define CMSDK_PL110_INTCLR_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 INTCLR_OVRRUNERRINT: Clear Overrun Error Int Mask */
+
+#define CMSDK_PL110_INTCLR_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 INTCLR_BREAKERRINT: Clear Break Error Int Position */
+#define CMSDK_PL110_INTCLR_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_BREAKERRINT_Pos) /*!< CMSDK_PL110 INTCLR_BREAKERRINT: Clear Break Error Int Mask */
+
+#define CMSDK_PL110_INTCLR_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 INTCLR_PARITYERRINT: Clear Parity Error Int Position */
+#define CMSDK_PL110_INTCLR_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_PARITYERRINT_Pos) /*!< CMSDK_PL110 INTCLR_PARITYERRINT: Clear Parity Error Int Mask */
+
+#define CMSDK_PL110_INTCLR_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 INTCLR_FRAMEERRINT: Clear Frame Error Int Position */
+#define CMSDK_PL110_INTCLR_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_FRAMEERRINT_Pos) /*!< CMSDK_PL110 INTCLR_FRAMEERRINT: Clear Frame Error Int Mask */
+
+#define CMSDK_PL110_INTCLR_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 INTCLR_RECTRANSINT: Clear Receive Transmit Comb Int Position */
+#define CMSDK_PL110_INTCLR_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_INTCLR_RECTRANSINT_Pos) /*!< CMSDK_PL110 INTCLR_RECTRANSINT: Clear Receive Transmit Comb Int Mask */
+
+#define CMSDK_PL110_INTCLR_TRANSINT_Pos 5 /*!< CMSDK_PL110 INTCLR_TRANSINT: Clear Transmit Int Position */
+#define CMSDK_PL110_INTCLR_TRANSINT_Msk (0x1ul << CMSDK_PL110_INTCLR_TRANSINT_Pos) /*!< CMSDK_PL110 INTCLR_TRANSINT: Clear Transmit Int Mask */
+
+#define CMSDK_PL110_INTCLR_RECINT_Pos 4 /*!< CMSDK_PL110 INTCLR_RECINT: Clear Receive Int Position */
+#define CMSDK_PL110_INTCLR_RECINT_Msk (0x1ul << CMSDK_PL110_INTCLR_RECINT_Pos) /*!< CMSDK_PL110 INTCLR_RECINT: Clear Receive Int Mask */
+
+#define CMSDK_PL110_INTCLR_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 INTCLR_UART_DSRMODINT: Clear Data Carrier Detect Int Position */
+#define CMSDK_PL110_INTCLR_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UARTD_SRMODINT: Clear Data Carrier Detect Int Mask */
+
+#define CMSDK_PL110_INTCLR_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 INTCLR_UART_DCDMODINT: Clear Data Set Ready Int Position */
+#define CMSDK_PL110_INTCLR_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_DCDMODINT: Clear Data Set Ready Int Mask */
+
+#define CMSDK_PL110_INTCLR_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 INTCLR_UART_CTSMODINT: Clear Clear To Sent Int Position */
+#define CMSDK_PL110_INTCLR_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_CTSMODINT: Clear Clear To Sent Int Mask */
+
+#define CMSDK_PL110_INTCLR_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 INTCLR_UART_RIMODINT: Clear nUARTRI Modem Int Position */
+#define CMSDK_PL110_INTCLR_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_RIMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_RIMODINT: Clear nUARTRI Modem Int Mask */
+
+#define CMSDK_PL110_DMA_ERR_Pos 2 /*!< CMSDK_PL110 DMA_ERR: DMA Error Position */
+#define CMSDK_PL110_DMA_ERR_Msk (0x1ul << CMSDK_PL110_DMA_ERR_Pos) /*!< CMSDK_PL110 DMA_ERR: DMA Error Mask */
+
+#define CMSDK_PL110_DMA_TRANS_EN_Pos 1 /*!< CMSDK_PL110 DMA_TRANS_EN: DMA Transmit Error Position */
+#define CMSDK_PL110_DMA_TRANS_EN_Msk (0x1ul << CMSDK_PL110_DMA_TRANS_EN_Pos) /*!< CMSDK_PL110 DMA_TRANS_EN: DMA Transmit Error Mask */
+
+#define CMSDK_PL110_DMA_REC_EN_Pos 0 /*!< CMSDK_PL110 DMA_REC_EN: DMA Receive Error Position */
+#define CMSDK_PL110_DMA_REC_EN_Msk (0x1ul << CMSDK_PL110_DMA_REC_EN_Pos) /*!< CMSDK_PL110 DMA_REC_EN: DMA Receive Error Mask */
+
+
+/*@}*/ /* end of group CMSDK_PL110 */
+
+/*------------------- Watchdog ----------------------------------------------*/
+/** @addtogroup CMSDK_Watchdog CMSDK Watchdog
+ @{
+*/
+typedef struct
+{
+
+ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
+ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
+ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
+ // <o.1> RESEN: Reset enable
+ // <o.0> INTEN: Interrupt enable
+ // </h>
+ __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
+ __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
+ __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
+ uint32_t RESERVED0[762];
+ __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
+ uint32_t RESERVED1[191];
+ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
+ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
+}CMSDK_WATCHDOG_TypeDef;
+
+#define CMSDK_Watchdog_LOAD_Pos 0 /*!< CMSDK_Watchdog LOAD: LOAD Position */
+#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /*!< CMSDK_Watchdog LOAD: LOAD Mask */
+
+#define CMSDK_Watchdog_VALUE_Pos 0 /*!< CMSDK_Watchdog VALUE: VALUE Position */
+#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /*!< CMSDK_Watchdog VALUE: VALUE Mask */
+
+#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /*!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
+#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /*!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
+
+#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /*!< CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
+#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /*!< CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
+
+#define CMSDK_Watchdog_INTCLR_Pos 0 /*!< CMSDK_Watchdog INTCLR: Int Clear Position */
+#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /*!< CMSDK_Watchdog INTCLR: Int Clear Mask */
+
+#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /*!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /*!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /*!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /*!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_Watchdog_LOCK_Pos 0 /*!< CMSDK_Watchdog LOCK: LOCK Position */
+#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /*!< CMSDK_Watchdog LOCK: LOCK Mask */
+
+#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /*!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
+#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /*!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
+
+#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /*!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
+#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /*!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
+
+/*@}*/ /* end of group CMSDK_Watchdog */
+
+/*------------------- PrimeCell APB GPIO --------------------------------------*/
+/** @addtogroup CMSDK_PL061 CMSDK APB GPIO
+ @{
+*/
+typedef struct
+{
+
+__IO uint32_t DATA[256];
+__IO uint32_t DIR;
+__IO uint32_t INTSENSE;
+__IO uint32_t INTBOTHEDGE;
+__IO uint32_t INTEVENT;
+__IO uint32_t INTMASK;
+__O uint32_t RAWINTSTAT;
+__O uint32_t MASKINTSTAT;
+__I uint32_t INTCLR;
+__IO uint32_t MODECTRL;
+
+}APBGPIO_TypeDef;
+
+#define CMSDK_PL061_DATA_Pos 0 /*!< CMSDK_PL061 DATA: DATA Position */
+#define CMSDK_PL061_DATA_Msk (0xFFFFFFFFul << CMSDK_PL061_LOAD_Pos) /*!< CMSDK_PL061 DATA: DATA Mask */
+
+#define CMSDK_PL061_DIR_Pos 0 /*!< CMSDK_PL061 DIR: Data Direction Position */
+#define CMSDK_PL061_DIR_Msk (0x1ul << CMSDK_PL061_DIR_Pos) /*!< CMSDK_PL061 DIR: Data Direction Mask */
+
+#define CMSDK_PL061_INTSENSE_Pos 0 /*!< CMSDK_PL061 INTSENSE: INT SENSE Position */
+#define CMSDK_PL061_INTSENSE_Msk (0x1ul << CMSDK_PL061_INTSENSE_Pos) /*!< CMSDK_PL061 INTSENSE: INT SENSE Mask */
+
+#define CMSDK_PL061_INTBOTHEDGE_Pos 0 /*!< CMSDK_PL061 INTBOTHEDGE: INT BOTH EDGE Position */
+#define CMSDK_PL061_INTBOTHEDGE_Msk (0x1ul << CMSDK_PL061_INTBOTHEDGE_Pos) /*!< CMSDK_PL061 INTBOTHEDGE: INT BOTH EDGE Mask */
+
+#define CMSDK_PL061_INTEVENT_Pos 0 /*!< CMSDK_PL061 INTEVENT: INT EVENT Position */
+#define CMSDK_PL061_INTEVENT_Msk (0x1ul << CMSDK_PL061_INTEVENT_Pos) /*!< CMSDK_PL061 INTEVENT: INT EVENT Mask */
+
+#define CMSDK_PL061_INTMASK_Pos 0 /*!< CMSDK_PL061 INTMASK: INT MASK Position */
+#define CMSDK_PL061_INTMASK_Msk (0x1ul << CMSDK_PL061_INTMASK_Pos) /*!< CMSDK_PL061 INTMASK: INT MASK Mask */
+
+#define CMSDK_PL061_RAWINTSTAT_Pos 0 /*!< CMSDK_PL061 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_PL061_RAWINTSTAT_Msk (0x1ul << CMSDK_PL061_RAWINTSTAT_Pos) /*!< CMSDK_PL061 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_PL061_MASKINTSTAT_Pos 0 /*!< CMSDK_PL061 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_PL061_MASKINTSTAT_Msk (0x1ul << CMSDK_PL061_MASKINTSTAT_Pos) /*!< CMSDK_PL061 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_PL061_INTCLR_Pos 0 /*!< CMSDK_PL061 INTCLR: Int Clear Position */
+#define CMSDK_PL061_INTCLR_Msk (0x1ul << CMSDK_PL061_INTCLR_Pos) /*!< CMSDK_PL061 INTCLR: Int Clear Mask */
+
+#define CMSDK_PL061_MODECTRL_HWEN_Pos 0 /*!< CMSDK_PL061 MODECTRL_HWEN: Mode Control Hardware Enable Position */
+#define CMSDK_PL061_MODECTRL_HWEN_Msk (0x1ul << CMSDK_PL061_MODECTRL_HWEN_Pos) /*!< CMSDK_PL061 MODECTRL_HWEN: Mode Control Hardware Enable Mask */
+
+
+/*@}*/ /* end of group CMSDK_PL061 */
+
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/*@}*/ /* end of group CMSDK_CM4_Peripherals */
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/** @addtogroup CMSDK_CM4_MemoryMap CMSDK_CM4 Memory Mapping
+ @{
+*/
+
+/* Peripheral and SRAM base address */
+#define CMSDK_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
+#define CMSDK_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
+#define CMSDK_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
+
+/* Base addresses */
+#define CMSDK_RAM_BASE (0x20000000UL)
+#define CMSDK_APB_BASE (0x40000000UL)
+#define CMSDK_AHB_BASE (0x40010000UL)
+
+/* APB peripherals */
+#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
+#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
+#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
+#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
+#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
+#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
+#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
+#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
+//#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) //only used in extended version
+#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
+#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
+
+/* AHB peripherals */
+#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
+#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
+#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
+#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
+#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
+/*@}*/ /* end of group CMSDK_CM4_MemoryMap */
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+/** @addtogroup CMSDK_CM4_PeripheralDecl CMSDK_CM4 Peripheral Declaration
+ @{
+*/
+
+#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
+#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
+#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
+//#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) //only used in extended version
+#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
+#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
+#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
+#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
+#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
+#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
+#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
+#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
+#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
+#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
+#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
+#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
+/*@}*/ /* end of group CMSDK_CM4_PeripheralDecl */
+
+/*@}*/ /* end of group CMSDK_CM4_Definitions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CMSDK_CM4_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,595 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* File: smm_mps2.h
+* Release: Version 1.0
+*******************************************************************************/
+
+#ifndef __SMM_MPS2_H
+#define __SMM_MPS2_H
+
+#include "peripherallink.h" /* device specific header file */
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/******************************************************************************/
+/* FPGA System Register declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
+ // [31:2] : Reserved
+ // [1:0] : LEDs
+ uint32_t RESERVED1[1];
+ __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
+ // [31:2] : Reserved
+ // [1:0] : Buttons
+ uint32_t RESERVED2[1];
+ __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
+ __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
+ __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
+ // Increments when 32-bit prescale counter reach zero
+ uint32_t RESERVED3[1];
+ __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
+ // Bit[31:0] : reload value for prescale counter
+ __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
+ // current value of the pre-scaler counter
+ // The Cycle Up Counter increment when the prescale down counter reach 0
+ // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+ uint32_t RESERVED4[9];
+ __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
+ // [31:7] : Reserved
+ // [6] : CLCD_BL_CTRL
+ // [5] : CLCD_RD
+ // [4] : CLCD_RS
+ // [3] : CLCD_RESET
+ // [2] : RESERVED
+ // [1] : SPI_nSS
+ // [0] : CLCD_CS
+} MPS2_FPGAIO_TypeDef;
+
+// MISC register bit definitions
+
+#define CLCD_CS_Pos 0
+#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
+#define SPI_nSS_Pos 1
+#define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
+#define CLCD_RESET_Pos 3
+#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
+#define CLCD_RS_Pos 4
+#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
+#define CLCD_RD_Pos 5
+#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
+#define CLCD_BL_Pos 6
+#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
+
+/******************************************************************************/
+/* SCC Register declaration */
+/******************************************************************************/
+
+typedef struct //
+{
+ __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
+ // [31:1] : Reserved
+ // [0] 1 : REMAP BlockRam to ZBT
+ __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
+ // [31:8] : Reserved
+ // [7:0] : MCC LEDs
+ uint32_t RESERVED0[1];
+ __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
+ // [31:8] : Reserved
+ // [7:0] : These bits indicate state of the MCC switches
+ __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
+ // [31:4] : Reserved
+ // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
+ uint32_t RESERVED1[35];
+ __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
+ // [31:0] : Data
+ __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
+ // [31:0] : Data
+ __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
+ // [31] : Start (generates interrupt on write to this bit)
+ // [30] : R/W access
+ // [29:26] : Reserved
+ // [25:20] : Function value
+ // [19:12] : Reserved
+ // [11:0] : Device (value of 0/1/2 for supported clocks)
+ __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
+ // [31:2] : Reserved
+ // [1] : Error
+ // [0] : Complete
+ __IO uint32_t RESERVED2[20];
+ __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
+ // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
+ // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
+ // [15:1] : Reserved
+ // [0] : This bit indicates if all enabled DLLs are locked
+ uint32_t RESERVED3[957];
+ __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
+ // [31:24] : FPGA build number
+ // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
+ // [19:11] : Reserved
+ // [10] : if “1” SCC_SW register has been implemented
+ // [9] : if “1” SCC_LED register has been implemented
+ // [8] : if “1” DLL lock register has been implemented
+ // [7:0] : number of SCC configuration register
+ __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
+ // [31:24] : Implementer ID: 0x41 = ARM
+ // [23:20] : Application note IP variant number
+ // [19:16] : IP Architecture: 0x4 =AHB
+ // [15:4] : Primary part number: 386 = AN386
+ // [3:0] : Application note IP revision number
+} MPS2_SCC_TypeDef;
+
+
+/******************************************************************************/
+/* SSP Peripheral declaration */
+/******************************************************************************/
+
+typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
+{
+ __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
+ // [31:16] : Reserved
+ // [15:8] : Serial clock rate
+ // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
+ // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
+ // [5:4] : Frame format
+ // [3:0] : Data Size Select
+ __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
+ // [31:4] : Reserved
+ // [3] : Slave-mode output disable
+ // [2] : Master or slave mode select
+ // [1] : Synchronous serial port enable
+ // [0] : Loop back mode
+ __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
+ // [31:16] : Reserved
+ // [15:0] : Transmit/Receive FIFO
+ __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
+ // [31:5] : Reserved
+ // [4] : PrimeCell SSP busy flag
+ // [3] : Receive FIFO full
+ // [2] : Receive FIFO not empty
+ // [1] : Transmit FIFO not full
+ // [0] : Transmit FIFO empty
+ __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
+ // [31:8] : Reserved
+ // [8:0] : Clock prescale divisor
+ __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
+ // [31:4] : Reserved
+ // [3] : Transmit FIFO interrupt mask
+ // [2] : Receive FIFO interrupt mask
+ // [1] : Receive timeout interrupt mask
+ // [0] : Receive overrun interrupt mask
+ __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
+ // [31:4] : Reserved
+ // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
+ // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
+ // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
+ // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
+ __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
+ // [31:4] : Reserved
+ // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
+ // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
+ // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
+ // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
+ __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
+ // [31:2] : Reserved
+ // [1] : Clears the SSPRTINTR interrupt
+ // [0] : Clears the SSPRORINTR interrupt
+ __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
+ // [31:2] : Reserved
+ // [1] : Transmit DMA Enable
+ // [0] : Receive DMA Enable
+} MPS2_SSP_TypeDef;
+
+
+// SSP_CR0 Control register 0
+#define SSP_CR0_DSS_Pos 0 // Data Size Select
+#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
+#define SSP_CR0_FRF_Pos 4 // Frame Format Select
+#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
+#define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
+#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
+#define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
+#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
+#define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
+#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
+
+#define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
+#define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
+#define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
+#define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
+
+// SSP_CR1 Control register 1
+#define SSP_CR1_LBM_Pos 0 // Loop Back Mode
+#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
+#define SSP_CR1_SSE_Pos 1 // Serial port enable
+#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
+#define SSP_CR1_MS_Pos 2 // Master or Slave mode
+#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
+#define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
+#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
+
+// SSP_SR Status register
+#define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
+#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
+#define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
+#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
+#define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
+#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
+#define SSP_SR_RFF_Pos 3 // Receive FIFO full
+#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
+#define SSP_SR_BSY_Pos 4 // Busy
+#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
+
+// SSP_CPSR Clock prescale register
+#define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
+#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
+
+#define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
+
+// SSPIMSC Interrupt mask set and clear register
+#define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
+#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
+#define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
+#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
+#define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
+#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
+#define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
+#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
+
+// SSPRIS Raw interrupt status register
+#define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
+#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
+#define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
+#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
+#define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
+#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
+#define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
+#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
+
+// SSPMIS Masked interrupt status register
+#define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
+#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
+#define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
+#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
+#define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
+#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
+#define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
+#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
+
+// SSPICR Interrupt clear register
+#define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
+#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
+#define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
+#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
+
+// SSPDMACR DMA control register
+#define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
+#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
+#define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
+#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
+
+/******************************************************************************/
+/* Audio and Touch Screen (I2C) Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ union {
+ __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
+ __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
+ };
+ __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
+} MPS2_I2C_TypeDef;
+
+#define SDA 1 << 1
+#define SCL 1 << 0
+
+
+/******************************************************************************/
+/* Audio I2S Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ /*!< Offset: 0x000 CONTROL Register (R/W) */
+ __IO uint32_t CONTROL; // <h> CONTROL </h>
+ // <o.0> TX Enable
+ // <0=> TX disabled
+ // <1=> TX enabled
+ // <o.1> TX IRQ Enable
+ // <0=> TX IRQ disabled
+ // <1=> TX IRQ enabled
+ // <o.2> RX Enable
+ // <0=> RX disabled
+ // <1=> RX enabled
+ // <o.3> RX IRQ Enable
+ // <0=> RX IRQ disabled
+ // <1=> RX IRQ enabled
+ // <o.10..8> TX Buffer Water Level
+ // <0=> / IRQ triggers when any space available
+ // <1=> / IRQ triggers when more than 1 space available
+ // <2=> / IRQ triggers when more than 2 space available
+ // <3=> / IRQ triggers when more than 3 space available
+ // <4=> Undefined!
+ // <5=> Undefined!
+ // <6=> Undefined!
+ // <7=> Undefined!
+ // <o.14..12> RX Buffer Water Level
+ // <0=> Undefined!
+ // <1=> / IRQ triggers when less than 1 space available
+ // <2=> / IRQ triggers when less than 2 space available
+ // <3=> / IRQ triggers when less than 3 space available
+ // <4=> / IRQ triggers when less than 4 space available
+ // <5=> Undefined!
+ // <6=> Undefined!
+ // <7=> Undefined!
+ // <o.16> FIFO reset
+ // <0=> Normal operation
+ // <1=> FIFO reset
+ // <o.17> Audio Codec reset
+ // <0=> Normal operation
+ // <1=> Assert audio Codec reset
+ /*!< Offset: 0x004 STATUS Register (R/ ) */
+ __I uint32_t STATUS; // <h> STATUS </h>
+ // <o.0> TX Buffer alert
+ // <0=> TX buffer don't need service yet
+ // <1=> TX buffer need service
+ // <o.1> RX Buffer alert
+ // <0=> RX buffer don't need service yet
+ // <1=> RX buffer need service
+ // <o.2> TX Buffer Empty
+ // <0=> TX buffer have data
+ // <1=> TX buffer empty
+ // <o.3> TX Buffer Full
+ // <0=> TX buffer not full
+ // <1=> TX buffer full
+ // <o.4> RX Buffer Empty
+ // <0=> RX buffer have data
+ // <1=> RX buffer empty
+ // <o.5> RX Buffer Full
+ // <0=> RX buffer not full
+ // <1=> RX buffer full
+ union {
+ /*!< Offset: 0x008 Error Status Register (R/ ) */
+ __I uint32_t ERROR; // <h> ERROR </h>
+ // <o.0> TX error
+ // <0=> Okay
+ // <1=> TX overrun/underrun
+ // <o.1> RX error
+ // <0=> Okay
+ // <1=> RX overrun/underrun
+ /*!< Offset: 0x008 Error Clear Register ( /W) */
+ __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
+ // <o.0> TX error
+ // <0=> Okay
+ // <1=> Clear TX error
+ // <o.1> RX error
+ // <0=> Okay
+ // <1=> Clear RX error
+ };
+ /*!< Offset: 0x00C Divide ratio Register (R/W) */
+ __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
+ // <o.9..0> TX error (default 0x80)
+ /*!< Offset: 0x010 Transmit Buffer ( /W) */
+ __O uint32_t TXBUF; // <h> Transmit buffer </h>
+ // <o.15..0> Right channel
+ // <o.31..16> Left channel
+ /*!< Offset: 0x014 Receive Buffer (R/ ) */
+ __I uint32_t RXBUF; // <h> Receive buffer </h>
+ // <o.15..0> Right channel
+ // <o.31..16> Left channel
+ uint32_t RESERVED1[186];
+ __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
+ // <o.0> ITEN
+ // <0=> Normal operation
+ // <1=> Integration Test mode enable
+ __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
+ // <o.0> SDIN
+ __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
+ // <o.0> SDOUT
+ // <o.1> SCLK
+ // <o.2> LRCK
+ // <o.3> IRQOUT
+} MPS2_I2S_TypeDef;
+
+#define I2S_CONTROL_TXEN_Pos 0
+#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
+
+#define I2S_CONTROL_TXIRQEN_Pos 1
+#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
+
+#define I2S_CONTROL_RXEN_Pos 2
+#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
+
+#define I2S_CONTROL_RXIRQEN_Pos 3
+#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
+
+#define I2S_CONTROL_TXWLVL_Pos 8
+#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
+
+#define I2S_CONTROL_RXWLVL_Pos 12
+#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
+/* FIFO reset*/
+#define I2S_CONTROL_FIFORST_Pos 16
+#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
+/* Codec reset*/
+#define I2S_CONTROL_CODECRST_Pos 17
+#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
+
+#define I2S_STATUS_TXIRQ_Pos 0
+#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
+
+#define I2S_STATUS_RXIRQ_Pos 1
+#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
+
+#define I2S_STATUS_TXEmpty_Pos 2
+#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
+
+#define I2S_STATUS_TXFull_Pos 3
+#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
+
+#define I2S_STATUS_RXEmpty_Pos 4
+#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
+
+#define I2S_STATUS_RXFull_Pos 5
+#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
+
+#define I2S_ERROR_TXERR_Pos 0
+#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
+
+#define I2S_ERROR_RXERR_Pos 1
+#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
+
+/******************************************************************************/
+/* SMSC9220 Register Definitions */
+/******************************************************************************/
+
+typedef struct // SMSC LAN9220
+{
+__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
+ uint32_t RESERVED1[0x7];
+__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
+ uint32_t RESERVED2[0x7];
+
+__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
+__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
+__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
+__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
+
+__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
+__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
+__IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
+__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
+ uint32_t RESERVED3; // Reserved for future use (offset 0x60)
+__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
+__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
+__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
+__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
+__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
+__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
+__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
+__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
+__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
+__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
+__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
+__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
+ uint32_t RESERVED4; // Reserved for future use (offset 0x94)
+__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
+__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
+__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
+__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
+__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
+__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
+__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
+__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
+
+} SMSC9220_TypeDef;
+
+// SMSC9220 MAC Registers Indices
+#define SMSC9220_MAC_CR 0x1
+#define SMSC9220_MAC_ADDRH 0x2
+#define SMSC9220_MAC_ADDRL 0x3
+#define SMSC9220_MAC_HASHH 0x4
+#define SMSC9220_MAC_HASHL 0x5
+#define SMSC9220_MAC_MII_ACC 0x6
+#define SMSC9220_MAC_MII_DATA 0x7
+#define SMSC9220_MAC_FLOW 0x8
+#define SMSC9220_MAC_VLAN1 0x9
+#define SMSC9220_MAC_VLAN2 0xA
+#define SMSC9220_MAC_WUFF 0xB
+#define SMSC9220_MAC_WUCSR 0xC
+
+// SMSC9220 PHY Registers Indices
+#define SMSC9220_PHY_BCONTROL 0x0
+#define SMSC9220_PHY_BSTATUS 0x1
+#define SMSC9220_PHY_ID1 0x2
+#define SMSC9220_PHY_ID2 0x3
+#define SMSC9220_PHY_ANEG_ADV 0x4
+#define SMSC9220_PHY_ANEG_LPA 0x5
+#define SMSC9220_PHY_ANEG_EXP 0x6
+#define SMSC9220_PHY_MCONTROL 0x17
+#define SMSC9220_PHY_MSTATUS 0x18
+#define SMSC9220_PHY_CSINDICATE 0x27
+#define SMSC9220_PHY_INTSRC 0x29
+#define SMSC9220_PHY_INTMASK 0x30
+#define SMSC9220_PHY_CS 0x31
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+
+#define MPS2_SSP1_BASE (0x40020000ul) /* User SSP Base Address */
+#define MPS2_SSP0_BASE (0x40021000ul) /* CLCD SSP Base Address */
+#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
+#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
+#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
+#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
+#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
+
+#ifdef CORTEX_M7
+#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
+#else
+#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
+#endif
+
+#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
+#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+
+#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
+#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
+#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
+#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
+#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
+#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
+#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
+#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
+
+/******************************************************************************/
+/* General Function Definitions */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/* General MACRO Definitions */
+/******************************************************************************/
+
+
+
+#endif /* __SMM_MPS2_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,47 @@
+;* MPS2 CMSIS Library
+;*
+;* Copyright (c) 2006-2015 ARM Limited
+;* All rights reserved.
+;*
+;* Redistribution and use in source and binary forms, with or without
+;* modification, are permitted provided that the following conditions are met:
+;*
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;*
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;*
+;* 3. Neither the name of the copyright holder nor the names of its contributors
+;* may be used to endorse or promote products derived from this software without
+;* specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
+;*
+; *************************************************************
+; *** Scatter-Loading Description File ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00400000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/startup_MPS2.s Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,293 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2015 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM4.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM4 Device +; @version V3.03 +; @date 04. February 2015 +; +; @note +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler + DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler + DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler + DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler + DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler + DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler + DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler + DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler + DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + EXPORT PORT0_8_Handler [WEAK] + EXPORT PORT0_9_Handler [WEAK] + EXPORT PORT0_10_Handler [WEAK] + EXPORT PORT0_11_Handler [WEAK] + EXPORT PORT0_12_Handler [WEAK] + EXPORT PORT0_13_Handler [WEAK] + EXPORT PORT0_14_Handler [WEAK] + EXPORT PORT0_15_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler +PORT0_8_Handler +PORT0_9_Handler +PORT0_10_Handler +PORT0_11_Handler +PORT0_12_Handler +PORT0_13_Handler +PORT0_14_Handler +PORT0_15_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,42 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in MPS2 specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_CM4.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,58 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* CMSIS-style functionality to support dynamic vectors
+*******************************************************************************/
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,54 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* CMSIS-style functionality to support dynamic vectors
+*******************************************************************************/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/peripherallink.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,53 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* Name: Device.h +* Purpose: Include the correct device header file +*******************************************************************************/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_CM0 + #include "CMSDK_CM0.h" /* device specific header file */ +#elif defined CMSDK_CM0plus + #include "CMSDK_CM0plus.h" /* device specific header file */ +#elif defined CMSDK_CM3 + #include "CMSDK_CM3.h" /* device specific header file */ +#elif defined CMSDK_CM4 + #include "CMSDK_CM4.h" /* device specific header file */ +#elif defined CMSDK_CM7 + #include "CMSDK_CM7.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,101 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* @file system_CMSDK_CM4.c
+* @brief CMSIS Device System Source File for
+* CMSDK_M4 Device
+* @version V3.02
+* @date 15. November 2013
+*
+* @note
+*
+*******************************************************************************/
+
+
+
+#include "CMSDK_CM4.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (50000000UL) /* Oscillator frequency */
+
+#define __SYSTEM_CLOCK (__XTAL / 2)
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate (void)
+{
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+ #if (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
+ (3UL << 11*2) ); /* set CP11 Full Access */
+ #endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,80 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+*******************************************************************************
+* @file system_CMSDK_CM4.h
+* @brief CMSIS Device Peripheral Access Layer Header File for
+* CMSDK_CM4 Device
+* @version V3.02
+* @date 15. March 2013
+*
+* @note
+*
+******************************************************************************/
+
+
+#ifndef SYSTEM_CMSDK_CM4_H
+#define SYSTEM_CMSDK_CM4_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CMSDK_CM4_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,733 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* @file CMSDK_CM7.h
+* @brief CMSIS Core Peripheral Access Layer Header File for
+* CMSDK_CM7 Device
+* @version V1.00
+* @date 27. August 2014
+*
+* @note configured for CM7 without FPU
+*
+*******************************************************************************/
+
+
+#ifndef CMSDK_CM7_H
+#define CMSDK_CM7_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/* ------------------- CM7 Processor Exceptions Numbers --------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+// HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
+
+/* ---------------------- CMSDK_CM7 Specific Interrupt Numbers -------------- */
+ UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
+ UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
+ UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
+ UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
+ UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
+ UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
+ PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */
+ PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */
+ TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
+ TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
+ DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
+ SPI_IRQn = 11, /* SPI Interrupt */
+ UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
+ ETHERNET_IRQn = 13, /* Ethernet Interrupt */
+ I2S_IRQn = 14, /* I2S Interrupt */
+ TSC_IRQn = 15, /* Touch Screen Interrupt */
+// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
+ PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
+ PORT0_1_IRQn = 17, /* There are 16 pins in total */
+ PORT0_2_IRQn = 18,
+ PORT0_3_IRQn = 19,
+ PORT0_4_IRQn = 20,
+ PORT0_5_IRQn = 21,
+ PORT0_6_IRQn = 22,
+ PORT0_7_IRQn = 23,
+ PORT0_8_IRQn = 24,
+ PORT0_9_IRQn = 25,
+ PORT0_10_IRQn = 26,
+ PORT0_11_IRQn = 27,
+ PORT0_12_IRQn = 28,
+ PORT0_13_IRQn = 29,
+ PORT0_14_IRQn = 30,
+ PORT0_15_IRQn = 31,
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* -------- Configuration of the CM7 Processor and Core Peripherals --------- */
+#define __CM4_REV 0x0000 /* Core revision r0p0 */
+#define __MPU_PRESENT 1 /* MPU present or not */
+#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /* no FPU present */
+#define __FPU_DP 1 /* unused */
+#define __ICACHE_PRESENT 1
+#define __DCACHE_PRESENT 1
+
+#include "core_CM7.h" /* Processor and core peripherals */
+#include "system_CMSDK_CM7.h" /* System Header */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
+ __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
+ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
+ };
+ __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
+
+} CMSDK_UART_TypeDef;
+
+/* CMSDK_UART DATA Register Definitions */
+
+#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
+#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
+
+#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
+#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
+
+#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
+#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
+
+#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
+#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
+
+#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
+#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
+
+#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
+#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
+
+#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
+#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
+#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
+#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
+#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
+#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
+
+#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
+#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
+
+#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
+#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
+#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
+#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
+#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
+
+#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
+#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
+
+
+/*----------------------------- Timer (TIMER) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
+ __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
+ };
+
+} CMSDK_TIMER_TypeDef;
+
+/* CMSDK_TIMER CTRL Register Definitions */
+
+#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
+#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
+
+#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
+#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
+
+#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
+#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
+
+#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
+#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
+
+#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
+#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
+
+#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
+#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
+
+#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
+#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
+
+#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
+#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
+
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
+ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
+ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
+ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
+ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
+ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
+ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
+ uint32_t RESERVED0;
+ __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
+ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
+ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
+ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
+ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
+ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
+ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
+ uint32_t RESERVED1[945];
+ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
+ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
+} CMSDK_DUALTIMER_BOTH_TypeDef;
+
+#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
+#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
+#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
+
+#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
+#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
+#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
+
+
+typedef struct
+{
+ __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
+ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
+ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
+ __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
+ __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
+ __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
+ __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
+} CMSDK_DUALTIMER_SINGLE_TypeDef;
+
+#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
+#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
+
+#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
+#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
+#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
+
+#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
+#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
+#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
+
+#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
+#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
+#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
+
+#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
+#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
+
+#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
+#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
+
+#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
+#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
+
+
+/*-------------------- General Purpose Input Output (GPIO) -------------------*/
+typedef struct
+{
+ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
+ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
+ __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
+ __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
+ __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
+ __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
+ __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
+ __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
+ __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
+ __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
+ __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
+ union {
+ __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
+ };
+ uint32_t RESERVED1[241];
+ __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
+ __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
+} CMSDK_GPIO_TypeDef;
+
+#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
+#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
+
+#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
+#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
+
+#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
+#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
+
+#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
+#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
+
+#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
+#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
+
+#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
+#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
+
+#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
+#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
+
+#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
+#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
+
+#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
+#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
+
+#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
+#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
+
+#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
+#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
+
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+typedef struct
+{
+ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
+ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
+ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
+ __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
+ __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
+} CMSDK_SYSCON_TypeDef;
+
+#define CMSDK_SYSCON_REMAP_Pos 0
+#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
+
+#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
+#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
+
+#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
+#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
+#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
+#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
+#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
+
+#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
+#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
+
+#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
+#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
+
+#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
+#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
+
+#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
+#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
+
+
+/*------------- PL230 uDMA (PL230) --------------------------------------*/
+typedef struct
+{
+ __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
+ __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
+ __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
+ __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
+ __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
+ __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
+ __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
+ __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
+ __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
+ __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
+ __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
+ __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
+ __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
+ __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
+ __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
+ __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
+ uint32_t RESERVED0[3];
+ __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
+
+} CMSDK_PL230_TypeDef;
+
+#define PL230_DMA_CHNL_BITS 0
+
+#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
+#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
+#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
+
+#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
+#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
+
+#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
+#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
+
+#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
+#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
+#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
+#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
+
+#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
+#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
+
+#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
+#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
+
+#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
+#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
+
+#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
+#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
+
+#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
+#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
+
+#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
+#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
+
+#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
+#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
+
+#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
+#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
+
+#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
+#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
+
+#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
+#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
+
+#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
+#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
+
+#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
+#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
+
+#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
+#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
+
+#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
+#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
+
+#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
+#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
+
+#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
+#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
+
+
+/*------------------- Watchdog ----------------------------------------------*/
+typedef struct
+{
+
+ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
+ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
+ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
+ __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
+ __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
+ __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
+ uint32_t RESERVED0[762];
+ __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
+ uint32_t RESERVED1[191];
+ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
+ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
+}CMSDK_WATCHDOG_TypeDef;
+
+#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
+#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
+
+#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
+#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
+
+#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
+#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
+
+#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
+#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
+
+#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
+#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
+
+#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
+#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
+
+#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
+#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
+
+#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
+#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
+
+#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
+#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
+
+#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
+#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
+
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+/* Peripheral and SRAM base address */
+#define CMSDK_FLASH_BASE (0x00000000UL)
+#define CMSDK_SRAM_BASE (0x20000000UL)
+#define CMSDK_PERIPH_BASE (0x40000000UL)
+
+#define CMSDK_RAM_BASE (0x20000000UL)
+#define CMSDK_APB_BASE (0x40000000UL)
+#define CMSDK_AHB_BASE (0x40010000UL)
+
+/* APB peripherals */
+#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
+#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
+#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
+#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
+#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
+#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
+#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
+#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
+#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
+#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
+
+/* AHB peripherals */
+#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
+#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
+#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
+#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
+#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
+#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
+#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
+#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
+#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
+#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
+#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
+#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
+#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
+#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
+#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
+#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
+#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
+#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
+#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CMSDK_CM7_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,591 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* File: smm_mps2.h
+* Release: Version 1.0
+*******************************************************************************/
+
+#ifndef __SMM_MPS2_H
+#define __SMM_MPS2_H
+
+#include "peripherallink.h" /* device specific header file */
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/******************************************************************************/
+/* FPGA System Register declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
+ // [31:2] : Reserved
+ // [1:0] : LEDs
+ uint32_t RESERVED1[1];
+ __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
+ // [31:2] : Reserved
+ // [1:0] : Buttons
+ uint32_t RESERVED2[1];
+ __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
+ __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
+ __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
+ // Increments when 32-bit prescale counter reach zero
+ uint32_t RESERVED3[1];
+ __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
+ // Bit[31:0] : reload value for prescale counter
+ __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
+ // current value of the pre-scaler counter
+ // The Cycle Up Counter increment when the prescale down counter reach 0
+ // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+ uint32_t RESERVED4[9];
+ __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
+ // [31:7] : Reserved
+ // [6] : CLCD_BL_CTRL
+ // [5] : CLCD_RD
+ // [4] : CLCD_RS
+ // [3] : CLCD_RESET
+ // [2] : RESERVED
+ // [1] : SPI_nSS
+ // [0] : CLCD_CS
+} MPS2_FPGAIO_TypeDef;
+
+// MISC register bit definitions
+
+#define CLCD_CS_Pos 0
+#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
+#define SPI_nSS_Pos 1
+#define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
+#define CLCD_RESET_Pos 3
+#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
+#define CLCD_RS_Pos 4
+#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
+#define CLCD_RD_Pos 5
+#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
+#define CLCD_BL_Pos 6
+#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
+
+/******************************************************************************/
+/* SCC Register declaration */
+/******************************************************************************/
+
+typedef struct //
+{
+ __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
+ // [31:1] : Reserved
+ // [0] 1 : REMAP BlockRam to ZBT
+ __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
+ // [31:8] : Reserved
+ // [7:0] : MCC LEDs
+ uint32_t RESERVED0[1];
+ __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
+ // [31:8] : Reserved
+ // [7:0] : These bits indicate state of the MCC switches
+ __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
+ // [31:4] : Reserved
+ // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
+ uint32_t RESERVED1[35];
+ __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
+ // [31:0] : Data
+ __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
+ // [31:0] : Data
+ __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
+ // [31] : Start (generates interrupt on write to this bit)
+ // [30] : R/W access
+ // [29:26] : Reserved
+ // [25:20] : Function value
+ // [19:12] : Reserved
+ // [11:0] : Device (value of 0/1/2 for supported clocks)
+ __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
+ // [31:2] : Reserved
+ // [1] : Error
+ // [0] : Complete
+ __IO uint32_t RESERVED2[20];
+ __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
+ // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
+ // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
+ // [15:1] : Reserved
+ // [0] : This bit indicates if all enabled DLLs are locked
+ uint32_t RESERVED3[957];
+ __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
+ // [31:24] : FPGA build number
+ // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
+ // [19:11] : Reserved
+ // [10] : if “1” SCC_SW register has been implemented
+ // [9] : if “1” SCC_LED register has been implemented
+ // [8] : if “1” DLL lock register has been implemented
+ // [7:0] : number of SCC configuration register
+ __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
+ // [31:24] : Implementer ID: 0x41 = ARM
+ // [23:20] : Application note IP variant number
+ // [19:16] : IP Architecture: 0x4 =AHB
+ // [15:4] : Primary part number: 386 = AN386
+ // [3:0] : Application note IP revision number
+} MPS2_SCC_TypeDef;
+
+
+/******************************************************************************/
+/* SSP Peripheral declaration */
+/******************************************************************************/
+
+typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
+{
+ __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
+ // [31:16] : Reserved
+ // [15:8] : Serial clock rate
+ // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
+ // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
+ // [5:4] : Frame format
+ // [3:0] : Data Size Select
+ __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
+ // [31:4] : Reserved
+ // [3] : Slave-mode output disable
+ // [2] : Master or slave mode select
+ // [1] : Synchronous serial port enable
+ // [0] : Loop back mode
+ __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
+ // [31:16] : Reserved
+ // [15:0] : Transmit/Receive FIFO
+ __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
+ // [31:5] : Reserved
+ // [4] : PrimeCell SSP busy flag
+ // [3] : Receive FIFO full
+ // [2] : Receive FIFO not empty
+ // [1] : Transmit FIFO not full
+ // [0] : Transmit FIFO empty
+ __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
+ // [31:8] : Reserved
+ // [8:0] : Clock prescale divisor
+ __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
+ // [31:4] : Reserved
+ // [3] : Transmit FIFO interrupt mask
+ // [2] : Receive FIFO interrupt mask
+ // [1] : Receive timeout interrupt mask
+ // [0] : Receive overrun interrupt mask
+ __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
+ // [31:4] : Reserved
+ // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
+ // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
+ // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
+ // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
+ __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
+ // [31:4] : Reserved
+ // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
+ // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
+ // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
+ // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
+ __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
+ // [31:2] : Reserved
+ // [1] : Clears the SSPRTINTR interrupt
+ // [0] : Clears the SSPRORINTR interrupt
+ __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
+ // [31:2] : Reserved
+ // [1] : Transmit DMA Enable
+ // [0] : Receive DMA Enable
+} MPS2_SSP_TypeDef;
+
+
+// SSP_CR0 Control register 0
+#define SSP_CR0_DSS_Pos 0 // Data Size Select
+#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
+#define SSP_CR0_FRF_Pos 4 // Frame Format Select
+#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
+#define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
+#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
+#define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
+#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
+#define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
+#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
+
+#define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
+#define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
+#define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
+#define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
+
+// SSP_CR1 Control register 1
+#define SSP_CR1_LBM_Pos 0 // Loop Back Mode
+#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
+#define SSP_CR1_SSE_Pos 1 // Serial port enable
+#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
+#define SSP_CR1_MS_Pos 2 // Master or Slave mode
+#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
+#define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
+#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
+
+// SSP_SR Status register
+#define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
+#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
+#define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
+#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
+#define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
+#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
+#define SSP_SR_RFF_Pos 3 // Receive FIFO full
+#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
+#define SSP_SR_BSY_Pos 4 // Busy
+#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
+
+// SSP_CPSR Clock prescale register
+#define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
+#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
+
+#define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
+
+// SSPIMSC Interrupt mask set and clear register
+#define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
+#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
+#define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
+#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
+#define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
+#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
+#define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
+#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
+
+// SSPRIS Raw interrupt status register
+#define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
+#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
+#define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
+#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
+#define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
+#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
+#define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
+#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
+
+// SSPMIS Masked interrupt status register
+#define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
+#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
+#define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
+#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
+#define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
+#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
+#define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
+#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
+
+// SSPICR Interrupt clear register
+#define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
+#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
+#define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
+#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
+
+// SSPDMACR DMA control register
+#define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
+#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
+#define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
+#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
+
+/******************************************************************************/
+/* Audio and Touch Screen (I2C) Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ union {
+ __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
+ __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
+ };
+ __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
+} MPS2_I2C_TypeDef;
+
+#define SDA 1 << 1
+#define SCL 1 << 0
+
+
+/******************************************************************************/
+/* Audio I2S Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ /*!< Offset: 0x000 CONTROL Register (R/W) */
+ __IO uint32_t CONTROL; // <h> CONTROL </h>
+ // <o.0> TX Enable
+ // <0=> TX disabled
+ // <1=> TX enabled
+ // <o.1> TX IRQ Enable
+ // <0=> TX IRQ disabled
+ // <1=> TX IRQ enabled
+ // <o.2> RX Enable
+ // <0=> RX disabled
+ // <1=> RX enabled
+ // <o.3> RX IRQ Enable
+ // <0=> RX IRQ disabled
+ // <1=> RX IRQ enabled
+ // <o.10..8> TX Buffer Water Level
+ // <0=> / IRQ triggers when any space available
+ // <1=> / IRQ triggers when more than 1 space available
+ // <2=> / IRQ triggers when more than 2 space available
+ // <3=> / IRQ triggers when more than 3 space available
+ // <4=> Undefined!
+ // <5=> Undefined!
+ // <6=> Undefined!
+ // <7=> Undefined!
+ // <o.14..12> RX Buffer Water Level
+ // <0=> Undefined!
+ // <1=> / IRQ triggers when less than 1 space available
+ // <2=> / IRQ triggers when less than 2 space available
+ // <3=> / IRQ triggers when less than 3 space available
+ // <4=> / IRQ triggers when less than 4 space available
+ // <5=> Undefined!
+ // <6=> Undefined!
+ // <7=> Undefined!
+ // <o.16> FIFO reset
+ // <0=> Normal operation
+ // <1=> FIFO reset
+ // <o.17> Audio Codec reset
+ // <0=> Normal operation
+ // <1=> Assert audio Codec reset
+ /*!< Offset: 0x004 STATUS Register (R/ ) */
+ __I uint32_t STATUS; // <h> STATUS </h>
+ // <o.0> TX Buffer alert
+ // <0=> TX buffer don't need service yet
+ // <1=> TX buffer need service
+ // <o.1> RX Buffer alert
+ // <0=> RX buffer don't need service yet
+ // <1=> RX buffer need service
+ // <o.2> TX Buffer Empty
+ // <0=> TX buffer have data
+ // <1=> TX buffer empty
+ // <o.3> TX Buffer Full
+ // <0=> TX buffer not full
+ // <1=> TX buffer full
+ // <o.4> RX Buffer Empty
+ // <0=> RX buffer have data
+ // <1=> RX buffer empty
+ // <o.5> RX Buffer Full
+ // <0=> RX buffer not full
+ // <1=> RX buffer full
+ union {
+ /*!< Offset: 0x008 Error Status Register (R/ ) */
+ __I uint32_t ERROR; // <h> ERROR </h>
+ // <o.0> TX error
+ // <0=> Okay
+ // <1=> TX overrun/underrun
+ // <o.1> RX error
+ // <0=> Okay
+ // <1=> RX overrun/underrun
+ /*!< Offset: 0x008 Error Clear Register ( /W) */
+ __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
+ // <o.0> TX error
+ // <0=> Okay
+ // <1=> Clear TX error
+ // <o.1> RX error
+ // <0=> Okay
+ // <1=> Clear RX error
+ };
+ /*!< Offset: 0x00C Divide ratio Register (R/W) */
+ __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
+ // <o.9..0> TX error (default 0x80)
+ /*!< Offset: 0x010 Transmit Buffer ( /W) */
+ __O uint32_t TXBUF; // <h> Transmit buffer </h>
+ // <o.15..0> Right channel
+ // <o.31..16> Left channel
+ /*!< Offset: 0x014 Receive Buffer (R/ ) */
+ __I uint32_t RXBUF; // <h> Receive buffer </h>
+ // <o.15..0> Right channel
+ // <o.31..16> Left channel
+ uint32_t RESERVED1[186];
+ __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
+ // <o.0> ITEN
+ // <0=> Normal operation
+ // <1=> Integration Test mode enable
+ __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
+ // <o.0> SDIN
+ __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
+ // <o.0> SDOUT
+ // <o.1> SCLK
+ // <o.2> LRCK
+ // <o.3> IRQOUT
+} MPS2_I2S_TypeDef;
+
+#define I2S_CONTROL_TXEN_Pos 0
+#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
+
+#define I2S_CONTROL_TXIRQEN_Pos 1
+#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
+
+#define I2S_CONTROL_RXEN_Pos 2
+#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
+
+#define I2S_CONTROL_RXIRQEN_Pos 3
+#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
+
+#define I2S_CONTROL_TXWLVL_Pos 8
+#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
+
+#define I2S_CONTROL_RXWLVL_Pos 12
+#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
+/* FIFO reset*/
+#define I2S_CONTROL_FIFORST_Pos 16
+#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
+/* Codec reset*/
+#define I2S_CONTROL_CODECRST_Pos 17
+#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
+
+#define I2S_STATUS_TXIRQ_Pos 0
+#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
+
+#define I2S_STATUS_RXIRQ_Pos 1
+#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
+
+#define I2S_STATUS_TXEmpty_Pos 2
+#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
+
+#define I2S_STATUS_TXFull_Pos 3
+#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
+
+#define I2S_STATUS_RXEmpty_Pos 4
+#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
+
+#define I2S_STATUS_RXFull_Pos 5
+#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
+
+#define I2S_ERROR_TXERR_Pos 0
+#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
+
+#define I2S_ERROR_RXERR_Pos 1
+#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
+
+/******************************************************************************/
+/* SMSC9220 Register Definitions */
+/******************************************************************************/
+
+typedef struct // SMSC LAN9220
+{
+__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
+ uint32_t RESERVED1[0x7];
+__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
+ uint32_t RESERVED2[0x7];
+
+__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
+__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
+__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
+__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
+
+__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
+__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
+__IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
+__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
+ uint32_t RESERVED3; // Reserved for future use (offset 0x60)
+__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
+__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
+__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
+__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
+__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
+__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
+__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
+__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
+__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
+__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
+__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
+__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
+ uint32_t RESERVED4; // Reserved for future use (offset 0x94)
+__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
+__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
+__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
+__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
+__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
+__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
+__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
+__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
+
+} SMSC9220_TypeDef;
+
+// SMSC9220 MAC Registers Indices
+#define SMSC9220_MAC_CR 0x1
+#define SMSC9220_MAC_ADDRH 0x2
+#define SMSC9220_MAC_ADDRL 0x3
+#define SMSC9220_MAC_HASHH 0x4
+#define SMSC9220_MAC_HASHL 0x5
+#define SMSC9220_MAC_MII_ACC 0x6
+#define SMSC9220_MAC_MII_DATA 0x7
+#define SMSC9220_MAC_FLOW 0x8
+#define SMSC9220_MAC_VLAN1 0x9
+#define SMSC9220_MAC_VLAN2 0xA
+#define SMSC9220_MAC_WUFF 0xB
+#define SMSC9220_MAC_WUCSR 0xC
+
+// SMSC9220 PHY Registers Indices
+#define SMSC9220_PHY_BCONTROL 0x0
+#define SMSC9220_PHY_BSTATUS 0x1
+#define SMSC9220_PHY_ID1 0x2
+#define SMSC9220_PHY_ID2 0x3
+#define SMSC9220_PHY_ANEG_ADV 0x4
+#define SMSC9220_PHY_ANEG_LPA 0x5
+#define SMSC9220_PHY_ANEG_EXP 0x6
+#define SMSC9220_PHY_MCONTROL 0x17
+#define SMSC9220_PHY_MSTATUS 0x18
+#define SMSC9220_PHY_CSINDICATE 0x27
+#define SMSC9220_PHY_INTSRC 0x29
+#define SMSC9220_PHY_INTMASK 0x30
+#define SMSC9220_PHY_CS 0x31
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+
+#define MPS2_SSP1_BASE (0x40020000ul) /* User SSP Base Address */
+#define MPS2_SSP0_BASE (0x40021000ul) /* CLCD SSP Base Address */
+#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
+#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
+#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
+#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
+#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
+
+#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
+
+#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
+#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+
+#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
+#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
+#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
+#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
+#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
+#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
+#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
+#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
+
+/******************************************************************************/
+/* General Function Definitions */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/* General MACRO Definitions */
+/******************************************************************************/
+
+
+
+#endif /* __SMM_MPS2_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/MPS2.sct Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,47 @@
+;* MPS2 CMSIS Library
+;*
+;* Copyright (c) 2006-2015 ARM Limited
+;* All rights reserved.
+;*
+;* Redistribution and use in source and binary forms, with or without
+;* modification, are permitted provided that the following conditions are met:
+;*
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;*
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;*
+;* 3. Neither the name of the copyright holder nor the names of its contributors
+;* may be used to endorse or promote products derived from this software without
+;* specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
+;*
+; *************************************************************
+; *** Scatter-Loading Description File ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00400000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,293 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2015 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM7.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM7 Device +; @version V1.00 +; @date 04. February 2015 +; +; @note +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler + DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler + DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler + DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler + DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler + DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler + DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler + DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler + DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + EXPORT PORT0_8_Handler [WEAK] + EXPORT PORT0_9_Handler [WEAK] + EXPORT PORT0_10_Handler [WEAK] + EXPORT PORT0_11_Handler [WEAK] + EXPORT PORT0_12_Handler [WEAK] + EXPORT PORT0_13_Handler [WEAK] + EXPORT PORT0_14_Handler [WEAK] + EXPORT PORT0_15_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler +PORT0_8_Handler +PORT0_9_Handler +PORT0_10_Handler +PORT0_11_Handler +PORT0_12_Handler +PORT0_13_Handler +PORT0_14_Handler +PORT0_15_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/gcc_arm.ld Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,195 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ KEEP(*(.stack*))
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/startup_ARMCM7.s Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,314 @@ +/* File: startup_ARMCM7.S + * Purpose: startup file for Cortex-M7 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.00 + * Date: 22 August 2014 + * + */ +/* Copyright (c) 2011 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00000400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000C00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long WDT_IRQHandler /* 0: Watchdog Timer */ + .long RTC_IRQHandler /* 1: Real Time Clock */ + .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */ + .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */ + .long MCIA_IRQHandler /* 4: MCIa */ + .long MCIB_IRQHandler /* 5: MCIb */ + .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */ + .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */ + .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */ + .long UART4_IRQHandler /* 9: UART4 - not connected */ + .long AACI_IRQHandler /* 10: AACI / AC97 */ + .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */ + .long ENET_IRQHandler /* 12: Ethernet */ + .long USBDC_IRQHandler /* 13: USB Device */ + .long USBHC_IRQHandler /* 14: USB Host Controller */ + .long CHLCD_IRQHandler /* 15: Character LCD */ + .long FLEXRAY_IRQHandler /* 16: Flexray */ + .long CAN_IRQHandler /* 17: CAN */ + .long LIN_IRQHandler /* 18: LIN */ + .long I2C_IRQHandler /* 19: I2C ADC/DAC */ + .long 0 /* 20: Reserved */ + .long 0 /* 21: Reserved */ + .long 0 /* 22: Reserved */ + .long 0 /* 23: Reserved */ + .long 0 /* 24: Reserved */ + .long 0 /* 25: Reserved */ + .long 0 /* 26: Reserved */ + .long 0 /* 27: Reserved */ + .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */ + .long 0 /* 29: Reserved - CPU FPGA */ + .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */ + .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler WDT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TIM0_IRQHandler + def_irq_handler TIM2_IRQHandler + def_irq_handler MCIA_IRQHandler + def_irq_handler MCIB_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler AACI_IRQHandler + def_irq_handler CLCD_IRQHandler + def_irq_handler ENET_IRQHandler + def_irq_handler USBDC_IRQHandler + def_irq_handler USBHC_IRQHandler + def_irq_handler CHLCD_IRQHandler + def_irq_handler FLEXRAY_IRQHandler + def_irq_handler CAN_IRQHandler + def_irq_handler LIN_IRQHandler + def_irq_handler I2C_IRQHandler + def_irq_handler CPU_CLCD_IRQHandler + def_irq_handler SPI_IRQHandler + + .end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,42 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in MPS2 specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_CM7.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,58 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* CMSIS-style functionality to support dynamic vectors
+*******************************************************************************/
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,54 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* CMSIS-style functionality to support dynamic vectors
+*******************************************************************************/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/peripherallink.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,53 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* Name: Device.h +* Purpose: Include the correct device header file +*******************************************************************************/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_CM0 + #include "CMSDK_CM0.h" /* device specific header file */ +#elif defined CMSDK_CM0plus + #include "CMSDK_CM0plus.h" /* device specific header file */ +#elif defined CMSDK_CM3 + #include "CMSDK_CM3.h" /* device specific header file */ +#elif defined CMSDK_CM4 + #include "CMSDK_CM4.h" /* device specific header file */ +#elif defined CMSDK_CM7 + #include "CMSDK_CM7.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,105 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+* @file system_CMSDK_CM7.c
+* @brief CMSIS Device System Source File for
+* CMSDK_CM7 Device
+* @version V1.00
+* @date 27. August 2014
+*
+* @note
+*
+*******************************************************************************/
+
+
+#if defined (CMSDK_CM7)
+ #include "CMSDK_CM7.h"
+#elif defined (CMSDK_CM7_SP)
+ #include "CMSDK_CM7_SP.h"
+#elif defined (CMSDK_CM7_DP)
+ #include "CMSDK_CM7_DP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (50000000UL) /* Oscillator frequency */
+
+#define __SYSTEM_CLOCK (__XTAL / 2)
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency */
+
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate (void)
+{
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+ #if (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
+ (3UL << 11*2) ); /* set CP11 Full Access */
+ #endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,80 @@
+/* MPS2 CMSIS Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+*******************************************************************************
+* @file system_CMSDK_CM7.h
+* @brief CMSIS Device Peripheral Access Layer Header File for
+* CMSDK_CM7 Device
+* @version V1.00
+* @date 27. August 2014
+*
+* @note
+*
+******************************************************************************/
+
+
+#ifndef SYSTEM_CMSDK_CM7_H
+#define SYSTEM_CMSDK_CM7_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CMSDK_CM7_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PeripheralNames.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)CMSDK_UART0_BASE,
+ UART_1 = (int)CMSDK_UART1_BASE
+} UARTName;
+
+typedef enum {
+ I2C_0 = (int)MPS2_TS_I2C,
+ I2C_1 = (int)MPS2_AAIC_I2C
+
+} I2CName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ SPI_0 = (int)MPS2_SSP1,
+ SPI_1 = (int)MPS2_SSP0
+} SPIName;
+
+typedef enum {
+ PWM_1 = 0,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6,
+ PWM_7,
+ PWM_8,
+ PWM_9,
+ PWM_10,
+ PWM_11
+} PWMName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+#define MBED_UART0 USBTX, USBRX
+#define MBED_UART1 UART_TX1, UART_RX1
+#define MBED_UART2 UART_TX2, UART_RX2
+#define MBED_UARTUSB USBTX, USBRX
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,168 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // MPS2 EXP Pin Names
+ EXP0 = 0,
+ EXP1 = 1,
+ EXP2 = 2,
+ EXP3 = 3,
+ EXP4 = 4,
+ EXP5 = 5,
+ EXP6 = 6,
+ EXP7 = 7,
+ EXP8 = 8,
+ EXP9 = 9,
+ EXP10 = 10,
+ EXP11 = 11,
+ EXP12 = 12,
+ EXP13 = 13,
+ EXP14 = 14,
+ EXP15 = 15,
+ EXP16 = 16,
+ EXP17 = 17,
+ EXP18 = 18,
+ EXP19 = 19,
+ EXP20 = 20,
+ EXP21 = 21,
+ EXP22 = 22,
+ EXP23 = 23,
+ EXP24 = 24,
+ EXP25 = 25,
+
+ EXP26 = 26,
+ EXP27 = 27,
+ EXP28 = 28,
+ EXP29 = 29,
+ EXP30 = 30,
+ EXP31 = 31,
+ EXP32 = 32,
+ EXP33 = 33,
+ EXP34 = 34,
+ EXP35 = 35,
+ EXP36 = 36,
+ EXP37 = 37,
+ EXP38 = 38,
+ EXP39 = 39,
+ EXP40 = 40,
+ EXP41 = 41,
+ EXP42 = 42,
+ EXP43 = 43,
+ EXP44 = 44,
+ EXP45 = 45,
+ EXP46 = 46,
+ EXP47 = 47,
+ EXP48 = 48,
+ EXP49 = 49,
+ EXP50 = 50,
+ EXP51 = 51,
+
+// Other mbed Pin Names
+
+ //LEDs on mps2
+ //user leds
+ USERLED1 = 100,
+ USERLED2 = 101,
+ //user switches
+ USERSW1 = 110,
+ USERSW2 = 111,
+
+ //mcc leds
+ LED1 = 200,
+ LED2 = 201,
+ LED3 = 202,
+ LED4 = 203,
+ LED5 = 204,
+ LED6 = 205,
+ LED7 = 206,
+ LED8 = 207,
+
+ //MCC Switches
+ SW1 = 210,
+ SW2 = 211,
+ SW3 = 212,
+ SW4 = 213,
+ SW5 = 214,
+ SW6 = 215,
+ SW7 = 216,
+ SW8 = 217,
+
+ //MPS2 SPI header pins j21
+ MOSI_SPI = 300,
+ MISO_SPI = 301,
+ SCLK_SPI = 302,
+ SSEL_SPI = 303,
+
+ //MPS2 CLCD SPI
+ CLCD_MOSI = 304,
+ CLCD_MISO = 305,
+ CLCD_SCLK = 306,
+ CLCD_SSEL = 307,
+ CLCD_RESET = 308,
+ CLCD_RS = 309,
+ CLCD_RD = 310,
+ CLCD_BL_CTRL = 311,
+
+
+ //MPS2 Uart
+ USBTX = 400,
+ USBRX = 401,
+ UART_TX1 = 402,
+ UART_RX1 = 403,
+ UART_TX2 = 404,
+ UART_RX2 = 405,
+
+ //MPS2 I2C touchscreen and audio
+ TSC_SDA = 500,
+ TSC_SCL = 501,
+ AUD_SDA = 502,
+ AUD_SCL = 503,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+} PinName;
+
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ Repeater = 3,
+ OpenDrain = 4,
+ PullDefault = PullDown
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PortNames.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,451 @@
+/* MPS2 Peripheral Library
+*
+* Copyright (c) 2006-2015 ARM Limited
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * Code implementation file for the LAN Ethernet interface.
+ */
+
+#include <stdio.h>
+
+#include "ETH_MPS2.h"
+#include "fpga.h"
+
+// SMSC9220 low-level operations
+unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
+{
+ unsigned int val, maccmd;
+ int timedout;
+ int error;
+
+ error = 0;
+ val = SMSC9220->MAC_CSR_CMD;
+ if(!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
+ maccmd = 0;
+ maccmd |= regoffset;
+ maccmd |= ((unsigned int)1 << 30); // Indicates read
+ maccmd |= ((unsigned int)1 << 31); // Start bit
+ SMSC9220->MAC_CSR_CMD = maccmd; // Start operation
+
+ timedout = 50;
+ do {
+ val = SMSC9220->BYTE_TEST; // A no-op read.
+ Sleepms(1);
+ timedout--;
+ } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
+
+ if(!timedout) {
+ error = 1;
+ }
+ else
+ *data = SMSC9220->MAC_CSR_DATA;
+ } else {
+ *data = 0;
+ }
+ return error;
+}
+
+unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
+{
+ unsigned int read, maccmd;
+ int timedout;
+ int error;
+
+ error = 0;
+ read = SMSC9220->MAC_CSR_CMD;
+ if(!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
+ SMSC9220->MAC_CSR_DATA = data; // Store data.
+ maccmd = 0;
+ maccmd |= regoffset;
+ maccmd &= ~((unsigned int)1 << 30); // Clear indicates write
+ maccmd |= ((unsigned int)1 << 31); // Indicate start of operation
+ SMSC9220->MAC_CSR_CMD = maccmd;
+
+ timedout = 50;
+ do {
+ read = SMSC9220->BYTE_TEST; // A no-op read.
+ Sleepms(1);
+ timedout--;
+ } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
+
+ if(!timedout) {
+ error = 1;
+ }
+ } else {
+ printf("Warning: SMSC9220 MAC CSR is busy. No data written.\n");
+ }
+ return error;
+}
+
+unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
+{
+ unsigned int val, phycmd; int error;
+ int timedout;
+
+ error = 0;
+
+ smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
+
+ if(!(val & 1)) { // Not busy
+ phycmd = 0;
+ phycmd |= (1 << 11); // 1 to [15:11]
+ phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6]
+ phycmd &= ~(1 << 1); // Clear [1] indicates read.
+ phycmd |= (1 << 0); // Set [0] indicates operation start
+
+ smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd);
+
+ val = 0;
+ timedout = 50;
+ do {
+ Sleepms(1);
+ timedout--;
+ smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val);
+ } while(timedout && (val & ((unsigned int)1 << 0)));
+
+ if(!timedout) {
+ error = 1;
+ }
+ else
+ smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data);
+
+ } else {
+ *data = 0;
+ }
+ return error;
+}
+
+unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data)
+{
+ unsigned int val, phycmd; int error;
+ int timedout;
+
+ error = 0;
+
+ smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
+
+ if(!(val & 1)) { // Not busy
+ smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data
+ phycmd = 0;
+ phycmd |= (1 << 11); // 1 to [15:11]
+ phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6]
+ phycmd |= (1 << 1); // Set [1] indicates write.
+ phycmd |= (1 << 0); // Set [0] indicates operation start
+ smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd); // Start operation
+
+ phycmd = 0;
+ timedout = 50;
+
+ do {
+
+ Sleepms(1);
+ timedout--;
+ smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd);
+ } while(timedout && (phycmd & (1 << 0)));
+
+ if(!timedout) {
+ error = 1;
+ }
+
+ } else {
+ printf("Warning: SMSC9220 MAC MII is busy. No data written.\n");
+ }
+ return error;
+}
+
+// Returns smsc9220 id.
+unsigned int smsc9220_read_id(void)
+{
+ return SMSC9220->ID_REV;
+}
+
+// Initiates a soft reset, returns failure or success.
+unsigned int smsc9220_soft_reset(void)
+{
+ int timedout;
+
+ timedout = 10;
+ // Soft reset
+ SMSC9220->HW_CFG |= 1;
+
+ do {
+ Sleepms(1);
+ timedout--;
+ } while(timedout && (SMSC9220->HW_CFG & 1));
+
+ if(!timedout)
+ return 1;
+
+ return 0;
+}
+
+void smsc9220_set_txfifo(unsigned int val)
+{
+ // 2kb minimum, 14kb maximum
+ if(val < 2 || val > 14)
+ return;
+
+ SMSC9220->HW_CFG = val << 16;
+}
+
+
+unsigned int smsc9220_wait_eeprom(void)
+{
+ int timedout;
+
+ timedout = 50;
+
+ do {
+ Sleepms(1);
+ timedout--;
+
+ } while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31)));
+
+ if(!timedout)
+ return 1;
+
+ return 0;
+}
+
+/* initialise irqs */
+void smsc9220_init_irqs(void)
+{
+ SMSC9220->INT_EN = 0x0;
+ SMSC9220->INT_STS = 0xFFFFFFFF; // clear all interrupts
+ SMSC9220->IRQ_CFG = 0x22000100; // irq deassertion at 220 usecs and master IRQ enable.
+}
+
+unsigned int smsc9220_check_phy(void)
+{
+ unsigned short phyid1, phyid2;
+
+ smsc9220_phy_regread(SMSC9220_PHY_ID1,&phyid1);
+ smsc9220_phy_regread(SMSC9220_PHY_ID2,&phyid2);
+ return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) ||
+ (phyid1 == 0x0 && phyid2 == 0x0));
+}
+
+unsigned int smsc9220_reset_phy(void)
+{
+ unsigned short read;
+ int error;
+
+ error = 0;
+ if(smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) {
+ error = 1;
+ return error;
+ }
+
+ read |= (1 << 15);
+ if(smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) {
+ error = 1;
+ return error;
+ }
+ return 0;
+}
+
+/* Advertise all speeds and pause capabilities */
+void smsc9220_advertise_cap(void)
+{
+ unsigned short aneg_adv;
+ aneg_adv = 0;
+
+
+ smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
+ aneg_adv |= 0xDE0;
+
+ smsc9220_phy_regwrite(SMSC9220_PHY_ANEG_ADV, aneg_adv);
+ smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
+ return;
+}
+
+void smsc9220_establish_link(void)
+{
+ unsigned short bcr;
+
+ smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
+ bcr |= (1 << 12) | (1 << 9);
+ smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, bcr);
+ smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
+
+ {
+ unsigned int hw_cfg;
+
+ hw_cfg = 0;
+ hw_cfg = SMSC9220->HW_CFG;
+
+ hw_cfg &= 0xF0000;
+ hw_cfg |= (1 << 20);
+ SMSC9220->HW_CFG = hw_cfg;
+ }
+
+ return;
+}
+
+void smsc9220_enable_xmit(void)
+{
+ SMSC9220->TX_CFG = 0x2; // Enable trasmission
+ return;
+}
+
+void smsc9220_enable_mac_xmit(void)
+{
+ unsigned int mac_cr;
+
+ mac_cr = 0;
+ smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr);
+
+ mac_cr |= (1 << 3); // xmit enable
+ mac_cr |= (1 << 28); // Heartbeat disable
+
+ smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
+ return;
+}
+
+void smsc9220_enable_mac_recv(void)
+{
+ unsigned int mac_cr;
+
+ mac_cr = 0;
+ smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr);
+ mac_cr |= (1 << 2); // Recv enable
+ smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
+
+ return;
+}
+
+
+unsigned int smsc9220_check_ready(void)
+{
+ return !(SMSC9220->PMT_CTRL & 1);
+}
+
+/* Generate a soft irq */
+void smsc9220_set_soft_int(void)
+{
+ SMSC9220->INT_EN |= 0x80000000;
+}
+
+/* clear soft irq */
+void smsc9220_clear_soft_int(void)
+{
+ SMSC9220->INT_STS |= 0x80000000;
+}
+
+
+unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
+{
+ unsigned int rxfifo_inf; // Tells us the status of rx payload and status fifos.
+ unsigned int rxfifo_stat;
+
+ unsigned int pktsize;
+ unsigned int dwords_to_read;
+
+ rxfifo_inf = SMSC9220->RX_FIFO_INF;
+
+ if(rxfifo_inf & 0xFFFF) { // If there's data
+ rxfifo_stat = SMSC9220->RX_STAT_PORT;
+ if(rxfifo_stat != 0) { // Fetch status of this packet
+ pktsize = ((rxfifo_stat >> 16) & 0x3FFF);
+ if(rxfifo_stat & (1 << 15)) {
+ printf("Error occured during receiving of packets on the bus.\n");
+ return 1;
+ } else {
+ /* Below formula (recommended by SMSC9220 code)
+ * gives 1 more than required. This is perhaps because
+ * a last word is needed for not word aligned packets.
+ */
+ dwords_to_read = (pktsize + 3) >> 2;
+ // PIO copy of data received:
+ while(dwords_to_read > 0) {
+ recvbuf[*index] = SMSC9220->RX_DATA_PORT;
+ (*index)++;
+ dwords_to_read--;
+ }
+ }
+ } else {
+ return 1;
+ }
+ } else {
+ return 1;
+ }
+
+ rxfifo_stat = SMSC9220->RX_STAT_PORT;
+ rxfifo_inf = SMSC9220->RX_FIFO_INF;
+
+ return 0;
+}
+
+
+// Does the actual transfer of data to FIFO, note it does no
+// fifo availability checking. This should be done by caller.
+// Assumes the whole frame is transferred at once as a single segment
+void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length)
+{
+ unsigned int txcmd_a, txcmd_b;
+ unsigned int dwords_to_write;
+ volatile unsigned int dwritten;
+ unsigned int *pktptr;
+ volatile unsigned int xmit_stat, xmit_stat2, xmit_inf;
+ int i;
+
+ pktptr = (unsigned int *) pkt;
+ txcmd_a = 0;
+ txcmd_b = 0;
+
+ txcmd_a |= (1 << 12) | (1 << 13); // First and last segments
+ txcmd_a |= length & 0x7FF; // [10:0] contains length
+
+ txcmd_b |= ((length & 0xFFFF) << 16); // [31:16] contains length
+ txcmd_b |= length & 0x7FF; // [10:0] also contains length
+
+
+ SMSC9220->TX_DATA_PORT = txcmd_a;
+ SMSC9220->TX_DATA_PORT = txcmd_b;
+ dwritten = dwords_to_write = (length + 3) >> 2;
+
+ // PIO Copy to FIFO. Could replace this with DMA.
+ while(dwords_to_write > 0) {
+ SMSC9220->TX_DATA_PORT = *pktptr;
+ pktptr++;
+ dwords_to_write--;
+ }
+
+ xmit_stat = SMSC9220->TX_STAT_PORT;
+ xmit_stat2 = SMSC9220->TX_STAT_PORT;
+ xmit_inf = SMSC9220->TX_FIFO_INF;
+
+ if(xmit_stat2 != 0 ) {
+ for(i = 0; i < 6; i++) {
+ xmit_stat2 = SMSC9220->TX_STAT_PORT;
+ }
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,65 @@ +/* MPS2 Peripheral Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _ETH_MPS2_H_ +#define _ETH_MPS2_H_ + +#include "SMM_MPS2.h" + +// Function declarations + +unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data); +unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data); +unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data); +unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data); + +unsigned int smsc9220_read_id(void); +unsigned int smsc9220_soft_reset(void); +void smsc9220_set_txfifo(unsigned int val); +unsigned int smsc9220_wait_eeprom(void); +void smsc9220_init_irqs(void); +unsigned int smsc9220_check_phy(void); +unsigned int smsc9220_reset_phy(void); + +void smsc9220_advertise_cap(void); +void smsc9220_establish_link(void); +void smsc9220_enable_xmit(void); +void smsc9220_enable_mac_xmit(void); +void smsc9220_enable_mac_recv(void); +unsigned int smsc9220_check_ready(void); +void smsc9220_set_soft_int(void); +void smsc9220_clear_soft_int(void); + +unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index); +void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length); + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/fpga.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * ----------------------------------------------------------------
+ * File: fpga.c
+ * Release: Version 1.0
+ * ----------------------------------------------------------------
+ */
+
+/*
+ * Code implementation file for the fpga functions.
+ */
+
+#include "SMM_MPS2.h" // MPS2 common header
+
+// Function to delay n*ticks (25MHz = 40nS per tick)
+// Used for I2C drivers
+void i2c_delay(unsigned int tick)
+{
+ unsigned int end;
+ unsigned int start;
+
+ start = MPS2_FPGAIO->COUNTER;
+ end = start + (tick);
+
+ if(end >= start)
+ {
+ while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
+ }
+ else
+ {
+ while (MPS2_FPGAIO->COUNTER >= start);
+ while (MPS2_FPGAIO->COUNTER < end);
+ }
+}
+
+/* Sleep function to delay n*mS
+ * Uses FPGA counter.
+ */
+void Sleepms(unsigned int msec)
+{
+ unsigned int end;
+ unsigned int start;
+
+ start = MPS2_FPGAIO->COUNTER;
+ end = start + (25 * msec * 1000);
+
+ if(end >= start)
+ {
+ while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
+ }
+ else
+ {
+ while (MPS2_FPGAIO->COUNTER >= start);
+ while (MPS2_FPGAIO->COUNTER < end);
+ }
+}
+
+/* Sleep function to delay n*uS
+ */
+void Sleepus(unsigned int usec)
+{
+ unsigned int end;
+ unsigned int start;
+
+ start = MPS2_FPGAIO->COUNTER;
+ end = start + (25 * usec);
+
+ if(end >= start)
+ {
+ while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end);
+ }
+ else
+ {
+ while (MPS2_FPGAIO->COUNTER >= start);
+ while (MPS2_FPGAIO->COUNTER < end);
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/fpga.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,34 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Code implementation file for the fpga functions. + */ + +#include "SMM_MPS2.h" // MPS2 common header + +// Function to delay n*ticks (25MHz = 40nS per tick) +// Used for I2C drivers +void i2c_delay(unsigned int tick); + +/* Sleep function to delay n*mS + * Uses FPGA counter. + */ +void Sleepms(unsigned int msec); + +/* Sleep function to delay n*uS + */ +void Sleepus(unsigned int usec);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+
+#include "mps2_ethernet_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+#include "ETH_MPS2.h"
+#include "wait_api.h"
+
+#define TX_PKT_SIZE 256
+#define RX_PKT_SIZE 300
+
+// Types
+#undef FALSE
+#undef TRUE
+#define FALSE 0
+#define TRUE 1
+
+
+int smsc9220_check_id(void)
+{
+ int error;
+ unsigned int id;
+ error = 0;
+
+ id = smsc9220_read_id();
+
+ // If bottom and top halves of the word are the same
+ if(((id >> 16) & 0xFFFF) == (id & 0xFFFF)) {
+ error = 1;
+ return error;
+ }
+ switch(((id >> 16) & 0xFFFF)) {
+ case 0x9220:
+ break;
+
+ default:
+ error = 1;
+ break;
+ }
+
+ return error;
+}
+
+int smsc9220_check_macaddress(void)
+{
+ int error;
+ const unsigned int mac_valid_high = 0xC00A;
+ const unsigned int mac_valid_low = 0x00F70200;
+ unsigned int mac_low;
+ unsigned int mac_high;
+
+ error = 0;
+
+ // Read current mac address.
+ smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high);
+ smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low);
+
+ // Writing temporary address:
+ smsc9220_mac_regwrite(SMSC9220_MAC_ADDRH, mac_valid_high);
+ smsc9220_mac_regwrite(SMSC9220_MAC_ADDRL, mac_valid_low);
+
+ // Verify write was correct:
+ smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high);
+ smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low);
+
+
+ if(mac_high != mac_valid_high || mac_low != mac_valid_low) {
+ error = TRUE;
+ return error;
+ }
+
+ return error;
+}
+
+
+/*----------------------------------------------------------------------------
+ Ethernet Device initialize
+ *----------------------------------------------------------------------------*/
+
+int ethernet_transmission(unsigned char * pkt, unsigned int length)
+{
+ smsc9220_xmit_packet(pkt, length);
+ return 0;
+}
+
+int ethernet_reception(unsigned int *recvbuf, unsigned int *index)
+{
+ return smsc9220_recv_packet((unsigned int *)recvbuf, index);
+}
+
+int ethernet_mac_address(char *mac)
+{
+ return smsc9220_check_macaddress();
+}
+
+unsigned int ethernet_check_ready(void)
+{
+ return smsc9220_check_ready();
+}
+
+unsigned int ethernet_intf()
+{
+ unsigned int txfifo_inf;
+
+ txfifo_inf = SMSC9220->TX_FIFO_INF;
+
+ return txfifo_inf;
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MPS2_ETHERNET_API_H
+#define MPS2_ETHERNET_API_H
+
+#include "device.h"
+
+#if DEVICE_ETHERNET
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Connection constants
+
+// send ethernet write buffer, returning the packet size sent
+int ethernet_transmission(unsigned char * pkt, unsigned int length);
+
+// recieve from ethernet buffer, returning packet size, or 0 if no packet
+int ethernet_reception(unsigned int *recvbuf, unsigned int *index);
+
+// get the ethernet address
+int ethernet_mac_address(char *mac);
+
+unsigned int ethernet_check_ready(void);
+
+unsigned int ethernet_intf(void);
+
+int smsc9220_check_id(void);
+
+int smsc9220_check_macaddress(void);
+
+void smsc9220_print_mac_registers(void);
+void smsc9220_print_phy_registers(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/device.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,64 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 0 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CLCD 1 + +#define DEVICE_TSC 1 + +#define DEVICE_AACI 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 1 + +#define DEVICE_PWMOUT 0 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 + +#define DEVICE_SLEEP 0 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,164 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+
+#include "ethernet_api.h"
+#include "mps2_ethernet_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+#include "ETH_MPS2.h"
+#include "wait_api.h"
+
+#define TX_PKT_SIZE 256
+#define RX_PKT_SIZE 300
+
+// Types
+#undef FALSE
+#undef TRUE
+#define FALSE 0
+#define TRUE 1
+
+/*----------------------------------------------------------------------------
+ Ethernet Device initialize
+ *----------------------------------------------------------------------------*/
+int ethernet_init()
+{
+ int error;
+ error = 0;
+
+ if(smsc9220_check_id()) {
+ error = TRUE;
+ }
+
+ if(smsc9220_soft_reset()) {
+ error = TRUE;
+ }
+
+ smsc9220_set_txfifo(5);
+
+ // Sets automatic flow control thresholds, and backpressure
+ // threshold to defaults specified.
+ SMSC9220->AFC_CFG = 0x006E3740;
+
+ if(smsc9220_wait_eeprom()) {
+ error = TRUE;
+ }
+
+ // Configure GPIOs as LED outputs.
+ SMSC9220->GPIO_CFG = 0x70070000;
+
+ smsc9220_init_irqs();
+
+ /* Configure MAC addresses here if needed. */
+
+ if(smsc9220_check_phy()) {
+ error = TRUE;
+ }
+
+ if(smsc9220_reset_phy()) {
+ error = TRUE;
+ return error;
+ }
+
+ wait_ms(100);
+ // Checking whether phy reset completed successfully.
+ {
+ unsigned short phyreset;
+ phyreset = 0;
+ smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset);
+ if(phyreset & (1 << 15)) {
+ error = TRUE;
+ return error;
+ }
+ }
+
+ /* Advertise capabilities */
+ smsc9220_advertise_cap();
+
+
+ /* Begin to establish link */
+ smsc9220_establish_link(); // bit [12] of BCONTROL seems self-clearing.
+ // Although it's not so in the manual.
+
+ /* Interrupt threshold */
+ SMSC9220->FIFO_INT = 0xFF000000;
+
+ smsc9220_enable_mac_xmit();
+
+ smsc9220_enable_xmit();
+
+ SMSC9220->RX_CFG = 0;
+
+ smsc9220_enable_mac_recv();
+
+ // Rx status FIFO level irq threshold
+ SMSC9220->FIFO_INT &= ~(0xFF); // Clear 2 bottom nibbles
+
+ // This sleep is compulsory otherwise txmit/receive will fail.
+ wait_ms(2000);
+ return error;
+
+}
+
+/*----------------------------------------------------------------------------
+ Ethernet Device Uninitialize
+ *----------------------------------------------------------------------------*/
+void ethernet_free() {
+}
+
+int ethernet_write(const char *data, int size)
+{
+ return 0;
+}
+
+int ethernet_send()
+{
+ return 0;
+}
+
+int ethernet_receive()
+{
+ return 0;
+}
+
+// Read from an recevied ethernet packet.
+// After receive returnd a number bigger than 0 it is
+// possible to read bytes from this packet.
+// Read will write up to size bytes into data.
+// It is possible to use read multible times.
+// Each time read will start reading after the last read byte before.
+
+int ethernet_read(char *data, int dlen)
+{
+ return 0;
+}
+
+void ethernet_address(char *mac) {
+ mbed_mac_address(mac);
+}
+
+int ethernet_link(void)
+{
+ return 0;
+}
+
+void ethernet_set_link(int speed, int duplex)
+{
+ smsc9220_establish_link();
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,124 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+
+// function to enable the GPIO pin
+uint32_t gpio_set(PinName pin) {
+ return (1);
+}
+
+//function to initialise the gpio pin
+// this links the board control bits for each pin
+// with the object created for the pin
+void gpio_init(gpio_t *obj, PinName pin) {
+ if(pin == NC){ return;}
+ else {
+ int pin_value = 0;
+ obj->pin = pin;
+ if(pin <=15){
+ pin_value = pin;
+ }else if (pin >= 16 && pin <= 31){
+ pin_value = pin-16;
+ }else if (pin >= 32 && pin <= 47){
+ pin_value = pin-32;
+ }else if (pin >= 48 && pin <= 51){
+ pin_value = pin-48;
+ }else if (pin == 100 || pin == 101){
+ pin_value = pin-100;
+ }else if (pin == 110 || pin == 111){
+ pin_value = pin-110;
+ }else if (pin >= 200 && pin <= 207){
+ pin_value = pin-200;
+ }else if (pin >= 210 && pin <= 217){
+ pin_value = pin-210;
+ }else if (pin == 303){
+ pin_value = pin-302;
+ }else if (pin == 307){
+ pin_value = pin-307;
+ }else if (pin == 308){
+ pin_value = pin-305;
+ }else if (pin == 309){
+ pin_value = pin-305;
+ }else if (pin == 310){
+ pin_value = pin-305;
+ }else if (pin == 311){
+ pin_value = pin-305;
+ }
+
+ obj->mask = 0x1 << pin_value;
+ obj->pin_number = pin;
+ if(pin <=15) {
+ obj->reg_data = &CMSDK_GPIO0->DATAOUT ;
+ obj->reg_in = &CMSDK_GPIO0->DATA ;
+ obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET ;
+ obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ;
+ } else if (pin >= 16 && pin <= 31){
+ obj->reg_data = &CMSDK_GPIO1->DATAOUT ;
+ obj->reg_in = &CMSDK_GPIO1->DATA ;
+ obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET ;
+ obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ;
+ } else if (pin >= 32 && pin <= 47){
+ obj->reg_data = &CMSDK_GPIO2->DATAOUT;
+ obj->reg_in = &CMSDK_GPIO2->DATA;
+ obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET ;
+ obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ;
+ } else if (pin >= 48 && pin <= 51){
+ obj->reg_data = &CMSDK_GPIO3->DATAOUT;
+ obj->reg_in = &CMSDK_GPIO3->DATA;
+ obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET ;
+ obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ;
+ } else if (pin == 100 || pin == 101){
+ obj->reg_data = &MPS2_FPGAIO->LED; //user leds
+ obj->reg_in = &MPS2_FPGAIO->LED;
+ } else if (pin == 110 || pin == 111){
+ obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches
+ obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches
+ }else if (pin >= 200 && pin <= 207){
+ obj->reg_data = &MPS2_SCC->LEDS; //mcc leds
+ obj->reg_in = &MPS2_SCC->LEDS; //mcc leds
+ }else if (pin >= 210 && pin <= 217){
+ obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches
+ }else if (pin == 303 || pin == 307){
+ obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307
+ }else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){
+ obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits
+ }
+ }
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+ pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+ if(obj->pin >= 0 && obj->pin <= 51)
+ {
+ switch (direction) {
+ case PIN_INPUT : *obj->reg_dirclr = obj->mask; break;
+ case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
+ }
+ } else {return;}
+}
+
+int gpio_is_connected(const gpio_t *obj){
+ if(obj->pin != (PinName)NC){
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,241 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "mbed_error.h"
+
+#define CHANNEL_NUM 32
+#define CMSDK_GPIO_0 CMSDK_GPIO0
+#define CMSDK_GPIO_1 CMSDK_GPIO1
+#define PININT_IRQ 0
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+static inline void handle_interrupt_in(uint32_t channel) {
+ uint32_t ch_bit = (1 << channel);
+ // Return immediately if:
+ // * The interrupt was already served
+ // * There is no user handler
+ // * It is a level interrupt, not an edge interrupt
+ if (ch_bit <16){
+ if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return;
+
+ if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
+ irq_handler(channel_ids[channel], IRQ_RISE);
+ CMSDK_GPIO_0->INTPOLSET = ch_bit;
+ }
+ if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
+ irq_handler(channel_ids[channel], IRQ_FALL);
+ }
+ CMSDK_GPIO_0->INTCLEAR = ch_bit;
+ }
+
+ if (ch_bit>=16) {
+ if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return;
+
+ if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
+ irq_handler(channel_ids[channel], IRQ_RISE);
+ CMSDK_GPIO_1->INTPOLSET = ch_bit;
+ }
+ if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
+ irq_handler(channel_ids[channel], IRQ_FALL);
+ }
+ CMSDK_GPIO_1->INTCLEAR = ch_bit;
+ }
+}
+
+void gpio0_irq0(void) {handle_interrupt_in(0);}
+void gpio0_irq1(void) {handle_interrupt_in(1);}
+void gpio0_irq2(void) {handle_interrupt_in(2);}
+void gpio0_irq3(void) {handle_interrupt_in(3);}
+void gpio0_irq4(void) {handle_interrupt_in(4);}
+void gpio0_irq5(void) {handle_interrupt_in(5);}
+void gpio0_irq6(void) {handle_interrupt_in(6);}
+void gpio0_irq7(void) {handle_interrupt_in(7);}
+void gpio0_irq8(void) {handle_interrupt_in(8);}
+void gpio0_irq9(void) {handle_interrupt_in(9);}
+void gpio0_irq10(void) {handle_interrupt_in(10);}
+void gpio0_irq11(void) {handle_interrupt_in(11);}
+void gpio0_irq12(void) {handle_interrupt_in(12);}
+void gpio0_irq13(void) {handle_interrupt_in(13);}
+void gpio0_irq14(void) {handle_interrupt_in(14);}
+void gpio0_irq15(void) {handle_interrupt_in(15);}
+void gpio1_irq0(void) {handle_interrupt_in(16);}
+void gpio1_irq1(void) {handle_interrupt_in(17);}
+void gpio1_irq2(void) {handle_interrupt_in(18);}
+void gpio1_irq3(void) {handle_interrupt_in(19);}
+void gpio1_irq4(void) {handle_interrupt_in(20);}
+void gpio1_irq5(void) {handle_interrupt_in(21);}
+void gpio1_irq6(void) {handle_interrupt_in(22);}
+void gpio1_irq7(void) {handle_interrupt_in(23);}
+void gpio1_irq8(void) {handle_interrupt_in(24);}
+void gpio1_irq9(void) {handle_interrupt_in(25);}
+void gpio1_irq10(void) {handle_interrupt_in(26);}
+void gpio1_irq11(void) {handle_interrupt_in(27);}
+void gpio1_irq12(void) {handle_interrupt_in(28);}
+void gpio1_irq13(void) {handle_interrupt_in(29);}
+void gpio1_irq14(void) {handle_interrupt_in(30);}
+void gpio1_irq15(void) {handle_interrupt_in(31);}
+
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+ if (pin == NC) {return -1;}
+ else {
+
+ irq_handler = handler;
+
+ int found_free_channel = 0;
+ int i = 0;
+ for (i=0; i<CHANNEL_NUM; i++) {
+ if (channel_ids[i] == 0) {
+ channel_ids[i] = id;
+ obj->ch = i;
+ found_free_channel = 1;
+ break;
+ }
+ }
+ if (!found_free_channel) return -1;
+
+
+ /* To select a pin for any of the eight pin interrupts, write the pin number
+ * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
+ * @see: mbed_capi/PinNames.h
+ */
+ if (pin <16)
+ {
+ CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
+ }
+
+ if (pin >= 16)
+ {
+ CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
+ }
+
+ void (*channels_irq)(void) = NULL;
+ switch (obj->ch) {
+ case 0: channels_irq = &gpio0_irq0; break;
+ case 1: channels_irq = &gpio0_irq1; break;
+ case 2: channels_irq = &gpio0_irq2; break;
+ case 3: channels_irq = &gpio0_irq3; break;
+ case 4: channels_irq = &gpio0_irq4; break;
+ case 5: channels_irq = &gpio0_irq5; break;
+ case 6: channels_irq = &gpio0_irq6; break;
+ case 7: channels_irq = &gpio0_irq7; break;
+ case 8: channels_irq = &gpio0_irq8; break;
+ case 9: channels_irq = &gpio0_irq9; break;
+ case 10: channels_irq = &gpio0_irq10; break;
+ case 11: channels_irq = &gpio0_irq11; break;
+ case 12: channels_irq = &gpio0_irq12; break;
+ case 13: channels_irq = &gpio0_irq13; break;
+ case 14: channels_irq = &gpio0_irq14; break;
+ case 15: channels_irq = &gpio0_irq15; break;
+ case 16: channels_irq = &gpio1_irq0; break;
+ case 17: channels_irq = &gpio1_irq1; break;
+ case 18: channels_irq = &gpio1_irq2; break;
+ case 19: channels_irq = &gpio1_irq3; break;
+ case 20: channels_irq = &gpio1_irq4; break;
+ case 21: channels_irq = &gpio1_irq5; break;
+ case 22: channels_irq = &gpio1_irq6; break;
+ case 23: channels_irq = &gpio1_irq7; break;
+ case 24: channels_irq = &gpio1_irq8; break;
+ case 25: channels_irq = &gpio1_irq9; break;
+ case 26: channels_irq = &gpio1_irq10; break;
+ case 27: channels_irq = &gpio1_irq11; break;
+ case 28: channels_irq = &gpio1_irq12; break;
+ case 29: channels_irq = &gpio1_irq13; break;
+ case 30: channels_irq = &gpio1_irq14; break;
+ case 31: channels_irq = &gpio1_irq15; break;
+
+ }
+ NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
+ NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+
+ return 0;
+ }
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+ unsigned int ch_bit = (1 << obj->ch);
+
+ // Clear interrupt
+ if (obj->ch <16)
+ {
+ if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit))
+ {
+ CMSDK_GPIO_0->INTCLEAR = ch_bit;
+ }
+ }
+ if (obj->ch >= 16)
+ {
+ if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit))
+ {
+ CMSDK_GPIO_1->INTCLEAR = ch_bit;
+ }
+ }
+
+ // Edge trigger
+ if (obj->ch <16)
+ {
+ CMSDK_GPIO_0->INTTYPESET &= ch_bit;
+ if (event == IRQ_RISE) {
+ CMSDK_GPIO_0->INTPOLSET |= ch_bit;
+ if (enable) {
+ CMSDK_GPIO_0->INTENSET |= ch_bit;
+ } else {
+ CMSDK_GPIO_0->INTENCLR |= ch_bit;
+ }
+ } else {
+ CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
+ if (enable) {
+ CMSDK_GPIO_0->INTENSET |= ch_bit;
+ } else {
+ CMSDK_GPIO_0->INTENCLR |= ch_bit;
+ }
+ }
+ }
+ if (obj->ch >= 16)
+ {
+ CMSDK_GPIO_1->INTTYPESET &= ch_bit;
+ if (event == IRQ_RISE) {
+ CMSDK_GPIO_1->INTPOLSET |= ch_bit;
+ if (enable) {
+ CMSDK_GPIO_1->INTENSET |= ch_bit;
+ } else {
+ CMSDK_GPIO_1->INTENCLR |= ch_bit;
+ }
+ } else {
+ CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
+ if (enable) {
+ CMSDK_GPIO_1->INTENSET |= ch_bit;
+ } else {
+ CMSDK_GPIO_1->INTENCLR |= ch_bit;
+ }
+ }
+ }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj) {
+ NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+}
+
+void gpio_irq_disable(gpio_irq_t *obj) {
+ NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+ uint32_t pin_number;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_dirclr;
+ __IO uint32_t *reg_data;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value == 1){
+ *obj->reg_data |= (obj->mask);
+ } else if (value == 0){
+ *obj->reg_data &= ~(obj->mask);
+ }
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,415 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "SMM_MPS2.h"
+#include "wait_api.h"
+#include "fpga.h"
+
+// Types
+#undef FALSE
+#undef TRUE
+#define FALSE 0
+#define TRUE 1
+
+// TSC I2C controller
+#define TSC_I2C_ADDR 0x82
+// AACI I2C controller I2C address
+#define AAIC_I2C_ADDR 0x96
+
+#define TSC_I2C_CID 0x0811
+
+// TSC I2C controller registers
+#define TSC_I2C_CRID 0x00
+
+
+// TSSPCPSR Clock prescale register
+#define TSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR)
+
+// TSC defaults
+#define TSC_XOFF 20 // X offset
+#define TSC_YOFF 20 // Y offset
+#define TSC_MAXVAL 37000 // 0x0FFF * 10 with TSC to LCD scaling
+
+#define TSC_TSU 15 // Setup delay 600nS min
+#define AAIC_TSU 25 // Setup delay 1000nS min
+
+
+static const PinMap PinMap_I2C_SDA[] = {
+ {TSC_SDA, I2C_0, 0},
+ {AUD_SDA, I2C_1, 0},
+// {EXP_SDA, I2C_2, 0}, //only used in extended version
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+ {TSC_SCL, I2C_0, 0},
+ {AUD_SCL, I2C_1, 0},
+// {EXP_SCL, I2C_2, 0}, //only used in extended version
+ {NC , NC, 0}
+};
+
+static inline void i2c_send_byte(i2c_t *obj, unsigned char c)
+{
+ int loop;
+ switch ((int)obj->i2c) {
+ case I2C_0:
+ obj->i2c->CONTROLC = SCL;
+ i2c_delay(TSC_TSU);
+
+ for (loop = 0; loop < 8; loop++)
+ {
+ if (c & (1 << (7 - loop)))
+ obj->i2c->CONTROLS = SDA;
+ else
+ obj->i2c->CONTROLC = SDA;
+ i2c_delay(TSC_TSU);
+ obj->i2c->CONTROLS = SCL;
+ i2c_delay(TSC_TSU);
+ obj->i2c->CONTROLC = SCL;
+ i2c_delay(TSC_TSU);
+ }
+
+ obj->i2c->CONTROLS = SDA;
+ i2c_delay(TSC_TSU);
+ break;
+ case I2C_1:
+ for (loop = 0; loop < 8; loop++) {
+ i2c_delay(AAIC_TSU);
+ obj->i2c->CONTROLC = SCL;
+ i2c_delay(AAIC_TSU);
+ if (c & (1 << (7 - loop)))
+ obj->i2c->CONTROLS = SDA;
+ else
+ obj->i2c->CONTROLC = SDA;
+ i2c_delay(AAIC_TSU);
+ obj->i2c->CONTROLS = SCL;
+ i2c_delay(AAIC_TSU);
+ obj->i2c->CONTROLC = SCL;
+ }
+
+ i2c_delay(AAIC_TSU);
+ obj->i2c->CONTROLS = SDA;
+ i2c_delay(AAIC_TSU);
+ break;
+ }
+}
+
+static inline unsigned char i2c_receive_byte(i2c_t *obj)
+{
+ int data_receive_byte, loop;
+ switch ((int)obj->i2c) {
+ case I2C_0:
+ obj->i2c->CONTROLS = SDA;
+ i2c_delay(TSC_TSU);
+
+ data_receive_byte = 0;
+
+ for (loop = 0; loop < 8; loop++)
+ {
+ obj->i2c->CONTROLS = SCL;
+ i2c_delay(TSC_TSU);
+ if ((obj->i2c->CONTROL & SDA))
+ data_receive_byte += (1 << (7 - loop));
+ obj->i2c->CONTROLC = SCL;
+ i2c_delay(TSC_TSU);
+ }
+
+ obj->i2c->CONTROLC = SDA;
+ i2c_delay(TSC_TSU);
+ break;
+ case I2C_1:
+ obj->i2c->CONTROLS = SDA;
+ data_receive_byte = 0;
+
+ for (loop = 0; loop < 8; loop++) {
+ i2c_delay(AAIC_TSU);
+ obj->i2c->CONTROLC = SCL;
+ i2c_delay(AAIC_TSU);
+ obj->i2c->CONTROLS = SCL | SDA;
+ i2c_delay(AAIC_TSU);
+ if ((obj->i2c->CONTROL & SDA))
+ data_receive_byte += (1 << (7 - loop));
+ i2c_delay(AAIC_TSU);
+ obj->i2c->CONTROLC = SCL;
+ }
+
+ i2c_delay(AAIC_TSU);
+ obj->i2c->CONTROLC = SDA;
+ i2c_delay(AAIC_TSU);
+ break;
+ }
+ return data_receive_byte;
+}
+
+static inline int i2c_receive_ack(i2c_t *obj)
+{
+ int nack;
+ int delay_value;
+ switch ((int)obj->i2c) {
+ case I2C_0: delay_value = TSC_TSU; break;
+ case I2C_1: delay_value = AAIC_TSU; break;
+ }
+
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLS = SDA;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLC = SCL;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLS = SCL;
+ i2c_delay(delay_value);
+ nack = obj->i2c->CONTROL & SDA;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLC = SCL;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLS = SDA;
+ i2c_delay(delay_value);
+ if(nack==0)
+ return 1;
+
+ return 0;
+}
+
+
+static inline void i2c_send_ack(i2c_t *obj)
+{
+ int delay_value;
+ switch ((int)obj->i2c) {
+ case I2C_0: delay_value = TSC_TSU; break;
+ case I2C_1: delay_value = AAIC_TSU; break;
+ }
+
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLC = SCL;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLS = SDA;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLS = SCL;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLC = SCL;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLC = SDA;
+ i2c_delay(delay_value);
+
+}
+
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+
+
+ // determine the SPI to use
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+ obj->i2c = (MPS2_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
+
+ if ((int)obj->i2c == NC) {
+ error("I2C pin mapping failed");
+ }
+
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+}
+
+int i2c_start(i2c_t *obj) {
+
+ int delay_value;
+ switch ((int)obj->i2c) {
+ case I2C_0: delay_value = TSC_TSU; break;
+ case I2C_1: delay_value = AAIC_TSU; break;
+ }
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLS = SDA | SCL;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLC = SDA;
+ i2c_delay(delay_value);
+
+
+
+ return 0;
+}
+
+int i2c_start_tsc(i2c_t *obj) {
+
+ int delay_value;
+ switch ((int)obj->i2c) {
+ case I2C_0: delay_value = TSC_TSU; break;
+ case I2C_1: delay_value = AAIC_TSU; break;
+ }
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLC = SDA;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLC = SCL;
+ i2c_delay(delay_value);
+
+ return 0;
+}
+
+int i2c_stop(i2c_t *obj) {
+
+ int delay_value;
+ switch ((int)obj->i2c) {
+ case I2C_0: delay_value = TSC_TSU; break;
+ case I2C_1: delay_value = AAIC_TSU; break;
+ }
+ // Actual stop bit
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLC = SDA;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLS = SCL;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLS = SDA;
+ i2c_delay(delay_value);
+
+ return 0;
+}
+
+
+
+void i2c_frequency(i2c_t *obj, int hz) {
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+ unsigned int loop, rxdata;
+ int delay_value, sadr, ack, bytes_read;
+ rxdata=0;
+ switch ((int)obj->i2c) {
+ case I2C_0:
+ delay_value = TSC_TSU;
+ sadr = TSC_I2C_ADDR;
+ break;
+ case I2C_1:
+ delay_value = AAIC_TSU;
+ sadr = AAIC_I2C_ADDR;
+ break;
+ }
+ // Start bit
+ i2c_start(obj);
+
+ // Set serial and register address
+ i2c_send_byte(obj,sadr);
+ ack += i2c_receive_ack(obj);
+ i2c_send_byte(obj, address);
+ ack += i2c_receive_ack(obj);
+
+ // Stop bit
+ i2c_stop(obj);
+
+ // Start bit
+ i2c_start_tsc(obj);
+
+ // Read from serial address
+ i2c_send_byte(obj,sadr | 1);
+ ack += i2c_receive_ack(obj);
+ bytes_read = 0;
+
+ switch ((int)obj->i2c) {
+ case I2C_0:
+ rxdata = (i2c_receive_byte(obj) & 0xFF);
+ data[((length-1)-bytes_read)] = (char)rxdata;
+ bytes_read++;
+ // Read multiple bytes
+ if ((length > 1) && (length < 5))
+ {
+ for (loop = 1; loop <= (length - 1); loop++)
+ {
+ // Send ACK
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLC = SDA;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLS = SCL;
+ i2c_delay(delay_value);
+ obj->i2c->CONTROLC = SCL;
+ i2c_delay(delay_value);
+
+ rxdata = i2c_receive_byte(obj);
+ data[(length-1)-bytes_read] = (char)rxdata;
+ bytes_read++;
+
+ }
+ }
+ break;
+ case I2C_1:
+ rxdata = i2c_receive_byte(obj);
+ data[bytes_read] = (char)rxdata;
+ bytes_read++;
+ break;
+ }
+ i2c_send_ack(obj);
+
+ // Actual stop bit
+ i2c_stop(obj);
+
+ return bytes_read;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+ int ack=0;
+ int sadr;
+ switch ((int)obj->i2c) {
+ case I2C_0: sadr = TSC_I2C_ADDR; break;
+ case I2C_1: sadr = AAIC_I2C_ADDR; break;
+ }
+ for(int i = 1; i<=length; i++)
+ {
+ i2c_start(obj);
+
+ // Set serial and register address
+ i2c_send_byte(obj,sadr);
+ ack += i2c_receive_ack(obj);
+ i2c_send_byte(obj, address);
+ ack += i2c_receive_ack(obj);
+ i2c_send_byte(obj, *data);
+ ack += i2c_receive_ack(obj);
+ }
+
+ i2c_stop(obj);
+ if(ack==3) { return 1; }
+ else{ return 0; }
+
+}
+
+void i2c_reset(i2c_t *obj) {
+ i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+ return 0;
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+ return 0;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+ return 0;
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+ return 0;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+ return 0;
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/objects.h Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,74 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t ch;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_dirclr;
+ __IO uint32_t *reg_out;
+ __IO uint32_t *reg_in;
+ PortName port;
+ uint32_t mask;
+};
+
+struct serial_s {
+ CMSDK_UART_TypeDef *uart;
+ int index;
+};
+
+struct i2c_s {
+ MPS2_I2C_TypeDef *i2c;
+};
+
+struct tsc_s {
+ MPS2_I2C_TypeDef *tsc;
+};
+
+struct audio_s {
+ MPS2_I2S_TypeDef *audio_I2S;
+ MPS2_I2C_TypeDef *audio_I2C;
+};
+
+
+struct spi_s {
+ MPS2_SSP_TypeDef *spi;
+};
+
+struct clcd_s {
+ MPS2_SSP_TypeDef *clcd;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/pinmap.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+
+void pin_function(PinName pin, int function) {
+ MBED_ASSERT(pin != (PinName)NC);
+
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+ MBED_ASSERT(pin != (PinName)NC);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/port_api.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+PinName port_pin(PortName port, int pin_n) {
+ return (PinName)((port << PORT_SHIFT) | pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+ obj->port = port;
+ obj->mask = mask;
+
+ CMSDK_GPIO_TypeDef *port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO0_BASE + ((int)port * 0x10));
+
+ obj->reg_in = &port_reg->DATAOUT;
+ obj->reg_dir = &port_reg->OUTENABLESET;
+ obj->reg_dirclr = &port_reg->OUTENABLECLR;
+
+ uint32_t i;
+ // The function is set per pin: reuse gpio logic
+ for (i=0; i<16; i++) {
+ if (obj->mask & (1<<i)) {
+ gpio_set(port_pin(obj->port, i));
+ }
+ }
+
+ port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+ uint32_t i;
+ // The mode is set per pin: reuse pinmap logic
+ for (i=0; i<32; i++) {
+ if (obj->mask & (1<<i)) {
+ pin_mode(port_pin(obj->port, i), mode);
+ }
+ }
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+ switch (dir) {
+ case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+ case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
+ }
+}
+
+void port_write(port_t *obj, int value) {
+ *obj->reg_in = value;
+}
+
+int port_read(port_t *obj) {
+ return (*obj->reg_in);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,230 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "gpio_api.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+
+static const PinMap PinMap_UART_TX[] = {
+ {USBTX , UART_0, 0},
+ {UART_TX1, UART_1, 0},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+ {USBRX , UART_0, 0},
+ {UART_RX1, UART_1, 0},
+ {NC , NC , 0}
+};
+
+#define UART_NUM 3
+
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+struct serial_global_data_s {
+ uint32_t serial_irq_id;
+ gpio_t sw_rts, sw_cts;
+ uint8_t count, rx_irq_set_flow, rx_irq_set_api;
+};
+
+static struct serial_global_data_s uart_data[UART_NUM];
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+ int is_stdio_uart = 0;
+
+ // determine the UART to use
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+ UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+ if ((int)uart == NC) {
+ error("Serial pinout mapping failed");
+ }
+
+ obj->uart = (CMSDK_UART_TypeDef *)uart;
+ //set baud rate and enable Uart in normarl mode (RX and TX enabled)
+ switch (uart) {
+ case UART_0: CMSDK_UART0->CTRL = 0; // Disable UART when changing configuration
+ CMSDK_UART0->CTRL = 0x3; // Normal mode
+ break;
+ case UART_1: CMSDK_UART1->CTRL = 0; // Disable UART when changing configuration
+ CMSDK_UART1->CTRL = 0x3; // Normal mode
+ break;
+ }
+
+ // set default baud rate and format
+ serial_baud (obj, 9600);
+
+ // pinout the chosen uart
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+
+ switch (uart) {
+ case UART_0: obj->index = 0; break;
+ case UART_1: obj->index = 1; break;
+ }
+ uart_data[obj->index].sw_rts.pin = NC;
+ uart_data[obj->index].sw_cts.pin = NC;
+ serial_set_flow_control(obj, FlowControlNone, NC, NC);
+
+ is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+
+ if (is_stdio_uart) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj) {
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+ // The MPS2 has a simple divider to control the baud rate. The formula is:
+ //
+ // Baudrate = PCLK / BAUDDIV
+ //
+ // PCLK = 25 Mhz
+ // so for a desired baud rate of 9600
+ // 25000000 / 9600 = 2604
+ //
+ //check to see if minimum baud value entered
+ int baudrate_div = 0;
+ baudrate_div = 25000000 / baudrate;
+ if(baudrate >= 16){
+ switch ((int)obj->uart) {
+ case UART_0: CMSDK_UART0->BAUDDIV = baudrate_div; break;
+ case UART_1: CMSDK_UART1->BAUDDIV = baudrate_div; break;
+ default: error("serial_baud"); break;
+ }
+ } else {
+ error("serial_baud");
+ }
+
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) {
+ SerialIrq irq_type;
+ switch (intstatus) {
+ case 1: irq_type = TxIrq; break;
+ case 2: irq_type = RxIrq; break;
+ default: return;
+ }
+ if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
+ gpio_write(&uart_data[index].sw_rts, 1);
+ // Disable interrupt if it wasn't enabled by other part of the application
+ if (!uart_data[index].rx_irq_set_api)
+ puart->CTRL &= ~(1 << RxIrq);
+ }
+ if (uart_data[index].serial_irq_id != 0)
+ if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
+ irq_handler(uart_data[index].serial_irq_id, irq_type);
+}
+
+void uart0_irq() {uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART0);}
+void uart1_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART1);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ uart_data[obj->index].serial_irq_id = id;
+}
+
+static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ switch ((int)obj->uart) {
+ case UART_0: irq_n=((irq>> 2) ? UARTRX0_IRQn : UARTTX0_IRQn); vector = (uint32_t)&uart0_irq; break;
+ case UART_1: irq_n=((irq>> 2) ? UARTRX1_IRQn : UARTTX1_IRQn); vector = (uint32_t)&uart1_irq; break;
+ }
+
+ if (enable) {
+ obj->uart->CTRL |= 1 << irq;
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+ } else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
+ int all_disabled = 0;
+ SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+ obj->uart->CTRL &= ~(1 << irq);
+ all_disabled = (obj->uart->CTRL & (1 << other_irq)) == 0;
+ if (all_disabled)
+ NVIC_DisableIRQ(irq_n);
+ }
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ if (RxIrq == irq)
+ uart_data[obj->index].rx_irq_set_api = enable;
+ serial_irq_set_internal(obj, irq, enable);
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+ while (serial_readable(obj) == 0);
+ int data = obj->uart->DATA;
+ return data;
+}
+
+void serial_putc(serial_t *obj, int c) {
+ while (serial_writable(obj));
+ obj->uart->DATA = c;
+}
+
+int serial_readable(serial_t *obj) {
+ return obj->uart->STATE & 2;
+}
+
+int serial_writable(serial_t *obj) {
+ return obj->uart->STATE & 1;
+}
+
+void serial_clear(serial_t *obj) {
+ obj->uart->DATA = 0x00;
+}
+
+void serial_pinout_tx(PinName tx) {
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+}
+
+void serial_break_clear(serial_t *obj) {
+}
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,227 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+
+#include "spi_api.h"
+#include "spi_def.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "wait_api.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+ {SCLK_SPI , SPI_0, 0},
+ {CLCD_SCLK , SPI_1, 0},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+ {MOSI_SPI, SPI_0, 0},
+ {CLCD_MOSI, SPI_1, 0},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+ {MISO_SPI, SPI_0, 0},
+ {CLCD_MISO, SPI_1, 0},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+ {SSEL_SPI, SPI_0, 0},
+ {CLCD_SSEL, SPI_1, 0},
+ {NC , NC , 0}
+};
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+ // determine the SPI to use
+ SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+ SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+ SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+ SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+ obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
+ if ((int)obj->spi == NC) {
+ error("SPI pinout mapping failed");
+ }
+
+ // enable power and clocking
+ switch ((int)obj->spi) {
+ case (int)SPI_0:
+ obj->spi->CR1 = 0;
+ obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
+ obj->spi->CPSR = SSP_CPSR_DFLT;
+ obj->spi->IMSC = 0x8;
+ obj->spi->DMACR = 0;
+ obj->spi->CR1 = SSP_CR1_SSE_Msk;
+ obj->spi->ICR = 0x3;
+ break;
+ case (int)SPI_1:
+ /* Configure SSP used for LCD */
+ obj->spi->CR1 = 0; /* Synchronous serial port disable */
+ obj->spi->DMACR = 0; /* Disable FIFO DMA */
+ obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */
+ obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */
+ (1ul << 1) ); /* Clear SSPRTINTR interrupt */
+ obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */
+ (0ul << 4) | /* Motorola frame format */
+ (0ul << 6) | /* CPOL = 0 */
+ (0ul << 7) | /* CPHA = 0 */
+ (1ul << 8) ); /* Set serial clock rate */
+ obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */
+ obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */
+ (0ul << 2) ); /* Device configured as master */
+ break;
+ }
+
+ // set default format and frequency
+ if (ssel == NC) {
+ spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
+ } else {
+ spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
+ }
+ spi_frequency(obj, 1000000);
+
+ // enable the ssp channel
+ ssp_enable(obj);
+
+ // pin out the spi pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+ if (ssel != NC) {
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+ ssp_disable(obj);
+ if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
+ error("SPI format error");
+ }
+
+ int polarity = (mode & 0x2) ? 1 : 0;
+ int phase = (mode & 0x1) ? 1 : 0;
+
+ // set it up
+ int DSS = bits - 1; // DSS (data select size)
+ int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
+ int SPH = (phase) ? 1 : 0; // SPH - clock out phase
+
+ int FRF = 0; // FRF (frame format) = SPI
+ uint32_t tmp = obj->spi->CR0;
+ tmp &= ~(0xFFFF);
+ tmp |= DSS << 0
+ | FRF << 4
+ | SPO << 6
+ | SPH << 7;
+ obj->spi->CR0 = tmp;
+
+ tmp = obj->spi->CR1;
+ tmp &= ~(0xD);
+ tmp |= 0 << 0 // LBM - loop back mode - off
+ | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
+ | 0 << 3; // SOD - slave output disable - na
+ obj->spi->CR1 = tmp;
+
+ ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+ ssp_disable(obj);
+
+ uint32_t PCLK = SystemCoreClock;
+
+ int prescaler;
+
+ for (prescaler = 2; prescaler <= 254; prescaler += 2) {
+ int prescale_hz = PCLK / prescaler;
+
+ // calculate the divider
+ int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
+
+ // check we can support the divider
+ if (divider < 256) {
+ // prescaler
+ obj->spi->CPSR = prescaler;
+
+ // divider
+ obj->spi->CR0 &= ~(0xFFFF << 8);
+ obj->spi->CR0 |= (divider - 1) << 8;
+ ssp_enable(obj);
+ return;
+ }
+ }
+ error("Couldn't setup requested SPI frequency");
+}
+
+static inline int ssp_disable(spi_t *obj) {
+ return obj->spi->CR1 &= ~(1 << 1);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+ return obj->spi->CR1 |= SSP_CR1_SSE_Msk;
+}
+
+static inline int ssp_readable(spi_t *obj) {
+ return obj->spi->SR & (1 << 2);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+ return obj->spi->SR & SSP_SR_BSY_Msk;
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+ obj->spi->DR = value;
+ while (ssp_writeable(obj));
+}
+static inline int ssp_read(spi_t *obj) {
+ int read_DR = obj->spi->DR;
+ return read_DR;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+ return (obj->spi->SR & (1 << 4)) ? (1) : (0);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+ ssp_write(obj, value);
+ while (MPS2_SSP0->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */
+ return (ssp_read(obj));
+}
+
+int spi_slave_receive(spi_t *obj) {
+ return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+}
+
+int spi_slave_read(spi_t *obj) {
+ return obj->spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+ while (ssp_writeable(obj) == 0) ;
+ obj->spi->DR = value;
+}
+
+int spi_busy(spi_t *obj) {
+ return ssp_busy(obj);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_def.h Thu Jul 02 16:15:09 2015 +0100 @@ -0,0 +1,174 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ---------------------------------------------------------------- + * File: apspi.h + * Release: Version 2.0 + * ---------------------------------------------------------------- + * + * SSP interface Support + * ===================== + */ + +#define SSPCS_BASE (0x4002804C) // SSP chip select register +#define SSP_BASE (0x40020000) // SSP Prime Cell + +#define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00)) +#define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04)) +#define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08)) +#define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C)) +#define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10)) +#define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14)) +#define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18)) +#define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C)) +#define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20)) +#define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24)) +#define SSPCS ((volatile unsigned int *)(SSPCS_BASE)) + +// SSPCR0 Control register 0 +#define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3 +#define SSPCR0_SPH 0x0080 // SSPCLKOUT phase +#define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity +#define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola +#define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits +#define SSPCR0_DSS_16 0x000F // Data packet size, 16bits + +// SSPCR1 Control register 1 +#define SSPCR1_SOD 0x0008 // Slave Output mode Disable +#define SSPCR1_MS 0x0004 // Master or Slave mode +#define SSPCR1_SSE 0x0002 // Serial port enable +#define SSPCR1_LBM 0x0001 // Loop Back Mode + +// SSPSR Status register +#define SSPSR_BSY 0x0010 // Busy +#define SSPSR_RFF 0x0008 // Receive FIFO full +#define SSPSR_RNE 0x0004 // Receive FIFO not empty +#define SSPSR_TNF 0x0002 // Transmit FIFO not full +#define SSPSR_TFE 0x0001 // Transmit FIFO empty + +// SSPCPSR Clock prescale register +#define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8 + +// SSPIMSC Interrupt mask set and clear register +#define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked +#define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked +#define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked +#define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked + +// SSPRIS Raw interrupt status register +#define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag +#define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag +#define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag +#define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag + +// SSPMIS Masked interrupt status register +#define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag +#define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag +#define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag +#define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag + +// SSPICR Interrupt clear register +#define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag +#define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag + +// SSPDMACR DMA control register +#define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA +#define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA + +// SPICS register (0=Chip Select low) +#define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS) + +// SPI defaults +#define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS) + +// EEPROM instruction set +#define EEWRSR 0x0001 // Write status +#define EEWRITE 0x0002 // Write data +#define EEREAD 0x0003 // Read data +#define EEWDI 0x0004 // Write disable +#define EEWREN 0x0006 // Write enable +#define EERDSR 0x0005 // Read status + +// EEPROM status register flags +#define EERDSR_WIP 0x0001 // Write in process +#define EERDSR_WEL 0x0002 // Write enable latch +#define EERDSR_BP0 0x0004 // Block protect 0 +#define EERDSR_BP1 0x0008 // Block protect 1 +#define EERDSR_WPEN 0x0080 // Write protect enable + + /* ---------------------------------------------------------------- + * + * Color LCD Support + * ================= + */ + +// Color LCD Controller Internal Register addresses +#define LSSPCS_BASE (0x4002804C) // LSSP chip select register +#define LSSP_BASE (0x40021000) // LSSP Prime Cell + +#define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00)) +#define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04)) +#define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08)) +#define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C)) +#define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10)) +#define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14)) +#define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18)) +#define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C)) +#define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20)) +#define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24)) +#define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE)) + +// LSSPCR0 Control register 0 +#define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR)) +#define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase +#define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity +#define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola +#define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits +#define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits + +// LSSPCR1 Control register 1 +#define LSSPCR1_SOD 0x0008 // Slave Output mode Disable +#define LSSPCR1_MS 0x0004 // Master or Slave mode +#define LSSPCR1_SSE 0x0002 // Serial port enable +#define LSSPCR1_LBM 0x0001 // Loop Back Mode + +// LSSPSR Status register +#define LSSPSR_BSY 0x0010 // Busy +#define LSSPSR_RFF 0x0008 // Receive FIFO full +#define LSSPSR_RNE 0x0004 // Receive FIFO not empty +#define LSSPSR_TNF 0x0002 // Transmit FIFO not full +#define LSSPSR_TFE 0x0001 // Transmit FIFO empty + +// LSSPCPSR Clock prescale register +#define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR) + +// SPICS register +#define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS) +#define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS) +#define LCD_RESET 0x0008 // RESET (CLCD_RESET) +#define LCD_RS 0x0010 // RS (CLCD_RS) +#define LCD_RD 0x0020 // RD (CLCD_RD) +#define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL) + +// SPI defaults +#define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS) +#define LSPI_START (0x70) // Start byte for SPI transfer +#define LSPI_RD (0x01) // WR bit 1 within start +#define LSPI_WR (0x00) // WR bit 0 within start +#define LSPI_DATA (0x02) // RS bit 1 within start byte +#define LSPI_INDEX (0x00) // RS bit 0 within start byte + +// Screen size +#define LCD_WIDTH 320 // Screen Width (in pixels) +#define LCD_HEIGHT 240 // Screen Height (in pixels)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c Thu Jul 02 16:15:09 2015 +0100
@@ -0,0 +1,84 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+#define US_TICKER_TIMER1 CMSDK_DUALTIMER1
+#define US_TICKER_TIMER2 CMSDK_DUALTIMER2
+#define US_TICKER_TIMER_IRQn DUALTIMER_IRQn
+
+int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+ if (us_ticker_inited) return;
+ us_ticker_inited = 1;
+
+ US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
+ US_TICKER_TIMER2->TimerControl = 0x00; // disable timer
+ US_TICKER_TIMER1->TimerLoad = 0xFFFFFFFF;
+ US_TICKER_TIMER2->TimerLoad = 0xFFFFFFFF;
+
+ US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
+ US_TICKER_TIMER2->TimerControl = 0x42; // enable interrupt and set to 32 bit counter
+
+ US_TICKER_TIMER1->TimerControl |= 0x80; // enable counter
+ US_TICKER_TIMER2->TimerControl |= 0x80; // enable counter
+
+ NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+ NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+uint32_t us_ticker_read() {
+uint32_t return_value = 0;
+ if (!us_ticker_inited)
+ us_ticker_init();
+ return_value = ((~US_TICKER_TIMER2->TimerValue)/25);
+ return return_value;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp) {
+uint32_t timer_value = 0;
+int delta = 0;
+ if (!us_ticker_inited)
+ us_ticker_init();
+ delta = (int)(timestamp - us_ticker_read());
+ if (delta <= 0) {
+ // This event was in the past:
+ us_ticker_irq_handler();
+ return;
+ }
+ timer_value = (delta)*25;
+ // enable interrupt
+ US_TICKER_TIMER1->TimerControl = 0x0; // disable timer
+ US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode
+ US_TICKER_TIMER1->TimerLoad = (delta)*25; //initialise the timer value
+ US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer
+}
+
+void us_ticker_disable_interrupt(void) {
+
+ US_TICKER_TIMER1->TimerControl &= 0xDF;
+ US_TICKER_TIMER2->TimerControl &= 0xDF;
+
+}
+
+void us_ticker_clear_interrupt(void) {
+
+ US_TICKER_TIMER1->TimerIntClr = 0x1;
+ US_TICKER_TIMER2->TimerIntClr = 0x1;
+
+}