Renesas / mbed-src_GR-PEACH_rev_c

Please use mbed-src instead of this library.mbed-src supports GR-PEACH rev.C. mbed-srcライブラリをご利用ください。mbed-srcはGR-PEACH rev.Cに対応しています。

Fork of mbed-src_GR-PEACH_rev_c by GR-PEACH_producer_meeting

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c@491:affe2fb21f3a, 2015-04-06 (annotated)

Committer:
RyoheiHagimoto
Date:
Mon Apr 06 12:35:13 2015 +0000
Revision:
491:affe2fb21f3a
Parent:
482:d9a48e768ce0 
The time-out of I2C is changed to 10ms from 1s.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /**************************************************************************//**
mbed_official 390:35c2c1cf29cd 2 * @file system_MBRZA1H.c
mbed_official 390:35c2c1cf29cd 3 * @brief CMSIS Device System Source File for
mbed_official 390:35c2c1cf29cd 4 * ARMCA9 Device Series
mbed_official 390:35c2c1cf29cd 5 * @version V1.00
mbed_official 390:35c2c1cf29cd 6 * @date 19 Sept 2013
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * @note
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 11 /* Copyright (c) 2011 - 2013 ARM LIMITED
mbed_official 390:35c2c1cf29cd 12
mbed_official 390:35c2c1cf29cd 13 All rights reserved.
mbed_official 390:35c2c1cf29cd 14 Redistribution and use in source and binary forms, with or without
mbed_official 390:35c2c1cf29cd 15 modification, are permitted provided that the following conditions are met:
mbed_official 390:35c2c1cf29cd 16 - Redistributions of source code must retain the above copyright
mbed_official 390:35c2c1cf29cd 17 notice, this list of conditions and the following disclaimer.
mbed_official 390:35c2c1cf29cd 18 - Redistributions in binary form must reproduce the above copyright
mbed_official 390:35c2c1cf29cd 19 notice, this list of conditions and the following disclaimer in the
mbed_official 390:35c2c1cf29cd 20 documentation and/or other materials provided with the distribution.
mbed_official 390:35c2c1cf29cd 21 - Neither the name of ARM nor the names of its contributors may be used
mbed_official 390:35c2c1cf29cd 22 to endorse or promote products derived from this software without
mbed_official 390:35c2c1cf29cd 23 specific prior written permission.
mbed_official 390:35c2c1cf29cd 24 *
mbed_official 390:35c2c1cf29cd 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 390:35c2c1cf29cd 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 390:35c2c1cf29cd 27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 390:35c2c1cf29cd 28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 390:35c2c1cf29cd 29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 390:35c2c1cf29cd 30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 390:35c2c1cf29cd 31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 390:35c2c1cf29cd 32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 390:35c2c1cf29cd 33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 390:35c2c1cf29cd 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 390:35c2c1cf29cd 35 POSSIBILITY OF SUCH DAMAGE.
mbed_official 390:35c2c1cf29cd 36 ---------------------------------------------------------------------------*/
mbed_official 390:35c2c1cf29cd 37
mbed_official 390:35c2c1cf29cd 38
mbed_official 390:35c2c1cf29cd 39 #include <stdint.h>
mbed_official 390:35c2c1cf29cd 40 #include "MBRZA1H.h"
mbed_official 390:35c2c1cf29cd 41 #include "RZ_A1_Init.h"
mbed_official 390:35c2c1cf29cd 42
mbed_official 390:35c2c1cf29cd 43
mbed_official 482:d9a48e768ce0 44 #if defined(__ARMCC_VERSION)
mbed_official 390:35c2c1cf29cd 45 extern void $Super$$main(void);
mbed_official 390:35c2c1cf29cd 46 __asm void FPUEnable(void);
mbed_official 482:d9a48e768ce0 47 #else
mbed_official 482:d9a48e768ce0 48 void FPUEnable(void);
mbed_official 482:d9a48e768ce0 49
mbed_official 482:d9a48e768ce0 50 #endif
mbed_official 390:35c2c1cf29cd 51
mbed_official 390:35c2c1cf29cd 52 uint32_t IRQNestLevel;
mbed_official 390:35c2c1cf29cd 53
mbed_official 390:35c2c1cf29cd 54
mbed_official 482:d9a48e768ce0 55 #if defined(__ARMCC_VERSION)
mbed_official 390:35c2c1cf29cd 56 /**
mbed_official 390:35c2c1cf29cd 57 * Initialize the cache.
mbed_official 390:35c2c1cf29cd 58 *
mbed_official 390:35c2c1cf29cd 59 * @param none
mbed_official 390:35c2c1cf29cd 60 * @return none
mbed_official 390:35c2c1cf29cd 61 *
mbed_official 390:35c2c1cf29cd 62 * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
mbed_official 390:35c2c1cf29cd 63 */
mbed_official 390:35c2c1cf29cd 64 #pragma push
mbed_official 390:35c2c1cf29cd 65 #pragma arm
mbed_official 390:35c2c1cf29cd 66
mbed_official 390:35c2c1cf29cd 67 void InitMemorySubsystem(void) {
mbed_official 390:35c2c1cf29cd 68
mbed_official 390:35c2c1cf29cd 69 /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
mbed_official 390:35c2c1cf29cd 70 * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
mbed_official 390:35c2c1cf29cd 71 * You are not required to invalidate the main TLB, even though it is recommended for safety
mbed_official 390:35c2c1cf29cd 72 * reasons. This ensures compatibility with future revisions of the processor. */
mbed_official 390:35c2c1cf29cd 73
mbed_official 390:35c2c1cf29cd 74 unsigned int l2_id;
mbed_official 390:35c2c1cf29cd 75
mbed_official 390:35c2c1cf29cd 76 /* Invalidate undefined data */
mbed_official 390:35c2c1cf29cd 77 __ca9u_inv_tlb_all();
mbed_official 390:35c2c1cf29cd 78 __v7_inv_icache_all();
mbed_official 390:35c2c1cf29cd 79 __v7_inv_dcache_all();
mbed_official 390:35c2c1cf29cd 80 __v7_inv_btac();
mbed_official 390:35c2c1cf29cd 81
mbed_official 390:35c2c1cf29cd 82 /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
mbed_official 390:35c2c1cf29cd 83 * invalidate in order to flush the valid data to the next level cache.
mbed_official 390:35c2c1cf29cd 84 */
mbed_official 390:35c2c1cf29cd 85 __enable_mmu();
mbed_official 390:35c2c1cf29cd 86
mbed_official 390:35c2c1cf29cd 87 /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
mbed_official 390:35c2c1cf29cd 88 __enable_caches();
mbed_official 390:35c2c1cf29cd 89 __enable_btac();
mbed_official 390:35c2c1cf29cd 90
mbed_official 390:35c2c1cf29cd 91 /* If present, you may also need to Invalidate and Enable L2 cache here */
mbed_official 390:35c2c1cf29cd 92 l2_id = PL310_GetID();
mbed_official 390:35c2c1cf29cd 93 if (l2_id)
mbed_official 390:35c2c1cf29cd 94 {
mbed_official 390:35c2c1cf29cd 95 PL310_InvAllByWay();
mbed_official 390:35c2c1cf29cd 96 PL310_Enable();
mbed_official 390:35c2c1cf29cd 97 }
mbed_official 390:35c2c1cf29cd 98 }
mbed_official 390:35c2c1cf29cd 99 #pragma pop
mbed_official 390:35c2c1cf29cd 100
mbed_official 482:d9a48e768ce0 101 #elif defined(__GNUC__)
mbed_official 482:d9a48e768ce0 102
mbed_official 482:d9a48e768ce0 103 void InitMemorySubsystem(void) {
mbed_official 482:d9a48e768ce0 104
mbed_official 482:d9a48e768ce0 105 /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
mbed_official 482:d9a48e768ce0 106 * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
mbed_official 482:d9a48e768ce0 107 * You are not required to invalidate the main TLB, even though it is recommended for safety
mbed_official 482:d9a48e768ce0 108 * reasons. This ensures compatibility with future revisions of the processor. */
mbed_official 482:d9a48e768ce0 109
mbed_official 482:d9a48e768ce0 110 unsigned int l2_id;
mbed_official 482:d9a48e768ce0 111
mbed_official 482:d9a48e768ce0 112 /* Invalidate undefined data */
mbed_official 482:d9a48e768ce0 113 __ca9u_inv_tlb_all();
mbed_official 482:d9a48e768ce0 114 __v7_inv_icache_all();
mbed_official 482:d9a48e768ce0 115 __v7_inv_dcache_all();
mbed_official 482:d9a48e768ce0 116 __v7_inv_btac();
mbed_official 482:d9a48e768ce0 117
mbed_official 482:d9a48e768ce0 118 /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
mbed_official 482:d9a48e768ce0 119 * invalidate in order to flush the valid data to the next level cache.
mbed_official 482:d9a48e768ce0 120 */
mbed_official 482:d9a48e768ce0 121 __enable_mmu();
mbed_official 482:d9a48e768ce0 122
mbed_official 482:d9a48e768ce0 123 /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
mbed_official 482:d9a48e768ce0 124 __enable_caches();
mbed_official 482:d9a48e768ce0 125 __enable_btac();
mbed_official 482:d9a48e768ce0 126
mbed_official 482:d9a48e768ce0 127 /* If present, you may also need to Invalidate and Enable L2 cache here */
mbed_official 482:d9a48e768ce0 128 l2_id = PL310_GetID();
mbed_official 482:d9a48e768ce0 129 if (l2_id)
mbed_official 482:d9a48e768ce0 130 {
mbed_official 482:d9a48e768ce0 131 PL310_InvAllByWay();
mbed_official 482:d9a48e768ce0 132 PL310_Enable();
mbed_official 482:d9a48e768ce0 133 }
mbed_official 482:d9a48e768ce0 134 }
mbed_official 482:d9a48e768ce0 135 #else
mbed_official 482:d9a48e768ce0 136
mbed_official 482:d9a48e768ce0 137 #endif
mbed_official 482:d9a48e768ce0 138
mbed_official 482:d9a48e768ce0 139
mbed_official 390:35c2c1cf29cd 140 IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
mbed_official 390:35c2c1cf29cd 141
mbed_official 390:35c2c1cf29cd 142 uint32_t IRQCount = sizeof IRQTable / 4;
mbed_official 390:35c2c1cf29cd 143
mbed_official 390:35c2c1cf29cd 144 uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
mbed_official 390:35c2c1cf29cd 145 {
mbed_official 390:35c2c1cf29cd 146 if (irq < IRQCount) {
mbed_official 390:35c2c1cf29cd 147 IRQTable[irq] = handler;
mbed_official 390:35c2c1cf29cd 148 return 0;
mbed_official 390:35c2c1cf29cd 149 }
mbed_official 390:35c2c1cf29cd 150 else {
mbed_official 390:35c2c1cf29cd 151 return 1;
mbed_official 390:35c2c1cf29cd 152 }
mbed_official 390:35c2c1cf29cd 153 }
mbed_official 390:35c2c1cf29cd 154
mbed_official 390:35c2c1cf29cd 155 uint32_t InterruptHandlerUnregister (IRQn_Type irq)
mbed_official 390:35c2c1cf29cd 156 {
mbed_official 390:35c2c1cf29cd 157 if (irq < IRQCount) {
mbed_official 390:35c2c1cf29cd 158 IRQTable[irq] = 0;
mbed_official 390:35c2c1cf29cd 159 return 0;
mbed_official 390:35c2c1cf29cd 160 }
mbed_official 390:35c2c1cf29cd 161 else {
mbed_official 390:35c2c1cf29cd 162 return 1;
mbed_official 390:35c2c1cf29cd 163 }
mbed_official 390:35c2c1cf29cd 164 }
mbed_official 390:35c2c1cf29cd 165
mbed_official 390:35c2c1cf29cd 166 /**
mbed_official 390:35c2c1cf29cd 167 * Initialize the system
mbed_official 390:35c2c1cf29cd 168 *
mbed_official 390:35c2c1cf29cd 169 * @param none
mbed_official 390:35c2c1cf29cd 170 * @return none
mbed_official 390:35c2c1cf29cd 171 *
mbed_official 390:35c2c1cf29cd 172 * @brief Setup the microcontroller system.
mbed_official 390:35c2c1cf29cd 173 * Initialize the System.
mbed_official 390:35c2c1cf29cd 174 */
mbed_official 390:35c2c1cf29cd 175 void SystemInit (void)
mbed_official 390:35c2c1cf29cd 176 {
mbed_official 390:35c2c1cf29cd 177 IRQNestLevel = 0;
mbed_official 390:35c2c1cf29cd 178 /* do not use global variables because this function is called before
mbed_official 390:35c2c1cf29cd 179 reaching pre-main. RW section maybe overwritten afterwards. */
mbed_official 390:35c2c1cf29cd 180 RZ_A1_InitClock();
mbed_official 390:35c2c1cf29cd 181 RZ_A1_InitBus();
mbed_official 390:35c2c1cf29cd 182
mbed_official 390:35c2c1cf29cd 183 //Configure GIC ICDICFR GIC_SetICDICFR()
mbed_official 390:35c2c1cf29cd 184 GIC_Enable();
mbed_official 390:35c2c1cf29cd 185 __enable_irq();
mbed_official 390:35c2c1cf29cd 186
mbed_official 390:35c2c1cf29cd 187 }
mbed_official 390:35c2c1cf29cd 188
mbed_official 390:35c2c1cf29cd 189
mbed_official 390:35c2c1cf29cd 190 //Fault Status Register (IFSR/DFSR) definitions
mbed_official 390:35c2c1cf29cd 191 #define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
mbed_official 390:35c2c1cf29cd 192 #define FSR_INSTRUCTION_CACHE_MAINTAINANCE 0x04 //DFSR only - async/external
mbed_official 390:35c2c1cf29cd 193 #define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
mbed_official 390:35c2c1cf29cd 194 #define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
mbed_official 390:35c2c1cf29cd 195 #define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
mbed_official 390:35c2c1cf29cd 196 #define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
mbed_official 390:35c2c1cf29cd 197 #define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 198 #define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 199 #define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 200 #define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 201 #define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 202 #define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 203 #define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 204 #define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 205 #define FSR_DEBUG_EVENT 0x02 //internal
mbed_official 390:35c2c1cf29cd 206 #define FSR_SYNC_EXT_ABORT 0x08 //sync/external
mbed_official 390:35c2c1cf29cd 207 #define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
mbed_official 390:35c2c1cf29cd 208 #define FSR_LOCKDOWN 0x14 //internal
mbed_official 390:35c2c1cf29cd 209 #define FSR_COPROCESSOR_ABORT 0x1a //internal
mbed_official 390:35c2c1cf29cd 210 #define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
mbed_official 390:35c2c1cf29cd 211 #define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
mbed_official 390:35c2c1cf29cd 212 #define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
mbed_official 390:35c2c1cf29cd 213
mbed_official 390:35c2c1cf29cd 214 void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
mbed_official 390:35c2c1cf29cd 215 uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
mbed_official 390:35c2c1cf29cd 216
mbed_official 390:35c2c1cf29cd 217 switch(FS) {
mbed_official 390:35c2c1cf29cd 218 //Synchronous parity errors - retry
mbed_official 390:35c2c1cf29cd 219 case FSR_SYNC_PARITY_ERROR:
mbed_official 390:35c2c1cf29cd 220 case FSR_SYNC_PARITY_TTB_WALK_FIRST:
mbed_official 390:35c2c1cf29cd 221 case FSR_SYNC_PARITY_TTB_WALK_SECOND:
mbed_official 390:35c2c1cf29cd 222 return;
mbed_official 390:35c2c1cf29cd 223
mbed_official 390:35c2c1cf29cd 224 //Your code here. Value in DFAR is invalid for some fault statuses.
mbed_official 390:35c2c1cf29cd 225 case FSR_ALIGNMENT_FAULT:
mbed_official 390:35c2c1cf29cd 226 case FSR_INSTRUCTION_CACHE_MAINTAINANCE:
mbed_official 390:35c2c1cf29cd 227 case FSR_SYNC_EXT_TTB_WALK_FIRST:
mbed_official 390:35c2c1cf29cd 228 case FSR_SYNC_EXT_TTB_WALK_SECOND:
mbed_official 390:35c2c1cf29cd 229 case FSR_TRANSLATION_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 230 case FSR_TRANSLATION_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 231 case FSR_ACCESS_FLAG_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 232 case FSR_ACCESS_FLAG_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 233 case FSR_DOMAIN_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 234 case FSR_DOMAIN_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 235 case FSR_PERMISION_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 236 case FSR_PERMISION_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 237 case FSR_DEBUG_EVENT:
mbed_official 390:35c2c1cf29cd 238 case FSR_SYNC_EXT_ABORT:
mbed_official 390:35c2c1cf29cd 239 case FSR_TLB_CONFLICT_ABORT:
mbed_official 390:35c2c1cf29cd 240 case FSR_LOCKDOWN:
mbed_official 390:35c2c1cf29cd 241 case FSR_COPROCESSOR_ABORT:
mbed_official 390:35c2c1cf29cd 242 case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
mbed_official 390:35c2c1cf29cd 243 case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
mbed_official 390:35c2c1cf29cd 244 default:
mbed_official 390:35c2c1cf29cd 245 while(1);
mbed_official 390:35c2c1cf29cd 246 }
mbed_official 390:35c2c1cf29cd 247 }
mbed_official 390:35c2c1cf29cd 248
mbed_official 390:35c2c1cf29cd 249 void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
mbed_official 390:35c2c1cf29cd 250 uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
mbed_official 390:35c2c1cf29cd 251
mbed_official 390:35c2c1cf29cd 252 switch(FS) {
mbed_official 390:35c2c1cf29cd 253 //Synchronous parity errors - retry
mbed_official 390:35c2c1cf29cd 254 case FSR_SYNC_PARITY_ERROR:
mbed_official 390:35c2c1cf29cd 255 case FSR_SYNC_PARITY_TTB_WALK_FIRST:
mbed_official 390:35c2c1cf29cd 256 case FSR_SYNC_PARITY_TTB_WALK_SECOND:
mbed_official 390:35c2c1cf29cd 257 return;
mbed_official 390:35c2c1cf29cd 258
mbed_official 390:35c2c1cf29cd 259 //Your code here. Value in IFAR is invalid for some fault statuses.
mbed_official 390:35c2c1cf29cd 260 case FSR_SYNC_EXT_TTB_WALK_FIRST:
mbed_official 390:35c2c1cf29cd 261 case FSR_SYNC_EXT_TTB_WALK_SECOND:
mbed_official 390:35c2c1cf29cd 262 case FSR_TRANSLATION_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 263 case FSR_TRANSLATION_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 264 case FSR_ACCESS_FLAG_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 265 case FSR_ACCESS_FLAG_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 266 case FSR_DOMAIN_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 267 case FSR_DOMAIN_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 268 case FSR_PERMISION_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 269 case FSR_PERMISION_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 270 case FSR_DEBUG_EVENT: //IFAR invalid
mbed_official 390:35c2c1cf29cd 271 case FSR_SYNC_EXT_ABORT:
mbed_official 390:35c2c1cf29cd 272 case FSR_TLB_CONFLICT_ABORT:
mbed_official 390:35c2c1cf29cd 273 case FSR_LOCKDOWN:
mbed_official 390:35c2c1cf29cd 274 case FSR_COPROCESSOR_ABORT:
mbed_official 390:35c2c1cf29cd 275 default:
mbed_official 390:35c2c1cf29cd 276 while(1);
mbed_official 390:35c2c1cf29cd 277 }
mbed_official 390:35c2c1cf29cd 278 }
mbed_official 390:35c2c1cf29cd 279
mbed_official 390:35c2c1cf29cd 280 //returns amount to decrement lr by
mbed_official 390:35c2c1cf29cd 281 //this will be 0 when we have emulated the instruction and simply want to execute the next instruction
mbed_official 390:35c2c1cf29cd 282 //this will be 2 when we have performed some maintenance and want to retry the instruction in thumb (state == 2)
mbed_official 390:35c2c1cf29cd 283 //this will be 4 when we have performed some maintenance and want to retry the instruction in arm (state == 4)
mbed_official 390:35c2c1cf29cd 284 uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
mbed_official 482:d9a48e768ce0 285 const unsigned int THUMB = 2;
mbed_official 482:d9a48e768ce0 286 const unsigned int ARM = 4;
mbed_official 390:35c2c1cf29cd 287 //Lazy VFP/NEON initialisation and switching
mbed_official 390:35c2c1cf29cd 288 if ((state == ARM && ((opcode & 0x0C000000)) >> 26 == 0x03) ||
mbed_official 390:35c2c1cf29cd 289 (state == THUMB && ((opcode & 0xEC000000)) >> 26 == 0x3B)) {
mbed_official 390:35c2c1cf29cd 290 if (((opcode & 0x00000E00) >> 9) == 5) { //fp instruction?
mbed_official 390:35c2c1cf29cd 291 FPUEnable();
mbed_official 390:35c2c1cf29cd 292 return state;
mbed_official 390:35c2c1cf29cd 293 }
mbed_official 390:35c2c1cf29cd 294 }
mbed_official 390:35c2c1cf29cd 295
mbed_official 390:35c2c1cf29cd 296 //Add code here for other Undef cases
mbed_official 390:35c2c1cf29cd 297 while(1);
mbed_official 390:35c2c1cf29cd 298 }
mbed_official 390:35c2c1cf29cd 299
mbed_official 482:d9a48e768ce0 300 #if defined(__ARMCC_VERSION)
mbed_official 390:35c2c1cf29cd 301 #pragma push
mbed_official 390:35c2c1cf29cd 302 #pragma arm
mbed_official 390:35c2c1cf29cd 303 //Critical section, called from undef handler, so systick is disabled
mbed_official 390:35c2c1cf29cd 304 __asm void FPUEnable(void) {
mbed_official 390:35c2c1cf29cd 305 ARM
mbed_official 390:35c2c1cf29cd 306
mbed_official 390:35c2c1cf29cd 307 //Permit access to VFP registers by modifying CPACR
mbed_official 390:35c2c1cf29cd 308 MRC p15,0,R1,c1,c0,2
mbed_official 390:35c2c1cf29cd 309 ORR R1,R1,#0x00F00000
mbed_official 390:35c2c1cf29cd 310 MCR p15,0,R1,c1,c0,2
mbed_official 390:35c2c1cf29cd 311
mbed_official 390:35c2c1cf29cd 312 //Enable VFP
mbed_official 390:35c2c1cf29cd 313 VMRS R1,FPEXC
mbed_official 390:35c2c1cf29cd 314 ORR R1,R1,#0x40000000
mbed_official 390:35c2c1cf29cd 315 VMSR FPEXC,R1
mbed_official 390:35c2c1cf29cd 316
mbed_official 390:35c2c1cf29cd 317 //Initialise VFP registers to 0
mbed_official 390:35c2c1cf29cd 318 MOV R2,#0
mbed_official 390:35c2c1cf29cd 319 VMOV D0, R2,R2
mbed_official 390:35c2c1cf29cd 320 VMOV D1, R2,R2
mbed_official 390:35c2c1cf29cd 321 VMOV D2, R2,R2
mbed_official 390:35c2c1cf29cd 322 VMOV D3, R2,R2
mbed_official 390:35c2c1cf29cd 323 VMOV D4, R2,R2
mbed_official 390:35c2c1cf29cd 324 VMOV D5, R2,R2
mbed_official 390:35c2c1cf29cd 325 VMOV D6, R2,R2
mbed_official 390:35c2c1cf29cd 326 VMOV D7, R2,R2
mbed_official 390:35c2c1cf29cd 327 VMOV D8, R2,R2
mbed_official 390:35c2c1cf29cd 328 VMOV D9, R2,R2
mbed_official 390:35c2c1cf29cd 329 VMOV D10,R2,R2
mbed_official 390:35c2c1cf29cd 330 VMOV D11,R2,R2
mbed_official 390:35c2c1cf29cd 331 VMOV D12,R2,R2
mbed_official 390:35c2c1cf29cd 332 VMOV D13,R2,R2
mbed_official 390:35c2c1cf29cd 333 VMOV D14,R2,R2
mbed_official 390:35c2c1cf29cd 334 VMOV D15,R2,R2
mbed_official 390:35c2c1cf29cd 335
mbed_official 390:35c2c1cf29cd 336 //Initialise FPSCR to a known state
mbed_official 390:35c2c1cf29cd 337 VMRS R2,FPSCR
mbed_official 390:35c2c1cf29cd 338 LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
mbed_official 390:35c2c1cf29cd 339 AND R2,R2,R3
mbed_official 390:35c2c1cf29cd 340 VMSR FPSCR,R2
mbed_official 390:35c2c1cf29cd 341
mbed_official 390:35c2c1cf29cd 342 BX LR
mbed_official 390:35c2c1cf29cd 343 }
mbed_official 390:35c2c1cf29cd 344 #pragma pop
mbed_official 482:d9a48e768ce0 345
mbed_official 482:d9a48e768ce0 346 #elif defined(__GNUC__)
mbed_official 482:d9a48e768ce0 347 void FPUEnable(void)
mbed_official 482:d9a48e768ce0 348 {
mbed_official 482:d9a48e768ce0 349 __asm__ __volatile__ (
mbed_official 482:d9a48e768ce0 350 ".align 2 \n\t"
mbed_official 482:d9a48e768ce0 351 ".arm \n\t"
mbed_official 482:d9a48e768ce0 352 "mrc p15,0,r1,c1,c0,2 \n\t"
mbed_official 482:d9a48e768ce0 353 "orr r1,r1,#0x00f00000 \n\t"
mbed_official 482:d9a48e768ce0 354 "mcr p15,0,r1,c1,c0,2 \n\t"
mbed_official 482:d9a48e768ce0 355 "vmrs r1,fpexc \n\t"
mbed_official 482:d9a48e768ce0 356 "orr r1,r1,#0x40000000 \n\t"
mbed_official 482:d9a48e768ce0 357 "vmsr fpexc,r1 \n\t"
mbed_official 482:d9a48e768ce0 358 "mov r2,#0 \n\t"
mbed_official 482:d9a48e768ce0 359 "vmov d0, r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 360 "vmov d1, r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 361 "vmov d2, r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 362 "vmov d3, r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 363 "vmov d4, r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 364 "vmov d5, r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 365 "vmov d6, r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 366 "vmov d7, r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 367 "vmov d8, r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 368 "vmov d9, r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 369 "vmov d10,r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 370 "vmov d11,r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 371 "vmov d12,r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 372 "vmov d13,r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 373 "vmov d14,r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 374 "vmov d15,r2,r2 \n\t"
mbed_official 482:d9a48e768ce0 375 "vmrs r2,fpscr \n\t"
mbed_official 482:d9a48e768ce0 376 "ldr r3,=0x00086060 \n\t"
mbed_official 482:d9a48e768ce0 377 "and r2,r2,r3 \n\t"
mbed_official 482:d9a48e768ce0 378 "vmsr fpscr,r2 \n\t"
mbed_official 482:d9a48e768ce0 379 "bx lr \n\t"
mbed_official 482:d9a48e768ce0 380 );
mbed_official 482:d9a48e768ce0 381 }
mbed_official 482:d9a48e768ce0 382 #else
mbed_official 482:d9a48e768ce0 383 #endif
mbed_official 482:d9a48e768ce0 384