Renesas / mbed-src_GR-PEACH_rev_c

Please use mbed-src instead of this library.mbed-src supports GR-PEACH rev.C. mbed-srcライブラリをご利用ください。mbed-srcはGR-PEACH rev.Cに対応しています。

Fork of mbed-src_GR-PEACH_rev_c by GR-PEACH_producer_meeting

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.c@491:affe2fb21f3a, 2015-04-06 (annotated)

Committer:
RyoheiHagimoto
Date:
Mon Apr 06 12:35:13 2015 +0000
Revision:
491:affe2fb21f3a
Parent:
390:35c2c1cf29cd 
The time-out of I2C is changed to 10ms from 1s.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /**************************************************************************//**
mbed_official 390:35c2c1cf29cd 2 * @file gic.c
mbed_official 390:35c2c1cf29cd 3 * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
mbed_official 390:35c2c1cf29cd 4 * @version
mbed_official 390:35c2c1cf29cd 5 * @date 19 Sept 2013
mbed_official 390:35c2c1cf29cd 6 *
mbed_official 390:35c2c1cf29cd 7 * @note
mbed_official 390:35c2c1cf29cd 8 *
mbed_official 390:35c2c1cf29cd 9 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 10 /* Copyright (c) 2011 - 2013 ARM LIMITED
mbed_official 390:35c2c1cf29cd 11
mbed_official 390:35c2c1cf29cd 12 All rights reserved.
mbed_official 390:35c2c1cf29cd 13 Redistribution and use in source and binary forms, with or without
mbed_official 390:35c2c1cf29cd 14 modification, are permitted provided that the following conditions are met:
mbed_official 390:35c2c1cf29cd 15 - Redistributions of source code must retain the above copyright
mbed_official 390:35c2c1cf29cd 16 notice, this list of conditions and the following disclaimer.
mbed_official 390:35c2c1cf29cd 17 - Redistributions in binary form must reproduce the above copyright
mbed_official 390:35c2c1cf29cd 18 notice, this list of conditions and the following disclaimer in the
mbed_official 390:35c2c1cf29cd 19 documentation and/or other materials provided with the distribution.
mbed_official 390:35c2c1cf29cd 20 - Neither the name of ARM nor the names of its contributors may be used
mbed_official 390:35c2c1cf29cd 21 to endorse or promote products derived from this software without
mbed_official 390:35c2c1cf29cd 22 specific prior written permission.
mbed_official 390:35c2c1cf29cd 23 *
mbed_official 390:35c2c1cf29cd 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 390:35c2c1cf29cd 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 390:35c2c1cf29cd 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 390:35c2c1cf29cd 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 390:35c2c1cf29cd 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 390:35c2c1cf29cd 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 390:35c2c1cf29cd 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 390:35c2c1cf29cd 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 390:35c2c1cf29cd 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 390:35c2c1cf29cd 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 390:35c2c1cf29cd 34 POSSIBILITY OF SUCH DAMAGE.
mbed_official 390:35c2c1cf29cd 35 ---------------------------------------------------------------------------*/
mbed_official 390:35c2c1cf29cd 36
mbed_official 390:35c2c1cf29cd 37 #include "MBRZA1H.h"
mbed_official 390:35c2c1cf29cd 38
mbed_official 390:35c2c1cf29cd 39 #define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
mbed_official 390:35c2c1cf29cd 40 #define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */
mbed_official 390:35c2c1cf29cd 41
mbed_official 390:35c2c1cf29cd 42 /* Globals for use of post-scatterloading code that must access GIC */
mbed_official 390:35c2c1cf29cd 43 const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE;
mbed_official 390:35c2c1cf29cd 44 const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE;
mbed_official 390:35c2c1cf29cd 45
mbed_official 390:35c2c1cf29cd 46 void GIC_EnableDistributor(void)
mbed_official 390:35c2c1cf29cd 47 {
mbed_official 390:35c2c1cf29cd 48 GICDistributor->ICDDCR |= 1; //enable distributor
mbed_official 390:35c2c1cf29cd 49 }
mbed_official 390:35c2c1cf29cd 50
mbed_official 390:35c2c1cf29cd 51 void GIC_DisableDistributor(void)
mbed_official 390:35c2c1cf29cd 52 {
mbed_official 390:35c2c1cf29cd 53 GICDistributor->ICDDCR &=~1; //disable distributor
mbed_official 390:35c2c1cf29cd 54 }
mbed_official 390:35c2c1cf29cd 55
mbed_official 390:35c2c1cf29cd 56 uint32_t GIC_DistributorInfo(void)
mbed_official 390:35c2c1cf29cd 57 {
mbed_official 390:35c2c1cf29cd 58 return (uint32_t)(GICDistributor->ICDICTR);
mbed_official 390:35c2c1cf29cd 59 }
mbed_official 390:35c2c1cf29cd 60
mbed_official 390:35c2c1cf29cd 61 uint32_t GIC_DistributorImplementer(void)
mbed_official 390:35c2c1cf29cd 62 {
mbed_official 390:35c2c1cf29cd 63 return (uint32_t)(GICDistributor->ICDIIDR);
mbed_official 390:35c2c1cf29cd 64 }
mbed_official 390:35c2c1cf29cd 65
mbed_official 390:35c2c1cf29cd 66 void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
mbed_official 390:35c2c1cf29cd 67 {
mbed_official 390:35c2c1cf29cd 68 volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
mbed_official 390:35c2c1cf29cd 69 field += IRQn % 4;
mbed_official 390:35c2c1cf29cd 70 *field = (uint8_t)cpu_target & 0xf;
mbed_official 390:35c2c1cf29cd 71 }
mbed_official 390:35c2c1cf29cd 72
mbed_official 390:35c2c1cf29cd 73 void GIC_SetICDICFR (const uint32_t *ICDICFRn)
mbed_official 390:35c2c1cf29cd 74 {
mbed_official 390:35c2c1cf29cd 75 uint32_t i, num_irq;
mbed_official 390:35c2c1cf29cd 76
mbed_official 390:35c2c1cf29cd 77 //Get the maximum number of interrupts that the GIC supports
mbed_official 390:35c2c1cf29cd 78 num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
mbed_official 390:35c2c1cf29cd 79
mbed_official 390:35c2c1cf29cd 80 for (i = 0; i < (num_irq/16); i++)
mbed_official 390:35c2c1cf29cd 81 {
mbed_official 390:35c2c1cf29cd 82 GICDistributor->ICDISPR[i] = *ICDICFRn++;
mbed_official 390:35c2c1cf29cd 83 }
mbed_official 390:35c2c1cf29cd 84 }
mbed_official 390:35c2c1cf29cd 85
mbed_official 390:35c2c1cf29cd 86 uint32_t GIC_GetTarget(IRQn_Type IRQn)
mbed_official 390:35c2c1cf29cd 87 {
mbed_official 390:35c2c1cf29cd 88 volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
mbed_official 390:35c2c1cf29cd 89 field += IRQn % 4;
mbed_official 390:35c2c1cf29cd 90 return ((uint32_t)*field & 0xf);
mbed_official 390:35c2c1cf29cd 91 }
mbed_official 390:35c2c1cf29cd 92
mbed_official 390:35c2c1cf29cd 93 void GIC_EnableInterface(void)
mbed_official 390:35c2c1cf29cd 94 {
mbed_official 390:35c2c1cf29cd 95 GICInterface->ICCICR |= 1; //enable interface
mbed_official 390:35c2c1cf29cd 96 }
mbed_official 390:35c2c1cf29cd 97
mbed_official 390:35c2c1cf29cd 98 void GIC_DisableInterface(void)
mbed_official 390:35c2c1cf29cd 99 {
mbed_official 390:35c2c1cf29cd 100 GICInterface->ICCICR &=~1; //disable distributor
mbed_official 390:35c2c1cf29cd 101 }
mbed_official 390:35c2c1cf29cd 102
mbed_official 390:35c2c1cf29cd 103 IRQn_Type GIC_AcknowledgePending(void)
mbed_official 390:35c2c1cf29cd 104 {
mbed_official 390:35c2c1cf29cd 105 return (IRQn_Type)(GICInterface->ICCIAR);
mbed_official 390:35c2c1cf29cd 106 }
mbed_official 390:35c2c1cf29cd 107
mbed_official 390:35c2c1cf29cd 108 void GIC_EndInterrupt(IRQn_Type IRQn)
mbed_official 390:35c2c1cf29cd 109 {
mbed_official 390:35c2c1cf29cd 110 GICInterface->ICCEOIR = IRQn;
mbed_official 390:35c2c1cf29cd 111 }
mbed_official 390:35c2c1cf29cd 112
mbed_official 390:35c2c1cf29cd 113 void GIC_EnableIRQ(IRQn_Type IRQn)
mbed_official 390:35c2c1cf29cd 114 {
mbed_official 390:35c2c1cf29cd 115 GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
mbed_official 390:35c2c1cf29cd 116 }
mbed_official 390:35c2c1cf29cd 117
mbed_official 390:35c2c1cf29cd 118 void GIC_DisableIRQ(IRQn_Type IRQn)
mbed_official 390:35c2c1cf29cd 119 {
mbed_official 390:35c2c1cf29cd 120 GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
mbed_official 390:35c2c1cf29cd 121 }
mbed_official 390:35c2c1cf29cd 122
mbed_official 390:35c2c1cf29cd 123 void GIC_SetPendingIRQ(IRQn_Type IRQn)
mbed_official 390:35c2c1cf29cd 124 {
mbed_official 390:35c2c1cf29cd 125 GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
mbed_official 390:35c2c1cf29cd 126 }
mbed_official 390:35c2c1cf29cd 127
mbed_official 390:35c2c1cf29cd 128 void GIC_ClearPendingIRQ(IRQn_Type IRQn)
mbed_official 390:35c2c1cf29cd 129 {
mbed_official 390:35c2c1cf29cd 130 GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
mbed_official 390:35c2c1cf29cd 131 }
mbed_official 390:35c2c1cf29cd 132
mbed_official 390:35c2c1cf29cd 133 void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
mbed_official 390:35c2c1cf29cd 134 {
mbed_official 390:35c2c1cf29cd 135 volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]);
mbed_official 390:35c2c1cf29cd 136 int bit_shift = (IRQn % 16)<<1;
mbed_official 390:35c2c1cf29cd 137 uint8_t save_byte;
mbed_official 390:35c2c1cf29cd 138
mbed_official 390:35c2c1cf29cd 139 field += (bit_shift / 8);
mbed_official 390:35c2c1cf29cd 140 bit_shift %= 8;
mbed_official 390:35c2c1cf29cd 141
mbed_official 390:35c2c1cf29cd 142 save_byte = *field;
mbed_official 390:35c2c1cf29cd 143 save_byte &= ((uint8_t)~(3u << bit_shift));
mbed_official 390:35c2c1cf29cd 144
mbed_official 390:35c2c1cf29cd 145 *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift);
mbed_official 390:35c2c1cf29cd 146 }
mbed_official 390:35c2c1cf29cd 147
mbed_official 390:35c2c1cf29cd 148 void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mbed_official 390:35c2c1cf29cd 149 {
mbed_official 390:35c2c1cf29cd 150 volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
mbed_official 390:35c2c1cf29cd 151 field += (IRQn % 4);
mbed_official 390:35c2c1cf29cd 152 *field = (uint8_t)priority;
mbed_official 390:35c2c1cf29cd 153 }
mbed_official 390:35c2c1cf29cd 154
mbed_official 390:35c2c1cf29cd 155 uint32_t GIC_GetPriority(IRQn_Type IRQn)
mbed_official 390:35c2c1cf29cd 156 {
mbed_official 390:35c2c1cf29cd 157 volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
mbed_official 390:35c2c1cf29cd 158 field += (IRQn % 4);
mbed_official 390:35c2c1cf29cd 159 return (uint32_t)*field;
mbed_official 390:35c2c1cf29cd 160 }
mbed_official 390:35c2c1cf29cd 161
mbed_official 390:35c2c1cf29cd 162 void GIC_InterfacePriorityMask(uint32_t priority)
mbed_official 390:35c2c1cf29cd 163 {
mbed_official 390:35c2c1cf29cd 164 GICInterface->ICCPMR = priority & 0xff; //set priority mask
mbed_official 390:35c2c1cf29cd 165 }
mbed_official 390:35c2c1cf29cd 166
mbed_official 390:35c2c1cf29cd 167 void GIC_SetBinaryPoint(uint32_t binary_point)
mbed_official 390:35c2c1cf29cd 168 {
mbed_official 390:35c2c1cf29cd 169 GICInterface->ICCBPR = binary_point & 0x07; //set binary point
mbed_official 390:35c2c1cf29cd 170 }
mbed_official 390:35c2c1cf29cd 171
mbed_official 390:35c2c1cf29cd 172 uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
mbed_official 390:35c2c1cf29cd 173 {
mbed_official 390:35c2c1cf29cd 174 return (uint32_t)GICInterface->ICCBPR;
mbed_official 390:35c2c1cf29cd 175 }
mbed_official 390:35c2c1cf29cd 176
mbed_official 390:35c2c1cf29cd 177 uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
mbed_official 390:35c2c1cf29cd 178 {
mbed_official 390:35c2c1cf29cd 179 uint32_t pending, active;
mbed_official 390:35c2c1cf29cd 180
mbed_official 390:35c2c1cf29cd 181 active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
mbed_official 390:35c2c1cf29cd 182 pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
mbed_official 390:35c2c1cf29cd 183
mbed_official 390:35c2c1cf29cd 184 return ((active<<1) | pending);
mbed_official 390:35c2c1cf29cd 185 }
mbed_official 390:35c2c1cf29cd 186
mbed_official 390:35c2c1cf29cd 187 void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
mbed_official 390:35c2c1cf29cd 188 {
mbed_official 390:35c2c1cf29cd 189 GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
mbed_official 390:35c2c1cf29cd 190 }
mbed_official 390:35c2c1cf29cd 191
mbed_official 390:35c2c1cf29cd 192 void GIC_DistInit(void)
mbed_official 390:35c2c1cf29cd 193 {
mbed_official 390:35c2c1cf29cd 194 //IRQn_Type i;
mbed_official 390:35c2c1cf29cd 195 uint32_t i;
mbed_official 390:35c2c1cf29cd 196 uint32_t num_irq = 0;
mbed_official 390:35c2c1cf29cd 197 uint32_t priority_field;
mbed_official 390:35c2c1cf29cd 198
mbed_official 390:35c2c1cf29cd 199 //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
mbed_official 390:35c2c1cf29cd 200 //configuring all of the interrupts as Secure.
mbed_official 390:35c2c1cf29cd 201
mbed_official 390:35c2c1cf29cd 202 //Disable interrupt forwarding
mbed_official 390:35c2c1cf29cd 203 GIC_DisableDistributor();
mbed_official 390:35c2c1cf29cd 204 //Get the maximum number of interrupts that the GIC supports
mbed_official 390:35c2c1cf29cd 205 num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
mbed_official 390:35c2c1cf29cd 206
mbed_official 390:35c2c1cf29cd 207 /* Priority level is implementation defined.
mbed_official 390:35c2c1cf29cd 208 To determine the number of priority bits implemented write 0xFF to an ICDIPR
mbed_official 390:35c2c1cf29cd 209 priority field and read back the value stored.*/
mbed_official 390:35c2c1cf29cd 210 GIC_SetPriority((IRQn_Type)0, 0xff);
mbed_official 390:35c2c1cf29cd 211 priority_field = GIC_GetPriority((IRQn_Type)0);
mbed_official 390:35c2c1cf29cd 212
mbed_official 390:35c2c1cf29cd 213 for (i = 32; i < num_irq; i++)
mbed_official 390:35c2c1cf29cd 214 {
mbed_official 390:35c2c1cf29cd 215 //Disable all SPI the interrupts
mbed_official 390:35c2c1cf29cd 216 GIC_DisableIRQ((IRQn_Type)i);
mbed_official 390:35c2c1cf29cd 217 //Set level-sensitive and N-N model
mbed_official 390:35c2c1cf29cd 218 //GIC_SetLevelModel(i, 0, 0);
mbed_official 390:35c2c1cf29cd 219 //Set priority
mbed_official 390:35c2c1cf29cd 220 GIC_SetPriority((IRQn_Type)i, priority_field/2);
mbed_official 390:35c2c1cf29cd 221 //Set target list to "all cpus"
mbed_official 390:35c2c1cf29cd 222 GIC_SetTarget((IRQn_Type)i, 0xff);
mbed_official 390:35c2c1cf29cd 223 }
mbed_official 390:35c2c1cf29cd 224 /* Set level-edge and 1-N model */
mbed_official 390:35c2c1cf29cd 225 /* GICDistributor->ICDICFR[ 0] is read only */
mbed_official 390:35c2c1cf29cd 226 GICDistributor->ICDICFR[ 1] = 0x00000055;
mbed_official 390:35c2c1cf29cd 227 GICDistributor->ICDICFR[ 2] = 0xFFFD5555;
mbed_official 390:35c2c1cf29cd 228 GICDistributor->ICDICFR[ 3] = 0x555FFFFF;
mbed_official 390:35c2c1cf29cd 229 GICDistributor->ICDICFR[ 4] = 0x55555555;
mbed_official 390:35c2c1cf29cd 230 GICDistributor->ICDICFR[ 5] = 0x55555555;
mbed_official 390:35c2c1cf29cd 231 GICDistributor->ICDICFR[ 6] = 0x55555555;
mbed_official 390:35c2c1cf29cd 232 GICDistributor->ICDICFR[ 7] = 0x55555555;
mbed_official 390:35c2c1cf29cd 233 GICDistributor->ICDICFR[ 8] = 0x5555F555;
mbed_official 390:35c2c1cf29cd 234 GICDistributor->ICDICFR[ 9] = 0x55555555;
mbed_official 390:35c2c1cf29cd 235 GICDistributor->ICDICFR[10] = 0x55555555;
mbed_official 390:35c2c1cf29cd 236 GICDistributor->ICDICFR[11] = 0xF5555555;
mbed_official 390:35c2c1cf29cd 237 GICDistributor->ICDICFR[12] = 0xF555F555;
mbed_official 390:35c2c1cf29cd 238 GICDistributor->ICDICFR[13] = 0x5555F555;
mbed_official 390:35c2c1cf29cd 239 GICDistributor->ICDICFR[14] = 0x55555555;
mbed_official 390:35c2c1cf29cd 240 GICDistributor->ICDICFR[15] = 0x55555555;
mbed_official 390:35c2c1cf29cd 241 GICDistributor->ICDICFR[16] = 0x55555555;
mbed_official 390:35c2c1cf29cd 242 GICDistributor->ICDICFR[17] = 0xFD555555;
mbed_official 390:35c2c1cf29cd 243 GICDistributor->ICDICFR[18] = 0x55555557;
mbed_official 390:35c2c1cf29cd 244 GICDistributor->ICDICFR[19] = 0x55555555;
mbed_official 390:35c2c1cf29cd 245 GICDistributor->ICDICFR[20] = 0xFFD55555;
mbed_official 390:35c2c1cf29cd 246 GICDistributor->ICDICFR[21] = 0x5F55557F;
mbed_official 390:35c2c1cf29cd 247 GICDistributor->ICDICFR[22] = 0xFD55555F;
mbed_official 390:35c2c1cf29cd 248 GICDistributor->ICDICFR[23] = 0x55555557;
mbed_official 390:35c2c1cf29cd 249 GICDistributor->ICDICFR[24] = 0x55555555;
mbed_official 390:35c2c1cf29cd 250 GICDistributor->ICDICFR[25] = 0x55555555;
mbed_official 390:35c2c1cf29cd 251 GICDistributor->ICDICFR[26] = 0x55555555;
mbed_official 390:35c2c1cf29cd 252 GICDistributor->ICDICFR[27] = 0x55555555;
mbed_official 390:35c2c1cf29cd 253 GICDistributor->ICDICFR[28] = 0x55555555;
mbed_official 390:35c2c1cf29cd 254 GICDistributor->ICDICFR[29] = 0x55555555;
mbed_official 390:35c2c1cf29cd 255 GICDistributor->ICDICFR[30] = 0x55555555;
mbed_official 390:35c2c1cf29cd 256 GICDistributor->ICDICFR[31] = 0x55555555;
mbed_official 390:35c2c1cf29cd 257 GICDistributor->ICDICFR[32] = 0x55555555;
mbed_official 390:35c2c1cf29cd 258 GICDistributor->ICDICFR[33] = 0x55555555;
mbed_official 390:35c2c1cf29cd 259
mbed_official 390:35c2c1cf29cd 260 //Enable distributor
mbed_official 390:35c2c1cf29cd 261 GIC_EnableDistributor();
mbed_official 390:35c2c1cf29cd 262 }
mbed_official 390:35c2c1cf29cd 263
mbed_official 390:35c2c1cf29cd 264 void GIC_CPUInterfaceInit(void)
mbed_official 390:35c2c1cf29cd 265 {
mbed_official 390:35c2c1cf29cd 266 IRQn_Type i;
mbed_official 390:35c2c1cf29cd 267 uint32_t priority_field;
mbed_official 390:35c2c1cf29cd 268
mbed_official 390:35c2c1cf29cd 269 //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
mbed_official 390:35c2c1cf29cd 270 //configuring all of the interrupts as Secure.
mbed_official 390:35c2c1cf29cd 271
mbed_official 390:35c2c1cf29cd 272 //Disable interrupt forwarding
mbed_official 390:35c2c1cf29cd 273 GIC_DisableInterface();
mbed_official 390:35c2c1cf29cd 274
mbed_official 390:35c2c1cf29cd 275 /* Priority level is implementation defined.
mbed_official 390:35c2c1cf29cd 276 To determine the number of priority bits implemented write 0xFF to an ICDIPR
mbed_official 390:35c2c1cf29cd 277 priority field and read back the value stored.*/
mbed_official 390:35c2c1cf29cd 278 GIC_SetPriority((IRQn_Type)0, 0xff);
mbed_official 390:35c2c1cf29cd 279 priority_field = GIC_GetPriority((IRQn_Type)0);
mbed_official 390:35c2c1cf29cd 280
mbed_official 390:35c2c1cf29cd 281 //SGI and PPI
mbed_official 390:35c2c1cf29cd 282 for (i = (IRQn_Type)0; i < 32; i++)
mbed_official 390:35c2c1cf29cd 283 {
mbed_official 390:35c2c1cf29cd 284 //Set level-sensitive and N-N model for PPI
mbed_official 390:35c2c1cf29cd 285 //if(i > 15)
mbed_official 390:35c2c1cf29cd 286 //GIC_SetLevelModel(i, 0, 0);
mbed_official 390:35c2c1cf29cd 287 //Disable SGI and PPI interrupts
mbed_official 390:35c2c1cf29cd 288 GIC_DisableIRQ(i);
mbed_official 390:35c2c1cf29cd 289 //Set priority
mbed_official 390:35c2c1cf29cd 290 GIC_SetPriority(i, priority_field/2);
mbed_official 390:35c2c1cf29cd 291 }
mbed_official 390:35c2c1cf29cd 292 //Enable interface
mbed_official 390:35c2c1cf29cd 293 GIC_EnableInterface();
mbed_official 390:35c2c1cf29cd 294 //Set binary point to 0
mbed_official 390:35c2c1cf29cd 295 GIC_SetBinaryPoint(0);
mbed_official 390:35c2c1cf29cd 296 //Set priority mask
mbed_official 390:35c2c1cf29cd 297 GIC_InterfacePriorityMask(0xff);
mbed_official 390:35c2c1cf29cd 298 }
mbed_official 390:35c2c1cf29cd 299
mbed_official 390:35c2c1cf29cd 300 void GIC_Enable(void)
mbed_official 390:35c2c1cf29cd 301 {
mbed_official 390:35c2c1cf29cd 302 GIC_DistInit();
mbed_official 390:35c2c1cf29cd 303 GIC_CPUInterfaceInit(); //per CPU
mbed_official 390:35c2c1cf29cd 304 }
mbed_official 390:35c2c1cf29cd 305