Renesas / mbed-src_GR-PEACH_rev_c

Please use mbed-src instead of this library.mbed-src supports GR-PEACH rev.C. mbed-srcライブラリをご利用ください。mbed-srcはGR-PEACH rev.Cに対応しています。

Fork of mbed-src_GR-PEACH_rev_c by GR-PEACH_producer_meeting

targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.c@491:affe2fb21f3a, 2015-04-06 (annotated)

Committer:
RyoheiHagimoto
Date:
Mon Apr 06 12:35:13 2015 +0000
Revision:
491:affe2fb21f3a
Parent:
358:9d7ef901f004 
The time-out of I2C is changed to 10ms from 1s.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 358:9d7ef901f004 1 /* mbed Microcontroller Library
mbed_official 358:9d7ef901f004 2 * CMSIS-style functionality to support dynamic vectors
mbed_official 358:9d7ef901f004 3 *******************************************************************************
bogdanm 13:0645d8841f51 4 * Copyright (c) 2011 ARM Limited. All rights reserved.
mbed_official 358:9d7ef901f004 5 * All rights reserved.
mbed_official 358:9d7ef901f004 6 *
mbed_official 358:9d7ef901f004 7 * Redistribution and use in source and binary forms, with or without
mbed_official 358:9d7ef901f004 8 * modification, are permitted provided that the following conditions are met:
bogdanm 13:0645d8841f51 9 *
mbed_official 358:9d7ef901f004 10 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 358:9d7ef901f004 11 * this list of conditions and the following disclaimer.
mbed_official 358:9d7ef901f004 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 358:9d7ef901f004 13 * this list of conditions and the following disclaimer in the documentation
mbed_official 358:9d7ef901f004 14 * and/or other materials provided with the distribution.
mbed_official 358:9d7ef901f004 15 * 3. Neither the name of ARM Limited nor the names of its contributors
mbed_official 358:9d7ef901f004 16 * may be used to endorse or promote products derived from this software
mbed_official 358:9d7ef901f004 17 * without specific prior written permission.
mbed_official 358:9d7ef901f004 18 *
mbed_official 358:9d7ef901f004 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 358:9d7ef901f004 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 358:9d7ef901f004 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 358:9d7ef901f004 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 358:9d7ef901f004 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 358:9d7ef901f004 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 358:9d7ef901f004 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 358:9d7ef901f004 26 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 358:9d7ef901f004 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 358:9d7ef901f004 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 358:9d7ef901f004 29 *******************************************************************************
mbed_official 358:9d7ef901f004 30 */
bogdanm 13:0645d8841f51 31 #include "cmsis_nvic.h"
bogdanm 13:0645d8841f51 32
bogdanm 13:0645d8841f51 33 /* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
bogdanm 13:0645d8841f51 34 * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
bogdanm 13:0645d8841f51 35 * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
bogdanm 13:0645d8841f51 36 * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
bogdanm 13:0645d8841f51 37 *
bogdanm 13:0645d8841f51 38 * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
bogdanm 13:0645d8841f51 39 * above the vector table before 0x200 will actually go to RAM. So we need to provide
bogdanm 13:0645d8841f51 40 * a solution where the compiler gets the right results based on the memory map
bogdanm 13:0645d8841f51 41 *
bogdanm 13:0645d8841f51 42 * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
bogdanm 13:0645d8841f51 43 * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
bogdanm 13:0645d8841f51 44 * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
bogdanm 13:0645d8841f51 45 *
bogdanm 13:0645d8841f51 46 * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
bogdanm 13:0645d8841f51 47 * - No flash accesses will go to ram, as there will be nothing there
bogdanm 13:0645d8841f51 48 * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
bogdanm 13:0645d8841f51 49 * - RAM overhead: 0, FLASH overhead: 320 bytes
bogdanm 13:0645d8841f51 50 *
bogdanm 13:0645d8841f51 51 * Option 2 is the one to go for, as RAM is the most valuable resource
bogdanm 13:0645d8841f51 52 */
bogdanm 13:0645d8841f51 53
bogdanm 13:0645d8841f51 54 #define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
bogdanm 13:0645d8841f51 55
bogdanm 13:0645d8841f51 56 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
bogdanm 13:0645d8841f51 57 int i;
bogdanm 13:0645d8841f51 58 // Space for dynamic vectors, initialised to allocate in R/W
bogdanm 13:0645d8841f51 59 static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
bogdanm 13:0645d8841f51 60
bogdanm 13:0645d8841f51 61 // Copy and switch to dynamic vectors if first time called
bogdanm 13:0645d8841f51 62 if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
bogdanm 13:0645d8841f51 63 uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
bogdanm 13:0645d8841f51 64 for(i = 0; i < NVIC_NUM_VECTORS; i++) {
bogdanm 13:0645d8841f51 65 vectors[i] = old_vectors[i];
bogdanm 13:0645d8841f51 66 }
bogdanm 13:0645d8841f51 67 LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
bogdanm 13:0645d8841f51 68 }
bogdanm 13:0645d8841f51 69
bogdanm 13:0645d8841f51 70 // Set the vector
bogdanm 13:0645d8841f51 71 vectors[IRQn + 16] = vector;
bogdanm 13:0645d8841f51 72 }
bogdanm 13:0645d8841f51 73
bogdanm 13:0645d8841f51 74 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
bogdanm 13:0645d8841f51 75 // We can always read vectors at 0x0, as the addresses are remapped
bogdanm 13:0645d8841f51 76 uint32_t *vectors = (uint32_t*)0;
bogdanm 13:0645d8841f51 77
bogdanm 13:0645d8841f51 78 // Return the vector
bogdanm 13:0645d8841f51 79 return vectors[IRQn + 16];
bogdanm 13:0645d8841f51 80 }
bogdanm 13:0645d8841f51 81