Diff: targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.c

Revision:

44:2ce89a25b635

Parent:

33:e214068ab66c

--- a/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.c	Mon Nov 04 10:30:05 2013 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.c	Tue Nov 05 21:45:05 2013 +0000
@@ -1,37 +1,43 @@
 /*
 ** ###################################################################
-**     Processor:           MKL46Z128VLK4
+**     Processors:          MKL46Z256VLH4
+**                          MKL46Z128VLH4
+**                          MKL46Z256VLL4
+**                          MKL46Z128VLL4
+**                          MKL46Z256VMC4
+**                          MKL46Z128VMC4
+**
 **     Compilers:           ARM Compiler
 **                          Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
 **
-**     Reference manual:    KL25RM, Rev.1, Jun 2012
-**     Version:             rev. 1.1, 2012-06-21
+**     Reference manual:    KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
+**     Version:             rev. 2.0, 2012-12-12
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
 **         contains the system frequency. It configures the device and initializes
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
-**     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**     Copyright: 2012 Freescale, Inc. All Rights Reserved.
 **
 **     http:                 www.freescale.com
 **     mail:                 support@freescale.com
 **
 **     Revisions:
-**     - rev. 1.0 (2012-06-13)
+**     - rev. 1.0 (2012-10-16)
 **         Initial version.
-**     - rev. 1.1 (2012-06-21)
-**         Update according to reference manual rev. 1.
+**     - rev. 2.0 (2012-12-12)
+**         Update to reference manual rev. 1.
 **
 ** ###################################################################
 */
 
 /**
  * @file MKL46Z4
- * @version 1.1
- * @date 2012-06-21
+ * @version 2.0
+ * @date 2012-12-12
  * @brief Device specific configuration file for MKL46Z4 (implementation file)
  *
  * Provides a system configuration function and a global variable that contains
@@ -100,8 +106,8 @@
   /* Switch to FEI Mode */
   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
   MCG->C1 = (uint8_t)0x06U;
-  /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
-  MCG->C2 = (uint8_t)0x00U;
+  /* MCG_C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+  MCG->C2 &= (uint8_t)~(uint8_t)0xBFU;
   /* MCG->C4: DMX32=0,DRST_DRS=1 */
   MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
   /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
@@ -124,11 +130,11 @@
   /* PORTA->PCR19: ISF=0,MUX=0 */
   PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
   /* Switch to FBE Mode */
-  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
-  OSC0->CR = (uint8_t)0x89U;
-  /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
-  MCG->C2 = (uint8_t)0x24U;
-  /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+  MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x9BU) | (uint8_t)0x24U);
+  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
+  OSC0->CR = (uint8_t)0x80U;
+  /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
   MCG->C1 = (uint8_t)0x9AU;
   /* MCG->C4: DMX32=0,DRST_DRS=0 */
   MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
@@ -162,10 +168,10 @@
   /* PORTA->PCR19: ISF=0,MUX=0 */
   PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
   /* Switch to FBE Mode */
-  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
-  OSC0->CR = (uint8_t)0x89U;
   /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
   MCG->C2 = (uint8_t)0x24U;
+  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
+  OSC0->CR = (uint8_t)0x80U;
   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
   MCG->C1 = (uint8_t)0x9AU;
   /* MCG->C4: DMX32=0,DRST_DRS=0 */
@@ -179,8 +185,8 @@
   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
   }
   /* Switch to BLPE Mode */
-  /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
-  MCG->C2 = (uint8_t)0x26U;
+  /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
+  MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x99U) | (uint8_t)0x26U);
   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
   }
 #endif /* (CLOCK_SETUP == 2) */