mbed library sources for GR-PEACH rev.B.
Fork of mbed-src by
targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/us_ticker.c@96:c359415e941f, 2014-02-18 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Feb 18 15:45:07 2014 +0000
- Revision:
- 96:c359415e941f
- Parent:
- 92:05f19f05c134
- Child:
- 100:0412b5443284
Synchronized with git revision 94a1bdc84b31212c9b6a6d275f9411fa3b2225fa
Full URL: https://github.com/mbedmicro/mbed/commit/94a1bdc84b31212c9b6a6d275f9411fa3b2225fa/
[NUCLEO_xxx] Fix issue with ticker + add volatile
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 76:aeb1df146756 | 1 | /* mbed Microcontroller Library |
mbed_official | 76:aeb1df146756 | 2 | * Copyright (c) 2014, STMicroelectronics |
mbed_official | 76:aeb1df146756 | 3 | * All rights reserved. |
mbed_official | 76:aeb1df146756 | 4 | * |
mbed_official | 76:aeb1df146756 | 5 | * Redistribution and use in source and binary forms, with or without |
mbed_official | 76:aeb1df146756 | 6 | * modification, are permitted provided that the following conditions are met: |
mbed_official | 76:aeb1df146756 | 7 | * |
mbed_official | 76:aeb1df146756 | 8 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 76:aeb1df146756 | 9 | * this list of conditions and the following disclaimer. |
mbed_official | 76:aeb1df146756 | 10 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 76:aeb1df146756 | 11 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 76:aeb1df146756 | 12 | * and/or other materials provided with the distribution. |
mbed_official | 76:aeb1df146756 | 13 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 76:aeb1df146756 | 14 | * may be used to endorse or promote products derived from this software |
mbed_official | 76:aeb1df146756 | 15 | * without specific prior written permission. |
mbed_official | 76:aeb1df146756 | 16 | * |
mbed_official | 76:aeb1df146756 | 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 76:aeb1df146756 | 18 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 76:aeb1df146756 | 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 76:aeb1df146756 | 20 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 76:aeb1df146756 | 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 76:aeb1df146756 | 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 76:aeb1df146756 | 23 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 76:aeb1df146756 | 24 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 76:aeb1df146756 | 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 76:aeb1df146756 | 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 76:aeb1df146756 | 27 | */ |
mbed_official | 76:aeb1df146756 | 28 | #include <stddef.h> |
mbed_official | 76:aeb1df146756 | 29 | #include "us_ticker_api.h" |
mbed_official | 76:aeb1df146756 | 30 | #include "PeripheralNames.h" |
mbed_official | 76:aeb1df146756 | 31 | |
mbed_official | 84:f54042cbc282 | 32 | // Timer selection: |
mbed_official | 84:f54042cbc282 | 33 | #define TIM_MST TIM9 |
mbed_official | 84:f54042cbc282 | 34 | #define TIM_MST_IRQ TIM9_IRQn |
mbed_official | 84:f54042cbc282 | 35 | #define TIM_MST_RCC RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9, ENABLE) |
mbed_official | 76:aeb1df146756 | 36 | |
mbed_official | 84:f54042cbc282 | 37 | static int us_ticker_inited = 0; |
mbed_official | 92:05f19f05c134 | 38 | static volatile uint32_t SlaveCounter = 0; |
mbed_official | 96:c359415e941f | 39 | static volatile uint32_t oc_int_part = 0; |
mbed_official | 96:c359415e941f | 40 | static volatile uint16_t oc_rem_part = 0; |
mbed_official | 91:0a39e62a0464 | 41 | |
mbed_official | 91:0a39e62a0464 | 42 | void set_compare(uint16_t count) { |
mbed_official | 91:0a39e62a0464 | 43 | // Set new output compare value |
mbed_official | 91:0a39e62a0464 | 44 | TIM_SetCompare1(TIM_MST, count); |
mbed_official | 91:0a39e62a0464 | 45 | // Enable IT |
mbed_official | 91:0a39e62a0464 | 46 | TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE); |
mbed_official | 91:0a39e62a0464 | 47 | } |
mbed_official | 84:f54042cbc282 | 48 | |
mbed_official | 84:f54042cbc282 | 49 | static void tim_update_oc_irq_handler(void) { |
mbed_official | 91:0a39e62a0464 | 50 | uint16_t cval = TIM_MST->CNT; |
mbed_official | 91:0a39e62a0464 | 51 | |
mbed_official | 84:f54042cbc282 | 52 | // Update interrupt: increment the slave counter |
mbed_official | 84:f54042cbc282 | 53 | if (TIM_GetITStatus(TIM_MST, TIM_IT_Update) == SET) { |
mbed_official | 84:f54042cbc282 | 54 | TIM_ClearITPendingBit(TIM_MST, TIM_IT_Update); |
mbed_official | 84:f54042cbc282 | 55 | SlaveCounter++; |
mbed_official | 84:f54042cbc282 | 56 | } |
mbed_official | 76:aeb1df146756 | 57 | |
mbed_official | 84:f54042cbc282 | 58 | // Output compare interrupt: used by interrupt system |
mbed_official | 84:f54042cbc282 | 59 | if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) { |
mbed_official | 91:0a39e62a0464 | 60 | TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1); |
mbed_official | 96:c359415e941f | 61 | if (oc_rem_part > 0) { |
mbed_official | 96:c359415e941f | 62 | set_compare(oc_rem_part); // Finish the remaining time left |
mbed_official | 96:c359415e941f | 63 | oc_rem_part = 0; |
mbed_official | 91:0a39e62a0464 | 64 | } |
mbed_official | 91:0a39e62a0464 | 65 | else { |
mbed_official | 96:c359415e941f | 66 | if (oc_int_part > 0) { |
mbed_official | 96:c359415e941f | 67 | set_compare(0xFFFF); |
mbed_official | 96:c359415e941f | 68 | oc_rem_part = cval; // To finish the counter loop the next time |
mbed_official | 96:c359415e941f | 69 | oc_int_part--; |
mbed_official | 96:c359415e941f | 70 | } |
mbed_official | 96:c359415e941f | 71 | else { |
mbed_official | 96:c359415e941f | 72 | us_ticker_irq_handler(); |
mbed_official | 96:c359415e941f | 73 | } |
mbed_official | 84:f54042cbc282 | 74 | } |
mbed_official | 84:f54042cbc282 | 75 | } |
mbed_official | 84:f54042cbc282 | 76 | } |
mbed_official | 76:aeb1df146756 | 77 | |
mbed_official | 91:0a39e62a0464 | 78 | void us_ticker_init(void) { |
mbed_official | 76:aeb1df146756 | 79 | TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; |
mbed_official | 84:f54042cbc282 | 80 | |
mbed_official | 76:aeb1df146756 | 81 | if (us_ticker_inited) return; |
mbed_official | 76:aeb1df146756 | 82 | us_ticker_inited = 1; |
mbed_official | 76:aeb1df146756 | 83 | |
mbed_official | 84:f54042cbc282 | 84 | // Enable Timer clock |
mbed_official | 76:aeb1df146756 | 85 | TIM_MST_RCC; |
mbed_official | 76:aeb1df146756 | 86 | |
mbed_official | 84:f54042cbc282 | 87 | // Configure time base |
mbed_official | 76:aeb1df146756 | 88 | TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); |
mbed_official | 76:aeb1df146756 | 89 | TIM_TimeBaseStructure.TIM_Period = 0xFFFF; |
mbed_official | 76:aeb1df146756 | 90 | TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick |
mbed_official | 76:aeb1df146756 | 91 | TIM_TimeBaseStructure.TIM_ClockDivision = 0; |
mbed_official | 76:aeb1df146756 | 92 | TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; |
mbed_official | 76:aeb1df146756 | 93 | TIM_TimeBaseInit(TIM_MST, &TIM_TimeBaseStructure); |
mbed_official | 84:f54042cbc282 | 94 | |
mbed_official | 84:f54042cbc282 | 95 | // Configure interrupts |
mbed_official | 84:f54042cbc282 | 96 | TIM_ITConfig(TIM_MST, TIM_IT_Update, ENABLE); |
mbed_official | 76:aeb1df146756 | 97 | |
mbed_official | 84:f54042cbc282 | 98 | // For 32-bit counter and output compare |
mbed_official | 84:f54042cbc282 | 99 | NVIC_SetVector(TIM_MST_IRQ, (uint32_t)tim_update_oc_irq_handler); |
mbed_official | 84:f54042cbc282 | 100 | NVIC_EnableIRQ(TIM_MST_IRQ); |
mbed_official | 76:aeb1df146756 | 101 | |
mbed_official | 84:f54042cbc282 | 102 | // Enable timer |
mbed_official | 76:aeb1df146756 | 103 | TIM_Cmd(TIM_MST, ENABLE); |
mbed_official | 76:aeb1df146756 | 104 | } |
mbed_official | 76:aeb1df146756 | 105 | |
mbed_official | 76:aeb1df146756 | 106 | uint32_t us_ticker_read() { |
mbed_official | 76:aeb1df146756 | 107 | uint32_t counter, counter2; |
mbed_official | 76:aeb1df146756 | 108 | if (!us_ticker_inited) us_ticker_init(); |
mbed_official | 76:aeb1df146756 | 109 | // A situation might appear when Master overflows right after Slave is read and before the |
mbed_official | 76:aeb1df146756 | 110 | // new (overflowed) value of Master is read. Which would make the code below consider the |
mbed_official | 76:aeb1df146756 | 111 | // previous (incorrect) value of Slave and the new value of Master, which would return a |
mbed_official | 76:aeb1df146756 | 112 | // value in the past. Avoid this by computing consecutive values of the timer until they |
mbed_official | 76:aeb1df146756 | 113 | // are properly ordered. |
mbed_official | 84:f54042cbc282 | 114 | counter = (uint32_t)(SlaveCounter << 16); |
mbed_official | 91:0a39e62a0464 | 115 | counter += TIM_MST->CNT; |
mbed_official | 76:aeb1df146756 | 116 | while (1) { |
mbed_official | 84:f54042cbc282 | 117 | counter2 = (uint32_t)(SlaveCounter << 16); |
mbed_official | 91:0a39e62a0464 | 118 | counter2 += TIM_MST->CNT; |
mbed_official | 76:aeb1df146756 | 119 | if (counter2 > counter) { |
mbed_official | 76:aeb1df146756 | 120 | break; |
mbed_official | 76:aeb1df146756 | 121 | } |
mbed_official | 76:aeb1df146756 | 122 | counter = counter2; |
mbed_official | 76:aeb1df146756 | 123 | } |
mbed_official | 76:aeb1df146756 | 124 | return counter2; |
mbed_official | 76:aeb1df146756 | 125 | } |
mbed_official | 76:aeb1df146756 | 126 | |
mbed_official | 76:aeb1df146756 | 127 | void us_ticker_set_interrupt(unsigned int timestamp) { |
mbed_official | 84:f54042cbc282 | 128 | int delta = (int)(timestamp - us_ticker_read()); |
mbed_official | 91:0a39e62a0464 | 129 | uint16_t cval = TIM_MST->CNT; |
mbed_official | 84:f54042cbc282 | 130 | |
mbed_official | 84:f54042cbc282 | 131 | if (delta <= 0) { // This event was in the past |
mbed_official | 84:f54042cbc282 | 132 | us_ticker_irq_handler(); |
mbed_official | 76:aeb1df146756 | 133 | } |
mbed_official | 76:aeb1df146756 | 134 | else { |
mbed_official | 91:0a39e62a0464 | 135 | oc_int_part = (uint32_t)(delta >> 16); |
mbed_official | 91:0a39e62a0464 | 136 | oc_rem_part = (uint16_t)(delta & 0xFFFF); |
mbed_official | 91:0a39e62a0464 | 137 | if (oc_rem_part <= (0xFFFF - cval)) { |
mbed_official | 91:0a39e62a0464 | 138 | set_compare(cval + oc_rem_part); |
mbed_official | 91:0a39e62a0464 | 139 | oc_rem_part = 0; |
mbed_official | 84:f54042cbc282 | 140 | } else { |
mbed_official | 91:0a39e62a0464 | 141 | set_compare(0xFFFF); |
mbed_official | 91:0a39e62a0464 | 142 | oc_rem_part = oc_rem_part - (0xFFFF - cval); |
mbed_official | 84:f54042cbc282 | 143 | } |
mbed_official | 76:aeb1df146756 | 144 | } |
mbed_official | 76:aeb1df146756 | 145 | } |
mbed_official | 76:aeb1df146756 | 146 | |
mbed_official | 76:aeb1df146756 | 147 | void us_ticker_disable_interrupt(void) { |
mbed_official | 76:aeb1df146756 | 148 | TIM_ITConfig(TIM_MST, TIM_IT_CC1, DISABLE); |
mbed_official | 76:aeb1df146756 | 149 | } |
mbed_official | 76:aeb1df146756 | 150 | |
mbed_official | 76:aeb1df146756 | 151 | void us_ticker_clear_interrupt(void) { |
mbed_official | 84:f54042cbc282 | 152 | if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) { |
mbed_official | 84:f54042cbc282 | 153 | TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1); |
mbed_official | 84:f54042cbc282 | 154 | } |
mbed_official | 76:aeb1df146756 | 155 | } |