Renesas / mbed-src_GR-PEACH_rev_b

mbed library sources for GR-PEACH rev.B.

Fork of mbed-src by mbed official

targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_irq_api.c@285:31249416b6f9, 2014-08-15 (annotated)

Committer:
mbed_official
Date:
Fri Aug 15 16:30:08 2014 +0100
Revision:
285:31249416b6f9
Parent:
251:de9a1e4ffd79 
Synchronized with git revision 601712595f49bbd2a2771c52cf3e84c9c7a591af



Full URL: https://github.com/mbedmicro/mbed/commit/601712595f49bbd2a2771c52cf3e84c9c7a591af/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 103:9b881da47c92 1 /* mbed Microcontroller Library
mbed_official 103:9b881da47c92 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 103:9b881da47c92 3 *
mbed_official 103:9b881da47c92 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 103:9b881da47c92 5 * you may not use this file except in compliance with the License.
mbed_official 103:9b881da47c92 6 * You may obtain a copy of the License at
mbed_official 103:9b881da47c92 7 *
mbed_official 103:9b881da47c92 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 103:9b881da47c92 9 *
mbed_official 103:9b881da47c92 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 103:9b881da47c92 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 103:9b881da47c92 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 103:9b881da47c92 13 * See the License for the specific language governing permissions and
mbed_official 103:9b881da47c92 14 * limitations under the License.
mbed_official 103:9b881da47c92 15 */
mbed_official 103:9b881da47c92 16 #include <stddef.h>
mbed_official 103:9b881da47c92 17
mbed_official 103:9b881da47c92 18 #include "cmsis.h"
mbed_official 103:9b881da47c92 19 #include "gpio_irq_api.h"
mbed_official 285:31249416b6f9 20 #include "mbed_error.h"
mbed_official 103:9b881da47c92 21
mbed_official 103:9b881da47c92 22 #define CHANNEL_NUM 8
mbed_official 103:9b881da47c92 23 #define LPC_GPIO_X LPC_PINT
mbed_official 103:9b881da47c92 24 #define PININT_IRQ PIN_INT0_IRQn
mbed_official 103:9b881da47c92 25
mbed_official 103:9b881da47c92 26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
mbed_official 103:9b881da47c92 27 static gpio_irq_handler irq_handler;
mbed_official 103:9b881da47c92 28
mbed_official 103:9b881da47c92 29 static inline void handle_interrupt_in(uint32_t channel) {
mbed_official 103:9b881da47c92 30 uint32_t ch_bit = (1 << channel);
mbed_official 103:9b881da47c92 31 // Return immediately if:
mbed_official 103:9b881da47c92 32 // * The interrupt was already served
mbed_official 103:9b881da47c92 33 // * There is no user handler
mbed_official 103:9b881da47c92 34 // * It is a level interrupt, not an edge interrupt
mbed_official 103:9b881da47c92 35 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
mbed_official 103:9b881da47c92 36 (channel_ids[channel] == 0 ) ||
mbed_official 103:9b881da47c92 37 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
mbed_official 103:9b881da47c92 38
mbed_official 103:9b881da47c92 39 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
mbed_official 103:9b881da47c92 40 irq_handler(channel_ids[channel], IRQ_RISE);
mbed_official 103:9b881da47c92 41 LPC_GPIO_X->RISE = ch_bit;
mbed_official 103:9b881da47c92 42 }
mbed_official 103:9b881da47c92 43 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
mbed_official 103:9b881da47c92 44 irq_handler(channel_ids[channel], IRQ_FALL);
mbed_official 103:9b881da47c92 45 LPC_GPIO_X->FALL = ch_bit;
mbed_official 103:9b881da47c92 46 }
mbed_official 103:9b881da47c92 47 LPC_GPIO_X->IST = ch_bit;
mbed_official 103:9b881da47c92 48 }
mbed_official 103:9b881da47c92 49
mbed_official 103:9b881da47c92 50 void gpio_irq0(void) {handle_interrupt_in(0);}
mbed_official 103:9b881da47c92 51 void gpio_irq1(void) {handle_interrupt_in(1);}
mbed_official 103:9b881da47c92 52 void gpio_irq2(void) {handle_interrupt_in(2);}
mbed_official 103:9b881da47c92 53 void gpio_irq3(void) {handle_interrupt_in(3);}
mbed_official 103:9b881da47c92 54 void gpio_irq4(void) {handle_interrupt_in(4);}
mbed_official 103:9b881da47c92 55 void gpio_irq5(void) {handle_interrupt_in(5);}
mbed_official 103:9b881da47c92 56 void gpio_irq6(void) {handle_interrupt_in(6);}
mbed_official 103:9b881da47c92 57 void gpio_irq7(void) {handle_interrupt_in(7);}
mbed_official 103:9b881da47c92 58
mbed_official 103:9b881da47c92 59 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
mbed_official 103:9b881da47c92 60 // PINT only supprt GPIO port 0 and 1 interrupt
mbed_official 103:9b881da47c92 61 if (pin >= P2_0) return -1;
mbed_official 103:9b881da47c92 62
mbed_official 103:9b881da47c92 63 irq_handler = handler;
mbed_official 103:9b881da47c92 64
mbed_official 103:9b881da47c92 65 int found_free_channel = 0;
mbed_official 103:9b881da47c92 66 int i = 0;
mbed_official 103:9b881da47c92 67 for (i=0; i<CHANNEL_NUM; i++) {
mbed_official 103:9b881da47c92 68 if (channel_ids[i] == 0) {
mbed_official 103:9b881da47c92 69 channel_ids[i] = id;
mbed_official 103:9b881da47c92 70 obj->ch = i;
mbed_official 103:9b881da47c92 71 found_free_channel = 1;
mbed_official 103:9b881da47c92 72 break;
mbed_official 103:9b881da47c92 73 }
mbed_official 103:9b881da47c92 74 }
mbed_official 103:9b881da47c92 75 if (!found_free_channel) return -1;
mbed_official 103:9b881da47c92 76
mbed_official 103:9b881da47c92 77 /* Enable AHB clock to the PIN, GPIO0/1, IOCON and MUX domain. */
mbed_official 103:9b881da47c92 78 LPC_SYSCON->SYSAHBCLKCTRL0 |= ((1 << 18) | (0x1D << 11));
mbed_official 103:9b881da47c92 79
mbed_official 103:9b881da47c92 80 LPC_INMUX->PINTSEL[obj->ch] = pin;
mbed_official 103:9b881da47c92 81
mbed_official 103:9b881da47c92 82 // Interrupt Wake-Up Enable
mbed_official 103:9b881da47c92 83 LPC_SYSCON->STARTERP0 |= (1 << (obj->ch + 5));
mbed_official 103:9b881da47c92 84
mbed_official 103:9b881da47c92 85 LPC_GPIO_PORT->DIR[pin >> 5] &= ~(1 << (pin & 0x1F));
mbed_official 103:9b881da47c92 86
mbed_official 103:9b881da47c92 87 void (*channels_irq)(void) = NULL;
mbed_official 103:9b881da47c92 88 switch (obj->ch) {
mbed_official 103:9b881da47c92 89 case 0: channels_irq = &gpio_irq0; break;
mbed_official 103:9b881da47c92 90 case 1: channels_irq = &gpio_irq1; break;
mbed_official 103:9b881da47c92 91 case 2: channels_irq = &gpio_irq2; break;
mbed_official 103:9b881da47c92 92 case 3: channels_irq = &gpio_irq3; break;
mbed_official 103:9b881da47c92 93 case 4: channels_irq = &gpio_irq4; break;
mbed_official 103:9b881da47c92 94 case 5: channels_irq = &gpio_irq5; break;
mbed_official 103:9b881da47c92 95 case 6: channels_irq = &gpio_irq6; break;
mbed_official 103:9b881da47c92 96 case 7: channels_irq = &gpio_irq7; break;
mbed_official 103:9b881da47c92 97 }
mbed_official 103:9b881da47c92 98 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
mbed_official 103:9b881da47c92 99 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 103:9b881da47c92 100
mbed_official 103:9b881da47c92 101 return 0;
mbed_official 103:9b881da47c92 102 }
mbed_official 103:9b881da47c92 103
mbed_official 103:9b881da47c92 104 void gpio_irq_free(gpio_irq_t *obj) {
mbed_official 103:9b881da47c92 105 channel_ids[obj->ch] = 0;
mbed_official 103:9b881da47c92 106 LPC_SYSCON->STARTERP0 &= ~(1 << (obj->ch + 5));
mbed_official 103:9b881da47c92 107 }
mbed_official 103:9b881da47c92 108
mbed_official 103:9b881da47c92 109 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
mbed_official 103:9b881da47c92 110 unsigned int ch_bit = (1 << obj->ch);
mbed_official 103:9b881da47c92 111
mbed_official 103:9b881da47c92 112 // Clear interrupt
mbed_official 103:9b881da47c92 113 if (!(LPC_GPIO_X->ISEL & ch_bit))
mbed_official 103:9b881da47c92 114 LPC_GPIO_X->IST = ch_bit;
mbed_official 103:9b881da47c92 115
mbed_official 103:9b881da47c92 116 // Edge trigger
mbed_official 103:9b881da47c92 117 LPC_GPIO_X->ISEL &= ~ch_bit;
mbed_official 103:9b881da47c92 118 if (event == IRQ_RISE) {
mbed_official 103:9b881da47c92 119 if (enable) {
mbed_official 103:9b881da47c92 120 LPC_GPIO_X->IENR |= ch_bit;
mbed_official 103:9b881da47c92 121 } else {
mbed_official 103:9b881da47c92 122 LPC_GPIO_X->IENR &= ~ch_bit;
mbed_official 103:9b881da47c92 123 }
mbed_official 103:9b881da47c92 124 } else {
mbed_official 103:9b881da47c92 125 if (enable) {
mbed_official 103:9b881da47c92 126 LPC_GPIO_X->IENF |= ch_bit;
mbed_official 103:9b881da47c92 127 } else {
mbed_official 103:9b881da47c92 128 LPC_GPIO_X->IENF &= ~ch_bit;
mbed_official 103:9b881da47c92 129 }
mbed_official 103:9b881da47c92 130 }
mbed_official 103:9b881da47c92 131 }
mbed_official 103:9b881da47c92 132
mbed_official 103:9b881da47c92 133 void gpio_irq_enable(gpio_irq_t *obj) {
mbed_official 103:9b881da47c92 134 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 103:9b881da47c92 135 }
mbed_official 103:9b881da47c92 136
mbed_official 103:9b881da47c92 137 void gpio_irq_disable(gpio_irq_t *obj) {
mbed_official 103:9b881da47c92 138 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 103:9b881da47c92 139 }