Renesas / TLV320_RBSP

TLV320_RBSP class, defined on the I2C master bus.

Dependents:   MovPlayer GR-PEACH_Audio_Playback_Sample GR-PEACH_Audio_Playback_7InchLCD_Sample RGA-MJPEG_VideoDemo ... more

Fork of TLV320_RBSP by Daiki Kato

TLV320_RBSP.cpp@4:15487e571d9f, 2015-10-21 (annotated)

Committer:
dkato
Date:
Wed Oct 21 06:58:35 2015 +0000
Revision:
4:15487e571d9f
Parent:
2:b1fab4a2b59d 
Add API "micVolume()".

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:bb69b79a1e05 1 /*******************************************************************************
dkato 0:bb69b79a1e05 2 * DISCLAIMER
dkato 0:bb69b79a1e05 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:bb69b79a1e05 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:bb69b79a1e05 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:bb69b79a1e05 6 * all applicable laws, including copyright laws.
dkato 0:bb69b79a1e05 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:bb69b79a1e05 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:bb69b79a1e05 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:bb69b79a1e05 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:bb69b79a1e05 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:bb69b79a1e05 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:bb69b79a1e05 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:bb69b79a1e05 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:bb69b79a1e05 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:bb69b79a1e05 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:bb69b79a1e05 17 * and to discontinue the availability of this software. By using this software,
dkato 0:bb69b79a1e05 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:bb69b79a1e05 19 * following link:
dkato 0:bb69b79a1e05 20 * http://www.renesas.com/disclaimer*
dkato 0:bb69b79a1e05 21 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:bb69b79a1e05 22 *******************************************************************************/
dkato 0:bb69b79a1e05 23
dkato 0:bb69b79a1e05 24 #include "mbed.h"
dkato 0:bb69b79a1e05 25 #include "TLV320_RBSP.h"
dkato 0:bb69b79a1e05 26 #include "pinmap.h"
dkato 0:bb69b79a1e05 27
dkato 2:b1fab4a2b59d 28 #define MCLK_12MHZ
dkato 2:b1fab4a2b59d 29 #undef MCLK_11_2896MHZ
dkato 0:bb69b79a1e05 30
dkato 2:b1fab4a2b59d 31 TLV320_RBSP::TLV320_RBSP(PinName cs, PinName sda, PinName scl, PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level, int32_t max_write_num, int32_t max_read_num)
dkato 4:15487e571d9f 32 : audio_cs_(cs), mI2c_(sda, scl), mI2s_(sck, ws, tx, rx, int_level, max_write_num, max_read_num) {
dkato 0:bb69b79a1e05 33 audio_cs_ = 0;
dkato 0:bb69b79a1e05 34 mAddr = 0x34;
dkato 0:bb69b79a1e05 35 audio_path_control = 0;
dkato 0:bb69b79a1e05 36
dkato 2:b1fab4a2b59d 37 // I2S Mode
dkato 0:bb69b79a1e05 38 ssif_cfg.enabled = true;
dkato 0:bb69b79a1e05 39 ssif_cfg.int_level = 0x78;
dkato 0:bb69b79a1e05 40 ssif_cfg.slave_mode = true;
dkato 0:bb69b79a1e05 41 ssif_cfg.sample_freq = 44100u;
dkato 0:bb69b79a1e05 42 ssif_cfg.clk_select = SSIF_CFG_CKS_AUDIO_X1;
dkato 0:bb69b79a1e05 43 ssif_cfg.multi_ch = SSIF_CFG_MULTI_CH_1;
dkato 0:bb69b79a1e05 44 ssif_cfg.data_word = SSIF_CFG_DATA_WORD_16;
dkato 0:bb69b79a1e05 45 ssif_cfg.system_word = SSIF_CFG_SYSTEM_WORD_32;
dkato 0:bb69b79a1e05 46 ssif_cfg.bclk_pol = SSIF_CFG_FALLING;
dkato 0:bb69b79a1e05 47 ssif_cfg.ws_pol = SSIF_CFG_WS_LOW;
dkato 0:bb69b79a1e05 48 ssif_cfg.padding_pol = SSIF_CFG_PADDING_LOW;
dkato 0:bb69b79a1e05 49 ssif_cfg.serial_alignment = SSIF_CFG_DATA_FIRST;
dkato 0:bb69b79a1e05 50 ssif_cfg.parallel_alignment = SSIF_CFG_LEFT;
dkato 0:bb69b79a1e05 51 ssif_cfg.ws_delay = SSIF_CFG_DELAY;
dkato 2:b1fab4a2b59d 52 ssif_cfg.noise_cancel = SSIF_CFG_ENABLE_NOISE_CANCEL;
dkato 0:bb69b79a1e05 53 ssif_cfg.tdm_mode = SSIF_CFG_DISABLE_TDM;
dkato 0:bb69b79a1e05 54 ssif_cfg.romdec_direct.mode = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
dkato 0:bb69b79a1e05 55 ssif_cfg.romdec_direct.p_cbfunc = NULL;
dkato 0:bb69b79a1e05 56 mI2s_.ConfigChannel(&ssif_cfg);
dkato 0:bb69b79a1e05 57
dkato 0:bb69b79a1e05 58 mI2c_.frequency(150000);
dkato 0:bb69b79a1e05 59 reset(); // TLV resets
dkato 0:bb69b79a1e05 60 power(0x80); // Power off
dkato 0:bb69b79a1e05 61 format(16); // 16Bit I2S protocol format
dkato 0:bb69b79a1e05 62 frequency(44100); // Default sample frequency is 44.1kHz
dkato 0:bb69b79a1e05 63 bypass(false); // Do not bypass device
dkato 0:bb69b79a1e05 64 mic(false); // Input select for ADC is line
dkato 0:bb69b79a1e05 65 mute(false); // Not muted
dkato 0:bb69b79a1e05 66 activateDigitalInterface_(); // The digital part of the chip is active
dkato 0:bb69b79a1e05 67 }
dkato 0:bb69b79a1e05 68
dkato 0:bb69b79a1e05 69 // Public Functions
dkato 0:bb69b79a1e05 70 bool TLV320_RBSP::inputVolume(float leftVolumeIn, float rightVolumeIn) {
dkato 0:bb69b79a1e05 71 // check values are in range
dkato 0:bb69b79a1e05 72 if ((leftVolumeIn < 0.0) || (leftVolumeIn > 1.0)
dkato 0:bb69b79a1e05 73 || (rightVolumeIn < 0.0) || (rightVolumeIn > 1.0)) {
dkato 0:bb69b79a1e05 74 return false;
dkato 0:bb69b79a1e05 75 }
dkato 0:bb69b79a1e05 76
dkato 0:bb69b79a1e05 77 // convert float to encoded char
dkato 0:bb69b79a1e05 78 char left = (char)(31 * leftVolumeIn);
dkato 0:bb69b79a1e05 79 char right = (char)(31 * rightVolumeIn);
dkato 0:bb69b79a1e05 80
dkato 0:bb69b79a1e05 81 // Left Channel
dkato 0:bb69b79a1e05 82 cmd[0] = LEFT_LINE_INPUT_CHANNEL_VOLUME_CONTROL;
dkato 0:bb69b79a1e05 83 cmd[1] = left | (0 << 7); // set volume, mute off
dkato 0:bb69b79a1e05 84 mI2c_.write(mAddr, cmd, 2);
dkato 0:bb69b79a1e05 85
dkato 0:bb69b79a1e05 86 // Right Channel
dkato 0:bb69b79a1e05 87 cmd[0] = RIGHT_LINE_INPUT_CHANNEL_VOLUME_CONTROL;
dkato 0:bb69b79a1e05 88 cmd[1] = right | (0 << 7); // set volume, mute off
dkato 0:bb69b79a1e05 89 mI2c_.write(mAddr, cmd, 2);
dkato 0:bb69b79a1e05 90
dkato 0:bb69b79a1e05 91 return true;
dkato 0:bb69b79a1e05 92 }
dkato 0:bb69b79a1e05 93
dkato 0:bb69b79a1e05 94 bool TLV320_RBSP::outputVolume(float leftVolumeOut, float rightVolumeOut) {
dkato 0:bb69b79a1e05 95 // check values are in range
dkato 0:bb69b79a1e05 96 if ((leftVolumeOut < 0.0) || (leftVolumeOut > 1.0)
dkato 0:bb69b79a1e05 97 || (rightVolumeOut < 0.0) || (rightVolumeOut > 1.0)) {
dkato 0:bb69b79a1e05 98 return false;
dkato 0:bb69b79a1e05 99 }
dkato 0:bb69b79a1e05 100
dkato 0:bb69b79a1e05 101 // convert float to encoded char
dkato 0:bb69b79a1e05 102 char left = (char)((79 * leftVolumeOut) + 0x30);
dkato 0:bb69b79a1e05 103 char right = (char)((79 * rightVolumeOut) + 0x30);
dkato 0:bb69b79a1e05 104
dkato 0:bb69b79a1e05 105 // Left Channel
dkato 0:bb69b79a1e05 106 cmd[0] = LEFT_CHANNEL_HEADPHONE_VOLUME_CONTROL;
dkato 0:bb69b79a1e05 107 cmd[1] = left | (1 << 7); // set volume, Zero-cross detect
dkato 0:bb69b79a1e05 108 mI2c_.write(mAddr, cmd, 2);
dkato 0:bb69b79a1e05 109
dkato 0:bb69b79a1e05 110 // Right Channel
dkato 0:bb69b79a1e05 111 cmd[0] = RIGHT_CHANNEL_HEADPHONE_VOLUME_CONTROL;
dkato 0:bb69b79a1e05 112 cmd[1] = right | (1 << 7); // set volume, Zero-cross detect
dkato 0:bb69b79a1e05 113 mI2c_.write(mAddr, cmd, 2);
dkato 0:bb69b79a1e05 114
dkato 0:bb69b79a1e05 115 return true;
dkato 0:bb69b79a1e05 116 }
dkato 0:bb69b79a1e05 117
dkato 0:bb69b79a1e05 118 void TLV320_RBSP::bypass(bool bypassVar) {
dkato 0:bb69b79a1e05 119 cmd[0] = ANALOG_AUDIO_PATH_CONTROL;
dkato 0:bb69b79a1e05 120 if (bypassVar != false) {
dkato 0:bb69b79a1e05 121 audio_path_control |= (1 << 3); // bypass enabled
dkato 0:bb69b79a1e05 122 audio_path_control &= ~(1 << 4); // DAC disable
dkato 0:bb69b79a1e05 123 } else {
dkato 0:bb69b79a1e05 124 audio_path_control &= ~(1 << 3); // bypass disable
dkato 0:bb69b79a1e05 125 audio_path_control |= (1 << 4); // DAC enabled
dkato 0:bb69b79a1e05 126 }
dkato 0:bb69b79a1e05 127 cmd[1] = audio_path_control;
dkato 0:bb69b79a1e05 128 mI2c_.write(mAddr, cmd, 2);
dkato 0:bb69b79a1e05 129 }
dkato 0:bb69b79a1e05 130
dkato 0:bb69b79a1e05 131 void TLV320_RBSP::mic(bool micVar) {
dkato 0:bb69b79a1e05 132 cmd[0] = ANALOG_AUDIO_PATH_CONTROL;
dkato 0:bb69b79a1e05 133 if (micVar != false) {
dkato 0:bb69b79a1e05 134 audio_path_control |= (1 << 2); // INSEL Microphone
dkato 0:bb69b79a1e05 135 } else {
dkato 0:bb69b79a1e05 136 audio_path_control &= ~(1 << 2); // INSEL Line
dkato 0:bb69b79a1e05 137 }
dkato 0:bb69b79a1e05 138 cmd[1] = audio_path_control;
dkato 0:bb69b79a1e05 139 mI2c_.write(mAddr, cmd, 2);
dkato 0:bb69b79a1e05 140 }
dkato 0:bb69b79a1e05 141
dkato 4:15487e571d9f 142 void TLV320_RBSP::micVolume(bool mute, bool boost) {
dkato 4:15487e571d9f 143 cmd[0] = ANALOG_AUDIO_PATH_CONTROL;
dkato 4:15487e571d9f 144 if (mute != false) {
dkato 4:15487e571d9f 145 audio_path_control |= (1 << 1); // MICM Muted
dkato 4:15487e571d9f 146 } else {
dkato 4:15487e571d9f 147 audio_path_control &= ~(1 << 1); // MICM Normal
dkato 4:15487e571d9f 148 }
dkato 4:15487e571d9f 149 if (boost != false) {
dkato 4:15487e571d9f 150 audio_path_control |= (1 << 0); // MICB 20dB
dkato 4:15487e571d9f 151 } else {
dkato 4:15487e571d9f 152 audio_path_control &= ~(1 << 0); // MICB 0dB
dkato 4:15487e571d9f 153 }
dkato 4:15487e571d9f 154 cmd[1] = audio_path_control;
dkato 4:15487e571d9f 155 mI2c_.write(mAddr, cmd, 2);
dkato 4:15487e571d9f 156 }
dkato 4:15487e571d9f 157
dkato 0:bb69b79a1e05 158 void TLV320_RBSP::mute(bool softMute) {
dkato 0:bb69b79a1e05 159 cmd[0] = DIGITAL_AUDIO_PATH_CONTROL;
dkato 0:bb69b79a1e05 160 if (softMute != false) {
dkato 0:bb69b79a1e05 161 cmd[1] = 0x08; // set instruction to mute
dkato 0:bb69b79a1e05 162 } else {
dkato 0:bb69b79a1e05 163 cmd[1] = 0x00; // set instruction to NOT mute
dkato 0:bb69b79a1e05 164 }
dkato 0:bb69b79a1e05 165 mI2c_.write(mAddr, cmd, 2);
dkato 0:bb69b79a1e05 166 }
dkato 0:bb69b79a1e05 167
dkato 0:bb69b79a1e05 168 void TLV320_RBSP::power(int device) {
dkato 0:bb69b79a1e05 169 cmd[0] = POWER_DOWN_CONTROL;
dkato 0:bb69b79a1e05 170 cmd[1] = (char)device; // set user defined commands
dkato 0:bb69b79a1e05 171 mI2c_.write(mAddr, cmd, 2);
dkato 0:bb69b79a1e05 172 }
dkato 0:bb69b79a1e05 173
dkato 2:b1fab4a2b59d 174 bool TLV320_RBSP::format(char length) {
dkato 0:bb69b79a1e05 175 cmd[0] = DIGITAL_AUDIO_INTERFACE_FORMAT;
dkato 0:bb69b79a1e05 176 cmd[1] = (1 << 6); // Master
dkato 0:bb69b79a1e05 177 switch (length) { // input data into instruction byte
dkato 0:bb69b79a1e05 178 case 16:
dkato 0:bb69b79a1e05 179 ssif_cfg.data_word = SSIF_CFG_DATA_WORD_16;
dkato 0:bb69b79a1e05 180 cmd[1] |= 0x02;
dkato 0:bb69b79a1e05 181 break;
dkato 0:bb69b79a1e05 182 case 20:
dkato 0:bb69b79a1e05 183 ssif_cfg.data_word = SSIF_CFG_DATA_WORD_20;
dkato 0:bb69b79a1e05 184 cmd[1] |= 0x06;
dkato 0:bb69b79a1e05 185 break;
dkato 0:bb69b79a1e05 186 case 24:
dkato 0:bb69b79a1e05 187 ssif_cfg.data_word = SSIF_CFG_DATA_WORD_24;
dkato 0:bb69b79a1e05 188 cmd[1] |= 0x0A;
dkato 0:bb69b79a1e05 189 break;
dkato 0:bb69b79a1e05 190 case 32:
dkato 0:bb69b79a1e05 191 ssif_cfg.data_word = SSIF_CFG_DATA_WORD_32;
dkato 0:bb69b79a1e05 192 cmd[1] |= 0x0E;
dkato 0:bb69b79a1e05 193 break;
dkato 0:bb69b79a1e05 194 default:
dkato 2:b1fab4a2b59d 195 return false;
dkato 0:bb69b79a1e05 196 }
dkato 0:bb69b79a1e05 197 mI2s_.ConfigChannel(&ssif_cfg);
dkato 0:bb69b79a1e05 198 mI2c_.write(mAddr, cmd, 2);
dkato 2:b1fab4a2b59d 199
dkato 2:b1fab4a2b59d 200 return true;
dkato 0:bb69b79a1e05 201 }
dkato 0:bb69b79a1e05 202
dkato 0:bb69b79a1e05 203 bool TLV320_RBSP::frequency(int hz) {
dkato 2:b1fab4a2b59d 204 char control_setting;
dkato 0:bb69b79a1e05 205
dkato 2:b1fab4a2b59d 206 #if defined(MCLK_12MHZ)
dkato 0:bb69b79a1e05 207 switch (hz) {
dkato 2:b1fab4a2b59d 208 case 96000:
dkato 2:b1fab4a2b59d 209 control_setting = 0x1D;
dkato 2:b1fab4a2b59d 210 break;
dkato 2:b1fab4a2b59d 211 case 88200:
dkato 2:b1fab4a2b59d 212 control_setting = 0x3F;
dkato 2:b1fab4a2b59d 213 break;
dkato 2:b1fab4a2b59d 214 case 48000:
dkato 2:b1fab4a2b59d 215 control_setting = 0x01;
dkato 0:bb69b79a1e05 216 break;
dkato 0:bb69b79a1e05 217 case 44100:
dkato 2:b1fab4a2b59d 218 control_setting = 0x23;
dkato 2:b1fab4a2b59d 219 break;
dkato 2:b1fab4a2b59d 220 case 32000:
dkato 2:b1fab4a2b59d 221 control_setting = 0x19;
dkato 0:bb69b79a1e05 222 break;
dkato 2:b1fab4a2b59d 223 case 8021:
dkato 2:b1fab4a2b59d 224 control_setting = 0x2F;
dkato 2:b1fab4a2b59d 225 break;
dkato 2:b1fab4a2b59d 226 case 8000:
dkato 2:b1fab4a2b59d 227 control_setting = 0x0D;
dkato 0:bb69b79a1e05 228 break;
dkato 0:bb69b79a1e05 229 default:
dkato 0:bb69b79a1e05 230 return false;
dkato 0:bb69b79a1e05 231 }
dkato 2:b1fab4a2b59d 232 #elif defined(MCLK_11_2896MHZ)
dkato 2:b1fab4a2b59d 233 switch (hz) {
dkato 2:b1fab4a2b59d 234 case 88200:
dkato 2:b1fab4a2b59d 235 control_setting = 0x3C;
dkato 2:b1fab4a2b59d 236 break;
dkato 2:b1fab4a2b59d 237 case 44100:
dkato 2:b1fab4a2b59d 238 control_setting = 0x20;
dkato 2:b1fab4a2b59d 239 break;
dkato 2:b1fab4a2b59d 240 case 8021:
dkato 2:b1fab4a2b59d 241 control_setting = 0x2C;
dkato 2:b1fab4a2b59d 242 break;
dkato 2:b1fab4a2b59d 243 default:
dkato 2:b1fab4a2b59d 244 return false;
dkato 2:b1fab4a2b59d 245 }
dkato 2:b1fab4a2b59d 246 #else
dkato 2:b1fab4a2b59d 247 #error MCLK error
dkato 2:b1fab4a2b59d 248 #endif
dkato 0:bb69b79a1e05 249 cmd[0] = SAMPLE_RATE_CONTROL;
dkato 2:b1fab4a2b59d 250 cmd[1] = control_setting;
dkato 0:bb69b79a1e05 251 mI2c_.write(mAddr, cmd, 2);
dkato 0:bb69b79a1e05 252
dkato 0:bb69b79a1e05 253 return true;
dkato 0:bb69b79a1e05 254 }
dkato 0:bb69b79a1e05 255
dkato 0:bb69b79a1e05 256 void TLV320_RBSP::reset(void) {
dkato 0:bb69b79a1e05 257 cmd[0] = RESET_REGISTER;
dkato 0:bb69b79a1e05 258 cmd[1] = 0x00; // Write 000000000 to this register triggers reset
dkato 0:bb69b79a1e05 259 mI2c_.write(mAddr, cmd, 2);
dkato 0:bb69b79a1e05 260 }
dkato 0:bb69b79a1e05 261
dkato 0:bb69b79a1e05 262 // Private Functions
dkato 0:bb69b79a1e05 263 void TLV320_RBSP::activateDigitalInterface_(void) {
dkato 0:bb69b79a1e05 264 cmd[0] = DIGITAL_INTERFACE_ACTIVATION;
dkato 0:bb69b79a1e05 265 cmd[1] = 0x01; // Activate
dkato 0:bb69b79a1e05 266 mI2c_.write(mAddr, cmd, 2);
dkato 0:bb69b79a1e05 267 }