sdg_iobitmask.h

00001 /*******************************************************************************
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00022 *******************************************************************************/
00023 
00024 #ifndef SDG_IOBITMASK_H
00025 #define SDG_IOBITMASK_H
00026 
00027 
00028 /* ==== Mask values for IO registers ==== */
00029 /* ---- SDGn ---- */
00030 #define     SDGn_SGCR1_SGST_SHIFT       (7u)
00031 #define     SDGn_SGCR1_STPM_SHIFT       (6u)
00032 #define     SDGn_SGCR1_SGCK_SHIFT       (3u)
00033 #define     SDGn_SGCR1_DPF_SHIFT        (0u)
00034 
00035 #define     SDGn_SGCSR_SGIE_SHIFT       (7u)
00036 #define     SDGn_SGCSR_SGDEF_SHIFT      (6u)
00037 
00038 #define     SDGn_SGCR2_SGEND_SHIFT      (7u)
00039 #define     SDGn_SGCR2_TCHG_SHIFT       (6u)
00040 
00041 #define     SDGn_SGLR_LD_SHIFT          (0u)
00042 
00043 #define     SDGn_SGTFR_TONE_SHIFT       (0u)
00044 
00045 #define     SDGn_SGSFR_SFS_SHIFT        (0u)
00046 
00047 
00048 #define     SDGn_SGCR1_SGST             (1u << SDGn_SGCR1_SGST_SHIFT)
00049 #define     SDGn_SGCR1_STPM             (1u << SDGn_SGCR1_STPM_SHIFT)
00050 #define     SDGn_SGCR1_SGCK             (0x3u << SDGn_SGCR1_SGCK_SHIFT)
00051 #define     SDGn_SGCR1_DPF              (0x7u << SDGn_SGCR1_DPF_SHIFT)
00052 
00053 #define     SDGn_SGCSR_SGIE             (1u << SDGn_SGCSR_SGIE_SHIFT)
00054 #define     SDGn_SGCSR_SGDEF            (1u << SDGn_SGCSR_SGDEF_SHIFT)
00055 
00056 #define     SDGn_SGCR2_SGEND            (1u << SDGn_SGCR2_SGEND_SHIFT)
00057 #define     SDGn_SGCR2_TCHG             (1u << SDGn_SGCR2_TCHG_SHIFT)
00058 
00059 #define     SDGn_SGLR_LD                (0xFFu << SDGn_SGLR_LD_SHIFT)
00060 
00061 #define     SDGn_SGTFR_TONE             (0x7Fu << SDGn_SGTFR_TONE_SHIFT)
00062 
00063 #define     SDGn_SGSFR_SFS              (0xFFu << SDGn_SGSFR_SFS_SHIFT )
00064 
00065 
00066 
00067 #endif /* SDG_IOBITMASK_H */
00068 
00069 /* End of File */