RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.
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ssif.h
00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer 00021 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 00024 /****************************************************************************** 00025 * File Name : ssif.h 00026 * $Rev: 891 $ 00027 * $Date:: 2014-06-27 10:40:52 +0900#$ 00028 * Description : SSIF driver functions header 00029 ******************************************************************************/ 00030 00031 #ifndef SSIF_H 00032 #define SSIF_H 00033 00034 /******************************************************************************* 00035 Includes <System Includes>, "Project Includes" 00036 *******************************************************************************/ 00037 #include "aioif.h" 00038 #include "iodefine.h" 00039 #include "ssif_if.h" 00040 #include "bsp_drv_cmn.h" 00041 00042 /****************************************************************************** 00043 Macro definitions 00044 ******************************************************************************/ 00045 00046 #define SSIF_CHNUM_0 (0u) 00047 #define SSIF_CHNUM_1 (1u) 00048 #define SSIF_CHNUM_2 (2u) 00049 #define SSIF_CHNUM_3 (3u) 00050 #define SSIF_CHNUM_4 (4u) 00051 #define SSIF_CHNUM_5 (5u) 00052 00053 #define SSIF_CHSTR_0 "\\0" 00054 #define SSIF_CHSTR_1 "\\1" 00055 #define SSIF_CHSTR_2 "\\2" 00056 #define SSIF_CHSTR_3 "\\3" 00057 #define SSIF_CHSTR_4 "\\4" 00058 #define SSIF_CHSTR_5 "\\5" 00059 00060 #define SSIF_MAX_PATH_LEN (32u) 00061 00062 #define SSIF_CR_SHIFT_CKS (30u) 00063 #define SSIF_CR_SHIFT_TUIEN (29u) 00064 #define SSIF_CR_SHIFT_TOIEN (28u) 00065 #define SSIF_CR_SHIFT_RUIEN (27u) 00066 #define SSIF_CR_SHIFT_ROIEN (26u) 00067 #define SSIF_CR_SHIFT_IIEN (25u) 00068 #define SSIF_CR_SHIFT_CHNL (22u) 00069 #define SSIF_CR_SHIFT_DWL (19u) 00070 #define SSIF_CR_SHIFT_SWL (16u) 00071 #define SSIF_CR_SHIFT_SCKD (15u) 00072 #define SSIF_CR_SHIFT_SWSD (14u) 00073 #define SSIF_CR_SHIFT_SCKP (13u) 00074 #define SSIF_CR_SHIFT_SWSP (12u) 00075 #define SSIF_CR_SHIFT_SPDP (11u) 00076 #define SSIF_CR_SHIFT_SDTA (10u) 00077 #define SSIF_CR_SHIFT_PDTA ( 9u) 00078 #define SSIF_CR_SHIFT_DEL ( 8u) 00079 #define SSIF_CR_SHIFT_CKDV ( 4u) 00080 #define SSIF_CR_SHIFT_MUEN ( 3u) 00081 #define SSIF_CR_SHIFT_TEN ( 1u) 00082 #define SSIF_CR_SHIFT_REN ( 0u) 00083 00084 #define SSIF_CR_BIT_CKS (1u << SSIF_CR_SHIFT_CKS) 00085 #define SSIF_CR_BIT_TUIEN (1u << SSIF_CR_SHIFT_TUIEN) 00086 #define SSIF_CR_BIT_TOIEN (1u << SSIF_CR_SHIFT_TOIEN) 00087 #define SSIF_CR_BIT_RUIEN (1u << SSIF_CR_SHIFT_RUIEN) 00088 #define SSIF_CR_BIT_ROIEN (1u << SSIF_CR_SHIFT_ROIEN) 00089 #define SSIF_CR_BIT_IIEN (1u << SSIF_CR_SHIFT_IIEN) 00090 #define SSIF_CR_BITS_CHNL (3u << SSIF_CR_SHIFT_CHNL) 00091 #define SSIF_CR_BITS_DWL (7u << SSIF_CR_SHIFT_DWL) 00092 #define SSIF_CR_BITS_SWL (7u << SSIF_CR_SHIFT_SWL) 00093 #define SSIF_CR_BIT_SCKD (1u << SSIF_CR_SHIFT_SCKD) 00094 #define SSIF_CR_BIT_SWSD (1u << SSIF_CR_SHIFT_SWSD) 00095 #define SSIF_CR_BIT_SCKP (1u << SSIF_CR_SHIFT_SCKP) 00096 #define SSIF_CR_BIT_SWSP (1u << SSIF_CR_SHIFT_SWSP) 00097 #define SSIF_CR_BIT_SPDP (1u << SSIF_CR_SHIFT_SPDP) 00098 #define SSIF_CR_BIT_SDTA (1u << SSIF_CR_SHIFT_SDTA) 00099 #define SSIF_CR_BIT_PDTA (1u << SSIF_CR_SHIFT_PDTA) 00100 #define SSIF_CR_BIT_DEL (1u << SSIF_CR_SHIFT_DEL) 00101 #define SSIF_CR_BITS_CKDV (0xfu << SSIF_CR_SHIFT_CKDV) 00102 #define SSIF_CR_BIT_MUEN (1u << SSIF_CR_SHIFT_MUEN) 00103 #define SSIF_CR_BIT_TEN (1u << SSIF_CR_SHIFT_TEN) 00104 #define SSIF_CR_BIT_REN (1u << SSIF_CR_SHIFT_REN) 00105 #define SSIF_CR_INT_ERR_MASK (SSIF_CR_BIT_TUIEN | SSIF_CR_BIT_TOIEN | SSIF_CR_BIT_RUIEN | SSIF_CR_BIT_ROIEN) 00106 00107 #define SSIF_SR_SHIFT_TUIRQ (29u) 00108 #define SSIF_SR_SHIFT_TOIRQ (28u) 00109 #define SSIF_SR_SHIFT_RUIRQ (27u) 00110 #define SSIF_SR_SHIFT_ROIRQ (26u) 00111 #define SSIF_SR_SHIFT_IIRQ (25u) 00112 #define SSIF_SR_SHIFT_IDST ( 0u) 00113 00114 #define SSIF_SR_BIT_TUIRQ (1u << SSIF_SR_SHIFT_TUIRQ) 00115 #define SSIF_SR_BIT_TOIRQ (1u << SSIF_SR_SHIFT_TOIRQ) 00116 #define SSIF_SR_BIT_RUIRQ (1u << SSIF_SR_SHIFT_RUIRQ) 00117 #define SSIF_SR_BIT_ROIRQ (1u << SSIF_SR_SHIFT_ROIRQ) 00118 #define SSIF_SR_BIT_IIRQ (1u << SSIF_SR_SHIFT_IIRQ) 00119 #define SSIF_SR_BIT_IDST (1u << SSIF_SR_SHIFT_IDST) 00120 #define SSIF_SR_INT_ERR_MASK (SSIF_SR_BIT_TUIRQ | SSIF_SR_BIT_TOIRQ | SSIF_SR_BIT_RUIRQ | SSIF_SR_BIT_ROIRQ) 00121 00122 #define SSIF_FCR_SHIFT_TIE (3u) 00123 #define SSIF_FCR_SHIFT_RIE (2u) 00124 #define SSIF_FCR_SHIFT_TFRST (1u) 00125 #define SSIF_FCR_SHIFT_RFRST (0u) 00126 00127 #define SSIF_FCR_BIT_TIE (1u << SSIF_FCR_SHIFT_TIE) 00128 #define SSIF_FCR_BIT_RIE (1u << SSIF_FCR_SHIFT_RIE) 00129 #define SSIF_FCR_BIT_TFRST (1u << SSIF_FCR_SHIFT_TFRST) 00130 #define SSIF_FCR_BIT_RFRST (1u << SSIF_FCR_SHIFT_RFRST) 00131 00132 #define SSIF_TDMR_SHIFT_CONT (8u) 00133 #define SSIF_TDMR_SHIFT_TDM (0u) 00134 00135 #define SSIF_TDMR_BIT_CONT (1u << SSIF_TDMR_SHIFT_CONT) 00136 #define SSIF_TDMR_BIT_TDM (1u << SSIF_TDMR_SHIFT_TDM) 00137 00138 /* noise canceled bit */ 00139 #define GPIO_SNCR_BIT_SSI5NCE (1u << 5) 00140 #define GPIO_SNCR_BIT_SSI4NCE (1u << 4) 00141 #define GPIO_SNCR_BIT_SSI3NCE (1u << 3) 00142 #define GPIO_SNCR_BIT_SSI2NCE (1u << 2) 00143 #define GPIO_SNCR_BIT_SSI1NCE (1u << 1) 00144 #define GPIO_SNCR_BIT_SSI0NCE (1u << 0) 00145 00146 /****************************************************************************** 00147 Private global variables and functions 00148 ******************************************************************************/ 00149 00150 /************************************************************************* 00151 Enumerated Types 00152 *************************************************************************/ 00153 typedef enum { 00154 SSIF_DRVSTS_UNINIT = 0, 00155 SSIF_DRVSTS_INIT 00156 } ssif_drv_stat_t; 00157 00158 typedef enum 00159 { 00160 SSIF_CHSTS_UNINIT = 0, 00161 SSIF_CHSTS_INIT, 00162 SSIF_CHSTS_OPEN 00163 } ssif_ch_stat_t; 00164 00165 typedef enum 00166 { 00167 SSIF_ASYNC_W = 0, 00168 SSIF_ASYNC_R 00169 } ssif_rw_mode_t; 00170 00171 /** Serial bit clock direction */ 00172 typedef enum 00173 { 00174 SSIF_CFG_CLOCK_IN = 0, /**< Clock IN - Slave mode */ 00175 SSIF_CFG_CLOCK_OUT = 1 /**< Clock OUT - Master mode */ 00176 } ssif_chcfg_clock_dir_t; 00177 00178 00179 /** Serial word select direction */ 00180 typedef enum 00181 { 00182 SSIF_CFG_WS_IN = 0, /**< Word select IN - Slave mode */ 00183 SSIF_CFG_WS_OUT = 1 /**< Word select OUT - Master mode */ 00184 } ssif_chcfg_ws_dir_t; 00185 00186 00187 /************************************************************************* 00188 Structures 00189 *************************************************************************/ 00190 typedef struct ssif_info_ch 00191 { 00192 uint32_t channel; 00193 bool_t enabled; 00194 bool_t slave_mode; 00195 uint32_t sample_freq; 00196 ssif_ch_stat_t ch_stat; 00197 osSemaphoreId sem_access; 00198 AHF_S tx_que; 00199 AHF_S rx_que; 00200 int_t dma_rx_ch; 00201 int_t dma_tx_ch; 00202 bool_t is_full_duplex; /* full/half duplex */ 00203 int_t openflag; 00204 AIOCB* p_aio_tx_curr; 00205 AIOCB* p_aio_tx_next; 00206 AIOCB* p_aio_rx_curr; 00207 AIOCB* p_aio_rx_next; 00208 ssif_chcfg_cks_t clk_select; 00209 ssif_chcfg_multi_ch_t multi_ch; 00210 ssif_chcfg_data_word_t data_word; 00211 ssif_chcfg_system_word_t system_word; 00212 ssif_chcfg_clock_dir_t clock_direction; 00213 ssif_chcfg_ws_dir_t ws_direction; 00214 ssif_chcfg_clock_pol_t bclk_pol; 00215 ssif_chcfg_ws_pol_t ws_pol; 00216 ssif_chcfg_padding_pol_t padding_pol; 00217 ssif_chcfg_serial_alignment_t serial_alignment; 00218 ssif_chcfg_parallel_alignment_t parallel_alignment; 00219 ssif_chcfg_ws_delay_t ws_delay; 00220 ssif_chcfg_noise_cancel_t noise_cancel; 00221 ssif_chcfg_tdm_t tdm_mode; 00222 ssif_chcfg_ckdv_t clk_div; 00223 ssif_chcfg_romdec_t romdec_direct; 00224 } ssif_info_ch_t; 00225 00226 00227 typedef struct ssif_info_drv 00228 { 00229 ssif_drv_stat_t drv_stat; 00230 ssif_info_ch_t info_ch[SSIF_NUM_CHANS]; 00231 } ssif_info_drv_t; 00232 00233 extern volatile struct st_ssif* const g_ssireg[SSIF_NUM_CHANS]; 00234 00235 /****************************************************************************** 00236 Function Prototypes 00237 *****************************************************************************/ 00238 #if(1) /* mbed */ 00239 int_t SSIF_InitialiseOne(const int_t channel, const ssif_channel_cfg_t* const p_cfg_data); 00240 int_t SSIF_UnInitialiseOne(const int_t channel); 00241 #endif /* end mbed */ 00242 int_t SSIF_Initialise(const ssif_channel_cfg_t* const p_cfg_data); 00243 int_t SSIF_UnInitialise(void); 00244 int_t SSIF_EnableChannel(ssif_info_ch_t* const p_info_ch); 00245 int_t SSIF_DisableChannel(ssif_info_ch_t* const p_info_ch); 00246 void SSIF_ErrorRecovery(ssif_info_ch_t* const p_info_ch); 00247 00248 void SSIF_PostAsyncIo(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio); 00249 void SSIF_PostAsyncCancel(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio); 00250 00251 int_t SSIF_IOCTL_ConfigChannel(ssif_info_ch_t* const p_info_ch, 00252 const ssif_channel_cfg_t* const p_ch_cfg); 00253 int_t SSIF_IOCTL_GetStatus(const ssif_info_ch_t* const p_info_ch, uint32_t* const p_status); 00254 00255 int_t SSIF_InitDMA(ssif_info_ch_t* const p_info_ch); 00256 void SSIF_UnInitDMA(ssif_info_ch_t* const p_info_ch); 00257 void SSIF_CancelDMA(const ssif_info_ch_t* const p_info_ch); 00258 int_t SSIF_RestartDMA(ssif_info_ch_t* const p_info_ch); 00259 00260 int_t SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl); 00261 int_t SSIF_DWLtoLen(const ssif_chcfg_data_word_t ssicr_dwl); 00262 00263 extern ssif_info_drv_t g_ssif_info_drv; 00264 00265 #endif /* SSIF_H */
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