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scux_ioctl.c
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00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer* 00021 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 00024 /**************************************************************************//** 00025 * @file scux_ioctl.c 00026 * $Rev: 1674 $ 00027 * $Date:: 2015-05-29 16:35:57 +0900#$ 00028 * @brief SCUX Driver ioctl functions 00029 ******************************************************************************/ 00030 00031 /******************************************************************************* 00032 Includes <System Includes>, "Project Includes" 00033 *******************************************************************************/ 00034 00035 #include "scux.h" 00036 #include "bsp_util.h" 00037 00038 /****************************************************************************** 00039 Exported global variables (to be accessed by other files) 00040 ******************************************************************************/ 00041 00042 /****************************************************************************** 00043 Private global driver management information 00044 ******************************************************************************/ 00045 00046 /****************************************************************************** 00047 Function prototypes 00048 ******************************************************************************/ 00049 00050 /**************************************************************************//** 00051 * Function Name: SCUX_IoctlTransStart 00052 * @brief SCUX transfer start. 00053 * 00054 * Description:<br> 00055 * 00056 * @param[in] channel:SCUX channel number. 00057 * @param[in] p_scux_addr_param:address parameter. 00058 * @retval ESUCCESS : Operation successful. 00059 * EACCES : DVU setup isn't carried out when using DVU. 00060 * EACCES : MIX setup isn't carried out when using MIX. 00061 * EACCES : SSIF setup isn't carried out when using SSIF. 00062 * EACCES : SSIF channel is already used. 00063 * EACCES : When use MIX, it is a setup which does not agree in a route setup. 00064 * EBUSY : It has already transmitted. 00065 * EMFILE : Allocate DMA ch for read is failed. 00066 * EPERM : Transfer parameter is unexpected. 00067 * EFAULT : Internal error is occured. 00068 ******************************************************************************/ 00069 00070 #if(1) /* mbed */ 00071 #if defined (__CC_ARM) 00072 #pragma O0 00073 #endif 00074 #endif /* end mbed */ 00075 int_t SCUX_IoctlTransStart(const int_t channel) 00076 { 00077 int32_t sem_wait_ercd; 00078 int_t retval = ESUCCESS; 00079 uint32_t ssif_sem_ch = 0; 00080 int_t was_masked; 00081 int_t ssif_ch; 00082 osStatus sem_ercd; 00083 scux_ssif_info_t * p_ssif_ch; 00084 scux_ssif_info_t * p_ssif_ch_num[SCUX_SSIF_CH_NUM]; 00085 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 00086 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 00087 00088 /* for processing for the measure against MISRA R1.1 and IPA R3.2.2 */ 00089 for (ssif_ch = 0; ssif_ch < SCUX_SSIF_CH_NUM; ssif_ch++) 00090 { 00091 p_ssif_ch_num[ssif_ch] = SCUX_GetSsifChInfo(ssif_ch); 00092 } 00093 if ((NULL == p_info_drv) || (NULL == p_info_ch)) 00094 { 00095 retval = EFAULT; 00096 } 00097 else 00098 { 00099 /* check using MIX route */ 00100 if (SCUX_ROUTE_MIX == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 00101 { 00102 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00103 sem_wait_ercd = osSemaphoreWait(p_info_drv->shared_info.sem_shared_access, osWaitForever); 00104 /* <-MISRA 10.6 */ 00105 /* semaphore error check */ 00106 if ((-1) == sem_wait_ercd) 00107 { 00108 /* set semaphore error */ 00109 retval = EFAULT; 00110 } 00111 } 00112 00113 if ((SCUX_ROUTE_SSIF == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)) || 00114 (SCUX_ROUTE_MIX == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))) 00115 { 00116 /* check using SSIF route */ 00117 /* mode is async mode only when SSIF direvct route */ 00118 p_info_ch->src_cfg.mode_sync = false; 00119 switch (p_info_ch->route_set) 00120 { 00121 case SCUX_ROUTE_SRC0_MEM : 00122 /* fall through */ 00123 case SCUX_ROUTE_SRC1_MEM : 00124 /* fall through */ 00125 case SCUX_ROUTE_SRC2_MEM : 00126 /* fall through */ 00127 case SCUX_ROUTE_SRC3_MEM : 00128 /* NOTREACHED on At the time of a normal performance */ 00129 break; 00130 00131 case SCUX_ROUTE_SRC0_SSIF0 : 00132 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0]; 00133 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00134 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00135 /* <-MISRA 10.6 */ 00136 /* semaphore error check */ 00137 if ((-1) == sem_wait_ercd) 00138 { 00139 /* set semaphore error */ 00140 retval = EFAULT; 00141 } 00142 else 00143 { 00144 ssif_sem_ch |= (1U << SCUX_SSIF_CH_0); 00145 } 00146 break; 00147 00148 case SCUX_ROUTE_SRC0_SSIF012 : 00149 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0]; 00150 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00151 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00152 /* <-MISRA 10.6 */ 00153 /* semaphore error check */ 00154 if ((-1) == sem_wait_ercd) 00155 { 00156 /* set semaphore error */ 00157 retval = EFAULT; 00158 } 00159 else 00160 { 00161 ssif_sem_ch |= (1U << SCUX_SSIF_CH_0); 00162 } 00163 00164 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1]; 00165 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00166 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00167 /* <-MISRA 10.6 */ 00168 /* semaphore error check */ 00169 if ((-1) == sem_wait_ercd) 00170 { 00171 /* set semaphore error */ 00172 retval = EFAULT; 00173 } 00174 else 00175 { 00176 ssif_sem_ch |= (1U << SCUX_SSIF_CH_1); 00177 } 00178 00179 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2]; 00180 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00181 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00182 /* <-MISRA 10.6 */ 00183 /* semaphore error check */ 00184 if ((-1) == sem_wait_ercd) 00185 { 00186 /* set semaphore error */ 00187 retval = EFAULT; 00188 } 00189 else 00190 { 00191 ssif_sem_ch |= (1U << SCUX_SSIF_CH_2); 00192 } 00193 break; 00194 00195 case SCUX_ROUTE_SRC0_SSIF3 : 00196 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3]; 00197 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00198 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00199 /* <-MISRA 10.6 */ 00200 /* semaphore error check */ 00201 if ((-1) == sem_wait_ercd) 00202 { 00203 /* set semaphore error */ 00204 retval = EFAULT; 00205 } 00206 else 00207 { 00208 ssif_sem_ch |= (1U << SCUX_SSIF_CH_3); 00209 } 00210 break; 00211 00212 case SCUX_ROUTE_SRC0_SSIF345 : 00213 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3]; 00214 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00215 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00216 /* <-MISRA 10.6 */ 00217 /* semaphore error check */ 00218 if ((-1) == sem_wait_ercd) 00219 { 00220 /* set semaphore error */ 00221 retval = EFAULT; 00222 } 00223 else 00224 { 00225 ssif_sem_ch |= (1U << SCUX_SSIF_CH_3); 00226 } 00227 00228 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4]; 00229 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00230 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00231 /* <-MISRA 10.6 */ 00232 /* semaphore error check */ 00233 if ((-1) == sem_wait_ercd) 00234 { 00235 /* set semaphore error */ 00236 retval = EFAULT; 00237 } 00238 else 00239 { 00240 ssif_sem_ch |= (1U << SCUX_SSIF_CH_4); 00241 } 00242 00243 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5]; 00244 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00245 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00246 /* <-MISRA 10.6 */ 00247 /* semaphore error check */ 00248 if ((-1) == sem_wait_ercd) 00249 { 00250 /* set semaphore error */ 00251 retval = EFAULT; 00252 } 00253 else 00254 { 00255 ssif_sem_ch |= (1U << SCUX_SSIF_CH_5); 00256 } 00257 break; 00258 00259 case SCUX_ROUTE_SRC1_SSIF0 : 00260 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0]; 00261 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00262 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00263 /* <-MISRA 10.6 */ 00264 /* semaphore error check */ 00265 if ((-1) == sem_wait_ercd) 00266 { 00267 /* set semaphore error */ 00268 retval = EFAULT; 00269 } 00270 else 00271 { 00272 ssif_sem_ch |= (1U << SCUX_SSIF_CH_0); 00273 } 00274 break; 00275 00276 case SCUX_ROUTE_SRC1_SSIF012 : 00277 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0]; 00278 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00279 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00280 /* <-MISRA 10.6 */ 00281 /* semaphore error check */ 00282 if ((-1) == sem_wait_ercd) 00283 { 00284 /* set semaphore error */ 00285 retval = EFAULT; 00286 } 00287 else 00288 { 00289 ssif_sem_ch |= (1U << SCUX_SSIF_CH_0); 00290 } 00291 00292 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1]; 00293 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00294 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00295 /* <-MISRA 10.6 */ 00296 /* semaphore error check */ 00297 if ((-1) == sem_wait_ercd) 00298 { 00299 /* set semaphore error */ 00300 retval = EFAULT; 00301 } 00302 else 00303 { 00304 ssif_sem_ch |= (1U << SCUX_SSIF_CH_1); 00305 } 00306 00307 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2]; 00308 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00309 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00310 /* <-MISRA 10.6 */ 00311 /* semaphore error check */ 00312 if ((-1) == sem_wait_ercd) 00313 { 00314 /* set semaphore error */ 00315 retval = EFAULT; 00316 } 00317 else 00318 { 00319 ssif_sem_ch |= (1U << SCUX_SSIF_CH_2); 00320 } 00321 break; 00322 00323 case SCUX_ROUTE_SRC1_SSIF3 : 00324 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3]; 00325 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00326 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00327 /* <-MISRA 10.6 */ 00328 /* semaphore error check */ 00329 if ((-1) == sem_wait_ercd) 00330 { 00331 /* set semaphore error */ 00332 retval = EFAULT; 00333 } 00334 else 00335 { 00336 ssif_sem_ch |= (1U << SCUX_SSIF_CH_3); 00337 } 00338 break; 00339 00340 case SCUX_ROUTE_SRC1_SSIF345 : 00341 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3]; 00342 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00343 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00344 /* <-MISRA 10.6 */ 00345 /* semaphore error check */ 00346 if ((-1) == sem_wait_ercd) 00347 { 00348 /* set semaphore error */ 00349 retval = EFAULT; 00350 } 00351 else 00352 { 00353 ssif_sem_ch |= (1U << SCUX_SSIF_CH_3); 00354 } 00355 00356 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4]; 00357 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00358 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00359 /* <-MISRA 10.6 */ 00360 /* semaphore error check */ 00361 if ((-1) == sem_wait_ercd) 00362 { 00363 /* set semaphore error */ 00364 retval = EFAULT; 00365 } 00366 else 00367 { 00368 ssif_sem_ch |= (1U << SCUX_SSIF_CH_4); 00369 } 00370 00371 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5]; 00372 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00373 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00374 /* <-MISRA 10.6 */ 00375 /* semaphore error check */ 00376 if ((-1) == sem_wait_ercd) 00377 { 00378 /* set semaphore error */ 00379 retval = EFAULT; 00380 } 00381 else 00382 { 00383 ssif_sem_ch |= (1U << SCUX_SSIF_CH_5); 00384 } 00385 break; 00386 00387 case SCUX_ROUTE_SRC2_SSIF1 : 00388 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1]; 00389 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00390 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00391 /* <-MISRA 10.6 */ 00392 /* semaphore error check */ 00393 if ((-1) == sem_wait_ercd) 00394 { 00395 /* set semaphore error */ 00396 retval = EFAULT; 00397 } 00398 else 00399 { 00400 ssif_sem_ch |= (1U << SCUX_SSIF_CH_1); 00401 } 00402 break; 00403 00404 case SCUX_ROUTE_SRC2_SSIF4 : 00405 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4]; 00406 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00407 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00408 /* <-MISRA 10.6 */ 00409 /* semaphore error check */ 00410 if ((-1) == sem_wait_ercd) 00411 { 00412 /* set semaphore error */ 00413 retval = EFAULT; 00414 } 00415 else 00416 { 00417 ssif_sem_ch |= (1U << SCUX_SSIF_CH_4); 00418 } 00419 break; 00420 00421 case SCUX_ROUTE_SRC3_SSIF2 : 00422 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2]; 00423 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00424 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00425 /* <-MISRA 10.6 */ 00426 /* semaphore error check */ 00427 if ((-1) == sem_wait_ercd) 00428 { 00429 /* set semaphore error */ 00430 retval = EFAULT; 00431 } 00432 else 00433 { 00434 ssif_sem_ch |= (1U << SCUX_SSIF_CH_2); 00435 } 00436 break; 00437 00438 case SCUX_ROUTE_SRC3_SSIF5 : 00439 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5]; 00440 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00441 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00442 /* <-MISRA 10.6 */ 00443 /* semaphore error check */ 00444 if ((-1) == sem_wait_ercd) 00445 { 00446 /* set semaphore error */ 00447 retval = EFAULT; 00448 } 00449 else 00450 { 00451 ssif_sem_ch |= (1U << SCUX_SSIF_CH_5); 00452 } 00453 break; 00454 00455 case SCUX_ROUTE_SRC0_MIX_SSIF0 : 00456 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0]; 00457 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00458 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00459 /* <-MISRA 10.6 */ 00460 /* semaphore error check */ 00461 if ((-1) == sem_wait_ercd) 00462 { 00463 /* set semaphore error */ 00464 retval = EFAULT; 00465 } 00466 else 00467 { 00468 ssif_sem_ch |= (1U << SCUX_SSIF_CH_0); 00469 } 00470 break; 00471 00472 case SCUX_ROUTE_SRC0_MIX_SSIF012 : 00473 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0]; 00474 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00475 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00476 /* <-MISRA 10.6 */ 00477 /* semaphore error check */ 00478 if ((-1) == sem_wait_ercd) 00479 { 00480 /* set semaphore error */ 00481 retval = EFAULT; 00482 } 00483 else 00484 { 00485 ssif_sem_ch |= (1U << SCUX_SSIF_CH_0); 00486 } 00487 00488 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1]; 00489 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00490 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00491 /* <-MISRA 10.6 */ 00492 /* semaphore error check */ 00493 if ((-1) == sem_wait_ercd) 00494 { 00495 /* set semaphore error */ 00496 retval = EFAULT; 00497 } 00498 else 00499 { 00500 ssif_sem_ch |= (1U << SCUX_SSIF_CH_1); 00501 } 00502 00503 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2]; 00504 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00505 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00506 /* <-MISRA 10.6 */ 00507 /* semaphore error check */ 00508 if ((-1) == sem_wait_ercd) 00509 { 00510 /* set semaphore error */ 00511 retval = EFAULT; 00512 } 00513 else 00514 { 00515 ssif_sem_ch |= (1U << SCUX_SSIF_CH_2); 00516 } 00517 break; 00518 00519 case SCUX_ROUTE_SRC0_MIX_SSIF3 : 00520 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3]; 00521 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00522 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00523 /* <-MISRA 10.6 */ 00524 /* semaphore error check */ 00525 if ((-1) == sem_wait_ercd) 00526 { 00527 /* set semaphore error */ 00528 retval = EFAULT; 00529 } 00530 else 00531 { 00532 ssif_sem_ch |= (1U << SCUX_SSIF_CH_3); 00533 } 00534 break; 00535 00536 case SCUX_ROUTE_SRC0_MIX_SSIF345 : 00537 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3]; 00538 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00539 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00540 /* <-MISRA 10.6 */ 00541 /* semaphore error check */ 00542 if ((-1) == sem_wait_ercd) 00543 { 00544 /* set semaphore error */ 00545 retval = EFAULT; 00546 } 00547 else 00548 { 00549 ssif_sem_ch |= (1U << SCUX_SSIF_CH_3); 00550 } 00551 00552 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4]; 00553 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00554 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00555 /* <-MISRA 10.6 */ 00556 /* semaphore error check */ 00557 if ((-1) == sem_wait_ercd) 00558 { 00559 /* set semaphore error */ 00560 retval = EFAULT; 00561 } 00562 else 00563 { 00564 ssif_sem_ch |= (1U << SCUX_SSIF_CH_4); 00565 } 00566 00567 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5]; 00568 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00569 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00570 /* <-MISRA 10.6 */ 00571 /* semaphore error check */ 00572 if ((-1) == sem_wait_ercd) 00573 { 00574 /* set semaphore error */ 00575 retval = EFAULT; 00576 } 00577 else 00578 { 00579 ssif_sem_ch |= (1U << SCUX_SSIF_CH_5); 00580 } 00581 break; 00582 00583 case SCUX_ROUTE_SRC1_MIX_SSIF0 : 00584 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0]; 00585 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00586 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00587 /* <-MISRA 10.6 */ 00588 /* semaphore error check */ 00589 if ((-1) == sem_wait_ercd) 00590 { 00591 /* set semaphore error */ 00592 retval = EFAULT; 00593 } 00594 else 00595 { 00596 ssif_sem_ch |= (1U << SCUX_SSIF_CH_0); 00597 } 00598 break; 00599 00600 case SCUX_ROUTE_SRC1_MIX_SSIF012 : 00601 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0]; 00602 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00603 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00604 /* <-MISRA 10.6 */ 00605 /* semaphore error check */ 00606 if ((-1) == sem_wait_ercd) 00607 { 00608 /* set semaphore error */ 00609 retval = EFAULT; 00610 } 00611 else 00612 { 00613 ssif_sem_ch |= (1U << SCUX_SSIF_CH_0); 00614 } 00615 00616 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1]; 00617 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00618 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00619 /* <-MISRA 10.6 */ 00620 /* semaphore error check */ 00621 if ((-1) == sem_wait_ercd) 00622 { 00623 /* set semaphore error */ 00624 retval = EFAULT; 00625 } 00626 else 00627 { 00628 ssif_sem_ch |= (1U << SCUX_SSIF_CH_1); 00629 } 00630 00631 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2]; 00632 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00633 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00634 /* <-MISRA 10.6 */ 00635 /* semaphore error check */ 00636 if ((-1) == sem_wait_ercd) 00637 { 00638 /* set semaphore error */ 00639 retval = EFAULT; 00640 } 00641 else 00642 { 00643 ssif_sem_ch |= (1U << SCUX_SSIF_CH_2); 00644 } 00645 break; 00646 00647 case SCUX_ROUTE_SRC1_MIX_SSIF3 : 00648 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3]; 00649 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00650 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00651 /* <-MISRA 10.6 */ 00652 /* semaphore error check */ 00653 if ((-1) == sem_wait_ercd) 00654 { 00655 /* set semaphore error */ 00656 retval = EFAULT; 00657 } 00658 else 00659 { 00660 ssif_sem_ch |= (1U << SCUX_SSIF_CH_3); 00661 } 00662 break; 00663 00664 case SCUX_ROUTE_SRC1_MIX_SSIF345 : 00665 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3]; 00666 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00667 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00668 /* <-MISRA 10.6 */ 00669 /* semaphore error check */ 00670 if ((-1) == sem_wait_ercd) 00671 { 00672 /* set semaphore error */ 00673 retval = EFAULT; 00674 } 00675 else 00676 { 00677 ssif_sem_ch |= (1U << SCUX_SSIF_CH_3); 00678 } 00679 00680 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4]; 00681 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00682 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00683 /* <-MISRA 10.6 */ 00684 /* semaphore error check */ 00685 if ((-1) == sem_wait_ercd) 00686 { 00687 /* set semaphore error */ 00688 retval = EFAULT; 00689 } 00690 else 00691 { 00692 ssif_sem_ch |= (1U << SCUX_SSIF_CH_4); 00693 } 00694 00695 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5]; 00696 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00697 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00698 /* <-MISRA 10.6 */ 00699 /* semaphore error check */ 00700 if ((-1) == sem_wait_ercd) 00701 { 00702 /* set semaphore error */ 00703 retval = EFAULT; 00704 } 00705 else 00706 { 00707 ssif_sem_ch |= (1U << SCUX_SSIF_CH_5); 00708 } 00709 break; 00710 00711 case SCUX_ROUTE_SRC2_MIX_SSIF0 : 00712 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0]; 00713 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00714 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00715 /* <-MISRA 10.6 */ 00716 /* semaphore error check */ 00717 if ((-1) == sem_wait_ercd) 00718 { 00719 /* set semaphore error */ 00720 retval = EFAULT; 00721 } 00722 else 00723 { 00724 ssif_sem_ch |= (1U << SCUX_SSIF_CH_0); 00725 } 00726 break; 00727 00728 case SCUX_ROUTE_SRC2_MIX_SSIF012 : 00729 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0]; 00730 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00731 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00732 /* <-MISRA 10.6 */ 00733 /* semaphore error check */ 00734 if ((-1) == sem_wait_ercd) 00735 { 00736 /* set semaphore error */ 00737 retval = EFAULT; 00738 } 00739 else 00740 { 00741 ssif_sem_ch |= (1U << SCUX_SSIF_CH_0); 00742 } 00743 00744 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1]; 00745 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00746 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00747 /* <-MISRA 10.6 */ 00748 /* semaphore error check */ 00749 if ((-1) == sem_wait_ercd) 00750 { 00751 /* set semaphore error */ 00752 retval = EFAULT; 00753 } 00754 else 00755 { 00756 ssif_sem_ch |= (1U << SCUX_SSIF_CH_1); 00757 } 00758 00759 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2]; 00760 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00761 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00762 /* <-MISRA 10.6 */ 00763 /* semaphore error check */ 00764 if ((-1) == sem_wait_ercd) 00765 { 00766 /* set semaphore error */ 00767 retval = EFAULT; 00768 } 00769 else 00770 { 00771 ssif_sem_ch |= (1U << SCUX_SSIF_CH_2); 00772 } 00773 break; 00774 00775 case SCUX_ROUTE_SRC2_MIX_SSIF3 : 00776 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3]; 00777 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00778 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00779 /* <-MISRA 10.6 */ 00780 /* semaphore error check */ 00781 if ((-1) == sem_wait_ercd) 00782 { 00783 /* set semaphore error */ 00784 retval = EFAULT; 00785 } 00786 else 00787 { 00788 ssif_sem_ch |= (1U << SCUX_SSIF_CH_3); 00789 } 00790 break; 00791 00792 case SCUX_ROUTE_SRC2_MIX_SSIF345 : 00793 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3]; 00794 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00795 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00796 /* <-MISRA 10.6 */ 00797 /* semaphore error check */ 00798 if ((-1) == sem_wait_ercd) 00799 { 00800 /* set semaphore error */ 00801 retval = EFAULT; 00802 } 00803 else 00804 { 00805 ssif_sem_ch |= (1U << SCUX_SSIF_CH_3); 00806 } 00807 00808 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4]; 00809 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00810 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00811 /* <-MISRA 10.6 */ 00812 /* semaphore error check */ 00813 if ((-1) == sem_wait_ercd) 00814 { 00815 /* set semaphore error */ 00816 retval = EFAULT; 00817 } 00818 else 00819 { 00820 ssif_sem_ch |= (1U << SCUX_SSIF_CH_4); 00821 } 00822 00823 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5]; 00824 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00825 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00826 /* <-MISRA 10.6 */ 00827 /* semaphore error check */ 00828 if ((-1) == sem_wait_ercd) 00829 { 00830 /* set semaphore error */ 00831 retval = EFAULT; 00832 } 00833 else 00834 { 00835 ssif_sem_ch |= (1U << SCUX_SSIF_CH_5); 00836 } 00837 break; 00838 00839 case SCUX_ROUTE_SRC3_MIX_SSIF0 : 00840 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0]; 00841 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00842 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00843 /* <-MISRA 10.6 */ 00844 /* semaphore error check */ 00845 if ((-1) == sem_wait_ercd) 00846 { 00847 /* set semaphore error */ 00848 retval = EFAULT; 00849 } 00850 else 00851 { 00852 ssif_sem_ch |= (1U << SCUX_SSIF_CH_0); 00853 } 00854 break; 00855 00856 case SCUX_ROUTE_SRC3_MIX_SSIF012 : 00857 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0]; 00858 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00859 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00860 /* <-MISRA 10.6 */ 00861 /* semaphore error check */ 00862 if ((-1) == sem_wait_ercd) 00863 { 00864 /* set semaphore error */ 00865 retval = EFAULT; 00866 } 00867 else 00868 { 00869 ssif_sem_ch |= (1U << SCUX_SSIF_CH_0); 00870 } 00871 00872 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1]; 00873 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00874 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00875 /* <-MISRA 10.6 */ 00876 /* semaphore error check */ 00877 if ((-1) == sem_wait_ercd) 00878 { 00879 /* set semaphore error */ 00880 retval = EFAULT; 00881 } 00882 else 00883 { 00884 ssif_sem_ch |= (1U << SCUX_SSIF_CH_1); 00885 } 00886 00887 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2]; 00888 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00889 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00890 /* <-MISRA 10.6 */ 00891 /* semaphore error check */ 00892 if ((-1) == sem_wait_ercd) 00893 { 00894 /* set semaphore error */ 00895 retval = EFAULT; 00896 } 00897 else 00898 { 00899 ssif_sem_ch |= (1U << SCUX_SSIF_CH_2); 00900 } 00901 break; 00902 00903 case SCUX_ROUTE_SRC3_MIX_SSIF3 : 00904 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3]; 00905 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00906 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00907 /* <-MISRA 10.6 */ 00908 /* semaphore error check */ 00909 if ((-1) == sem_wait_ercd) 00910 { 00911 /* set semaphore error */ 00912 retval = EFAULT; 00913 } 00914 else 00915 { 00916 ssif_sem_ch |= (1U << SCUX_SSIF_CH_3); 00917 } 00918 break; 00919 00920 case SCUX_ROUTE_SRC3_MIX_SSIF345 : 00921 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3]; 00922 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00923 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00924 /* <-MISRA 10.6 */ 00925 /* semaphore error check */ 00926 if ((-1) == sem_wait_ercd) 00927 { 00928 /* set semaphore error */ 00929 retval = EFAULT; 00930 } 00931 else 00932 { 00933 ssif_sem_ch |= (1U << SCUX_SSIF_CH_3); 00934 } 00935 00936 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4]; 00937 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00938 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00939 /* <-MISRA 10.6 */ 00940 /* semaphore error check */ 00941 if ((-1) == sem_wait_ercd) 00942 { 00943 /* set semaphore error */ 00944 retval = EFAULT; 00945 } 00946 else 00947 { 00948 ssif_sem_ch |= (1U << SCUX_SSIF_CH_4); 00949 } 00950 00951 p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5]; 00952 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 00953 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 00954 /* <-MISRA 10.6 */ 00955 /* semaphore error check */ 00956 if ((-1) == sem_wait_ercd) 00957 { 00958 /* set semaphore error */ 00959 retval = EFAULT; 00960 } 00961 else 00962 { 00963 ssif_sem_ch |= (1U << SCUX_SSIF_CH_5); 00964 } 00965 break; 00966 00967 default : 00968 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 00969 /* <-IPA R3.5.2 */ 00970 /* NOTREACHED on At the time of a normal performance */ 00971 break; 00972 } 00973 } 00974 00975 if (ESUCCESS == retval) 00976 { 00977 retval = SCUX_CheckParam(p_info_ch); 00978 00979 if (ESUCCESS == retval) 00980 { 00981 #if defined (__ICCARM__) 00982 was_masked = __disable_irq_iar(); 00983 #else 00984 was_masked = __disable_irq(); 00985 #endif 00986 SCUX_InitHw(p_info_ch); 00987 if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 00988 { 00989 SCUX_SetupSsif(p_info_ch); 00990 } 00991 00992 SCUX_SetupSrc(p_info_ch); 00993 if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 00994 { 00995 SCUX_SetupDvu(p_info_ch); 00996 } 00997 00998 retval = SCUX_SetupDma(p_info_ch); 00999 01000 if (ESUCCESS == retval) 01001 { 01002 if (false != p_info_ch->src_cfg.mode_sync) 01003 { 01004 SCUX_SyncStartHw(p_info_ch); 01005 } 01006 else 01007 { 01008 SCUX_AsyncStartHw(p_info_ch); 01009 } 01010 p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE; 01011 p_info_ch->p_flush_callback = NULL; 01012 01013 p_info_ch->dma_tx_current_size = 0; 01014 p_info_ch->dma_rx_current_size = 0; 01015 p_info_ch->tx_fifo_total_size = 0; 01016 p_info_ch->rx_fifo_total_size = 0; 01017 01018 p_info_ch->p_tx_aio = NULL; 01019 p_info_ch->p_rx_aio = NULL; 01020 p_info_ch->p_tx_next_aio = NULL; 01021 p_info_ch->p_rx_next_aio = NULL; 01022 p_info_ch->dvu_mute_stat = 0; 01023 p_info_ch->first_ramp_flag = false; 01024 p_info_ch->cancel_operate_flag = false; 01025 p_info_ch->restart_ramp_flag = false; 01026 p_info_ch->err_stat_backup = ESUCCESS; 01027 } 01028 01029 if (0 == was_masked) 01030 { 01031 __enable_irq(); 01032 } 01033 } 01034 } 01035 01036 for (ssif_ch = 0; ssif_ch < SCUX_SSIF_CH_NUM; ssif_ch++) 01037 { 01038 if (0U != (ssif_sem_ch & (1U << ssif_ch))) 01039 { 01040 p_ssif_ch = p_ssif_ch_num[ssif_ch]; 01041 sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access); 01042 /* semaphore error check */ 01043 if (osOK != sem_ercd) 01044 { 01045 /* set semaphore error */ 01046 retval = EFAULT; 01047 p_info_ch->ch_stat = SCUX_CH_STOP; 01048 } 01049 } 01050 } 01051 01052 /* check using MIX route */ 01053 if (SCUX_ROUTE_MIX == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 01054 { 01055 sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access); 01056 /* semaphore error check */ 01057 if (osOK != sem_ercd) 01058 { 01059 /* set semaphore error */ 01060 retval = EFAULT; 01061 p_info_ch->ch_stat = SCUX_CH_STOP; 01062 } 01063 } 01064 } 01065 01066 return retval; 01067 } 01068 #if(1) /* mbed */ 01069 #if defined (__CC_ARM) 01070 #pragma O3 01071 #endif 01072 #endif /* end mbed */ 01073 01074 /****************************************************************************** 01075 End of function SCUX_IoctlTransStart 01076 ******************************************************************************/ 01077 01078 /**************************************************************************//** 01079 * Function Name: SCUX_IoctlFlushStop 01080 * @brief Set flush stop paramter. 01081 * 01082 * Description:<br> 01083 * 01084 * @param[in] channel:SCUX channel number. 01085 * @param[in] (*callback)(void):callback function pointer. 01086 * @param[in] was_masked:interrupt enable information. 01087 * @retval ESUCCESS : Operation successful. 01088 * EFAULT : Internal error is occured. 01089 ******************************************************************************/ 01090 01091 int_t SCUX_IoctlFlushStop(const int_t channel, void (* const callback)(int_t), const int_t was_masked) 01092 { 01093 int_t retval = ESUCCESS; 01094 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 01095 01096 if (NULL == p_info_ch) 01097 { 01098 retval = EFAULT; 01099 } 01100 else 01101 { 01102 if (SCUX_ROUTE_MEM_TO_MEM == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 01103 { 01104 /* mem to mem route */ 01105 if ((SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) || (SCUX_CH_TRANS_RD == p_info_ch->ch_stat)) 01106 { 01107 /* Flush process is performed only when dummy buffer transmission has not been started yet */ 01108 if (false == p_info_ch->tx_dummy_run_flag) 01109 { 01110 /* start flush write */ 01111 retval = SCUX_FlushWriteStart(p_info_ch); 01112 } 01113 01114 if (ESUCCESS == retval) 01115 { 01116 /* memory to memory route */ 01117 if (SCUX_CH_TRANS_RD == p_info_ch->ch_stat) 01118 { 01119 p_info_ch->ch_stat = SCUX_CH_STOP_WAIT; 01120 } 01121 else 01122 { 01123 p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE; 01124 } 01125 p_info_ch->p_flush_callback = callback; 01126 } 01127 } 01128 else 01129 { 01130 /* on going write process */ 01131 /* status is SCUX_CH_TRANS_WR, SCUX_CH_TRANS_RDWR, SCUX_CH_STOP_WAIT, SCUX_CH_STOP_WAIT_IDLE */ 01132 if (SCUX_CH_TRANS_RDWR == p_info_ch->ch_stat) 01133 { 01134 p_info_ch->ch_stat = SCUX_CH_STOP_WAIT; 01135 } 01136 if (SCUX_CH_TRANS_WR == p_info_ch->ch_stat) 01137 { 01138 p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE; 01139 } 01140 01141 p_info_ch->p_flush_callback = callback; 01142 } 01143 } 01144 else 01145 { 01146 /* SSIF direct route */ 01147 if (SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) 01148 { 01149 /* Flush process is performed only when dummy buffer transmission has not been started yet */ 01150 if (false == p_info_ch->tx_dummy_run_flag) 01151 { 01152 /* start flush write */ 01153 retval = SCUX_FlushWriteStart(p_info_ch); 01154 } 01155 01156 if (ESUCCESS == retval) 01157 { 01158 /* memory to memory route */ 01159 p_info_ch->ch_stat = SCUX_CH_STOP_WAIT; 01160 p_info_ch->p_flush_callback = callback; 01161 } 01162 } 01163 else 01164 { 01165 /* on going write process */ 01166 p_info_ch->ch_stat = SCUX_CH_STOP_WAIT; 01167 p_info_ch->p_flush_callback = callback; 01168 01169 } 01170 } 01171 } 01172 01173 if (0 == was_masked) 01174 { 01175 /* enable all irq */ 01176 __enable_irq(); 01177 } 01178 01179 return retval; 01180 } 01181 01182 /****************************************************************************** 01183 End of function SCUX_IoctlFlushStop 01184 ******************************************************************************/ 01185 01186 /**************************************************************************//** 01187 * Function Name: SCUX_IoctlClearStop 01188 * @brief Set flush stop paramter. 01189 * 01190 * Description:<br> 01191 * 01192 * @param[in] channel:SCUX channel number. 01193 * @retval ESUCCESS : Operation successful. 01194 * EFAULT : Internal error is occured. 01195 ******************************************************************************/ 01196 01197 int_t SCUX_IoctlClearStop(const int_t channel, const int_t was_masked) 01198 { 01199 int_t retval = ESUCCESS; 01200 int_t dma_ercd; 01201 int_t dma_retval; 01202 scux_stat_ch_t old_stat; 01203 uint32_t rx_remain_size = 0; 01204 uint32_t tx_remain_size = 0; 01205 01206 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 01207 if (NULL == p_info_ch) 01208 { 01209 retval = EFAULT; 01210 if (0 == was_masked) 01211 { 01212 /* enable all irq */ 01213 __enable_irq(); 01214 } 01215 } 01216 else 01217 { 01218 if (SCUX_ROUTE_MEM_TO_MEM == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 01219 { 01220 /* memory to memory route */ 01221 dma_retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd); 01222 /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */ 01223 if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd)) 01224 { 01225 retval = EFAULT; 01226 } 01227 else 01228 { 01229 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size; 01230 p_info_ch->dma_tx_current_size = 0; 01231 } 01232 01233 dma_retval = R_DMA_Cancel(p_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd); 01234 /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */ 01235 if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd)) 01236 { 01237 retval = EFAULT; 01238 } 01239 else 01240 { 01241 p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size; 01242 p_info_ch->dma_rx_current_size = 0; 01243 01244 dma_retval = R_DMA_Free(p_info_ch->dma_rx_ch, NULL); 01245 if (ESUCCESS != dma_retval) 01246 { 01247 retval = EFAULT; 01248 } 01249 } 01250 01251 if (ESUCCESS == retval) 01252 { 01253 /* return write request */ 01254 if (NULL != p_info_ch->p_tx_aio) 01255 { 01256 p_info_ch->p_tx_aio->aio_return = (ssize_t)(p_info_ch->p_tx_aio->aio_nbytes - tx_remain_size); 01257 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio); 01258 } 01259 01260 /* return read request */ 01261 if (NULL != p_info_ch->p_rx_aio) 01262 { 01263 p_info_ch->p_rx_aio->aio_return = (ssize_t)(p_info_ch->p_rx_aio->aio_nbytes - rx_remain_size); 01264 ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio); 01265 } 01266 01267 ahf_cancelall(&p_info_ch->tx_que); 01268 ahf_cancelall(&p_info_ch->rx_que); 01269 01270 p_info_ch->p_tx_aio = NULL; 01271 p_info_ch->p_rx_aio = NULL; 01272 } 01273 } 01274 else 01275 { 01276 /* SSIF direct route */ 01277 dma_retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd); 01278 /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */ 01279 if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd)) 01280 { 01281 retval = EFAULT; 01282 } 01283 else 01284 { 01285 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size; 01286 p_info_ch->dma_tx_current_size = 0; 01287 } 01288 01289 if (ESUCCESS == retval) 01290 { 01291 /* return the request after 2nd */ 01292 if (false == p_info_ch->first_tx_flag) 01293 { 01294 /* return current aio request */ 01295 if (NULL != p_info_ch->p_tx_aio) 01296 { 01297 p_info_ch->p_tx_aio->aio_return = (ssize_t)(p_info_ch->p_tx_aio->aio_nbytes - tx_remain_size); 01298 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio); 01299 } 01300 /* return next aio request */ 01301 if (NULL != p_info_ch->p_tx_next_aio) 01302 { 01303 p_info_ch->p_tx_next_aio->aio_return = ECANCELED; 01304 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_next_aio); 01305 } 01306 } 01307 else 01308 { 01309 /* return the 1st request */ 01310 if (NULL == p_info_ch->p_tx_aio) 01311 { 01312 /* return the first half part of a 1st request */ 01313 if (NULL != p_info_ch->p_tx_next_aio) 01314 { 01315 p_info_ch->p_tx_next_aio->aio_return 01316 = (ssize_t)((p_info_ch->p_tx_next_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE) - tx_remain_size); 01317 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_next_aio); 01318 } 01319 } 01320 else 01321 { 01322 /* return the second half part of a 1st request */ 01323 p_info_ch->p_tx_aio->aio_return 01324 = (ssize_t)(p_info_ch->p_tx_aio->aio_nbytes - tx_remain_size); 01325 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio); 01326 01327 /* in case of the next request is acquired */ 01328 if (NULL != p_info_ch->p_tx_next_aio) 01329 { 01330 p_info_ch->p_tx_next_aio->aio_return = ECANCELED; 01331 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_next_aio); 01332 } 01333 } 01334 } 01335 ahf_cancelall(&p_info_ch->tx_que); 01336 01337 p_info_ch->p_tx_aio = NULL; 01338 p_info_ch->p_tx_next_aio = NULL; 01339 } 01340 } 01341 01342 if (ESUCCESS == retval) 01343 { 01344 SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, rx_remain_size); 01345 if (false != p_info_ch->src_cfg.mode_sync) 01346 { 01347 SCUX_SyncStopHw(p_info_ch); 01348 } 01349 else 01350 { 01351 SCUX_AsyncStopHw(p_info_ch); 01352 } 01353 01354 old_stat = p_info_ch->ch_stat; 01355 p_info_ch->ch_stat = SCUX_CH_STOP; 01356 01357 if (0 == was_masked) 01358 { 01359 /* enable all irq */ 01360 __enable_irq(); 01361 } 01362 01363 if ((SCUX_CH_STOP_WAIT == old_stat) || (SCUX_CH_STOP_WAIT_IDLE == old_stat)) 01364 { 01365 p_info_ch->p_flush_callback(ECANCELED); 01366 p_info_ch->p_flush_callback = NULL; 01367 } 01368 } 01369 else 01370 { 01371 if (0 == was_masked) 01372 { 01373 /* enable all irq */ 01374 __enable_irq(); 01375 } 01376 } 01377 } 01378 01379 return retval; 01380 } 01381 01382 /****************************************************************************** 01383 End of function SCUX_IoctlClearStop 01384 ******************************************************************************/ 01385 01386 /**************************************************************************//** 01387 * Function Name: SCUX_IoctlSetRoute 01388 * @brief Set SCUX data transfer route. 01389 * 01390 * Description:<br> 01391 * 01392 * @param[in] channel:SCUX channel number. 01393 * @param[in] route:route parameter. 01394 * @retval None. 01395 ******************************************************************************/ 01396 01397 void SCUX_IoctlSetRoute(const int_t channel, const scux_route_t route) 01398 { 01399 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 01400 01401 if (NULL == p_info_ch) 01402 { 01403 /* NON_NOTICE_ASSERT: NULL pointer */ 01404 } 01405 else 01406 { 01407 p_info_ch->route_set = route; 01408 } 01409 01410 return; 01411 } 01412 01413 /****************************************************************************** 01414 End of function SCUX_IoctlSetRoute 01415 ******************************************************************************/ 01416 01417 01418 /**************************************************************************//** 01419 * Function Name: SCUX_IoctlSetPinClk 01420 * @brief Set clock source for AUDIO_CLK pin. 01421 * 01422 * Description:<br> 01423 * 01424 * @param[in] channel:SCUX channel number. 01425 * @param[in] *p_pin_clk_param:clock source parameter. 01426 * @retval ESUCCESS:Operation successful. 01427 * EPERM:Parameter is unexpected value. 01428 * EFAULT:Internal error is occured. 01429 ******************************************************************************/ 01430 01431 int_t SCUX_IoctlSetPinClk(const int_t channel, const scux_ssif_pin_clk_t * const p_pin_clk_param) 01432 { 01433 int_t retval = ESUCCESS; 01434 int32_t sem_wait_ercd; 01435 osStatus sem_ercd; 01436 scux_ssif_info_t * p_ssif_ch; 01437 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 01438 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 01439 01440 if ((NULL == p_info_drv) || (NULL == p_info_ch) || (NULL == p_pin_clk_param)) 01441 { 01442 retval = EFAULT; 01443 } 01444 else 01445 { 01446 /* check SSIF channel number */ 01447 if (SCUX_SSIF_CH_NUM > p_pin_clk_param->ssif_ch_num) 01448 { 01449 p_ssif_ch = SCUX_GetSsifChInfo((int_t)p_pin_clk_param->ssif_ch_num); 01450 if (NULL == p_ssif_ch) 01451 { 01452 retval = EFAULT; 01453 } 01454 else 01455 { 01456 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 01457 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 01458 /* <-MISRA 10.6 */ 01459 /* semaphore error check */ 01460 if ((-1) == sem_wait_ercd) 01461 { 01462 /* set semaphore error */ 01463 retval = EFAULT; 01464 } 01465 else 01466 { 01467 /* check clock source parameter */ 01468 if ((SCUX_CLK_AUDIO_CLK == p_pin_clk_param->pin_clk) || (SCUX_CLK_MLB_CLK == p_pin_clk_param->pin_clk)) 01469 { 01470 p_ssif_ch->pin_clk = p_pin_clk_param->pin_clk; 01471 } 01472 else 01473 { 01474 retval = EPERM; 01475 } 01476 } 01477 sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access); 01478 /* semaphore error check */ 01479 if (osOK != sem_ercd) 01480 { 01481 /* set semaphore error */ 01482 retval = EFAULT; 01483 } 01484 01485 if (ESUCCESS == retval) 01486 { 01487 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 01488 sem_wait_ercd = osSemaphoreWait(p_info_drv->shared_info.sem_shared_access, osWaitForever); 01489 /* <-MISRA 10.6 */ 01490 /* semaphore error check */ 01491 if ((-1) == sem_wait_ercd) 01492 { 01493 /* set semaphore error */ 01494 retval = EFAULT; 01495 } 01496 else 01497 { 01498 if (SCUX_CLK_MLB_CLK == p_pin_clk_param->pin_clk) 01499 { 01500 /* set MLB_CLK */ 01501 *(p_info_ch->p_scux_reg->ssipmd_cim) |= (SSIPMD_CIM_SSI0CKS_SET << p_pin_clk_param->ssif_ch_num); 01502 } 01503 else 01504 { 01505 /* set AUDIO_CLK */ 01506 *(p_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI0CKS_SET << p_pin_clk_param->ssif_ch_num); 01507 } 01508 } 01509 01510 sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access); 01511 /* semaphore error check */ 01512 if (osOK != sem_ercd) 01513 { 01514 /* set semaphore error */ 01515 retval = EFAULT; 01516 } 01517 } 01518 } 01519 } 01520 else 01521 { 01522 retval = EPERM; 01523 } 01524 } 01525 01526 return retval; 01527 } 01528 01529 /****************************************************************************** 01530 End of function SCUX_IoctlSetPinClk 01531 ******************************************************************************/ 01532 01533 /**************************************************************************//** 01534 * Function Name: SCUX_IoctlSetPinMode 01535 * @brief Set synchronous setting for each SSIP pin. 01536 * 01537 * Description:<br> 01538 * 01539 * @param[in] channel:SCUX channel number. 01540 * @param[in] *p_pin_mode_param:synchronous setting parameter. 01541 * @retval ESUCCESS:Operation successful. 01542 * EPERM:Parameter is unexpected value. 01543 * EFAUT:Internal error is occured. 01544 ******************************************************************************/ 01545 01546 int_t SCUX_IoctlSetPinMode(const int_t channel, const scux_ssif_pin_mode_t * const p_pin_mode_param) 01547 { 01548 int_t retval = ESUCCESS; 01549 uint32_t ssipmd_reg; 01550 uint32_t ssipmd_mask = 0; 01551 uint32_t ssipmd_shift = 0; 01552 osStatus sem_ercd; 01553 int32_t sem_wait_ercd; 01554 scux_ssif_info_t * p_ssif_ch; 01555 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 01556 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 01557 01558 if ((NULL == p_info_drv) || (NULL == p_info_ch) || (NULL == p_pin_mode_param)) 01559 { 01560 retval = EFAULT; 01561 } 01562 else 01563 { 01564 /* check SSIF channel number (disable setting for SSIF0) */ 01565 if (SCUX_SSIF_CH_NUM > p_pin_mode_param->ssif_ch_num) 01566 { 01567 p_ssif_ch = SCUX_GetSsifChInfo((int_t)p_pin_mode_param->ssif_ch_num); 01568 if (NULL == p_ssif_ch) 01569 { 01570 retval = EFAULT; 01571 } 01572 else 01573 { 01574 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 01575 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 01576 /* <-MISRA 10.6 */ 01577 /* semaphore error check */ 01578 if ((-1) == sem_wait_ercd) 01579 { 01580 /* set semaphore error */ 01581 retval = EFAULT; 01582 } 01583 else 01584 { 01585 /* check clock source parameter */ 01586 if ((SCUX_PIN_MODE_MIN < p_pin_mode_param->pin_mode) || (SCUX_PIN_MODE_MAX > p_pin_mode_param->pin_mode)) 01587 { 01588 p_ssif_ch->pin_mode = p_pin_mode_param->pin_mode; 01589 } 01590 else 01591 { 01592 retval = EPERM; 01593 } 01594 } 01595 sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access); 01596 /* semaphore error check */ 01597 if (osOK != sem_ercd) 01598 { 01599 /* set semaphore error */ 01600 retval = EFAULT; 01601 } 01602 01603 if (ESUCCESS == retval) 01604 { 01605 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 01606 sem_wait_ercd = osSemaphoreWait(p_info_drv->shared_info.sem_shared_access, osWaitForever); 01607 /* <-MISRA 10.6 */ 01608 /* semaphore error check */ 01609 if ((-1) == sem_wait_ercd) 01610 { 01611 /* set semaphore error */ 01612 retval = EFAULT; 01613 } 01614 else 01615 { 01616 /* pin_mode setup to SSIF0 does not exist */ 01617 if (SCUX_SSIF_CH_0 != p_pin_mode_param->ssif_ch_num) 01618 { 01619 switch (p_pin_mode_param->ssif_ch_num) 01620 { 01621 case SCUX_SSIF_CH_1 : 01622 ssipmd_mask = SSIPMD_CIM_SSI1PMD_MASK; 01623 ssipmd_shift = SSIPMD_CIM_SSI1PMD_SHIFT; 01624 break; 01625 01626 case SCUX_SSIF_CH_2 : 01627 ssipmd_mask = SSIPMD_CIM_SSI2PMD_MASK; 01628 ssipmd_shift = SSIPMD_CIM_SSI2PMD_SHIFT; 01629 break; 01630 01631 case SCUX_SSIF_CH_3 : 01632 ssipmd_mask = SSIPMD_CIM_SSI3PMD_MASK; 01633 ssipmd_shift = SSIPMD_CIM_SSI3PMD_SHIFT; 01634 break; 01635 01636 case SCUX_SSIF_CH_4 : 01637 ssipmd_mask = SSIPMD_CIM_SSI4PMD_MASK; 01638 ssipmd_shift = SSIPMD_CIM_SSI4PMD_SHIFT; 01639 break; 01640 01641 case SCUX_SSIF_CH_5 : 01642 ssipmd_mask = SSIPMD_CIM_SSI5PMD_MASK; 01643 ssipmd_shift = SSIPMD_CIM_SSI5PMD_SHIFT; 01644 break; 01645 01646 default : 01647 /* SCUX channel is 6 oe more */ 01648 retval = EPERM; 01649 break; 01650 } 01651 01652 if (ESUCCESS == retval) 01653 { 01654 ssipmd_reg = *(p_info_ch->p_scux_reg->ssipmd_cim); 01655 ssipmd_reg &= ~ssipmd_mask; 01656 01657 /* ->IPA R2.4.1 Even if pinmode and ssipmd_shift are max value, omission dose not occur. */ 01658 *(p_info_ch->p_scux_reg->ssipmd_cim) = (ssipmd_reg | ((uint32_t)p_pin_mode_param->pin_mode << ssipmd_shift)); 01659 /* <-IPA R2.4.1 */ 01660 } 01661 } 01662 } 01663 01664 sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access); 01665 /* semaphore error check */ 01666 if (osOK != sem_ercd) 01667 { 01668 /* set semaphore error */ 01669 retval = EFAULT; 01670 } 01671 } 01672 } 01673 } 01674 else 01675 { 01676 retval = EPERM; 01677 } 01678 } 01679 01680 return retval; 01681 } 01682 01683 /****************************************************************************** 01684 End of function SCUX_IoctlSetPinMode 01685 ******************************************************************************/ 01686 01687 /**************************************************************************//** 01688 * Function Name: SCUX_IoctlSetSrcCfg 01689 * @brief Set SRC paramter. 01690 * 01691 * Description:<br> 01692 * 01693 * @param[in] channel:SCUX channel number. 01694 * @param[in] *p_src_param:SRC parameter. 01695 * @retval None. 01696 ******************************************************************************/ 01697 01698 void SCUX_IoctlSetSrcCfg(const int_t channel, const scux_src_cfg_t * const p_src_param) 01699 { 01700 scux_audio_channel_t audio_ch; 01701 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 01702 01703 if ((NULL == p_info_ch) || (NULL == p_src_param)) 01704 { 01705 /* NON_NOTICE_ASSERT: NULL pointer */ 01706 } 01707 else 01708 { 01709 p_info_ch->src_cfg.src_enable = p_src_param->src_enable; 01710 p_info_ch->src_cfg.use_ch = p_src_param->use_ch; 01711 p_info_ch->src_cfg.word_len = p_src_param->word_len; 01712 p_info_ch->src_cfg.mode_sync = p_src_param->mode_sync; 01713 p_info_ch->src_cfg.input_rate_sync = p_src_param->input_rate_sync; 01714 p_info_ch->src_cfg.input_clk_async = p_src_param->input_clk_async; 01715 p_info_ch->src_cfg.input_div_async = p_src_param->input_div_async; 01716 p_info_ch->src_cfg.output_rate_sync = p_src_param->output_rate_sync; 01717 p_info_ch->src_cfg.output_clk_async = p_src_param->output_clk_async; 01718 p_info_ch->src_cfg.output_div_async = p_src_param->output_div_async; 01719 p_info_ch->src_cfg.delay_mode = p_src_param->delay_mode; 01720 p_info_ch->src_cfg.wait_sample = p_src_param->wait_sample; 01721 p_info_ch->src_cfg.min_rate_percentage = p_src_param->min_rate_percentage; 01722 p_info_ch->src_cfg.output_ws = p_src_param->output_ws; 01723 p_info_ch->src_cfg.input_ws = p_src_param->input_ws; 01724 p_info_ch->src_cfg.freq_tioc3a = p_src_param->freq_tioc3a; 01725 p_info_ch->src_cfg.freq_tioc4a = p_src_param->freq_tioc4a; 01726 for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++) 01727 { 01728 p_info_ch->src_cfg.select_in_data_ch[audio_ch] = p_src_param->select_in_data_ch[audio_ch]; 01729 } 01730 } 01731 01732 return; 01733 } 01734 01735 /****************************************************************************** 01736 End of function SCUX_IoctlSetSrcCfg 01737 ******************************************************************************/ 01738 01739 /**************************************************************************//** 01740 * Function Name: SCUX_IoctlSetDvuCfg 01741 * @brief Set DVU parameter. 01742 * 01743 * Description:<br> 01744 * 01745 * @param[in] channel:SCUX channel number. 01746 * @param[in] *p_dvu_param:DVU parameter. 01747 * @retval None. 01748 ******************************************************************************/ 01749 01750 void SCUX_IoctlSetDvuCfg(const int_t channel, const scux_dvu_cfg_t * const p_dvu_param) 01751 { 01752 scux_audio_channel_t audio_ch; 01753 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 01754 01755 if ((NULL == p_info_ch) || (NULL == p_dvu_param)) 01756 { 01757 /* NON_NOTICE_ASSERT: NULL pointer */ 01758 } 01759 else 01760 { 01761 p_info_ch->dvu_cfg.dvu_enable = p_dvu_param->dvu_enable; 01762 01763 /* digital volume setting */ 01764 p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable = p_dvu_param->dvu_digi_vol.digi_vol_enable; 01765 for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++) 01766 { 01767 p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch] = p_dvu_param->dvu_digi_vol.digi_vol[audio_ch]; 01768 } 01769 01770 /* ramp volume setting */ 01771 for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++) 01772 { 01773 p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch] = p_dvu_param->dvu_ramp_vol.ramp_vol_enable[audio_ch]; 01774 } 01775 p_info_ch->dvu_cfg.dvu_ramp_vol.up_period = p_dvu_param->dvu_ramp_vol.up_period; 01776 p_info_ch->dvu_cfg.dvu_ramp_vol.down_period = p_dvu_param->dvu_ramp_vol.down_period; 01777 p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol = p_dvu_param->dvu_ramp_vol.ramp_vol; 01778 p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time = p_dvu_param->dvu_ramp_vol.ramp_wait_time; 01779 01780 /* zerocross mute setting */ 01781 for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++) 01782 { 01783 p_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch] = p_dvu_param->dvu_zc_mute.zc_mute_enable[audio_ch]; 01784 p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[audio_ch] = p_dvu_param->dvu_zc_mute.pcallback[audio_ch]; 01785 } 01786 01787 p_info_ch->dvu_setup = true; 01788 } 01789 01790 return; 01791 } 01792 01793 /****************************************************************************** 01794 End of function SCUX_IoctlSetDvuCfg 01795 ******************************************************************************/ 01796 01797 /**************************************************************************//** 01798 * Function Name: SCUX_IoctlSetDvuDigiVol 01799 * @brief Set Digital volume parameter. 01800 * 01801 * Description:<br> 01802 * 01803 * @param[in] channel:SCUX channel number. 01804 * @param[in] *p_dvu_param:Digital volume parameter. 01805 * @retval ESUCCESS:Operation successful. 01806 * EPERM:Parameter is unexpected value. 01807 * EFAULT : Internal error is occured. 01808 ******************************************************************************/ 01809 01810 int_t SCUX_IoctlSetDvuDigiVol(const int_t channel, const scux_dvu_digi_vol_t * const p_digi_vol_param) 01811 { 01812 int_t retval = ESUCCESS; 01813 int_t was_masked; 01814 scux_audio_channel_t audio_ch; 01815 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 01816 01817 if ((NULL == p_info_ch) || (NULL == p_digi_vol_param)) 01818 { 01819 retval = EFAULT; 01820 } 01821 else 01822 { 01823 /* digital volume setting */ 01824 p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable = p_digi_vol_param->digi_vol_enable; 01825 for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++) 01826 { 01827 p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch] = p_digi_vol_param->digi_vol[audio_ch]; 01828 } 01829 01830 /* check digital volume */ 01831 for (audio_ch = SCUX_AUDIO_CH_0; ((ESUCCESS == retval) && (audio_ch < p_info_ch->src_cfg.use_ch)); audio_ch++) 01832 { 01833 if (SCUX_MAX_DIGITAL_VOLUME < p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch]) 01834 { 01835 retval = EPERM; 01836 } 01837 } 01838 01839 if (ESUCCESS == retval) 01840 { 01841 #if defined (__ICCARM__) 01842 was_masked = __disable_irq_iar(); 01843 #else 01844 was_masked = __disable_irq(); 01845 #endif 01846 01847 if (SCUX_CH_STOP != p_info_ch->ch_stat) 01848 { 01849 p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET; 01850 01851 /* set parameter for register */ 01852 SCUX_SetDigiVolRegister(p_info_ch); 01853 01854 p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET; 01855 } 01856 01857 if (0 == was_masked) 01858 { 01859 __enable_irq(); 01860 } 01861 } 01862 } 01863 01864 return retval; 01865 } 01866 01867 /****************************************************************************** 01868 End of function SCUX_IoctlSetDvuDigiVol 01869 ******************************************************************************/ 01870 01871 /**************************************************************************//** 01872 * Function Name: SCUX_IoctlSetDvuRampVol 01873 * @brief Set Digital volume parameter. 01874 * 01875 * Description:<br> 01876 * 01877 * @param[in] channel:SCUX channel number. 01878 * @param[in] *p_dvu_param:Digital volume parameter. 01879 * @retval ESUCCESS:Operation successful. 01880 * EPERM:Parameter is unexpected value. 01881 * EFAULT : Internal error is occured. 01882 ******************************************************************************/ 01883 01884 int_t SCUX_IoctlSetDvuRampVol(const int_t channel, const scux_dvu_ramp_vol_t * const p_ramp_vol_param) 01885 { 01886 int_t retval = ESUCCESS; 01887 int_t was_masked; 01888 scux_audio_channel_t audio_ch; 01889 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 01890 01891 if ((NULL == p_info_ch) || (NULL == p_ramp_vol_param)) 01892 { 01893 retval = EFAULT; 01894 } 01895 else 01896 { 01897 /* ramp volume setting */ 01898 for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++) 01899 { 01900 p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch] = p_ramp_vol_param->ramp_vol_enable[audio_ch]; 01901 } 01902 p_info_ch->dvu_cfg.dvu_ramp_vol.up_period = p_ramp_vol_param->up_period; 01903 p_info_ch->dvu_cfg.dvu_ramp_vol.down_period = p_ramp_vol_param->down_period; 01904 p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol = p_ramp_vol_param->ramp_vol; 01905 p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time = p_ramp_vol_param->ramp_wait_time; 01906 01907 /* check ramp volume */ 01908 /* check ramp down period */ 01909 if ((p_info_ch->dvu_cfg.dvu_ramp_vol.down_period <= SCUX_DVU_TIME_MIN) || 01910 (p_info_ch->dvu_cfg.dvu_ramp_vol.down_period >= SCUX_DVU_TIME_MAX)) 01911 { 01912 retval = EPERM; 01913 } 01914 01915 if (ESUCCESS == retval) 01916 { 01917 /* check ramp up period */ 01918 if ((p_info_ch->dvu_cfg.dvu_ramp_vol.up_period <= SCUX_DVU_TIME_MIN) || 01919 (p_info_ch->dvu_cfg.dvu_ramp_vol.up_period >= SCUX_DVU_TIME_MAX)) 01920 { 01921 retval = EPERM; 01922 } 01923 } 01924 01925 if (ESUCCESS == retval) 01926 { 01927 /* check ramp volume */ 01928 if (SCUX_MAX_RAMP_VOLUME < p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol) 01929 { 01930 retval = EPERM; 01931 } 01932 } 01933 01934 if (ESUCCESS != retval) 01935 { 01936 /* check wait time */ 01937 if (SCUX_MAX_WAIT_TIME < p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time) 01938 { 01939 retval = EPERM; 01940 } 01941 } 01942 01943 if (ESUCCESS == retval) 01944 { 01945 #if defined (__ICCARM__) 01946 was_masked = __disable_irq_iar(); 01947 #else 01948 was_masked = __disable_irq(); 01949 #endif 01950 01951 if ((SCUX_CH_STOP != p_info_ch->ch_stat) && (false != p_info_ch->first_ramp_flag)) 01952 { 01953 p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET; 01954 01955 /* set parameter for register */ 01956 SCUX_SetRampVolRegister(p_info_ch); 01957 01958 p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET; 01959 } 01960 01961 /* an updating setting is used when a seting is updated before the first request is going */ 01962 p_info_ch->restart_ramp_flag = false; 01963 01964 if (0 == was_masked) 01965 { 01966 __enable_irq(); 01967 } 01968 } 01969 } 01970 01971 return retval; 01972 } 01973 01974 /****************************************************************************** 01975 End of function SCUX_IoctlSetDvuRampVol 01976 ******************************************************************************/ 01977 01978 /**************************************************************************//** 01979 * Function Name: SCUX_IoctlSetDvuZerocrossMute 01980 * @brief Set zerocross mute parameter. 01981 * 01982 * Description:<br> 01983 * 01984 * @param[in] channel:SCUX channel number. 01985 * @param[in] *p_zc_mute_param:zerocross mute parameter. 01986 * @retval ESUCCESS:Operation successful. 01987 * EPERM:Parameter is unexpected value. 01988 * EPERM:Rewrite callback pointer while waiting zerocross. 01989 ******************************************************************************/ 01990 01991 int_t SCUX_IoctlSetDvuZerocrossMute(const int_t channel, const scux_zc_mute_t * const p_zc_mute_param) 01992 { 01993 int_t retval = ESUCCESS; 01994 int_t was_masked; 01995 scux_audio_channel_t audio_ch; 01996 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 01997 01998 if ((NULL == p_info_ch) || (NULL == p_zc_mute_param)) 01999 { 02000 retval = EFAULT; 02001 } 02002 else 02003 { 02004 /* set zerocross mute paramter */ 02005 for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++) 02006 { 02007 p_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch]= p_zc_mute_param->zc_mute_enable[audio_ch]; 02008 p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[audio_ch] = p_zc_mute_param->pcallback[audio_ch]; 02009 } 02010 02011 #if defined (__ICCARM__) 02012 was_masked = __disable_irq_iar(); 02013 #else 02014 was_masked = __disable_irq(); 02015 #endif 02016 02017 if (SCUX_CH_STOP != p_info_ch->ch_stat) 02018 { 02019 p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET; 02020 02021 /* set parameter for register */ 02022 SCUX_SetZerocrossMuteRegister(p_info_ch); 02023 02024 p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET; 02025 } 02026 02027 if (0 == was_masked) 02028 { 02029 __enable_irq(); 02030 } 02031 } 02032 02033 return retval; 02034 } 02035 02036 /****************************************************************************** 02037 End of function SCUX_IoctlSetDvuZerocrossMute 02038 ******************************************************************************/ 02039 02040 /**************************************************************************//** 02041 * Function Name: SCUX_IoctlSetStopMute 02042 * @brief Stop mute. 02043 * 02044 * Description:<br> 02045 * 02046 * @param[in] channel:SCUX channel number. 02047 * @param[in] audio_channel:Audio channel number. 02048 * @retval ESUCCESS:Operation successful. 02049 * EPERM:Parameter is unexpected value. 02050 * EFAULT : Internal error is occured. 02051 ******************************************************************************/ 02052 02053 int_t SCUX_IoctlSetStopMute(const int_t channel, const uint32_t audio_channel) 02054 { 02055 int_t retval = ESUCCESS; 02056 int_t was_masked; 02057 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 02058 02059 if (NULL == p_info_ch) 02060 { 02061 retval = EFAULT; 02062 } 02063 else 02064 { 02065 if (audio_channel >= (uint32_t)p_info_ch->src_cfg.use_ch) 02066 { 02067 retval = EPERM; 02068 } 02069 02070 if (ESUCCESS == retval) 02071 { 02072 #if defined (__ICCARM__) 02073 was_masked = __disable_irq_iar(); 02074 #else 02075 was_masked = __disable_irq(); 02076 #endif 02077 02078 p_info_ch->dvu_mute_stat &= ~(1U << audio_channel); 02079 p_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_channel] = false; 02080 p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET; 02081 p_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 &= ~(ZCMCR_DVU0_ZCEN_SET << audio_channel); 02082 p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET; 02083 02084 if (0 == was_masked) 02085 { 02086 __enable_irq(); 02087 } 02088 } 02089 } 02090 02091 return retval; 02092 } 02093 02094 /****************************************************************************** 02095 End of function SCUX_IoctlSetStopMute 02096 ******************************************************************************/ 02097 02098 /**************************************************************************//** 02099 * Function Name: SCUX_IoctlSetMixCfg 02100 * @brief Set MIX parameter. 02101 * 02102 * Description:<br> 02103 * 02104 * @param[in] *p_mix_param:MIX parameter. 02105 * @retval ESUCCESS : Operation successful. 02106 * EPERM : Transfer parameter is unexpected. 02107 * EFAULT : Internal error is occured. 02108 ******************************************************************************/ 02109 02110 int_t SCUX_IoctlSetMixCfg(const scux_mix_cfg_t * const p_mix_param) 02111 { 02112 int_t retval = ESUCCESS; 02113 int_t scux_ch; 02114 int_t audio_ch; 02115 int_t was_masked; 02116 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 02117 02118 if ((NULL == p_info_drv) || (NULL == p_mix_param)) 02119 { 02120 retval = EFAULT; 02121 } 02122 else 02123 { 02124 #if defined (__ICCARM__) 02125 was_masked = __disable_irq_iar(); 02126 #else 02127 was_masked = __disable_irq(); 02128 #endif 02129 02130 p_info_drv->shared_info.mixmode_ramp = p_mix_param->mixmode_ramp; 02131 p_info_drv->shared_info.up_period = p_mix_param->up_period; 02132 p_info_drv->shared_info.down_period = p_mix_param->down_period; 02133 for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++) 02134 { 02135 p_info_drv->shared_info.mix_vol[scux_ch] = p_mix_param->mix_vol[scux_ch]; 02136 } 02137 for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++) 02138 { 02139 p_info_drv->shared_info.select_out_data_ch[audio_ch] = p_mix_param->select_out_data_ch[audio_ch]; 02140 } 02141 02142 for (scux_ch = SCUX_CH_0; ((ESUCCESS == retval) && (scux_ch < SCUX_CH_NUM)); scux_ch++) 02143 { 02144 /* check going channel number */ 02145 if (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch))) 02146 { 02147 /* check ramp volume */ 02148 if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[scux_ch]) 02149 { 02150 retval = EPERM; 02151 } 02152 } 02153 } 02154 02155 if (ESUCCESS == retval) 02156 { 02157 for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++) 02158 { 02159 /* check going channel number */ 02160 if (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch))) 02161 { 02162 /* set parameter for register */ 02163 SCUX_SetMixVolRegister(scux_ch); 02164 } 02165 } 02166 02167 p_info_drv->shared_info.mix_setup = true; 02168 } 02169 else 02170 { 02171 p_info_drv->shared_info.mix_setup = false; 02172 } 02173 02174 if (0 == was_masked) 02175 { 02176 __enable_irq(); 02177 } 02178 } 02179 02180 return retval; 02181 } 02182 02183 /****************************************************************************** 02184 End of function SCUX_IoctlSetMixCfg 02185 ******************************************************************************/ 02186 02187 /**************************************************************************//** 02188 * Function Name: SCUX_IoctlSetMixVol 02189 * @brief Set MIX volume. 02190 * 02191 * Description:<br> 02192 * 02193 * @param[in] channel:SCUX channel number. 02194 * @param[in] mix_vol:MIX volume. 02195 * @retval ESUCCESS : Operation successful. 02196 * EPERM : Transfer parameter is unexpected. 02197 * EFAULT: Internel error si occured. 02198 ******************************************************************************/ 02199 02200 int_t SCUX_IoctlSetMixVol(const int_t channel, const uint32_t mix_vol) 02201 { 02202 int_t retval = ESUCCESS; 02203 int_t was_masked; 02204 int32_t sem_wait_ercd; 02205 osStatus sem_ercd; 02206 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 02207 02208 if (NULL == p_info_drv) 02209 { 02210 retval = EFAULT; 02211 } 02212 else 02213 { 02214 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 02215 if (0 == R_ExceptionalMode()) 02216 { 02217 sem_wait_ercd = osSemaphoreWait(p_info_drv->shared_info.sem_shared_access, osWaitForever); 02218 /* <-MISRA 10.6 */ 02219 /* semaphore error check */ 02220 if ((-1) == sem_wait_ercd) 02221 { 02222 /* set semaphore error */ 02223 retval = EFAULT; 02224 } 02225 } 02226 02227 if (ESUCCESS == retval) 02228 { 02229 p_info_drv->shared_info.mix_vol[channel] = mix_vol; 02230 02231 #if defined (__ICCARM__) 02232 was_masked = __disable_irq_iar(); 02233 #else 02234 was_masked = __disable_irq(); 02235 #endif 02236 02237 /* check going channel number */ 02238 if (0U != (p_info_drv->shared_info.mix_run_ch & (1U << channel))) 02239 { 02240 /* check ramp volume */ 02241 if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[channel]) 02242 { 02243 retval = EPERM; 02244 } 02245 else 02246 { 02247 /* set parameter for register */ 02248 SCUX_SetMixVolRegister(channel); 02249 } 02250 } 02251 02252 if (0 == was_masked) 02253 { 02254 __enable_irq(); 02255 } 02256 } 02257 02258 if (0 == R_ExceptionalMode()) 02259 { 02260 sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access); 02261 /* semaphore error check */ 02262 if (osOK != sem_ercd) 02263 { 02264 /* set semaphore error */ 02265 retval = EFAULT; 02266 } 02267 } 02268 } 02269 02270 return retval; 02271 } 02272 02273 /****************************************************************************** 02274 End of function SCUX_IoctlSetMixVol 02275 ******************************************************************************/ 02276 02277 /**************************************************************************//** 02278 * Function Name: SCUX_IoctlSetSsifCfg 02279 * @brief Set SSIF parameter. 02280 * 02281 * Description:<br> 02282 * 02283 * @param[in] channel:SCUX channel number. 02284 * @param[in] p_ssif_param:SSIF parameter. 02285 * @retval ESUCCESS : Operation successful. 02286 * EBADF : SSIF channel has already used on other SCUX channel. 02287 * EPERM : Transfer parameter is unexpected. 02288 * EFAULT: Internel error is occured. 02289 ******************************************************************************/ 02290 02291 int_t SCUX_IoctlSetSsifCfg(const scux_ssif_cfg_t * const p_ssif_param) 02292 { 02293 int_t retval = ESUCCESS; 02294 int32_t sem_wait_ercd; 02295 osStatus sem_ercd; 02296 scux_ssif_info_t * p_ssif_ch; 02297 02298 if (NULL == p_ssif_param) 02299 { 02300 retval = EFAULT; 02301 } 02302 else 02303 { 02304 if (SCUX_SSIF_CH_NUM > p_ssif_param->ssif_ch_num) 02305 { 02306 p_ssif_ch = SCUX_GetSsifChInfo((int_t)p_ssif_param->ssif_ch_num); 02307 if (NULL == p_ssif_ch) 02308 { 02309 retval = EFAULT; 02310 } 02311 else 02312 { 02313 /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 02314 sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever); 02315 /* <-MISRA 10.6 */ 02316 /* semaphore error check */ 02317 if ((-1) == sem_wait_ercd) 02318 { 02319 /* set semaphore error */ 02320 retval = EFAULT; 02321 } 02322 else 02323 { 02324 if (0 != p_ssif_ch->scux_channel) 02325 { 02326 retval = EBADF; 02327 } 02328 else 02329 { 02330 p_ssif_ch->ssif_cfg.ssif_ch_num = p_ssif_param->ssif_ch_num; 02331 p_ssif_ch->ssif_cfg.mode_master = p_ssif_param->mode_master; 02332 p_ssif_ch->ssif_cfg.select_audio_clk = p_ssif_param->select_audio_clk; 02333 p_ssif_ch->ssif_cfg.system_word = p_ssif_param->system_word; 02334 p_ssif_ch->ssif_cfg.sck_polarity_rise = p_ssif_param->sck_polarity_rise; 02335 p_ssif_ch->ssif_cfg.ws_polarity_high = p_ssif_param->ws_polarity_high; 02336 p_ssif_ch->ssif_cfg.padding_high = p_ssif_param->padding_high; 02337 p_ssif_ch->ssif_cfg.serial_data_align = p_ssif_param->serial_data_align; 02338 p_ssif_ch->ssif_cfg.ws_delay = p_ssif_param->ws_delay; 02339 p_ssif_ch->ssif_cfg.use_noise_cancel = p_ssif_param->use_noise_cancel; 02340 p_ssif_ch->ssif_cfg.use_tdm = p_ssif_param->use_tdm; 02341 p_ssif_ch->ssif_setup = true; 02342 } 02343 } 02344 02345 sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access); 02346 /* semaphore error check */ 02347 if (osOK != sem_ercd) 02348 { 02349 /* set semaphore error */ 02350 retval = EFAULT; 02351 } 02352 } 02353 } 02354 else 02355 { 02356 retval = EPERM; 02357 } 02358 } 02359 02360 return retval; 02361 } 02362 02363 /****************************************************************************** 02364 End of function SCUX_IoctlSetMixVol 02365 ******************************************************************************/ 02366 02367 /**************************************************************************//** 02368 * Function Name: SCUX_IoctlGetWriteStat 02369 * @brief Get write request status. 02370 * 02371 * Description:<br> 02372 * 02373 * @param[in] channel:SCUX channel number. 02374 * @param[in] *p_write_stat:Write request status. 02375 * @retval None. 02376 ******************************************************************************/ 02377 02378 void SCUX_IoctlGetWriteStat(const int_t channel, uint32_t * const p_write_stat) 02379 { 02380 int_t was_masked; 02381 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 02382 02383 if ((NULL == p_info_ch) || (NULL == p_write_stat)) 02384 { 02385 /* NON_NOTICE_ASSERT: NULL pointer */ 02386 } 02387 else 02388 { 02389 #if defined (__ICCARM__) 02390 was_masked = __disable_irq_iar(); 02391 #else 02392 was_masked = __disable_irq(); 02393 #endif 02394 02395 if ((SCUX_CH_STOP == p_info_ch->ch_stat) || 02396 (SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) || 02397 (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat)) 02398 { 02399 *p_write_stat = SCUX_STAT_STOP; 02400 } 02401 else if ((SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) || (SCUX_CH_TRANS_RD == p_info_ch->ch_stat)) 02402 { 02403 *p_write_stat = SCUX_STAT_IDLE; 02404 } 02405 else 02406 { 02407 *p_write_stat = SCUX_STAT_TRANS; 02408 } 02409 02410 if (0 == was_masked) 02411 { 02412 __enable_irq(); 02413 } 02414 } 02415 02416 return; 02417 } 02418 02419 /****************************************************************************** 02420 End of function SCUX_IoctlGetWriteStat 02421 ******************************************************************************/ 02422 02423 /**************************************************************************//** 02424 * Function Name: SCUX_IoctlGetReadStat 02425 * @brief Get read request status. 02426 * 02427 * Description:<br> 02428 * 02429 * @param[in] channel:SCUX channel number. 02430 * @param[in] *p_read_stat:Read request status. 02431 * @retval None. 02432 ******************************************************************************/ 02433 02434 void SCUX_IoctlGetReadStat(const int_t channel, uint32_t * const p_read_stat) 02435 { 02436 int_t was_masked; 02437 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 02438 02439 #if defined (__ICCARM__) 02440 was_masked = __disable_irq_iar(); 02441 #else 02442 was_masked = __disable_irq(); 02443 #endif 02444 02445 if ((NULL == p_info_ch) || (NULL == p_read_stat)) 02446 { 02447 /* NON_NOTICE_ASSERT: NULL pointer */ 02448 } 02449 else 02450 { 02451 if (SCUX_CH_STOP == p_info_ch->ch_stat) 02452 { 02453 *p_read_stat = SCUX_STAT_STOP; 02454 } 02455 else if ((SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) || 02456 (SCUX_CH_TRANS_WR == p_info_ch->ch_stat) || 02457 (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat)) 02458 { 02459 *p_read_stat = SCUX_STAT_IDLE; 02460 } 02461 else 02462 { 02463 *p_read_stat = SCUX_STAT_TRANS; 02464 } 02465 02466 if (0 == was_masked) 02467 { 02468 __enable_irq(); 02469 } 02470 } 02471 02472 return; 02473 } 02474 02475 /****************************************************************************** 02476 End of function SCUX_IoctlGetReadStat 02477 ******************************************************************************/ 02478 02479 /**************************************************************************//** 02480 * Function Name: SCUX_IoctlGetDvuStat 02481 * @brief Get DVU status. 02482 * 02483 * Description:<br> 02484 * 02485 * @param[in] channel:SCUX channel number. 02486 * @param[in] *p_dvu_stat:DVU status. 02487 * @retval None. 02488 ******************************************************************************/ 02489 02490 void SCUX_IoctlGetDvuStat(const int_t channel, uint32_t * const p_dvu_stat) 02491 { 02492 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 02493 02494 if ((NULL == p_info_ch) || (NULL == p_dvu_stat)) 02495 { 02496 /* NON_NOTICE_ASSERT: NULL pointer */ 02497 } 02498 else 02499 { 02500 *p_dvu_stat = (p_info_ch->p_scux_reg->p_dvu_reg->DVUSR_DVU0_0 & DVUSR_DVU0_VRSTS_MASK); 02501 } 02502 02503 return; 02504 } 02505 02506 /****************************************************************************** 02507 End of function SCUX_IoctlGetDvuStat 02508 ******************************************************************************/ 02509 02510 /**************************************************************************//** 02511 * Function Name: SCUX_IoctlGetMuteStat 02512 * @brief Get MUTE status. 02513 * 02514 * Description:<br> 02515 * 02516 * @param[in] channel:SCUX channel number. 02517 * @param[in] *p_mute_stat:MUTE status. 02518 * @retval None. 02519 ******************************************************************************/ 02520 02521 void SCUX_IoctlGetMuteStat(const int_t channel, uint32_t * const p_mute_stat) 02522 { 02523 int_t was_masked; 02524 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 02525 02526 if ((NULL == p_info_ch) || (NULL == p_mute_stat)) 02527 { 02528 /* NON_NOTICE_ASSERT: NULL pointer */ 02529 } 02530 else 02531 { 02532 #if defined (__ICCARM__) 02533 was_masked = __disable_irq_iar(); 02534 #else 02535 was_masked = __disable_irq(); 02536 #endif 02537 02538 *p_mute_stat = p_info_ch->dvu_mute_stat; 02539 02540 if (0 == was_masked) 02541 { 02542 __enable_irq(); 02543 } 02544 } 02545 02546 return; 02547 } 02548 02549 /****************************************************************************** 02550 End of function SCUX_IoctlGetMuteStat 02551 ******************************************************************************/ 02552 02553 /**************************************************************************//** 02554 * Function Name: SCUX_IoctlGetMixStat 02555 * @brief Get MIX status. 02556 * 02557 * Description:<br> 02558 * 02559 * @param[in] channel:SCUX channel number. 02560 * @param[in] *p_mix_stat:MIX status. 02561 * @retval None. 02562 ******************************************************************************/ 02563 02564 void SCUX_IoctlGetMixStat(const int_t channel, uint32_t * const p_mix_stat) 02565 { 02566 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel); 02567 02568 if ((NULL == p_info_ch) || (NULL == p_mix_stat)) 02569 { 02570 /* NON_NOTICE_ASSERT: NULL pointer */ 02571 } 02572 else 02573 { 02574 *p_mix_stat = (*(p_info_ch->p_scux_reg->mixsr_mix0_0) & MIXSR_MIX0_MIXSTS_MASK); 02575 } 02576 02577 return; 02578 } 02579 02580 /****************************************************************************** 02581 End of function SCUX_IoctlGetMixStat 02582 ******************************************************************************/ 02583
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