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scux_if.h

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00001 /*******************************************************************************
00002 * DISCLAIMER
00003 * This software is supplied by Renesas Electronics Corporation and is only
00004 * intended for use with Renesas products. No other uses are authorized. This
00005 * software is owned by Renesas Electronics Corporation and is protected under
00006 * all applicable laws, including copyright laws.
00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
00016 * Renesas reserves the right, without notice, to make changes to this software
00017 * and to discontinue the availability of this software. By using this software,
00018 * you agree to the additional terms and conditions found by accessing the
00019 * following link:
00020 * http://www.renesas.com/disclaimer
00021 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
00022 *******************************************************************************/
00023 /**************************************************************************//**
00024 * @file          scux_if.h
00025 * $Rev: 1032 $
00026 * $Date:: 2014-08-06 09:04:50 +0900#$
00027 * @brief         SCUX Driver IOIF API header
00028 ******************************************************************************/
00029 
00030 #ifndef SCUX_IF_H
00031 #define SCUX_IF_H
00032 
00033 /******************************************************************************
00034 Includes <System Includes> , "Project Includes"
00035 ******************************************************************************/
00036 
00037 #include "cmsis_os.h"
00038 #include "r_errno.h"
00039 #include "r_typedefs.h"
00040 #if(1) /* mbed */
00041 #include "ioif_aio.h"
00042 #include "misratypes.h"
00043 #include "R_BSP_mbed_fns.h"
00044 #include "R_BSP_ScuxDef.h"
00045 #else  /* not mbed */
00046 #include "ioif_public.h"
00047 #endif /* end mbed */
00048 
00049 #ifdef __cplusplus
00050 extern "C"
00051 {
00052 #endif /* __cplusplus */
00053 
00054 /*************************************************************************
00055  Enumerated Types
00056 *************************************************************************/
00057 
00058 #if(1) /* mbed */
00059 #else  /* not mbed */
00060 /* Number of SCUX channel */
00061 typedef enum
00062 {
00063     SCUX_CH_0 = 0,
00064     SCUX_CH_1 = 1,
00065     SCUX_CH_2 = 2,
00066     SCUX_CH_3 = 3,
00067     SCUX_CH_NUM = 4  /* Number of SCUX channel */
00068 } scux_ch_num_t;
00069 #endif /* end mbed */
00070 
00071 /* SCUX route setting */
00072 typedef enum
00073 {
00074     /* mem to mem */
00075     SCUX_ROUTE_SRC_MEM_MIN = 0x1000,
00076     SCUX_ROUTE_SRC0_MEM    = 0x1001,
00077     SCUX_ROUTE_SRC1_MEM    = 0x1002,
00078     SCUX_ROUTE_SRC2_MEM    = 0x1003,
00079     SCUX_ROUTE_SRC3_MEM    = 0x1004,
00080     SCUX_ROUTE_SRC_MEM_MAX = 0x1005,
00081     /* mem to SSIF */
00082     SCUX_ROUTE_SRC_SSIF_MIN = 0x2000,
00083     SCUX_ROUTE_SRC0_SSIF0   = 0x2001,
00084     SCUX_ROUTE_SRC0_SSIF012 = 0x2002,
00085     SCUX_ROUTE_SRC0_SSIF3   = 0x2003,
00086     SCUX_ROUTE_SRC0_SSIF345 = 0x2004,
00087     SCUX_ROUTE_SRC1_SSIF0   = 0x2005,
00088     SCUX_ROUTE_SRC1_SSIF012 = 0x2006,
00089     SCUX_ROUTE_SRC1_SSIF3   = 0x2007,
00090     SCUX_ROUTE_SRC1_SSIF345 = 0x2008,    
00091     SCUX_ROUTE_SRC2_SSIF1   = 0x2009,
00092     SCUX_ROUTE_SRC2_SSIF4   = 0x200A,
00093     SCUX_ROUTE_SRC3_SSIF2   = 0x200B,
00094     SCUX_ROUTE_SRC3_SSIF5   = 0x200C,
00095     SCUX_ROUTE_SRC_SSIF_MAX = 0x200D,
00096     /* mem to NIX to SSIF */
00097     SCUX_ROUTE_SRC_MIX_SSIF_MIN  = 0x3000,
00098     SCUX_ROUTE_SRC0_MIX_SSIF0   = 0x3001,
00099     SCUX_ROUTE_SRC0_MIX_SSIF012 = 0x3002,
00100     SCUX_ROUTE_SRC0_MIX_SSIF3   = 0x3003,
00101     SCUX_ROUTE_SRC0_MIX_SSIF345 = 0x3004,
00102     SCUX_ROUTE_SRC1_MIX_SSIF0   = 0x3005,
00103     SCUX_ROUTE_SRC1_MIX_SSIF012 = 0x3006,
00104     SCUX_ROUTE_SRC1_MIX_SSIF3   = 0x3007,
00105     SCUX_ROUTE_SRC1_MIX_SSIF345 = 0x3008,   
00106     SCUX_ROUTE_SRC2_MIX_SSIF0   = 0x3009,
00107     SCUX_ROUTE_SRC2_MIX_SSIF012 = 0x300A,
00108     SCUX_ROUTE_SRC2_MIX_SSIF3   = 0x300B,
00109     SCUX_ROUTE_SRC2_MIX_SSIF345 = 0x300C,
00110     SCUX_ROUTE_SRC3_MIX_SSIF0   = 0x300D,
00111     SCUX_ROUTE_SRC3_MIX_SSIF012 = 0x300E,
00112     SCUX_ROUTE_SRC3_MIX_SSIF3   = 0x300F,
00113     SCUX_ROUTE_SRC3_MIX_SSIF345 = 0x3010,   
00114     SCUX_ROUTE_SRC_MIX_SSIF_MAX = 0x3011
00115 } scux_route_t;
00116 
00117 #if(1) /* mbed */
00118 #else  /* not mbed */
00119 /* used audio channel number setting */
00120 typedef enum
00121 {
00122     SCUX_USE_CH_1 = 1,   /* used audio channel number is 1 */
00123     SCUX_USE_CH_2 = 2,   /* used audio channel number is 2 */
00124     SCUX_USE_CH_4 = 4,   /* used audio channel number is 4 */
00125     SCUX_USE_CH_6 = 6,   /* used audio channel number is 6 */
00126     SCUX_USE_CH_8 = 8    /* used audio channel number is 8 */
00127 } scux_use_channel_t;
00128 #endif /* end mbed */
00129 
00130 /* select audio channel number setting */
00131 typedef enum
00132 {
00133     SCUX_AUDIO_CH_MIN = -1,
00134     SCUX_AUDIO_CH_0 = 0,   /* select audio channel number is 0 */
00135     SCUX_AUDIO_CH_1 = 1,   /* select audio channel number is 1 */
00136     SCUX_AUDIO_CH_2 = 2,   /* select audio channel number is 2 */
00137     SCUX_AUDIO_CH_3 = 3,   /* select audio channel number is 3 */
00138     SCUX_AUDIO_CH_4 = 4,   /* select audio channel number is 4 */
00139     SCUX_AUDIO_CH_5 = 5,   /* select audio channel number is 5 */
00140     SCUX_AUDIO_CH_6 = 6,   /* select audio channel number is 6 */
00141     SCUX_AUDIO_CH_7 = 7,   /* select audio channel number is 7 */
00142     SCUX_AUDIO_CH_MAX = 8
00143 } scux_audio_channel_t;
00144 
00145 #if(1) /* mbed */
00146 #else  /* not mbed */
00147 /* SCUX data word length */
00148 typedef enum
00149 {
00150     SCUX_DATA_LEN_MIN      =(-1),
00151     SCUX_DATA_LEN_24       = 0,   /* data word length is 24bit */
00152     SCUX_DATA_LEN_16       = 1,   /* data word length is 16bit */
00153     SCUX_DATA_LEN_16_TO_24 = 2,   /* data word length is 24bit */
00154     SCUX_DATA_LEN_MAX      = 3
00155 } scux_data_word_len_t;
00156 #endif /* end mbed */
00157 
00158 /* SSIF PIN mode setting */
00159 typedef enum
00160 {
00161     SCUX_PIN_MODE_MIN          =(-1),
00162     SCUX_PIN_MODE_INDEPEND     = 0,   /* PIN mode is independent */
00163     SCUX_PIN_MODE_SLAVE_SLAVE  = 1,   /* PIN mode is slave-slave */
00164     SCUX_PIN_MODE_MASTER_SLAVE = 2,   /* PIN mode is master-slave */
00165     SCUX_PIN_MODE_MAX = 3
00166 } scux_pin_mode_t;
00167 
00168 /* SCUX sampling rate */
00169 typedef enum
00170 {
00171     SCUX_SYNC_RATE_8      = 8000,    /* 8KHz */
00172     SCUX_SYNC_RATE_11_025 = 11025,   /* 11.025KHz */
00173     SCUX_SYNC_RATE_12     = 12000,   /* 12KHz */
00174     SCUX_SYNC_RATE_16     = 16000,   /* 16KHz */
00175     SCUX_SYNC_RATE_22_05  = 22050,   /* 22.05KHz */
00176     SCUX_SYNC_RATE_24     = 24000,   /* 24KHz */
00177     SCUX_SYNC_RATE_32     = 32000,   /* 32KHz */
00178     SCUX_SYNC_RATE_44_1   = 44100,   /* 44.1KHz */
00179     SCUX_SYNC_RATE_48     = 48000,   /* 48KHz */
00180     SCUX_SYNC_RATE_64     = 64000,   /* 64KHz */
00181     SCUX_SYNC_RATE_88_2   = 88200,   /* 88.2KHz */
00182     SCUX_SYNC_RATE_96     = 96000    /* 96KHz */
00183 } scux_src_sync_rate_t;
00184 
00185 /* SCUX clock source setting */
00186 typedef enum
00187 {
00188     SCUX_CLK_MIN  =(-1),
00189     SCUX_CLK_AUDIO_CLK  = 0,   /* clock source is AUDIO_CLK */
00190     SCUX_CLK_AUDIO_X1   = 1,   /* clock source is AUDIO_X1 */
00191     SCUX_CLK_MLB_CLK    = 2,   /* clock source is MLB_CLK */
00192     SCUX_CLK_USB_X1     = 3,   /* clock source is USB_X1 */
00193     SCUX_CLK_CLKP1_2    = 4,   /* clock source is surrounding clock */
00194     SCUX_CLK_MTU_TIOC3A = 5,   /* clock source is TIOC3A */
00195     SCUX_CLK_MTU_TIOC4A = 6,   /* clock source is TIOC4A */
00196     SCUX_CLK_SSIF0_WS   = 8,   /* clock source is SSIF0 WS */
00197     SCUX_CLK_SSIF1_WS   = 9,   /* clock source is SSIF1 WS */
00198     SCUX_CLK_SSIF2_WS   = 10,   /* clock source is SSIF2 WS */
00199     SCUX_CLK_SSIF3_WS   = 11,  /* clock source is SSIF3 WS */
00200     SCUX_CLK_SSIF4_WS   = 12,  /* clock source is SSIF4 WS */
00201     SCUX_CLK_SSIF5_WS   = 13,  /* clock source is SSIF5 WS */
00202     SCUX_CLK_MAX        = 14
00203 } scux_src_clk_source_t;
00204 
00205 /* SCUX delay mode setting */
00206 typedef enum
00207 {
00208     SCUX_DELAY_MIN         =(-1),  
00209     SCUX_DELAY_NORMAL      = 0,    /* Delay mode is normal */
00210     SCUX_DELAY_LOW_DELAY1  = 1,    /* Delay mode is Low Delay1 */
00211     SCUX_DELAY_LOW_DELAY2  = 2,    /* Delay mode is Low Delay2 */
00212     SCUX_DELAY_MAX         = 3     
00213 } scux_src_delay_mode_t;
00214 
00215 /* DVU ramp time setting */
00216 typedef enum
00217 {
00218     SCUX_DVU_TIME_MIN  =(-1),
00219     SCUX_DVU_TIME_128DB_1STEP      = 0,   /* volume change 128DB among 1 step */
00220     SCUX_DVU_TIME_64DB_1STEP       = 1,   /* volume change 64DB among 1 step */
00221     SCUX_DVU_TIME_32DB_1STEP       = 2,   /* volume change 32DB among 1 step */
00222     SCUX_DVU_TIME_16DB_1STEP       = 3,   /* volume change 16DB among 1 step */
00223     SCUX_DVU_TIME_8DB_1STEP        = 4,   /* volume change 8DB among 1 step */
00224     SCUX_DVU_TIME_4DB_1STEP        = 5,   /* volume change 4DB among 1 step */
00225     SCUX_DVU_TIME_2DB_1STEP        = 6,   /* volume change 2DB among 1 step */
00226     SCUX_DVU_TIME_1DB_1STEP        = 7,   /* volume change 1DB among 1 step */
00227     SCUX_DVU_TIME_0_5DB_1STEP      = 8,   /* volume change 0.5DB among 1 step */
00228     SCUX_DVU_TIME_0_25DB_1STEP     = 9,   /* volume change 0.25DB among 1 step */
00229     SCUX_DVU_TIME_0_125DB_1STEP    = 10,  /* volume change 0.125DB among 1 step */
00230     SCUX_DVU_TIME_0_125DB_2STEP    = 11,  /* volume change 0.125DB among 2 step */
00231     SCUX_DVU_TIME_0_125DB_4STEP    = 12,  /* volume change 0.125DB among 4 step */
00232     SCUX_DVU_TIME_0_125DB_8STEP    = 13,  /* volume change 0.125DB among 8 step */
00233     SCUX_DVU_TIME_0_125DB_16STEP   = 14,  /* volume change 0.125DB among 16 step */
00234     SCUX_DVU_TIME_0_125DB_32STEP   = 15,  /* volume change 0.125DB among 32 step */
00235     SCUX_DVU_TIME_0_125DB_64STEP   = 16,  /* volume change 0.125DB among 64 step */
00236     SCUX_DVU_TIME_0_125DB_128STEP  = 17,  /* volume change 0.125DB among 128 step */
00237     SCUX_DVU_TIME_0_125DB_256STEP  = 18,  /* volume change 0.125DB among 256 step */
00238     SCUX_DVU_TIME_0_125DB_512STEP  = 19,  /* volume change 0.125DB among 512 step */
00239     SCUX_DVU_TIME_0_125DB_1024STEP = 20,  /* volume change 0.125DB among 1024 step */
00240     SCUX_DVU_TIME_0_125DB_2048STEP = 21,  /* volume change 0.125DB among 2048 step */
00241     SCUX_DVU_TIME_0_125DB_4096STEP = 22,  /* volume change 0.125DB among 4096 step */
00242     SCUX_DVU_TIME_0_125DB_8192STEP = 23,  /* volume change 0.125DB among 8192 step */
00243     SCUX_DVU_TIME_MAX              = 24   
00244 } scux_dvu_ramp_time_t;
00245 
00246 /* MIX ramp time setting */
00247 typedef enum
00248 {
00249     SCUX_MIX_TIME_MIN            =(-1),  
00250     SCUX_MIX_TIME_128DB_1STEP    = 0,    /* volume change 128DB among 1 step */
00251     SCUX_MIX_TIME_64DB_1STEP     = 1,    /* volume change 64DB among 1 step */
00252     SCUX_MIX_TIME_32DB_1STEP     = 2,    /* volume change 32DB among 1 step */
00253     SCUX_MIX_TIME_16DB_1STEP     = 3,    /* volume change 16DB among 1 step */
00254     SCUX_MIX_TIME_8DB_1STEP      = 4,    /* volume change 8DB among 1 step */
00255     SCUX_MIX_TIME_4DB_1STEP      = 5,    /* volume change 4DB among 1 step */
00256     SCUX_MIX_TIME_2DB_1STEP      = 6,    /* volume change 2DB among 1 step */
00257     SCUX_MIX_TIME_1DB_1STEP      = 7,    /* volume change 1DB among 1 step */
00258     SCUX_MIX_TIME_0_5DB_1STEP    = 8,    /* volume change 0.5DB among 1 step */
00259     SCUX_MIX_TIME_0_25DB_1STEP   = 9,    /* volume change 0.25DB among 1 step */
00260     SCUX_MIX_TIME_0_125DB_1STEP  = 10,   /* volume change 0.125DB among 1 step */
00261     SCUX_MIX_TIME_MAX            = 11     
00262 } scux_mix_ramp_time_t;
00263 
00264 /* SSIF channels */
00265 typedef enum
00266 {
00267     SCUX_SSIF_CH_0    = 0,    /* volume change 128DB among 1 step */
00268     SCUX_SSIF_CH_1    = 1,    /* volume change 64DB among 1 step */
00269     SCUX_SSIF_CH_2    = 2,    /* volume change 32DB among 1 step */
00270     SCUX_SSIF_CH_3    = 3,    /* volume change 16DB among 1 step */
00271     SCUX_SSIF_CH_4    = 4,    /* volume change 8DB among 1 step */
00272     SCUX_SSIF_CH_5    = 5,    /* volume change 4DB among 1 step */
00273     SCUX_SSIF_CH_NUM  = 6
00274 } scux_ssif_ch_num_t;
00275 
00276 /* SSIF channels */
00277 typedef enum
00278 {
00279     SCUX_SSIF_SYSTEM_LEN_MIN   = 0,    
00280     SCUX_SSIF_SYSTEM_LEN_16    = 1,    /* SSIF system word length is 16bit */
00281     SCUX_SSIF_SYSTEM_LEN_24    = 2,    /* SSIF system word length is 24bit */
00282     SCUX_SSIF_SYSTEM_LEN_32    = 3,    /* SSIF system word length is 32bit */
00283     SCUX_SSIF_SYSTEM_LEN_48    = 4,    /* SSIF system word length is 48bit */
00284     SCUX_SSIF_SYSTEM_LEN_64    = 5,    /* SSIF system word length is 64bit */
00285     SCUX_SSIF_SYSTEM_LEN_128   = 6,    /* SSIF system word length is 128bit */
00286     SCUX_SSIF_SYSTEM_LEN_256   = 7,    /* SSIF system word length is 256bit */
00287     SCUX_SSIF_SYSTEM_LEN_MAX   = 8
00288 } scux_ssif_system_len_t;
00289 
00290 /******************************************************************************
00291 Macro definitions
00292 ******************************************************************************/
00293 
00294 /* SCUX IOCTL function code */
00295 #define SCUX_IOCTL_MIN                 (-1)
00296 #define SCUX_IOCTL_SET_START           0   /* start transfer */
00297 #define SCUX_IOCTL_SET_FLUSH_STOP      1   /* set flush stop function */
00298 #define SCUX_IOCTL_SET_CLEAR_STOP      2   /* set clear stop function */
00299 #define SCUX_IOCTL_SET_ROUTE           3   /* set route parameter */
00300 #define SCUX_IOCTL_SET_PIN_CLK         4   /* set pin clock parameter */
00301 #define SCUX_IOCTL_SET_PIN_MODE        5   /* set pin mode parameter */
00302 #define SCUX_IOCTL_SET_SRC_CFG         6   /* set SRC parameter */
00303 #define SCUX_IOCTL_SET_DVU_CFG         7   /* set DVU parameter */
00304 #define SCUX_IOCTL_SET_DVU_DIGI_VOL    8   /* set dgital volume parameter */
00305 #define SCUX_IOCTL_SET_DVU_RAMP_VOL    9   /* set ramp volume parameter */
00306 #define SCUX_IOCTL_SET_ZEROCROSS_MUTE  10  /* set zerocross mute paramter */
00307 #define SCUX_IOCTL_SET_STOP_MUTE       11  /* set mute stop */
00308 #define SCUX_IOCTL_SET_MIX_CFG         12  /* set MIX parameter */
00309 #define SCUX_IOCTL_SET_MIX_VOL         13  /* set MIX volume parameter */
00310 #define SCUX_IOCTL_SET_SSIF_CFG        14  /* set SSIF parameter */
00311 #define SCUX_IOCTL_GET_WRITE_STAT      15  /* get write status */
00312 #define SCUX_IOCTL_GET_READ_STAT       16  /* get read status */
00313 #define SCUX_IOCTL_GET_DVU_STAT        17  /* get DVU status */
00314 #define SCUX_IOCTL_GET_MUTE_STAT       18  /* get MUTE status */
00315 #define SCUX_IOCTL_GET_MIX_STAT        19  /* get MIX status */
00316 #define SCUX_IOCTL_MAX                 20
00317 
00318 #if(1) /* mbed */
00319 #else  /* not mbed */
00320 /* SCUX status */
00321 #define SCUX_STAT_STOP    0  /* request regstration isn't start */
00322 #define SCUX_STAT_IDLE    1  /* request isn't receied */
00323 #define SCUX_STAT_TRANS   2  /* under data transfer execution */
00324 #endif /* end mbed */
00325 
00326 /* DVU status */
00327 #define SCUX_DVU_STAT_MUTE          0  /* DVU volume is mute */
00328 #define SCUX_DVU_STAT_RAMP_DOWN     1  /* DVU volume is ramp down */
00329 #define SCUX_DVU_STAT_RAMP_UP       2  /* DVU volume is ramp up */
00330 #define SCUX_DVU_STAT_RAMP_FIXED    3  /* DVU volume change is stop */
00331 #define SCUX_DVU_STAT_ORIGINAL_SIZE 4  /* DVU volume is original size */
00332 
00333 /* MIX status */
00334 #define SCUX_MIX_STAT_RAMP_FIXED  0  /* MIX volume change is stop */
00335 #define SCUX_MIX_STAT_RAMP_DOWN   1  /* MIX volume is ramp down */
00336 #define SCUX_MIX_STAT_RAMP_UP     2  /* MIX volume is ramp up */
00337 
00338 /*************************************************************************
00339  Structures
00340 *************************************************************************/
00341 
00342 /* SSIF channel synchronous setting */
00343 typedef struct
00344 {
00345     scux_ssif_ch_num_t     ssif_ch_num;       /* ssif channel number */
00346     scux_pin_mode_t        pin_mode;          /* SSIF sync setting */
00347 } scux_ssif_pin_mode_t;
00348 
00349 /* SSIF AUDIO_CLK source parameters */
00350 typedef struct
00351 {
00352     scux_ssif_ch_num_t     ssif_ch_num;       /* ssif channel number */
00353     scux_src_clk_source_t  pin_clk;           /* AUDIO_CLK source */
00354 } scux_ssif_pin_clk_t;
00355 
00356 /* SSIF parameters */
00357 typedef struct
00358 {
00359     scux_ssif_ch_num_t     ssif_ch_num;       /* ssif channel number */
00360     bool_t                 mode_master;       /* master mode / slave mode select */
00361     bool_t                 select_audio_clk;  /* AUDIO_X1 / AUDIO_CLK select */
00362     scux_ssif_system_len_t system_word;       /* system word length */
00363     bool_t                 sck_polarity_rise; /* SCK polarity type select */
00364     bool_t                 ws_polarity_high;  /* WS polarity type select */
00365     bool_t                 padding_high;      /* padding type select */
00366     bool_t                 serial_data_align; /* serial data alingment type select */
00367     bool_t                 ws_delay;          /* WS delay type select */
00368     bool_t                 use_noise_cancel;  /* noise cancel ON / OFF select */
00369     bool_t                 use_tdm;           /* TDM mode ON / OFF select */
00370 } scux_ssif_cfg_t;
00371 
00372 /* MIX parameters */
00373 typedef struct
00374 {
00375     bool_t               mixmode_ramp;                          /* ramp mode / step mpde select */
00376     scux_mix_ramp_time_t up_period;                             /* ramp up period */
00377     scux_mix_ramp_time_t down_period;                           /* ramp down period */
00378     uint32_t             mix_vol[SCUX_CH_NUM];                  /* MIX volume value */
00379     scux_audio_channel_t select_out_data_ch[SCUX_AUDIO_CH_MAX]; /* audio data position setting */
00380 } scux_mix_cfg_t;
00381 
00382 /* zerocross mute parameters */
00383 typedef struct
00384 {
00385     bool_t               zc_mute_enable[SCUX_AUDIO_CH_MAX];     /* zerocross mute enable setting */
00386     void                 (*pcallback[SCUX_AUDIO_CH_MAX])(void); /* callback pointer for zerocross */
00387 } scux_zc_mute_t;
00388 
00389 /* ramp volume parameters */
00390 typedef struct
00391 {
00392     bool_t               ramp_vol_enable[SCUX_AUDIO_CH_MAX];  /* ramp volume enable setting */
00393     scux_dvu_ramp_time_t up_period;                           /* ramp up period */
00394     scux_dvu_ramp_time_t down_period;                         /* ramp down period */
00395     uint32_t             ramp_vol;                            /* ramp volume value */
00396     uint32_t             ramp_wait_time;                      /* wait time for volume change */
00397 } scux_dvu_ramp_vol_t;
00398 
00399 /* digital volume parameters */
00400 typedef struct
00401 {
00402     bool_t               digi_vol_enable;             /* digital volume enable setting */
00403     uint32_t             digi_vol[SCUX_AUDIO_CH_MAX]; /* digital volume value */
00404 } scux_dvu_digi_vol_t;
00405 
00406 /* DVU parameters */
00407 typedef struct
00408 {
00409     bool_t               dvu_enable;          /* DVU enable setting */
00410     scux_dvu_digi_vol_t  dvu_digi_vol;        /* digital volume setting */
00411     scux_dvu_ramp_vol_t  dvu_ramp_vol;        /* ramp volume setting */
00412     scux_zc_mute_t       dvu_zc_mute;         /* zerocross mute setting */
00413 } scux_dvu_cfg_t;
00414 
00415 /* SRC parameters */
00416 typedef struct
00417 {
00418     bool_t                src_enable;          /* SRC enable setting */
00419     scux_use_channel_t    use_ch;              /* used data channel setting */
00420     scux_data_word_len_t  word_len;            /* used word length setting */
00421     bool_t                mode_sync;           /* sync mode/async mode select */
00422     scux_src_sync_rate_t  input_rate_sync;     /* input rate on sync mode */
00423     scux_src_clk_source_t input_clk_async;      /* input clock source on async mode */
00424     uint32_t              input_div_async;     /* input divide rate on async mode */
00425     scux_src_sync_rate_t  output_rate_sync;    /* output rate on sync mode */
00426     scux_src_clk_source_t output_clk_async;    /* output clock source on async mode */
00427     uint32_t              output_div_async;    /* output divide rate on async mode */
00428     uint32_t              input_ws;            /* input WS frequency */
00429     uint32_t              output_ws;           /* output WS frequency */
00430     uint32_t              freq_tioc3a;         /* frequency of TIOC3A */
00431     uint32_t              freq_tioc4a;         /* frequency of TIOC4A */
00432     scux_src_delay_mode_t delay_mode;          /* delay mode setting */
00433     uint32_t              wait_sample;         /* wait time setting */
00434     uint8_t               min_rate_percentage; /* minimum rate setting */
00435     scux_audio_channel_t  select_in_data_ch[SCUX_AUDIO_CH_MAX]; /* audio data position setting */
00436 } scux_src_cfg_t;
00437 
00438 /* SCUX setup parameter */
00439 typedef struct
00440 {
00441     bool_t           enabled;               /* channel used flag */
00442     uint8_t          int_level;             /* interrupt priority */
00443     scux_route_t     route;                 /* reoute setting */
00444     scux_src_cfg_t   src_cfg;               /* SRC parameters */
00445 } scux_channel_cfg_t;
00446 
00447 /******************************************************************************
00448 Functions Prototypes
00449 ******************************************************************************/
00450 
00451 #if(1) /* mbed */
00452 RBSP_MBED_FNS* R_SCUX_MakeCbTbl_mbed(void);
00453 #else  /* not mbed */
00454 IOIF_DRV_API* R_SCUX_MakeCbTbl(void);
00455 #endif /* end mbed */
00456 
00457 extern uint16_t R_SCUX_GetVersion(void);
00458 
00459 #ifdef __cplusplus
00460 }
00461 #endif /* __cplusplus */
00462 
00463 #endif /* SCUX_IF_H */