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scux_dev.c
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00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer 00021 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 00024 /**************************************************************************//** 00025 * @file scux_dev.c 00026 * $Rev: 1674 $ 00027 * $Date:: 2015-05-29 16:35:57 +0900#$ 00028 * @brief SCUX device control functions 00029 ******************************************************************************/ 00030 00031 /******************************************************************************* 00032 Includes <System Includes>, "Project Includes" 00033 *******************************************************************************/ 00034 00035 #include "scux.h" 00036 00037 /****************************************************************************** 00038 Exported global variables (to be accessed by other files) 00039 ******************************************************************************/ 00040 00041 /****************************************************************************** 00042 Private global driver management information 00043 ******************************************************************************/ 00044 00045 /* SSIF clock mask register table define */ 00046 static const uint32_t gb_cpg_scux_ssif_stbcr_bit[SCUX_SSIF_CH_NUM] = 00047 { 00048 CPG_STBCR11_BIT_MSTP115, /* SSIF0 */ 00049 CPG_STBCR11_BIT_MSTP114, /* SSIF1 */ 00050 CPG_STBCR11_BIT_MSTP113, /* SSIF2 */ 00051 CPG_STBCR11_BIT_MSTP112, /* SSIF3 */ 00052 CPG_STBCR11_BIT_MSTP111, /* SSIF4 */ 00053 CPG_STBCR11_BIT_MSTP110 /* SSIF5 */ 00054 }; 00055 00056 /* SSIF software reset register table define */ 00057 static const uint32_t gb_cpg_scux_ssif_swrst_bit[SCUX_SSIF_CH_NUM] = 00058 { 00059 CPG_SWRSTCR1_BIT_SRST16, /* SSIF0 */ 00060 CPG_SWRSTCR1_BIT_SRST15, /* SSIF1 */ 00061 CPG_SWRSTCR1_BIT_SRST14, /* SSIF2 */ 00062 CPG_SWRSTCR1_BIT_SRST13, /* SSIF3 */ 00063 CPG_SWRSTCR1_BIT_SRST12, /* SSIF4 */ 00064 CPG_SWRSTCR1_BIT_SRST11 /* SSIF5 */ 00065 }; 00066 00067 /* SSIF noise cancel register table define */ 00068 static const uint32_t gb_cpg_scux_ssif_sncr_bit[SCUX_SSIF_CH_NUM] = 00069 { 00070 SCUX_SSIF_GPIO_SNCR_SHIFT_CH0, /* SSIF0 */ 00071 SCUX_SSIF_GPIO_SNCR_SHIFT_CH1, /* SSIF1 */ 00072 SCUX_SSIF_GPIO_SNCR_SHIFT_CH2, /* SSIF2 */ 00073 SCUX_SSIF_GPIO_SNCR_SHIFT_CH3, /* SSIF3 */ 00074 SCUX_SSIF_GPIO_SNCR_SHIFT_CH4, /* SSIF4 */ 00075 SCUX_SSIF_GPIO_SNCR_SHIFT_CH5 /* SSIF5 */ 00076 }; 00077 00078 /* AIOCB information for DMA */ 00079 static AIOCB gb_scux_write_dma_aio[SCUX_CH_NUM]; 00080 static AIOCB gb_scux_read_dma_aio[SCUX_CH_NUM]; 00081 00082 /****************************************************************************** 00083 Function prototypes 00084 ******************************************************************************/ 00085 00086 static void SCUX_SetupDataPosition(scux_info_ch_t * const p_scux_info_ch); 00087 static void SCUX_SetupSrcClk(scux_info_ch_t * const p_scux_info_ch); 00088 static void SCUX_SetupFifo(scux_info_ch_t * const p_scux_info_ch); 00089 static void SCUX_SetupSrcFunction(scux_info_ch_t * const p_scux_info_ch); 00090 static void SCUX_SetupDvuVolume(scux_info_ch_t * const p_scux_info_ch); 00091 static void SCUX_SetupMix(scux_info_ch_t * const p_scux_info_ch); 00092 static void SCUX_DMA_CopyRxCallBack(union sigval const param); 00093 static void SCUX_DMA_CommonTxNextDummyData(scux_info_ch_t * const p_info_ch); 00094 static void SCUX_DMA_CopyTxEndFlush(scux_info_ch_t * const p_info_ch); 00095 static void SCUX_DMA_CopyTxNextRemainData(scux_info_ch_t * const p_info_ch); 00096 static void SCUX_DMA_CopyTxNextData(scux_info_ch_t * const p_info_ch); 00097 static void SCUX_DMA_CopyTxCallBack(union sigval const param); 00098 static void SCUX_DMA_DirectTxEndFlush(scux_info_ch_t * const p_info_ch); 00099 static void SCUX_DMA_DirectTxNextRemainData(scux_info_ch_t * const p_info_ch); 00100 static void SCUX_DMA_DirectTxNextData(scux_info_ch_t * const p_info_ch); 00101 static void SCUX_DMA_DirectTxCallBack(union sigval const param); 00102 00103 /**************************************************************************//** 00104 * Function Name: SCUX_CopyWriteStart 00105 * @brief Start write request (mem->mem). 00106 * 00107 * Description:<br> 00108 * 00109 * @param[in] *p_scux_info_ch:SCUX channel information. 00110 * @param[in] *p_write_aio:Write request information. 00111 * @retval ESUCCESS : Operation successful. 00112 * EFAULT : Internal error is occured. 00113 ******************************************************************************/ 00114 00115 int_t SCUX_CopyWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio) 00116 { 00117 int_t retval; 00118 int_t dma_retval; 00119 dma_trans_data_t dma_address_param; 00120 uint32_t dma_src_addr; 00121 int_t ret; 00122 00123 if ((NULL == p_scux_info_ch) || (NULL == p_write_aio)) 00124 { 00125 retval = EFAULT; 00126 } 00127 else 00128 { 00129 retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL); 00130 00131 if (ESUCCESS != retval) 00132 { 00133 retval = EFAULT; 00134 } 00135 else 00136 { 00137 /* set first trans information */ 00138 p_scux_info_ch->p_tx_aio = p_write_aio; 00139 p_scux_info_ch->p_tx_next_aio = NULL; 00140 p_scux_info_ch->first_tx_flag = false; 00141 00142 /* cast uint8_t pointer from void pointer */ 00143 dma_src_addr = (uint32_t)p_write_aio->aio_buf; 00144 00145 /* set 1st DMA parameter */ 00146 dma_address_param.src_addr = (void *)dma_src_addr; 00147 dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim; 00148 dma_address_param.count = p_write_aio->aio_nbytes; 00149 00150 dma_retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, &ret); 00151 if (ESUCCESS != dma_retval) 00152 { 00153 retval = EFAULT; 00154 } 00155 else 00156 { 00157 p_scux_info_ch->dma_tx_current_size = dma_address_param.count; 00158 /* enable interrupt */ 00159 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET | 00160 DEVMR_FFD0_DEVMOF_SET | 00161 DEVMR_FFD0_DEVMOL_SET | 00162 DEVMR_FFD0_DEVMIUF_SET); 00163 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE; 00164 /* start clock devide on async mode */ 00165 if (false == p_scux_info_ch->src_cfg.mode_sync) 00166 { 00167 if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00168 (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00169 (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00170 (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00171 (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00172 (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async)) 00173 { 00174 *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET; 00175 } 00176 } 00177 /* update channel status */ 00178 switch (p_scux_info_ch->ch_stat) 00179 { 00180 case SCUX_CH_UNINIT : 00181 /* fall through */ 00182 case SCUX_CH_INIT : 00183 /* fall through */ 00184 case SCUX_CH_STOP : 00185 retval = EBADF; 00186 break; 00187 00188 case SCUX_CH_TRANS_IDLE : 00189 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_WR; 00190 break; 00191 00192 case SCUX_CH_TRANS_RD : 00193 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RDWR; 00194 break; 00195 00196 case SCUX_CH_TRANS_WR : 00197 /* fall through */ 00198 case SCUX_CH_TRANS_RDWR : 00199 /* fall through */ 00200 case SCUX_CH_STOP_WAIT : 00201 /* fall through */ 00202 case SCUX_CH_STOP_WAIT_IDLE : 00203 /* do nothing, stats isn't updated */ 00204 break; 00205 00206 default : 00207 retval = EFAULT; 00208 /* NOTREACHED on At the time of a normal performance */ 00209 break; 00210 } 00211 } 00212 } 00213 } 00214 00215 return retval; 00216 } 00217 00218 /****************************************************************************** 00219 End of function SCUX_CopyWriteStart 00220 ******************************************************************************/ 00221 00222 /**************************************************************************//** 00223 * Function Name: SCUX_DirectWriteStart 00224 * @brief Start write request(SSIF direct route). 00225 * 00226 * Description:<br> 00227 * 00228 * @param[in] *p_scux_info_ch:SCUX channel information. 00229 * @param[in] *p_write_aio:Write request information. 00230 * @retval ESUCCESS : Operation successful. 00231 * EFAULT : Internal error is occured. 00232 ******************************************************************************/ 00233 00234 int_t SCUX_DirectWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio) 00235 { 00236 int_t retval; 00237 int_t dma_retval; 00238 dma_trans_data_t dma_address_param; 00239 dma_trans_data_t next_dma_address_param; 00240 uint32_t dma_src_addr; 00241 int_t ret; 00242 uint32_t ramp_wait_cnt = 0; 00243 00244 if ((NULL == p_scux_info_ch) || (NULL == p_write_aio)) 00245 { 00246 retval = EFAULT; 00247 } 00248 else 00249 { 00250 retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL); 00251 00252 if (ESUCCESS != retval) 00253 { 00254 retval = EFAULT; 00255 } 00256 else 00257 { 00258 /* set first trans information */ 00259 p_scux_info_ch->p_tx_aio = NULL; 00260 p_scux_info_ch->p_tx_next_aio = p_write_aio; 00261 p_scux_info_ch->first_tx_flag = true; 00262 00263 /* cast uint8_t pointer from void pointer */ 00264 dma_src_addr = (uint32_t)p_write_aio->aio_buf; 00265 00266 /* set 2nd DMA parameter */ 00267 next_dma_address_param.src_addr = (void *)(dma_src_addr + (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE)); 00268 next_dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim; 00269 next_dma_address_param.count = (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE); 00270 if (0U != (p_write_aio->aio_nbytes % SCUX_HALF_SIZE_VALUE)) 00271 { 00272 /* last data ,when even value size */ 00273 next_dma_address_param.count++; 00274 } 00275 dma_retval = R_DMA_NextData(p_scux_info_ch->dma_tx_ch, &next_dma_address_param, &ret); 00276 00277 if (ESUCCESS != dma_retval) 00278 { 00279 retval = EFAULT; 00280 } 00281 else 00282 { 00283 p_scux_info_ch->dma_tx_next_size = next_dma_address_param.count; 00284 /* set 1st DMA parameter */ 00285 dma_address_param.src_addr = (void *)dma_src_addr; 00286 dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim; 00287 dma_address_param.count = (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE); 00288 00289 dma_retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, &ret); 00290 if (ESUCCESS != dma_retval) 00291 { 00292 retval = EFAULT; 00293 } 00294 else 00295 { 00296 p_scux_info_ch->dma_tx_current_size = dma_address_param.count; 00297 /* enable interrupt */ 00298 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET | 00299 DEVMR_FFD0_DEVMOF_SET | 00300 DEVMR_FFD0_DEVMOL_SET | 00301 DEVMR_FFD0_DEVMIUF_SET); 00302 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE; 00303 *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET; 00304 00305 switch (p_scux_info_ch->ch_stat) 00306 { 00307 case SCUX_CH_UNINIT : 00308 /* fall through */ 00309 case SCUX_CH_INIT : 00310 /* fall through */ 00311 case SCUX_CH_STOP : 00312 /* fall through */ 00313 retval = EBADF; 00314 break; 00315 00316 case SCUX_CH_TRANS_IDLE : 00317 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_WR; 00318 break; 00319 00320 case SCUX_CH_TRANS_RD : 00321 /* read function disabled */ 00322 retval = EFAULT; 00323 break; 00324 00325 case SCUX_CH_TRANS_WR : 00326 /* do nothing, stats isn't updated */ 00327 break; 00328 00329 case SCUX_CH_TRANS_RDWR : 00330 /* read function disabled */ 00331 retval = EFAULT; 00332 break; 00333 00334 case SCUX_CH_STOP_WAIT : 00335 /* do nothing, stats isn't updated */ 00336 break; 00337 00338 case SCUX_CH_STOP_WAIT_IDLE : 00339 /* read function disabled */ 00340 retval = EFAULT; 00341 break; 00342 00343 default : 00344 /* NOTREACHED on At the time of a normal performance */ 00345 retval = EFAULT; 00346 break; 00347 } 00348 00349 /* set ramp setting */ 00350 if (false == p_scux_info_ch->first_ramp_flag) 00351 { 00352 while((DVUSR_DVU0_VRSTS_VOL_FIX != (p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUSR_DVU0_0 & DVUSR_DVU0_VRSTS_MASK)) && 00353 (SCUX_RAMP_WAIT_MAX > ramp_wait_cnt)) 00354 { 00355 ramp_wait_cnt++; 00356 } 00357 if (SCUX_RAMP_WAIT_MAX <= ramp_wait_cnt) 00358 { 00359 retval = EFAULT; 00360 } 00361 else 00362 { 00363 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET; 00364 SCUX_SetRampVolRegister(p_scux_info_ch); 00365 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET; 00366 p_scux_info_ch->first_ramp_flag = true; 00367 } 00368 } 00369 } 00370 } 00371 } 00372 } 00373 00374 return retval; 00375 } 00376 00377 /****************************************************************************** 00378 End of function SCUX_DirectWriteStart 00379 ******************************************************************************/ 00380 00381 /**************************************************************************//** 00382 * Function Name: SCUX_CopyReadStart 00383 * @brief Start read request(mem -> mem). 00384 * 00385 * Description:<br> 00386 * 00387 * @param[in] *p_scux_info_ch:SCUX channel information. 00388 * @param[in] *p_read_aio:Read request information. 00389 * @retval ESUCCESS : Operation successful. 00390 * EFAULT : Internal error is occured. 00391 ******************************************************************************/ 00392 00393 int_t SCUX_CopyReadStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_read_aio) 00394 { 00395 int_t retval; 00396 int_t dma_retval; 00397 dma_trans_data_t dma_address_param; 00398 uint32_t dma_dst_addr; 00399 00400 if ((NULL == p_scux_info_ch) || (NULL == p_read_aio)) 00401 { 00402 retval = EFAULT; 00403 } 00404 else 00405 { 00406 retval = R_DMA_Setup(p_scux_info_ch->dma_rx_ch, &p_scux_info_ch->dma_rx_setup, NULL); 00407 00408 if (ESUCCESS != retval) 00409 { 00410 retval = EFAULT; 00411 } 00412 else 00413 { 00414 /* set first trans information */ 00415 p_scux_info_ch->p_rx_aio = p_read_aio; 00416 p_scux_info_ch->p_rx_next_aio = NULL; 00417 p_scux_info_ch->first_rx_flag = false; 00418 00419 /* cast uint8_t pointer from void pointer */ 00420 dma_dst_addr = (uint32_t)p_read_aio->aio_buf; 00421 00422 /* set 1st DMA parameter */ 00423 dma_address_param.src_addr = (void *)p_scux_info_ch->p_scux_reg->dmatu_n_cim; 00424 dma_address_param.dst_addr = (void *)dma_dst_addr; 00425 dma_address_param.count = p_read_aio->aio_nbytes; 00426 00427 dma_retval = R_DMA_Start(p_scux_info_ch->dma_rx_ch, &dma_address_param, NULL); 00428 00429 if (ESUCCESS != dma_retval) 00430 { 00431 retval = EFAULT; 00432 } 00433 else 00434 { 00435 /* enable interrupt */ 00436 p_scux_info_ch->dma_rx_current_size = dma_address_param.count; 00437 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = (UEVMR_FFU0_UEVMUF_SET | 00438 UEVMR_FFU0_UEVMOF_SET | 00439 UEVMR_FFU0_UEVMOL_SET); 00440 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = DEVCR_FFD0_INIT_VALUE; 00441 /* start clock devide on async mode */ 00442 if (false == p_scux_info_ch->src_cfg.mode_sync) 00443 { 00444 if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00445 (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00446 (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00447 (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00448 (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00449 (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async)) 00450 { 00451 p_scux_info_ch->futsel_cim_value |= FUTSEL_CIM_DIVEN_SET; 00452 *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value; 00453 } 00454 } 00455 /* update channel status */ 00456 00457 switch (p_scux_info_ch->ch_stat) 00458 { 00459 case SCUX_CH_UNINIT : 00460 /* fall through */ 00461 case SCUX_CH_INIT : 00462 /* fall through */ 00463 case SCUX_CH_STOP : 00464 /* fall through */ 00465 retval = EBADF; 00466 break; 00467 00468 case SCUX_CH_TRANS_IDLE : 00469 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RD; 00470 break; 00471 00472 case SCUX_CH_TRANS_RD : 00473 /* do nothing, stats isn't updated */ 00474 break; 00475 00476 case SCUX_CH_TRANS_WR : 00477 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RDWR; 00478 break; 00479 00480 case SCUX_CH_TRANS_RDWR : 00481 /* fall through */ 00482 case SCUX_CH_STOP_WAIT : 00483 /* do nothing, stats isn't updated */ 00484 break; 00485 00486 case SCUX_CH_STOP_WAIT_IDLE : 00487 p_scux_info_ch->ch_stat = SCUX_CH_STOP_WAIT; 00488 break; 00489 00490 default : 00491 /* NOTREACHED on At the time of a normal performance */ 00492 retval = EFAULT; 00493 break; 00494 } 00495 } 00496 } 00497 } 00498 00499 return retval; 00500 } 00501 00502 /****************************************************************************** 00503 End of function SCUX_CopyReadStart 00504 ******************************************************************************/ 00505 00506 /**************************************************************************//** 00507 * Function Name: SCUX_FlushWriteStart 00508 * @brief Start dummy write for FIFO flush. 00509 * 00510 * Description:<br> 00511 * 00512 * @param[in] *p_scux_info_ch:SCUX channel information. 00513 * @param[in] *p_write_aio:Write request information. 00514 * @retval ESUCCESS : Operation successful. 00515 * EFAULT : Internal error is occured. 00516 ******************************************************************************/ 00517 00518 int_t SCUX_FlushWriteStart(scux_info_ch_t * const p_scux_info_ch) 00519 { 00520 int_t retval = ESUCCESS; 00521 dma_trans_data_t dma_address_param; 00522 00523 if (NULL == p_scux_info_ch) 00524 { 00525 retval = EFAULT; 00526 } 00527 else 00528 { 00529 if (0U != p_scux_info_ch->flush_stop_size) 00530 { 00531 retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL); 00532 00533 if (ESUCCESS != retval) 00534 { 00535 retval = EFAULT; 00536 } 00537 else 00538 { 00539 /* trans dummy data size is FIFO size unit */ 00540 if (p_scux_info_ch->flush_stop_size >= p_scux_info_ch->fifo_size) 00541 { 00542 dma_address_param.count = p_scux_info_ch->fifo_size; 00543 p_scux_info_ch->flush_stop_size -= p_scux_info_ch->fifo_size; 00544 } 00545 else 00546 { 00547 /* last data is fraction of FIFO size */ 00548 dma_address_param.count = p_scux_info_ch->flush_stop_size; 00549 p_scux_info_ch->flush_stop_size = 0; 00550 } 00551 00552 dma_address_param.src_addr = (void *)(p_scux_info_ch->p_tx_dummy_data); 00553 dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim; 00554 00555 retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, NULL); 00556 if (ESUCCESS != retval) 00557 { 00558 retval = EFAULT; 00559 } 00560 else 00561 { 00562 p_scux_info_ch->dma_tx_current_size = dma_address_param.count; 00563 00564 p_scux_info_ch->tx_dummy_run_flag = true; 00565 00566 if ((SCUX_CH_TRANS_RD == p_scux_info_ch->ch_stat) || (SCUX_CH_TRANS_IDLE == p_scux_info_ch->ch_stat)) 00567 { 00568 /* restart write operation when write is stopped */ 00569 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET | 00570 DEVMR_FFD0_DEVMOF_SET | 00571 DEVMR_FFD0_DEVMOL_SET | 00572 DEVMR_FFD0_DEVMIUF_SET); 00573 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 00574 = DEVCR_FFD0_INIT_VALUE; 00575 /* start clock devide on async mode or SSIF direct route setting */ 00576 if (false == p_scux_info_ch->src_cfg.mode_sync) 00577 { 00578 if((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00579 (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00580 (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00581 (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00582 (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) && 00583 (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async)) 00584 { 00585 *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET; 00586 } 00587 } 00588 } 00589 } 00590 } 00591 } 00592 } 00593 00594 return retval; 00595 } 00596 00597 /****************************************************************************** 00598 End of function SCUX_FlushWriteStart 00599 ******************************************************************************/ 00600 00601 /**************************************************************************//** 00602 * Function Name: SCUX_CopyCancelSpecific 00603 * @brief Cancel specific request(mem->mem). 00604 * 00605 * Description:<br> 00606 * 00607 * @param[in] *p_scux_info_ch : SCUX channel information. 00608 * @param[in] *p_cancel_aio : Cancel request information. 00609 * @retval ESUCCESS : Operation successful. 00610 * EBUSY : Cancel requst is on going. 00611 * EFAULT : Internal error is occured. 00612 ******************************************************************************/ 00613 00614 #if(1) /* mbed */ 00615 #if defined (__CC_ARM) 00616 #pragma O0 00617 #endif 00618 #endif /* end mbed */ 00619 int_t SCUX_CopyCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio) 00620 { 00621 int_t retval = ESUCCESS; 00622 int_t dummy_retval; 00623 int_t was_masked; 00624 00625 if (NULL == p_scux_info_ch) 00626 { 00627 retval = EFAULT; 00628 } 00629 else 00630 { 00631 #if defined (__ICCARM__) 00632 was_masked = __disable_irq_iar(); 00633 #else 00634 was_masked = __disable_irq(); 00635 #endif 00636 00637 /* check cancel request */ 00638 if ((p_scux_info_ch->p_tx_aio == p_cancel_aio) || (p_scux_info_ch->p_rx_aio == p_cancel_aio)) 00639 { 00640 retval = EBUSY; 00641 } 00642 else 00643 { 00644 /* request don't going */ 00645 dummy_retval = ahf_cancel(&p_scux_info_ch->tx_que, p_cancel_aio); 00646 if (ESUCCESS != dummy_retval) 00647 { 00648 /* NON_NOTICE_ASSERT: queue cancel error */ 00649 } 00650 dummy_retval = ahf_cancel(&p_scux_info_ch->rx_que, p_cancel_aio); 00651 if (ESUCCESS != dummy_retval) 00652 { 00653 /* NON_NOTICE_ASSERT: queue cancel error */ 00654 } 00655 } 00656 00657 if (0 == was_masked) 00658 { 00659 __enable_irq(); 00660 } 00661 } 00662 00663 return retval; 00664 } 00665 #if(1) /* mbed */ 00666 #if defined (__CC_ARM) 00667 #pragma O3 00668 #endif 00669 #endif /* end mbed */ 00670 00671 /****************************************************************************** 00672 End of function SCUX_CopyCancelSpecific 00673 ******************************************************************************/ 00674 00675 /**************************************************************************//** 00676 * Function Name: SCUX_DirectCancelSpecific 00677 * @brief Cancel specific request(SSIF direct route). 00678 * 00679 * Description:<br> 00680 * 00681 * @param[in] *p_scux_info_ch : SCUX channel information. 00682 * @param[in] *p_cancel_aio : Cancel request information. 00683 * @retval ESUCCESS : Operation successful. 00684 * EBUSY : Cancel requst is on going. 00685 * EFAULT : Internal error is occured. 00686 ******************************************************************************/ 00687 00688 int_t SCUX_DirectCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio) 00689 { 00690 int_t retval = ESUCCESS; 00691 int_t dummy_retval; 00692 int_t was_masked; 00693 00694 if (NULL == p_scux_info_ch) 00695 { 00696 retval = EFAULT; 00697 } 00698 else 00699 { 00700 #if defined (__ICCARM__) 00701 was_masked = __disable_irq_iar(); 00702 #else 00703 was_masked = __disable_irq(); 00704 #endif 00705 00706 /* check cancel request */ 00707 if ((p_scux_info_ch->p_tx_aio == p_cancel_aio) || (p_scux_info_ch->p_tx_next_aio == p_cancel_aio)) 00708 { 00709 retval = EBUSY; 00710 } 00711 else 00712 { 00713 /* request don't going */ 00714 dummy_retval = ahf_cancel(&p_scux_info_ch->tx_que, p_cancel_aio); 00715 if (ESUCCESS != dummy_retval) 00716 { 00717 /* NON_NOTICE_ASSERT: queue cancel error */ 00718 } 00719 } 00720 00721 if (0 == was_masked) 00722 { 00723 __enable_irq(); 00724 } 00725 } 00726 00727 return retval; 00728 } 00729 00730 /****************************************************************************** 00731 End of function SCUX_DirectCancelSpecific 00732 ******************************************************************************/ 00733 00734 /**************************************************************************//** 00735 * Function Name: SCUX_CopyCancelAll 00736 * @brief Cancel all request(mem->mem). 00737 * 00738 * Description:<br> 00739 * 00740 * @param[in] *p_scux_info_ch : SCUX channel information. 00741 * @retval ESUCCESS : Operation successful. 00742 * EFAULT : Internal error is occured. 00743 ******************************************************************************/ 00744 00745 #if(1) /* mbed */ 00746 #if defined (__CC_ARM) 00747 #pragma O0 00748 #endif 00749 #endif /* end mbed */ 00750 int_t SCUX_CopyCancelAll(scux_info_ch_t * const p_scux_info_ch) 00751 { 00752 int_t retval = ESUCCESS; 00753 int_t dma_ercd; 00754 int_t dma_retval; 00755 int_t was_masked; 00756 uint32_t tx_remain_size = 0; 00757 uint32_t rx_remain_size = 0; 00758 00759 if (NULL == p_scux_info_ch) 00760 { 00761 retval = EFAULT; 00762 } 00763 else 00764 { 00765 #if defined (__ICCARM__) 00766 was_masked = __disable_irq_iar(); 00767 #else 00768 was_masked = __disable_irq(); 00769 #endif 00770 00771 dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd); 00772 /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */ 00773 if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd)) 00774 { 00775 retval = EFAULT; 00776 } 00777 else 00778 { 00779 p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size; 00780 p_scux_info_ch->dma_tx_current_size = 0; 00781 } 00782 00783 dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd); 00784 /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */ 00785 if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd)) 00786 { 00787 retval = EFAULT; 00788 } 00789 else 00790 { 00791 p_scux_info_ch->rx_fifo_total_size += p_scux_info_ch->dma_rx_current_size; 00792 p_scux_info_ch->dma_rx_current_size = 0; 00793 } 00794 00795 if (ESUCCESS == retval) 00796 { 00797 /* return write request */ 00798 if (NULL != p_scux_info_ch->p_tx_aio) 00799 { 00800 p_scux_info_ch->p_tx_aio->aio_return = ECANCELED; 00801 ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio); 00802 } 00803 00804 /* return read request */ 00805 if (NULL != p_scux_info_ch->p_rx_aio) 00806 { 00807 p_scux_info_ch->p_rx_aio->aio_return = ECANCELED; 00808 ahf_complete(&p_scux_info_ch->rx_que, p_scux_info_ch->p_rx_aio); 00809 } 00810 00811 ahf_cancelall(&p_scux_info_ch->tx_que); 00812 ahf_cancelall(&p_scux_info_ch->rx_que); 00813 00814 p_scux_info_ch->p_tx_aio = NULL; 00815 p_scux_info_ch->p_rx_aio = NULL; 00816 00817 SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, rx_remain_size); 00818 p_scux_info_ch->cancel_operate_flag = true; 00819 00820 if (false != p_scux_info_ch->src_cfg.mode_sync) 00821 { 00822 SCUX_SyncStopHw(p_scux_info_ch); 00823 SCUX_InitHw(p_scux_info_ch); 00824 SCUX_SetupSrc(p_scux_info_ch); 00825 SCUX_SyncStartHw(p_scux_info_ch); 00826 } 00827 else 00828 { 00829 SCUX_AsyncStopHw(p_scux_info_ch); 00830 SCUX_InitHw(p_scux_info_ch); 00831 SCUX_SetupSrc(p_scux_info_ch); 00832 SCUX_AsyncStartHw(p_scux_info_ch); 00833 } 00834 00835 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_IDLE; 00836 p_scux_info_ch->p_flush_callback = NULL; 00837 00838 p_scux_info_ch->tx_fifo_total_size = 0; 00839 p_scux_info_ch->rx_fifo_total_size = 0; 00840 00841 p_scux_info_ch->cancel_operate_flag = false; 00842 } 00843 00844 if (0 == was_masked) 00845 { 00846 __enable_irq(); 00847 } 00848 } 00849 00850 return retval; 00851 } 00852 00853 /****************************************************************************** 00854 End of function SCUX_CopyCancelAll 00855 ******************************************************************************/ 00856 00857 /**************************************************************************//** 00858 * Function Name: SCUX_DirectCancelAll 00859 * @brief Cancel all request(SSIF direct route). 00860 * 00861 * Description:<br> 00862 * 00863 * @param[in] *p_scux_info_ch : SCUX channel information. 00864 * @retval ESUCCESS : Operation successful. 00865 * EFAULT : Internal error is occured. 00866 ******************************************************************************/ 00867 00868 int_t SCUX_DirectCancelAll(scux_info_ch_t * const p_scux_info_ch) 00869 { 00870 int_t retval = ESUCCESS; 00871 int_t dma_ercd; 00872 int_t dma_retval; 00873 int_t was_masked; 00874 uint32_t tx_remain_size = 0; 00875 00876 if (NULL == p_scux_info_ch) 00877 { 00878 retval = EFAULT; 00879 } 00880 else 00881 { 00882 #if defined (__ICCARM__) 00883 was_masked = __disable_irq_iar(); 00884 #else 00885 was_masked = __disable_irq(); 00886 #endif 00887 00888 dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd); 00889 /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */ 00890 if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd)) 00891 { 00892 retval = EFAULT; 00893 } 00894 else 00895 { 00896 p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size; 00897 p_scux_info_ch->dma_tx_current_size = 0; 00898 00899 if (NULL != p_scux_info_ch->p_tx_aio) 00900 { 00901 p_scux_info_ch->p_tx_aio->aio_return = ECANCELED; 00902 ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio); 00903 } 00904 if (NULL != p_scux_info_ch->p_tx_next_aio) 00905 { 00906 p_scux_info_ch->p_tx_next_aio->aio_return = ECANCELED; 00907 ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_next_aio); 00908 } 00909 ahf_cancelall(&p_scux_info_ch->tx_que); 00910 00911 p_scux_info_ch->p_tx_aio = NULL; 00912 p_scux_info_ch->p_tx_next_aio = NULL; 00913 00914 SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, 0); 00915 00916 p_scux_info_ch->cancel_operate_flag = true; 00917 p_scux_info_ch->restart_ramp_flag = true; 00918 00919 SCUX_AsyncStopHw(p_scux_info_ch); 00920 00921 SCUX_InitHw(p_scux_info_ch); 00922 SCUX_SetupSsif(p_scux_info_ch); 00923 SCUX_SetupSrc(p_scux_info_ch); 00924 SCUX_SetupDvu(p_scux_info_ch); 00925 SCUX_AsyncStartHw(p_scux_info_ch); 00926 00927 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_IDLE; 00928 p_scux_info_ch->p_flush_callback = NULL; 00929 00930 p_scux_info_ch->tx_fifo_total_size = 0; 00931 p_scux_info_ch->rx_fifo_total_size = 0; 00932 p_scux_info_ch->dvu_mute_stat = 0; 00933 p_scux_info_ch->first_ramp_flag = false; 00934 p_scux_info_ch->cancel_operate_flag = false; 00935 } 00936 00937 if (0 == was_masked) 00938 { 00939 __enable_irq(); 00940 } 00941 } 00942 00943 return retval; 00944 } 00945 #if(1) /* mbed */ 00946 #if defined (__CC_ARM) 00947 #pragma O3 00948 #endif 00949 #endif /* end mbed */ 00950 00951 /****************************************************************************** 00952 End of function SCUX_DirectCancelAll 00953 ******************************************************************************/ 00954 00955 /**************************************************************************//** 00956 * Function Name: SCUX_AdjustAccessFifo 00957 * @brief Fifo is Cleared. 00958 * 00959 * Description:<br> 00960 * 00961 * @param[in] p_scux_info_ch:channel information. 00962 * @retval None. 00963 ******************************************************************************/ 00964 00965 void SCUX_AdjustAccessFifo(scux_info_ch_t * const p_scux_info_ch, const uint32_t tx_remain_size, const uint32_t rx_remain_size) 00966 { 00967 uint32_t dummy_data_size; 00968 uint32_t request_data_size; 00969 uint32_t access_size = SCUX_DMA_UNIT_SIZE16; 00970 uint32_t dummy_read_data; 00971 00972 if (NULL == p_scux_info_ch) 00973 { 00974 /* NON_NOTICE_ASSERT: NULL pointer */ 00975 } 00976 else 00977 { 00978 *(p_scux_info_ch->p_scux_reg->dmacr_cim) &= ~(DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel); 00979 switch (p_scux_info_ch->src_cfg.word_len) 00980 { 00981 case SCUX_DATA_LEN_24 : 00982 access_size = SCUX_DMA_UNIT_SIZE24; 00983 break; 00984 00985 case SCUX_DATA_LEN_16 : 00986 /* fall through */ 00987 case SCUX_DATA_LEN_16_TO_24 : 00988 access_size = SCUX_DMA_UNIT_SIZE16; 00989 break; 00990 00991 default : 00992 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 00993 /* <-IPA R3.5.2 */ 00994 /* NOTREACHED on At the time of a normal performance */ 00995 break; 00996 } 00997 00998 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET | 00999 DEVMR_FFD0_DEVMOF_SET | 01000 DEVMR_FFD0_DEVMOL_SET | 01001 DEVMR_FFD0_DEVMIUF_SET); 01002 /* access count is adjusted for tx DMA remain size */ 01003 if (0U != tx_remain_size) 01004 { 01005 for (dummy_data_size = 0; dummy_data_size < tx_remain_size; dummy_data_size += access_size ) 01006 { 01007 *(p_scux_info_ch->p_scux_reg->dmatd_n_cim) = 0; 01008 } 01009 } 01010 01011 /* access count is adjusted for tx total remain size */ 01012 if (0U != (p_scux_info_ch->tx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U))) 01013 { 01014 request_data_size = (p_scux_info_ch->fifo_size - (p_scux_info_ch->tx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U))); 01015 for (dummy_data_size = 0; dummy_data_size < request_data_size; dummy_data_size += access_size ) 01016 { 01017 *(p_scux_info_ch->p_scux_reg->dmatd_n_cim) = 0; 01018 } 01019 } 01020 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = 0; 01021 *(p_scux_info_ch->p_scux_reg->dmacr_cim) |= (DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel); 01022 01023 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 01024 { 01025 *(p_scux_info_ch->p_scux_reg->dmacr_cim) &= ~(DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel); 01026 switch (p_scux_info_ch->src_cfg.word_len) 01027 { 01028 case SCUX_DATA_LEN_16 : 01029 access_size = SCUX_DMA_UNIT_SIZE16; 01030 break; 01031 01032 case SCUX_DATA_LEN_24 : 01033 /* fall through */ 01034 case SCUX_DATA_LEN_16_TO_24 : 01035 access_size = SCUX_DMA_UNIT_SIZE24; 01036 break; 01037 01038 default : 01039 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 01040 /* <-IPA R3.5.2 */ 01041 /* NOTREACHED on At the time of a normal performance */ 01042 break; 01043 } 01044 01045 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET | 01046 UEVMR_FFU0_UEVMOF_SET | 01047 UEVMR_FFU0_UEVMOL_SET); 01048 /* access count is adjusted for rx DMA remain size */ 01049 if (0U != rx_remain_size) 01050 { 01051 for (dummy_data_size = 0; dummy_data_size < rx_remain_size; dummy_data_size += access_size ) 01052 { 01053 dummy_read_data = *(p_scux_info_ch->p_scux_reg->dmatu_n_cim); 01054 UNUSED_ARG(dummy_read_data); 01055 } 01056 } 01057 01058 /* access count is adjusted for rx total remain size */ 01059 if (0U != (p_scux_info_ch->rx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U))) 01060 { 01061 request_data_size = (p_scux_info_ch->fifo_size - (p_scux_info_ch->rx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U))); 01062 01063 for (dummy_data_size = 0; dummy_data_size < request_data_size; dummy_data_size += access_size ) 01064 { 01065 dummy_read_data = *(p_scux_info_ch->p_scux_reg->dmatu_n_cim); 01066 UNUSED_ARG(dummy_read_data); 01067 } 01068 } 01069 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = 0; 01070 *(p_scux_info_ch->p_scux_reg->dmacr_cim) |= (DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel); 01071 } 01072 } 01073 01074 return; 01075 } 01076 01077 /****************************************************************************** 01078 End of function SCUX_AdjustAccessFifo 01079 ******************************************************************************/ 01080 01081 /**************************************************************************//** 01082 * Function Name: SCUX_SetupSrc 01083 * @brief SRC HW setup. 01084 * 01085 * Description:<br> 01086 * 01087 * @param[in] *p_scux_info_ch : SCUX channel information. 01088 * @retval None. 01089 ******************************************************************************/ 01090 01091 void SCUX_SetupSrc(scux_info_ch_t * const p_scux_info_ch) 01092 { 01093 uint32_t process_delay = 0; 01094 uint32_t data_size; 01095 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 01096 01097 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch)) 01098 { 01099 /* NON_NOTICE_ASSERT: NULL pointer */ 01100 } 01101 else 01102 { 01103 if (false != p_scux_info_ch->src_cfg.src_enable) 01104 { 01105 /* check delay mode and enabled audio channel */ 01106 switch (p_scux_info_ch->src_cfg.delay_mode) 01107 { 01108 case SCUX_DELAY_NORMAL : 01109 switch (p_scux_info_ch->src_cfg.use_ch) 01110 { 01111 case SCUX_USE_CH_1 : 01112 process_delay = SCUX_PROCESS_DELAY_NORMAL_CH1; 01113 break; 01114 01115 case SCUX_USE_CH_2 : 01116 process_delay = SCUX_PROCESS_DELAY_NORMAL_CH2; 01117 break; 01118 01119 case SCUX_USE_CH_4 : 01120 process_delay = SCUX_PROCESS_DELAY_NORMAL_CH4; 01121 break; 01122 01123 case SCUX_USE_CH_6 : 01124 process_delay = SCUX_PROCESS_DELAY_NORMAL_CH6; 01125 break; 01126 01127 case SCUX_USE_CH_8 : 01128 process_delay = SCUX_PROCESS_DELAY_NORMAL_CH8; 01129 break; 01130 01131 default : 01132 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 01133 /* <-IPA R3.5.2 */ 01134 /* NOTREACHED on At the time of a normal performance */ 01135 break; 01136 } 01137 break; 01138 01139 case SCUX_DELAY_LOW_DELAY1 : 01140 process_delay = SCUX_PROCESS_DELAY_1_CH1_2; 01141 break; 01142 01143 case SCUX_DELAY_LOW_DELAY2 : 01144 process_delay = SCUX_PROCESS_DELAY_2_CH1_2; 01145 break; 01146 01147 default : 01148 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 01149 /* <-IPA R3.5.2 */ 01150 /* NOTREACHED on At the time of a normal performance */ 01151 break; 01152 } 01153 01154 /* set dummy data size for flush */ 01155 if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len) 01156 { 01157 data_size = sizeof(uint16_t); 01158 } 01159 else 01160 { 01161 data_size = sizeof(uint32_t); 01162 } 01163 01164 process_delay = (process_delay * ((p_scux_info_ch->output_rate * SCUX_RATE_INT_CONV_VALUE) / p_scux_info_ch->input_rate)); 01165 if (0U != (process_delay % SCUX_RATE_INT_CONV_VALUE)) 01166 { 01167 /* A redundant value is added that delay size below a decimal point may come out */ 01168 process_delay = ((process_delay / SCUX_RATE_INT_CONV_VALUE) + SCUX_ADJUST_REST_VALUE); 01169 } 01170 else 01171 { 01172 process_delay = (process_delay / SCUX_RATE_INT_CONV_VALUE); 01173 } 01174 01175 p_scux_info_ch->flush_stop_size = (p_scux_info_ch->src_cfg.use_ch * (data_size * (process_delay + SCUX_LOGIC_DELAY_BYPASS_OFF))); 01176 if (0U != (p_scux_info_ch->flush_stop_size % SCUX_EVEN_VALUE_DIV)) 01177 { 01178 /* set even value */ 01179 p_scux_info_ch->flush_stop_size++; 01180 } 01181 } 01182 else 01183 { 01184 /* set dummy data size for flush */ 01185 if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len) 01186 { 01187 data_size = sizeof(uint16_t); 01188 } 01189 else 01190 { 01191 data_size = sizeof(uint32_t); 01192 } 01193 01194 p_scux_info_ch->flush_stop_size = (p_scux_info_ch->src_cfg.use_ch * (data_size * SCUX_LOGIC_DELAY_BYPASS_ON)); 01195 if (0U != (p_scux_info_ch->flush_stop_size % SCUX_EVEN_VALUE_DIV)) 01196 { 01197 /* set even value */ 01198 p_scux_info_ch->flush_stop_size++; 01199 } 01200 } 01201 01202 p_scux_info_ch->tx_dummy_run_flag = false; 01203 01204 /* set FFD & FFU parameter depend on the combination of route and sync mode */ 01205 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 01206 { 01207 if (false != p_scux_info_ch->src_cfg.mode_sync) 01208 { 01209 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_SYNC; 01210 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_PASS_SET_SYNC; 01211 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_SYNC; 01212 p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_SYNC; 01213 } 01214 else 01215 { 01216 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_ASYNC; 01217 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_PASS_SET_ASYNC; 01218 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_ASYNC; 01219 p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_ASYNC; 01220 } 01221 } 01222 else 01223 { 01224 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_ASYNC; 01225 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = 0; 01226 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_ASYNC; 01227 p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_DIRECT; 01228 } 01229 01230 /* set route CIM register for SSIF channel and MIX */ 01231 switch (p_scux_info_ch->route_set) 01232 { 01233 case SCUX_ROUTE_SRC0_MEM : 01234 /* fall through */ 01235 case SCUX_ROUTE_SRC1_MEM : 01236 /* fall through */ 01237 case SCUX_ROUTE_SRC2_MEM : 01238 /* fall through */ 01239 case SCUX_ROUTE_SRC3_MEM : 01240 /* do nothing, when mem to mem route is setting */ 01241 break; 01242 01243 case SCUX_ROUTE_SRC0_SSIF0 : 01244 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK; 01245 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_SRC0_SET; 01246 break; 01247 01248 case SCUX_ROUTE_SRC0_SSIF012 : 01249 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK); 01250 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_SRC0_SET | SSIRSEL_CIM_SOSEL1_SRC0_SET | SSIRSEL_CIM_SOSEL2_SRC0_SET); 01251 break; 01252 01253 case SCUX_ROUTE_SRC0_SSIF3 : 01254 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK; 01255 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_SRC0_SET; 01256 break; 01257 01258 case SCUX_ROUTE_SRC0_SSIF345 : 01259 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK); 01260 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_SRC0_SET | SSIRSEL_CIM_SOSEL4_SRC0_SET | SSIRSEL_CIM_SOSEL5_SRC0_SET); 01261 break; 01262 01263 case SCUX_ROUTE_SRC1_SSIF0 : 01264 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK; 01265 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_SRC1_SET; 01266 break; 01267 01268 case SCUX_ROUTE_SRC1_SSIF012 : 01269 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK); 01270 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_SRC1_SET | SSIRSEL_CIM_SOSEL1_SRC1_SET | SSIRSEL_CIM_SOSEL2_SRC1_SET); 01271 break; 01272 01273 case SCUX_ROUTE_SRC1_SSIF3 : 01274 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK; 01275 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_SRC1_SET; 01276 break; 01277 01278 case SCUX_ROUTE_SRC1_SSIF345 : 01279 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK); 01280 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_SRC1_SET | SSIRSEL_CIM_SOSEL4_SRC1_SET | SSIRSEL_CIM_SOSEL5_SRC1_SET); 01281 break; 01282 01283 case SCUX_ROUTE_SRC2_SSIF1 : 01284 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL1_MASK; 01285 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL1_SRC2_SET; 01286 break; 01287 01288 case SCUX_ROUTE_SRC2_SSIF4 : 01289 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL4_MASK; 01290 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL4_SRC2_SET; 01291 break; 01292 01293 case SCUX_ROUTE_SRC3_SSIF2 : 01294 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL2_MASK; 01295 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL2_SRC3_SET; 01296 break; 01297 01298 case SCUX_ROUTE_SRC3_SSIF5 : 01299 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL5_MASK; 01300 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL5_SRC3_SET; 01301 break; 01302 01303 case SCUX_ROUTE_SRC0_MIX_SSIF0 : 01304 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK; 01305 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET; 01306 break; 01307 01308 case SCUX_ROUTE_SRC0_MIX_SSIF012 : 01309 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK); 01310 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET); 01311 break; 01312 01313 case SCUX_ROUTE_SRC0_MIX_SSIF3 : 01314 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK; 01315 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET; 01316 break; 01317 01318 case SCUX_ROUTE_SRC0_MIX_SSIF345 : 01319 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK); 01320 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET); 01321 break; 01322 01323 case SCUX_ROUTE_SRC1_MIX_SSIF0 : 01324 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK; 01325 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET; 01326 break; 01327 01328 case SCUX_ROUTE_SRC1_MIX_SSIF012 : 01329 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK); 01330 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET); 01331 break; 01332 01333 case SCUX_ROUTE_SRC1_MIX_SSIF3 : 01334 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK; 01335 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET; 01336 break; 01337 01338 case SCUX_ROUTE_SRC1_MIX_SSIF345 : 01339 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK); 01340 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET); 01341 break; 01342 01343 case SCUX_ROUTE_SRC2_MIX_SSIF0 : 01344 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK; 01345 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET; 01346 break; 01347 01348 case SCUX_ROUTE_SRC2_MIX_SSIF012 : 01349 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK); 01350 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET); 01351 break; 01352 01353 case SCUX_ROUTE_SRC2_MIX_SSIF3 : 01354 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK; 01355 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET; 01356 break; 01357 01358 case SCUX_ROUTE_SRC2_MIX_SSIF345 : 01359 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK); 01360 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET); 01361 break; 01362 01363 case SCUX_ROUTE_SRC3_MIX_SSIF0 : 01364 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK; 01365 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET; 01366 break; 01367 01368 case SCUX_ROUTE_SRC3_MIX_SSIF012 : 01369 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK); 01370 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET); 01371 break; 01372 01373 case SCUX_ROUTE_SRC3_MIX_SSIF3 : 01374 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK; 01375 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET; 01376 break; 01377 01378 case SCUX_ROUTE_SRC3_MIX_SSIF345 : 01379 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK); 01380 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET); 01381 break; 01382 01383 default : 01384 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 01385 /* <-IPA R3.5.2 */ 01386 /* NOTREACHED on At the time of a normal performance */ 01387 break; 01388 } 01389 01390 SCUX_SetupDataPosition(p_scux_info_ch); 01391 01392 /* set route SSICTRL register for each route */ 01393 if (false == p_scux_info_ch->src_cfg.mode_sync) 01394 { 01395 switch (p_scux_info_ch->route_set) 01396 { 01397 case SCUX_ROUTE_SRC0_MEM : 01398 /* fall through */ 01399 case SCUX_ROUTE_SRC1_MEM : 01400 /* fall through */ 01401 case SCUX_ROUTE_SRC2_MEM : 01402 /* fall through */ 01403 case SCUX_ROUTE_SRC3_MEM : 01404 /* do nothing, when mem to mem route is setting */ 01405 break; 01406 01407 case SCUX_ROUTE_SRC0_SSIF0 : 01408 /* fall through */ 01409 case SCUX_ROUTE_SRC0_SSIF012 : 01410 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET; 01411 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01412 break; 01413 01414 case SCUX_ROUTE_SRC0_SSIF3 : 01415 /* fall through */ 01416 case SCUX_ROUTE_SRC0_SSIF345 : 01417 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET; 01418 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01419 break; 01420 01421 case SCUX_ROUTE_SRC1_SSIF0 : 01422 /* fall through */ 01423 case SCUX_ROUTE_SRC1_SSIF012 : 01424 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET; 01425 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01426 break; 01427 01428 case SCUX_ROUTE_SRC1_SSIF3 : 01429 /* fall through */ 01430 case SCUX_ROUTE_SRC1_SSIF345 : 01431 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET; 01432 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01433 break; 01434 01435 case SCUX_ROUTE_SRC2_SSIF1 : 01436 /* fall through */ 01437 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI1TX_SET; 01438 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01439 break; 01440 01441 case SCUX_ROUTE_SRC2_SSIF4 : 01442 /* fall through */ 01443 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI4TX_SET; 01444 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01445 break; 01446 01447 case SCUX_ROUTE_SRC3_SSIF2 : 01448 /* fall through */ 01449 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI2TX_SET; 01450 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01451 break; 01452 01453 case SCUX_ROUTE_SRC3_SSIF5 : 01454 /* fall through */ 01455 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI5TX_SET; 01456 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01457 break; 01458 01459 case SCUX_ROUTE_SRC0_MIX_SSIF0 : 01460 /* fall through */ 01461 case SCUX_ROUTE_SRC0_MIX_SSIF012 : 01462 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET; 01463 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01464 break; 01465 01466 case SCUX_ROUTE_SRC0_MIX_SSIF3 : 01467 /* fall through */ 01468 case SCUX_ROUTE_SRC0_MIX_SSIF345 : 01469 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET; 01470 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01471 break; 01472 01473 case SCUX_ROUTE_SRC1_MIX_SSIF0 : 01474 /* fall through */ 01475 case SCUX_ROUTE_SRC1_MIX_SSIF012 : 01476 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET; 01477 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01478 break; 01479 01480 case SCUX_ROUTE_SRC1_MIX_SSIF3 : 01481 /* fall through */ 01482 case SCUX_ROUTE_SRC1_MIX_SSIF345 : 01483 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET; 01484 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01485 break; 01486 01487 case SCUX_ROUTE_SRC2_MIX_SSIF0 : 01488 /* fall through */ 01489 case SCUX_ROUTE_SRC2_MIX_SSIF012 : 01490 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET; 01491 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01492 break; 01493 01494 case SCUX_ROUTE_SRC2_MIX_SSIF3 : 01495 /* fall through */ 01496 case SCUX_ROUTE_SRC2_MIX_SSIF345 : 01497 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET; 01498 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01499 break; 01500 01501 case SCUX_ROUTE_SRC3_MIX_SSIF0 : 01502 /* fall through */ 01503 case SCUX_ROUTE_SRC3_MIX_SSIF012 : 01504 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET; 01505 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01506 break; 01507 01508 case SCUX_ROUTE_SRC3_MIX_SSIF3 : 01509 /* fall through */ 01510 case SCUX_ROUTE_SRC3_MIX_SSIF345 : 01511 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET; 01512 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 01513 break; 01514 01515 default : 01516 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 01517 /* <-IPA R3.5.2 */ 01518 /* NOTREACHED on At the time of a normal performance */ 01519 break; 01520 } 01521 } 01522 01523 SCUX_SetupSrcClk(p_scux_info_ch); 01524 01525 /* set pin mode for each route */ 01526 switch (p_scux_info_ch->route_set) 01527 { 01528 case SCUX_ROUTE_SRC0_MEM : 01529 /* fall through */ 01530 case SCUX_ROUTE_SRC1_MEM : 01531 /* fall through */ 01532 case SCUX_ROUTE_SRC2_MEM : 01533 /* fall through */ 01534 case SCUX_ROUTE_SRC3_MEM : 01535 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01536 break; 01537 01538 case SCUX_ROUTE_SRC0_SSIF0 : 01539 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01540 break; 01541 01542 case SCUX_ROUTE_SRC0_SSIF012 : 01543 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET; 01544 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET; 01545 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK); 01546 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master) 01547 { 01548 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) | 01549 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT)); 01550 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01551 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01552 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01553 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01554 } 01555 else 01556 { 01557 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) | 01558 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT)); 01559 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01560 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01561 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01562 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01563 } 01564 break; 01565 01566 case SCUX_ROUTE_SRC0_SSIF3 : 01567 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01568 break; 01569 01570 case SCUX_ROUTE_SRC0_SSIF345 : 01571 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET; 01572 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET; 01573 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK); 01574 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master) 01575 { 01576 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) | 01577 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT)); 01578 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01579 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01580 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01581 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01582 } 01583 else 01584 { 01585 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) | 01586 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT)); 01587 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01588 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01589 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01590 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01591 } 01592 break; 01593 01594 case SCUX_ROUTE_SRC1_SSIF0 : 01595 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01596 break; 01597 01598 case SCUX_ROUTE_SRC1_SSIF012 : 01599 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET; 01600 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET; 01601 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK); 01602 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master) 01603 { 01604 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) | 01605 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT)); 01606 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01607 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01608 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01609 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01610 } 01611 else 01612 { 01613 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) | 01614 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT)); 01615 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01616 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01617 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01618 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01619 } 01620 break; 01621 01622 case SCUX_ROUTE_SRC1_SSIF3 : 01623 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01624 break; 01625 01626 case SCUX_ROUTE_SRC1_SSIF345 : 01627 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET; 01628 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET; 01629 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK); 01630 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master) 01631 { 01632 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) | 01633 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT)); 01634 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01635 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01636 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01637 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01638 } 01639 else 01640 { 01641 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) | 01642 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT)); 01643 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01644 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01645 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01646 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01647 } 01648 break; 01649 01650 case SCUX_ROUTE_SRC2_SSIF1 : 01651 /* fall through */ 01652 case SCUX_ROUTE_SRC2_SSIF4 : 01653 /* fall through */ 01654 case SCUX_ROUTE_SRC3_SSIF2 : 01655 /* fall through */ 01656 case SCUX_ROUTE_SRC3_SSIF5 : 01657 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01658 break; 01659 01660 case SCUX_ROUTE_SRC0_MIX_SSIF0 : 01661 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01662 break; 01663 01664 case SCUX_ROUTE_SRC0_MIX_SSIF012 : 01665 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET; 01666 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET; 01667 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK); 01668 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master) 01669 { 01670 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) | 01671 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT)); 01672 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01673 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01674 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01675 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01676 } 01677 else 01678 { 01679 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) | 01680 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT)); 01681 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01682 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01683 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01684 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01685 } 01686 break; 01687 01688 case SCUX_ROUTE_SRC0_MIX_SSIF3 : 01689 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01690 break; 01691 01692 case SCUX_ROUTE_SRC0_MIX_SSIF345 : 01693 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET; 01694 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET; 01695 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK); 01696 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master) 01697 { 01698 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) | 01699 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT)); 01700 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01701 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01702 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01703 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01704 } 01705 else 01706 { 01707 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) | 01708 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT)); 01709 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01710 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01711 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01712 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01713 } 01714 break; 01715 01716 case SCUX_ROUTE_SRC1_MIX_SSIF0 : 01717 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01718 break; 01719 01720 case SCUX_ROUTE_SRC1_MIX_SSIF012 : 01721 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET; 01722 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET; 01723 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK); 01724 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master) 01725 { 01726 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) | 01727 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT)); 01728 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01729 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01730 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01731 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01732 } 01733 else 01734 { 01735 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) | 01736 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT)); 01737 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01738 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01739 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01740 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01741 } 01742 break; 01743 01744 case SCUX_ROUTE_SRC1_MIX_SSIF3 : 01745 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01746 break; 01747 01748 case SCUX_ROUTE_SRC1_MIX_SSIF345 : 01749 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET; 01750 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET; 01751 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK); 01752 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master) 01753 { 01754 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) | 01755 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT)); 01756 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01757 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01758 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01759 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01760 } 01761 else 01762 { 01763 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) | 01764 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT)); 01765 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01766 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01767 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01768 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01769 } 01770 break; 01771 01772 case SCUX_ROUTE_SRC2_MIX_SSIF0 : 01773 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01774 break; 01775 01776 case SCUX_ROUTE_SRC2_MIX_SSIF012 : 01777 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET; 01778 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET; 01779 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK); 01780 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master) 01781 { 01782 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) | 01783 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT)); 01784 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01785 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01786 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01787 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01788 } 01789 else 01790 { 01791 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) | 01792 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT)); 01793 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01794 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01795 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01796 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01797 } 01798 break; 01799 01800 case SCUX_ROUTE_SRC2_MIX_SSIF3 : 01801 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01802 break; 01803 01804 case SCUX_ROUTE_SRC2_MIX_SSIF345 : 01805 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET; 01806 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET; 01807 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK); 01808 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master) 01809 { 01810 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) | 01811 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT)); 01812 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01813 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01814 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01815 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01816 } 01817 else 01818 { 01819 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) | 01820 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT)); 01821 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01822 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01823 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01824 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01825 } 01826 break; 01827 01828 case SCUX_ROUTE_SRC3_MIX_SSIF0 : 01829 /* fall through */ 01830 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01831 break; 01832 01833 case SCUX_ROUTE_SRC3_MIX_SSIF012 : 01834 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET; 01835 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET; 01836 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK); 01837 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master) 01838 { 01839 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) | 01840 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT)); 01841 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01842 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01843 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01844 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01845 } 01846 else 01847 { 01848 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) | 01849 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT)); 01850 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01851 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01852 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01853 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01854 } 01855 break; 01856 01857 case SCUX_ROUTE_SRC3_MIX_SSIF3 : 01858 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET); 01859 break; 01860 01861 case SCUX_ROUTE_SRC3_MIX_SSIF345 : 01862 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET; 01863 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET; 01864 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK); 01865 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master) 01866 { 01867 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) | 01868 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT)); 01869 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01870 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01871 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01872 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE; 01873 } 01874 else 01875 { 01876 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) | 01877 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT)); 01878 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode; 01879 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01880 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode; 01881 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE; 01882 } 01883 break; 01884 01885 default : 01886 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 01887 /* <-IPA R3.5.2 */ 01888 /* NOTREACHED on At the time of a normal performance */ 01889 break; 01890 } 01891 01892 SCUX_SetupFifo(p_scux_info_ch); 01893 SCUX_SetupSrcFunction(p_scux_info_ch); 01894 } 01895 01896 return; 01897 } 01898 01899 /****************************************************************************** 01900 End of function SCUX_SetupSrc 01901 ******************************************************************************/ 01902 01903 /**************************************************************************//** 01904 * Function Name: SCUX_SetupDataPosition 01905 * @brief Audio data position setup. 01906 * 01907 * Description:<br> 01908 * 01909 * @param[in] *p_scux_info_ch : SCUX channel information. 01910 * @retval None. 01911 ******************************************************************************/ 01912 01913 static void SCUX_SetupDataPosition(scux_info_ch_t * const p_scux_info_ch) 01914 { 01915 int_t audio_ch; 01916 uint32_t audio_place = 0; 01917 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 01918 01919 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch)) 01920 { 01921 /* NON_NOTICE_ASSERT: NULL pointer */ 01922 } 01923 else 01924 { 01925 /* set data posion for SRC */ 01926 for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++) 01927 { 01928 audio_place |= (((uint32_t)p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch] & SRCRSEL_CIM_PLACE_N_MASK) << ((uint32_t)audio_ch * SRCRSEL_CIM_PLACE_N_SHIFT)); 01929 } 01930 *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = audio_place; 01931 01932 /* set data position for MIX */ 01933 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 01934 { 01935 if (0U == p_info_drv->shared_info.mix_run_ch) 01936 { 01937 audio_place = 0; 01938 for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++) 01939 { 01940 audio_place |= (((uint32_t)p_info_drv->shared_info.select_out_data_ch[audio_ch] & MIXRSEL_CIM_PLACE_N_MASK) << ((uint32_t)audio_ch * MIXRSEL_CIM_PLACE_N_SHIFT)); 01941 } 01942 *(p_scux_info_ch->p_scux_reg->mixrsel_cim) = audio_place; 01943 } 01944 } 01945 } 01946 01947 return; 01948 } 01949 01950 /****************************************************************************** 01951 End of function SCUX_SetupDataPosition 01952 ******************************************************************************/ 01953 01954 /**************************************************************************//** 01955 * Function Name: SCUX_SetupSrcClk 01956 * @brief SRC clock setup. 01957 * 01958 * Description:<br> 01959 * 01960 * @param[in] *p_scux_info_ch : SCUX channel information. 01961 * @retval None. 01962 ******************************************************************************/ 01963 01964 static void SCUX_SetupSrcClk(scux_info_ch_t * const p_scux_info_ch) 01965 { 01966 uint32_t fdtsel_value = 0; 01967 01968 if (NULL == p_scux_info_ch) 01969 { 01970 /* NON_NOTICE_ASSERT: NULL pointer */ 01971 } 01972 else 01973 { 01974 /* set input timing clock */ 01975 if (false == p_scux_info_ch->src_cfg.mode_sync) 01976 { 01977 /* get value of register setting */ 01978 switch (p_scux_info_ch->src_cfg.input_clk_async) 01979 { 01980 01981 case SCUX_CLK_AUDIO_CLK : 01982 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 01983 FDTSEL_CIM_SCKSEL_AUDIO_CLK_SET); 01984 break; 01985 01986 case SCUX_CLK_AUDIO_X1 : 01987 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 01988 FDTSEL_CIM_SCKSEL_AUDIO_X1_SET); 01989 break; 01990 01991 case SCUX_CLK_MLB_CLK : 01992 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 01993 FDTSEL_CIM_SCKSEL_MLB_CLK_SET); 01994 break; 01995 01996 case SCUX_CLK_USB_X1 : 01997 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 01998 FDTSEL_CIM_SCKSEL_USB_X1_SET); 01999 break; 02000 02001 case SCUX_CLK_CLKP1_2 : 02002 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 02003 FDTSEL_CIM_SCKSEL_CLKP1_2_SET); 02004 break; 02005 02006 case SCUX_CLK_MTU_TIOC3A : 02007 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 02008 FDTSEL_CIM_SCKSEL_MTUSEL2_SET | 02009 FDTSEL_CIM_MTUSEL_SET_TIOC3A); 02010 break; 02011 02012 case SCUX_CLK_MTU_TIOC4A : 02013 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 02014 FDTSEL_CIM_SCKSEL_MTUSEL2_SET | 02015 FDTSEL_CIM_MTUSEL_SET_TIOC4A); 02016 break; 02017 02018 case SCUX_CLK_SSIF0_WS : 02019 fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF0_WS_SET; 02020 break; 02021 02022 case SCUX_CLK_SSIF1_WS : 02023 fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF1_WS_SET; 02024 break; 02025 02026 case SCUX_CLK_SSIF2_WS : 02027 fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF2_WS_SET; 02028 break; 02029 02030 case SCUX_CLK_SSIF3_WS : 02031 fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF3_WS_SET; 02032 break; 02033 02034 case SCUX_CLK_SSIF4_WS : 02035 fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF4_WS_SET; 02036 break; 02037 02038 case SCUX_CLK_SSIF5_WS : 02039 fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF5_WS_SET; 02040 break; 02041 02042 default : 02043 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 02044 /* <-IPA R3.5.2 */ 02045 /* NOTREACHED on At the time of a normal performance */ 02046 break; 02047 } 02048 *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) = fdtsel_value; 02049 } 02050 02051 /* set output timing clock on MIX */ 02052 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 02053 { 02054 p_scux_info_ch->futsel_cim_value = (((0 << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 02055 (((uint32_t)p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num | FUTSEL_CIM_SCKSEL_SSIF0_WS_SET) & FUTSEL_CIM_SCKSEL_MASK)); 02056 *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value; 02057 } 02058 else if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 02059 { 02060 /* set output timing clock on other MIX */ 02061 if (false == p_scux_info_ch->src_cfg.mode_sync) 02062 { 02063 switch (p_scux_info_ch->src_cfg.output_clk_async) 02064 { 02065 case SCUX_CLK_AUDIO_CLK : 02066 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 02067 FUTSEL_CIM_SCKSEL_AUDIO_CLK_SET); 02068 break; 02069 02070 case SCUX_CLK_AUDIO_X1 : 02071 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 02072 FUTSEL_CIM_SCKSEL_AUDIO_X1_SET); 02073 break; 02074 02075 case SCUX_CLK_MLB_CLK : 02076 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 02077 FUTSEL_CIM_SCKSEL_MLB_CLK_SET); 02078 break; 02079 02080 case SCUX_CLK_USB_X1 : 02081 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 02082 FUTSEL_CIM_SCKSEL_USB_X1_SET); 02083 break; 02084 02085 case SCUX_CLK_CLKP1_2 : 02086 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 02087 FUTSEL_CIM_SCKSEL_CLKP1_2_SET); 02088 break; 02089 02090 case SCUX_CLK_MTU_TIOC3A : 02091 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 02092 FUTSEL_CIM_SCKSEL_MTUSEL2_SET | 02093 FUTSEL_CIM_MTUSEL_SET_TIOC3A); 02094 break; 02095 02096 case SCUX_CLK_MTU_TIOC4A : 02097 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 02098 FUTSEL_CIM_SCKSEL_MTUSEL2_SET | 02099 FUTSEL_CIM_MTUSEL_SET_TIOC4A); 02100 break; 02101 02102 case SCUX_CLK_SSIF0_WS : 02103 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF0_WS_SET; 02104 break; 02105 02106 case SCUX_CLK_SSIF1_WS : 02107 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF1_WS_SET; 02108 break; 02109 02110 case SCUX_CLK_SSIF2_WS : 02111 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF2_WS_SET; 02112 break; 02113 02114 case SCUX_CLK_SSIF3_WS : 02115 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF3_WS_SET; 02116 break; 02117 02118 case SCUX_CLK_SSIF4_WS : 02119 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF4_WS_SET; 02120 break; 02121 02122 case SCUX_CLK_SSIF5_WS : 02123 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF5_WS_SET; 02124 break; 02125 02126 default : 02127 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 02128 /* <-IPA R3.5.2 */ 02129 /* NOTREACHED on At the time of a normal performance */ 02130 break; 02131 } 02132 *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value; 02133 } 02134 } 02135 else 02136 { 02137 /* do nothing for SSIF route */ 02138 } 02139 } 02140 02141 return; 02142 } 02143 02144 /****************************************************************************** 02145 End of function SCUX_SetupSrcClk 02146 ******************************************************************************/ 02147 02148 /**************************************************************************//** 02149 * Function Name: SCUX_SetupFifo 02150 * @brief SRC FIFO setup. 02151 * 02152 * Description:<br> 02153 * 02154 * @param[in] *p_scux_info_ch : SCUX channel information. 02155 * @retval None. 02156 ******************************************************************************/ 02157 02158 static void SCUX_SetupFifo(scux_info_ch_t * const p_scux_info_ch) 02159 { 02160 if (NULL == p_scux_info_ch) 02161 { 02162 /* NON_NOTICE_ASSERT: NULL pointer */ 02163 } 02164 else 02165 { 02166 /* set FFD register */ 02167 p_scux_info_ch->p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = p_scux_info_ch->src_cfg.use_ch; 02168 p_scux_info_ch->p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = SCUX_FIFO_REQ_SIZE_128_32; 02169 02170 GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]); 02171 02172 /* set FFU register */ 02173 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 02174 { 02175 p_scux_info_ch->p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = p_scux_info_ch->src_cfg.use_ch; 02176 p_scux_info_ch->p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = SCUX_FIFO_REQ_SIZE_128_32; 02177 02178 GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]); 02179 } 02180 02181 p_scux_info_ch->tx_fifo_total_size = 0; 02182 p_scux_info_ch->rx_fifo_total_size = 0; 02183 } 02184 02185 return; 02186 } 02187 02188 /****************************************************************************** 02189 End of function SCUX_SetupFifo 02190 ******************************************************************************/ 02191 02192 /**************************************************************************//** 02193 * Function Name: SCUX_SetupSrcFunction 02194 * @brief SRC function setup. 02195 * 02196 * Description:<br> 02197 * 02198 * @param[in] *p_scux_info_ch : SCUX channel information. 02199 * @retval None. 02200 ******************************************************************************/ 02201 02202 static void SCUX_SetupSrcFunction(scux_info_ch_t * const p_scux_info_ch) 02203 { 02204 float32_t ifs_calc_value; 02205 uint32_t ifs_value; 02206 uint32_t sadir_value; 02207 uint32_t srccr_value = 0; 02208 uint32_t bfssr_value; 02209 02210 if (NULL == p_scux_info_ch) 02211 { 02212 /* NON_NOTICE_ASSERT: NULL pointer */ 02213 } 02214 else 02215 { 02216 if (false == p_scux_info_ch->src_cfg.src_enable) 02217 { 02218 /* set bypass mode */ 02219 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel)) 02220 { 02221 p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 |= SRCBR_2SRC0_BYPASS_SET; 02222 } 02223 else 02224 { 02225 p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 |= SRCBR_2SRC0_BYPASS_SET; 02226 } 02227 } 02228 else 02229 { 02230 /* calculate sampling rate convert rate parameter */ 02231 ifs_calc_value = ((float32_t)p_scux_info_ch->input_rate / (float32_t)p_scux_info_ch->output_rate); 02232 /* ->IPA R2.4.1 float value is intentionall casted to uint32_t value, because it is resigter value. */ 02233 ifs_value = (uint32_t)(ifs_calc_value * (float32_t)SCUX_RATE_CONVERT_CALC_VALUE); 02234 /* <-IPA R2.4.1 */ 02235 if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len) 02236 { 02237 sadir_value = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & SADIR_2SRC0_CHNUM_MASK) | SADIR_2SRC0_OTBL_SET_16BIT); 02238 } 02239 else 02240 { 02241 sadir_value = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & SADIR_2SRC0_CHNUM_MASK) | SADIR_2SRC0_OTBL_SET_24BIT); 02242 } 02243 02244 /* setting of sync mode bit */ 02245 if (false != p_scux_info_ch->src_cfg.mode_sync) 02246 { 02247 /* set sync mode */ 02248 srccr_value |= SRCCR_2SRC0_SRCMD_SET; 02249 } 02250 else 02251 { 02252 /* set async mode (bit clear) */ 02253 srccr_value &= ~SRCCR_2SRC0_SRCMD_SET; 02254 } 02255 02256 /* setting of buffer for delay mode */ 02257 if (SCUX_DELAY_NORMAL == p_scux_info_ch->src_cfg.delay_mode) 02258 { 02259 /* delay normal setting (bit clear) */ 02260 srccr_value &= ~SRCCR_2SRC0_BUFMD_SET; 02261 } 02262 else 02263 { 02264 /* delay setting (bit set) */ 02265 srccr_value |= SRCCR_2SRC0_BUFMD_SET; 02266 } 02267 02268 /* setting enable bit for wait mode */ 02269 if ((0U == p_scux_info_ch->src_cfg.wait_sample) || (false != p_scux_info_ch->cancel_operate_flag)) 02270 { 02271 /* clear wait mode enable bit when wait value is 0 or cancel operatin on going */ 02272 srccr_value &= ~SRCCR_2SRC0_WATMD_SET; 02273 } 02274 else 02275 { 02276 /* set wait mode enable bit when wait value is other than 0 */ 02277 srccr_value |= SRCCR_2SRC0_WATMD_SET; 02278 } 02279 02280 /* setting buffer value for delay mode */ 02281 if (SCUX_DELAY_NORMAL == p_scux_info_ch->src_cfg.delay_mode) 02282 { 02283 /* set 0 to BFSSR register on delay normal */ 02284 bfssr_value = 0; 02285 } 02286 else if (SCUX_DELAY_LOW_DELAY1 == p_scux_info_ch->src_cfg.delay_mode) 02287 { 02288 /* set delay mode 1 setting to BFSSR register on delay mode1 */ 02289 bfssr_value = ((BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE1 & BFSSR_2SRC0_BUFDATA_MASK) | 02290 (BFSSR_2SRC0_BUFIN_SET_DELAY_MODE & BFSSR_2SRC0_BUFIN_MASK)); 02291 } 02292 else 02293 { 02294 /* set delay mode 2 setting to BFSSR register on delay mode2 */ 02295 bfssr_value = ((BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE2 & BFSSR_2SRC0_BUFDATA_MASK) | 02296 (BFSSR_2SRC0_BUFIN_SET_DELAY_MODE & BFSSR_2SRC0_BUFIN_MASK)); 02297 } 02298 02299 /* set register */ 02300 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel)) 02301 { 02302 p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 &= ~SRCBR_2SRC0_BYPASS_SET; 02303 p_scux_info_ch->p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = sadir_value; 02304 p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 |= IFSCR_2SRC0_INTIFSEN_SET; 02305 p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = ifs_value; 02306 p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = ((ifs_value * (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage) 02307 / SCUX_CALC_MINFS_VALUE); 02308 p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_BASE_VALUE | srccr_value); 02309 p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = bfssr_value; 02310 if (false != p_scux_info_ch->cancel_operate_flag) 02311 { 02312 /* set 0 to register compulsorily when cancel operation on going */ 02313 p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = 0U; 02314 } 02315 else 02316 { 02317 /* set wait value to register when cancel operation on going */ 02318 p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = (p_scux_info_ch->src_cfg.wait_sample & WATSR_2SRC0_WTIME_MASK); 02319 } 02320 } 02321 else 02322 { 02323 p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 &= ~SRCBR_2SRC0_BYPASS_SET; 02324 p_scux_info_ch->p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = sadir_value; 02325 p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 |= IFSCR_2SRC0_INTIFSEN_SET; 02326 p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = ifs_value; 02327 p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = ((ifs_value * (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage) 02328 / SCUX_CALC_MINFS_VALUE); 02329 p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_BASE_VALUE | srccr_value); 02330 p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = bfssr_value; 02331 if (false != p_scux_info_ch->cancel_operate_flag) 02332 { 02333 /* set 0 to register compulsorily when cancel operation on going */ 02334 p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = 0U; 02335 } 02336 else 02337 { 02338 /* set wait value to register when cancel operation on going */ 02339 p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = (p_scux_info_ch->src_cfg.wait_sample & WATSR_2SRC0_WTIME_MASK); 02340 } 02341 } 02342 } 02343 } 02344 02345 return; 02346 } 02347 02348 /****************************************************************************** 02349 End of function SCUX_SetupSrcFunction 02350 ******************************************************************************/ 02351 02352 /**************************************************************************//** 02353 * Function Name: SCUX_SetupDvu 02354 * @brief DVU module setup. 02355 * 02356 * Description:<br> 02357 * 02358 * @param[in] *p_scux_info_ch : SCUX channel information. 02359 * @retval None. 02360 ******************************************************************************/ 02361 02362 void SCUX_SetupDvu(scux_info_ch_t * const p_scux_info_ch) 02363 { 02364 if (NULL == p_scux_info_ch) 02365 { 02366 /* NON_NOTICE_ASSERT: NULL pointer */ 02367 } 02368 else 02369 { 02370 if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len) 02371 { 02372 p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & VADIR_DVU0_CHNUM_MASK) | 02373 VADIR_DVU0_OTBL_SET_16BIT); 02374 } 02375 else 02376 { 02377 p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & VADIR_DVU0_CHNUM_MASK) | 02378 VADIR_DVU0_OTBL_SET_24BIT); 02379 } 02380 02381 if (false == p_scux_info_ch->dvu_cfg.dvu_enable) 02382 { 02383 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 |= DVUBR_DVU0_BYPASS_SET; 02384 } 02385 else 02386 { 02387 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 &= ~DVUBR_DVU0_BYPASS_SET; 02388 } 02389 } 02390 02391 return; 02392 } 02393 02394 /****************************************************************************** 02395 End of function SCUX_SetupDvu 02396 ******************************************************************************/ 02397 02398 /**************************************************************************//** 02399 * Function Name: SCUX_SetupDvuVolume 02400 * @brief DVU volume setup. 02401 * 02402 * Description:<br> 02403 * 02404 * @param[in] *p_scux_info_ch : SCUX channel information. 02405 * @retval None. 02406 ******************************************************************************/ 02407 02408 static void SCUX_SetupDvuVolume(scux_info_ch_t * const p_scux_info_ch) 02409 { 02410 int_t audio_ch; 02411 uint32_t vrctr_value = 0; 02412 02413 if (NULL == p_scux_info_ch) 02414 { 02415 /* NON_NOTICE_ASSERT: NULL pointer */ 02416 } 02417 else 02418 { 02419 /* init DVU module */ 02420 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 &= ~DVUIR_DVU0_INIT_SET; 02421 if (false != p_scux_info_ch->dvu_cfg.dvu_enable) 02422 { 02423 /* set digital volume */ 02424 SCUX_SetDigiVolRegister(p_scux_info_ch); 02425 02426 /* dummy setting to volume ramp */ 02427 for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++) 02428 { 02429 vrctr_value |= (VRCTR_DVU0_VREN_SET << audio_ch); 02430 } 02431 02432 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_VRMD_SET; 02433 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = vrctr_value; 02434 02435 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = 0; 02436 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = 0; 02437 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = 0; 02438 02439 /* set zerocross mute */ 02440 SCUX_SetZerocrossMuteRegister(p_scux_info_ch); 02441 02442 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET; 02443 GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_DVI]); 02444 } 02445 } 02446 02447 return; 02448 } 02449 02450 /****************************************************************************** 02451 End of function SCUX_SetupDvu 02452 ******************************************************************************/ 02453 02454 /**************************************************************************//** 02455 * Function Name: SCUX_SetupMix 02456 * @brief MIX module setup. 02457 * 02458 * Description:<br> 02459 * 02460 * @param[in] *p_scux_info_ch : SCUX channel information. 02461 * @retval None. 02462 ******************************************************************************/ 02463 02464 static void SCUX_SetupMix(scux_info_ch_t * const p_scux_info_ch) 02465 { 02466 int_t scux_ch; 02467 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 02468 02469 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch)) 02470 { 02471 /* NON_NOTICE_ASSERT: NULL pointer */ 02472 } 02473 else 02474 { 02475 /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */ 02476 if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag)) 02477 { 02478 *(p_scux_info_ch->p_scux_reg->madir_mix0_0) = ((uint32_t)p_scux_info_ch->src_cfg.use_ch & MADIR_MIX0_CHNUM_MASK); 02479 *(p_scux_info_ch->p_scux_reg->mixir_mix0_0) &= ~MIXIR_MIX0_INIT_SET; 02480 } 02481 02482 for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++) 02483 { 02484 /* register set on the channel itself which sets up or channel which has already MIX operated */ 02485 if ((scux_ch == p_scux_info_ch->channel) || 02486 (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch)))) 02487 { 02488 SCUX_SetMixVolRegister(scux_ch); 02489 } 02490 } 02491 02492 /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */ 02493 if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag)) 02494 { 02495 *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET; 02496 02497 if (false != p_info_drv->shared_info.mixmode_ramp) 02498 { 02499 /* set ramp mode */ 02500 *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) |= MIXMR_MIX0_MIXMODE_SET; 02501 *(p_scux_info_ch->p_scux_reg->mvpdr_mix0_0) = (uint32_t)((((uint32_t)p_info_drv->shared_info.up_period << MVPDR_MIX0_MXPDUP_SHIFT) & MVPDR_MIX0_MXPDUP_MASK) | 02502 (((uint32_t)p_info_drv->shared_info.down_period << MVPDR_MIX0_MXPDDW_SHIFT) & MVPDR_MIX0_MXPDDW_MASK)); 02503 } 02504 else 02505 { 02506 /* set step mode */ 02507 *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) &= ~MIXMR_MIX0_MIXMODE_SET; 02508 } 02509 02510 *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) |= MDBER_MIX0_MIXDBEN_SET; 02511 } 02512 /* set bit SCUX channel which useing MIX */ 02513 p_info_drv->shared_info.mix_run_ch |= (1U << p_scux_info_ch->channel); 02514 } 02515 02516 return; 02517 } 02518 02519 /****************************************************************************** 02520 End of function SCUX_SetupMix 02521 ******************************************************************************/ 02522 02523 /**************************************************************************//** 02524 * Function Name: SCUX_SetupSsif 02525 * @brief SSIF module setup. 02526 * 02527 * Description:<br> 02528 * 02529 * @param[in] *p_scux_info_ch : SCUX channel information. 02530 * @retval None. 02531 ******************************************************************************/ 02532 02533 void SCUX_SetupSsif(const scux_info_ch_t * const p_scux_info_ch) 02534 { 02535 scux_ssif_info_t *p_set_ssif; 02536 volatile uint8_t dummy_buf; 02537 uint32_t ssif_arrange_num; 02538 uint32_t ssicr_value = 0; 02539 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 02540 int_t was_masked; 02541 02542 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch)) 02543 { 02544 /* NON_NOTICE_ASSERT: NULL pointer */ 02545 } 02546 else 02547 { 02548 for (ssif_arrange_num = 0; ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT; ssif_arrange_num++) 02549 { 02550 switch (ssif_arrange_num) 02551 { 02552 case SCUX_SSIF_CH_ARRANGEMENT1: 02553 p_set_ssif = p_scux_info_ch->p_ssif_info1; 02554 break; 02555 02556 case SCUX_SSIF_CH_ARRANGEMENT2: 02557 p_set_ssif = p_scux_info_ch->p_ssif_info2; 02558 break; 02559 02560 case SCUX_SSIF_CH_ARRANGEMENT3: 02561 p_set_ssif = p_scux_info_ch->p_ssif_info3; 02562 break; 02563 02564 default : 02565 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 02566 /* <-IPA R3.5.2 */ 02567 /* NOTREACHED on At the time of a normal performance */ 02568 break; 02569 } 02570 02571 /* check wherher SSIF pointer 1, 2, 3 is NULL */ 02572 if (NULL != p_set_ssif) 02573 { 02574 /* check SSIF is used on other MIX SCUX channel */ 02575 if (0U == ((uint32_t)p_set_ssif->scux_channel & ~(1U << p_scux_info_ch->channel))) 02576 { 02577 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 02578 { 02579 p_info_drv->shared_info.mix_ssif_ch |= (1U << p_set_ssif->ssif_cfg.ssif_ch_num); 02580 } 02581 02582 #if defined (__ICCARM__) 02583 was_masked = __disable_irq_iar(); 02584 #else 02585 was_masked = __disable_irq(); 02586 #endif 02587 02588 /* input clock */ 02589 CPGSTBCR11 &= (uint8_t)~((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]); 02590 dummy_buf = CPGSTBCR11; 02591 02592 /* SSIF rest */ 02593 CPGSWRSTCR1 |= (uint8_t)gb_cpg_scux_ssif_swrst_bit[p_set_ssif->ssif_cfg.ssif_ch_num]; 02594 dummy_buf = CPGSWRSTCR1; 02595 02596 CPGSWRSTCR1 &= (uint8_t)~((uint8_t)gb_cpg_scux_ssif_swrst_bit[p_set_ssif->ssif_cfg.ssif_ch_num]); 02597 dummy_buf = CPGSWRSTCR1; 02598 02599 if (0 == was_masked) 02600 { 02601 __enable_irq(); 02602 } 02603 02604 SCUX_SetupSsifGpio(p_set_ssif->ssif_cfg.ssif_ch_num); 02605 02606 /* if mode is master mode, WS continue mode is enabled */ 02607 if (false != p_set_ssif->ssif_cfg.mode_master) 02608 { 02609 p_set_ssif->p_scux_ssif_reg->SSITDMR |= SCUX_SSITDMR_CONT_SET; 02610 } 02611 else 02612 { 02613 p_set_ssif->p_scux_ssif_reg->SSITDMR &= ~SCUX_SSITDMR_CONT_SET; 02614 } 02615 02616 /* TDM mode is set according to use_tdm */ 02617 if (false != p_set_ssif->ssif_cfg.use_tdm) 02618 { 02619 p_set_ssif->p_scux_ssif_reg->SSITDMR |= SCUX_SSITDMR_TDM_SET; 02620 } 02621 else 02622 { 02623 p_set_ssif->p_scux_ssif_reg->SSITDMR &= ~SCUX_SSITDMR_TDM_SET; 02624 } 02625 02626 /* over sample clock is set according to select_audio_clk */ 02627 /* if select_audio_clk is 0, set AUDIO_X1 */ 02628 /* if select_audio_clk is 0, set AUDIO_CLK */ 02629 if (false != p_set_ssif->ssif_cfg.select_audio_clk) 02630 { 02631 ssicr_value |= SCUX_SSICR_CKS_SET; 02632 } 02633 else 02634 { 02635 ssicr_value &= ~SCUX_SSICR_CKS_SET; 02636 } 02637 02638 if (NULL == p_scux_info_ch->p_ssif_info2) 02639 { 02640 /* in case single channel, SSIF channel is set as use_ch kinds */ 02641 switch (p_scux_info_ch->src_cfg.use_ch) 02642 { 02643 case SCUX_USE_CH_1: 02644 /* NOTREACHED on At the time of a normal performance */ 02645 break; 02646 02647 case SCUX_USE_CH_2: 02648 /* if TDM mode is used on audio 2ch , error occured in SCUX_CheckSrcParam */ 02649 ssicr_value |= SCUX_SSICR_CHNL_SET_1CH; 02650 break; 02651 02652 case SCUX_USE_CH_4: 02653 ssicr_value |= SCUX_SSICR_CHNL_SET_2CH; 02654 break; 02655 02656 case SCUX_USE_CH_6: 02657 ssicr_value |= SCUX_SSICR_CHNL_SET_3CH; 02658 break; 02659 02660 case SCUX_USE_CH_8: 02661 ssicr_value |= SCUX_SSICR_CHNL_SET_4CH; 02662 break; 02663 02664 default : 02665 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 02666 /* <-IPA R3.5.2 */ 02667 /* NOTREACHED on At the time of a normal performance */ 02668 break; 02669 } 02670 } 02671 else 02672 { 02673 /* in case multi channel, SSIF channel is set 1ch compulsorily */ 02674 ssicr_value |= SCUX_SSICR_CHNL_SET_1CH; 02675 } 02676 02677 /* set data word */ 02678 if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len) 02679 { 02680 ssicr_value |= SCUX_SSICR_DWL_16BIT_SET; 02681 } 02682 else 02683 { 02684 ssicr_value |= SCUX_SSICR_DWL_24BIT_SET; 02685 } 02686 02687 ssicr_value |= ((uint32_t)p_set_ssif->ssif_cfg.system_word << SCUX_SSICR_SWL_SHIFT); 02688 02689 02690 if (SCUX_PIN_MODE_INDEPEND == p_set_ssif->pin_mode) 02691 { 02692 /* in case pin synchronization is slave, SSIF mode is set mode following mode_master */ 02693 if (false != p_set_ssif->ssif_cfg.mode_master) 02694 { 02695 ssicr_value |= (SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET); 02696 } 02697 else 02698 { 02699 ssicr_value &= ~(SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET); 02700 } 02701 } 02702 else 02703 { 02704 /* in case pin synchronization is slave, SSIF mode is set slave mode compulsorily */ 02705 ssicr_value &= ~(SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET); 02706 } 02707 02708 /* set serial bit clock polarity */ 02709 if (false != p_set_ssif->ssif_cfg.sck_polarity_rise) 02710 { 02711 ssicr_value |= SCUX_SSICR_SCKP_SET; 02712 } 02713 else 02714 { 02715 ssicr_value &= ~SCUX_SSICR_SCKP_SET; 02716 } 02717 02718 /* set WS signal polarity */ 02719 if (false != p_set_ssif->ssif_cfg.ws_polarity_high) 02720 { 02721 ssicr_value |= SCUX_SSICR_SWSP_SET; 02722 } 02723 else 02724 { 02725 ssicr_value &= ~SCUX_SSICR_SWSP_SET; 02726 } 02727 02728 /* set serial padding polarity */ 02729 if (false != p_set_ssif->ssif_cfg.padding_high) 02730 { 02731 ssicr_value |= SCUX_SSICR_SPDP_SET; 02732 } 02733 else 02734 { 02735 ssicr_value &= ~SCUX_SSICR_SPDP_SET; 02736 } 02737 02738 /* set serial data align polarity */ 02739 if (false != p_set_ssif->ssif_cfg.serial_data_align) 02740 { 02741 ssicr_value &= ~SCUX_SSICR_SDTA_SET; 02742 } 02743 else 02744 { 02745 ssicr_value |= SCUX_SSICR_SDTA_SET; 02746 } 02747 02748 /* set WS delay setting */ 02749 if (false == p_set_ssif->ssif_cfg.ws_delay) 02750 { 02751 ssicr_value |= SCUX_SSICR_DEL_SET; 02752 } 02753 else 02754 { 02755 ssicr_value &= ~SCUX_SSICR_DEL_SET; 02756 } 02757 02758 /* set SSIF devide rate */ 02759 ssicr_value |= ((uint32_t)p_set_ssif->clk_div << SCUX_SSICR_CKDV_SHIFT); 02760 02761 p_set_ssif->p_scux_ssif_reg->SSICR = ssicr_value; 02762 02763 /* set noise cancel setting */ 02764 if ((false == p_set_ssif->ssif_cfg.mode_master) && (false != p_set_ssif->ssif_cfg.use_noise_cancel)) 02765 { 02766 GPIO.SNCR |= (1U << gb_cpg_scux_ssif_sncr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]); 02767 } 02768 else 02769 { 02770 GPIO.SNCR &= ~(1U << gb_cpg_scux_ssif_sncr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]); 02771 } 02772 } 02773 } 02774 } 02775 } 02776 02777 return; 02778 } 02779 02780 /****************************************************************************** 02781 End of function SCUX_SetupSsif 02782 ******************************************************************************/ 02783 02784 /**************************************************************************//** 02785 * Function Name: SCUX_SetupDma 02786 * @brief DMA setup. 02787 * 02788 * Description:<br> 02789 * 02790 * @param[in] *p_scux_info_ch : SCUX channel information. 02791 * @retval None. 02792 ******************************************************************************/ 02793 02794 int_t SCUX_SetupDma(scux_info_ch_t * const p_scux_info_ch) 02795 { 02796 int_t retval = ESUCCESS; 02797 AIOCB *dma_aio; 02798 uint32_t dmacr_cim_value = 0; 02799 02800 if (NULL == p_scux_info_ch) 02801 { 02802 /* NON_NOTICE_ASSERT: NULL pointer */ 02803 } 02804 else 02805 { 02806 dma_aio = &gb_scux_write_dma_aio[p_scux_info_ch->channel]; 02807 /* dummy data write start */ 02808 dma_aio->aio_sigevent.sigev_notify = SIGEV_THREAD; 02809 dma_aio->aio_sigevent.sigev_value.sival_int = p_scux_info_ch->channel; 02810 if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 02811 { 02812 dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_DirectTxCallBack; 02813 } 02814 else 02815 { 02816 dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_CopyTxCallBack; 02817 } 02818 p_scux_info_ch->dma_tx_setup.resource = p_scux_info_ch->dma_resource_tx; 02819 p_scux_info_ch->dma_tx_setup.direction = DMA_REQ_DES; 02820 02821 switch (p_scux_info_ch->src_cfg.word_len) 02822 { 02823 case SCUX_DATA_LEN_16 : 02824 /* fall through */ 02825 case SCUX_DATA_LEN_16_TO_24 : 02826 p_scux_info_ch->dma_tx_setup.dst_width = DMA_UNIT_2; 02827 p_scux_info_ch->dma_tx_setup.src_width = DMA_UNIT_2; 02828 break; 02829 02830 case SCUX_DATA_LEN_24 : 02831 p_scux_info_ch->dma_tx_setup.dst_width = DMA_UNIT_4; 02832 p_scux_info_ch->dma_tx_setup.src_width = DMA_UNIT_4; 02833 break; 02834 02835 default : 02836 /* NOTREACHED on At the time of a normal performance */ 02837 break; 02838 } 02839 02840 p_scux_info_ch->dma_tx_setup.dst_cnt = DMA_ADDR_FIX; 02841 p_scux_info_ch->dma_tx_setup.src_cnt = DMA_ADDR_INCREMENT; 02842 p_scux_info_ch->dma_tx_setup.p_aio = dma_aio; 02843 02844 /* get read DMA channel */ 02845 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 02846 { 02847 p_scux_info_ch->dma_rx_ch = R_DMA_Alloc(DMA_ALLOC_CH, NULL); 02848 if (EERROR == p_scux_info_ch->dma_rx_ch) 02849 { 02850 retval = EMFILE; 02851 } 02852 else 02853 { 02854 dma_aio = &gb_scux_read_dma_aio[p_scux_info_ch->channel]; 02855 dma_aio->aio_sigevent.sigev_notify = SIGEV_THREAD; 02856 dma_aio->aio_sigevent.sigev_value.sival_int = p_scux_info_ch->channel; 02857 dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_CopyRxCallBack; 02858 p_scux_info_ch->dma_rx_setup.resource = p_scux_info_ch->dma_resource_rx; 02859 p_scux_info_ch->dma_rx_setup.direction = DMA_REQ_SRC; 02860 02861 switch (p_scux_info_ch->src_cfg.word_len) 02862 { 02863 case SCUX_DATA_LEN_16 : 02864 p_scux_info_ch->dma_rx_setup.dst_width = DMA_UNIT_2; 02865 p_scux_info_ch->dma_rx_setup.src_width = DMA_UNIT_2; 02866 break; 02867 02868 case SCUX_DATA_LEN_24 : 02869 /* fall through */ 02870 case SCUX_DATA_LEN_16_TO_24 : 02871 p_scux_info_ch->dma_rx_setup.dst_width = DMA_UNIT_4; 02872 p_scux_info_ch->dma_rx_setup.src_width = DMA_UNIT_4; 02873 break; 02874 02875 default : 02876 /* NOTREACHED on At the time of a normal performance */ 02877 break; 02878 } 02879 02880 p_scux_info_ch->dma_rx_setup.dst_cnt = DMA_ADDR_INCREMENT; 02881 p_scux_info_ch->dma_rx_setup.src_cnt = DMA_ADDR_FIX; 02882 p_scux_info_ch->dma_rx_setup.p_aio = dma_aio; 02883 } 02884 } 02885 02886 if (ESUCCESS == retval) 02887 { 02888 dmacr_cim_value = *(p_scux_info_ch->p_scux_reg->dmacr_cim); 02889 /* set write DMA param */ 02890 dmacr_cim_value |= (DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel); 02891 02892 /* set read DMA param */ 02893 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 02894 { 02895 dmacr_cim_value |= (DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel); 02896 } 02897 } 02898 02899 if (ESUCCESS == retval) 02900 { 02901 *(p_scux_info_ch->p_scux_reg->dmacr_cim) = dmacr_cim_value; 02902 } 02903 } 02904 02905 return retval; 02906 } 02907 02908 /****************************************************************************** 02909 End of function SCUX_SetupDma 02910 ******************************************************************************/ 02911 02912 /**************************************************************************//** 02913 * Function Name: SCUX_InitHw 02914 * @brief Initialize HW . 02915 * 02916 * Description:<br> 02917 * 02918 * @param[in] *p_scux_info_ch : SCUX channel information. 02919 * @retval None. 02920 ******************************************************************************/ 02921 02922 void SCUX_InitHw(scux_info_ch_t * const p_scux_info_ch) 02923 { 02924 scux_ssif_info_t *p_set_ssif; 02925 uint32_t ssif_arrange_num; 02926 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 02927 02928 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch)) 02929 { 02930 /* NON_NOTICE_ASSERT: NULL pointer */ 02931 } 02932 else 02933 { 02934 /* init FFD register */ 02935 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE; 02936 p_scux_info_ch->p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE; 02937 p_scux_info_ch->p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE; 02938 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE; 02939 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE; 02940 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE; 02941 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE; 02942 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE; 02943 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE; 02944 *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE; 02945 *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE; 02946 02947 /* check usc_ch ,and init SRC register */ 02948 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel)) 02949 { 02950 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE; 02951 p_scux_info_ch->p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE; 02952 p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE; 02953 p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE; 02954 p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE; 02955 p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE); 02956 p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE; 02957 p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE; 02958 p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE; 02959 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE; 02960 p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE; 02961 } 02962 else 02963 { 02964 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE; 02965 p_scux_info_ch->p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE; 02966 p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE; 02967 p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE; 02968 p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE; 02969 p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE); 02970 p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE; 02971 p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE; 02972 p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE; 02973 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE; 02974 p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE; 02975 p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE; 02976 } 02977 02978 /* init FFU register */ 02979 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 02980 { 02981 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE; 02982 p_scux_info_ch->p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE; 02983 p_scux_info_ch->p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE; 02984 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE; 02985 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE; 02986 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE; 02987 p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE; 02988 p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE; 02989 *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE; 02990 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_INIT_VALUE; 02991 } 02992 else 02993 { 02994 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE; 02995 p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE; 02996 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE; 02997 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE; 02998 p_scux_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE; 02999 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE; 03000 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE; 03001 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE; 03002 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE; 03003 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE; 03004 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE; 03005 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE; 03006 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE; 03007 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE; 03008 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE; 03009 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE; 03010 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE; 03011 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE; 03012 p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE; 03013 p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE; 03014 03015 for (ssif_arrange_num = 0; ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT; ssif_arrange_num++) 03016 { 03017 switch (ssif_arrange_num) 03018 { 03019 case SCUX_SSIF_CH_ARRANGEMENT1: 03020 p_set_ssif = p_scux_info_ch->p_ssif_info1; 03021 break; 03022 03023 case SCUX_SSIF_CH_ARRANGEMENT2: 03024 p_set_ssif = p_scux_info_ch->p_ssif_info2; 03025 break; 03026 03027 case SCUX_SSIF_CH_ARRANGEMENT3: 03028 p_set_ssif = p_scux_info_ch->p_ssif_info3; 03029 break; 03030 03031 default : 03032 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 03033 /* <-IPA R3.5.2 */ 03034 /* NOTREACHED on At the time of a normal performance */ 03035 break; 03036 } 03037 03038 if (NULL != p_set_ssif) 03039 { 03040 /* check SSIF is used on other MIX SCUX channel */ 03041 if (0U == ((uint32_t)p_set_ssif->scux_channel & ~(1U << p_scux_info_ch->channel))) 03042 { 03043 /* init SSIF register */ 03044 p_set_ssif->p_scux_ssif_reg->SSICR = SCUX_SSICR_INIT_VALUE; 03045 p_set_ssif->p_scux_ssif_reg->SSIFCR = SCUX_SSIFCR_INIT_VALUE; 03046 p_set_ssif->p_scux_ssif_reg->SSIFTDR = SCUX_SSIFTDR_INIT_VALUE; 03047 p_set_ssif->p_scux_ssif_reg->SSITDMR = SCUX_SSITDMR_INIT_VALUE; 03048 p_set_ssif->p_scux_ssif_reg->SSIFCCR = SCUX_SSIFCCR_INIT_VALUE; 03049 p_set_ssif->p_scux_ssif_reg->SSIFCMR = SCUX_SSIFCMR_INIT_VALUE; 03050 } 03051 } 03052 } 03053 } 03054 03055 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 03056 { 03057 /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */ 03058 if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag)) 03059 { 03060 *(p_scux_info_ch->p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE; 03061 *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE; 03062 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_INIT_VALUE; 03063 *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE; 03064 *(p_scux_info_ch->p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE; 03065 *(p_scux_info_ch->p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE; 03066 *(p_scux_info_ch->p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE; 03067 *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE; 03068 *(p_scux_info_ch->p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE; 03069 *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE; 03070 *(p_scux_info_ch->p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE; 03071 } 03072 } 03073 } 03074 03075 return; 03076 } 03077 03078 /****************************************************************************** 03079 End of function SCUX_InitHw 03080 ******************************************************************************/ 03081 03082 /**************************************************************************//** 03083 * Function Name: SCUX_SyncStartHw 03084 * @brief Start Hw on sync mode. 03085 * 03086 * Description:<br> 03087 * 03088 * @param[in] *p_scux_info_ch : SCUX channel information. 03089 * @retval None. 03090 ******************************************************************************/ 03091 03092 void SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch) 03093 { 03094 if (NULL == p_scux_info_ch) 03095 { 03096 /* NON_NOTICE_ASSERT: NULL pointer */ 03097 } 03098 else 03099 { 03100 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 &= ~FFDIR_FFD0_INIT_SET; 03101 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 |= FFDBR_FFD0_BOOT_SET; 03102 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 &= ~FFUIR_FFU0_INIT_SET; 03103 03104 /* check usc_ch ,and init SRC register */ 03105 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel)) 03106 { 03107 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET; 03108 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET); 03109 } 03110 else 03111 { 03112 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET; 03113 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET); 03114 } 03115 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 &= ~IPCIR_IPC0_INIT_SET; 03116 p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 &= ~OPCIR_OPC0_INIT_SET; 03117 03118 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 &= ~SRCIRR_2SRC0_INIT_SET; 03119 03120 GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]); 03121 } 03122 03123 return; 03124 } 03125 03126 /****************************************************************************** 03127 End of function SCUX_SyncStartHw 03128 ******************************************************************************/ 03129 03130 /**************************************************************************//** 03131 * Function Name: SCUX_AsyncStartHw 03132 * @brief Start Hw on async mode. 03133 * 03134 * Description:<br> 03135 * 03136 * @param[in] *p_scux_info_ch : SCUX channel information. 03137 * @retval None. 03138 ******************************************************************************/ 03139 03140 void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch) 03141 { 03142 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 03143 03144 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch)) 03145 { 03146 /* NON_NOTICE_ASSERT: NULL pointer */ 03147 } 03148 else 03149 { 03150 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 &= ~FFDIR_FFD0_INIT_SET; 03151 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 |= FFDBR_FFD0_BOOT_SET; 03152 03153 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 03154 { 03155 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 &= ~FFUIR_FFU0_INIT_SET; 03156 } 03157 03158 /* check usc_ch ,and init SRC register */ 03159 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel)) 03160 { 03161 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET; 03162 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET); 03163 } 03164 else 03165 { 03166 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET; 03167 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET); 03168 } 03169 03170 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 &= ~SRCIRR_2SRC0_INIT_SET; 03171 03172 GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]); 03173 03174 if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 03175 { 03176 SCUX_SetupDvuVolume(p_scux_info_ch); 03177 03178 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 03179 { 03180 SCUX_SetupMix(p_scux_info_ch); 03181 } 03182 } 03183 03184 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 &= ~IPCIR_IPC0_INIT_SET; 03185 p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 &= ~OPCIR_OPC0_INIT_SET; 03186 03187 if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 03188 { 03189 /* check used SSIF is only 1 ch */ 03190 if (NULL == p_scux_info_ch->p_ssif_info2) 03191 { 03192 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR |= SCUX_SSICR_TEN_SET; 03193 } 03194 else 03195 { 03196 if (SCUX_SSIF_CH_0 == p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num) 03197 { 03198 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI012TEN_SET; 03199 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03200 } 03201 else 03202 { 03203 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI345TEN_SET; 03204 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03205 } 03206 } 03207 } 03208 } 03209 03210 return; 03211 } 03212 03213 /****************************************************************************** 03214 End of function SCUX_AsyncStartHw 03215 ******************************************************************************/ 03216 03217 /**************************************************************************//** 03218 * Function Name: SCUX_SyncStopHw 03219 * @brief Stop Hw on sync mode. 03220 * 03221 * Description:<br> 03222 * 03223 * @param[in] *p_scux_info_ch : SCUX channel information. 03224 * @retval None. 03225 ******************************************************************************/ 03226 03227 void SCUX_SyncStopHw(const scux_info_ch_t * const p_scux_info_ch) 03228 { 03229 if (NULL == p_scux_info_ch) 03230 { 03231 /* NON_NOTICE_ASSERT: NULL pointer */ 03232 } 03233 else 03234 { 03235 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET | 03236 UEVMR_FFU0_UEVMOF_SET | 03237 UEVMR_FFU0_UEVMOL_SET); 03238 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]); 03239 03240 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 |= FFUIR_FFU0_INIT_SET; 03241 p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 |= OPCIR_OPC0_INIT_SET; 03242 03243 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET | 03244 DEVMR_FFD0_DEVMOF_SET | 03245 DEVMR_FFD0_DEVMOL_SET | 03246 DEVMR_FFD0_DEVMIUF_SET); 03247 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]); 03248 03249 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 |= FFDIR_FFD0_INIT_SET; 03250 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 |= IPCIR_IPC0_INIT_SET; 03251 03252 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 &= ~FFDBR_FFD0_BOOT_SET; 03253 03254 /* check usc_ch ,and init SRC register */ 03255 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel)) 03256 { 03257 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 |= SRCIR_2SRC0_INIT_SET; 03258 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET | 03259 SEVMR_2SRC0_EVMOF_SET); 03260 } 03261 else 03262 { 03263 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 |= SRCIR_2SRC0_INIT_SET; 03264 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET | 03265 SEVMR_2SRC0_EVMOF_SET); 03266 } 03267 03268 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 |= SRCIRR_2SRC0_INIT_SET; 03269 03270 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]); 03271 } 03272 03273 return; 03274 } 03275 03276 /****************************************************************************** 03277 End of function SCUX_SyncStopHw 03278 ******************************************************************************/ 03279 03280 /**************************************************************************//** 03281 * Function Name: SCUX_AsyncStopHw 03282 * @brief Stop Hw on async mode. 03283 * 03284 * Description:<br> 03285 * 03286 * @param[in] *p_scux_info_ch : SCUX channel information. 03287 * @retval None. 03288 ******************************************************************************/ 03289 03290 void SCUX_AsyncStopHw(scux_info_ch_t * const p_scux_info_ch) 03291 { 03292 uint32_t scux_check_ch; 03293 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 03294 uint32_t ssipmd_mask_ssif2 = 0; 03295 uint32_t ssipmd_mask_ssif3 = 0; 03296 uint32_t ssipmd_shift_ssif2 = 0; 03297 uint32_t ssipmd_shift_ssif3 = 0; 03298 uint32_t ssipmd_reg; 03299 scux_info_ch_t *p_pair_scux_ch; 03300 int_t was_masked; 03301 03302 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch)) 03303 { 03304 /* NON_NOTICE_ASSERT: NULL pointer */ 03305 } 03306 else 03307 { 03308 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 03309 { 03310 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET | 03311 UEVMR_FFU0_UEVMOF_SET | 03312 UEVMR_FFU0_UEVMOL_SET); 03313 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]); 03314 p_scux_info_ch->futsel_cim_value &= ~FUTSEL_CIM_DIVEN_SET; 03315 *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value; 03316 03317 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 |= FFUIR_FFU0_INIT_SET; 03318 } 03319 03320 p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 |= OPCIR_OPC0_INIT_SET; 03321 03322 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 03323 { 03324 p_info_drv->shared_info.mix_run_ch &= ~(1U << p_scux_info_ch->channel); 03325 } 03326 03327 switch (p_scux_info_ch->route_set) 03328 { 03329 case SCUX_ROUTE_SRC0_MEM : 03330 /* fall through */ 03331 case SCUX_ROUTE_SRC1_MEM : 03332 /* fall through */ 03333 case SCUX_ROUTE_SRC2_MEM : 03334 /* fall through */ 03335 case SCUX_ROUTE_SRC3_MEM : 03336 /* do nothing, when mem to mem route is setting */ 03337 break; 03338 03339 case SCUX_ROUTE_SRC0_SSIF0 : 03340 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET; 03341 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03342 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03343 break; 03344 03345 case SCUX_ROUTE_SRC0_SSIF012 : 03346 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET); 03347 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03348 break; 03349 03350 case SCUX_ROUTE_SRC0_SSIF3 : 03351 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET; 03352 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03353 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03354 break; 03355 03356 case SCUX_ROUTE_SRC0_SSIF345 : 03357 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET); 03358 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03359 break; 03360 03361 case SCUX_ROUTE_SRC1_SSIF0 : 03362 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET; 03363 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03364 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03365 break; 03366 03367 case SCUX_ROUTE_SRC1_SSIF012 : 03368 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET); 03369 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03370 break; 03371 03372 case SCUX_ROUTE_SRC1_SSIF3 : 03373 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET; 03374 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03375 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03376 break; 03377 03378 case SCUX_ROUTE_SRC1_SSIF345 : 03379 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET); 03380 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03381 break; 03382 03383 case SCUX_ROUTE_SRC2_SSIF1 : 03384 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI1TX_SET; 03385 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03386 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03387 break; 03388 03389 case SCUX_ROUTE_SRC2_SSIF4 : 03390 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI4TX_SET; 03391 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03392 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03393 break; 03394 03395 case SCUX_ROUTE_SRC3_SSIF2 : 03396 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI2TX_SET; 03397 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03398 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03399 break; 03400 03401 case SCUX_ROUTE_SRC3_SSIF5 : 03402 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI5TX_SET; 03403 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03404 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03405 break; 03406 03407 case SCUX_ROUTE_SRC0_MIX_SSIF0 : 03408 if (0U == p_info_drv->shared_info.mix_run_ch) 03409 { 03410 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET; 03411 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03412 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03413 /* initialized MIX parameter not on going cancel */ 03414 if (false == p_scux_info_ch->cancel_operate_flag) 03415 { 03416 p_info_drv->shared_info.mix_ssif_ch = 0; 03417 } 03418 } 03419 break; 03420 03421 case SCUX_ROUTE_SRC0_MIX_SSIF012 : 03422 if (0U == p_info_drv->shared_info.mix_run_ch) 03423 { 03424 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET); 03425 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03426 /* initialized MIX parameter not on going cancel */ 03427 if (false == p_scux_info_ch->cancel_operate_flag) 03428 { 03429 p_info_drv->shared_info.mix_ssif_ch = 0; 03430 } 03431 } 03432 break; 03433 03434 case SCUX_ROUTE_SRC0_MIX_SSIF3 : 03435 if (0U == p_info_drv->shared_info.mix_run_ch) 03436 { 03437 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET; 03438 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03439 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03440 /* initialized MIX parameter not on going cancel */ 03441 if (false == p_scux_info_ch->cancel_operate_flag) 03442 { 03443 p_info_drv->shared_info.mix_ssif_ch = 0; 03444 } 03445 } 03446 break; 03447 03448 case SCUX_ROUTE_SRC0_MIX_SSIF345 : 03449 if (0U == p_info_drv->shared_info.mix_run_ch) 03450 { 03451 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET); 03452 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03453 /* initialized MIX parameter not on going cancel */ 03454 if (false == p_scux_info_ch->cancel_operate_flag) 03455 { 03456 p_info_drv->shared_info.mix_ssif_ch = 0; 03457 } 03458 } 03459 break; 03460 03461 case SCUX_ROUTE_SRC1_MIX_SSIF0 : 03462 if (0U == p_info_drv->shared_info.mix_run_ch) 03463 { 03464 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET; 03465 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03466 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03467 /* initialized MIX parameter not on going cancel */ 03468 if (false == p_scux_info_ch->cancel_operate_flag) 03469 { 03470 p_info_drv->shared_info.mix_ssif_ch = 0; 03471 } 03472 } 03473 break; 03474 03475 case SCUX_ROUTE_SRC1_MIX_SSIF012 : 03476 if (0U == p_info_drv->shared_info.mix_run_ch) 03477 { 03478 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET); 03479 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03480 /* initialized MIX parameter not on going cancel */ 03481 if (false == p_scux_info_ch->cancel_operate_flag) 03482 { 03483 p_info_drv->shared_info.mix_ssif_ch = 0; 03484 } 03485 } 03486 break; 03487 03488 case SCUX_ROUTE_SRC1_MIX_SSIF3 : 03489 if (0U == p_info_drv->shared_info.mix_run_ch) 03490 { 03491 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET; 03492 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03493 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03494 /* initialized MIX parameter not on going cancel */ 03495 if (false == p_scux_info_ch->cancel_operate_flag) 03496 { 03497 p_info_drv->shared_info.mix_ssif_ch = 0; 03498 } 03499 } 03500 break; 03501 03502 case SCUX_ROUTE_SRC1_MIX_SSIF345 : 03503 if (0U == p_info_drv->shared_info.mix_run_ch) 03504 { 03505 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET); 03506 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03507 /* initialized MIX parameter not on going cancel */ 03508 if (false == p_scux_info_ch->cancel_operate_flag) 03509 { 03510 p_info_drv->shared_info.mix_ssif_ch = 0; 03511 } 03512 } 03513 break; 03514 03515 case SCUX_ROUTE_SRC2_MIX_SSIF0 : 03516 if (0U == p_info_drv->shared_info.mix_run_ch) 03517 { 03518 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET; 03519 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03520 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03521 /* initialized MIX parameter not on going cancel */ 03522 if (false == p_scux_info_ch->cancel_operate_flag) 03523 { 03524 p_info_drv->shared_info.mix_ssif_ch = 0; 03525 } 03526 } 03527 break; 03528 03529 case SCUX_ROUTE_SRC2_MIX_SSIF012 : 03530 if (0U == p_info_drv->shared_info.mix_run_ch) 03531 { 03532 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET); 03533 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03534 /* initialized MIX parameter not on going cancel */ 03535 if (false == p_scux_info_ch->cancel_operate_flag) 03536 { 03537 p_info_drv->shared_info.mix_ssif_ch = 0; 03538 } 03539 } 03540 break; 03541 03542 case SCUX_ROUTE_SRC2_MIX_SSIF3 : 03543 if (0U == p_info_drv->shared_info.mix_run_ch) 03544 { 03545 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET; 03546 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03547 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03548 /* initialized MIX parameter not on going cancel */ 03549 if (false == p_scux_info_ch->cancel_operate_flag) 03550 { 03551 p_info_drv->shared_info.mix_ssif_ch = 0; 03552 } 03553 } 03554 break; 03555 03556 case SCUX_ROUTE_SRC2_MIX_SSIF345 : 03557 if (0U == p_info_drv->shared_info.mix_run_ch) 03558 { 03559 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET); 03560 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03561 /* initialized MIX parameter not on going cancel */ 03562 if (false == p_scux_info_ch->cancel_operate_flag) 03563 { 03564 p_info_drv->shared_info.mix_ssif_ch = 0; 03565 } 03566 } 03567 break; 03568 03569 case SCUX_ROUTE_SRC3_MIX_SSIF0 : 03570 if (0U == p_info_drv->shared_info.mix_run_ch) 03571 { 03572 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET; 03573 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03574 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03575 /* initialized MIX parameter not on going cancel */ 03576 if (false == p_scux_info_ch->cancel_operate_flag) 03577 { 03578 p_info_drv->shared_info.mix_ssif_ch = 0; 03579 } 03580 } 03581 break; 03582 03583 case SCUX_ROUTE_SRC3_MIX_SSIF012 : 03584 if (0U == p_info_drv->shared_info.mix_run_ch) 03585 { 03586 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET); 03587 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03588 /* initialized MIX parameter not on going cancel */ 03589 if (false == p_scux_info_ch->cancel_operate_flag) 03590 { 03591 p_info_drv->shared_info.mix_ssif_ch = 0; 03592 } 03593 } 03594 break; 03595 03596 case SCUX_ROUTE_SRC3_MIX_SSIF3 : 03597 if (0U == p_info_drv->shared_info.mix_run_ch) 03598 { 03599 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET; 03600 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03601 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET; 03602 /* initialized MIX parameter not on going cancel */ 03603 if (false == p_scux_info_ch->cancel_operate_flag) 03604 { 03605 p_info_drv->shared_info.mix_ssif_ch = 0; 03606 } 03607 } 03608 break; 03609 03610 case SCUX_ROUTE_SRC3_MIX_SSIF345 : 03611 if (0U == p_info_drv->shared_info.mix_run_ch) 03612 { 03613 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET); 03614 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value; 03615 /* initialized MIX parameter not on going cancel */ 03616 if (false == p_scux_info_ch->cancel_operate_flag) 03617 { 03618 p_info_drv->shared_info.mix_ssif_ch = 0; 03619 } 03620 } 03621 break; 03622 03623 default : 03624 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 03625 /* <-IPA R3.5.2 */ 03626 /* do nothing, when mem to mem route is setting */ 03627 break; 03628 } 03629 03630 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET | 03631 DEVMR_FFD0_DEVMOF_SET | 03632 DEVMR_FFD0_DEVMOL_SET | 03633 DEVMR_FFD0_DEVMIUF_SET); 03634 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]); 03635 03636 *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) &= ~FDTSEL_CIM_DIVEN_SET; 03637 03638 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 |= FFDIR_FFD0_INIT_SET; 03639 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 |= IPCIR_IPC0_INIT_SET; 03640 03641 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 &= ~FFDBR_FFD0_BOOT_SET; 03642 03643 /* check usc_ch ,and init SRC register */ 03644 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel)) 03645 { 03646 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET | 03647 SEVMR_2SRC0_EVMOF_SET); 03648 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 |= SRCIR_2SRC0_INIT_SET; 03649 } 03650 else 03651 { 03652 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET | 03653 SEVMR_2SRC0_EVMOF_SET); 03654 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 |= SRCIR_2SRC0_INIT_SET; 03655 } 03656 03657 /* if pair channel is stopped, common SRC unit is initialized */ 03658 if (SCUX_CH_0 == p_scux_info_ch->channel) 03659 { 03660 p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_1); 03661 } 03662 else if (SCUX_CH_1 == p_scux_info_ch->channel) 03663 { 03664 p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_0); 03665 } 03666 else if (SCUX_CH_2 == p_scux_info_ch->channel) 03667 { 03668 p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_3); 03669 } 03670 else 03671 { 03672 p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_2); 03673 } 03674 03675 if (NULL != p_pair_scux_ch) 03676 { 03677 if ((SCUX_CH_UNINIT == p_pair_scux_ch->ch_stat) || 03678 (SCUX_CH_INIT == p_pair_scux_ch->ch_stat) || 03679 (SCUX_CH_STOP == p_pair_scux_ch->ch_stat)) 03680 { 03681 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 |= SRCIRR_2SRC0_INIT_SET; 03682 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]); 03683 } 03684 } 03685 else 03686 { 03687 /* NON_NOTICE_ASSERT: NULL pointer */ 03688 } 03689 03690 if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 03691 { 03692 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 |= DVUIR_DVU0_INIT_SET; 03693 03694 p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = 0; 03695 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_DVI]); 03696 03697 scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info1->scux_channel; 03698 scux_check_ch &= ~(1U << p_scux_info_ch->channel); 03699 p_scux_info_ch->p_ssif_info1->scux_channel = (int_t)scux_check_ch; 03700 if (0 == p_scux_info_ch->p_ssif_info1->scux_channel) 03701 { 03702 #if defined (__ICCARM__) 03703 was_masked = __disable_irq_iar(); 03704 #else 03705 was_masked = __disable_irq(); 03706 #endif 03707 03708 /* clock mask on all used SSIF channel shutdown */ 03709 CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num]); 03710 03711 if (0 == was_masked) 03712 { 03713 __enable_irq(); 03714 } 03715 } 03716 03717 if (NULL != p_scux_info_ch->p_ssif_info2) 03718 { 03719 /* clear multiple SSIF setting */ 03720 scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info2->scux_channel; 03721 scux_check_ch &= ~(1U << p_scux_info_ch->channel); 03722 p_scux_info_ch->p_ssif_info2->scux_channel = (int_t)scux_check_ch; 03723 p_scux_info_ch->p_ssif_info2->pin_mode = p_scux_info_ch->p_ssif_info2->pin_mode_backup; 03724 03725 switch (p_scux_info_ch->p_ssif_info2->ssif_cfg.ssif_ch_num) 03726 { 03727 case SCUX_SSIF_CH_1 : 03728 ssipmd_mask_ssif2 = SSIPMD_CIM_SSI1PMD_MASK; 03729 ssipmd_shift_ssif2 = SSIPMD_CIM_SSI1PMD_SHIFT; 03730 break; 03731 03732 case SCUX_SSIF_CH_2 : 03733 ssipmd_mask_ssif2 = SSIPMD_CIM_SSI2PMD_MASK; 03734 ssipmd_shift_ssif2 = SSIPMD_CIM_SSI2PMD_SHIFT; 03735 break; 03736 03737 case SCUX_SSIF_CH_3 : 03738 ssipmd_mask_ssif2 = SSIPMD_CIM_SSI3PMD_MASK; 03739 ssipmd_shift_ssif2 = SSIPMD_CIM_SSI3PMD_SHIFT; 03740 break; 03741 03742 case SCUX_SSIF_CH_4 : 03743 ssipmd_mask_ssif2 = SSIPMD_CIM_SSI4PMD_MASK; 03744 ssipmd_shift_ssif2 = SSIPMD_CIM_SSI4PMD_SHIFT; 03745 break; 03746 03747 case SCUX_SSIF_CH_5 : 03748 ssipmd_mask_ssif2 = SSIPMD_CIM_SSI5PMD_MASK; 03749 ssipmd_shift_ssif2 = SSIPMD_CIM_SSI5PMD_SHIFT; 03750 break; 03751 03752 default : 03753 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 03754 /* <-IPA R3.5.2 */ 03755 /* NOTREACHED on At the time of a normal performance */ 03756 break; 03757 } 03758 03759 scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info3->scux_channel; 03760 scux_check_ch &= ~(1U << p_scux_info_ch->channel); 03761 p_scux_info_ch->p_ssif_info3->scux_channel = (int_t)scux_check_ch; 03762 p_scux_info_ch->p_ssif_info3->pin_mode = p_scux_info_ch->p_ssif_info3->pin_mode_backup; 03763 03764 switch (p_scux_info_ch->p_ssif_info3->ssif_cfg.ssif_ch_num) 03765 { 03766 case SCUX_SSIF_CH_1 : 03767 ssipmd_mask_ssif3 = SSIPMD_CIM_SSI1PMD_MASK; 03768 ssipmd_shift_ssif3 = SSIPMD_CIM_SSI1PMD_SHIFT; 03769 break; 03770 03771 case SCUX_SSIF_CH_2 : 03772 ssipmd_mask_ssif3 = SSIPMD_CIM_SSI2PMD_MASK; 03773 ssipmd_shift_ssif3 = SSIPMD_CIM_SSI2PMD_SHIFT; 03774 break; 03775 03776 case SCUX_SSIF_CH_3 : 03777 ssipmd_mask_ssif3 = SSIPMD_CIM_SSI3PMD_MASK; 03778 ssipmd_shift_ssif3 = SSIPMD_CIM_SSI3PMD_SHIFT; 03779 break; 03780 03781 case SCUX_SSIF_CH_4 : 03782 ssipmd_mask_ssif3 = SSIPMD_CIM_SSI4PMD_MASK; 03783 ssipmd_shift_ssif3 = SSIPMD_CIM_SSI4PMD_SHIFT; 03784 break; 03785 03786 case SCUX_SSIF_CH_5 : 03787 ssipmd_mask_ssif3 = SSIPMD_CIM_SSI5PMD_MASK; 03788 ssipmd_shift_ssif3 = SSIPMD_CIM_SSI5PMD_SHIFT; 03789 break; 03790 03791 default : 03792 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 03793 /* <-IPA R3.5.2 */ 03794 /* NOTREACHED on At the time of a normal performance */ 03795 break; 03796 } 03797 ssipmd_reg = *(p_scux_info_ch->p_scux_reg->ssipmd_cim); 03798 ssipmd_reg &= ~(ssipmd_mask_ssif2 | ssipmd_mask_ssif3); 03799 03800 /* ->IPA R2.4.1 Even if pinmode and ssipmd_shift are max value, omission dose not occur. */ 03801 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) = (ssipmd_reg | 03802 ((uint32_t)p_scux_info_ch->p_ssif_info2->pin_mode << ssipmd_shift_ssif2) | 03803 ((uint32_t)p_scux_info_ch->p_ssif_info3->pin_mode << ssipmd_shift_ssif3)); 03804 /* <-IPA R2.4.1 */ 03805 03806 if (0 == p_scux_info_ch->p_ssif_info2->scux_channel) 03807 { 03808 #if defined (__ICCARM__) 03809 was_masked = __disable_irq_iar(); 03810 #else 03811 was_masked = __disable_irq(); 03812 #endif 03813 03814 /* clock mask */ 03815 CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info2->ssif_cfg.ssif_ch_num]); 03816 03817 if (0 == was_masked) 03818 { 03819 __enable_irq(); 03820 } 03821 } 03822 03823 if (0 == p_scux_info_ch->p_ssif_info3->scux_channel) 03824 { 03825 #if defined (__ICCARM__) 03826 was_masked = __disable_irq_iar(); 03827 #else 03828 was_masked = __disable_irq(); 03829 #endif 03830 03831 CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info3->ssif_cfg.ssif_ch_num]); 03832 03833 if (0 == was_masked) 03834 { 03835 __enable_irq(); 03836 } 03837 } 03838 03839 if (false == p_scux_info_ch->cancel_operate_flag) 03840 { 03841 /* set NULL to SSIF information when cancel not on going */ 03842 p_scux_info_ch->p_ssif_info2 = NULL; 03843 p_scux_info_ch->p_ssif_info3 = NULL; 03844 } 03845 } 03846 if (false == p_scux_info_ch->cancel_operate_flag) 03847 { 03848 /* set NULL to SSIF information when cancel not on going */ 03849 p_scux_info_ch->p_ssif_info1 = NULL; 03850 } 03851 03852 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK)) 03853 { 03854 if (0U == p_info_drv->shared_info.mix_run_ch) 03855 { 03856 *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) |= MIXIR_MIX0_INIT_SET; 03857 *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET; 03858 } 03859 } 03860 } 03861 } 03862 03863 return; 03864 } 03865 03866 /****************************************************************************** 03867 End of function SCUX_AsyncStopHw 03868 ******************************************************************************/ 03869 03870 /**************************************************************************//** 03871 * Function Name: SCUX_SetDigiVolRegister 03872 * @brief Set digital volume register. 03873 * 03874 * Description:<br> 03875 * 03876 * @param[in] *p_scux_info_ch : SCUX channel information. 03877 * @retval none. 03878 ******************************************************************************/ 03879 03880 void SCUX_SetDigiVolRegister(const scux_info_ch_t * const p_scux_info_ch) 03881 { 03882 int_t audio_ch; 03883 03884 if (NULL == p_scux_info_ch) 03885 { 03886 /* NON_NOTICE_ASSERT: NULL pointer */ 03887 } 03888 else 03889 { 03890 /* check and set digital volume */ 03891 if (false != p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable) 03892 { 03893 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_VVMD_SET; 03894 03895 for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++) 03896 { 03897 switch (audio_ch) 03898 { 03899 case SCUX_AUDIO_CH_0 : 03900 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch]; 03901 break; 03902 03903 case SCUX_AUDIO_CH_1 : 03904 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch]; 03905 break; 03906 03907 case SCUX_AUDIO_CH_2 : 03908 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch]; 03909 break; 03910 03911 case SCUX_AUDIO_CH_3 : 03912 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch]; 03913 break; 03914 03915 case SCUX_AUDIO_CH_4 : 03916 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch]; 03917 break; 03918 03919 case SCUX_AUDIO_CH_5 : 03920 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch]; 03921 break; 03922 03923 case SCUX_AUDIO_CH_6 : 03924 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch]; 03925 break; 03926 03927 case SCUX_AUDIO_CH_7 : 03928 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch]; 03929 break; 03930 03931 default : 03932 /* ->IPA R3.5.2 Nothing is being processed intentionally. */ 03933 /* <-IPA R3.5.2 */ 03934 /* NOTREACHED on At the time of a normal performance */ 03935 break; 03936 } 03937 } 03938 } 03939 else 03940 { 03941 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 &= ~DVUCR_DVU0_VVMD_SET; 03942 } 03943 } 03944 03945 return; 03946 } 03947 03948 /****************************************************************************** 03949 End of function SCUX_SetDigiVolRegister 03950 ******************************************************************************/ 03951 03952 /**************************************************************************//** 03953 * Function Name: SCUX_SetRampVolRegister 03954 * @brief Set ramp volume register. 03955 * 03956 * Description:<br> 03957 * 03958 * @param[in] *p_scux_info_ch : SCUX channel information. 03959 * @retval none. 03960 ******************************************************************************/ 03961 03962 void SCUX_SetRampVolRegister(scux_info_ch_t * const p_scux_info_ch) 03963 { 03964 int_t audio_ch; 03965 uint32_t vrctr_value = 0; 03966 03967 if (NULL == p_scux_info_ch) 03968 { 03969 /* NON_NOTICE_ASSERT: NULL pointer */ 03970 } 03971 else 03972 { 03973 for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++) 03974 { 03975 if (false != p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch]) 03976 { 03977 vrctr_value |= (VRCTR_DVU0_VREN_SET << audio_ch); 03978 } 03979 else 03980 { 03981 vrctr_value &= ~(VRCTR_DVU0_VREN_SET << audio_ch); 03982 } 03983 } 03984 03985 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = vrctr_value; 03986 03987 if (false == p_scux_info_ch->restart_ramp_flag) 03988 { 03989 /* set ramp paramteter to register when timming isn't restart after cancel */ 03990 /* ->IPA R2.4.1 Even if each parameters are max value, omission dose not occur. */ 03991 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = (uint32_t)((((uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period << VRPDR_DVU0_VRPDUP_SHIFT) & VRPDR_DVU0_VRPDUP_MASK) | 03992 (((uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period << VRPDR_DVU0_VRPDDW_SHIFT) & VRPDR_DVU0_VRPDDW_MASK)); 03993 /* <-IPA R2.4.1 */ 03994 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time & VRWTR_DVU0_VRWT_MASK); 03995 } 03996 else 03997 { 03998 /* set fatest ramp parameter to register when timming is restart after cancel */ 03999 /* ->IPA R2.4.1 Even if each parameters are max value, omission dose not occur. */ 04000 /* when restart ,volume is changed immedeatly */ 04001 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = (uint32_t)((((uint32_t)SCUX_DVU_TIME_128DB_1STEP << VRPDR_DVU0_VRPDUP_SHIFT) & VRPDR_DVU0_VRPDUP_MASK) | 04002 (((uint32_t)SCUX_DVU_TIME_128DB_1STEP << VRPDR_DVU0_VRPDDW_SHIFT) & VRPDR_DVU0_VRPDDW_MASK)); 04003 /* <-IPA R2.4.1 */ 04004 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = 0U; 04005 p_scux_info_ch->restart_ramp_flag = false; 04006 } 04007 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol; 04008 } 04009 04010 return; 04011 } 04012 04013 /****************************************************************************** 04014 End of function SCUX_SetRampVolRegister 04015 ******************************************************************************/ 04016 04017 /**************************************************************************//** 04018 * Function Name: SCUX_SetZerocrossMuteRegister 04019 * @brief Set zerocross mute register. 04020 * 04021 * Description:<br> 04022 * 04023 * @param[in] *p_scux_info_ch : SCUX channel information. 04024 * @retval None. 04025 ******************************************************************************/ 04026 04027 void SCUX_SetZerocrossMuteRegister(const scux_info_ch_t * const p_scux_info_ch) 04028 { 04029 int_t audio_ch; 04030 uint32_t zcmcr_value = 0; 04031 uint32_t vevmr_value = 0; 04032 04033 if (NULL == p_scux_info_ch) 04034 { 04035 /* NON_NOTICE_ASSERT: NULL pointer */ 04036 } 04037 else 04038 { 04039 for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++) 04040 { 04041 if (false != p_scux_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch]) 04042 { 04043 zcmcr_value |= (ZCMCR_DVU0_ZCEN_SET << audio_ch); 04044 vevmr_value |= (VEVMR_DVU0_VEVMZCM_SET << audio_ch); 04045 } 04046 else 04047 { 04048 zcmcr_value &= ~(ZCMCR_DVU0_ZCEN_SET << audio_ch); 04049 vevmr_value &= ~(VEVMR_DVU0_VEVMZCM_SET << audio_ch); 04050 } 04051 } 04052 p_scux_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = zcmcr_value; 04053 p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = vevmr_value; 04054 04055 if (0U != zcmcr_value) 04056 { 04057 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_ZCMD_SET; 04058 } 04059 else 04060 { 04061 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 &= ~DVUCR_DVU0_ZCMD_SET; 04062 } 04063 04064 } 04065 04066 return; 04067 } 04068 04069 /****************************************************************************** 04070 End of function SCUX_SetZerocrossMuteRegister 04071 ******************************************************************************/ 04072 04073 /**************************************************************************//** 04074 * Function Name: SCUX_SetMixVolRegister 04075 * @brief Set MIX volume register. 04076 * 04077 * Description:<br> 04078 * 04079 * @param[in] channel : SCUX channel number. 04080 * @retval None. 04081 ******************************************************************************/ 04082 04083 void SCUX_SetMixVolRegister(const int_t channel) 04084 { 04085 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance(); 04086 scux_info_ch_t * const p_scux_info_ch = SCUX_GetDrvChInfo(channel); 04087 04088 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch)) 04089 { 04090 /* NON_NOTICE_ASSERT: NULL pointer */ 04091 } 04092 else 04093 { 04094 *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET; 04095 *(p_scux_info_ch->p_scux_reg->mdb_n_r_mix0_0) = p_info_drv->shared_info.mix_vol[channel]; 04096 *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) |= MDBER_MIX0_MIXDBEN_SET; 04097 } 04098 04099 return; 04100 } 04101 04102 /****************************************************************************** 04103 End of function SCUX_SetMixVolRegister 04104 ******************************************************************************/ 04105 04106 /**************************************************************************//** 04107 * Function Name: SCUX_DMA_RxCallBack 04108 * @brief Read request callback (mem to mem). 04109 * 04110 * Description:<br> 04111 * 04112 * @param[in] param : SCUX channel number. 04113 * @retval None. 04114 ******************************************************************************/ 04115 04116 static void SCUX_DMA_CopyRxCallBack(union sigval const param) 04117 { 04118 dma_trans_data_t dma_address_param; 04119 int_t retval; 04120 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int); 04121 04122 if (NULL == p_info_ch) 04123 { 04124 /* NON_NOTICE_ASSERT: NULL pointer */ 04125 } 04126 else 04127 { 04128 if (NULL != p_info_ch->p_rx_aio) 04129 { 04130 p_info_ch->p_rx_aio->aio_return = (ssize_t)p_info_ch->p_rx_aio->aio_nbytes; 04131 ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio); 04132 p_info_ch->first_rx_flag = false; 04133 } 04134 04135 p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size; 04136 p_info_ch->dma_rx_current_size = 0; 04137 p_info_ch->p_rx_aio = ahf_removehead(&p_info_ch->rx_que); 04138 04139 if (NULL != p_info_ch->p_rx_aio) 04140 { 04141 /* set nect data read */ 04142 dma_address_param.src_addr = (void *)p_info_ch->p_scux_reg->dmatu_n_cim; 04143 dma_address_param.dst_addr = (void *)(p_info_ch->p_rx_aio->aio_buf); 04144 dma_address_param.count = p_info_ch->p_rx_aio->aio_nbytes; 04145 04146 retval = R_DMA_Start(p_info_ch->dma_rx_ch, &dma_address_param, NULL); 04147 if (ESUCCESS != retval) 04148 { 04149 /* NON_NOTICE_ASSERT: NULL pointer */ 04150 } 04151 else 04152 { 04153 p_info_ch->dma_rx_current_size = dma_address_param.count; 04154 } 04155 } 04156 else 04157 { 04158 switch (p_info_ch->ch_stat) 04159 { 04160 case SCUX_CH_UNINIT : 04161 /* fall through */ 04162 case SCUX_CH_INIT : 04163 /* fall through */ 04164 case SCUX_CH_STOP : 04165 /* fall through */ 04166 case SCUX_CH_TRANS_IDLE : 04167 /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */ 04168 break; 04169 04170 case SCUX_CH_TRANS_RD : 04171 p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE; 04172 break; 04173 04174 case SCUX_CH_TRANS_WR : 04175 /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */ 04176 break; 04177 04178 case SCUX_CH_TRANS_RDWR : 04179 p_info_ch->ch_stat = SCUX_CH_TRANS_WR; 04180 break; 04181 04182 case SCUX_CH_STOP_WAIT : 04183 p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE; 04184 break; 04185 04186 case SCUX_CH_STOP_WAIT_IDLE : 04187 /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */ 04188 break; 04189 04190 default : 04191 /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */ 04192 break; 04193 } 04194 } 04195 } 04196 } 04197 04198 /****************************************************************************** 04199 End of function SCUX_DMA_CopyRxCallBack 04200 ******************************************************************************/ 04201 04202 /**************************************************************************//** 04203 * Function Name: SCUX_DMA_CommonTxNextDummyData 04204 * @brief Set next dummy data for flush (mem to mem , SSIF direct route). 04205 * 04206 * Description:<br> 04207 * 04208 * @param[in] *p_scux_info_ch : SCUX channel information. 04209 * @retval None. 04210 ******************************************************************************/ 04211 04212 static void SCUX_DMA_CommonTxNextDummyData(scux_info_ch_t * const p_info_ch) 04213 { 04214 int_t retval; 04215 04216 if (NULL == p_info_ch) 04217 { 04218 /* NON_NOTICE_ASSERT: NULL pointer */ 04219 } 04220 else 04221 { 04222 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size; 04223 p_info_ch->dma_tx_current_size = 0; 04224 04225 retval = SCUX_FlushWriteStart(p_info_ch); 04226 if (ESUCCESS != retval) 04227 { 04228 /* NON_NOTICE_ASSERT: DMA operation failed */ 04229 } 04230 } 04231 } 04232 04233 /****************************************************************************** 04234 End of function SCUX_DMA_CommonTxNextDummyData 04235 ******************************************************************************/ 04236 04237 /**************************************************************************//** 04238 * Function Name: SCUX_DMA_CopyTxEndFlush 04239 * @brief End of flush operation (mem to mem route). 04240 * 04241 * Description:<br> 04242 * 04243 * @param[in] *p_scux_info_ch : SCUX channel information. 04244 * @retval None. 04245 ******************************************************************************/ 04246 04247 static void SCUX_DMA_CopyTxEndFlush(scux_info_ch_t * const p_info_ch) 04248 { 04249 int_t retval; 04250 int_t dma_ercd; 04251 uint32_t tx_remain_size = 0; 04252 uint32_t rx_remain_size = 0; 04253 04254 if (NULL == p_info_ch) 04255 { 04256 /* NON_NOTICE_ASSERT: NULL pointer */ 04257 } 04258 else 04259 { 04260 /* finish send dummy data process, and SCUX stop process */ 04261 retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd); 04262 /* It isn't an error even if error code is EBADF, because it is already stopped. */ 04263 if ((ESUCCESS != retval) && (EBADF != dma_ercd)) 04264 { 04265 /* NON_NOTICE_ASSERT: DMA operation failed */ 04266 } 04267 04268 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size; 04269 p_info_ch->dma_tx_current_size = 0; 04270 04271 retval = R_DMA_Cancel(p_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd); 04272 /* It isn't an error even if error code is EBADF, because it is already stopped. */ 04273 if ((ESUCCESS != retval) && (EBADF != dma_ercd)) 04274 { 04275 /* NON_NOTICE_ASSERT: DMA operation failed */ 04276 } 04277 else 04278 { 04279 retval = R_DMA_Free(p_info_ch->dma_rx_ch, NULL); 04280 if (ESUCCESS != retval) 04281 { 04282 /* NON_NOTICE_ASSERT: DMA operation failed */ 04283 } 04284 } 04285 p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size; 04286 p_info_ch->dma_rx_current_size = 0; 04287 04288 if (NULL != p_info_ch->p_rx_aio) 04289 { 04290 /* in case NULL, dummy data read */ 04291 p_info_ch->p_rx_aio->aio_return = (ssize_t)(p_info_ch->p_rx_aio->aio_nbytes - rx_remain_size); 04292 ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio); 04293 } 04294 ahf_cancelall(&p_info_ch->rx_que); 04295 p_info_ch->p_rx_aio = NULL; 04296 04297 SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, rx_remain_size); 04298 04299 if (false != p_info_ch->src_cfg.mode_sync) 04300 { 04301 SCUX_SyncStopHw(p_info_ch); 04302 } 04303 else 04304 { 04305 SCUX_AsyncStopHw(p_info_ch); 04306 } 04307 04308 p_info_ch->ch_stat = SCUX_CH_STOP; 04309 if (NULL != p_info_ch->p_flush_callback) 04310 { 04311 p_info_ch->p_flush_callback(ESUCCESS); 04312 } 04313 } 04314 } 04315 04316 /****************************************************************************** 04317 End of function SCUX_DMA_CopyTxEndFlush 04318 ******************************************************************************/ 04319 04320 /**************************************************************************//** 04321 * Function Name: SCUX_DMA_CopyTxNextRemainData 04322 * @brief Set next remain data for flush (mem to mem route). 04323 * 04324 * Description:<br> 04325 * 04326 * @param[in] *p_scux_info_ch : SCUX channel information. 04327 * @retval None. 04328 ******************************************************************************/ 04329 04330 static void SCUX_DMA_CopyTxNextRemainData(scux_info_ch_t * const p_info_ch) 04331 { 04332 dma_trans_data_t dma_address_param; 04333 int_t retval; 04334 04335 if (NULL == p_info_ch) 04336 { 04337 /* NON_NOTICE_ASSERT: NULL pointer */ 04338 } 04339 else 04340 { 04341 /* send remain tx data prcess for flush */ 04342 if (NULL != p_info_ch->p_tx_aio) 04343 { 04344 p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes; 04345 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio); 04346 } 04347 04348 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size; 04349 p_info_ch->dma_tx_current_size = 0; 04350 p_info_ch->p_tx_aio = ahf_removehead(&p_info_ch->tx_que); 04351 04352 if (NULL == p_info_ch->p_tx_aio) 04353 { 04354 retval = SCUX_FlushWriteStart(p_info_ch); 04355 if (ESUCCESS != retval) 04356 { 04357 /* NON_NOTICE_ASSERT: DMA operation failed */ 04358 } 04359 } 04360 else 04361 { 04362 dma_address_param.src_addr = (void *)(p_info_ch->p_tx_aio->aio_buf); 04363 dma_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim; 04364 dma_address_param.count = p_info_ch->p_tx_aio->aio_nbytes; 04365 04366 retval = R_DMA_Start(p_info_ch->dma_tx_ch, &dma_address_param, NULL); 04367 if (ESUCCESS != retval) 04368 { 04369 /* NON_NOTICE_ASSERT: DMA operation failed */ 04370 } 04371 else 04372 { 04373 p_info_ch->dma_tx_current_size = dma_address_param.count; 04374 } 04375 } 04376 } 04377 } 04378 04379 /****************************************************************************** 04380 End of function SCUX_DMA_CopyTxNextRemainData 04381 ******************************************************************************/ 04382 04383 /**************************************************************************//** 04384 * Function Name: SCUX_DMA_CopyTxNextData 04385 * @brief Set next data for normal operation (mem to mem route). 04386 * 04387 * Description:<br> 04388 * 04389 * @param[in] *p_scux_info_ch : SCUX channel information. 04390 * @retval None. 04391 ******************************************************************************/ 04392 04393 static void SCUX_DMA_CopyTxNextData(scux_info_ch_t * const p_info_ch) 04394 { 04395 dma_trans_data_t dma_address_param; 04396 int_t retval; 04397 04398 if (NULL == p_info_ch) 04399 { 04400 /* NON_NOTICE_ASSERT: NULL pointer */ 04401 } 04402 else 04403 { 04404 /* normal send process */ 04405 if (NULL != p_info_ch->p_tx_aio) 04406 { 04407 p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes; 04408 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio); 04409 } 04410 04411 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size; 04412 p_info_ch->dma_tx_current_size = 0; 04413 p_info_ch->p_tx_aio = ahf_removehead(&p_info_ch->tx_que); 04414 04415 if (NULL != p_info_ch->p_tx_aio) 04416 { 04417 dma_address_param.src_addr = (void *)(p_info_ch->p_tx_aio->aio_buf); 04418 dma_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim; 04419 dma_address_param.count = p_info_ch->p_tx_aio->aio_nbytes; 04420 04421 retval = R_DMA_Start(p_info_ch->dma_tx_ch, &dma_address_param, NULL); 04422 if (ESUCCESS != retval) 04423 { 04424 /* NON_NOTICE_ASSERT: NULL pointer */ 04425 } 04426 else 04427 { 04428 p_info_ch->dma_tx_current_size = dma_address_param.count; 04429 } 04430 } 04431 else 04432 { 04433 switch (p_info_ch->ch_stat) 04434 { 04435 case SCUX_CH_UNINIT : 04436 /* fall through */ 04437 case SCUX_CH_INIT : 04438 /* fall through */ 04439 case SCUX_CH_STOP : 04440 /* fall through */ 04441 case SCUX_CH_TRANS_IDLE : 04442 /* fall through */ 04443 case SCUX_CH_TRANS_RD : 04444 /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */ 04445 break; 04446 04447 case SCUX_CH_TRANS_WR : 04448 p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE; 04449 break; 04450 04451 case SCUX_CH_TRANS_RDWR : 04452 p_info_ch->ch_stat = SCUX_CH_TRANS_RD; 04453 break; 04454 04455 case SCUX_CH_STOP_WAIT : 04456 /* fall through */ 04457 case SCUX_CH_STOP_WAIT_IDLE : 04458 /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */ 04459 break; 04460 04461 default : 04462 /* NOTREACHED on At the time of a normal performance */ 04463 break; 04464 } 04465 } 04466 } 04467 } 04468 04469 /****************************************************************************** 04470 End of function SCUX_DMA_CopyTxNextData 04471 ******************************************************************************/ 04472 04473 /**************************************************************************//** 04474 * Function Name: SCUX_DMA_CopyTxCallBack 04475 * @brief Write request callback (mem to mem route). 04476 * 04477 * Description:<br> 04478 * 04479 * @param[in] param : SCUX channel number. 04480 * @retval None. 04481 ******************************************************************************/ 04482 04483 static void SCUX_DMA_CopyTxCallBack(union sigval const param) 04484 { 04485 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int); 04486 04487 if (NULL == p_info_ch) 04488 { 04489 /* NON_NOTICE_ASSERT: NULL pointer */ 04490 } 04491 else 04492 { 04493 if ((SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) || (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat)) 04494 { 04495 /* data flush process */ 04496 if (false != p_info_ch->tx_dummy_run_flag) 04497 { 04498 if (0U == p_info_ch->flush_stop_size) 04499 { 04500 SCUX_DMA_CopyTxEndFlush(p_info_ch); 04501 } 04502 else 04503 { 04504 SCUX_DMA_CommonTxNextDummyData(p_info_ch); 04505 } 04506 } 04507 else 04508 { 04509 SCUX_DMA_CopyTxNextRemainData(p_info_ch); 04510 } 04511 } 04512 else 04513 { 04514 SCUX_DMA_CopyTxNextData(p_info_ch); 04515 } 04516 } 04517 } 04518 04519 /****************************************************************************** 04520 End of function SCUX_DMA_CopyTxCallBack 04521 ******************************************************************************/ 04522 04523 /**************************************************************************//** 04524 * Function Name: SCUX_DMA_DirectTxEndFlush 04525 * @brief End of flush operation (SSIF Direct route). 04526 * 04527 * Description:<br> 04528 * 04529 * @param[in] *p_scux_info_ch : SCUX channel information. 04530 * @retval None. 04531 ******************************************************************************/ 04532 04533 static void SCUX_DMA_DirectTxEndFlush(scux_info_ch_t * const p_info_ch) 04534 { 04535 int_t retval; 04536 int_t dma_ercd; 04537 uint32_t tx_remain_size = 0; 04538 04539 if (NULL == p_info_ch) 04540 { 04541 /* NON_NOTICE_ASSERT: NULL pointer */ 04542 } 04543 else 04544 { 04545 /* finish send dummy data process, and SCUX stop process */ 04546 retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd); 04547 /* It isn't an error even if error code is EBADF, because it is already stopped. */ 04548 if ((ESUCCESS != retval) && (EBADF != dma_ercd)) 04549 { 04550 /* NON_NOTICE_ASSERT: NULL pointer */ 04551 } 04552 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size; 04553 p_info_ch->dma_tx_current_size = 0; 04554 04555 SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, 0); 04556 04557 SCUX_AsyncStopHw(p_info_ch); 04558 04559 p_info_ch->ch_stat = SCUX_CH_STOP; 04560 if (NULL != p_info_ch->p_flush_callback) 04561 { 04562 p_info_ch->p_flush_callback(ESUCCESS); 04563 } 04564 } 04565 } 04566 04567 /****************************************************************************** 04568 End of function SCUX_DMA_DirectTxEndFlush 04569 ******************************************************************************/ 04570 04571 /**************************************************************************//** 04572 * Function Name: SCUX_DMA_DirectTxNextRemainData 04573 * @brief Set next remain data for flush (SSIF Direct route). 04574 * 04575 * Description:<br> 04576 * 04577 * @param[in] *p_scux_info_ch : SCUX channel information. 04578 * @retval None. 04579 ******************************************************************************/ 04580 04581 static void SCUX_DMA_DirectTxNextRemainData(scux_info_ch_t * const p_info_ch) 04582 { 04583 dma_trans_data_t dma_next_address_param; 04584 int_t retval; 04585 04586 if (NULL == p_info_ch) 04587 { 04588 /* NON_NOTICE_ASSERT: NULL pointer */ 04589 } 04590 else 04591 { 04592 if (NULL != p_info_ch->p_tx_aio) 04593 { 04594 p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes; 04595 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio); 04596 p_info_ch->first_tx_flag = false; 04597 } 04598 04599 04600 /* send remain tx data prcess for flush */ 04601 p_info_ch->p_tx_aio = p_info_ch->p_tx_next_aio; 04602 p_info_ch->p_tx_next_aio = ahf_removehead(&p_info_ch->tx_que); 04603 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size; 04604 p_info_ch->dma_tx_current_size = 0; 04605 04606 if ((NULL != p_info_ch->p_tx_next_aio) && (NULL != p_info_ch->p_tx_aio)) 04607 { 04608 /* 1. 04609 * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio isn't NULL. 04610 * Since, Next DMA is effective and p_info_ch->p_tx_aio is set to Next DMA 04611 * The vaule of p_info_ch->dma_tx_current_size is updated to the value of 04612 * p_info_ch->dma_tx_next_size. 04613 * The vaule of p_info_ch->dma_tx_next_size is updated to the value of DMA size 04614 * on Next DMA. 04615 */ 04616 dma_next_address_param.src_addr = (void *)(p_info_ch->p_tx_next_aio->aio_buf); 04617 dma_next_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim; 04618 dma_next_address_param.count = p_info_ch->p_tx_next_aio->aio_nbytes; 04619 04620 retval = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_next_address_param, NULL); 04621 if (ESUCCESS != retval) 04622 { 04623 /* NON_NOTICE_ASSERT: NULL pointer */ 04624 } 04625 else 04626 { 04627 p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size; 04628 p_info_ch->dma_tx_next_size = dma_next_address_param.count; 04629 } 04630 } 04631 else if ((NULL != p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio)) 04632 { 04633 /* 2. 04634 * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio is NULL. 04635 * Since, Next DMA is Stopped and DMA is restarted to p_info_ch->p_tx_aio 04636 * The vaule of p_info_ch->dma_tx_current_size and p_info_ch->dma_tx_next_size 04637 * are updated to restart DMA value. 04638 */ 04639 retval = SCUX_DirectWriteStart(p_info_ch, p_info_ch->p_tx_next_aio); 04640 if (ESUCCESS != retval) 04641 { 04642 /* NON_NOTICE_ASSERT: NULL pointer */ 04643 } 04644 } 04645 else if ((NULL == p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio)) 04646 { 04647 /* 3. 04648 * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio is NULL. 04649 * Since, all request finished, and flush data write start. 04650 * The vaule of p_info_ch->dma_tx_current_size is updated to flush DMA value. 04651 */ 04652 04653 retval = SCUX_FlushWriteStart(p_info_ch); 04654 if (ESUCCESS != retval) 04655 { 04656 /* NON_NOTICE_ASSERT: DMA operation failed */ 04657 } 04658 } 04659 else 04660 { 04661 /* 4. 04662 * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio isn't NULL. 04663 * Since, Nothing new aio request, and processing of 2. or 3. is performed 04664 * in the next loop. 04665 * The vaule of p_info_ch->dma_tx_current_size is updated to the value of 04666 * p_info_ch->dma_tx_next_size. 04667 */ 04668 04669 p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size; 04670 p_info_ch->dma_tx_next_size = 0; 04671 } 04672 } 04673 } 04674 04675 /****************************************************************************** 04676 End of function SCUX_DMA_DirectTxNextRemainData 04677 ******************************************************************************/ 04678 04679 /**************************************************************************//** 04680 * Function Name: SCUX_DMA_DirectTxNextData 04681 * @brief Set next data normal operation (SSIF Direct route). 04682 * 04683 * Description:<br> 04684 * 04685 * @param[in] *p_scux_info_ch : SCUX channel information. 04686 * @retval None. 04687 ******************************************************************************/ 04688 04689 static void SCUX_DMA_DirectTxNextData(scux_info_ch_t * const p_info_ch) 04690 { 04691 dma_trans_data_t dma_next_address_param; 04692 int_t retval; 04693 04694 if (NULL == p_info_ch) 04695 { 04696 /* NON_NOTICE_ASSERT: NULL pointer */ 04697 } 04698 else 04699 { 04700 if (NULL != p_info_ch->p_tx_aio) 04701 { 04702 p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes; 04703 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio); 04704 p_info_ch->first_tx_flag = false; 04705 } 04706 04707 /* normal send process */ 04708 p_info_ch->p_tx_aio = p_info_ch->p_tx_next_aio; 04709 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size; 04710 p_info_ch->p_tx_next_aio = ahf_removehead(&p_info_ch->tx_que); 04711 04712 if ((NULL != p_info_ch->p_tx_next_aio) && (NULL != p_info_ch->p_tx_aio)) 04713 { 04714 /* 1. 04715 * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio isn't NULL. 04716 . * Since, Next DMA is effective and p_info_ch->p_tx_aio is set to Next DMA 04717 * The vaule of p_info_ch->dma_tx_current_size is updated to the value of 04718 * p_info_ch->dma_tx_next_size. 04719 * The vaule of p_info_ch->dma_tx_next_size is updated to the value of DMA size 04720 * on Next DMA. 04721 */ 04722 dma_next_address_param.src_addr = (void *)(p_info_ch->p_tx_next_aio->aio_buf); 04723 dma_next_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim; 04724 dma_next_address_param.count = p_info_ch->p_tx_next_aio->aio_nbytes; 04725 04726 retval = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_next_address_param, NULL); 04727 if (ESUCCESS != retval) 04728 { 04729 /* NON_NOTICE_ASSERT: NULL pointer */ 04730 } 04731 else 04732 { 04733 p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size; 04734 p_info_ch->dma_tx_next_size = dma_next_address_param.count; 04735 } 04736 } 04737 else if ((NULL != p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio)) 04738 { 04739 /* 2. 04740 * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio is NULL. 04741 * Since, Next DMA is Stopped and DMA is restarted to p_info_ch->p_tx_aio 04742 * The vaule of p_info_ch->dma_tx_current_size and p_info_ch->dma_tx_next_size 04743 * are updated to restart DMA value. 04744 */ 04745 04746 retval = SCUX_DirectWriteStart(p_info_ch, p_info_ch->p_tx_next_aio); 04747 if (ESUCCESS != retval) 04748 { 04749 /* NON_NOTICE_ASSERT: NULL pointer */ 04750 } 04751 } 04752 else if((NULL == p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio)) 04753 { 04754 /* 3. 04755 * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio is NULL. 04756 * Since, all request finished, and status is made to change IDLE. 04757 * The vaule of p_info_ch->dma_tx_current_size is updated to 0. 04758 */ 04759 p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE; 04760 p_info_ch->dma_tx_current_size = 0; 04761 04762 } 04763 else 04764 { 04765 /* 4. 04766 * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio isn't NULL. 04767 * Since, Nothing new aio request, and processing of 2. or 3. is performed 04768 * in the next loop. 04769 * The vaule of p_info_ch->dma_tx_current_size is updated to the value of 04770 * p_info_ch->dma_tx_next_size. 04771 */ 04772 04773 p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size; 04774 p_info_ch->dma_tx_next_size = 0; 04775 } 04776 } 04777 } 04778 04779 /****************************************************************************** 04780 End of function SCUX_DMA_DirectTxNextData 04781 ******************************************************************************/ 04782 04783 /**************************************************************************//** 04784 * Function Name: SCUX_DMA_DirectTxCallBack 04785 * @brief Write request callback (SSIF Direct route). 04786 * 04787 * Description:<br> 04788 * 04789 * @param[in] param : SCUX channel number. 04790 * @retval None. 04791 ******************************************************************************/ 04792 04793 static void SCUX_DMA_DirectTxCallBack(union sigval const param) 04794 { 04795 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int); 04796 04797 if (NULL == p_info_ch) 04798 { 04799 /* NON_NOTICE_ASSERT: NULL pointer */ 04800 } 04801 else 04802 { 04803 if (SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) 04804 { 04805 /* data flush process */ 04806 if (false != p_info_ch->tx_dummy_run_flag) 04807 { 04808 if (0U == p_info_ch->flush_stop_size) 04809 { 04810 SCUX_DMA_DirectTxEndFlush(p_info_ch); 04811 } 04812 else 04813 { 04814 SCUX_DMA_CommonTxNextDummyData(p_info_ch); 04815 } 04816 } 04817 else 04818 { 04819 SCUX_DMA_DirectTxNextRemainData(p_info_ch); 04820 } 04821 } 04822 else 04823 { 04824 SCUX_DMA_DirectTxNextData(p_info_ch); 04825 } 04826 } 04827 } 04828 04829 /****************************************************************************** 04830 End of function SCUX_DMA_DirextTxCallBack 04831 ******************************************************************************/ 04832
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