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RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.
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scux.h
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00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer 00021 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 /**************************************************************************//** 00024 * @file scux.h 00025 * $Rev: 993 $ 00026 * $Date:: 2014-07-22 09:54:45 +0900#$ 00027 * @brief Sample driver internal header 00028 ******************************************************************************/ 00029 00030 #ifndef SCUX_H 00031 #define SCUX_H 00032 00033 /****************************************************************************** 00034 Includes <System Includes>, "Project Includes" 00035 ******************************************************************************/ 00036 00037 #include "scux_if.h" 00038 #include "scux_int.h" 00039 #include "aioif.h" 00040 #include "iodefine.h" 00041 #include "Renesas_RZ_A1.h" 00042 #include "dma_if.h" 00043 #include "bsp_drv_cmn.h" 00044 00045 /****************************************************************************** 00046 Macro definitions 00047 ******************************************************************************/ 00048 00049 /* SCUX Register Set Value */ 00050 /* Init Value */ 00051 /* IPC */ 00052 #define IPCIR_IPC0_INIT_VALUE (0x00000001U) 00053 #define IPSLR_IPC0_INIT_VALUE (0x00000000U) 00054 /* OPC */ 00055 #define OPCIR_OPC0_INIT_VALUE (0x00000001U) 00056 #define OPSLR_OPC0_INIT_VALUE (0x00000000U) 00057 /* FFD */ 00058 #define FFDIR_FFD0_INIT_VALUE (0x00000001U) 00059 #define FDAIR_FFD0_INIT_VALUE (0x00000000U) 00060 #define DRQSR_FFD0_INIT_VALUE (0x00000000U) 00061 #define FFDPR_FFD0_INIT_VALUE (0x00000000U) 00062 #define FFDBR_FFD0_INIT_VALUE (0x00000000U) 00063 #define DEVMR_FFD0_INIT_VALUE (0x00000000U) 00064 #define DEVCR_FFD0_INIT_VALUE (0x00000000U) 00065 /* FFU */ 00066 #define FFUIR_FFU0_INIT_VALUE (0x00000001U) 00067 #define FUAIR_FFU0_INIT_VALUE (0x00000000U) 00068 #define URQSR_FFU0_INIT_VALUE (0x00000000U) 00069 #define FFUPR_FFU0_INIT_VALUE (0x00000000U) 00070 #define UEVMR_FFU0_INIT_VALUE (0x00000000U) 00071 #define UEVCR_FFU0_INIT_VALUE (0x00000000U) 00072 /* SRC */ 00073 #define SRCIR_2SRC0_INIT_VALUE (0x00000001U) 00074 #define SADIR_2SRC0_INIT_VALUE (0x00000000U) 00075 #define SRCBR_2SRC0_INIT_VALUE (0x00000000U) 00076 #define IFSCR_2SRC0_INIT_VALUE (0x00000000U) 00077 #define IFSVR_2SRC0_INIT_VALUE (0x00000000U) 00078 #define SRCCR_2SRC0_INIT_VALUE (0x00000000U) 00079 #define MNFSR_2SRC0_INIT_VALUE (0x00000000U) 00080 #define BFSSR_2SRC0_INIT_VALUE (0x00000000U) 00081 #define WATSR_2SRC0_INIT_VALUE (0x00000000U) 00082 #define SEVMR_2SRC0_INIT_VALUE (0x00000000U) 00083 #define SEVCR_2SRC0_INIT_VALUE (0x00000000U) 00084 #define SRCIRR_2SRC0_INIT_VALUE (0x00000001U) 00085 /* DVU */ 00086 #define DVUIR_DVU0_INIT_VALUE (0x00000001U) 00087 #define VADIR_DVU0_INIT_VALUE (0x00000000U) 00088 #define DVUBR_DVU0_INIT_VALUE (0x00000000U) 00089 #define DVUCR_DVU0_INIT_VALUE (0x00000000U) 00090 #define ZCMCR_DVU0_INIT_VALUE (0x00000000U) 00091 #define VRCTR_DVU0_INIT_VALUE (0x00000000U) 00092 #define VRPDR_DVU0_INIT_VALUE (0x00000000U) 00093 #define VRDBR_DVU0_INIT_VALUE (0x00000000U) 00094 #define VRWTR_DVU0_INIT_VALUE (0x00000000U) 00095 #define VOL_N_R_DVU0_INIT_VALUE (0x00000000U) 00096 #define DVUER_DVU0_INIT_VALUE (0x00000000U) 00097 #define VEVMR_DVU0_INIT_VALUE (0x00000000U) 00098 #define VEVCR_DVU0_INIT_VALUE (0x00000000U) 00099 /* MIX */ 00100 #define MIXIR_MIX0_0_INIT_VALUE (0x00000001U) 00101 #define MADIR_MIX0_0_INIT_VALUE (0x00000000U) 00102 #define MIXBR_MIX0_0_INIT_VALUE (0x00000000U) 00103 #define MIXMR_MIX0_0_INIT_VALUE (0x00000000U) 00104 #define MVPDR_MIX0_0_INIT_VALUE (0x00000000U) 00105 #define MDB_N_R_MIX0_0_INIT_VALUE (0x00000000U) 00106 #define MDBER_MIX0_0_INIT_VALUE (0x00000000U) 00107 /* CIM */ 00108 #define SWRSR_CIM_INIT_VALUE (0x00000001U) 00109 #define DMACR_CIM_INIT_VALUE (0x00000000U) 00110 #define SSIRSEL_CIM_INIT_VALUE (0x00000000U) 00111 #define FDTSEL_CIM_INIT_VALUE (0x00000000U) 00112 #define FUTSEL_CIM_INIT_VALUE (0x00000000U) 00113 #define SSIPMD_CIM_INIT_VALUE (0x00000000U) 00114 #define SSICTRL_CIM_INIT_VALUE (0x00000000U) 00115 #define SRCRSEL_CIM_INIT_VALUE (0x76543210U) 00116 #define MIXRSEL_CIM_INIT_VALUE (0x76543210U) 00117 00118 /* SCUX bit value & mask & fixed setting */ 00119 00120 /* IPC */ 00121 #define IPCIR_IPC0_INIT_SET (1U << 0) 00122 00123 #define IPSLR_IPC_PASS_SEL_MASK (7U << 0) 00124 #define IPSLR_IPC_PASS_SEL_SET_ASYNC (3U << 0) 00125 #define IPSLR_IPC_PASS_SEL_SET_SYNC (4U << 0) 00126 00127 /* OPC */ 00128 #define OPCIR_OPC0_INIT_SET (1U << 0) 00129 00130 #define OPSLR_OPC_PASS_SEL_MASK (7U << 0) 00131 #define OPSLR_OPC_PASS_SEL_SET_DIRECT (1U << 0) 00132 #define OPSLR_OPC_PASS_SEL_SET_ASYNC (3U << 0) 00133 #define OPSLR_OPC_PASS_SEL_SET_SYNC (4U << 0) 00134 00135 /* FFD */ 00136 #define FFDIR_FFD0_INIT_SET (1U << 0) 00137 00138 #define FDAIR_FFD0_CHNUM_MASK (0x0FU << 0) 00139 00140 #define DRQSR_FFD0_SIZE_MASK (0x0FU << 0) 00141 00142 #define FFDPR_FFD0_PASS_SET_ASYNC (1U << 0) 00143 #define FFDPR_FFD0_PASS_SET_SYNC (2U << 0) 00144 00145 #define FFDBR_FFD0_BOOT_SET (1U << 0) 00146 00147 #define DEVMR_FFD0_DEVMUF_SET (1U << 31) 00148 #define DEVMR_FFD0_DEVMOF_SET (1U << 30) 00149 #define DEVMR_FFD0_DEVMOL_SET (1U << 29) 00150 #define DEVMR_FFD0_DEVMIUF_SET (1U << 28) 00151 #define DEVMR_FFD0_DEVMRQ_SET (1U << 15) 00152 00153 #define DEVCR_FFD0_DEVCUF_MASK (1U << 31) 00154 #define DEVCR_FFD0_DEVCUF_SET (1U << 31) 00155 #define DEVCR_FFD0_DEVCOF_MASK (1U << 30) 00156 #define DEVCR_FFD0_DEVCOF_SET (1U << 30) 00157 #define DEVCR_FFD0_DEVCOL_MASK (1U << 29) 00158 #define DEVCR_FFD0_DEVCOL_SET (1U << 29) 00159 #define DEVCR_FFD0_DEVCIUF_MASK (1U << 28) 00160 #define DEVCR_FFD0_DEVCIUF_SET (1U << 28) 00161 #define DEVCR_FFD0_DEVCRQ_MASK (1U << 15) 00162 #define DEVCR_FFD0_DEVCRQ_SET (1U << 15) 00163 00164 /* FFU */ 00165 #define FFUIR_FFU0_INIT_SET (1U << 0) 00166 00167 #define FUAIR_FFU0_CHNUM_MASK (0x0FU << 0) 00168 00169 #define URQSR_FFU0_SIZE_MASK (0x0FU << 0) 00170 00171 #define FFUPR_FFU0_PASS_SET_ASYNC (1U << 0) 00172 #define FFUPR_FFU0_PASS_SET_SYNC (2U << 0) 00173 00174 #define UEVMR_FFU0_UEVMUF_SET (1U << 31) 00175 #define UEVMR_FFU0_UEVMOF_SET (1U << 30) 00176 #define UEVMR_FFU0_UEVMOL_SET (1U << 29) 00177 #define UEVMR_FFU0_UEVMRQ_SET (1U << 15) 00178 00179 #define UEVCR_FFU0_UEVCUF_MASK (1U << 31) 00180 #define UEVCR_FFU0_UEVCUF_SET (1U << 31) 00181 #define UEVCR_FFU0_UEVCOF_MASK (1U << 30) 00182 #define UEVCR_FFU0_UEVCOF_SET (1U << 30) 00183 #define UEVCR_FFU0_UEVCOL_MASK (1U << 29) 00184 #define UEVCR_FFU0_UEVCOL_SET (1U << 29) 00185 #define UEVCR_FFU0_UEVCRQ_MASK (1U << 15) 00186 #define UEVCR_FFU0_UEVCRQ_SET (1U << 15) 00187 00188 /* SRC */ 00189 #define SRCIR_2SRC0_INIT_SET (1U << 0) 00190 00191 #define SADIR_2SRC0_CHNUM_MASK (0x0FU << 0) 00192 #define SADIR_2SRC0_OTBL_MASK (0x1FU << 16) 00193 #define SADIR_2SRC0_OTBL_SET_24BIT (0x0U << 16) 00194 #define SADIR_2SRC0_OTBL_SET_16BIT (0x8U << 16) 00195 00196 #define SRCBR_2SRC0_BYPASS_SET (0x1U << 0) 00197 00198 #define IFSCR_2SRC0_INTIFSEN_SET (0x1U << 0) 00199 00200 #define IFSVR_2SRC0_INTIFS_MASK (0x0FFFFFFFU << 0) 00201 00202 #define SRCCR_2SRC0_BASE_VALUE (0x00010110U) 00203 #define SRCCR_2SRC0_WATMD_SET (1U << 20) 00204 #define SRCCR_2SRC0_BUFMD_SET (1U << 12) 00205 #define SRCCR_2SRC0_SRCMD_SET (1U << 0) 00206 00207 #define MNFSR_2SRC0_MINFS_MASK (0x0FFFFFFFU << 0) 00208 00209 #define BFSSR_2SRC0_BUFDATA_MASK (0x3FFU << 16) 00210 #define BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE1 (0x80U << 16) 00211 #define BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE2 (0x40U << 16) 00212 #define BFSSR_2SRC0_BUFIN_MASK (0x0FU << 0) 00213 #define BFSSR_2SRC0_BUFIN_SET_DELAY_MODE (0x05U << 0) 00214 00215 #define WATSR_2SRC0_WTIME_MASK (0xFFFFFFU << 0) 00216 00217 #define SEVMR_2SRC0_EVMUF_SET (1U << 31) 00218 #define SEVMR_2SRC0_EVMOF_SET (1U << 30) 00219 00220 #define SEVCR_2SRC0_EVCUF_MASK (1U << 31) 00221 #define SEVCR_2SRC0_EVCUF_SET (1U << 31) 00222 #define SEVCR_2SRC0_EVCOF_MASK (1U << 30) 00223 #define SEVCR_2SRC0_EVCOF_SET (1U << 30) 00224 00225 #define SRCIRR_2SRC0_INIT_SET (1U << 0) 00226 00227 #define DVUIR_DVU0_INIT_SET (1U << 0) 00228 00229 #define VADIR_DVU0_OTBL_MASK (0x1FU << 16) 00230 #define VADIR_DVU0_OTBL_SET_24BIT (0x0U << 16) 00231 #define VADIR_DVU0_OTBL_SET_16BIT (0x8U << 16) 00232 #define VADIR_DVU0_CHNUM_MASK (0x0FU << 0) 00233 00234 #define DVUBR_DVU0_BYPASS_SET (0x1U << 0) 00235 00236 #define DVUCR_DVU0_VVMD_SET (1U << 8) 00237 #define DVUCR_DVU0_VRMD_SET (1U << 4) 00238 #define DVUCR_DVU0_ZCMD_SET (1U << 0) 00239 00240 #define ZCMCR_DVU0_ZCEN_SET (1U << 0) 00241 00242 #define VRCTR_DVU0_VREN_SET (1U << 0) 00243 00244 #define VRPDR_DVU0_VRPDUP_SHIFT (8U) 00245 #define VRPDR_DVU0_VRPDUP_MASK (0x1F << VRPDR_DVU0_VRPDUP_SHIFT) 00246 #define VRPDR_DVU0_VRPDDW_SHIFT (0U) 00247 #define VRPDR_DVU0_VRPDDW_MASK (0x1F << VRPDR_DVU0_VRPDDW_SHIFT) 00248 00249 #define VRDBR_DVU0_VRDB_MASK (0x3FFU << 0) 00250 00251 #define VRWTR_DVU0_VRWT_MASK (0xFFFFFFU << 0) 00252 00253 #define VOL_N_R_DVU_VOLVAL_MASK (0xFFFFFFU << 0) 00254 00255 #define DVUER_DVU0_DVUEN_SET (1U << 0) 00256 00257 #define DVUSR_DVU0_ZSTS_N_SHIFT (16U) 00258 #define DVUSR_DVU0_ZSTS_N_MASK (1U << DVUSR_DVU0_ZSTS_N_SHIFT) 00259 #define DVUSR_DVU0_ZSTS_MASK (0xFFU << DVUSR_DVU0_ZSTS_N_SHIFT) 00260 #define DVUSR_DVU0_VRSTS_MASK (7U << 0) 00261 #define DVUSR_DVU0_VRSTS_VOL_FIX (4U << 0) 00262 00263 #define VEVMR_DVU0_VEVMZCM_SET (1U << 24) 00264 00265 #define VEVCR_DVU0_VEVCZCM_SET (1U << 24) 00266 00267 /* MIX */ 00268 #define MIXIR_MIX0_INIT_SET (1U << 0) 00269 00270 #define MADIR_MIX0_CHNUM_MASK (0x0FU << 0) 00271 00272 #define MIXMR_MIX0_MIXMODE_SET (1U << 0) 00273 00274 #define MVPDR_MIX0_MXPDUP_SHIFT (8U) 00275 #define MVPDR_MIX0_MXPDUP_MASK (0x0FU << MVPDR_MIX0_MXPDUP_SHIFT) 00276 #define MVPDR_MIX0_MXPDDW_SHIFT (0U) 00277 #define MVPDR_MIX0_MXPDDW_MASK (0x0FU << MVPDR_MIX0_MXPDDW_SHIFT) 00278 00279 #define MDB_N_R_MIX0_MIXDB_N_MASK (0x3FFU <<0) 00280 00281 #define MDBER_MIX0_MIXDBEN_SET (1U << 0) 00282 00283 #define MIXSR_MIX0_MIXSTS_MASK (3U << 0) 00284 00285 /* CIM */ 00286 #define SWRSR_CIM_SWRST_SET (1U << 0) 00287 00288 #define DMACR_CIM_DMAMDFFU_N_SET (1U << 4) 00289 #define DMACR_CIM_DMAMDFFD_N_SET (1U << 0) 00290 00291 #define SSIRSEL_CIM_SOSEL5_MASK (3U << 20) 00292 #define SSIRSEL_CIM_SOSEL5_SRC3_SET (0U << 20) 00293 #define SSIRSEL_CIM_SOSEL5_SRC1_SET (1U << 20) 00294 #define SSIRSEL_CIM_SOSEL5_SRC0_SET (2U << 20) 00295 #define SSIRSEL_CIM_SOSEL5_MIX_SET (3U << 20) 00296 #define SSIRSEL_CIM_SOSEL4_MASK (3U << 16) 00297 #define SSIRSEL_CIM_SOSEL4_SRC2_SET (0U << 16) 00298 #define SSIRSEL_CIM_SOSEL4_SRC1_SET (1U << 16) 00299 #define SSIRSEL_CIM_SOSEL4_SRC0_SET (2U << 16) 00300 #define SSIRSEL_CIM_SOSEL4_MIX_SET (3U << 16) 00301 #define SSIRSEL_CIM_SOSEL3_MASK (3U << 12) 00302 #define SSIRSEL_CIM_SOSEL3_SRC1_SET (0U << 12) 00303 #define SSIRSEL_CIM_SOSEL3_SRC0_SET (1U << 12) 00304 #define SSIRSEL_CIM_SOSEL3_MIX_SET (2U << 12) 00305 #define SSIRSEL_CIM_SOSEL2_MASK (3U << 8) 00306 #define SSIRSEL_CIM_SOSEL2_SRC3_SET (0U << 8) 00307 #define SSIRSEL_CIM_SOSEL2_SRC0_SET (1U << 8) 00308 #define SSIRSEL_CIM_SOSEL2_SRC1_SET (2U << 8) 00309 #define SSIRSEL_CIM_SOSEL2_MIX_SET (3U << 8) 00310 #define SSIRSEL_CIM_SOSEL1_MASK (3U << 4) 00311 #define SSIRSEL_CIM_SOSEL1_SRC2_SET (0U << 4) 00312 #define SSIRSEL_CIM_SOSEL1_SRC0_SET (1U << 4) 00313 #define SSIRSEL_CIM_SOSEL1_SRC1_SET (2U << 4) 00314 #define SSIRSEL_CIM_SOSEL1_MIX_SET (3U << 4) 00315 #define SSIRSEL_CIM_SOSEL0_MASK (3U << 0) 00316 #define SSIRSEL_CIM_SOSEL0_SRC0_SET (0U << 0) 00317 #define SSIRSEL_CIM_SOSEL0_SRC1_SET (1U << 0) 00318 #define SSIRSEL_CIM_SOSEL0_MIX_SET (2U << 0) 00319 00320 #define FDTSEL_CIM_SCKDIV_SHIFT (16U) 00321 #define FDTSEL_CIM_SCKDIV_MASK (0x7FFU << FDTSEL_CIM_SCKDIV_SHIFT) 00322 #define FDTSEL_CIM_DIVEN_MASK (1U << 8) 00323 #define FDTSEL_CIM_DIVEN_SET (1U << 8) 00324 #define FDTSEL_CIM_MTUSEL_MASK (1U << 4) 00325 #define FDTSEL_CIM_MTUSEL_SET_TIOC3A (0U << 4) 00326 #define FDTSEL_CIM_MTUSEL_SET_TIOC4A (1U << 4) 00327 #define FDTSEL_CIM_SCKSEL_MASK (0x0FU << 0) 00328 #define FDTSEL_CIM_SCKSEL_AUDIO_CLK_SET (0U) 00329 #define FDTSEL_CIM_SCKSEL_AUDIO_X1_SET (1U) 00330 #define FDTSEL_CIM_SCKSEL_MLB_CLK_SET (2U) 00331 #define FDTSEL_CIM_SCKSEL_USB_X1_SET (3U) 00332 #define FDTSEL_CIM_SCKSEL_CLKP1_2_SET (4U) 00333 #define FDTSEL_CIM_SCKSEL_MTUSEL2_SET (5U) 00334 #define FDTSEL_CIM_SCKSEL_SSIF0_WS_SET (8U) 00335 #define FDTSEL_CIM_SCKSEL_SSIF1_WS_SET (9U) 00336 #define FDTSEL_CIM_SCKSEL_SSIF2_WS_SET (10U) 00337 #define FDTSEL_CIM_SCKSEL_SSIF3_WS_SET (11U) 00338 #define FDTSEL_CIM_SCKSEL_SSIF4_WS_SET (12U) 00339 #define FDTSEL_CIM_SCKSEL_SSIF5_WS_SET (13U) 00340 00341 #define FUTSEL_CIM_SCKDIV_SHIFT (16U) 00342 #define FUTSEL_CIM_SCKDIV_MASK (0x7FFU << FDTSEL_CIM_SCKDIV_SHIFT) 00343 #define FUTSEL_CIM_DIVEN_MASK (1U << 8) 00344 #define FUTSEL_CIM_DIVEN_SET (1U << 8) 00345 #define FUTSEL_CIM_MTUSEL_MASK (1U << 4) 00346 #define FUTSEL_CIM_MTUSEL_SET_TIOC3A (0U << 4) 00347 #define FUTSEL_CIM_MTUSEL_SET_TIOC4A (1U << 4) 00348 #define FUTSEL_CIM_SCKSEL_MASK (0x0FU << 0) 00349 #define FUTSEL_CIM_SCKSEL_AUDIO_CLK_SET (0U) 00350 #define FUTSEL_CIM_SCKSEL_AUDIO_X1_SET (1U) 00351 #define FUTSEL_CIM_SCKSEL_MLB_CLK_SET (2U) 00352 #define FUTSEL_CIM_SCKSEL_USB_X1_SET (3U) 00353 #define FUTSEL_CIM_SCKSEL_CLKP1_2_SET (4U) 00354 #define FUTSEL_CIM_SCKSEL_MTUSEL2_SET (5U) 00355 #define FUTSEL_CIM_SCKSEL_SSIF0_WS_SET (8U) 00356 #define FUTSEL_CIM_SCKSEL_SSIF1_WS_SET (9U) 00357 #define FUTSEL_CIM_SCKSEL_SSIF2_WS_SET (10U) 00358 #define FUTSEL_CIM_SCKSEL_SSIF3_WS_SET (11U) 00359 #define FUTSEL_CIM_SCKSEL_SSIF4_WS_SET (12U) 00360 #define FUTSEL_CIM_SCKSEL_SSIF5_WS_SET (13U) 00361 00362 #define SSIPMD_CIM_SSI5CKS_MASK (1U << 21) 00363 #define SSIPMD_CIM_SSI5CKS_SET (1U << 21) 00364 #define SSIPMD_CIM_SSI4CKS_MASK (1U << 20) 00365 #define SSIPMD_CIM_SSI4CKS_SET (1U << 20) 00366 #define SSIPMD_CIM_SSI3CKS_MASK (1U << 19) 00367 #define SSIPMD_CIM_SSI3CKS_SET (1U << 19) 00368 #define SSIPMD_CIM_SSI2CKS_MASK (1U << 18) 00369 #define SSIPMD_CIM_SSI2CKS_SET (1U << 18) 00370 #define SSIPMD_CIM_SSI1CKS_MASK (1U << 17) 00371 #define SSIPMD_CIM_SSI1CKS_SET (1U << 17) 00372 #define SSIPMD_CIM_SSI0CKS_MASK (1U << 16) 00373 #define SSIPMD_CIM_SSI0CKS_SET (1U << 16) 00374 #define SSIPMD_CIM_SSI3PMD_SHIFT (14U) 00375 #define SSIPMD_CIM_SSI3PMD_MASK (3U << SSIPMD_CIM_SSI3PMD_SHIFT) 00376 #define SSIPMD_CIM_SSI345EN_MASK (1U << 12) 00377 #define SSIPMD_CIM_SSI345EN_SET (1U << 12) 00378 #define SSIPMD_CIM_SSI4PMD_SHIFT (10U) 00379 #define SSIPMD_CIM_SSI4PMD_MASK (3U << SSIPMD_CIM_SSI4PMD_SHIFT) 00380 #define SSIPMD_CIM_SSI5PMD_SHIFT (8U) 00381 #define SSIPMD_CIM_SSI5PMD_MASK (3U << SSIPMD_CIM_SSI5PMD_SHIFT) 00382 #define SSIPMD_CIM_SSI012EN_MASK (1U << 4) 00383 #define SSIPMD_CIM_SSI012EN_SET (1U << 4) 00384 #define SSIPMD_CIM_SSI2PMD_SHIFT (2U) 00385 #define SSIPMD_CIM_SSI2PMD_MASK (3U << SSIPMD_CIM_SSI2PMD_SHIFT) 00386 #define SSIPMD_CIM_SSI1PMD_SHIFT (0U) 00387 #define SSIPMD_CIM_SSI1PMD_MASK (3U << SSIPMD_CIM_SSI1PMD_SHIFT) 00388 00389 #define SSICTRL_CIM_SSI3TX_SET (1U << 30) 00390 #define SSICTRL_CIM_SSI4TX_SET (1U << 29) 00391 #define SSICTRL_CIM_SSI5TX_SET (1U << 28) 00392 #define SSICTRL_CIM_SSI345TEN_SET (1U << 17) 00393 #define SSICTRL_CIM_SSI0TX_SET (1U << 14) 00394 #define SSICTRL_CIM_SSI1TX_SET (1U << 13) 00395 #define SSICTRL_CIM_SSI2TX_SET (1U << 12) 00396 #define SSICTRL_CIM_SSI012TEN_SET (1U << 1) 00397 00398 #define SRCRSEL_CIM_PLACE_N_MASK (7U) 00399 #define SRCRSEL_CIM_PLACE_N_SHIFT (4U) 00400 00401 #define MIXRSEL_CIM_PLACE_N_MASK (7U) 00402 #define MIXRSEL_CIM_PLACE_N_SHIFT (4U) 00403 00404 00405 /* SSIF Register Set Value */ 00406 /* Init Value */ 00407 #define SCUX_SSICR_INIT_VALUE (0x00000000U) 00408 #define SCUX_SSIFCR_INIT_VALUE (0x00000000U) 00409 #define SCUX_SSIFTDR_INIT_VALUE (0x00000000U) 00410 #define SCUX_SSITDMR_INIT_VALUE (0x00000000U) 00411 #define SCUX_SSIFCCR_INIT_VALUE (0x00000000U) 00412 #define SCUX_SSIFCMR_INIT_VALUE (0x00000000U) 00413 00414 /* SSIF bit value & mask & fixed setting */ 00415 #define SCUX_SSICR_CKS_SET (1U << 30) 00416 #define SCUX_SSICR_TUIEN_SET (1U << 29) 00417 #define SCUX_SSICR_TOIEN_SET (1U << 28) 00418 #define SCUX_SSICR_RUIEN_SET (1U << 27) 00419 #define SCUX_SSICR_ROIEN_SET (1U << 26) 00420 #define SCUX_SSICR_CHNL_SET_1CH (0U << 22) 00421 #define SCUX_SSICR_CHNL_SET_2CH (1U << 22) 00422 #define SCUX_SSICR_CHNL_SET_3CH (2U << 22) 00423 #define SCUX_SSICR_CHNL_SET_4CH (3U << 22) 00424 #define SCUX_SSICR_DWL_16BIT_SET (1U << 19) 00425 #define SCUX_SSICR_DWL_24BIT_SET (5U << 19) 00426 #define SCUX_SSICR_SWL_SHIFT (16U) 00427 #define SCUX_SSICR_SCKD_SET (1U << 15) 00428 #define SCUX_SSICR_SWSD_SET (1U << 14) 00429 #define SCUX_SSICR_SCKP_SET (1U << 13) 00430 #define SCUX_SSICR_SWSP_SET (1U << 12) 00431 #define SCUX_SSICR_SPDP_SET (1U << 11) 00432 #define SCUX_SSICR_SDTA_SET (1U << 10) 00433 #define SCUX_SSICR_DEL_SET (1U << 8) 00434 #define SCUX_SSICR_CKDV_SHIFT (4U) 00435 #define SCUX_SSICR_TEN_SET (1U << 1) 00436 00437 #define SCUX_SSITDMR_CONT_SET (1U << 8) 00438 #define SCUX_SSITDMR_TDM_SET (1U << 0) 00439 00440 /* SCUX fixed value */ 00441 #define SCUX_RATE_CONVERT_CALC_VALUE (0x400000U) 00442 #define SCUX_CALC_MINFS_VALUE (100U) 00443 #define SCUX_MAX_DIV_CLK (2046U) 00444 #define SCUX_MIN_RATE_MIN_PAERCENTAGE (90U) 00445 #define SCUX_MIN_RATE_MAX_PAERCENTAGE (98U) 00446 #define SCUX_MIN_RATE_DENOMINATOR (100U) 00447 #define SCUX_MAX_WAIT_TIME (0xFFFFFFU) 00448 #define SCUX_MAX_DIGITAL_VOLUME (0x7FFFFFU) 00449 #define SCUX_MAX_RAMP_VOLUME (0x3FFU) 00450 #define SCUX_RATE_INT_CONV_VALUE (1000U) 00451 #define SCUX_ADJUST_REST_VALUE (1U) 00452 #define SCUX_MAX_CONV_RATE (16000U) 00453 #define SCUX_MIN_CONV_RATE_NORMAL_CH1_2 (125U) 00454 #define SCUX_MIN_CONV_RATE_NORMAL_CH4 (250U) 00455 #define SCUX_MIN_CONV_RATE_NORMAL_CH6 (375U) 00456 #define SCUX_MIN_CONV_RATE_NORMAL_CH8 (500U) 00457 #define SCUX_MIN_CONV_RATE_DELAY1 (500U) 00458 #define SCUX_MIN_CONV_RATE_DELAY2 (1000U) 00459 #define SCUX_MIN_FREQ (1000U) 00460 #define SCUX_MAX_FREQ_CH1_4 (96000U) 00461 #define SCUX_MAX_FREQ_CH6 (66000U) 00462 #define SCUX_MAX_FREQ_CH8 (49000U) 00463 #define SCUX_PROC_DELAY_NONE (0U) 00464 #define SCUX_PROCESS_DELAY_NORMAL_CH1 (641U) 00465 #define SCUX_PROCESS_DELAY_NORMAL_CH2 (321U) 00466 #define SCUX_PROCESS_DELAY_NORMAL_CH4 (161U) 00467 #define SCUX_PROCESS_DELAY_NORMAL_CH6 (102U) 00468 #define SCUX_PROCESS_DELAY_NORMAL_CH8 (81U) 00469 #define SCUX_PROCESS_DELAY_1_CH1_2 (81U) 00470 #define SCUX_PROCESS_DELAY_2_CH1_2 (49U) 00471 #define SCUX_LOGIC_DELAY_BYPASS_ON (1U) 00472 #define SCUX_LOGIC_DELAY_BYPASS_OFF (3U) 00473 #define SCUX_AUDIO_X1 (22579200U) 00474 #define SCUX_AUDIO_CLK (0U) 00475 #define SCUX_MLB_CLK (66670000U) 00476 #define SCUX_USB_X1 (48000000U) 00477 #define SCUX_CLKLP1_DIV2 (33335000U) 00478 #define SCUX_SYSTEMWORD_16 (16U) 00479 #define SCUX_SYSTEMWORD_24 (24U) 00480 #define SCUX_SYSTEMWORD_32 (32U) 00481 #define SCUX_SYSTEMWORD_48 (48U) 00482 #define SCUX_SYSTEMWORD_64 (64U) 00483 #define SCUX_SYSTEMWORD_128 (128U) 00484 #define SCUX_SYSTEMWORD_256 (256U) 00485 #define SCUX_SSIF_CLK_DIV1 (1U) 00486 #define SCUX_SSIF_CLK_DIV2 (2U) 00487 #define SCUX_SSIF_CLK_DIV4 (4U) 00488 #define SCUX_SSIF_CLK_DIV8 (8U) 00489 #define SCUX_SSIF_CLK_DIV16 (16U) 00490 #define SCUX_SSIF_CLK_DIV32 (32U) 00491 #define SCUX_SSIF_CLK_DIV64 (64U) 00492 #define SCUX_SSIF_CLK_DIV128 (128U) 00493 #define SCUX_SSIF_CLK_DIV6 (6U) 00494 #define SCUX_SSIF_CLK_DIV12 (12U) 00495 #define SCUX_SSIF_CLK_DIV24 (24U) 00496 #define SCUX_SSIF_CLK_DIV48 (48U) 00497 #define SCUX_SSIF_CLK_DIV96 (96U) 00498 #define SCUX_SSIF_GPIO_SNCR_SHIFT_CH0 (0U) 00499 #define SCUX_SSIF_GPIO_SNCR_SHIFT_CH1 (1U) 00500 #define SCUX_SSIF_GPIO_SNCR_SHIFT_CH2 (2U) 00501 #define SCUX_SSIF_GPIO_SNCR_SHIFT_CH3 (3U) 00502 #define SCUX_SSIF_GPIO_SNCR_SHIFT_CH4 (4U) 00503 #define SCUX_SSIF_GPIO_SNCR_SHIFT_CH5 (5U) 00504 #define SCUX_DUMMY_BUF_SIZE (4096U) 00505 #define SCUX_GET_ROUTE_MASK (0xF000) 00506 #define SCUX_ROUTE_MEM_TO_MEM (0x1000) 00507 #define SCUX_ROUTE_SSIF (0x2000) 00508 #define SCUX_ROUTE_MIX (0x3000) 00509 #define SCUX_FIFO_SIZE_CH0_1 (1024U) 00510 #define SCUX_FIFO_SIZE_CH2_3 (256U) 00511 #define SCUX_SSIF_NO_USE_CH (0xFFFFU) 00512 #define SCUX_SSIF_USE_MIX_BIT (0x1000U) 00513 #define SRC_MOD_SRC0 (0U) 00514 #define SRC_MOD_SRC1 (1U) 00515 #define SCUX_EVEN_VALUE_DIV (2U) 00516 #define SCUX_SSIF_NUM_CH_ARRANGEMENT (3U) 00517 #define SCUX_SSIF_CH_ARRANGEMENT1 (0U) 00518 #define SCUX_SSIF_CH_ARRANGEMENT2 (1U) 00519 #define SCUX_SSIF_CH_ARRANGEMENT3 (2U) 00520 #define SCUX_DMA_UNIT_SIZE16 (2U) 00521 #define SCUX_DMA_UNIT_SIZE24 (4U) 00522 #define SCUX_HALF_SIZE_VALUE (2U) 00523 #define SCUX_RAMP_WAIT_MAX (10U) 00524 00525 /************************************************************************* 00526 Enumerated Types 00527 *************************************************************************/ 00528 00529 /* DRV Status */ 00530 typedef enum 00531 { 00532 SCUX_DRV_UNINIT = 0, /* Uninit */ 00533 #if(1) /* mbed */ 00534 SCUX_DRV_INIT_RUNNING = 1, /* Init running */ 00535 SCUX_DRV_INIT = 2 /* Init */ 00536 #else /* not mbed */ 00537 SCUX_DRV_INIT = 1 /* Init */ 00538 #endif /* end mbed */ 00539 } scux_stat_drv_t; 00540 00541 /* Channel Status */ 00542 typedef enum 00543 { 00544 SCUX_CH_UNINIT = 0, /* Uninit */ 00545 SCUX_CH_INIT = 1, /* Init */ 00546 SCUX_CH_STOP = 2, /* Open (request can't be received) */ 00547 SCUX_CH_TRANS_IDLE = 4, /* Open (request is not received) */ 00548 SCUX_CH_TRANS_RD = 8, /* Transfer (read only) */ 00549 SCUX_CH_TRANS_WR = 16, /* Transfer (read only) */ 00550 SCUX_CH_TRANS_RDWR = 32, /* Transfer (read & write) */ 00551 SCUX_CH_STOP_WAIT = 64, /* Transfer (wait flush stop) */ 00552 SCUX_CH_STOP_WAIT_IDLE = 128 /* Transfer (wait flush stop and request is not received */ 00553 } scux_stat_ch_t; 00554 00555 /* fifo size */ 00556 typedef enum 00557 { 00558 SCUX_FIFO_REQ_SIZE_256_64 = 0, /* fifo size is 256 data (SRC0, 1) and 64 data (SRC2, 3) */ 00559 SCUX_FIFO_REQ_SIZE_128_32 = 1, /* fifo size is 128 data (SRC0, 1) and 32 data (SRC2, 3) */ 00560 SCUX_FIFO_REQ_SIZE_64_16 = 2, /* fifo size is 64 data (SRC0, 1) and 16 data (SRC2, 3) */ 00561 SCUX_FIFO_REQ_SIZE_32_8 = 3, /* fifo size is 32 data (SRC0, 1) and 8 data (SRC2, 3) */ 00562 SCUX_FIFO_REQ_SIZE_16_4 = 4, /* fifo size is 16 data (SRC0, 1) and 4 data (SRC2, 3) */ 00563 SCUX_FIFO_REQ_SIZE_8_2 = 5, /* fifo size is 8 data (SRC0, 1) and 2 data (SRC2, 3) */ 00564 SCUX_FIFO_REQ_SIZE_4_1 = 6, /* fifo size is 4 data (SRC0, 1) and 1 data (SRC2, 3) */ 00565 SCUX_FIFO_REQ_SIZE_2 = 7, /* fifo size is 2 data (SRC0, 1) */ 00566 SCUX_FIFO_REQ_SIZE_1 = 8 /* fifo size is 1 data (SRC0, 1) */ 00567 } scux_fifo_req_size_t; 00568 00569 /* SSIF over sampling clock divide rate */ 00570 typedef enum 00571 { 00572 SCUX_SSIF_CKDIV_1 = 0, /* divide rate 1/1 */ 00573 SCUX_SSIF_CKDIV_2 = 1, /* divide rate 1/2 */ 00574 SCUX_SSIF_CKDIV_4 = 2, /* divide rate 1/4 */ 00575 SCUX_SSIF_CKDIV_8 = 3, /* divide rate 1/8 */ 00576 SCUX_SSIF_CKDIV_16 = 4, /* divide rate 1/16 */ 00577 SCUX_SSIF_CKDIV_32 = 5, /* divide rate 1/32 */ 00578 SCUX_SSIF_CKDIV_64 = 6, /* divide rate 1/64 */ 00579 SCUX_SSIF_CKDIV_128 = 7, /* divide rate 1/128 */ 00580 SCUX_SSIF_CKDIV_6 = 8, /* divide rate 1/6 */ 00581 SCUX_SSIF_CKDIV_12 = 9, /* divide rate 1/12 */ 00582 SCUX_SSIF_CKDIV_24 = 10, /* divide rate 1/24 */ 00583 SCUX_SSIF_CKDIV_48 = 11, /* divide rate 1/48 */ 00584 SCUX_SSIF_CKDIV_96 = 12 /* divide rate 1/96 */ 00585 } scux_ssif_ckdiv_t; 00586 00587 /************************************************************************* 00588 Structures 00589 *************************************************************************/ 00590 00591 /* Information of SCUX register */ 00592 typedef struct 00593 { 00594 struct st_scux_from_dvuir_dvu0_n *p_dvu_reg; /* DVU register */ 00595 struct st_scux_from_srcir0_2src0_n *p_src_reg; /* SRC register */ 00596 struct st_scux_from_ffuir_ffu0_n *p_ffu_reg; /* FFU register */ 00597 struct st_scux_from_ffdir_ffd0_n *p_ffd_reg; /* FFD register */ 00598 struct st_scux_from_opcir_opc0_n *p_opc_reg; /* OPC register */ 00599 struct st_scux_from_ipcir_ipc0_n *p_ipc_reg; /* IPC register */ 00600 volatile uint32_t *mixir_mix0_0; /* MIXIR_MIX0_0 register */ 00601 volatile uint32_t *madir_mix0_0; /* MADIR_MIX0_0 register */ 00602 volatile uint32_t *mixbr_mix0_0; /* MIXBR_MIX0_0 register */ 00603 volatile uint32_t *mixmr_mix0_0; /* MIXMR_MIX0_0 register */ 00604 volatile uint32_t *mvpdr_mix0_0; /* MVPDR_MIX0_0 register */ 00605 volatile uint32_t *mdb_n_r_mix0_0; /* MDBAR_MIX0_0 - MDBDR_MIX0_0 register */ 00606 volatile uint32_t *mdber_mix0_0; /* MDBER_MIX0_0 register */ 00607 volatile uint32_t *mixsr_mix0_0; /* MIXSR_MIX0_0 register */ 00608 volatile uint32_t *swrsr_cim; /* SWRSR_CIM register */ 00609 volatile uint32_t *dmacr_cim; /* DMACR_CIM register */ 00610 volatile uint32_t *dmatd_n_cim; /* DMATD0_CIM - DMATD3_CIM register */ 00611 volatile uint32_t *dmatu_n_cim; /* DMATU0_CIM - DMATU3_CIM register */ 00612 volatile uint32_t *ssirsel_cim; /* SSIRSEL_CIM register */ 00613 volatile uint32_t *fdtsel_n_cim; /* FDTSEL0_CIM - FDTSEL3_CIM register */ 00614 volatile uint32_t *futsel_n_cim; /* FUTSEL0_CIM - FUTSEL3_CIM register */ 00615 volatile uint32_t *ssipmd_cim; /* SSIPMD_CIM register */ 00616 volatile uint32_t *ssictrl_cim; /* SSICTRL_CIM register */ 00617 volatile uint32_t *srcrsel_n_cim; /* SRCRSEL0_CIM - SRCRSEL3_CIM register */ 00618 volatile uint32_t *mixrsel_cim; /* MIXRSEL_CIM register */ 00619 } scux_reg_info_t; 00620 00621 /* Information of SSIF */ 00622 typedef struct 00623 { 00624 bool_t ssif_enable; /* USE SSIF flag */ 00625 bool_t ssif_setup; /* SSIF setup complete flag */ 00626 osSemaphoreId sem_ch_scux_ssif_access; /* SSIF info semaphore */ 00627 int_t scux_channel; /* SCUX ch which is using SSIF */ 00628 scux_src_clk_source_t pin_clk; /* AUDIO_CLK source */ 00629 scux_pin_mode_t pin_mode; /* SSIF sync setting */ 00630 scux_pin_mode_t pin_mode_backup; /* back up of SSIF sync setting */ 00631 scux_ssif_cfg_t ssif_cfg; /* SSIF parameters */ 00632 scux_ssif_ckdiv_t clk_div; /* Over sampling clock divide rate */ 00633 volatile struct st_ssif *p_scux_ssif_reg; /* SSIF register */ 00634 } scux_ssif_info_t; 00635 00636 /* Information of Driver */ 00637 typedef struct 00638 { 00639 osSemaphoreId sem_shared_access; /* Shared info semaphore */ 00640 bool_t mix_setup; /* MIX setup complete flag */ 00641 uint32_t mix_run_ch; /* MIX used channel */ 00642 uint32_t mix_ssif_ch; /* SSIF channel on used MIX */ 00643 bool_t mixmode_ramp; /* Ramp mode / Step mode select */ 00644 scux_mix_ramp_time_t up_period; /* Ramp up period */ 00645 scux_mix_ramp_time_t down_period; /* Ramp down period */ 00646 uint32_t mix_vol[SCUX_CH_NUM]; /* MIX volume value */ 00647 scux_audio_channel_t select_out_data_ch[SCUX_AUDIO_CH_MAX]; /* Audio data position setting */ 00648 uint32_t ssictrl_cim_value; /* SSICTRL_CIM register (write only) value */ 00649 } scux_shared_info_t; 00650 00651 /* Information of Channel */ 00652 typedef struct 00653 { 00654 int_t channel; /* Channel Number */ 00655 bool_t enabled; /* Used channel flag */ 00656 int_t open_flags; /* Read/write flag */ 00657 scux_stat_ch_t ch_stat; /* Channel Status */ 00658 osSemaphoreId sem_ch_scux_access; /* Channel Semaphore */ 00659 AHF_S tx_que; /* Write request queue */ 00660 AHF_S rx_que; /* Read request queue */ 00661 AIOCB *p_tx_aio; /* Write request information pointer */ 00662 AIOCB *p_tx_next_aio; /* Next write request information pointer */ 00663 AIOCB *p_rx_aio; /* Read request information pointer */ 00664 AIOCB *p_rx_next_aio; /* Next read request information pointer */ 00665 uint8_t int_level; /* Interrupt priority */ 00666 IRQn_Type int_num[SCUX_INT_MAX]; /* Each interrupt number */ 00667 int_t dma_tx_ch; /* Write DMA channel */ 00668 int_t dma_rx_ch; /* Read DMA channel */ 00669 dma_res_select_t dma_resource_tx; /* Write DMA resource */ 00670 dma_res_select_t dma_resource_rx; /* Read DMA resource */ 00671 uint32_t dma_tx_current_size; /* Current write DMA size */ 00672 uint32_t dma_tx_next_size; /* Next write DMA size */ 00673 uint32_t dma_rx_current_size; /* Current read DMA size */ 00674 uint32_t dma_rx_next_size; /* Next read DMA size */ 00675 dma_ch_setup_t dma_tx_setup; /* Write DMA paramtter */ 00676 dma_ch_setup_t dma_rx_setup; /* Read DMA paramtter */ 00677 scux_reg_info_t *p_scux_reg; /* SCUX register information */ 00678 scux_route_t route_set; /* SCUX route paramter */ 00679 scux_src_cfg_t src_cfg; /* SRC parameter */ 00680 scux_dvu_cfg_t dvu_cfg; /* DVU parameter */ 00681 bool_t dvu_setup; /* DVU setup complete flag */ 00682 uint32_t dvu_mute_stat; /* DVU mute status */ 00683 scux_ssif_info_t *p_ssif_info1; /* SSIF channel information1 */ 00684 scux_ssif_info_t *p_ssif_info2; /* SSIF channel information2 */ 00685 scux_ssif_info_t *p_ssif_info3; /* SSIF channel information3 */ 00686 void (*p_flush_callback)(int_t ercd); /* Call back pointer for flush stop */ 00687 bool_t first_tx_flag; /* First write data transfer flag */ 00688 bool_t first_rx_flag; /* First read data transfer flag */ 00689 bool_t first_ramp_flag; /* First ramp setting flag */ 00690 volatile uint8_t *p_tx_dummy_data; /* Write dummy data buffer pointer */ 00691 volatile uint8_t *p_rx_dummy_data; /* Read dummy data buffer pointer */ 00692 uint32_t flush_stop_size; /* Needed transfer size for flush stop */ 00693 uint32_t fifo_size; /* Fifo size */ 00694 uint32_t fifo_req_size; /* Fifo request size */ 00695 uint32_t last_dummy_size; /* Last dummy data size for flush stop */ 00696 uint32_t tx_fifo_total_size; /* Total data size of write request size / FIFO size */ 00697 uint32_t rx_fifo_total_size; /* Total data size of read request size / FIFO size */ 00698 bool_t tx_dummy_run_flag; /* Dummy data transfer flag */ 00699 bool_t cancel_operate_flag; /* indicate cancel operation */ 00700 bool_t restart_ramp_flag; /* ramp restart flag after cancel operation */ 00701 uint32_t input_rate; /* Input rate */ 00702 uint32_t output_rate; /* Output rate */ 00703 uint32_t futsel_cim_value; /* FUTSEL_CIM register value (write only) */ 00704 int_t err_stat_backup; /* SCUX HW error status backup */ 00705 } scux_info_ch_t; 00706 00707 /* Information of Driver */ 00708 typedef struct 00709 { 00710 scux_stat_drv_t drv_stat; /* DRV status */ 00711 scux_info_ch_t info_ch[SCUX_CH_NUM]; /* CH status */ 00712 scux_shared_info_t shared_info; /* shared resource information */ 00713 } scux_info_drv_t; 00714 00715 /*********************************************************************************** 00716 Function Prototypes 00717 ***********************************************************************************/ 00718 00719 scux_info_drv_t *SCUX_GetDrvInstance(void); 00720 scux_info_ch_t *SCUX_GetDrvChInfo(const int_t channel); 00721 scux_ssif_info_t *SCUX_GetSsifChInfo(const int_t channel); 00722 #if(1) /* mbed */ 00723 int_t SCUX_InitializeOne(const int_t channel, const scux_channel_cfg_t * const p_scux_init_param); 00724 void SCUX_UnInitializeOne(const int_t channel); 00725 #endif /* end mbed */ 00726 int_t SCUX_Initialize(const scux_channel_cfg_t * const p_scux_init_param); 00727 void SCUX_UnInitialize(void); 00728 int_t SCUX_OpenChannel(const int_t channel, const int_t flags); 00729 int_t SCUX_CloseChannel(const int_t channel); 00730 int_t SCUX_IoctlTransStart(const int_t channel); 00731 int_t SCUX_IoctlFlushStop(const int_t channel, void (* const callback)(int_t ercd), const int_t was_masked); 00732 int_t SCUX_IoctlClearStop(const int_t channel, const int_t was_masked); 00733 void SCUX_IoctlSetRoute(const int_t channel, const scux_route_t route); 00734 int_t SCUX_IoctlSetPinClk(const int_t channel, const scux_ssif_pin_clk_t * const p_pin_clk_param); 00735 int_t SCUX_IoctlSetPinMode(const int_t channel, const scux_ssif_pin_mode_t * const p_pin_mode_param); 00736 void SCUX_IoctlSetSrcCfg(const int_t channel, const scux_src_cfg_t * const p_src_param); 00737 void SCUX_IoctlSetDvuCfg(const int_t channel, const scux_dvu_cfg_t * const p_dvu_param); 00738 int_t SCUX_IoctlSetDvuDigiVol(const int_t channel, const scux_dvu_digi_vol_t * const p_digi_vol_param); 00739 int_t SCUX_IoctlSetDvuRampVol(const int_t channel, const scux_dvu_ramp_vol_t * const p_ramp_vol_param); 00740 int_t SCUX_IoctlSetDvuZerocrossMute(const int_t channel, const scux_zc_mute_t * const p_zc_mute_param); 00741 int_t SCUX_IoctlSetStopMute(const int_t channel, const uint32_t audio_channel); 00742 int_t SCUX_IoctlSetMixCfg(const scux_mix_cfg_t * const p_mix_param); 00743 int_t SCUX_IoctlSetMixVol(const int_t channel, const uint32_t mix_vol); 00744 int_t SCUX_IoctlSetSsifCfg(const scux_ssif_cfg_t *const p_ssif_param); 00745 void SCUX_IoctlGetWriteStat(const int_t channel, uint32_t * const p_write_stat); 00746 void SCUX_IoctlGetReadStat(const int_t channel, uint32_t * const p_read_stat); 00747 void SCUX_IoctlGetDvuStat(const int_t channel, uint32_t * const p_dvu_stat); 00748 void SCUX_IoctlGetMuteStat(const int_t channel, uint32_t * const p_mute_stat); 00749 void SCUX_IoctlGetMixStat(const int_t channel, uint32_t * const p_mix_stat); 00750 int_t SCUX_CheckParam(scux_info_ch_t * const p_scux_info_ch); 00751 int_t SCUX_FlushWriteStart(scux_info_ch_t * const p_scux_info_ch); 00752 void SCUX_InitHw(scux_info_ch_t * const p_scux_info_ch); 00753 void SCUX_SetupSsif(const scux_info_ch_t * const p_scux_info_ch); 00754 void SCUX_SetupSrc(scux_info_ch_t * const p_scux_info_ch); 00755 void SCUX_SetupDvu(scux_info_ch_t * const p_scux_info_ch); 00756 int_t SCUX_SetupDma(scux_info_ch_t * const p_scux_info_ch); 00757 void SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch); 00758 void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch); 00759 int_t SCUX_CopyWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio); 00760 int_t SCUX_DirectWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio); 00761 int_t SCUX_CopyReadStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_read_aio); 00762 int_t SCUX_CopyCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio); 00763 int_t SCUX_DirectCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio); 00764 int_t SCUX_CopyCancelAll(scux_info_ch_t * const p_scux_info_ch); 00765 int_t SCUX_DirectCancelAll(scux_info_ch_t * const p_scux_info_ch); 00766 void SCUX_AdjustAccessFifo(scux_info_ch_t * const p_scux_info_ch, const uint32_t tx_remain_size, const uint32_t rx_remain_size); 00767 void SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch); 00768 void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch); 00769 void SCUX_SyncStopHw(const scux_info_ch_t * const p_scux_info_ch); 00770 void SCUX_AsyncStopHw(scux_info_ch_t * const p_scux_info_ch); 00771 void SCUX_SetDigiVolRegister(const scux_info_ch_t * const p_scux_info_ch); 00772 void SCUX_SetRampVolRegister(scux_info_ch_t * const p_scux_info_ch); 00773 void SCUX_SetZerocrossMuteRegister(const scux_info_ch_t * const p_scux_info_ch); 00774 void SCUX_SetMixVolRegister(const int_t channel); 00775 int_t SCUX_CheckSsifClockDiv(const scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch_num); 00776 void SCUX_SetupSsifGpio(const scux_ssif_ch_num_t ssif_ch); 00777 size_t SCUX_StrNLen(const char_t* p_str, size_t maxlen); 00778 00779 #endif /* SCUX_H */
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