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scux.c

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00001 /*******************************************************************************
00002 * DISCLAIMER
00003 * This software is supplied by Renesas Electronics Corporation and is only
00004 * intended for use with Renesas products. No other uses are authorized. This
00005 * software is owned by Renesas Electronics Corporation and is protected under
00006 * all applicable laws, including copyright laws.
00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
00016 * Renesas reserves the right, without notice, to make changes to this software
00017 * and to discontinue the availability of this software. By using this software,
00018 * you agree to the additional terms and conditions found by accessing the
00019 * following link:
00020 * http://www.renesas.com/disclaimer
00021 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
00022 *******************************************************************************/
00023 
00024 /**************************************************************************//**
00025 * @file         scux.c
00026 * $Rev: 1674 $
00027 * $Date:: 2015-05-29 16:35:57 +0900#$
00028 * @brief        SCUX Driver functions
00029 ******************************************************************************/
00030 
00031 /*******************************************************************************
00032 Includes <System Includes>, "Project Includes"
00033 *******************************************************************************/
00034 
00035 #include "scux.h"
00036 
00037 #if(1) /* mbed */
00038 /******************************************************************************
00039 Macro definitions
00040 ******************************************************************************/
00041 #define INIT_WAIT_TIME_MSEC (1)
00042 #define INIT_WAIT_NUM       (1000U)
00043 
00044 #endif /* end mbed */
00045 /******************************************************************************
00046 Exported global variables (to be accessed by other files)
00047 ******************************************************************************/
00048 
00049 /* ->MISRA 8.8 This description is based on the way to fill out OS defined. */
00050 /* ->IPA M2.2.2, MISRA 8.10 This description is based on the way to fill out OS defined. */
00051 osSemaphoreDef(scux_ch0_access);
00052 osSemaphoreDef(scux_ch1_access);
00053 osSemaphoreDef(scux_ch2_access);
00054 osSemaphoreDef(scux_ch3_access);
00055 
00056 osSemaphoreDef(scux_ssif_ch0_access);
00057 osSemaphoreDef(scux_ssif_ch1_access);
00058 osSemaphoreDef(scux_ssif_ch2_access);
00059 osSemaphoreDef(scux_ssif_ch3_access);
00060 osSemaphoreDef(scux_ssif_ch4_access);
00061 osSemaphoreDef(scux_ssif_ch5_access);
00062 
00063 osSemaphoreDef(scux_shared_access);
00064 /* <-MISRA 8.10, IPA M2.2.2 */
00065 /* <-MISRA 8.8 */
00066 
00067 /******************************************************************************
00068 Private global driver management information
00069 ******************************************************************************/
00070 
00071 /* driver management infrmation */
00072 static scux_info_drv_t gb_scux_info_drv = {
00073     SCUX_DRV_UNINIT,
00074     {
00075         {SCUX_CH_0, false, 0, SCUX_CH_UNINIT}, /* ch0 */
00076         {SCUX_CH_1, false, 0, SCUX_CH_UNINIT}, /* ch1 */
00077         {SCUX_CH_2, false, 0, SCUX_CH_UNINIT}, /* ch2 */
00078         {SCUX_CH_3, false, 0, SCUX_CH_UNINIT}  /* ch3 */
00079     }
00080 };
00081 
00082 /* SSIF management information */
00083 static scux_ssif_info_t gb_scux_ssif_info[SCUX_SSIF_CH_NUM];
00084 
00085 /* ->MISRA 11.3, 11.4 11.5 This cast is needed for register access. */
00086 /* address table of register set for each SCUX channel */
00087 static scux_reg_info_t p_scux_ch_reg_addr_table[SCUX_CH_NUM] = {
00088     {
00089         &SCUX_FROM_DVUIR_DVU0_0,
00090         &SCUX_FROM_SRCIR0_2SRC0_0, 
00091         &SCUX_FROM_FFUIR_FFU0_0, 
00092         &SCUX_FROM_FFDIR_FFD0_0, 
00093         &SCUX_FROM_OPCIR_OPC0_0, 
00094         &SCUX_FROM_IPCIR_IPC0_0,
00095         &SCUXMIXIR_MIX0_0,
00096         &SCUXMADIR_MIX0_0,
00097         &SCUXMIXBR_MIX0_0,
00098         &SCUXMIXMR_MIX0_0,
00099         &SCUXMVPDR_MIX0_0,
00100         &SCUXMDBAR_MIX0_0,
00101         &SCUXMDBER_MIX0_0,
00102         &SCUXMIXSR_MIX0_0,
00103         &SCUXSWRSR_CIM,
00104         &SCUXDMACR_CIM,
00105         &SCUXDMATD0_CIM,
00106         &SCUXDMATU0_CIM,
00107         &SCUXSSIRSEL_CIM,
00108         &SCUXFDTSEL0_CIM,
00109         &SCUXFUTSEL0_CIM,
00110         &SCUXSSIPMD_CIM,
00111         &SCUXSSICTRL_CIM,
00112         &SCUXSRCRSEL0_CIM,
00113         &SCUXMIXRSEL_CIM
00114     },
00115     {
00116         &SCUX_FROM_DVUIR_DVU0_1, 
00117         &SCUX_FROM_SRCIR0_2SRC0_0, 
00118         &SCUX_FROM_FFUIR_FFU0_1, 
00119         &SCUX_FROM_FFDIR_FFD0_1, 
00120         &SCUX_FROM_OPCIR_OPC0_1, 
00121         &SCUX_FROM_IPCIR_IPC0_1,
00122         &SCUXMIXIR_MIX0_0,
00123         &SCUXMADIR_MIX0_0,
00124         &SCUXMIXBR_MIX0_0,
00125         &SCUXMIXMR_MIX0_0,
00126         &SCUXMVPDR_MIX0_0,
00127         &SCUXMDBBR_MIX0_0,
00128         &SCUXMDBER_MIX0_0,
00129         &SCUXMIXSR_MIX0_0,
00130         &SCUXSWRSR_CIM,
00131         &SCUXDMACR_CIM,
00132         &SCUXDMATD1_CIM,
00133         &SCUXDMATU1_CIM,
00134         &SCUXSSIRSEL_CIM,
00135         &SCUXFDTSEL1_CIM,
00136         &SCUXFUTSEL1_CIM,
00137         &SCUXSSIPMD_CIM,
00138         &SCUXSSICTRL_CIM,
00139         &SCUXSRCRSEL1_CIM,
00140         &SCUXMIXRSEL_CIM
00141     },
00142     {
00143         &SCUX_FROM_DVUIR_DVU0_2, 
00144         &SCUX_FROM_SRCIR0_2SRC0_1, 
00145         &SCUX_FROM_FFUIR_FFU0_2, 
00146         &SCUX_FROM_FFDIR_FFD0_2, 
00147         &SCUX_FROM_OPCIR_OPC0_2, 
00148         &SCUX_FROM_IPCIR_IPC0_2,
00149         &SCUXMIXIR_MIX0_0,
00150         &SCUXMADIR_MIX0_0,
00151         &SCUXMIXBR_MIX0_0,
00152         &SCUXMIXMR_MIX0_0,
00153         &SCUXMVPDR_MIX0_0,
00154         &SCUXMDBCR_MIX0_0,
00155         &SCUXMDBER_MIX0_0,
00156         &SCUXMIXSR_MIX0_0,
00157         &SCUXSWRSR_CIM,
00158         &SCUXDMACR_CIM,
00159         &SCUXDMATD2_CIM,
00160         &SCUXDMATU2_CIM,
00161         &SCUXSSIRSEL_CIM,
00162         &SCUXFDTSEL2_CIM,
00163         &SCUXFUTSEL2_CIM,
00164         &SCUXSSIPMD_CIM,
00165         &SCUXSSICTRL_CIM,
00166         &SCUXSRCRSEL2_CIM,
00167         &SCUXMIXRSEL_CIM
00168     },
00169     {
00170         &SCUX_FROM_DVUIR_DVU0_3, 
00171         &SCUX_FROM_SRCIR0_2SRC0_1, 
00172         &SCUX_FROM_FFUIR_FFU0_3, 
00173         &SCUX_FROM_FFDIR_FFD0_3, 
00174         &SCUX_FROM_OPCIR_OPC0_3, 
00175         &SCUX_FROM_IPCIR_IPC0_3,
00176         &SCUXMIXIR_MIX0_0,
00177         &SCUXMADIR_MIX0_0,
00178         &SCUXMIXBR_MIX0_0,
00179         &SCUXMIXMR_MIX0_0,
00180         &SCUXMVPDR_MIX0_0,
00181         &SCUXMDBDR_MIX0_0,
00182         &SCUXMDBER_MIX0_0,
00183         &SCUXMIXSR_MIX0_0,
00184         &SCUXSWRSR_CIM,
00185         &SCUXDMACR_CIM,
00186         &SCUXDMATD3_CIM,
00187         &SCUXDMATU3_CIM,
00188         &SCUXSSIRSEL_CIM,
00189         &SCUXFDTSEL3_CIM,
00190         &SCUXFUTSEL3_CIM,
00191         &SCUXSSIPMD_CIM,
00192         &SCUXSSICTRL_CIM,
00193         &SCUXSRCRSEL3_CIM,
00194         &SCUXMIXRSEL_CIM
00195     }
00196 };
00197 /* <-MISRA 11.3, 11.4 11.5 */
00198     
00199 /* ->MISRA 11.3 This cast is needed for register access. */
00200 /* address table of register set for each SSIF channel */
00201 static volatile struct st_ssif * const p_scux_ssif_ch_reg_addr[SCUX_SSIF_CH_NUM] = 
00202 { 
00203     &SSIF0,
00204     &SSIF1,
00205     &SSIF2,
00206     &SSIF3,
00207     &SSIF4,
00208     &SSIF5
00209 };
00210 /* <-MISRA 11.3 */
00211     
00212 /* SCUX semaphore table define */
00213 static const osSemaphoreDef_t * const p_semdef_ch_scux_access[SCUX_CH_NUM] = 
00214 { 
00215     osSemaphore(scux_ch0_access),
00216     osSemaphore(scux_ch1_access),
00217     osSemaphore(scux_ch2_access),
00218     osSemaphore(scux_ch3_access)
00219 };
00220     
00221 /* SSIF semaphore table define */
00222 static const osSemaphoreDef_t * const p_semdef_ch_scux_ssif_access[SCUX_SSIF_CH_NUM] = 
00223 { 
00224     osSemaphore(scux_ssif_ch0_access),
00225     osSemaphore(scux_ssif_ch1_access),
00226     osSemaphore(scux_ssif_ch2_access),
00227     osSemaphore(scux_ssif_ch3_access),
00228     osSemaphore(scux_ssif_ch4_access),
00229     osSemaphore(scux_ssif_ch5_access)
00230 };
00231 
00232 /* write DMA resource define */
00233 static const dma_res_select_t gb_dma_res_select_tx[SCUX_CH_NUM] =
00234 {
00235     DMA_RS_SCUTXI0,
00236     DMA_RS_SCUTXI1,
00237     DMA_RS_SCUTXI2,
00238     DMA_RS_SCUTXI3
00239 };
00240    
00241 /* read DMA resource define */
00242 static const dma_res_select_t gb_dma_res_select_rx[SCUX_CH_NUM] =
00243 {
00244     DMA_RS_SCURXI0,
00245     DMA_RS_SCURXI1,
00246     DMA_RS_SCURXI2,
00247     DMA_RS_SCURXI3
00248 }; 
00249 
00250 /* write dummy data buffer */
00251 static uint8_t gb_scux_write_dummy_buf[SCUX_DUMMY_BUF_SIZE];
00252    
00253 /* read dummy data buffer */
00254 static uint8_t gb_scux_read_dummy_buf[SCUX_DUMMY_BUF_SIZE];
00255 
00256 /******************************************************************************
00257  Function prototypes
00258 ******************************************************************************/
00259  
00260 static int_t SCUX_CheckSrcParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT]);
00261 static int_t SCUX_CheckDvuParam(const scux_info_ch_t * const p_scux_info_ch);
00262 static int_t SCUX_CheckSsifParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT], const bool_t use_mix_flag);
00263 static int_t SCUX_CheckMixParam(const scux_info_ch_t * const p_scux_info_ch);
00264 #if(1) /* mbed */
00265 static int_t SCUX_CmnUnInitialize(void);
00266 #endif /* end mbed */
00267 
00268 /**************************************************************************//**
00269 * Function Name: SCUX_GetDrvInstance
00270 * @brief         Get pointer of gb_scux_info_drv.
00271 *
00272 *                Description:<br>
00273 *                
00274 * @param         None. 
00275 * @retval        pointer of gb_scux_info_drv -
00276 *                  driver instance.
00277 ******************************************************************************/
00278 
00279 scux_info_drv_t *SCUX_GetDrvInstance(void)
00280 {
00281     
00282     return &gb_scux_info_drv;
00283 }
00284 
00285 /******************************************************************************
00286 End of function SCUX_GetDrv_Instance
00287 ******************************************************************************/
00288 
00289 /**************************************************************************//**
00290 * Function Name: SCUX_GetDrvChInfo
00291 * @brief         gb_scux_info_drv.info_ch[channel].
00292 *
00293 *                Description:<br>
00294 *                
00295 * @param[in]     channel information number. 
00296 * @retval        pointer of gb_scux_info_drv -
00297 *                  pointer of channel information.
00298 ******************************************************************************/
00299 
00300 scux_info_ch_t *SCUX_GetDrvChInfo(const int_t channel)
00301 {
00302     
00303     return &gb_scux_info_drv.info_ch[channel];
00304 }
00305 
00306 /******************************************************************************
00307 End of function SCUX_GetDrvChInfo
00308 ******************************************************************************/
00309 
00310 /**************************************************************************//**
00311 * Function Name: SCUX_GetSsifChInfo
00312 * @brief         gb_scux_ssif_info.channel.
00313 *
00314 *                Description:<br>
00315 *                
00316 * @param[in]     SSIF channel number. 
00317 * @retval        pointer of gb_scux_ssif_info -
00318 *                  pointer of SSIF information.
00319 ******************************************************************************/
00320 
00321 scux_ssif_info_t *SCUX_GetSsifChInfo(const int_t channel)
00322 {
00323     
00324     return &gb_scux_ssif_info[channel];
00325 }
00326 
00327 /******************************************************************************
00328 End of function SCUX_GetSsifChInfo
00329 ******************************************************************************/
00330 
00331 #if(1) /* mbed */
00332 /**************************************************************************//**
00333 * Function Name: SCUX_InitializeOne
00334 * @brief         Init SCUX driver.
00335 *
00336 *                Description:<br>
00337 *                
00338 * @param[in]     channel    :initialize channel number.
00339 * @param[in]     p_scux_init_param :Initialize parameter for SCUX. 
00340 * @retval        ESUCCESS -
00341 *                  Operation successful.
00342 *                EERROR -
00343 *                  Error occured.
00344 *                    error code -
00345 *                       ENOMEM : Making semaphore is failed.
00346 *                       EFAULT : Internal error is occured.
00347 ******************************************************************************/
00348 int_t SCUX_InitializeOne(const int_t channel, const scux_channel_cfg_t * const p_scux_init_param)
00349 {
00350     int_t    retval = ESUCCESS;
00351     osStatus sem_ercd;
00352     int_t    scux_ch_count;
00353     int_t    audio_ch_count;
00354     scux_ssif_ch_num_t    ssif_ch_count;
00355     uint32_t cpg_value;
00356     bool_t   init_shared_flag = false;
00357     int_t    was_masked;
00358     volatile uint8_t dummy_buf;
00359     uint32_t scux_init_count;
00360     int_t    uninit_ercd;
00361     bool_t   init_start_flag = false;
00362     bool_t   uninit_all_flag = false;
00363     uint32_t i;
00364 
00365     if (NULL == p_scux_init_param)
00366     {
00367         retval = EFAULT;
00368     }
00369     else if (false == p_scux_init_param->enabled)
00370     {
00371         retval = EFAULT;
00372     }
00373     else
00374     {
00375         /* init channel management information */
00376         scux_ch_count = channel;
00377 
00378         for (i = 0; ((i < INIT_WAIT_NUM) && (false == init_start_flag)); i++)
00379         {
00380 #if defined (__ICCARM__)
00381             was_masked = __disable_irq_iar();
00382 #else
00383             was_masked = __disable_irq();
00384 #endif
00385 
00386             if (SCUX_DRV_INIT == gb_scux_info_drv.drv_stat)
00387             {
00388                 /* already scux driver shared information is initialized */
00389                 init_shared_flag = true;
00390 
00391                 /* enable the channel */
00392                 gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
00393 
00394                 init_start_flag = true;
00395             }
00396             else if (SCUX_DRV_UNINIT == gb_scux_info_drv.drv_stat)
00397             {
00398                 /* change the status to scux initialization running */
00399                 gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
00400 
00401                 for (scux_init_count = SCUX_CH_0; scux_init_count < SCUX_CH_NUM; scux_init_count++)
00402                 {
00403                     gb_scux_info_drv.info_ch[scux_init_count].enabled = false;
00404                     gb_scux_info_drv.info_ch[scux_init_count].ch_stat = SCUX_CH_UNINIT;
00405 
00406                     gb_scux_info_drv.info_ch[scux_init_count].sem_ch_scux_access = NULL;
00407                 }
00408 
00409                 for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
00410                 {
00411                     gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
00412                 }
00413 
00414                 gb_scux_info_drv.shared_info.sem_shared_access = NULL;
00415 
00416                 /* enable the channel */
00417                 gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
00418 
00419                 init_start_flag = true;
00420             }
00421             else
00422             {
00423                 /* do nothing : SCUX_DRV_INIT_RUNNING */
00424             }
00425 
00426             if (0 == was_masked)
00427             {
00428                 __enable_irq();
00429             }
00430 
00431             if (false == init_start_flag)
00432             {
00433                 /* wait for the change of drv_stat to SCUX_DRV_INIT */
00434                 (void)osDelay(INIT_WAIT_TIME_MSEC);
00435             }
00436         }
00437 
00438         if (false == init_start_flag)
00439         {
00440             retval = EFAULT;
00441         }
00442         else
00443         {
00444             {
00445     
00446                 /* copy parameter */
00447                 /* set interrupt parameter */
00448                 gb_scux_info_drv.info_ch[scux_ch_count].int_level = p_scux_init_param->int_level;
00449                         
00450                 /* set route parameter */
00451                 gb_scux_info_drv.info_ch[scux_ch_count].route_set = p_scux_init_param->route;
00452                 
00453                 /* set SRC paramter */
00454                 SCUX_IoctlSetSrcCfg(scux_ch_count, &p_scux_init_param->src_cfg);
00455                 
00456                 /* init SCUX parameter */
00457                 if ((SCUX_CH_0 == scux_ch_count) || (SCUX_CH_1 == scux_ch_count))
00458                 {
00459                     gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH0_1;
00460                 }
00461                 else
00462                 {
00463                     gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH2_3;
00464                 }
00465                 gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_tx = gb_dma_res_select_tx[scux_ch_count];
00466                 gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_rx = gb_dma_res_select_rx[scux_ch_count];
00467                 gb_scux_info_drv.info_ch[scux_ch_count].futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
00468                 gb_scux_info_drv.info_ch[scux_ch_count].err_stat_backup = ESUCCESS;
00469                 
00470                 /* init DVU parameter */
00471                 for (audio_ch_count = SCUX_AUDIO_CH_0; audio_ch_count < SCUX_AUDIO_CH_MAX; audio_ch_count++)
00472                 {
00473                     gb_scux_info_drv.info_ch[scux_ch_count].dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch_count] = false; 
00474                 }
00475                 gb_scux_info_drv.info_ch[scux_ch_count].dvu_setup = false;
00476              
00477                 if (false == init_shared_flag)
00478                 {
00479                     /* init MIX parameter */
00480                     gb_scux_info_drv.shared_info.mix_setup = false;
00481                     gb_scux_info_drv.shared_info.mix_run_ch = 0U;
00482                     gb_scux_info_drv.shared_info.mix_ssif_ch = 0U;
00483                     
00484                     /* init SSIF parameter */
00485                     for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
00486                     {
00487                         gb_scux_ssif_info[ssif_ch_count].ssif_setup = false;
00488                         gb_scux_ssif_info[ssif_ch_count].ssif_cfg.ssif_ch_num = ssif_ch_count;
00489                         gb_scux_ssif_info[ssif_ch_count].scux_channel = 0;
00490                         gb_scux_ssif_info[ssif_ch_count].pin_mode = SCUX_PIN_MODE_INDEPEND;
00491                     }
00492                     
00493                     /* init regsiter store value */
00494                     gb_scux_info_drv.shared_info.ssictrl_cim_value = SSICTRL_CIM_INIT_VALUE;
00495                 }
00496             
00497                 /* set register address */
00498                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg = &p_scux_ch_reg_addr_table[scux_ch_count];
00499                                        
00500                 if (false == init_shared_flag) {
00501 #if defined (__ICCARM__)
00502                     was_masked = __disable_irq_iar();
00503 #else
00504                     was_masked = __disable_irq();
00505 #endif
00506 
00507                     /* supply clock for SCUX */
00508                     cpg_value = (uint32_t)CPG.STBCR8 & ~(CPG_STBCR8_BIT_MSTP81);
00509                     CPG.STBCR8 = (uint8_t)cpg_value;
00510                     dummy_buf = CPG.STBCR8;
00511                     
00512                     if (0 == was_masked)
00513                     {
00514                         __enable_irq();
00515                     }
00516 
00517                     /* software reset */
00518                     SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
00519                     SCUX.SWRSR_CIM |= SWRSR_CIM_SWRST_SET;
00520                 }
00521                 
00522                 /* init DVU register */
00523                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
00524                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
00525                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
00526                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
00527                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
00528                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
00529                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
00530                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
00531                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
00532                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
00533                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
00534                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
00535                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
00536                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
00537                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
00538                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
00539                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
00540                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
00541                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
00542                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
00543                 
00544                 /* init SRC register */
00545                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
00546                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
00547                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
00548                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
00549                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
00550                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
00551                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
00552                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
00553                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
00554                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
00555                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
00556                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
00557                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
00558                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
00559                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
00560                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
00561                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
00562                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
00563                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
00564                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
00565                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
00566                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
00567                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
00568                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 = SRCIRR_2SRC0_INIT_VALUE;
00569                 
00570                 /* init FFU register */
00571                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
00572                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
00573                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
00574                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
00575                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
00576                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
00577                 
00578                 /* init FFD register */
00579                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
00580                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
00581                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
00582                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
00583                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
00584                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
00585                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
00586                 
00587                 /* init OPC register */
00588                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
00589                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
00590     
00591                 /* init IPC register */
00592                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
00593                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
00594     
00595                 /* init MIX register for each channel */
00596                 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
00597                 
00598                 /* init CIM register for each channel */
00599                 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
00600                 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
00601                 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
00602                 
00603                 /* init shared register */
00604                 if (false == init_shared_flag)
00605                 {
00606                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
00607                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
00608                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
00609                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
00610                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
00611                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
00612                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->dmacr_cim) = DMACR_CIM_INIT_VALUE;
00613                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssirsel_cim) = SSIRSEL_CIM_INIT_VALUE;
00614                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssipmd_cim) = SSIPMD_CIM_INIT_VALUE;
00615                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssictrl_cim) = SSICTRL_CIM_INIT_VALUE;
00616                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
00617                 }
00618                 
00619                 if (false == init_shared_flag)
00620                 {
00621                     /* set SSIF register */
00622                     for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
00623                     {
00624                         gb_scux_ssif_info[ssif_ch_count].p_scux_ssif_reg = p_scux_ssif_ch_reg_addr[ssif_ch_count];
00625                     }
00626                 }
00627             
00628                 /* set  semaphore parameter */
00629                 gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = osSemaphoreCreate(p_semdef_ch_scux_access[scux_ch_count], 1);
00630                 if (NULL == gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
00631                 {
00632                      retval = ENOMEM;
00633                 }
00634                 if ((ESUCCESS == retval) && (false == init_shared_flag))
00635                 {
00636                     for (ssif_ch_count = SCUX_SSIF_CH_0; ((ssif_ch_count < SCUX_SSIF_CH_NUM) && (ESUCCESS == retval)); ssif_ch_count++) 
00637                     {
00638                         gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = osSemaphoreCreate(p_semdef_ch_scux_ssif_access[ssif_ch_count], 1);
00639                         if (NULL == gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
00640                         {
00641                             retval = ENOMEM;
00642                         }
00643                     }
00644                 }
00645                 if ((ESUCCESS == retval) && (false == init_shared_flag))
00646                 {
00647                     gb_scux_info_drv.shared_info.sem_shared_access = osSemaphoreCreate(osSemaphore(scux_shared_access), 1);
00648                     if (NULL == gb_scux_info_drv.shared_info.sem_shared_access)
00649                     {
00650                         retval = ENOMEM;
00651                     }
00652                 }
00653                 
00654                 
00655                 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_INIT;
00656             }
00657 
00658             if (ESUCCESS != retval)
00659             {
00660                 /* uninit each resouces */
00661                 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
00662 
00663                 if (NULL != gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
00664                 {
00665                     /* semaphore delete */
00666                     sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
00667                     /* semaphore error check */
00668                     if (osOK != sem_ercd)
00669                     {
00670                         /* set error return value */
00671                         retval = EFAULT;
00672                     }
00673 
00674                     gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
00675                 }
00676 
00677 #if defined (__ICCARM__)
00678                 was_masked = __disable_irq_iar();
00679 #else
00680                 was_masked = __disable_irq();
00681 #endif
00682 
00683                 gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
00684 
00685                 for (i = SCUX_CH_0; i < SCUX_CH_NUM; i++)
00686                 {
00687                     if (false != gb_scux_info_drv.info_ch[i].enabled)
00688                     {
00689                         break;
00690                     }
00691                 }
00692 
00693                 if (SCUX_CH_NUM == i)
00694                 {
00695                     gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
00696                     uninit_all_flag = true;
00697                 }
00698 
00699                 if (0 == was_masked)
00700                 {
00701                     __enable_irq();
00702                 }
00703 
00704                 if (false != uninit_all_flag)
00705                 {
00706                     /* uninitialize driver infomation */
00707                     uninit_ercd = SCUX_CmnUnInitialize();
00708                     if (ESUCCESS != uninit_ercd)
00709                     {
00710                         retval = uninit_ercd;
00711                     }
00712 
00713                     gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
00714                 }
00715             }
00716             else
00717             {
00718                 gb_scux_info_drv.drv_stat = SCUX_DRV_INIT;
00719             }
00720         }
00721     }
00722     
00723     return retval;
00724 }
00725 
00726 /******************************************************************************
00727 End of function SCUX_InitializeOne
00728 ******************************************************************************/
00729 
00730 /**************************************************************************//**
00731 * Function Name: SCUX_UnInitializeOne
00732 * @brief         Uninit SCUX driver.
00733 *
00734 *                Description:<br>
00735 *                
00736 * @param[in]     channel    :unInitialize channel number.
00737 * @retval        None.
00738 ******************************************************************************/
00739 void SCUX_UnInitializeOne(const int_t channel)
00740 {
00741     osStatus sem_ercd;
00742     int_t    ercd;
00743     int_t    scux_ch_count;
00744     int_t    ssif_ch_count;
00745     bool_t   uninit_all_flag = false;
00746     uint32_t i;
00747     int_t    was_masked;
00748 
00749     scux_ch_count = channel;
00750     if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
00751     {
00752         /* check ch_stat whether going transfer */
00753         if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) && 
00754             (SCUX_CH_INIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
00755             (SCUX_CH_STOP != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat))
00756         {
00757             /* The exclusive access control (interrupt disabled) starts */
00758 #if defined (__ICCARM__)
00759             was_masked = __disable_irq_iar();
00760 #else
00761             was_masked = __disable_irq();
00762 #endif
00763 
00764             /* This exclusive access control ends in the SCUX_IoctlClearStop */
00765             /* call the __enable_irq in the SCUX_IoctlClearStop */
00766             ercd = SCUX_IoctlClearStop(scux_ch_count, was_masked);
00767             if (ESUCCESS != ercd)
00768             {
00769                 /* NON_NOTICE_ASSERT: SCUX stop failed */
00770             }
00771             
00772             ercd = R_DMA_Free(gb_scux_info_drv.info_ch[scux_ch_count].dma_tx_ch, NULL);
00773             if (ESUCCESS != ercd)
00774             {
00775                  /* NON_NOTICE_ASSERT: DMA release failed */
00776             }
00777         }
00778     }
00779     
00780     if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
00781     {
00782         if (gb_scux_info_drv.info_ch[scux_ch_count].ch_stat == SCUX_CH_UNINIT)
00783         {
00784             /* NON_NOTICE_ASSERT: abnormal status */
00785         }
00786         
00787         /* uninit each resouces */
00788         gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
00789         
00790         if (NULL != gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
00791         {
00792             /* delete each semaphore  */
00793             sem_ercd = osSemaphoreRelease(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
00794             /* semaphore error check */
00795             if (osOK != sem_ercd)
00796             {
00797                 /* NON_NOTICE_ASSERT: semaphore error */
00798             }
00799 
00800             sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
00801             /* semaphore error check */
00802             if (osOK != sem_ercd)
00803             {
00804                 /* NON_NOTICE_ASSERT: semaphore error */
00805             }
00806 
00807             gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
00808         }
00809         
00810         /* delete queue */
00811         ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
00812         ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
00813         ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
00814         ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
00815     }
00816 
00817 #if defined (__ICCARM__)
00818     was_masked = __disable_irq_iar();
00819 #else
00820     was_masked = __disable_irq();
00821 #endif
00822 
00823     gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
00824 
00825     for (i = SCUX_CH_0; i < SCUX_CH_NUM; i++)
00826     {
00827         if (false != gb_scux_info_drv.info_ch[i].enabled)
00828         {
00829             break;
00830         }
00831     }
00832 
00833     if (SCUX_CH_NUM == i)
00834     {
00835         if (SCUX_DRV_INIT == gb_scux_info_drv.drv_stat)
00836         {
00837             gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
00838             uninit_all_flag = true;
00839         }
00840     }
00841 
00842     if (0 == was_masked)
00843     {
00844         __enable_irq();
00845     }
00846 
00847     if (false != uninit_all_flag)
00848     {
00849         for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
00850         {
00851             if (NULL != gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
00852             {
00853                 sem_ercd = osSemaphoreRelease(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
00854                 /* semaphore error check */
00855                 if (osOK != sem_ercd)
00856                 {
00857                     /* NON_NOTICE_ASSERT: semaphore error */
00858                 }
00859             }
00860         }
00861 
00862         if (NULL != gb_scux_info_drv.shared_info.sem_shared_access)
00863         {
00864             sem_ercd = osSemaphoreRelease(gb_scux_info_drv.shared_info.sem_shared_access);
00865             /* semaphore error check */
00866             if (osOK != sem_ercd)
00867             {
00868                 /* NON_NOTICE_ASSERT: semaphore error */
00869             }
00870         }
00871 
00872         /* uninitialize driver infomation */
00873         (void)SCUX_CmnUnInitialize();
00874 
00875         gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
00876     }
00877 }
00878 
00879 /******************************************************************************
00880 End of function SCUX_UnInitializeOne
00881 ******************************************************************************/
00882 #endif /* end mbed */
00883 
00884 /**************************************************************************//**
00885 * Function Name: SCUX_Initialize
00886 * @brief         Init SCUX driver.
00887 *
00888 *                Description:<br>
00889 *                
00890 * @param[in]     p_scux_init_param :Initialize parameter for SCUX. 
00891 * @retval        ESUCCESS -
00892 *                  Operation successful.
00893 *                EERROR -
00894 *                  Error occured.
00895 *                    error code -
00896 *                       ENOMEM : Making semaphore is failed.
00897 *                       EFAULT : Internal error is occured.
00898 ******************************************************************************/
00899 int_t SCUX_Initialize(const scux_channel_cfg_t * const p_scux_init_param)
00900 {
00901     int_t    retval = ESUCCESS;
00902     osStatus sem_ercd;
00903     int_t    scux_ch_count;
00904     int_t    audio_ch_count;
00905     scux_ssif_ch_num_t    ssif_ch_count;
00906     uint32_t cpg_value;
00907     bool_t   init_shared_flag = false;
00908     int_t    was_masked;
00909     volatile uint8_t dummy_buf;
00910 
00911     if (NULL == p_scux_init_param)
00912     {
00913         retval = EFAULT;
00914     }
00915     else
00916     {
00917         /* init channel management information */
00918         for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
00919         {
00920             if (false == p_scux_init_param[scux_ch_count].enabled)
00921             {
00922                 /* set disable parameter */
00923                 gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
00924                 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
00925             }
00926             else
00927             {
00928                 gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
00929     
00930                 /* copy parameter */
00931                 /* set interrupt parameter */
00932                 gb_scux_info_drv.info_ch[scux_ch_count].int_level = p_scux_init_param[scux_ch_count].int_level;
00933                         
00934                 /* set route parameter */
00935                 gb_scux_info_drv.info_ch[scux_ch_count].route_set = p_scux_init_param[scux_ch_count].route;
00936                 
00937                 /* set SRC paramter */
00938                 SCUX_IoctlSetSrcCfg(scux_ch_count, &p_scux_init_param[scux_ch_count].src_cfg);
00939                 
00940                 /* init SCUX parameter */
00941                 if ((SCUX_CH_0 == scux_ch_count) || (SCUX_CH_1 == scux_ch_count))
00942                 {
00943                     gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH0_1;
00944                 }
00945                 else
00946                 {
00947                     gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH2_3;
00948                 }
00949                 gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_tx = gb_dma_res_select_tx[scux_ch_count];
00950                 gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_rx = gb_dma_res_select_rx[scux_ch_count];
00951                 gb_scux_info_drv.info_ch[scux_ch_count].futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
00952                 gb_scux_info_drv.info_ch[scux_ch_count].err_stat_backup = ESUCCESS;
00953                 
00954                 /* init DVU parameter */
00955                 for (audio_ch_count = SCUX_AUDIO_CH_0; audio_ch_count < SCUX_AUDIO_CH_MAX; audio_ch_count++)
00956                 {
00957                     gb_scux_info_drv.info_ch[scux_ch_count].dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch_count] = false; 
00958                 }
00959                 gb_scux_info_drv.info_ch[scux_ch_count].dvu_setup = false;
00960              
00961                 if (false == init_shared_flag)
00962                 {
00963                     /* init MIX parameter */
00964                     gb_scux_info_drv.shared_info.mix_setup = false;
00965                     gb_scux_info_drv.shared_info.mix_run_ch = 0U;
00966                     gb_scux_info_drv.shared_info.mix_ssif_ch = 0U;
00967                     
00968                     /* init SSIF parameter */
00969                     for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
00970                     {
00971                         gb_scux_ssif_info[ssif_ch_count].ssif_setup = false;
00972                         gb_scux_ssif_info[ssif_ch_count].ssif_cfg.ssif_ch_num = ssif_ch_count;
00973                         gb_scux_ssif_info[ssif_ch_count].scux_channel = 0;
00974                         gb_scux_ssif_info[ssif_ch_count].pin_mode = SCUX_PIN_MODE_INDEPEND;
00975                     }
00976                     
00977                     /* init regsiter store value */
00978                     gb_scux_info_drv.shared_info.ssictrl_cim_value = SSICTRL_CIM_INIT_VALUE;
00979                 }
00980             
00981                 /* set register address */
00982                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg = &p_scux_ch_reg_addr_table[scux_ch_count];
00983                                        
00984                 if (false == init_shared_flag) {
00985 #if defined (__ICCARM__)
00986                     was_masked = __disable_irq_iar();
00987 #else
00988                     was_masked = __disable_irq();
00989 #endif
00990 
00991                     /* supply clock for SCUX */
00992                     cpg_value = (uint32_t)CPG.STBCR8 & ~(CPG_STBCR8_BIT_MSTP81);
00993                     CPG.STBCR8 = (uint8_t)cpg_value;
00994                     dummy_buf = CPG.STBCR8;
00995                     
00996                     if (0 == was_masked)
00997                     {
00998                         __enable_irq();
00999                     }
01000 
01001                     /* software reset */
01002                     SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
01003                     SCUX.SWRSR_CIM |= SWRSR_CIM_SWRST_SET;
01004                 }
01005                 
01006                 /* init DVU register */
01007                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
01008                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
01009                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
01010                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
01011                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
01012                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
01013                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
01014                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
01015                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
01016                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
01017                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
01018                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
01019                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
01020                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
01021                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
01022                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
01023                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
01024                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
01025                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
01026                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
01027                 
01028                 /* init SRC register */
01029                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
01030                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
01031                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
01032                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
01033                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
01034                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
01035                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
01036                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
01037                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
01038                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
01039                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
01040                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
01041                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
01042                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
01043                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
01044                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
01045                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
01046                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
01047                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
01048                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
01049                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
01050                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
01051                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
01052                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 = SRCIRR_2SRC0_INIT_VALUE;
01053                 
01054                 /* init FFU register */
01055                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
01056                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
01057                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
01058                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
01059                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
01060                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
01061                 
01062                 /* init FFD register */
01063                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
01064                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
01065                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
01066                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
01067                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
01068                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
01069                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
01070                 
01071                 /* init OPC register */
01072                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
01073                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
01074     
01075                 /* init IPC register */
01076                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
01077                 gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
01078     
01079                 /* init MIX register for each channel */
01080                 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
01081                 
01082                 /* init CIM register for each channel */
01083                 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
01084                 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
01085                 *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
01086                 
01087                 /* init shared register */
01088                 if (false == init_shared_flag)
01089                 {
01090                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
01091                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
01092                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
01093                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
01094                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
01095                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
01096                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->dmacr_cim) = DMACR_CIM_INIT_VALUE;
01097                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssirsel_cim) = SSIRSEL_CIM_INIT_VALUE;
01098                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssipmd_cim) = SSIPMD_CIM_INIT_VALUE;
01099                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssictrl_cim) = SSICTRL_CIM_INIT_VALUE;
01100                     *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
01101                 }
01102                 
01103                 if (false == init_shared_flag)
01104                 {
01105                     /* set SSIF register */
01106                     for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
01107                     {
01108                         gb_scux_ssif_info[ssif_ch_count].p_scux_ssif_reg = p_scux_ssif_ch_reg_addr[ssif_ch_count];
01109                     }
01110                 }
01111             
01112                 /* set  semaphore parameter */
01113                 gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = osSemaphoreCreate(p_semdef_ch_scux_access[scux_ch_count], 1);
01114                 if (NULL == gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
01115                 {
01116                      retval = ENOMEM;
01117                 }
01118                 if ((ESUCCESS == retval) && (false == init_shared_flag))
01119                 {
01120                     for (ssif_ch_count = SCUX_SSIF_CH_0; ((ssif_ch_count < SCUX_SSIF_CH_NUM) && (ESUCCESS == retval)); ssif_ch_count++) 
01121                     {
01122                         gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = osSemaphoreCreate(p_semdef_ch_scux_ssif_access[ssif_ch_count], 1);
01123                         if (NULL == gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
01124                         {
01125                             retval = ENOMEM;
01126                         }
01127                     }
01128                 }
01129                 if ((ESUCCESS == retval) && (false == init_shared_flag))
01130                 {
01131                     gb_scux_info_drv.shared_info.sem_shared_access = osSemaphoreCreate(osSemaphore(scux_shared_access), 1);
01132                     if (NULL == gb_scux_info_drv.shared_info.sem_shared_access)
01133                     {
01134                         retval = ENOMEM;
01135                     }
01136                 }
01137                 
01138                 if (false == init_shared_flag)
01139                 {
01140                     init_shared_flag = true;
01141                 }
01142                 
01143                 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_INIT;
01144             }
01145         }
01146     }
01147     
01148     if (ESUCCESS != retval)
01149     {
01150         for (scux_ch_count = SCUX_SSIF_CH_0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
01151         {
01152             if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
01153             {
01154                 /* semaphore delete */
01155                 sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
01156                 /* semaphore error check */
01157                 if (osOK != sem_ercd)
01158                 {
01159                     /* set error return value */
01160                     retval = EFAULT;
01161                 }
01162                 
01163                 gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
01164                 gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
01165             }
01166         }
01167         
01168         for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
01169         {
01170             sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
01171             /* semaphore error check */
01172             if (osOK != sem_ercd)
01173             {
01174                 /* set error return value */
01175                 retval = EFAULT;
01176             }
01177         }
01178                 
01179         sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
01180         /* semaphore error check */
01181         if (osOK != sem_ercd)
01182         {
01183             /* set error return value */
01184             retval = EFAULT;
01185         }
01186         
01187         gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
01188     }
01189     else
01190     {
01191         gb_scux_info_drv.drv_stat = SCUX_DRV_INIT;
01192     }
01193     
01194     return retval;
01195 }
01196 
01197 /******************************************************************************
01198 End of function SCUX_Initialize
01199 ******************************************************************************/
01200 
01201 /**************************************************************************//**
01202 * Function Name: SCUX_UnInitialize
01203 * @brief         Uninit SCUX driver.
01204 *
01205 *                Description:<br>
01206 *                
01207 * @param[in]     None. 
01208 * @retval        None.
01209 ******************************************************************************/
01210 void SCUX_UnInitialize(void)
01211 {
01212     osStatus sem_ercd;
01213     int_t    ercd;
01214     int_t    scux_ch_count;
01215     int_t    ssif_ch_count;
01216     uint32_t cpg_value;
01217     int_t    was_masked;
01218 
01219     for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
01220     {
01221         if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
01222         {
01223             /* check ch_stat whether going transfer */
01224             if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) && 
01225                 (SCUX_CH_INIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
01226                 (SCUX_CH_STOP != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat))
01227             {
01228 #if defined (__ICCARM__)
01229                 was_masked = __disable_irq_iar();
01230 #else
01231                 was_masked = __disable_irq();
01232 #endif
01233 
01234                 /* This exclusive access control ends in the SCUX_IoctlClearStop */
01235                 ercd = SCUX_IoctlClearStop(scux_ch_count, was_masked);
01236                 if (ESUCCESS != ercd)
01237                 {
01238                     /* NON_NOTICE_ASSERT: SCUX stop failed */
01239                 }
01240                 
01241                 ercd = R_DMA_Free(gb_scux_info_drv.info_ch[scux_ch_count].dma_tx_ch, NULL);
01242                 if (ESUCCESS != ercd)
01243                 {
01244                      /* NON_NOTICE_ASSERT: DMA release failed */
01245                 }
01246             }
01247         }
01248     }
01249     
01250     /* software reset */
01251     SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
01252 
01253     for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
01254     {
01255         if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
01256         {
01257             if (gb_scux_info_drv.info_ch[scux_ch_count].ch_stat == SCUX_CH_UNINIT)
01258             {
01259                 /* NON_NOTICE_ASSERT: abnormal status */
01260             }
01261             
01262             /* uninit each resouces */
01263             gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
01264             
01265             /* delete each semaphore  */
01266             sem_ercd = osSemaphoreRelease(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
01267             /* semaphore error check */
01268             if (osOK != sem_ercd)
01269             {
01270                 /* NON_NOTICE_ASSERT: semaphore error */
01271             }
01272             
01273             sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
01274             /* semaphore error check */
01275             if (osOK != sem_ercd)
01276             {
01277                 /* NON_NOTICE_ASSERT: semaphore error */
01278             }
01279             
01280             gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
01281             
01282             /* delete queue */
01283             ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
01284             ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
01285             ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
01286             ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
01287         }
01288     }
01289 
01290     for (ssif_ch_count = 0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
01291     {
01292         sem_ercd = osSemaphoreRelease(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
01293         /* semaphore error check */
01294         if (osOK != sem_ercd)
01295         {
01296             /* NON_NOTICE_ASSERT: semaphore error */
01297         }
01298             
01299         sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
01300         /* semaphore error check */
01301         if (osOK != sem_ercd)
01302         {
01303             /* NON_NOTICE_ASSERT: semaphore error */
01304         }
01305             
01306         gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
01307     }
01308             
01309     sem_ercd = osSemaphoreRelease(gb_scux_info_drv.shared_info.sem_shared_access);
01310     /* semaphore error check */
01311     if (osOK != sem_ercd)
01312     {
01313         /* NON_NOTICE_ASSERT: semaphore error */
01314     }
01315             
01316     sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
01317     /* semaphore error check */
01318     if (osOK != sem_ercd)
01319     {
01320         /* NON_NOTICE_ASSERT: semaphore error */
01321     }
01322             
01323     gb_scux_info_drv.shared_info.sem_shared_access = NULL;
01324          
01325 #if defined (__ICCARM__)
01326     was_masked = __disable_irq_iar();
01327 #else
01328     was_masked = __disable_irq();
01329 #endif
01330 
01331     /* stop clock for SCUX */
01332     cpg_value = ((uint32_t)CPG.STBCR8 | CPG_STBCR8_BIT_MSTP81);
01333     CPG.STBCR8 = (uint8_t)cpg_value;
01334           
01335     if (0 == was_masked)
01336     {
01337         /* enable all irq */
01338         __enable_irq();
01339     }
01340 
01341     gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
01342 }
01343 
01344 /******************************************************************************
01345 End of function SCUX_UnInitialize
01346 ******************************************************************************/
01347 
01348 /**************************************************************************//**
01349 * Function Name: SCUX_OpenChannel
01350 * @brief         Open SCUX driver channel.
01351 *
01352 *                Description:<br>
01353 *                
01354 * @param[in]     channel:open channel number.
01355 * @param[in]     flags:specifies the access mode whether the channel is 
01356 *                      opened for a read or a write
01357 * @retval        ESUCCESS: Operation successful.
01358 *                ENOMEM: Create queue is failed.
01359 *                EMFILE: Allocate DMA ch for write is failed.
01360 ******************************************************************************/
01361 
01362 int_t SCUX_OpenChannel(const int_t channel, const int_t flags)
01363 {
01364     int_t    retval;
01365     
01366     /* create write request queue */
01367     retval = ahf_create(&gb_scux_info_drv.info_ch[channel].tx_que, AHF_LOCKINT);
01368     if (ESUCCESS != retval)
01369     {
01370         retval = ENOMEM;
01371     }
01372     else
01373     {
01374         /* create read request queue */
01375         retval = ahf_create(&gb_scux_info_drv.info_ch[channel].rx_que, AHF_LOCKINT);
01376         if (ESUCCESS != retval)
01377         {
01378             retval = ENOMEM;
01379         }
01380     }
01381     
01382     if (ESUCCESS == retval)
01383     {
01384         SCUX_InterruptInit(channel);
01385         
01386         /* init channel information parameter */
01387         gb_scux_info_drv.info_ch[channel].open_flags = flags;
01388         gb_scux_info_drv.info_ch[channel].p_tx_aio = NULL;
01389         gb_scux_info_drv.info_ch[channel].p_tx_next_aio = NULL;
01390         gb_scux_info_drv.info_ch[channel].p_rx_aio = NULL;
01391         gb_scux_info_drv.info_ch[channel].p_rx_next_aio = NULL;
01392         gb_scux_info_drv.info_ch[channel].p_ssif_info1 = NULL;
01393         gb_scux_info_drv.info_ch[channel].p_ssif_info2 = NULL;
01394         gb_scux_info_drv.info_ch[channel].p_ssif_info3 = NULL;
01395         gb_scux_info_drv.info_ch[channel].p_flush_callback = NULL;
01396         gb_scux_info_drv.info_ch[channel].p_tx_dummy_data = &gb_scux_write_dummy_buf[0];
01397         gb_scux_info_drv.info_ch[channel].p_rx_dummy_data = &gb_scux_read_dummy_buf[0];
01398         
01399         /* get DMA channel for write */
01400         gb_scux_info_drv.info_ch[channel].dma_tx_ch = R_DMA_Alloc(DMA_ALLOC_CH, NULL);
01401         if (EERROR == gb_scux_info_drv.info_ch[channel].dma_tx_ch)
01402         {
01403             retval = EMFILE;
01404         }
01405         else
01406         {
01407             gb_scux_info_drv.info_ch[channel].ch_stat = SCUX_CH_STOP;
01408         }
01409 
01410     }
01411     
01412     return retval;
01413 }
01414 
01415 /******************************************************************************
01416 End of function SCUX_OpenChannel
01417 ******************************************************************************/
01418 
01419 /**************************************************************************//**
01420 * Function Name: SCUX_CloseChannel
01421 * @brief         Close SCUX driver channel.
01422 *
01423 *                Description:<br>
01424 *                
01425 * @param[in]     channel: SCUX channel number.
01426 * @retval        ESUCCESS : Operation successful.
01427 *                EFAULT : Internal error is occured.
01428 ******************************************************************************/
01429 
01430 int_t  SCUX_CloseChannel(const int_t channel)
01431 {
01432     int_t    retval = ESUCCESS;
01433     int_t    ercd;
01434     int_t    was_masked;
01435 
01436     /* check ch_stat whether going transfer */
01437     if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[channel].ch_stat) && 
01438         (SCUX_CH_INIT != gb_scux_info_drv.info_ch[channel].ch_stat) &&
01439         (SCUX_CH_STOP != gb_scux_info_drv.info_ch[channel].ch_stat))
01440     {
01441 #if defined (__ICCARM__)
01442         was_masked = __disable_irq_iar();
01443 #else
01444         was_masked = __disable_irq();
01445 #endif
01446 
01447         /* This exclusive access control ends in the SCUX_IoctlClearStop */
01448         ercd = SCUX_IoctlClearStop(channel, was_masked);
01449         if (ESUCCESS != ercd)
01450         {
01451             retval = EFAULT;
01452         }
01453     }
01454     
01455     if (ESUCCESS == retval)
01456     {
01457         /* delete queue */
01458         ahf_cancelall(&gb_scux_info_drv.info_ch[channel].tx_que);
01459         ahf_destroy(&gb_scux_info_drv.info_ch[channel].tx_que);
01460         ahf_cancelall(&gb_scux_info_drv.info_ch[channel].rx_que);
01461         ahf_destroy(&gb_scux_info_drv.info_ch[channel].rx_que);
01462 
01463         SCUX_InterruptUninit(channel);
01464         
01465         ercd = R_DMA_Free(gb_scux_info_drv.info_ch[channel].dma_tx_ch, NULL);
01466         if (ESUCCESS != ercd)
01467         {
01468             retval = EFAULT;
01469         }
01470         else
01471         {
01472             /* reset error status */
01473             gb_scux_info_drv.info_ch[channel].err_stat_backup = ESUCCESS;
01474             /* set channel status to open */
01475             gb_scux_info_drv.info_ch[channel].ch_stat = SCUX_CH_INIT;
01476         }
01477     }
01478 
01479     return retval;
01480 }
01481 
01482 /******************************************************************************
01483 End of function SCUX_CloseChannel
01484 ******************************************************************************/
01485 
01486 
01487 /**************************************************************************//**
01488 * Function Name: SCUX_CheckParam
01489 * @brief         Check SCUX parameter.
01490 *
01491 *                Description:<br>
01492 *                
01493 * @param[in]     *p_scux_info_ch:SCUX channel information.
01494 * @retval        ESUCCESS : Parameter is no problems.
01495 *                EACCES : DVU setting isn't performed when DVU is used.
01496 *                EACCES : MIX setting isn't performed when MIX is used.
01497 *                EACCES : SSIF setting isn't performed when SSIF is used.
01498 *                EPERM : Parameter is unexpected value.
01499 *                EFAULT : Internal error is occured.
01500 ******************************************************************************/
01501 
01502 int_t SCUX_CheckParam(scux_info_ch_t * const p_scux_info_ch)
01503 {
01504     int_t retval = ESUCCESS;
01505     uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT] = {SCUX_SSIF_NO_USE_CH, SCUX_SSIF_NO_USE_CH, SCUX_SSIF_NO_USE_CH};
01506     bool_t use_mix_flag = false;
01507     
01508     if (NULL == p_scux_info_ch)
01509     {
01510         retval = EFAULT;
01511     }
01512     else
01513     {
01514         /* check route parameter */
01515         if (((SCUX_ROUTE_SRC_MEM_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_MEM_MAX <= p_scux_info_ch->route_set)) &&
01516             ((SCUX_ROUTE_SRC_SSIF_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_SSIF_MAX <= p_scux_info_ch->route_set)) &&
01517             ((SCUX_ROUTE_SRC_MIX_SSIF_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_MIX_SSIF_MAX <= p_scux_info_ch->route_set)))
01518         {
01519             retval = EPERM;
01520         }
01521         else
01522         {
01523             /* check route whether include SCUX channel */
01524             switch (p_scux_info_ch->channel)
01525             {
01526                 case SCUX_CH_0:
01527                     if ((SCUX_ROUTE_SRC0_MEM != p_scux_info_ch->route_set)         &&
01528                         (SCUX_ROUTE_SRC0_SSIF0 != p_scux_info_ch->route_set)       && 
01529                         (SCUX_ROUTE_SRC0_MIX_SSIF0 != p_scux_info_ch->route_set)   &&
01530                         (SCUX_ROUTE_SRC0_SSIF3 != p_scux_info_ch->route_set)       &&
01531                         (SCUX_ROUTE_SRC0_MIX_SSIF3 != p_scux_info_ch->route_set)   &&
01532                         (SCUX_ROUTE_SRC0_SSIF012 != p_scux_info_ch->route_set)     &&
01533                         (SCUX_ROUTE_SRC0_MIX_SSIF012 != p_scux_info_ch->route_set) &&
01534                         (SCUX_ROUTE_SRC0_SSIF345 != p_scux_info_ch->route_set)     &&
01535                         (SCUX_ROUTE_SRC0_MIX_SSIF345 != p_scux_info_ch->route_set))
01536                     {       
01537                         retval = EPERM;
01538                     }
01539                 break;
01540                 
01541                 case SCUX_CH_1:
01542                     if ((SCUX_ROUTE_SRC1_MEM != p_scux_info_ch->route_set)         &&
01543                         (SCUX_ROUTE_SRC1_SSIF0 != p_scux_info_ch->route_set)       && 
01544                         (SCUX_ROUTE_SRC1_MIX_SSIF0 != p_scux_info_ch->route_set)   &&
01545                         (SCUX_ROUTE_SRC1_SSIF3 != p_scux_info_ch->route_set)       &&
01546                         (SCUX_ROUTE_SRC1_MIX_SSIF3 != p_scux_info_ch->route_set)   &&
01547                         (SCUX_ROUTE_SRC1_SSIF012 != p_scux_info_ch->route_set)     &&
01548                         (SCUX_ROUTE_SRC1_MIX_SSIF012 != p_scux_info_ch->route_set) &&
01549                         (SCUX_ROUTE_SRC1_SSIF345 != p_scux_info_ch->route_set)     &&
01550                         (SCUX_ROUTE_SRC1_MIX_SSIF345 != p_scux_info_ch->route_set))
01551                     {  
01552                         retval = EPERM;
01553                     }
01554                 break;
01555                 
01556                 case SCUX_CH_2:
01557                     if ((SCUX_ROUTE_SRC2_MEM != p_scux_info_ch->route_set)         &&
01558                         (SCUX_ROUTE_SRC2_MIX_SSIF0 != p_scux_info_ch->route_set)   && 
01559                         (SCUX_ROUTE_SRC2_SSIF1 != p_scux_info_ch->route_set)       &&
01560                         (SCUX_ROUTE_SRC2_MIX_SSIF3 != p_scux_info_ch->route_set)   &&
01561                         (SCUX_ROUTE_SRC2_SSIF4 != p_scux_info_ch->route_set)       &&
01562                         (SCUX_ROUTE_SRC2_MIX_SSIF012 != p_scux_info_ch->route_set) &&
01563                         (SCUX_ROUTE_SRC2_MIX_SSIF345 != p_scux_info_ch->route_set))
01564                     {  
01565                         retval = EPERM;
01566                     }
01567                 break;
01568                 
01569                 case SCUX_CH_3:
01570                     if ((SCUX_ROUTE_SRC3_MEM != p_scux_info_ch->route_set)          && 
01571                         (SCUX_ROUTE_SRC3_MIX_SSIF0 != p_scux_info_ch->route_set)    && 
01572                         (SCUX_ROUTE_SRC3_SSIF2 != p_scux_info_ch->route_set)        &&
01573                         (SCUX_ROUTE_SRC3_MIX_SSIF3 != p_scux_info_ch->route_set)    &&
01574                         (SCUX_ROUTE_SRC3_SSIF5 != p_scux_info_ch->route_set)        &&
01575                         (SCUX_ROUTE_SRC3_MIX_SSIF012 != p_scux_info_ch->route_set)  &&
01576                         (SCUX_ROUTE_SRC3_MIX_SSIF345 != p_scux_info_ch->route_set))
01577                     {  
01578                         retval = EPERM;
01579                     }
01580                 break;
01581                 
01582                 default :
01583                     /* NOTREACHED on At the time of a normal performance */
01584                     retval = EFAULT;
01585                 break;
01586                 
01587             }
01588         }
01589     
01590         if (ESUCCESS == retval)
01591         {
01592             /* set using SSIF channel and MIX information */
01593             switch (p_scux_info_ch->route_set)
01594             {
01595                 case SCUX_ROUTE_SRC0_MEM :
01596                     /* fall through */
01597                 case SCUX_ROUTE_SRC1_MEM :
01598                     /* fall through */
01599                 case SCUX_ROUTE_SRC2_MEM :
01600                     /* fall through */
01601                 case SCUX_ROUTE_SRC3_MEM :
01602                     /* do nothing, when mem to mem route is setting */
01603                 break;
01604                 
01605                 case SCUX_ROUTE_SRC0_SSIF0 :
01606                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
01607                 break;
01608                 
01609                 case SCUX_ROUTE_SRC0_SSIF012 :
01610                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
01611                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_1;
01612                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_2;
01613                 break;
01614                 
01615                 case SCUX_ROUTE_SRC0_SSIF3 :
01616                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
01617                 break;                
01618                 
01619                 case SCUX_ROUTE_SRC0_SSIF345 :
01620                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
01621                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_4;
01622                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_5;
01623                 break;
01624                 
01625                 case SCUX_ROUTE_SRC1_SSIF0 :
01626                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
01627                 break;
01628                 
01629                 case SCUX_ROUTE_SRC1_SSIF012 :
01630                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
01631                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_1;
01632                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_2;
01633                 break;
01634                 
01635                 case SCUX_ROUTE_SRC1_SSIF3 :
01636                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
01637                 break;                
01638                 
01639                 case SCUX_ROUTE_SRC1_SSIF345 :
01640                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
01641                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_4;
01642                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_5;
01643                 break;      
01644                 
01645                 case SCUX_ROUTE_SRC2_SSIF1 :
01646                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_1;
01647                 break;                
01648                           
01649                 case SCUX_ROUTE_SRC2_SSIF4 :
01650                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_4;
01651                 break;                
01652                 
01653                 case SCUX_ROUTE_SRC3_SSIF2 :
01654                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_2;
01655                 break;
01656                 
01657                 case SCUX_ROUTE_SRC3_SSIF5 :
01658                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_5;
01659                 break;                                
01660                 
01661                 case SCUX_ROUTE_SRC0_MIX_SSIF0 :
01662                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
01663                     use_mix_flag = true;
01664                 break;
01665 
01666                 case SCUX_ROUTE_SRC0_MIX_SSIF012 :
01667                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
01668                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
01669                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
01670                     use_mix_flag = true;
01671                 break;
01672 
01673                 case SCUX_ROUTE_SRC0_MIX_SSIF3 :
01674                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
01675                     use_mix_flag = true;
01676                 break;
01677 
01678                 case SCUX_ROUTE_SRC0_MIX_SSIF345 :
01679                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
01680                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
01681                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
01682                     use_mix_flag = true;
01683                 break;
01684 
01685                 case SCUX_ROUTE_SRC1_MIX_SSIF0 :
01686                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
01687                     use_mix_flag = true;
01688                 break;
01689 
01690                 case SCUX_ROUTE_SRC1_MIX_SSIF012 :
01691                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
01692                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
01693                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
01694                     use_mix_flag = true;
01695                 break;
01696 
01697                 case SCUX_ROUTE_SRC1_MIX_SSIF3 :
01698                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
01699                     use_mix_flag = true;
01700                 break;
01701 
01702                 case SCUX_ROUTE_SRC1_MIX_SSIF345 :
01703                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
01704                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
01705                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
01706                     use_mix_flag = true;
01707                 break;
01708 
01709                 case SCUX_ROUTE_SRC2_MIX_SSIF0 :
01710                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
01711                     use_mix_flag = true;
01712                 break;
01713 
01714                 case SCUX_ROUTE_SRC2_MIX_SSIF012 :
01715                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
01716                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
01717                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
01718                     use_mix_flag = true;
01719                 break;
01720 
01721                 case SCUX_ROUTE_SRC2_MIX_SSIF3 :
01722                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
01723                     use_mix_flag = true;
01724                 break;
01725 
01726                 case SCUX_ROUTE_SRC2_MIX_SSIF345 :
01727                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
01728                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
01729                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
01730                     use_mix_flag = true;
01731                 break;
01732 
01733                 case SCUX_ROUTE_SRC3_MIX_SSIF0 :
01734                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
01735                     use_mix_flag = true;
01736                 break;
01737 
01738                 case SCUX_ROUTE_SRC3_MIX_SSIF012 :
01739                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
01740                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
01741                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
01742                     use_mix_flag = true;
01743                 break;
01744 
01745                 case SCUX_ROUTE_SRC3_MIX_SSIF3 :
01746                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
01747                     use_mix_flag = true;
01748                 break;
01749 
01750                 case SCUX_ROUTE_SRC3_MIX_SSIF345 :
01751                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
01752                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
01753                     ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
01754                     use_mix_flag = true;
01755                 break;
01756                         
01757                 default :
01758                     /* NOTREACHED on At the time of a normal performance */
01759                     retval = EPERM;
01760                 break;
01761             }
01762         }
01763         
01764         if (ESUCCESS == retval) 
01765         {
01766             if (false != p_scux_info_ch->src_cfg.src_enable)
01767             {
01768                 retval = SCUX_CheckSrcParam(p_scux_info_ch, ssif_ch);
01769             }
01770             else
01771             {
01772                 if (false != p_scux_info_ch->src_cfg.mode_sync)
01773                 {
01774                     /* src disable is async mode only */
01775                     retval = EPERM;
01776                 }
01777             }
01778         }
01779         
01780         if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1])
01781         {
01782             /* check parameter for SSIF direct route */
01783             if ((ESUCCESS == retval) && (false != p_scux_info_ch->dvu_cfg.dvu_enable))
01784             {
01785                 retval = SCUX_CheckDvuParam(p_scux_info_ch);
01786             }
01787             
01788             if (ESUCCESS == retval)
01789             {
01790                 retval = SCUX_CheckSsifParam(p_scux_info_ch, ssif_ch, use_mix_flag);
01791             }
01792             
01793             if ((ESUCCESS == retval) && (false != use_mix_flag))
01794             {
01795                 retval = SCUX_CheckMixParam(p_scux_info_ch);
01796             }
01797         }
01798     }
01799 
01800     return retval;
01801 }
01802 
01803 /******************************************************************************
01804 End of function SCUX_CheckParam
01805 ******************************************************************************/
01806 
01807 /**************************************************************************//**
01808 * Function Name: SCUX_CheckSrcParam
01809 * @brief         Check SRC parameter and set rate parameter to SCUX information.
01810 *
01811 *                Description:<br>
01812 *                
01813 * @param[in]     *p_scux_info_ch : SCUX channel information.
01814 * @param[in]     ssif_ch : Used ssif channel number.
01815 * @param[in]     use_mix_flag : Flag of Using MIX .
01816 * @retval        ESUCCESS : Parameter is no problems.
01817 *                EPERM : Parameter is unexpected value.
01818 *                EFAULT : Internal error is occured.
01819 ******************************************************************************/
01820 
01821 static int_t SCUX_CheckSrcParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT])
01822 {
01823     int_t retval = ESUCCESS;
01824     uint32_t ssif_arrange_num;
01825     uint32_t rate_sample_ratio;
01826     uint32_t max_conv_rate;
01827     uint32_t min_conv_rate = 0;
01828     uint32_t freq_value = 0;
01829     int_t audio_ch;
01830     uint32_t max_rate;
01831     
01832     if ((NULL == p_scux_info_ch) || (NULL == ssif_ch))
01833     {
01834         retval = EFAULT;
01835     }
01836     else
01837     {
01838         /* check use ch */
01839         if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_1 == p_scux_info_ch->channel))
01840         {
01841             if ((SCUX_USE_CH_1 != p_scux_info_ch->src_cfg.use_ch) && 
01842                 (SCUX_USE_CH_2 != p_scux_info_ch->src_cfg.use_ch) && 
01843                 (SCUX_USE_CH_4 != p_scux_info_ch->src_cfg.use_ch) && 
01844                 (SCUX_USE_CH_6 != p_scux_info_ch->src_cfg.use_ch) && 
01845                 (SCUX_USE_CH_8 != p_scux_info_ch->src_cfg.use_ch))
01846             {
01847                 retval = EPERM;
01848             }
01849         }
01850         else
01851         {
01852             /* on SCUX2, SCUX3, enable audio channel is only 1ch and 2ch */
01853             if ((SCUX_USE_CH_1 != p_scux_info_ch->src_cfg.use_ch) && (SCUX_USE_CH_2 != p_scux_info_ch->src_cfg.use_ch))
01854             {
01855                 retval = EPERM;
01856             }           
01857         }
01858         
01859         if (ESUCCESS == retval)
01860         {
01861             /* if using SSIF, 1ch audio channel is disabled */
01862             if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]) && (SCUX_USE_CH_1 == p_scux_info_ch->src_cfg.use_ch))
01863             {
01864                 retval = EPERM;
01865             }
01866         }
01867             
01868         if (ESUCCESS == retval)
01869         {
01870             /* if  mutiple SSIF channel and enable TDM mode, only 2ch audio channel is enabled */
01871             for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
01872             {
01873                 if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
01874                 {
01875                     if (false != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.use_tdm)
01876                     {
01877                         if (SCUX_USE_CH_2 == p_scux_info_ch->src_cfg.use_ch)
01878                         {
01879                             retval = EPERM;
01880                         }
01881                     }
01882                 }
01883             }
01884         }
01885         
01886         if (ESUCCESS == retval)
01887         {
01888             /* multiple SSIF ch check (multiple SSIF is used SSIF2) */
01889             if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]) && (SCUX_USE_CH_6 != p_scux_info_ch->src_cfg.use_ch))
01890             {
01891                 retval = EPERM;
01892             }
01893         }
01894         
01895         if (ESUCCESS == retval)
01896         {
01897             /* check word length */
01898             if ((SCUX_DATA_LEN_MIN >= p_scux_info_ch->src_cfg.word_len) || (SCUX_DATA_LEN_MAX <= p_scux_info_ch->src_cfg.word_len))
01899             {
01900                 retval = EPERM;
01901             }
01902         }
01903         
01904         if (ESUCCESS == retval)
01905         {
01906             /* check delay mode */
01907             if ((SCUX_DELAY_MIN >= p_scux_info_ch->src_cfg.delay_mode) || (SCUX_DELAY_MAX <= p_scux_info_ch->src_cfg.delay_mode))
01908             {
01909                 retval = EPERM;
01910             }
01911             else
01912             {
01913                 /* enable audio channel is less than 2ch when delay mode is enabled */
01914                 if ((SCUX_DELAY_NORMAL != p_scux_info_ch->src_cfg.delay_mode) && (SCUX_USE_CH_2 < p_scux_info_ch->src_cfg.use_ch))
01915                 {
01916                     retval = EPERM;
01917                 }
01918             }
01919         }
01920         
01921         if (ESUCCESS == retval)
01922         {
01923             /* check rate setting */
01924             if (false != p_scux_info_ch->src_cfg.mode_sync)
01925             {
01926                 /* check input rate */
01927                 if ((SCUX_SYNC_RATE_8      == p_scux_info_ch->src_cfg.input_rate_sync)  ||
01928                     (SCUX_SYNC_RATE_11_025  == p_scux_info_ch->src_cfg.input_rate_sync) ||
01929                     (SCUX_SYNC_RATE_12      == p_scux_info_ch->src_cfg.input_rate_sync) ||
01930                     (SCUX_SYNC_RATE_16      == p_scux_info_ch->src_cfg.input_rate_sync) ||
01931                     (SCUX_SYNC_RATE_22_05   == p_scux_info_ch->src_cfg.input_rate_sync) ||
01932                     (SCUX_SYNC_RATE_24      == p_scux_info_ch->src_cfg.input_rate_sync) ||
01933                     (SCUX_SYNC_RATE_32      == p_scux_info_ch->src_cfg.input_rate_sync) ||
01934                     (SCUX_SYNC_RATE_44_1    == p_scux_info_ch->src_cfg.input_rate_sync) ||
01935                     (SCUX_SYNC_RATE_48      == p_scux_info_ch->src_cfg.input_rate_sync) ||
01936                     (SCUX_SYNC_RATE_64      == p_scux_info_ch->src_cfg.input_rate_sync) ||
01937                     (SCUX_SYNC_RATE_88_2    == p_scux_info_ch->src_cfg.input_rate_sync) ||
01938                     (SCUX_SYNC_RATE_96      == p_scux_info_ch->src_cfg.input_rate_sync))
01939                 {
01940                     /* enable rate is less than 66KHz on 6ch */
01941                     if ((SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch) && 
01942                         ((SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
01943                          (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync)))
01944                     {
01945                         retval = EPERM;
01946                     }
01947                     
01948                     /* enable rate is less than 49KHz on 8ch */
01949                     if ((SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch) && 
01950                         ((SCUX_SYNC_RATE_64 == p_scux_info_ch->src_cfg.input_rate_sync)   ||
01951                          (SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
01952                          (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync)))
01953                     {
01954                         retval = EPERM;
01955                     }
01956                 }
01957                 else
01958                 {
01959                     retval = EPERM;
01960                 }
01961                 
01962                 if (ESUCCESS == retval) {
01963                     /* check output rate */
01964                     if ((SCUX_SYNC_RATE_8   == p_scux_info_ch->src_cfg.output_rate_sync)  ||
01965                         (SCUX_SYNC_RATE_16   == p_scux_info_ch->src_cfg.output_rate_sync) ||
01966                         (SCUX_SYNC_RATE_24   == p_scux_info_ch->src_cfg.output_rate_sync) ||
01967                         (SCUX_SYNC_RATE_32   == p_scux_info_ch->src_cfg.output_rate_sync) ||
01968                         (SCUX_SYNC_RATE_44_1 == p_scux_info_ch->src_cfg.output_rate_sync) ||
01969                         (SCUX_SYNC_RATE_48   == p_scux_info_ch->src_cfg.output_rate_sync) ||
01970                         (SCUX_SYNC_RATE_96   == p_scux_info_ch->src_cfg.output_rate_sync))
01971                     {
01972                         /* enable rate is less than 66KHz on 6ch, enable rate is less than 49KHz on 8ch  */
01973                         if ((SCUX_USE_CH_6 <= p_scux_info_ch->src_cfg.use_ch) && 
01974                             (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.output_rate_sync))
01975                         {
01976                             retval = EPERM;
01977                         }
01978                     }
01979                     else
01980                     {
01981                         retval = EPERM;
01982                     }
01983                 }
01984                 
01985                 if (ESUCCESS == retval)
01986                 {
01987                     p_scux_info_ch->input_rate = p_scux_info_ch->src_cfg.input_rate_sync;
01988                     p_scux_info_ch->output_rate = p_scux_info_ch->src_cfg.output_rate_sync;
01989                 }
01990             }
01991             else
01992             {
01993                 /* async mode */
01994                 /* check input rate */
01995                 /* get input source clock */
01996                 switch (p_scux_info_ch->src_cfg.input_clk_async)
01997                 {
01998                     case SCUX_CLK_AUDIO_CLK :
01999                         freq_value = SCUX_AUDIO_CLK;
02000                     break;                  
02001                     
02002                     case SCUX_CLK_AUDIO_X1 :
02003                         freq_value = SCUX_AUDIO_X1;
02004                     break;
02005                     
02006                     case SCUX_CLK_MLB_CLK :
02007                         freq_value = SCUX_MLB_CLK;
02008                     break;
02009     
02010                     case SCUX_CLK_USB_X1 :
02011                         freq_value = SCUX_USB_X1;
02012                     break;
02013     
02014                     case SCUX_CLK_CLKP1_2 :
02015                         freq_value = SCUX_CLKLP1_DIV2;
02016                     break;
02017     
02018                     case SCUX_CLK_MTU_TIOC3A :
02019                         freq_value = p_scux_info_ch->src_cfg.freq_tioc3a;
02020                         if (0U == freq_value)
02021                         {
02022                             retval = EPERM;
02023                         }
02024                     break;
02025     
02026                     case SCUX_CLK_MTU_TIOC4A :
02027                         freq_value = p_scux_info_ch->src_cfg.freq_tioc4a;
02028                         if (0U == freq_value)
02029                         {
02030                             retval = EPERM;
02031                         }
02032                     break;
02033     
02034                     case SCUX_CLK_SSIF0_WS :
02035                         /* fall through */
02036                     case SCUX_CLK_SSIF1_WS :
02037                         /* fall through */
02038                     case SCUX_CLK_SSIF2_WS :
02039                         /* fall through */
02040                     case SCUX_CLK_SSIF3_WS :
02041                         /* fall through */
02042                     case SCUX_CLK_SSIF4_WS :
02043                         /* fall through */
02044                     case SCUX_CLK_SSIF5_WS :
02045                         freq_value = p_scux_info_ch->src_cfg.input_ws;
02046                         if (0U == freq_value)
02047                         {
02048                             retval = EPERM;
02049                         }
02050                     break;
02051                     
02052                     default :
02053                         /* NOTREACHED on At the time of a normal performance */
02054                         retval = EPERM;
02055                     break;
02056                 }
02057                     
02058                 if (ESUCCESS == retval)
02059                 { 
02060                     /* check devide rate and devide source clock */
02061                     /* check source clock isn't SSIF WS signal */
02062                     if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
02063                         (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
02064                         (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
02065                         (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 
02066                         (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
02067                         (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
02068                     {
02069                         if ((0U != (p_scux_info_ch->src_cfg.input_div_async % SCUX_EVEN_VALUE_DIV)) ||
02070                             (SCUX_MAX_DIV_CLK < p_scux_info_ch->src_cfg.input_div_async))
02071                         {
02072                             retval = EPERM;
02073                         }
02074                         else
02075                         {
02076                             if (0U == p_scux_info_ch->src_cfg.input_div_async)
02077                             {
02078                                 /* 0 is a same size */
02079                                 p_scux_info_ch->input_rate = freq_value;
02080                             }
02081                             else{
02082                                 p_scux_info_ch->input_rate = freq_value / p_scux_info_ch->src_cfg.input_div_async;
02083                             }
02084                         }
02085                     }
02086                     else
02087                     {
02088                         p_scux_info_ch->input_rate = freq_value;
02089                     }
02090                     
02091                     if (ESUCCESS == retval)
02092                     {
02093                         /* check input frequency is enable range */
02094                         if (SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch)
02095                         {
02096                             max_rate = SCUX_MAX_FREQ_CH6;
02097                         }
02098                         else if (SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch)
02099                         {
02100                             max_rate = SCUX_MAX_FREQ_CH8;
02101                         }
02102                         else
02103                         {
02104                             max_rate = SCUX_MAX_FREQ_CH1_4;
02105                         }
02106                         
02107                         if ((SCUX_MIN_FREQ > p_scux_info_ch->input_rate) || 
02108                            (max_rate < p_scux_info_ch->input_rate))
02109                         {
02110                             retval = EPERM;
02111                         }
02112                     }
02113                 }
02114                     
02115                 if (ESUCCESS == retval)
02116                 {
02117                     /* if output route is SSIF direct route ,WS signal frequency is used */
02118                     if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1])
02119                     {
02120                         if ((SCUX_SYNC_RATE_8      == p_scux_info_ch->src_cfg.output_ws)  ||
02121                             (SCUX_SYNC_RATE_11_025  == p_scux_info_ch->src_cfg.output_ws) ||
02122                             (SCUX_SYNC_RATE_12      == p_scux_info_ch->src_cfg.output_ws) ||
02123                             (SCUX_SYNC_RATE_16      == p_scux_info_ch->src_cfg.output_ws) ||
02124                             (SCUX_SYNC_RATE_22_05   == p_scux_info_ch->src_cfg.output_ws) ||
02125                             (SCUX_SYNC_RATE_24      == p_scux_info_ch->src_cfg.output_ws) ||
02126                             (SCUX_SYNC_RATE_32      == p_scux_info_ch->src_cfg.output_ws) ||
02127                             (SCUX_SYNC_RATE_44_1    == p_scux_info_ch->src_cfg.output_ws) ||
02128                             (SCUX_SYNC_RATE_48      == p_scux_info_ch->src_cfg.output_ws) ||
02129                             (SCUX_SYNC_RATE_64      == p_scux_info_ch->src_cfg.output_ws) ||
02130                             (SCUX_SYNC_RATE_88_2    == p_scux_info_ch->src_cfg.output_ws) ||
02131                             (SCUX_SYNC_RATE_96      == p_scux_info_ch->src_cfg.output_ws))
02132                         {
02133                             p_scux_info_ch->output_rate = p_scux_info_ch->src_cfg.output_ws;
02134                         }   
02135                         else
02136                         {
02137                             retval = EPERM;
02138                         }
02139                     }
02140                     else
02141                     {              
02142                         /* check output rate (mem to mem)*/
02143                         /* get output source clock */
02144                         switch (p_scux_info_ch->src_cfg.output_clk_async)
02145                         {
02146                             case SCUX_CLK_AUDIO_CLK :
02147                                 freq_value = SCUX_AUDIO_CLK;
02148                             break;
02149                                                         
02150                             case SCUX_CLK_AUDIO_X1 :
02151                                 freq_value = SCUX_AUDIO_X1;
02152                             break;
02153                           
02154                             case SCUX_CLK_MLB_CLK :
02155                                 freq_value = SCUX_MLB_CLK;
02156                             break;
02157             
02158                             case SCUX_CLK_USB_X1 :
02159                                 freq_value = SCUX_USB_X1;
02160                             break;
02161             
02162                             case SCUX_CLK_CLKP1_2 :
02163                                 freq_value = SCUX_CLKLP1_DIV2;
02164                             break;
02165         
02166                             case SCUX_CLK_MTU_TIOC3A :
02167                                 freq_value = p_scux_info_ch->src_cfg.freq_tioc3a;
02168                                 if (0U == freq_value)
02169                                 {
02170                                     retval = EPERM;
02171                                 }
02172                             break;
02173             
02174                             case SCUX_CLK_MTU_TIOC4A :
02175                                 freq_value = p_scux_info_ch->src_cfg.freq_tioc4a;
02176                                 if (0U == freq_value)
02177                                 {
02178                                     retval = EPERM;
02179                                 }
02180                             break;
02181             
02182                             case SCUX_CLK_SSIF0_WS :
02183                                 /* fall through */
02184                             case SCUX_CLK_SSIF1_WS :
02185                                 /* fall through */
02186                             case SCUX_CLK_SSIF2_WS :
02187                                 /* fall through */
02188                             case SCUX_CLK_SSIF3_WS :
02189                                 /* fall through */
02190                             case SCUX_CLK_SSIF4_WS :
02191                                 /* fall through */
02192                             case SCUX_CLK_SSIF5_WS :
02193                                 freq_value = p_scux_info_ch->src_cfg.output_ws;
02194                                 if (0U == freq_value)
02195                                 {
02196                                     retval = EPERM;
02197                                 }
02198                             break;
02199                             
02200                             default :
02201                                 /* error check is gone when route is other than SSIF */
02202                                 if (SCUX_ROUTE_SSIF != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
02203                                 {
02204                                     retval = EPERM;
02205                                 }
02206                             break;
02207                         }
02208                     }
02209                     
02210                     if (ESUCCESS == retval)
02211                     {         
02212                         /* check devide rate on only except for SSIF route, MISRA R1.1 mesure */          
02213                         if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
02214                             (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
02215                             (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
02216                             (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async) && 
02217                             (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
02218                             (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.output_clk_async))
02219                         {                  
02220                             if ((0U != (p_scux_info_ch->src_cfg.output_div_async % SCUX_EVEN_VALUE_DIV)) ||
02221                                 (SCUX_MAX_DIV_CLK < p_scux_info_ch->src_cfg.output_div_async))
02222                             {
02223                                 retval = EPERM;
02224                             }
02225                         }
02226                     }
02227 
02228                     if (ESUCCESS == retval)
02229                     {
02230                         /* check source clock isn't SSIF WS signal */
02231                         if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
02232                             (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
02233                             (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
02234                             (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async) && 
02235                             (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
02236                             (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.output_clk_async))
02237                         {
02238                             if (0U == p_scux_info_ch->src_cfg.output_div_async)
02239                             {
02240                                 /* 0 is a same size */
02241                                 p_scux_info_ch->output_rate = freq_value;
02242                             }
02243                             else
02244                             {
02245                                 p_scux_info_ch->output_rate = freq_value / p_scux_info_ch->src_cfg.output_div_async;
02246                             }
02247                         }
02248                         else
02249                         {
02250                             p_scux_info_ch->output_rate = freq_value;
02251                         }
02252                         /* check input frequency is enable range */
02253                         if (SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch)
02254                         {
02255                             max_rate = SCUX_MAX_FREQ_CH6;
02256                         }
02257                         else if (SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch)
02258                         {
02259                             max_rate = SCUX_MAX_FREQ_CH8;
02260                         }
02261                         else
02262                         {
02263                             max_rate = SCUX_MAX_FREQ_CH1_4;
02264                         }
02265                         
02266                         if ((SCUX_MIN_FREQ > p_scux_info_ch->output_rate) || 
02267                             (max_rate < p_scux_info_ch->output_rate))
02268                         {
02269                             retval = EPERM;
02270                         }
02271                         
02272                     }
02273                 }
02274             }
02275             
02276             if (ESUCCESS == retval)
02277             {
02278                 /* check convert rate range */
02279                 max_conv_rate = SCUX_MAX_CONV_RATE;
02280                 switch (p_scux_info_ch->src_cfg.delay_mode)
02281                 {
02282                     case SCUX_DELAY_NORMAL :
02283                         switch (p_scux_info_ch->src_cfg.use_ch)
02284                         {
02285                             case SCUX_USE_CH_1 :
02286                                 /* fall through */
02287                             case SCUX_USE_CH_2 :
02288                                 min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH1_2;
02289                             break;
02290                             
02291                             case SCUX_USE_CH_4 :
02292                                 min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH4;
02293                             break;
02294                             
02295                             case SCUX_USE_CH_6 :
02296                                 min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH6;
02297                             break;
02298                             
02299                             case SCUX_USE_CH_8 :
02300                                 min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH8;
02301                             break;                          
02302                     
02303                             default :
02304                                 /* NOTREACHED on At the time of a normal performance */
02305                                 retval = EPERM;
02306                             break;
02307                         }                   
02308                     break;
02309                         
02310                     case SCUX_DELAY_LOW_DELAY1 :
02311                         min_conv_rate = SCUX_MIN_CONV_RATE_DELAY1;
02312                     break;
02313     
02314                     case SCUX_DELAY_LOW_DELAY2 :
02315                         min_conv_rate = SCUX_MIN_CONV_RATE_DELAY2;
02316                     break;                
02317                         
02318                     default :
02319                         /* NOTREACHED on At the time of a normal performance */
02320                         retval = EPERM;
02321                     break;
02322                 }
02323                         
02324                 rate_sample_ratio = ((p_scux_info_ch->output_rate * SCUX_RATE_INT_CONV_VALUE) / p_scux_info_ch->input_rate);
02325                 if ((min_conv_rate > rate_sample_ratio) || (max_conv_rate < rate_sample_ratio))
02326                 {
02327                     retval = EPERM;
02328                 }
02329             }
02330         }
02331     
02332         if (ESUCCESS == retval)
02333         {
02334             /* check wait time */
02335             if (SCUX_MAX_WAIT_TIME < p_scux_info_ch->src_cfg.wait_sample)
02336             {
02337                 retval = EPERM;
02338             }
02339         }
02340         
02341         if (ESUCCESS == retval)
02342         {
02343             /* check min rate ratio */
02344             if ((SCUX_MIN_RATE_MIN_PAERCENTAGE > (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage) || 
02345                 (SCUX_MIN_RATE_MAX_PAERCENTAGE < (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage))
02346             {
02347                 retval = EPERM;
02348             }
02349         }
02350         
02351         if (ESUCCESS == retval)
02352         {
02353             /* check input data position */
02354             for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
02355             {
02356                 if ((SCUX_AUDIO_CH_MIN >= p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch]) || 
02357                     (SCUX_AUDIO_CH_MAX <= p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch]))
02358                 {
02359                     retval = EPERM;
02360                 }
02361             }
02362         }
02363     }
02364 
02365     return retval;
02366 }
02367 
02368 /******************************************************************************
02369 End of function SCUX_CheckSrcParam
02370 ******************************************************************************/
02371 
02372 /**************************************************************************//**
02373 * Function Name: SCUX_CheckDvuParam
02374 * @brief         Check DVU parameter.
02375 *
02376 *                Description:<br>
02377 *                
02378 * @param[in]     *p_scux_info_ch:SCUX channel information.
02379 * @retval        ESUCCESS : Parameter is no problems.
02380 *                EACCES : DVU setting isn't performed when DVU is used.
02381 *                EPERM : Parameter is unexpected value.
02382 *                EFAULT : Internal error is occured.
02383 ******************************************************************************/
02384 
02385 static int_t SCUX_CheckDvuParam(const scux_info_ch_t * const p_scux_info_ch)
02386 {
02387     int_t retval = ESUCCESS;
02388     int_t audio_ch;
02389     uint32_t enable_ch_flag = false;
02390     
02391     if (NULL == p_scux_info_ch)
02392     {
02393         retval = EFAULT;
02394     }
02395     else
02396     {
02397         if (false == p_scux_info_ch->dvu_setup)
02398         {
02399             retval = EACCES;
02400         }
02401         else
02402         {
02403             if (false != p_scux_info_ch->dvu_cfg.dvu_enable)
02404             {
02405                 /* check digital volume value */
02406                 if (false !=  p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable)
02407                 {
02408                     /* check digital volume value */
02409                     for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
02410                     {
02411                         if (SCUX_MAX_DIGITAL_VOLUME < p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch])
02412                         {
02413                             retval = EPERM;
02414                         }
02415                     }
02416                 }
02417                 
02418                 /* check ramp volume value */
02419                 for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
02420                 {
02421                     enable_ch_flag |= (uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch];
02422                 }
02423                 
02424                 if ((ESUCCESS == retval) && (false != (bool_t)enable_ch_flag))
02425                 {
02426                     /* check ramp up period */
02427                     if ((p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period <= SCUX_DVU_TIME_MIN) ||
02428                         (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period >= SCUX_DVU_TIME_MAX))
02429                     {
02430                         retval = EPERM;
02431                     }
02432                     
02433                     if (ESUCCESS == retval) 
02434                     {
02435                         /* check ramp down period */
02436                         if ((p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period <= SCUX_DVU_TIME_MIN) ||
02437                             (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period >= SCUX_DVU_TIME_MAX))
02438                         {
02439                             retval = EPERM;
02440                         }
02441                     }
02442                 
02443                     if (ESUCCESS == retval)
02444                     {
02445                         /* check ramp volume */
02446                         if (SCUX_MAX_RAMP_VOLUME < p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol)
02447                         {
02448                             retval = EPERM;
02449                         }
02450                     }
02451                 
02452                     if (ESUCCESS != retval)
02453                     {
02454                         /* check wait time */
02455                         if (SCUX_MAX_WAIT_TIME < p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time)
02456                         {
02457                             retval = EPERM;
02458                         }
02459                     }
02460                 }
02461             }
02462         }
02463     }
02464     
02465     return retval;
02466 }
02467 
02468 /******************************************************************************
02469 End of function SCUX_CheckDvuParam
02470 ******************************************************************************/
02471 
02472 /**************************************************************************//**
02473 * Function Name: SCUX_CheckSsifParam
02474 * @brief         Check SSIF parameter.
02475 *
02476 *                Description:<br>
02477 *                
02478 * @param[in]     *p_scux_info_ch : SCUX channel information.
02479 * @param[in]     ssif_ch : Used ssif channel number.
02480 * @param[in]     use_mix_flag : Flag of Using MIX .
02481 * @retval        ESUCCESS : Parameter is no problems.
02482 *                EACCES : SSIF setting isn't performed when SSIF is used.
02483 *                EACCES : SSIF channel is already used.
02484 *                EACCES : When use MIX, it is a setup which does not agree in a route setup. 
02485 *                EPERM : Parameter is unexpected value.
02486 *                EFAULT : Internal error is occured.
02487 ******************************************************************************/
02488 
02489 static int_t SCUX_CheckSsifParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT], const bool_t use_mix_flag)
02490 {
02491     int_t retval = ESUCCESS;
02492     uint32_t ssif_arrange_num;
02493     uint32_t mix_ssif_ch_bit = 0;
02494     scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
02495     
02496     if ((NULL == p_info_drv) || (NULL == p_scux_info_ch) || (NULL == ssif_ch)) 
02497     {
02498         retval = EFAULT;
02499     }
02500     else
02501     {
02502         if (false == use_mix_flag)
02503         {
02504             /* used SSIF channel check no used MIX route */
02505             for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
02506             {
02507                 if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
02508                 {
02509                     /* check SSIF is already setup */
02510                     if (false == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_setup)
02511                     {
02512                         retval = EACCES;
02513                     }
02514                     else
02515                     {
02516                         /* used SSIF channel is checked by other SCUX channel */
02517                         if (0 != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel)
02518                         {
02519                             retval = EACCES;
02520                         }
02521                     }
02522                 }
02523             }
02524         }
02525         else
02526         {
02527             /* used SSIF channel check on MIX route */
02528             for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
02529             {
02530                 if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
02531                 {
02532                     /* clear SCUX_SSIF_use_mix_flag and get SSIF channel number */
02533                     mix_ssif_ch_bit |= (1U << ssif_ch[ssif_arrange_num]);
02534                     /* check SSIF is already setup */
02535                     if (false == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_setup)
02536                     {
02537                         retval = EACCES;
02538                     }
02539                 }
02540             }
02541             if (ESUCCESS == retval)
02542             {
02543                 /* used SSIF channel check, on MIX route check */
02544                 if (0U != p_info_drv->shared_info.mix_ssif_ch)
02545                 {
02546                     /* In the MIX setup for the and after 2times, it is checked that same SSIF ch on 1st setting is set up */
02547                     if (p_info_drv->shared_info.mix_ssif_ch != mix_ssif_ch_bit)
02548                     {
02549                         retval = EACCES;
02550                     }   
02551                 }
02552                 else
02553                 {
02554                     /*It checks that SSIF channel is not used once on first MIX setup */
02555                     if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2])
02556                     {
02557                         if ((0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]].scux_channel) ||
02558                             (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]].scux_channel) ||
02559                             (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3]].scux_channel))
02560                         {
02561                             retval = EACCES;
02562                         }
02563                     }
02564                     else
02565                     {
02566                         if (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]].scux_channel)
02567                         {
02568                             retval = EACCES;
02569                         }
02570                     }
02571                 }
02572             }
02573         }
02574                 
02575         /* each SSIF parameter check */
02576         for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
02577         {
02578             /* used SSIF channel check, on SSIF direct route check */
02579             if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
02580             {
02581                 
02582                 /* check system word */
02583                 if ((gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word <= SCUX_SSIF_SYSTEM_LEN_MIN) ||
02584                     (gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word >= SCUX_SSIF_SYSTEM_LEN_MAX))
02585                 {
02586                     retval = EPERM;
02587                 }
02588                 else
02589                 {
02590                     /* check system word >= data word */
02591                     /* The combination applicable to error only of data word of 24bit and system word of 16bit */
02592                     if ((SCUX_DATA_LEN_16 != p_scux_info_ch->src_cfg.word_len) && 
02593                         (SCUX_SSIF_SYSTEM_LEN_16 == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word))
02594                     {
02595                         retval = EPERM;
02596                     }
02597                 }
02598     
02599                 if (ESUCCESS == retval)
02600                 {
02601                     /* if multiple channel is used, TDM is disable */
02602                     if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]) &&
02603                         (false != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.use_tdm))
02604                     {
02605                         retval = EPERM;
02606                     }
02607                 }
02608                 if (ESUCCESS == retval)
02609                 {
02610                     retval = SCUX_CheckSsifClockDiv(p_scux_info_ch, ssif_ch[ssif_arrange_num]);
02611                 }
02612                 
02613                 if (ESUCCESS == retval)
02614                 {
02615                     gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel 
02616                     = (int_t)((uint32_t)gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel | (1U << p_scux_info_ch->channel));
02617                 }
02618             }
02619         }
02620         
02621         if (ESUCCESS == retval)
02622         {
02623             /* set SSIF information structure pointer */
02624             if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2])
02625             {
02626                 p_scux_info_ch->p_ssif_info1 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]];
02627                 p_scux_info_ch->p_ssif_info2 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]];
02628                 p_scux_info_ch->p_ssif_info3 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3]];
02629             }
02630             else
02631             {
02632                 p_scux_info_ch->p_ssif_info1 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]];
02633                 p_scux_info_ch->p_ssif_info2 = NULL;
02634                 p_scux_info_ch->p_ssif_info3 = NULL;
02635             }
02636         }
02637     }
02638     
02639     return retval;
02640 }
02641 
02642 /******************************************************************************
02643 End of function SCUX_CheckSsifParam
02644 ******************************************************************************/
02645 
02646 /**************************************************************************//**
02647 * Function Name: SCUX_CheckMixParam
02648 * @brief         Check MIX parameter.
02649 *
02650 *                Description:<br>
02651 *                
02652 * @param[in]     *p_scux_info_ch:SCUX channel information.
02653 * @retval        ESUCCESS : Parameter is no problems.
02654 *                EACCES : MIX setting isn't performed when MIX is used.
02655 *                EPERM : Parameter is unexpected value.
02656 *                EFAULT : Internal error is occured.
02657 ******************************************************************************/
02658 
02659 static int_t SCUX_CheckMixParam(const scux_info_ch_t * const p_scux_info_ch)
02660 {
02661     int_t retval = ESUCCESS;
02662     int_t scux_ch;
02663     int_t audio_ch;
02664     scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
02665     
02666     if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
02667     { 
02668         retval = EFAULT;
02669     }
02670     else
02671     {
02672         if (false == p_info_drv->shared_info.mix_setup)
02673         {
02674             retval = EACCES;
02675         }
02676         else
02677         {
02678             if (false != p_info_drv->shared_info.mixmode_ramp)
02679             {
02680                 /* check ramp up time */
02681                 if ((SCUX_MIX_TIME_MIN >= p_info_drv->shared_info.up_period) ||
02682                     (SCUX_MIX_TIME_MAX <= p_info_drv->shared_info.up_period))
02683                 {
02684                     retval = EPERM;
02685                 }
02686                 
02687                 /* check ramp down time */
02688                 if ((SCUX_MIX_TIME_MIN >= p_info_drv->shared_info.down_period) ||
02689                     (SCUX_MIX_TIME_MAX <= p_info_drv->shared_info.down_period))
02690                 {
02691                     retval = EPERM;
02692                 }
02693             }
02694             
02695             /* check MIX volume */
02696             for (scux_ch = SCUX_CH_0; ((ESUCCESS == retval) && (SCUX_CH_NUM > scux_ch)); scux_ch++)
02697             {
02698                 /* register set on the channel itself which sets up or channel which has already MIX operated */
02699                 if ((scux_ch == p_scux_info_ch->channel) ||
02700                     (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch))))
02701                 {
02702                     if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[scux_ch])
02703                     {
02704                         retval = EPERM;
02705                     }
02706                 }
02707             }
02708                     
02709             /* check output data position */
02710             for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
02711             {
02712                 /* check min rate ratio */
02713                 if ((SCUX_AUDIO_CH_MIN >= p_info_drv->shared_info.select_out_data_ch[audio_ch]) || 
02714                     (SCUX_AUDIO_CH_MAX <= p_info_drv->shared_info.select_out_data_ch[audio_ch]))
02715                 {
02716                     retval = EPERM;
02717                 }
02718             }
02719         }
02720     }
02721     
02722     return retval;
02723 }
02724 
02725 /******************************************************************************
02726 End of function SCUX_CheckMixParam
02727 ******************************************************************************/
02728 
02729 /**************************************************************************//**
02730 * Function Name: SCUX_StrNLen
02731 * @brief         computes the length of the string
02732 *
02733 *                Description:<br>
02734 *                if string is longer than maxlen, this function return maxlen
02735 * @param[in]     p_str      :pointer of string 
02736 * @param[in]     maxlen     :maximum length of inspection
02737 * @retval        'number of characters in the string' or 'maxlen'
02738 ******************************************************************************/
02739 size_t SCUX_StrNLen(const char_t* p_str, size_t maxlen)
02740 {
02741     size_t ret_len;
02742 
02743     if (NULL == p_str)
02744     {
02745         /* character string does not exist */
02746         ret_len = 0;
02747     }
02748     else
02749     {
02750         /* ->IPA P1.3.1 Even if a sign is positive, even a negative is no problem. */
02751         for (ret_len = 0; (maxlen != 0U) && (*p_str != '\0'); ret_len++)
02752         /* <-IPA P1.3.1 */
02753         {
02754             maxlen--;
02755             p_str++;
02756         }
02757     }
02758 
02759     return ret_len;
02760 }
02761 
02762 /******************************************************************************
02763 End of function SCUX_StrNLen
02764 ******************************************************************************/
02765 #if(1) /* mbed */
02766 /**************************************************************************//**
02767 * Function Name: SCUX_CmnUnInitialize
02768 * @brief         uninitialize driver infomation.
02769 *
02770 *                Description:<br>
02771 *                
02772 * @param[in]     None.
02773 * @retval        ESUCCESS : Parameter is no problems.
02774 *                EFAULT : Internal error is occured.
02775 ******************************************************************************/
02776 static int_t SCUX_CmnUnInitialize(void)
02777 {
02778     int_t    retval = ESUCCESS;
02779     osStatus sem_ercd;
02780     int_t    ssif_ch_count;
02781     uint32_t cpg_value;
02782     uint32_t was_masked;
02783     volatile uint8_t dummy_buf;
02784 
02785     /* software reset */
02786     SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
02787 
02788     for (ssif_ch_count = 0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
02789     {
02790         if (NULL != gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
02791         {
02792             sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
02793             /* semaphore error check */
02794             if (osOK != sem_ercd)
02795             {
02796                 /* set error return value */
02797                  retval = EFAULT;
02798             }
02799 
02800             gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
02801         }
02802     }
02803 
02804     if (NULL != gb_scux_info_drv.shared_info.sem_shared_access)
02805     {
02806         sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
02807         /* semaphore error check */
02808         if (osOK != sem_ercd)
02809         {
02810             /* set error return value */
02811             retval = EFAULT;
02812         }
02813 
02814         gb_scux_info_drv.shared_info.sem_shared_access = NULL;
02815     }
02816 
02817 #if defined (__ICCARM__)
02818     was_masked = __disable_irq_iar();
02819 #else
02820     was_masked = __disable_irq();
02821 #endif
02822 
02823     /* stop clock for SCUX */
02824     cpg_value = ((uint32_t)CPG.STBCR8 | CPG_STBCR8_BIT_MSTP81);
02825     CPG.STBCR8 = (uint8_t)cpg_value;
02826     dummy_buf = CPG.STBCR8;
02827 
02828     if (0U == was_masked)
02829     {
02830         /* enable all irq */
02831         __enable_irq();
02832     }
02833 
02834     return retval;
02835 }
02836 
02837 /******************************************************************************
02838 End of function SCUX_CmnUnInitialize
02839 ******************************************************************************/
02840 #endif /* end mbed */