RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.
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R_BSP_SsifDef.h
00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer 00021 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 /**************************************************************************//** 00024 * @file R_BSP_SsifDef.h 00025 * @brief SSIF defines 00026 ******************************************************************************/ 00027 00028 #ifndef R_BSP_SSIF_DEF_H 00029 #define R_BSP_SSIF_DEF_H 00030 00031 /****************************************************************************** 00032 Includes <System Includes> , "Project Includes" 00033 ******************************************************************************/ 00034 00035 #ifdef __cplusplus 00036 extern "C" 00037 { 00038 #endif /* __cplusplus */ 00039 00040 /****************************************************************************** 00041 Defines 00042 *****************************************************************************/ 00043 00044 /****************************************************************************** 00045 Constant Macros 00046 *****************************************************************************/ 00047 #define SSIF_NUM_CHANS (6u) /**< Number of SSIF channels */ 00048 00049 #define SSIF_CFG_DISABLE_ROMDEC_DIRECT (0x0u) /* Disable SSIRDR->STRMDIN0 route */ 00050 #define SSIF_CFG_ENABLE_ROMDEC_DIRECT (0xDEC0DEC1u) /* Enable SSIRDR->STRMDIN0 route */ 00051 00052 /****************************************************************************** 00053 Function Macros 00054 *****************************************************************************/ 00055 00056 /****************************************************************************** 00057 Enumerated Types 00058 *****************************************************************************/ 00059 00060 /** SSICR:CKS(Clock source for oversampling) */ 00061 typedef enum 00062 { 00063 SSIF_CFG_CKS_AUDIO_X1 = 0, /**< select AUDIO_X1 */ 00064 SSIF_CFG_CKS_AUDIO_CLK = 1 /**< select AUIDIO_CLK */ 00065 } ssif_chcfg_cks_t; 00066 00067 /** SSICR:CHNL(Audio channels per system word) */ 00068 typedef enum 00069 { 00070 SSIF_CFG_MULTI_CH_1 = 0, /**< 1ch within systemword (on tdm=0) */ 00071 SSIF_CFG_MULTI_CH_2 = 1, /**< 2ch within systemword (on tdm=0) */ 00072 SSIF_CFG_MULTI_CH_3 = 2, /**< 3ch within systemword (on tdm=0) */ 00073 SSIF_CFG_MULTI_CH_4 = 3 /**< 4ch within systemword (on tdm=0) */ 00074 } ssif_chcfg_multi_ch_t; 00075 00076 /** SSICR:DWL(Data word length) */ 00077 typedef enum 00078 { 00079 SSIF_CFG_DATA_WORD_8 = 0, /**< Data word length 8 */ 00080 SSIF_CFG_DATA_WORD_16 = 1, /**< Data word length 16 */ 00081 SSIF_CFG_DATA_WORD_18 = 2, /**< Data word length 18 */ 00082 SSIF_CFG_DATA_WORD_20 = 3, /**< Data word length 20 */ 00083 SSIF_CFG_DATA_WORD_22 = 4, /**< Data word length 22 */ 00084 SSIF_CFG_DATA_WORD_24 = 5, /**< Data word length 24 */ 00085 SSIF_CFG_DATA_WORD_32 = 6 /**< Data word length 32 */ 00086 } ssif_chcfg_data_word_t; 00087 00088 /** SSICR:SWL(System word length) */ 00089 typedef enum 00090 { 00091 SSIF_CFG_SYSTEM_WORD_8 = 0, /**< System word length 8 */ 00092 SSIF_CFG_SYSTEM_WORD_16 = 1, /**< System word length 16 */ 00093 SSIF_CFG_SYSTEM_WORD_24 = 2, /**< System word length 24 */ 00094 SSIF_CFG_SYSTEM_WORD_32 = 3, /**< System word length 32 */ 00095 SSIF_CFG_SYSTEM_WORD_48 = 4, /**< System word length 48 */ 00096 SSIF_CFG_SYSTEM_WORD_64 = 5, /**< System word length 64 */ 00097 SSIF_CFG_SYSTEM_WORD_128 = 6, /**< System word length 128 */ 00098 SSIF_CFG_SYSTEM_WORD_256 = 7 /**< System word length 256 */ 00099 } ssif_chcfg_system_word_t; 00100 00101 /** SSICR:SCKP(Clock polarity) */ 00102 typedef enum 00103 { 00104 SSIF_CFG_FALLING = 0, /**< Falling edge */ 00105 SSIF_CFG_RISING = 1 /**< Rising edge */ 00106 } ssif_chcfg_clock_pol_t; 00107 00108 /** SSICR:SWSP(Word select polarity) */ 00109 typedef enum 00110 { 00111 SSIF_CFG_WS_LOW = 0, /**< Low for ther 1st channel(not TDM) */ 00112 SSIF_CFG_WS_HIGH = 1 /**< High for the 1st channel(not TDM) */ 00113 } ssif_chcfg_ws_pol_t; 00114 00115 /** SSICR:SPDP(Serial padding polarity) */ 00116 typedef enum 00117 { 00118 SSIF_CFG_PADDING_LOW = 0, /**< Padding bits are low */ 00119 SSIF_CFG_PADDING_HIGH = 1 /**< Padding bits are high */ 00120 } ssif_chcfg_padding_pol_t; 00121 00122 /** SSICR:SDTA(Serial data alignment) */ 00123 typedef enum 00124 { 00125 SSIF_CFG_DATA_FIRST = 0, /**< Data first */ 00126 SSIF_CFG_PADDING_FIRST = 1 /**< Padding bits first */ 00127 } ssif_chcfg_serial_alignment_t; 00128 00129 /** SSICR:PDTA(Parallel data alignment) */ 00130 typedef enum 00131 { 00132 SSIF_CFG_LEFT = 0, /**< Left aligned */ 00133 SSIF_CFG_RIGHT = 1 /**< Right aligned */ 00134 } ssif_chcfg_parallel_alignment_t; 00135 00136 /** SSICR:DEL(Serial data delay) */ 00137 typedef enum 00138 { 00139 SSIF_CFG_DELAY = 0, /**< 1 clock delay */ 00140 SSIF_CFG_NO_DELAY = 1 /**< No delay */ 00141 } ssif_chcfg_ws_delay_t; 00142 00143 /** SSICR:CKDV(Serial oversampling clock division ratio) */ 00144 typedef enum 00145 { 00146 SSIF_CFG_CKDV_BITS_1 = 0, 00147 SSIF_CFG_CKDV_BITS_2 = 1, 00148 SSIF_CFG_CKDV_BITS_4 = 2, 00149 SSIF_CFG_CKDV_BITS_8 = 3, 00150 SSIF_CFG_CKDV_BITS_16 = 4, 00151 SSIF_CFG_CKDV_BITS_32 = 5, 00152 SSIF_CFG_CKDV_BITS_64 = 6, 00153 SSIF_CFG_CKDV_BITS_128 = 7, 00154 SSIF_CFG_CKDV_BITS_6 = 8, 00155 SSIF_CFG_CKDV_BITS_12 = 9, 00156 SSIF_CFG_CKDV_BITS_24 = 10, 00157 SSIF_CFG_CKDV_BITS_48 = 11, 00158 SSIF_CFG_CKDV_BITS_96 = 12 00159 } ssif_chcfg_ckdv_t; 00160 00161 00162 /** SNCR:SSIxNL(Serial sound interface channel x noise canceler enable) */ 00163 typedef enum 00164 { 00165 SSIF_CFG_DISABLE_NOISE_CANCEL = 0, /**< Not use noise cancel function */ 00166 SSIF_CFG_ENABLE_NOISE_CANCEL = 1 /**< Use noise cancel function */ 00167 } ssif_chcfg_noise_cancel_t; 00168 00169 00170 /** SSITDMR:TDM(TDM mode) */ 00171 typedef enum 00172 { 00173 SSIF_CFG_DISABLE_TDM = 0, /**< not TDM mode */ 00174 SSIF_CFG_ENABLE_TDM = 1 /**< set TDM mode */ 00175 } ssif_chcfg_tdm_t; 00176 00177 /****************************************************************************** 00178 Structures 00179 *****************************************************************************/ 00180 00181 /** It's used for ROMDEC direct transfer mode and the call back function registration. */ 00182 typedef struct 00183 { 00184 uint32_t mode; /**< Enable/Disable SSIRDR->STRMDIN0 route */ 00185 void (*p_cbfunc)(void); /**< SSIF error callback function */ 00186 } ssif_chcfg_romdec_t; 00187 00188 /** This structure contains the configuration settings */ 00189 typedef struct 00190 { 00191 bool enabled; /**< The enable flag for the channel */ 00192 uint8_t int_level; /**< Interrupt priority for the channel */ 00193 bool slave_mode; /**< Mode of operation */ 00194 uint32_t sample_freq; /**< Audio Sampling frequency(Hz) */ 00195 ssif_chcfg_cks_t clk_select; /**< SSICR-CKS : Audio clock select */ 00196 ssif_chcfg_multi_ch_t multi_ch; /**< SSICR-CHNL: Audio channels per system word */ 00197 ssif_chcfg_data_word_t data_word; /**< SSICR-DWL : Data word length */ 00198 ssif_chcfg_system_word_t system_word; /**< SSICR-SWL : System word length */ 00199 ssif_chcfg_clock_pol_t bclk_pol; /**< SSICR-SCKP: Bit Clock polarity */ 00200 ssif_chcfg_ws_pol_t ws_pol; /**< SSICR-SWSP: Word Clock polarity */ 00201 ssif_chcfg_padding_pol_t padding_pol; /**< SSICR-SPDP: Padding polarity */ 00202 ssif_chcfg_serial_alignment_t serial_alignment; /**< SSICR-SDTA: Serial data alignment */ 00203 ssif_chcfg_parallel_alignment_t parallel_alignment; /**< SSICR-PDTA: Parallel data alignment */ 00204 ssif_chcfg_ws_delay_t ws_delay; /**< SSICR-DEL : Serial clock delay */ 00205 ssif_chcfg_noise_cancel_t noise_cancel; /**< GPIO-SNCR : Noise cancel */ 00206 ssif_chcfg_tdm_t tdm_mode; /**< SSITDMR-TDM: TDM mode */ 00207 ssif_chcfg_romdec_t romdec_direct; /**< DMA : SSIRDR->STRMDIN0 route settings */ 00208 } ssif_channel_cfg_t; 00209 00210 /****************************************************************************** 00211 IOCTLS 00212 *****************************************************************************/ 00213 00214 #define SSIF_CONFIG_CHANNEL (7) 00215 #define SSIF_GET_STATUS (13) 00216 00217 #ifdef __cplusplus 00218 } 00219 #endif /* __cplusplus */ 00220 00221 #endif /* R_BSP_SSIF_DEF_H */
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