R_BSP_Scux.cpp

00001 /*******************************************************************************
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00021 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
00022 *******************************************************************************/
00023 
00024 #include "r_bsp_cmn.h"
00025 #include "R_BSP_Scux.h"
00026 #include "scux_if.h"
00027 
00028 #define CH_ERR_NUM                  (-1)     /* Channel error number */
00029 #define INT_LEVEL_MAX               (0xF7)   /* The maximum value of the interrupt level */
00030 #define REQ_BUFF_NUM_MIN            (1)      /* The minimum value of the request buffer */
00031 #define REQ_BUFF_NUM_MAX            (128)    /* The maximum value of the request buffer */
00032 #define INPUT_DIV_INIT_VALUE        (1000U)  /* The initial value of input divide ratio */
00033 #define OUTPUT_DIV_INIT_VALUE       (0U)     /* The initial value of output divide ratio  */
00034 #define INPUT_WS_INIT_VALUE         (1U)     /* The initial value of input WS frequency */
00035 #define OUTPUT_WS_INIT_VALUE        (96000U) /* The initial value of output WS frequency */
00036 #define FREQ_TIOC3A_INIT_VALUE      (1U)     /* The initial value of frequency of TIOC3 */
00037 #define FREQ_TIOC4A_INIT_VALUE      (1U)     /* The initial value of frequency of TIOC4 */
00038 #define WAIT_SAMPLE_INIT_VALUE      (0U)     /* The initial value of wait time */
00039 #define MIN_RATE_PER_INIT_VALUE     (98U)    /* The initial value of minimum rate */
00040 #define DIV_RATIO_CLK_AUDIO_22050HZ (1024U)  /* Divide ratio when the frequency is 22050Hz */
00041 #define DIV_RATIO_CLK_AUDIO_44100HZ (512U)   /* Divide ratio when the frequency is 44100Hz */
00042 #define DIV_RATIO_CLK_AUDIO_88200HZ (256U)   /* Divide ratio when the frequency is 88200Hz */
00043 #define DIV_RATIO_CLK_USB_24000HZ   (2000U)  /* Divide ratio when the frequency is 24000Hz */
00044 #define DIV_RATIO_CLK_USB_32000HZ   (1500U)  /* Divide ratio when the frequency is 36000Hz */
00045 #define DIV_RATIO_CLK_USB_48000HZ   (1000U)  /* Divide ratio when the frequency is 48000Hz */
00046 #define DIV_RATIO_CLK_USB_64000HZ   (750U)   /* Divide ratio when the frequency is 64000Hz */
00047 #define DIV_RATIO_CLK_USB_96000HZ   (500U)   /* Divide ratio when the frequency is 96000Hz */
00048 
00049 static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg);
00050 
00051 R_BSP_Scux::R_BSP_Scux(scux_ch_num_t channel, uint8_t int_level, int32_t max_write_num, int32_t max_read_num) {
00052     scux_channel_cfg_t scux_cfg;
00053     int32_t result;
00054     bool    init_result;
00055 
00056     if (channel >= SCUX_CH_NUM) {
00057         result = EERROR;
00058     } else if (int_level > INT_LEVEL_MAX) {
00059         result = EERROR;
00060     } else if ((max_write_num < REQ_BUFF_NUM_MIN) || (max_write_num > REQ_BUFF_NUM_MAX)) {
00061         result = EERROR;
00062     } else if ((max_read_num < REQ_BUFF_NUM_MIN) || (max_read_num > REQ_BUFF_NUM_MAX)) {
00063         result = EERROR;
00064     } else {
00065         result = R_BSP_CMN_Init();
00066         if (result == ESUCCESS) {
00067             scux_ch = (int32_t)channel;
00068 
00069             scux_cfg.enabled       = true;
00070             scux_cfg.int_level     = int_level;
00071 
00072             switch (channel) {
00073                 case SCUX_CH_0:
00074                     scux_cfg.route = SCUX_ROUTE_SRC0_MEM;
00075                     break;
00076                 case SCUX_CH_1:
00077                     scux_cfg.route = SCUX_ROUTE_SRC1_MEM;
00078                     break;
00079                 case SCUX_CH_2:
00080                     scux_cfg.route = SCUX_ROUTE_SRC2_MEM;
00081                     break;
00082                 case SCUX_CH_3:
00083                     scux_cfg.route = SCUX_ROUTE_SRC3_MEM;
00084                     break;
00085                 default:
00086                     /* NOTREACHED on At the time of a normal performance */
00087                     scux_cfg.route = SCUX_ROUTE_SRC0_MEM;
00088                     break;
00089             }
00090 
00091             init_result = set_src_init_cfg(&scux_cfg.src_cfg);
00092             if (init_result != false) {
00093                 init_result = init_channel(R_SCUX_MakeCbTbl_mbed(), (int32_t)channel, &scux_cfg, max_write_num, max_read_num);
00094                 if (init_result == false) {
00095                     result = EERROR;
00096                 }
00097             } else {
00098                 result = EERROR;
00099             }
00100         }
00101     }
00102 
00103     if (result != ESUCCESS) {
00104         scux_ch   = CH_ERR_NUM;
00105     }
00106 }
00107 
00108 R_BSP_Scux::~R_BSP_Scux(void) {
00109 }
00110 
00111 bool R_BSP_Scux::TransStart(void) {
00112     return ioctl(SCUX_IOCTL_SET_START, NULL);
00113 }
00114 
00115 bool R_BSP_Scux::FlushStop(void (* const callback)(int32_t)) {
00116     return ioctl(SCUX_IOCTL_SET_FLUSH_STOP, (void *)callback);
00117 }
00118 
00119 bool R_BSP_Scux::ClearStop(void) {
00120     return ioctl(SCUX_IOCTL_SET_CLEAR_STOP, NULL);
00121 }
00122 
00123 bool R_BSP_Scux::SetSrcCfg(const scux_src_usr_cfg_t * const p_src_param) {
00124     scux_src_cfg_t src_cfg;
00125     bool    init_result;
00126     bool    ret = true;
00127     int32_t i;
00128 
00129     if (scux_ch == CH_ERR_NUM) {
00130         ret = false;
00131     } else if (p_src_param == NULL) {
00132         ret = false;
00133     } else if ((p_src_param->mode_sync != false) && (p_src_param->src_enable == false)) {
00134         ret = false;
00135     } else {
00136         init_result = set_src_init_cfg(&src_cfg);
00137         if (init_result != true) {
00138             ret = false;
00139         } else {
00140             src_cfg.src_enable = p_src_param->src_enable;
00141             src_cfg.mode_sync  = p_src_param->mode_sync;
00142 
00143             switch (p_src_param->word_len) {
00144                 case SCUX_DATA_LEN_24:
00145                     /* fall through */
00146                 case SCUX_DATA_LEN_16:
00147                     /* fall through */
00148                 case SCUX_DATA_LEN_16_TO_24:
00149                     src_cfg.word_len = p_src_param->word_len;
00150                     break;
00151                 default:
00152                     ret = false;
00153                     break;
00154             }
00155 
00156             if (ret == true) {
00157                 if (p_src_param->mode_sync != false) {
00158                     switch (p_src_param->input_rate) {
00159                         case SAMPLING_RATE_8000HZ:
00160                             src_cfg.input_rate_sync = SCUX_SYNC_RATE_8;
00161                             break;
00162                         case SAMPLING_RATE_11025HZ:
00163                             src_cfg.input_rate_sync = SCUX_SYNC_RATE_11_025;
00164                             break;
00165                         case SAMPLING_RATE_12000HZ:
00166                             src_cfg.input_rate_sync = SCUX_SYNC_RATE_12;
00167                             break;
00168                         case SAMPLING_RATE_16000HZ:
00169                             src_cfg.input_rate_sync = SCUX_SYNC_RATE_16;
00170                             break;
00171                         case SAMPLING_RATE_22050HZ:
00172                             src_cfg.input_rate_sync = SCUX_SYNC_RATE_22_05;
00173                             break;
00174                         case SAMPLING_RATE_24000HZ:
00175                             src_cfg.input_rate_sync = SCUX_SYNC_RATE_24;
00176                             break;
00177                         case SAMPLING_RATE_32000HZ:
00178                             src_cfg.input_rate_sync = SCUX_SYNC_RATE_32;
00179                             break;
00180                         case SAMPLING_RATE_44100HZ:
00181                             src_cfg.input_rate_sync = SCUX_SYNC_RATE_44_1;
00182                             break;
00183                         case SAMPLING_RATE_48000HZ:
00184                             src_cfg.input_rate_sync = SCUX_SYNC_RATE_48;
00185                             break;
00186                         case SAMPLING_RATE_64000HZ:
00187                             src_cfg.input_rate_sync = SCUX_SYNC_RATE_64;
00188                             break;
00189                         case SAMPLING_RATE_88200HZ:
00190                             src_cfg.input_rate_sync = SCUX_SYNC_RATE_88_2;
00191                             break;
00192                         case SAMPLING_RATE_96000HZ:
00193                             src_cfg.input_rate_sync = SCUX_SYNC_RATE_96;
00194                             break;
00195                         default:
00196                             ret = false;
00197                             break;
00198                     }
00199                 } else {
00200                     switch (p_src_param->input_rate) {
00201                         case SAMPLING_RATE_22050HZ:
00202                             src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
00203                             src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_22050HZ;
00204                             break;
00205                         case SAMPLING_RATE_24000HZ:
00206                             src_cfg.input_clk_async = SCUX_CLK_USB_X1;
00207                             src_cfg.input_div_async = DIV_RATIO_CLK_USB_24000HZ;
00208                             break;
00209                         case SAMPLING_RATE_32000HZ:
00210                             src_cfg.input_clk_async = SCUX_CLK_USB_X1;
00211                             src_cfg.input_div_async = DIV_RATIO_CLK_USB_32000HZ;
00212                             break;
00213                         case SAMPLING_RATE_44100HZ:
00214                             src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
00215                             src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_44100HZ;
00216                             break;
00217                         case SAMPLING_RATE_48000HZ:
00218                             src_cfg.input_clk_async = SCUX_CLK_USB_X1;
00219                             src_cfg.input_div_async = DIV_RATIO_CLK_USB_48000HZ;
00220                             break;
00221                         case SAMPLING_RATE_64000HZ:
00222                             src_cfg.input_clk_async = SCUX_CLK_USB_X1;
00223                             src_cfg.input_div_async = DIV_RATIO_CLK_USB_64000HZ;
00224                             break;
00225                         case SAMPLING_RATE_88200HZ:
00226                             src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
00227                             src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_88200HZ;
00228                             break;
00229                         case SAMPLING_RATE_96000HZ:
00230                             src_cfg.input_clk_async = SCUX_CLK_USB_X1;
00231                             src_cfg.input_div_async = DIV_RATIO_CLK_USB_96000HZ;
00232                             break;
00233                         default:
00234                             ret = false;
00235                             break;
00236                     }
00237                 }
00238             }
00239 
00240             if (ret == true) {
00241                 if (p_src_param->mode_sync != false) {
00242                     switch (p_src_param->output_rate) {
00243                         case SAMPLING_RATE_44100HZ:
00244                             src_cfg.output_rate_sync = SCUX_SYNC_RATE_44_1;
00245                             break;
00246                         case SAMPLING_RATE_48000HZ:
00247                             src_cfg.output_rate_sync = SCUX_SYNC_RATE_48;
00248                             break;
00249                         case SAMPLING_RATE_96000HZ:
00250                             src_cfg.output_rate_sync = SCUX_SYNC_RATE_96;
00251                             break;
00252                         default:
00253                             ret = false;
00254                             break;
00255                     }
00256                 } else {
00257                     switch (p_src_param->output_rate) {
00258                         case SAMPLING_RATE_44100HZ:
00259                             src_cfg.output_ws = SAMPLING_RATE_44100HZ;
00260                             break;
00261                         case SAMPLING_RATE_48000HZ:
00262                             src_cfg.output_ws = SAMPLING_RATE_48000HZ;
00263                             break;
00264                         case SAMPLING_RATE_88200HZ:
00265                             src_cfg.output_ws = SAMPLING_RATE_88200HZ;
00266                             break;
00267                         case SAMPLING_RATE_96000HZ:
00268                             src_cfg.output_ws = SAMPLING_RATE_96000HZ;
00269                             break;
00270                         default:
00271                             ret = false;
00272                             break;
00273                     }
00274                 }
00275             }
00276 
00277             if (ret == true) {
00278                 for (i = 0; i < SCUX_USE_CH_2; i++) {
00279                     switch (p_src_param->select_in_data_ch[i]) {
00280                         case SELECT_IN_DATA_CH_0:
00281                             src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_0;
00282                             break;
00283                         case SELECT_IN_DATA_CH_1:
00284                             src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_1;
00285                             break;
00286                         default:
00287                             ret = false;
00288                             break;
00289                     }
00290                 }
00291             }
00292 
00293             if (ret == true) {
00294                 ret = ioctl(SCUX_IOCTL_SET_SRC_CFG, (void *)&src_cfg);
00295             }
00296         }
00297     }
00298 
00299     return ret;
00300 }
00301 
00302 bool R_BSP_Scux::GetWriteStat(uint32_t * const p_write_stat) {
00303     return ioctl(SCUX_IOCTL_GET_WRITE_STAT, (void *)p_write_stat);
00304 }
00305 
00306 bool R_BSP_Scux::GetReadStat(uint32_t * const p_read_stat) {
00307     return ioctl(SCUX_IOCTL_GET_READ_STAT, (void *)p_read_stat);
00308 }
00309 
00310 /**************************************************************************//**
00311 * Function Name: set_src_init_cfg
00312 * @brief         SRC configuration initialization.
00313 *
00314 *                Description:<br>
00315 *                
00316 * @param[in]     src_cfg SRC configuration. 
00317 * @retval        true  Setting success.
00318 *                false Setting fails.
00319 ******************************************************************************/
00320 static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg) {
00321     bool ret = true;
00322 
00323     if (src_cfg == NULL) {
00324         ret = false;
00325     } else {
00326         src_cfg->src_enable                         = true;
00327         src_cfg->use_ch                             = SCUX_USE_CH_2;
00328         src_cfg->word_len                           = SCUX_DATA_LEN_16;
00329         src_cfg->mode_sync                          = true;
00330         src_cfg->input_rate_sync                    = SCUX_SYNC_RATE_48;
00331         src_cfg->input_clk_async                    = SCUX_CLK_USB_X1;
00332         src_cfg->input_div_async                    = INPUT_DIV_INIT_VALUE;
00333         src_cfg->output_rate_sync                   = SCUX_SYNC_RATE_96;
00334         src_cfg->output_clk_async                   = SCUX_CLK_SSIF0_WS;
00335         src_cfg->output_div_async                   = OUTPUT_DIV_INIT_VALUE;
00336         src_cfg->input_ws                           = INPUT_WS_INIT_VALUE;
00337         src_cfg->output_ws                          = OUTPUT_WS_INIT_VALUE;
00338         src_cfg->freq_tioc3a                        = FREQ_TIOC3A_INIT_VALUE;
00339         src_cfg->freq_tioc4a                        = FREQ_TIOC4A_INIT_VALUE;
00340         src_cfg->delay_mode                         = SCUX_DELAY_NORMAL;
00341         src_cfg->wait_sample                        = WAIT_SAMPLE_INIT_VALUE;
00342         src_cfg->min_rate_percentage                = MIN_RATE_PER_INIT_VALUE;
00343         src_cfg->select_in_data_ch[SCUX_AUDIO_CH_0] = SCUX_AUDIO_CH_0;
00344         src_cfg->select_in_data_ch[SCUX_AUDIO_CH_1] = SCUX_AUDIO_CH_1;
00345         src_cfg->select_in_data_ch[SCUX_AUDIO_CH_2] = SCUX_AUDIO_CH_2;
00346         src_cfg->select_in_data_ch[SCUX_AUDIO_CH_3] = SCUX_AUDIO_CH_3;
00347         src_cfg->select_in_data_ch[SCUX_AUDIO_CH_4] = SCUX_AUDIO_CH_4;
00348         src_cfg->select_in_data_ch[SCUX_AUDIO_CH_5] = SCUX_AUDIO_CH_5;
00349         src_cfg->select_in_data_ch[SCUX_AUDIO_CH_6] = SCUX_AUDIO_CH_6;
00350         src_cfg->select_in_data_ch[SCUX_AUDIO_CH_7] = SCUX_AUDIO_CH_7;
00351     }
00352 
00353     return ret;
00354 }