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SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Fri Oct 02 03:03:25 2015 +0000
Revision:
6:aa1fc6a5cc2a
Add SCUX driver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 6:aa1fc6a5cc2a 1 /*******************************************************************************
dkato 6:aa1fc6a5cc2a 2 * DISCLAIMER
dkato 6:aa1fc6a5cc2a 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 6:aa1fc6a5cc2a 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 6:aa1fc6a5cc2a 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 6:aa1fc6a5cc2a 6 * all applicable laws, including copyright laws.
dkato 6:aa1fc6a5cc2a 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 6:aa1fc6a5cc2a 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 6:aa1fc6a5cc2a 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 6:aa1fc6a5cc2a 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 6:aa1fc6a5cc2a 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 6:aa1fc6a5cc2a 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 6:aa1fc6a5cc2a 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 6:aa1fc6a5cc2a 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 6:aa1fc6a5cc2a 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 6:aa1fc6a5cc2a 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 6:aa1fc6a5cc2a 17 * and to discontinue the availability of this software. By using this software,
dkato 6:aa1fc6a5cc2a 18 * you agree to the additional terms and conditions found by accessing the
dkato 6:aa1fc6a5cc2a 19 * following link:
dkato 6:aa1fc6a5cc2a 20 * http://www.renesas.com/disclaimer
dkato 6:aa1fc6a5cc2a 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
dkato 6:aa1fc6a5cc2a 22 *******************************************************************************/
dkato 6:aa1fc6a5cc2a 23
dkato 6:aa1fc6a5cc2a 24 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 25 * @file scux_dev.c
dkato 6:aa1fc6a5cc2a 26 * $Rev: 1674 $
dkato 6:aa1fc6a5cc2a 27 * $Date:: 2015-05-29 16:35:57 +0900#$
dkato 6:aa1fc6a5cc2a 28 * @brief SCUX device control functions
dkato 6:aa1fc6a5cc2a 29 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 30
dkato 6:aa1fc6a5cc2a 31 /*******************************************************************************
dkato 6:aa1fc6a5cc2a 32 Includes <System Includes>, "Project Includes"
dkato 6:aa1fc6a5cc2a 33 *******************************************************************************/
dkato 6:aa1fc6a5cc2a 34
dkato 6:aa1fc6a5cc2a 35 #include "scux.h"
dkato 6:aa1fc6a5cc2a 36
dkato 6:aa1fc6a5cc2a 37 /******************************************************************************
dkato 6:aa1fc6a5cc2a 38 Exported global variables (to be accessed by other files)
dkato 6:aa1fc6a5cc2a 39 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 40
dkato 6:aa1fc6a5cc2a 41 /******************************************************************************
dkato 6:aa1fc6a5cc2a 42 Private global driver management information
dkato 6:aa1fc6a5cc2a 43 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 44
dkato 6:aa1fc6a5cc2a 45 /* SSIF clock mask register table define */
dkato 6:aa1fc6a5cc2a 46 static const uint32_t gb_cpg_scux_ssif_stbcr_bit[SCUX_SSIF_CH_NUM] =
dkato 6:aa1fc6a5cc2a 47 {
dkato 6:aa1fc6a5cc2a 48 CPG_STBCR11_BIT_MSTP115, /* SSIF0 */
dkato 6:aa1fc6a5cc2a 49 CPG_STBCR11_BIT_MSTP114, /* SSIF1 */
dkato 6:aa1fc6a5cc2a 50 CPG_STBCR11_BIT_MSTP113, /* SSIF2 */
dkato 6:aa1fc6a5cc2a 51 CPG_STBCR11_BIT_MSTP112, /* SSIF3 */
dkato 6:aa1fc6a5cc2a 52 CPG_STBCR11_BIT_MSTP111, /* SSIF4 */
dkato 6:aa1fc6a5cc2a 53 CPG_STBCR11_BIT_MSTP110 /* SSIF5 */
dkato 6:aa1fc6a5cc2a 54 };
dkato 6:aa1fc6a5cc2a 55
dkato 6:aa1fc6a5cc2a 56 /* SSIF software reset register table define */
dkato 6:aa1fc6a5cc2a 57 static const uint32_t gb_cpg_scux_ssif_swrst_bit[SCUX_SSIF_CH_NUM] =
dkato 6:aa1fc6a5cc2a 58 {
dkato 6:aa1fc6a5cc2a 59 CPG_SWRSTCR1_BIT_SRST16, /* SSIF0 */
dkato 6:aa1fc6a5cc2a 60 CPG_SWRSTCR1_BIT_SRST15, /* SSIF1 */
dkato 6:aa1fc6a5cc2a 61 CPG_SWRSTCR1_BIT_SRST14, /* SSIF2 */
dkato 6:aa1fc6a5cc2a 62 CPG_SWRSTCR1_BIT_SRST13, /* SSIF3 */
dkato 6:aa1fc6a5cc2a 63 CPG_SWRSTCR1_BIT_SRST12, /* SSIF4 */
dkato 6:aa1fc6a5cc2a 64 CPG_SWRSTCR1_BIT_SRST11 /* SSIF5 */
dkato 6:aa1fc6a5cc2a 65 };
dkato 6:aa1fc6a5cc2a 66
dkato 6:aa1fc6a5cc2a 67 /* SSIF noise cancel register table define */
dkato 6:aa1fc6a5cc2a 68 static const uint32_t gb_cpg_scux_ssif_sncr_bit[SCUX_SSIF_CH_NUM] =
dkato 6:aa1fc6a5cc2a 69 {
dkato 6:aa1fc6a5cc2a 70 SCUX_SSIF_GPIO_SNCR_SHIFT_CH0, /* SSIF0 */
dkato 6:aa1fc6a5cc2a 71 SCUX_SSIF_GPIO_SNCR_SHIFT_CH1, /* SSIF1 */
dkato 6:aa1fc6a5cc2a 72 SCUX_SSIF_GPIO_SNCR_SHIFT_CH2, /* SSIF2 */
dkato 6:aa1fc6a5cc2a 73 SCUX_SSIF_GPIO_SNCR_SHIFT_CH3, /* SSIF3 */
dkato 6:aa1fc6a5cc2a 74 SCUX_SSIF_GPIO_SNCR_SHIFT_CH4, /* SSIF4 */
dkato 6:aa1fc6a5cc2a 75 SCUX_SSIF_GPIO_SNCR_SHIFT_CH5 /* SSIF5 */
dkato 6:aa1fc6a5cc2a 76 };
dkato 6:aa1fc6a5cc2a 77
dkato 6:aa1fc6a5cc2a 78 /* AIOCB information for DMA */
dkato 6:aa1fc6a5cc2a 79 static AIOCB gb_scux_write_dma_aio[SCUX_CH_NUM];
dkato 6:aa1fc6a5cc2a 80 static AIOCB gb_scux_read_dma_aio[SCUX_CH_NUM];
dkato 6:aa1fc6a5cc2a 81
dkato 6:aa1fc6a5cc2a 82 /******************************************************************************
dkato 6:aa1fc6a5cc2a 83 Function prototypes
dkato 6:aa1fc6a5cc2a 84 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 85
dkato 6:aa1fc6a5cc2a 86 static void SCUX_SetupDataPosition(scux_info_ch_t * const p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 87 static void SCUX_SetupSrcClk(scux_info_ch_t * const p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 88 static void SCUX_SetupFifo(scux_info_ch_t * const p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 89 static void SCUX_SetupSrcFunction(scux_info_ch_t * const p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 90 static void SCUX_SetupDvuVolume(scux_info_ch_t * const p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 91 static void SCUX_SetupMix(scux_info_ch_t * const p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 92 static void SCUX_DMA_CopyRxCallBack(union sigval const param);
dkato 6:aa1fc6a5cc2a 93 static void SCUX_DMA_CommonTxNextDummyData(scux_info_ch_t * const p_info_ch);
dkato 6:aa1fc6a5cc2a 94 static void SCUX_DMA_CopyTxEndFlush(scux_info_ch_t * const p_info_ch);
dkato 6:aa1fc6a5cc2a 95 static void SCUX_DMA_CopyTxNextRemainData(scux_info_ch_t * const p_info_ch);
dkato 6:aa1fc6a5cc2a 96 static void SCUX_DMA_CopyTxNextData(scux_info_ch_t * const p_info_ch);
dkato 6:aa1fc6a5cc2a 97 static void SCUX_DMA_CopyTxCallBack(union sigval const param);
dkato 6:aa1fc6a5cc2a 98 static void SCUX_DMA_DirectTxEndFlush(scux_info_ch_t * const p_info_ch);
dkato 6:aa1fc6a5cc2a 99 static void SCUX_DMA_DirectTxNextRemainData(scux_info_ch_t * const p_info_ch);
dkato 6:aa1fc6a5cc2a 100 static void SCUX_DMA_DirectTxNextData(scux_info_ch_t * const p_info_ch);
dkato 6:aa1fc6a5cc2a 101 static void SCUX_DMA_DirectTxCallBack(union sigval const param);
dkato 6:aa1fc6a5cc2a 102
dkato 6:aa1fc6a5cc2a 103 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 104 * Function Name: SCUX_CopyWriteStart
dkato 6:aa1fc6a5cc2a 105 * @brief Start write request (mem->mem).
dkato 6:aa1fc6a5cc2a 106 *
dkato 6:aa1fc6a5cc2a 107 * Description:<br>
dkato 6:aa1fc6a5cc2a 108 *
dkato 6:aa1fc6a5cc2a 109 * @param[in] *p_scux_info_ch:SCUX channel information.
dkato 6:aa1fc6a5cc2a 110 * @param[in] *p_write_aio:Write request information.
dkato 6:aa1fc6a5cc2a 111 * @retval ESUCCESS : Operation successful.
dkato 6:aa1fc6a5cc2a 112 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 113 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 114
dkato 6:aa1fc6a5cc2a 115 int_t SCUX_CopyWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio)
dkato 6:aa1fc6a5cc2a 116 {
dkato 6:aa1fc6a5cc2a 117 int_t retval;
dkato 6:aa1fc6a5cc2a 118 int_t dma_retval;
dkato 6:aa1fc6a5cc2a 119 dma_trans_data_t dma_address_param;
dkato 6:aa1fc6a5cc2a 120 uint32_t dma_src_addr;
dkato 6:aa1fc6a5cc2a 121 int_t ret;
dkato 6:aa1fc6a5cc2a 122
dkato 6:aa1fc6a5cc2a 123 if ((NULL == p_scux_info_ch) || (NULL == p_write_aio))
dkato 6:aa1fc6a5cc2a 124 {
dkato 6:aa1fc6a5cc2a 125 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 126 }
dkato 6:aa1fc6a5cc2a 127 else
dkato 6:aa1fc6a5cc2a 128 {
dkato 6:aa1fc6a5cc2a 129 retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL);
dkato 6:aa1fc6a5cc2a 130
dkato 6:aa1fc6a5cc2a 131 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 132 {
dkato 6:aa1fc6a5cc2a 133 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 134 }
dkato 6:aa1fc6a5cc2a 135 else
dkato 6:aa1fc6a5cc2a 136 {
dkato 6:aa1fc6a5cc2a 137 /* set first trans information */
dkato 6:aa1fc6a5cc2a 138 p_scux_info_ch->p_tx_aio = p_write_aio;
dkato 6:aa1fc6a5cc2a 139 p_scux_info_ch->p_tx_next_aio = NULL;
dkato 6:aa1fc6a5cc2a 140 p_scux_info_ch->first_tx_flag = false;
dkato 6:aa1fc6a5cc2a 141
dkato 6:aa1fc6a5cc2a 142 /* cast uint8_t pointer from void pointer */
dkato 6:aa1fc6a5cc2a 143 dma_src_addr = (uint32_t)p_write_aio->aio_buf;
dkato 6:aa1fc6a5cc2a 144
dkato 6:aa1fc6a5cc2a 145 /* set 1st DMA parameter */
dkato 6:aa1fc6a5cc2a 146 dma_address_param.src_addr = (void *)dma_src_addr;
dkato 6:aa1fc6a5cc2a 147 dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
dkato 6:aa1fc6a5cc2a 148 dma_address_param.count = p_write_aio->aio_nbytes;
dkato 6:aa1fc6a5cc2a 149
dkato 6:aa1fc6a5cc2a 150 dma_retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, &ret);
dkato 6:aa1fc6a5cc2a 151 if (ESUCCESS != dma_retval)
dkato 6:aa1fc6a5cc2a 152 {
dkato 6:aa1fc6a5cc2a 153 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 154 }
dkato 6:aa1fc6a5cc2a 155 else
dkato 6:aa1fc6a5cc2a 156 {
dkato 6:aa1fc6a5cc2a 157 p_scux_info_ch->dma_tx_current_size = dma_address_param.count;
dkato 6:aa1fc6a5cc2a 158 /* enable interrupt */
dkato 6:aa1fc6a5cc2a 159 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET |
dkato 6:aa1fc6a5cc2a 160 DEVMR_FFD0_DEVMOF_SET |
dkato 6:aa1fc6a5cc2a 161 DEVMR_FFD0_DEVMOL_SET |
dkato 6:aa1fc6a5cc2a 162 DEVMR_FFD0_DEVMIUF_SET);
dkato 6:aa1fc6a5cc2a 163 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 164 /* start clock devide on async mode */
dkato 6:aa1fc6a5cc2a 165 if (false == p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 166 {
dkato 6:aa1fc6a5cc2a 167 if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 168 (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 169 (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 170 (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 171 (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 172 (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
dkato 6:aa1fc6a5cc2a 173 {
dkato 6:aa1fc6a5cc2a 174 *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET;
dkato 6:aa1fc6a5cc2a 175 }
dkato 6:aa1fc6a5cc2a 176 }
dkato 6:aa1fc6a5cc2a 177 /* update channel status */
dkato 6:aa1fc6a5cc2a 178 switch (p_scux_info_ch->ch_stat)
dkato 6:aa1fc6a5cc2a 179 {
dkato 6:aa1fc6a5cc2a 180 case SCUX_CH_UNINIT :
dkato 6:aa1fc6a5cc2a 181 /* fall through */
dkato 6:aa1fc6a5cc2a 182 case SCUX_CH_INIT :
dkato 6:aa1fc6a5cc2a 183 /* fall through */
dkato 6:aa1fc6a5cc2a 184 case SCUX_CH_STOP :
dkato 6:aa1fc6a5cc2a 185 retval = EBADF;
dkato 6:aa1fc6a5cc2a 186 break;
dkato 6:aa1fc6a5cc2a 187
dkato 6:aa1fc6a5cc2a 188 case SCUX_CH_TRANS_IDLE :
dkato 6:aa1fc6a5cc2a 189 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_WR;
dkato 6:aa1fc6a5cc2a 190 break;
dkato 6:aa1fc6a5cc2a 191
dkato 6:aa1fc6a5cc2a 192 case SCUX_CH_TRANS_RD :
dkato 6:aa1fc6a5cc2a 193 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RDWR;
dkato 6:aa1fc6a5cc2a 194 break;
dkato 6:aa1fc6a5cc2a 195
dkato 6:aa1fc6a5cc2a 196 case SCUX_CH_TRANS_WR :
dkato 6:aa1fc6a5cc2a 197 /* fall through */
dkato 6:aa1fc6a5cc2a 198 case SCUX_CH_TRANS_RDWR :
dkato 6:aa1fc6a5cc2a 199 /* fall through */
dkato 6:aa1fc6a5cc2a 200 case SCUX_CH_STOP_WAIT :
dkato 6:aa1fc6a5cc2a 201 /* fall through */
dkato 6:aa1fc6a5cc2a 202 case SCUX_CH_STOP_WAIT_IDLE :
dkato 6:aa1fc6a5cc2a 203 /* do nothing, stats isn't updated */
dkato 6:aa1fc6a5cc2a 204 break;
dkato 6:aa1fc6a5cc2a 205
dkato 6:aa1fc6a5cc2a 206 default :
dkato 6:aa1fc6a5cc2a 207 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 208 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 209 break;
dkato 6:aa1fc6a5cc2a 210 }
dkato 6:aa1fc6a5cc2a 211 }
dkato 6:aa1fc6a5cc2a 212 }
dkato 6:aa1fc6a5cc2a 213 }
dkato 6:aa1fc6a5cc2a 214
dkato 6:aa1fc6a5cc2a 215 return retval;
dkato 6:aa1fc6a5cc2a 216 }
dkato 6:aa1fc6a5cc2a 217
dkato 6:aa1fc6a5cc2a 218 /******************************************************************************
dkato 6:aa1fc6a5cc2a 219 End of function SCUX_CopyWriteStart
dkato 6:aa1fc6a5cc2a 220 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 221
dkato 6:aa1fc6a5cc2a 222 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 223 * Function Name: SCUX_DirectWriteStart
dkato 6:aa1fc6a5cc2a 224 * @brief Start write request(SSIF direct route).
dkato 6:aa1fc6a5cc2a 225 *
dkato 6:aa1fc6a5cc2a 226 * Description:<br>
dkato 6:aa1fc6a5cc2a 227 *
dkato 6:aa1fc6a5cc2a 228 * @param[in] *p_scux_info_ch:SCUX channel information.
dkato 6:aa1fc6a5cc2a 229 * @param[in] *p_write_aio:Write request information.
dkato 6:aa1fc6a5cc2a 230 * @retval ESUCCESS : Operation successful.
dkato 6:aa1fc6a5cc2a 231 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 232 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 233
dkato 6:aa1fc6a5cc2a 234 int_t SCUX_DirectWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio)
dkato 6:aa1fc6a5cc2a 235 {
dkato 6:aa1fc6a5cc2a 236 int_t retval;
dkato 6:aa1fc6a5cc2a 237 int_t dma_retval;
dkato 6:aa1fc6a5cc2a 238 dma_trans_data_t dma_address_param;
dkato 6:aa1fc6a5cc2a 239 dma_trans_data_t next_dma_address_param;
dkato 6:aa1fc6a5cc2a 240 uint32_t dma_src_addr;
dkato 6:aa1fc6a5cc2a 241 int_t ret;
dkato 6:aa1fc6a5cc2a 242 uint32_t ramp_wait_cnt = 0;
dkato 6:aa1fc6a5cc2a 243
dkato 6:aa1fc6a5cc2a 244 if ((NULL == p_scux_info_ch) || (NULL == p_write_aio))
dkato 6:aa1fc6a5cc2a 245 {
dkato 6:aa1fc6a5cc2a 246 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 247 }
dkato 6:aa1fc6a5cc2a 248 else
dkato 6:aa1fc6a5cc2a 249 {
dkato 6:aa1fc6a5cc2a 250 retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL);
dkato 6:aa1fc6a5cc2a 251
dkato 6:aa1fc6a5cc2a 252 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 253 {
dkato 6:aa1fc6a5cc2a 254 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 255 }
dkato 6:aa1fc6a5cc2a 256 else
dkato 6:aa1fc6a5cc2a 257 {
dkato 6:aa1fc6a5cc2a 258 /* set first trans information */
dkato 6:aa1fc6a5cc2a 259 p_scux_info_ch->p_tx_aio = NULL;
dkato 6:aa1fc6a5cc2a 260 p_scux_info_ch->p_tx_next_aio = p_write_aio;
dkato 6:aa1fc6a5cc2a 261 p_scux_info_ch->first_tx_flag = true;
dkato 6:aa1fc6a5cc2a 262
dkato 6:aa1fc6a5cc2a 263 /* cast uint8_t pointer from void pointer */
dkato 6:aa1fc6a5cc2a 264 dma_src_addr = (uint32_t)p_write_aio->aio_buf;
dkato 6:aa1fc6a5cc2a 265
dkato 6:aa1fc6a5cc2a 266 /* set 2nd DMA parameter */
dkato 6:aa1fc6a5cc2a 267 next_dma_address_param.src_addr = (void *)(dma_src_addr + (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE));
dkato 6:aa1fc6a5cc2a 268 next_dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
dkato 6:aa1fc6a5cc2a 269 next_dma_address_param.count = (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE);
dkato 6:aa1fc6a5cc2a 270 if (0U != (p_write_aio->aio_nbytes % SCUX_HALF_SIZE_VALUE))
dkato 6:aa1fc6a5cc2a 271 {
dkato 6:aa1fc6a5cc2a 272 /* last data ,when even value size */
dkato 6:aa1fc6a5cc2a 273 next_dma_address_param.count++;
dkato 6:aa1fc6a5cc2a 274 }
dkato 6:aa1fc6a5cc2a 275 dma_retval = R_DMA_NextData(p_scux_info_ch->dma_tx_ch, &next_dma_address_param, &ret);
dkato 6:aa1fc6a5cc2a 276
dkato 6:aa1fc6a5cc2a 277 if (ESUCCESS != dma_retval)
dkato 6:aa1fc6a5cc2a 278 {
dkato 6:aa1fc6a5cc2a 279 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 280 }
dkato 6:aa1fc6a5cc2a 281 else
dkato 6:aa1fc6a5cc2a 282 {
dkato 6:aa1fc6a5cc2a 283 p_scux_info_ch->dma_tx_next_size = next_dma_address_param.count;
dkato 6:aa1fc6a5cc2a 284 /* set 1st DMA parameter */
dkato 6:aa1fc6a5cc2a 285 dma_address_param.src_addr = (void *)dma_src_addr;
dkato 6:aa1fc6a5cc2a 286 dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
dkato 6:aa1fc6a5cc2a 287 dma_address_param.count = (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE);
dkato 6:aa1fc6a5cc2a 288
dkato 6:aa1fc6a5cc2a 289 dma_retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, &ret);
dkato 6:aa1fc6a5cc2a 290 if (ESUCCESS != dma_retval)
dkato 6:aa1fc6a5cc2a 291 {
dkato 6:aa1fc6a5cc2a 292 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 293 }
dkato 6:aa1fc6a5cc2a 294 else
dkato 6:aa1fc6a5cc2a 295 {
dkato 6:aa1fc6a5cc2a 296 p_scux_info_ch->dma_tx_current_size = dma_address_param.count;
dkato 6:aa1fc6a5cc2a 297 /* enable interrupt */
dkato 6:aa1fc6a5cc2a 298 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET |
dkato 6:aa1fc6a5cc2a 299 DEVMR_FFD0_DEVMOF_SET |
dkato 6:aa1fc6a5cc2a 300 DEVMR_FFD0_DEVMOL_SET |
dkato 6:aa1fc6a5cc2a 301 DEVMR_FFD0_DEVMIUF_SET);
dkato 6:aa1fc6a5cc2a 302 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 303 *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET;
dkato 6:aa1fc6a5cc2a 304
dkato 6:aa1fc6a5cc2a 305 switch (p_scux_info_ch->ch_stat)
dkato 6:aa1fc6a5cc2a 306 {
dkato 6:aa1fc6a5cc2a 307 case SCUX_CH_UNINIT :
dkato 6:aa1fc6a5cc2a 308 /* fall through */
dkato 6:aa1fc6a5cc2a 309 case SCUX_CH_INIT :
dkato 6:aa1fc6a5cc2a 310 /* fall through */
dkato 6:aa1fc6a5cc2a 311 case SCUX_CH_STOP :
dkato 6:aa1fc6a5cc2a 312 /* fall through */
dkato 6:aa1fc6a5cc2a 313 retval = EBADF;
dkato 6:aa1fc6a5cc2a 314 break;
dkato 6:aa1fc6a5cc2a 315
dkato 6:aa1fc6a5cc2a 316 case SCUX_CH_TRANS_IDLE :
dkato 6:aa1fc6a5cc2a 317 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_WR;
dkato 6:aa1fc6a5cc2a 318 break;
dkato 6:aa1fc6a5cc2a 319
dkato 6:aa1fc6a5cc2a 320 case SCUX_CH_TRANS_RD :
dkato 6:aa1fc6a5cc2a 321 /* read function disabled */
dkato 6:aa1fc6a5cc2a 322 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 323 break;
dkato 6:aa1fc6a5cc2a 324
dkato 6:aa1fc6a5cc2a 325 case SCUX_CH_TRANS_WR :
dkato 6:aa1fc6a5cc2a 326 /* do nothing, stats isn't updated */
dkato 6:aa1fc6a5cc2a 327 break;
dkato 6:aa1fc6a5cc2a 328
dkato 6:aa1fc6a5cc2a 329 case SCUX_CH_TRANS_RDWR :
dkato 6:aa1fc6a5cc2a 330 /* read function disabled */
dkato 6:aa1fc6a5cc2a 331 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 332 break;
dkato 6:aa1fc6a5cc2a 333
dkato 6:aa1fc6a5cc2a 334 case SCUX_CH_STOP_WAIT :
dkato 6:aa1fc6a5cc2a 335 /* do nothing, stats isn't updated */
dkato 6:aa1fc6a5cc2a 336 break;
dkato 6:aa1fc6a5cc2a 337
dkato 6:aa1fc6a5cc2a 338 case SCUX_CH_STOP_WAIT_IDLE :
dkato 6:aa1fc6a5cc2a 339 /* read function disabled */
dkato 6:aa1fc6a5cc2a 340 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 341 break;
dkato 6:aa1fc6a5cc2a 342
dkato 6:aa1fc6a5cc2a 343 default :
dkato 6:aa1fc6a5cc2a 344 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 345 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 346 break;
dkato 6:aa1fc6a5cc2a 347 }
dkato 6:aa1fc6a5cc2a 348
dkato 6:aa1fc6a5cc2a 349 /* set ramp setting */
dkato 6:aa1fc6a5cc2a 350 if (false == p_scux_info_ch->first_ramp_flag)
dkato 6:aa1fc6a5cc2a 351 {
dkato 6:aa1fc6a5cc2a 352 while((DVUSR_DVU0_VRSTS_VOL_FIX != (p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUSR_DVU0_0 & DVUSR_DVU0_VRSTS_MASK)) &&
dkato 6:aa1fc6a5cc2a 353 (SCUX_RAMP_WAIT_MAX > ramp_wait_cnt))
dkato 6:aa1fc6a5cc2a 354 {
dkato 6:aa1fc6a5cc2a 355 ramp_wait_cnt++;
dkato 6:aa1fc6a5cc2a 356 }
dkato 6:aa1fc6a5cc2a 357 if (SCUX_RAMP_WAIT_MAX <= ramp_wait_cnt)
dkato 6:aa1fc6a5cc2a 358 {
dkato 6:aa1fc6a5cc2a 359 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 360 }
dkato 6:aa1fc6a5cc2a 361 else
dkato 6:aa1fc6a5cc2a 362 {
dkato 6:aa1fc6a5cc2a 363 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
dkato 6:aa1fc6a5cc2a 364 SCUX_SetRampVolRegister(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 365 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
dkato 6:aa1fc6a5cc2a 366 p_scux_info_ch->first_ramp_flag = true;
dkato 6:aa1fc6a5cc2a 367 }
dkato 6:aa1fc6a5cc2a 368 }
dkato 6:aa1fc6a5cc2a 369 }
dkato 6:aa1fc6a5cc2a 370 }
dkato 6:aa1fc6a5cc2a 371 }
dkato 6:aa1fc6a5cc2a 372 }
dkato 6:aa1fc6a5cc2a 373
dkato 6:aa1fc6a5cc2a 374 return retval;
dkato 6:aa1fc6a5cc2a 375 }
dkato 6:aa1fc6a5cc2a 376
dkato 6:aa1fc6a5cc2a 377 /******************************************************************************
dkato 6:aa1fc6a5cc2a 378 End of function SCUX_DirectWriteStart
dkato 6:aa1fc6a5cc2a 379 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 380
dkato 6:aa1fc6a5cc2a 381 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 382 * Function Name: SCUX_CopyReadStart
dkato 6:aa1fc6a5cc2a 383 * @brief Start read request(mem -> mem).
dkato 6:aa1fc6a5cc2a 384 *
dkato 6:aa1fc6a5cc2a 385 * Description:<br>
dkato 6:aa1fc6a5cc2a 386 *
dkato 6:aa1fc6a5cc2a 387 * @param[in] *p_scux_info_ch:SCUX channel information.
dkato 6:aa1fc6a5cc2a 388 * @param[in] *p_read_aio:Read request information.
dkato 6:aa1fc6a5cc2a 389 * @retval ESUCCESS : Operation successful.
dkato 6:aa1fc6a5cc2a 390 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 391 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 392
dkato 6:aa1fc6a5cc2a 393 int_t SCUX_CopyReadStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_read_aio)
dkato 6:aa1fc6a5cc2a 394 {
dkato 6:aa1fc6a5cc2a 395 int_t retval;
dkato 6:aa1fc6a5cc2a 396 int_t dma_retval;
dkato 6:aa1fc6a5cc2a 397 dma_trans_data_t dma_address_param;
dkato 6:aa1fc6a5cc2a 398 uint32_t dma_dst_addr;
dkato 6:aa1fc6a5cc2a 399
dkato 6:aa1fc6a5cc2a 400 if ((NULL == p_scux_info_ch) || (NULL == p_read_aio))
dkato 6:aa1fc6a5cc2a 401 {
dkato 6:aa1fc6a5cc2a 402 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 403 }
dkato 6:aa1fc6a5cc2a 404 else
dkato 6:aa1fc6a5cc2a 405 {
dkato 6:aa1fc6a5cc2a 406 retval = R_DMA_Setup(p_scux_info_ch->dma_rx_ch, &p_scux_info_ch->dma_rx_setup, NULL);
dkato 6:aa1fc6a5cc2a 407
dkato 6:aa1fc6a5cc2a 408 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 409 {
dkato 6:aa1fc6a5cc2a 410 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 411 }
dkato 6:aa1fc6a5cc2a 412 else
dkato 6:aa1fc6a5cc2a 413 {
dkato 6:aa1fc6a5cc2a 414 /* set first trans information */
dkato 6:aa1fc6a5cc2a 415 p_scux_info_ch->p_rx_aio = p_read_aio;
dkato 6:aa1fc6a5cc2a 416 p_scux_info_ch->p_rx_next_aio = NULL;
dkato 6:aa1fc6a5cc2a 417 p_scux_info_ch->first_rx_flag = false;
dkato 6:aa1fc6a5cc2a 418
dkato 6:aa1fc6a5cc2a 419 /* cast uint8_t pointer from void pointer */
dkato 6:aa1fc6a5cc2a 420 dma_dst_addr = (uint32_t)p_read_aio->aio_buf;
dkato 6:aa1fc6a5cc2a 421
dkato 6:aa1fc6a5cc2a 422 /* set 1st DMA parameter */
dkato 6:aa1fc6a5cc2a 423 dma_address_param.src_addr = (void *)p_scux_info_ch->p_scux_reg->dmatu_n_cim;
dkato 6:aa1fc6a5cc2a 424 dma_address_param.dst_addr = (void *)dma_dst_addr;
dkato 6:aa1fc6a5cc2a 425 dma_address_param.count = p_read_aio->aio_nbytes;
dkato 6:aa1fc6a5cc2a 426
dkato 6:aa1fc6a5cc2a 427 dma_retval = R_DMA_Start(p_scux_info_ch->dma_rx_ch, &dma_address_param, NULL);
dkato 6:aa1fc6a5cc2a 428
dkato 6:aa1fc6a5cc2a 429 if (ESUCCESS != dma_retval)
dkato 6:aa1fc6a5cc2a 430 {
dkato 6:aa1fc6a5cc2a 431 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 432 }
dkato 6:aa1fc6a5cc2a 433 else
dkato 6:aa1fc6a5cc2a 434 {
dkato 6:aa1fc6a5cc2a 435 /* enable interrupt */
dkato 6:aa1fc6a5cc2a 436 p_scux_info_ch->dma_rx_current_size = dma_address_param.count;
dkato 6:aa1fc6a5cc2a 437 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = (UEVMR_FFU0_UEVMUF_SET |
dkato 6:aa1fc6a5cc2a 438 UEVMR_FFU0_UEVMOF_SET |
dkato 6:aa1fc6a5cc2a 439 UEVMR_FFU0_UEVMOL_SET);
dkato 6:aa1fc6a5cc2a 440 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = DEVCR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 441 /* start clock devide on async mode */
dkato 6:aa1fc6a5cc2a 442 if (false == p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 443 {
dkato 6:aa1fc6a5cc2a 444 if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 445 (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 446 (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 447 (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 448 (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 449 (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
dkato 6:aa1fc6a5cc2a 450 {
dkato 6:aa1fc6a5cc2a 451 p_scux_info_ch->futsel_cim_value |= FUTSEL_CIM_DIVEN_SET;
dkato 6:aa1fc6a5cc2a 452 *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
dkato 6:aa1fc6a5cc2a 453 }
dkato 6:aa1fc6a5cc2a 454 }
dkato 6:aa1fc6a5cc2a 455 /* update channel status */
dkato 6:aa1fc6a5cc2a 456
dkato 6:aa1fc6a5cc2a 457 switch (p_scux_info_ch->ch_stat)
dkato 6:aa1fc6a5cc2a 458 {
dkato 6:aa1fc6a5cc2a 459 case SCUX_CH_UNINIT :
dkato 6:aa1fc6a5cc2a 460 /* fall through */
dkato 6:aa1fc6a5cc2a 461 case SCUX_CH_INIT :
dkato 6:aa1fc6a5cc2a 462 /* fall through */
dkato 6:aa1fc6a5cc2a 463 case SCUX_CH_STOP :
dkato 6:aa1fc6a5cc2a 464 /* fall through */
dkato 6:aa1fc6a5cc2a 465 retval = EBADF;
dkato 6:aa1fc6a5cc2a 466 break;
dkato 6:aa1fc6a5cc2a 467
dkato 6:aa1fc6a5cc2a 468 case SCUX_CH_TRANS_IDLE :
dkato 6:aa1fc6a5cc2a 469 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RD;
dkato 6:aa1fc6a5cc2a 470 break;
dkato 6:aa1fc6a5cc2a 471
dkato 6:aa1fc6a5cc2a 472 case SCUX_CH_TRANS_RD :
dkato 6:aa1fc6a5cc2a 473 /* do nothing, stats isn't updated */
dkato 6:aa1fc6a5cc2a 474 break;
dkato 6:aa1fc6a5cc2a 475
dkato 6:aa1fc6a5cc2a 476 case SCUX_CH_TRANS_WR :
dkato 6:aa1fc6a5cc2a 477 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RDWR;
dkato 6:aa1fc6a5cc2a 478 break;
dkato 6:aa1fc6a5cc2a 479
dkato 6:aa1fc6a5cc2a 480 case SCUX_CH_TRANS_RDWR :
dkato 6:aa1fc6a5cc2a 481 /* fall through */
dkato 6:aa1fc6a5cc2a 482 case SCUX_CH_STOP_WAIT :
dkato 6:aa1fc6a5cc2a 483 /* do nothing, stats isn't updated */
dkato 6:aa1fc6a5cc2a 484 break;
dkato 6:aa1fc6a5cc2a 485
dkato 6:aa1fc6a5cc2a 486 case SCUX_CH_STOP_WAIT_IDLE :
dkato 6:aa1fc6a5cc2a 487 p_scux_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
dkato 6:aa1fc6a5cc2a 488 break;
dkato 6:aa1fc6a5cc2a 489
dkato 6:aa1fc6a5cc2a 490 default :
dkato 6:aa1fc6a5cc2a 491 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 492 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 493 break;
dkato 6:aa1fc6a5cc2a 494 }
dkato 6:aa1fc6a5cc2a 495 }
dkato 6:aa1fc6a5cc2a 496 }
dkato 6:aa1fc6a5cc2a 497 }
dkato 6:aa1fc6a5cc2a 498
dkato 6:aa1fc6a5cc2a 499 return retval;
dkato 6:aa1fc6a5cc2a 500 }
dkato 6:aa1fc6a5cc2a 501
dkato 6:aa1fc6a5cc2a 502 /******************************************************************************
dkato 6:aa1fc6a5cc2a 503 End of function SCUX_CopyReadStart
dkato 6:aa1fc6a5cc2a 504 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 505
dkato 6:aa1fc6a5cc2a 506 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 507 * Function Name: SCUX_FlushWriteStart
dkato 6:aa1fc6a5cc2a 508 * @brief Start dummy write for FIFO flush.
dkato 6:aa1fc6a5cc2a 509 *
dkato 6:aa1fc6a5cc2a 510 * Description:<br>
dkato 6:aa1fc6a5cc2a 511 *
dkato 6:aa1fc6a5cc2a 512 * @param[in] *p_scux_info_ch:SCUX channel information.
dkato 6:aa1fc6a5cc2a 513 * @param[in] *p_write_aio:Write request information.
dkato 6:aa1fc6a5cc2a 514 * @retval ESUCCESS : Operation successful.
dkato 6:aa1fc6a5cc2a 515 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 516 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 517
dkato 6:aa1fc6a5cc2a 518 int_t SCUX_FlushWriteStart(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 519 {
dkato 6:aa1fc6a5cc2a 520 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 521 dma_trans_data_t dma_address_param;
dkato 6:aa1fc6a5cc2a 522
dkato 6:aa1fc6a5cc2a 523 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 524 {
dkato 6:aa1fc6a5cc2a 525 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 526 }
dkato 6:aa1fc6a5cc2a 527 else
dkato 6:aa1fc6a5cc2a 528 {
dkato 6:aa1fc6a5cc2a 529 if (0U != p_scux_info_ch->flush_stop_size)
dkato 6:aa1fc6a5cc2a 530 {
dkato 6:aa1fc6a5cc2a 531 retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL);
dkato 6:aa1fc6a5cc2a 532
dkato 6:aa1fc6a5cc2a 533 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 534 {
dkato 6:aa1fc6a5cc2a 535 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 536 }
dkato 6:aa1fc6a5cc2a 537 else
dkato 6:aa1fc6a5cc2a 538 {
dkato 6:aa1fc6a5cc2a 539 /* trans dummy data size is FIFO size unit */
dkato 6:aa1fc6a5cc2a 540 if (p_scux_info_ch->flush_stop_size >= p_scux_info_ch->fifo_size)
dkato 6:aa1fc6a5cc2a 541 {
dkato 6:aa1fc6a5cc2a 542 dma_address_param.count = p_scux_info_ch->fifo_size;
dkato 6:aa1fc6a5cc2a 543 p_scux_info_ch->flush_stop_size -= p_scux_info_ch->fifo_size;
dkato 6:aa1fc6a5cc2a 544 }
dkato 6:aa1fc6a5cc2a 545 else
dkato 6:aa1fc6a5cc2a 546 {
dkato 6:aa1fc6a5cc2a 547 /* last data is fraction of FIFO size */
dkato 6:aa1fc6a5cc2a 548 dma_address_param.count = p_scux_info_ch->flush_stop_size;
dkato 6:aa1fc6a5cc2a 549 p_scux_info_ch->flush_stop_size = 0;
dkato 6:aa1fc6a5cc2a 550 }
dkato 6:aa1fc6a5cc2a 551
dkato 6:aa1fc6a5cc2a 552 dma_address_param.src_addr = (void *)(p_scux_info_ch->p_tx_dummy_data);
dkato 6:aa1fc6a5cc2a 553 dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
dkato 6:aa1fc6a5cc2a 554
dkato 6:aa1fc6a5cc2a 555 retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, NULL);
dkato 6:aa1fc6a5cc2a 556 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 557 {
dkato 6:aa1fc6a5cc2a 558 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 559 }
dkato 6:aa1fc6a5cc2a 560 else
dkato 6:aa1fc6a5cc2a 561 {
dkato 6:aa1fc6a5cc2a 562 p_scux_info_ch->dma_tx_current_size = dma_address_param.count;
dkato 6:aa1fc6a5cc2a 563
dkato 6:aa1fc6a5cc2a 564 p_scux_info_ch->tx_dummy_run_flag = true;
dkato 6:aa1fc6a5cc2a 565
dkato 6:aa1fc6a5cc2a 566 if ((SCUX_CH_TRANS_RD == p_scux_info_ch->ch_stat) || (SCUX_CH_TRANS_IDLE == p_scux_info_ch->ch_stat))
dkato 6:aa1fc6a5cc2a 567 {
dkato 6:aa1fc6a5cc2a 568 /* restart write operation when write is stopped */
dkato 6:aa1fc6a5cc2a 569 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET |
dkato 6:aa1fc6a5cc2a 570 DEVMR_FFD0_DEVMOF_SET |
dkato 6:aa1fc6a5cc2a 571 DEVMR_FFD0_DEVMOL_SET |
dkato 6:aa1fc6a5cc2a 572 DEVMR_FFD0_DEVMIUF_SET);
dkato 6:aa1fc6a5cc2a 573 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0
dkato 6:aa1fc6a5cc2a 574 = DEVCR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 575 /* start clock devide on async mode or SSIF direct route setting */
dkato 6:aa1fc6a5cc2a 576 if (false == p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 577 {
dkato 6:aa1fc6a5cc2a 578 if((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 579 (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 580 (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 581 (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 582 (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
dkato 6:aa1fc6a5cc2a 583 (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
dkato 6:aa1fc6a5cc2a 584 {
dkato 6:aa1fc6a5cc2a 585 *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET;
dkato 6:aa1fc6a5cc2a 586 }
dkato 6:aa1fc6a5cc2a 587 }
dkato 6:aa1fc6a5cc2a 588 }
dkato 6:aa1fc6a5cc2a 589 }
dkato 6:aa1fc6a5cc2a 590 }
dkato 6:aa1fc6a5cc2a 591 }
dkato 6:aa1fc6a5cc2a 592 }
dkato 6:aa1fc6a5cc2a 593
dkato 6:aa1fc6a5cc2a 594 return retval;
dkato 6:aa1fc6a5cc2a 595 }
dkato 6:aa1fc6a5cc2a 596
dkato 6:aa1fc6a5cc2a 597 /******************************************************************************
dkato 6:aa1fc6a5cc2a 598 End of function SCUX_FlushWriteStart
dkato 6:aa1fc6a5cc2a 599 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 600
dkato 6:aa1fc6a5cc2a 601 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 602 * Function Name: SCUX_CopyCancelSpecific
dkato 6:aa1fc6a5cc2a 603 * @brief Cancel specific request(mem->mem).
dkato 6:aa1fc6a5cc2a 604 *
dkato 6:aa1fc6a5cc2a 605 * Description:<br>
dkato 6:aa1fc6a5cc2a 606 *
dkato 6:aa1fc6a5cc2a 607 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 608 * @param[in] *p_cancel_aio : Cancel request information.
dkato 6:aa1fc6a5cc2a 609 * @retval ESUCCESS : Operation successful.
dkato 6:aa1fc6a5cc2a 610 * EBUSY : Cancel requst is on going.
dkato 6:aa1fc6a5cc2a 611 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 612 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 613
dkato 6:aa1fc6a5cc2a 614 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 615 #if defined (__CC_ARM)
dkato 6:aa1fc6a5cc2a 616 #pragma O0
dkato 6:aa1fc6a5cc2a 617 #endif
dkato 6:aa1fc6a5cc2a 618 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 619 int_t SCUX_CopyCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio)
dkato 6:aa1fc6a5cc2a 620 {
dkato 6:aa1fc6a5cc2a 621 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 622 int_t dummy_retval;
dkato 6:aa1fc6a5cc2a 623 int_t was_masked;
dkato 6:aa1fc6a5cc2a 624
dkato 6:aa1fc6a5cc2a 625 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 626 {
dkato 6:aa1fc6a5cc2a 627 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 628 }
dkato 6:aa1fc6a5cc2a 629 else
dkato 6:aa1fc6a5cc2a 630 {
dkato 6:aa1fc6a5cc2a 631 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 632 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 633 #else
dkato 6:aa1fc6a5cc2a 634 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 635 #endif
dkato 6:aa1fc6a5cc2a 636
dkato 6:aa1fc6a5cc2a 637 /* check cancel request */
dkato 6:aa1fc6a5cc2a 638 if ((p_scux_info_ch->p_tx_aio == p_cancel_aio) || (p_scux_info_ch->p_rx_aio == p_cancel_aio))
dkato 6:aa1fc6a5cc2a 639 {
dkato 6:aa1fc6a5cc2a 640 retval = EBUSY;
dkato 6:aa1fc6a5cc2a 641 }
dkato 6:aa1fc6a5cc2a 642 else
dkato 6:aa1fc6a5cc2a 643 {
dkato 6:aa1fc6a5cc2a 644 /* request don't going */
dkato 6:aa1fc6a5cc2a 645 dummy_retval = ahf_cancel(&p_scux_info_ch->tx_que, p_cancel_aio);
dkato 6:aa1fc6a5cc2a 646 if (ESUCCESS != dummy_retval)
dkato 6:aa1fc6a5cc2a 647 {
dkato 6:aa1fc6a5cc2a 648 /* NON_NOTICE_ASSERT: queue cancel error */
dkato 6:aa1fc6a5cc2a 649 }
dkato 6:aa1fc6a5cc2a 650 dummy_retval = ahf_cancel(&p_scux_info_ch->rx_que, p_cancel_aio);
dkato 6:aa1fc6a5cc2a 651 if (ESUCCESS != dummy_retval)
dkato 6:aa1fc6a5cc2a 652 {
dkato 6:aa1fc6a5cc2a 653 /* NON_NOTICE_ASSERT: queue cancel error */
dkato 6:aa1fc6a5cc2a 654 }
dkato 6:aa1fc6a5cc2a 655 }
dkato 6:aa1fc6a5cc2a 656
dkato 6:aa1fc6a5cc2a 657 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 658 {
dkato 6:aa1fc6a5cc2a 659 __enable_irq();
dkato 6:aa1fc6a5cc2a 660 }
dkato 6:aa1fc6a5cc2a 661 }
dkato 6:aa1fc6a5cc2a 662
dkato 6:aa1fc6a5cc2a 663 return retval;
dkato 6:aa1fc6a5cc2a 664 }
dkato 6:aa1fc6a5cc2a 665 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 666 #if defined (__CC_ARM)
dkato 6:aa1fc6a5cc2a 667 #pragma O3
dkato 6:aa1fc6a5cc2a 668 #endif
dkato 6:aa1fc6a5cc2a 669 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 670
dkato 6:aa1fc6a5cc2a 671 /******************************************************************************
dkato 6:aa1fc6a5cc2a 672 End of function SCUX_CopyCancelSpecific
dkato 6:aa1fc6a5cc2a 673 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 674
dkato 6:aa1fc6a5cc2a 675 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 676 * Function Name: SCUX_DirectCancelSpecific
dkato 6:aa1fc6a5cc2a 677 * @brief Cancel specific request(SSIF direct route).
dkato 6:aa1fc6a5cc2a 678 *
dkato 6:aa1fc6a5cc2a 679 * Description:<br>
dkato 6:aa1fc6a5cc2a 680 *
dkato 6:aa1fc6a5cc2a 681 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 682 * @param[in] *p_cancel_aio : Cancel request information.
dkato 6:aa1fc6a5cc2a 683 * @retval ESUCCESS : Operation successful.
dkato 6:aa1fc6a5cc2a 684 * EBUSY : Cancel requst is on going.
dkato 6:aa1fc6a5cc2a 685 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 686 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 687
dkato 6:aa1fc6a5cc2a 688 int_t SCUX_DirectCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio)
dkato 6:aa1fc6a5cc2a 689 {
dkato 6:aa1fc6a5cc2a 690 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 691 int_t dummy_retval;
dkato 6:aa1fc6a5cc2a 692 int_t was_masked;
dkato 6:aa1fc6a5cc2a 693
dkato 6:aa1fc6a5cc2a 694 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 695 {
dkato 6:aa1fc6a5cc2a 696 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 697 }
dkato 6:aa1fc6a5cc2a 698 else
dkato 6:aa1fc6a5cc2a 699 {
dkato 6:aa1fc6a5cc2a 700 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 701 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 702 #else
dkato 6:aa1fc6a5cc2a 703 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 704 #endif
dkato 6:aa1fc6a5cc2a 705
dkato 6:aa1fc6a5cc2a 706 /* check cancel request */
dkato 6:aa1fc6a5cc2a 707 if ((p_scux_info_ch->p_tx_aio == p_cancel_aio) || (p_scux_info_ch->p_tx_next_aio == p_cancel_aio))
dkato 6:aa1fc6a5cc2a 708 {
dkato 6:aa1fc6a5cc2a 709 retval = EBUSY;
dkato 6:aa1fc6a5cc2a 710 }
dkato 6:aa1fc6a5cc2a 711 else
dkato 6:aa1fc6a5cc2a 712 {
dkato 6:aa1fc6a5cc2a 713 /* request don't going */
dkato 6:aa1fc6a5cc2a 714 dummy_retval = ahf_cancel(&p_scux_info_ch->tx_que, p_cancel_aio);
dkato 6:aa1fc6a5cc2a 715 if (ESUCCESS != dummy_retval)
dkato 6:aa1fc6a5cc2a 716 {
dkato 6:aa1fc6a5cc2a 717 /* NON_NOTICE_ASSERT: queue cancel error */
dkato 6:aa1fc6a5cc2a 718 }
dkato 6:aa1fc6a5cc2a 719 }
dkato 6:aa1fc6a5cc2a 720
dkato 6:aa1fc6a5cc2a 721 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 722 {
dkato 6:aa1fc6a5cc2a 723 __enable_irq();
dkato 6:aa1fc6a5cc2a 724 }
dkato 6:aa1fc6a5cc2a 725 }
dkato 6:aa1fc6a5cc2a 726
dkato 6:aa1fc6a5cc2a 727 return retval;
dkato 6:aa1fc6a5cc2a 728 }
dkato 6:aa1fc6a5cc2a 729
dkato 6:aa1fc6a5cc2a 730 /******************************************************************************
dkato 6:aa1fc6a5cc2a 731 End of function SCUX_DirectCancelSpecific
dkato 6:aa1fc6a5cc2a 732 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 733
dkato 6:aa1fc6a5cc2a 734 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 735 * Function Name: SCUX_CopyCancelAll
dkato 6:aa1fc6a5cc2a 736 * @brief Cancel all request(mem->mem).
dkato 6:aa1fc6a5cc2a 737 *
dkato 6:aa1fc6a5cc2a 738 * Description:<br>
dkato 6:aa1fc6a5cc2a 739 *
dkato 6:aa1fc6a5cc2a 740 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 741 * @retval ESUCCESS : Operation successful.
dkato 6:aa1fc6a5cc2a 742 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 743 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 744
dkato 6:aa1fc6a5cc2a 745 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 746 #if defined (__CC_ARM)
dkato 6:aa1fc6a5cc2a 747 #pragma O0
dkato 6:aa1fc6a5cc2a 748 #endif
dkato 6:aa1fc6a5cc2a 749 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 750 int_t SCUX_CopyCancelAll(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 751 {
dkato 6:aa1fc6a5cc2a 752 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 753 int_t dma_ercd;
dkato 6:aa1fc6a5cc2a 754 int_t dma_retval;
dkato 6:aa1fc6a5cc2a 755 int_t was_masked;
dkato 6:aa1fc6a5cc2a 756 uint32_t tx_remain_size = 0;
dkato 6:aa1fc6a5cc2a 757 uint32_t rx_remain_size = 0;
dkato 6:aa1fc6a5cc2a 758
dkato 6:aa1fc6a5cc2a 759 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 760 {
dkato 6:aa1fc6a5cc2a 761 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 762 }
dkato 6:aa1fc6a5cc2a 763 else
dkato 6:aa1fc6a5cc2a 764 {
dkato 6:aa1fc6a5cc2a 765 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 766 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 767 #else
dkato 6:aa1fc6a5cc2a 768 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 769 #endif
dkato 6:aa1fc6a5cc2a 770
dkato 6:aa1fc6a5cc2a 771 dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
dkato 6:aa1fc6a5cc2a 772 /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
dkato 6:aa1fc6a5cc2a 773 if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
dkato 6:aa1fc6a5cc2a 774 {
dkato 6:aa1fc6a5cc2a 775 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 776 }
dkato 6:aa1fc6a5cc2a 777 else
dkato 6:aa1fc6a5cc2a 778 {
dkato 6:aa1fc6a5cc2a 779 p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size;
dkato 6:aa1fc6a5cc2a 780 p_scux_info_ch->dma_tx_current_size = 0;
dkato 6:aa1fc6a5cc2a 781 }
dkato 6:aa1fc6a5cc2a 782
dkato 6:aa1fc6a5cc2a 783 dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd);
dkato 6:aa1fc6a5cc2a 784 /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
dkato 6:aa1fc6a5cc2a 785 if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
dkato 6:aa1fc6a5cc2a 786 {
dkato 6:aa1fc6a5cc2a 787 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 788 }
dkato 6:aa1fc6a5cc2a 789 else
dkato 6:aa1fc6a5cc2a 790 {
dkato 6:aa1fc6a5cc2a 791 p_scux_info_ch->rx_fifo_total_size += p_scux_info_ch->dma_rx_current_size;
dkato 6:aa1fc6a5cc2a 792 p_scux_info_ch->dma_rx_current_size = 0;
dkato 6:aa1fc6a5cc2a 793 }
dkato 6:aa1fc6a5cc2a 794
dkato 6:aa1fc6a5cc2a 795 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 796 {
dkato 6:aa1fc6a5cc2a 797 /* return write request */
dkato 6:aa1fc6a5cc2a 798 if (NULL != p_scux_info_ch->p_tx_aio)
dkato 6:aa1fc6a5cc2a 799 {
dkato 6:aa1fc6a5cc2a 800 p_scux_info_ch->p_tx_aio->aio_return = ECANCELED;
dkato 6:aa1fc6a5cc2a 801 ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);
dkato 6:aa1fc6a5cc2a 802 }
dkato 6:aa1fc6a5cc2a 803
dkato 6:aa1fc6a5cc2a 804 /* return read request */
dkato 6:aa1fc6a5cc2a 805 if (NULL != p_scux_info_ch->p_rx_aio)
dkato 6:aa1fc6a5cc2a 806 {
dkato 6:aa1fc6a5cc2a 807 p_scux_info_ch->p_rx_aio->aio_return = ECANCELED;
dkato 6:aa1fc6a5cc2a 808 ahf_complete(&p_scux_info_ch->rx_que, p_scux_info_ch->p_rx_aio);
dkato 6:aa1fc6a5cc2a 809 }
dkato 6:aa1fc6a5cc2a 810
dkato 6:aa1fc6a5cc2a 811 ahf_cancelall(&p_scux_info_ch->tx_que);
dkato 6:aa1fc6a5cc2a 812 ahf_cancelall(&p_scux_info_ch->rx_que);
dkato 6:aa1fc6a5cc2a 813
dkato 6:aa1fc6a5cc2a 814 p_scux_info_ch->p_tx_aio = NULL;
dkato 6:aa1fc6a5cc2a 815 p_scux_info_ch->p_rx_aio = NULL;
dkato 6:aa1fc6a5cc2a 816
dkato 6:aa1fc6a5cc2a 817 SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, rx_remain_size);
dkato 6:aa1fc6a5cc2a 818 p_scux_info_ch->cancel_operate_flag = true;
dkato 6:aa1fc6a5cc2a 819
dkato 6:aa1fc6a5cc2a 820 if (false != p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 821 {
dkato 6:aa1fc6a5cc2a 822 SCUX_SyncStopHw(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 823 SCUX_InitHw(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 824 SCUX_SetupSrc(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 825 SCUX_SyncStartHw(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 826 }
dkato 6:aa1fc6a5cc2a 827 else
dkato 6:aa1fc6a5cc2a 828 {
dkato 6:aa1fc6a5cc2a 829 SCUX_AsyncStopHw(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 830 SCUX_InitHw(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 831 SCUX_SetupSrc(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 832 SCUX_AsyncStartHw(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 833 }
dkato 6:aa1fc6a5cc2a 834
dkato 6:aa1fc6a5cc2a 835 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
dkato 6:aa1fc6a5cc2a 836 p_scux_info_ch->p_flush_callback = NULL;
dkato 6:aa1fc6a5cc2a 837
dkato 6:aa1fc6a5cc2a 838 p_scux_info_ch->tx_fifo_total_size = 0;
dkato 6:aa1fc6a5cc2a 839 p_scux_info_ch->rx_fifo_total_size = 0;
dkato 6:aa1fc6a5cc2a 840
dkato 6:aa1fc6a5cc2a 841 p_scux_info_ch->cancel_operate_flag = false;
dkato 6:aa1fc6a5cc2a 842 }
dkato 6:aa1fc6a5cc2a 843
dkato 6:aa1fc6a5cc2a 844 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 845 {
dkato 6:aa1fc6a5cc2a 846 __enable_irq();
dkato 6:aa1fc6a5cc2a 847 }
dkato 6:aa1fc6a5cc2a 848 }
dkato 6:aa1fc6a5cc2a 849
dkato 6:aa1fc6a5cc2a 850 return retval;
dkato 6:aa1fc6a5cc2a 851 }
dkato 6:aa1fc6a5cc2a 852
dkato 6:aa1fc6a5cc2a 853 /******************************************************************************
dkato 6:aa1fc6a5cc2a 854 End of function SCUX_CopyCancelAll
dkato 6:aa1fc6a5cc2a 855 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 856
dkato 6:aa1fc6a5cc2a 857 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 858 * Function Name: SCUX_DirectCancelAll
dkato 6:aa1fc6a5cc2a 859 * @brief Cancel all request(SSIF direct route).
dkato 6:aa1fc6a5cc2a 860 *
dkato 6:aa1fc6a5cc2a 861 * Description:<br>
dkato 6:aa1fc6a5cc2a 862 *
dkato 6:aa1fc6a5cc2a 863 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 864 * @retval ESUCCESS : Operation successful.
dkato 6:aa1fc6a5cc2a 865 * EFAULT : Internal error is occured.
dkato 6:aa1fc6a5cc2a 866 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 867
dkato 6:aa1fc6a5cc2a 868 int_t SCUX_DirectCancelAll(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 869 {
dkato 6:aa1fc6a5cc2a 870 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 871 int_t dma_ercd;
dkato 6:aa1fc6a5cc2a 872 int_t dma_retval;
dkato 6:aa1fc6a5cc2a 873 int_t was_masked;
dkato 6:aa1fc6a5cc2a 874 uint32_t tx_remain_size = 0;
dkato 6:aa1fc6a5cc2a 875
dkato 6:aa1fc6a5cc2a 876 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 877 {
dkato 6:aa1fc6a5cc2a 878 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 879 }
dkato 6:aa1fc6a5cc2a 880 else
dkato 6:aa1fc6a5cc2a 881 {
dkato 6:aa1fc6a5cc2a 882 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 883 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 884 #else
dkato 6:aa1fc6a5cc2a 885 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 886 #endif
dkato 6:aa1fc6a5cc2a 887
dkato 6:aa1fc6a5cc2a 888 dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
dkato 6:aa1fc6a5cc2a 889 /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
dkato 6:aa1fc6a5cc2a 890 if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
dkato 6:aa1fc6a5cc2a 891 {
dkato 6:aa1fc6a5cc2a 892 retval = EFAULT;
dkato 6:aa1fc6a5cc2a 893 }
dkato 6:aa1fc6a5cc2a 894 else
dkato 6:aa1fc6a5cc2a 895 {
dkato 6:aa1fc6a5cc2a 896 p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size;
dkato 6:aa1fc6a5cc2a 897 p_scux_info_ch->dma_tx_current_size = 0;
dkato 6:aa1fc6a5cc2a 898
dkato 6:aa1fc6a5cc2a 899 if (NULL != p_scux_info_ch->p_tx_aio)
dkato 6:aa1fc6a5cc2a 900 {
dkato 6:aa1fc6a5cc2a 901 p_scux_info_ch->p_tx_aio->aio_return = ECANCELED;
dkato 6:aa1fc6a5cc2a 902 ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);
dkato 6:aa1fc6a5cc2a 903 }
dkato 6:aa1fc6a5cc2a 904 if (NULL != p_scux_info_ch->p_tx_next_aio)
dkato 6:aa1fc6a5cc2a 905 {
dkato 6:aa1fc6a5cc2a 906 p_scux_info_ch->p_tx_next_aio->aio_return = ECANCELED;
dkato 6:aa1fc6a5cc2a 907 ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_next_aio);
dkato 6:aa1fc6a5cc2a 908 }
dkato 6:aa1fc6a5cc2a 909 ahf_cancelall(&p_scux_info_ch->tx_que);
dkato 6:aa1fc6a5cc2a 910
dkato 6:aa1fc6a5cc2a 911 p_scux_info_ch->p_tx_aio = NULL;
dkato 6:aa1fc6a5cc2a 912 p_scux_info_ch->p_tx_next_aio = NULL;
dkato 6:aa1fc6a5cc2a 913
dkato 6:aa1fc6a5cc2a 914 SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, 0);
dkato 6:aa1fc6a5cc2a 915
dkato 6:aa1fc6a5cc2a 916 p_scux_info_ch->cancel_operate_flag = true;
dkato 6:aa1fc6a5cc2a 917 p_scux_info_ch->restart_ramp_flag = true;
dkato 6:aa1fc6a5cc2a 918
dkato 6:aa1fc6a5cc2a 919 SCUX_AsyncStopHw(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 920
dkato 6:aa1fc6a5cc2a 921 SCUX_InitHw(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 922 SCUX_SetupSsif(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 923 SCUX_SetupSrc(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 924 SCUX_SetupDvu(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 925 SCUX_AsyncStartHw(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 926
dkato 6:aa1fc6a5cc2a 927 p_scux_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
dkato 6:aa1fc6a5cc2a 928 p_scux_info_ch->p_flush_callback = NULL;
dkato 6:aa1fc6a5cc2a 929
dkato 6:aa1fc6a5cc2a 930 p_scux_info_ch->tx_fifo_total_size = 0;
dkato 6:aa1fc6a5cc2a 931 p_scux_info_ch->rx_fifo_total_size = 0;
dkato 6:aa1fc6a5cc2a 932 p_scux_info_ch->dvu_mute_stat = 0;
dkato 6:aa1fc6a5cc2a 933 p_scux_info_ch->first_ramp_flag = false;
dkato 6:aa1fc6a5cc2a 934 p_scux_info_ch->cancel_operate_flag = false;
dkato 6:aa1fc6a5cc2a 935 }
dkato 6:aa1fc6a5cc2a 936
dkato 6:aa1fc6a5cc2a 937 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 938 {
dkato 6:aa1fc6a5cc2a 939 __enable_irq();
dkato 6:aa1fc6a5cc2a 940 }
dkato 6:aa1fc6a5cc2a 941 }
dkato 6:aa1fc6a5cc2a 942
dkato 6:aa1fc6a5cc2a 943 return retval;
dkato 6:aa1fc6a5cc2a 944 }
dkato 6:aa1fc6a5cc2a 945 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 946 #if defined (__CC_ARM)
dkato 6:aa1fc6a5cc2a 947 #pragma O3
dkato 6:aa1fc6a5cc2a 948 #endif
dkato 6:aa1fc6a5cc2a 949 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 950
dkato 6:aa1fc6a5cc2a 951 /******************************************************************************
dkato 6:aa1fc6a5cc2a 952 End of function SCUX_DirectCancelAll
dkato 6:aa1fc6a5cc2a 953 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 954
dkato 6:aa1fc6a5cc2a 955 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 956 * Function Name: SCUX_AdjustAccessFifo
dkato 6:aa1fc6a5cc2a 957 * @brief Fifo is Cleared.
dkato 6:aa1fc6a5cc2a 958 *
dkato 6:aa1fc6a5cc2a 959 * Description:<br>
dkato 6:aa1fc6a5cc2a 960 *
dkato 6:aa1fc6a5cc2a 961 * @param[in] p_scux_info_ch:channel information.
dkato 6:aa1fc6a5cc2a 962 * @retval None.
dkato 6:aa1fc6a5cc2a 963 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 964
dkato 6:aa1fc6a5cc2a 965 void SCUX_AdjustAccessFifo(scux_info_ch_t * const p_scux_info_ch, const uint32_t tx_remain_size, const uint32_t rx_remain_size)
dkato 6:aa1fc6a5cc2a 966 {
dkato 6:aa1fc6a5cc2a 967 uint32_t dummy_data_size;
dkato 6:aa1fc6a5cc2a 968 uint32_t request_data_size;
dkato 6:aa1fc6a5cc2a 969 uint32_t access_size = SCUX_DMA_UNIT_SIZE16;
dkato 6:aa1fc6a5cc2a 970 uint32_t dummy_read_data;
dkato 6:aa1fc6a5cc2a 971
dkato 6:aa1fc6a5cc2a 972 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 973 {
dkato 6:aa1fc6a5cc2a 974 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 975 }
dkato 6:aa1fc6a5cc2a 976 else
dkato 6:aa1fc6a5cc2a 977 {
dkato 6:aa1fc6a5cc2a 978 *(p_scux_info_ch->p_scux_reg->dmacr_cim) &= ~(DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel);
dkato 6:aa1fc6a5cc2a 979 switch (p_scux_info_ch->src_cfg.word_len)
dkato 6:aa1fc6a5cc2a 980 {
dkato 6:aa1fc6a5cc2a 981 case SCUX_DATA_LEN_24 :
dkato 6:aa1fc6a5cc2a 982 access_size = SCUX_DMA_UNIT_SIZE24;
dkato 6:aa1fc6a5cc2a 983 break;
dkato 6:aa1fc6a5cc2a 984
dkato 6:aa1fc6a5cc2a 985 case SCUX_DATA_LEN_16 :
dkato 6:aa1fc6a5cc2a 986 /* fall through */
dkato 6:aa1fc6a5cc2a 987 case SCUX_DATA_LEN_16_TO_24 :
dkato 6:aa1fc6a5cc2a 988 access_size = SCUX_DMA_UNIT_SIZE16;
dkato 6:aa1fc6a5cc2a 989 break;
dkato 6:aa1fc6a5cc2a 990
dkato 6:aa1fc6a5cc2a 991 default :
dkato 6:aa1fc6a5cc2a 992 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 993 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 994 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 995 break;
dkato 6:aa1fc6a5cc2a 996 }
dkato 6:aa1fc6a5cc2a 997
dkato 6:aa1fc6a5cc2a 998 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET |
dkato 6:aa1fc6a5cc2a 999 DEVMR_FFD0_DEVMOF_SET |
dkato 6:aa1fc6a5cc2a 1000 DEVMR_FFD0_DEVMOL_SET |
dkato 6:aa1fc6a5cc2a 1001 DEVMR_FFD0_DEVMIUF_SET);
dkato 6:aa1fc6a5cc2a 1002 /* access count is adjusted for tx DMA remain size */
dkato 6:aa1fc6a5cc2a 1003 if (0U != tx_remain_size)
dkato 6:aa1fc6a5cc2a 1004 {
dkato 6:aa1fc6a5cc2a 1005 for (dummy_data_size = 0; dummy_data_size < tx_remain_size; dummy_data_size += access_size )
dkato 6:aa1fc6a5cc2a 1006 {
dkato 6:aa1fc6a5cc2a 1007 *(p_scux_info_ch->p_scux_reg->dmatd_n_cim) = 0;
dkato 6:aa1fc6a5cc2a 1008 }
dkato 6:aa1fc6a5cc2a 1009 }
dkato 6:aa1fc6a5cc2a 1010
dkato 6:aa1fc6a5cc2a 1011 /* access count is adjusted for tx total remain size */
dkato 6:aa1fc6a5cc2a 1012 if (0U != (p_scux_info_ch->tx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)))
dkato 6:aa1fc6a5cc2a 1013 {
dkato 6:aa1fc6a5cc2a 1014 request_data_size = (p_scux_info_ch->fifo_size - (p_scux_info_ch->tx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)));
dkato 6:aa1fc6a5cc2a 1015 for (dummy_data_size = 0; dummy_data_size < request_data_size; dummy_data_size += access_size )
dkato 6:aa1fc6a5cc2a 1016 {
dkato 6:aa1fc6a5cc2a 1017 *(p_scux_info_ch->p_scux_reg->dmatd_n_cim) = 0;
dkato 6:aa1fc6a5cc2a 1018 }
dkato 6:aa1fc6a5cc2a 1019 }
dkato 6:aa1fc6a5cc2a 1020 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = 0;
dkato 6:aa1fc6a5cc2a 1021 *(p_scux_info_ch->p_scux_reg->dmacr_cim) |= (DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel);
dkato 6:aa1fc6a5cc2a 1022
dkato 6:aa1fc6a5cc2a 1023 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 1024 {
dkato 6:aa1fc6a5cc2a 1025 *(p_scux_info_ch->p_scux_reg->dmacr_cim) &= ~(DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel);
dkato 6:aa1fc6a5cc2a 1026 switch (p_scux_info_ch->src_cfg.word_len)
dkato 6:aa1fc6a5cc2a 1027 {
dkato 6:aa1fc6a5cc2a 1028 case SCUX_DATA_LEN_16 :
dkato 6:aa1fc6a5cc2a 1029 access_size = SCUX_DMA_UNIT_SIZE16;
dkato 6:aa1fc6a5cc2a 1030 break;
dkato 6:aa1fc6a5cc2a 1031
dkato 6:aa1fc6a5cc2a 1032 case SCUX_DATA_LEN_24 :
dkato 6:aa1fc6a5cc2a 1033 /* fall through */
dkato 6:aa1fc6a5cc2a 1034 case SCUX_DATA_LEN_16_TO_24 :
dkato 6:aa1fc6a5cc2a 1035 access_size = SCUX_DMA_UNIT_SIZE24;
dkato 6:aa1fc6a5cc2a 1036 break;
dkato 6:aa1fc6a5cc2a 1037
dkato 6:aa1fc6a5cc2a 1038 default :
dkato 6:aa1fc6a5cc2a 1039 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 1040 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 1041 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 1042 break;
dkato 6:aa1fc6a5cc2a 1043 }
dkato 6:aa1fc6a5cc2a 1044
dkato 6:aa1fc6a5cc2a 1045 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET |
dkato 6:aa1fc6a5cc2a 1046 UEVMR_FFU0_UEVMOF_SET |
dkato 6:aa1fc6a5cc2a 1047 UEVMR_FFU0_UEVMOL_SET);
dkato 6:aa1fc6a5cc2a 1048 /* access count is adjusted for rx DMA remain size */
dkato 6:aa1fc6a5cc2a 1049 if (0U != rx_remain_size)
dkato 6:aa1fc6a5cc2a 1050 {
dkato 6:aa1fc6a5cc2a 1051 for (dummy_data_size = 0; dummy_data_size < rx_remain_size; dummy_data_size += access_size )
dkato 6:aa1fc6a5cc2a 1052 {
dkato 6:aa1fc6a5cc2a 1053 dummy_read_data = *(p_scux_info_ch->p_scux_reg->dmatu_n_cim);
dkato 6:aa1fc6a5cc2a 1054 UNUSED_ARG(dummy_read_data);
dkato 6:aa1fc6a5cc2a 1055 }
dkato 6:aa1fc6a5cc2a 1056 }
dkato 6:aa1fc6a5cc2a 1057
dkato 6:aa1fc6a5cc2a 1058 /* access count is adjusted for rx total remain size */
dkato 6:aa1fc6a5cc2a 1059 if (0U != (p_scux_info_ch->rx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)))
dkato 6:aa1fc6a5cc2a 1060 {
dkato 6:aa1fc6a5cc2a 1061 request_data_size = (p_scux_info_ch->fifo_size - (p_scux_info_ch->rx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)));
dkato 6:aa1fc6a5cc2a 1062
dkato 6:aa1fc6a5cc2a 1063 for (dummy_data_size = 0; dummy_data_size < request_data_size; dummy_data_size += access_size )
dkato 6:aa1fc6a5cc2a 1064 {
dkato 6:aa1fc6a5cc2a 1065 dummy_read_data = *(p_scux_info_ch->p_scux_reg->dmatu_n_cim);
dkato 6:aa1fc6a5cc2a 1066 UNUSED_ARG(dummy_read_data);
dkato 6:aa1fc6a5cc2a 1067 }
dkato 6:aa1fc6a5cc2a 1068 }
dkato 6:aa1fc6a5cc2a 1069 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = 0;
dkato 6:aa1fc6a5cc2a 1070 *(p_scux_info_ch->p_scux_reg->dmacr_cim) |= (DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel);
dkato 6:aa1fc6a5cc2a 1071 }
dkato 6:aa1fc6a5cc2a 1072 }
dkato 6:aa1fc6a5cc2a 1073
dkato 6:aa1fc6a5cc2a 1074 return;
dkato 6:aa1fc6a5cc2a 1075 }
dkato 6:aa1fc6a5cc2a 1076
dkato 6:aa1fc6a5cc2a 1077 /******************************************************************************
dkato 6:aa1fc6a5cc2a 1078 End of function SCUX_AdjustAccessFifo
dkato 6:aa1fc6a5cc2a 1079 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1080
dkato 6:aa1fc6a5cc2a 1081 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 1082 * Function Name: SCUX_SetupSrc
dkato 6:aa1fc6a5cc2a 1083 * @brief SRC HW setup.
dkato 6:aa1fc6a5cc2a 1084 *
dkato 6:aa1fc6a5cc2a 1085 * Description:<br>
dkato 6:aa1fc6a5cc2a 1086 *
dkato 6:aa1fc6a5cc2a 1087 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 1088 * @retval None.
dkato 6:aa1fc6a5cc2a 1089 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1090
dkato 6:aa1fc6a5cc2a 1091 void SCUX_SetupSrc(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 1092 {
dkato 6:aa1fc6a5cc2a 1093 uint32_t process_delay = 0;
dkato 6:aa1fc6a5cc2a 1094 uint32_t data_size;
dkato 6:aa1fc6a5cc2a 1095 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
dkato 6:aa1fc6a5cc2a 1096
dkato 6:aa1fc6a5cc2a 1097 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
dkato 6:aa1fc6a5cc2a 1098 {
dkato 6:aa1fc6a5cc2a 1099 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 1100 }
dkato 6:aa1fc6a5cc2a 1101 else
dkato 6:aa1fc6a5cc2a 1102 {
dkato 6:aa1fc6a5cc2a 1103 if (false != p_scux_info_ch->src_cfg.src_enable)
dkato 6:aa1fc6a5cc2a 1104 {
dkato 6:aa1fc6a5cc2a 1105 /* check delay mode and enabled audio channel */
dkato 6:aa1fc6a5cc2a 1106 switch (p_scux_info_ch->src_cfg.delay_mode)
dkato 6:aa1fc6a5cc2a 1107 {
dkato 6:aa1fc6a5cc2a 1108 case SCUX_DELAY_NORMAL :
dkato 6:aa1fc6a5cc2a 1109 switch (p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 1110 {
dkato 6:aa1fc6a5cc2a 1111 case SCUX_USE_CH_1 :
dkato 6:aa1fc6a5cc2a 1112 process_delay = SCUX_PROCESS_DELAY_NORMAL_CH1;
dkato 6:aa1fc6a5cc2a 1113 break;
dkato 6:aa1fc6a5cc2a 1114
dkato 6:aa1fc6a5cc2a 1115 case SCUX_USE_CH_2 :
dkato 6:aa1fc6a5cc2a 1116 process_delay = SCUX_PROCESS_DELAY_NORMAL_CH2;
dkato 6:aa1fc6a5cc2a 1117 break;
dkato 6:aa1fc6a5cc2a 1118
dkato 6:aa1fc6a5cc2a 1119 case SCUX_USE_CH_4 :
dkato 6:aa1fc6a5cc2a 1120 process_delay = SCUX_PROCESS_DELAY_NORMAL_CH4;
dkato 6:aa1fc6a5cc2a 1121 break;
dkato 6:aa1fc6a5cc2a 1122
dkato 6:aa1fc6a5cc2a 1123 case SCUX_USE_CH_6 :
dkato 6:aa1fc6a5cc2a 1124 process_delay = SCUX_PROCESS_DELAY_NORMAL_CH6;
dkato 6:aa1fc6a5cc2a 1125 break;
dkato 6:aa1fc6a5cc2a 1126
dkato 6:aa1fc6a5cc2a 1127 case SCUX_USE_CH_8 :
dkato 6:aa1fc6a5cc2a 1128 process_delay = SCUX_PROCESS_DELAY_NORMAL_CH8;
dkato 6:aa1fc6a5cc2a 1129 break;
dkato 6:aa1fc6a5cc2a 1130
dkato 6:aa1fc6a5cc2a 1131 default :
dkato 6:aa1fc6a5cc2a 1132 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 1133 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 1134 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 1135 break;
dkato 6:aa1fc6a5cc2a 1136 }
dkato 6:aa1fc6a5cc2a 1137 break;
dkato 6:aa1fc6a5cc2a 1138
dkato 6:aa1fc6a5cc2a 1139 case SCUX_DELAY_LOW_DELAY1 :
dkato 6:aa1fc6a5cc2a 1140 process_delay = SCUX_PROCESS_DELAY_1_CH1_2;
dkato 6:aa1fc6a5cc2a 1141 break;
dkato 6:aa1fc6a5cc2a 1142
dkato 6:aa1fc6a5cc2a 1143 case SCUX_DELAY_LOW_DELAY2 :
dkato 6:aa1fc6a5cc2a 1144 process_delay = SCUX_PROCESS_DELAY_2_CH1_2;
dkato 6:aa1fc6a5cc2a 1145 break;
dkato 6:aa1fc6a5cc2a 1146
dkato 6:aa1fc6a5cc2a 1147 default :
dkato 6:aa1fc6a5cc2a 1148 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 1149 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 1150 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 1151 break;
dkato 6:aa1fc6a5cc2a 1152 }
dkato 6:aa1fc6a5cc2a 1153
dkato 6:aa1fc6a5cc2a 1154 /* set dummy data size for flush */
dkato 6:aa1fc6a5cc2a 1155 if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
dkato 6:aa1fc6a5cc2a 1156 {
dkato 6:aa1fc6a5cc2a 1157 data_size = sizeof(uint16_t);
dkato 6:aa1fc6a5cc2a 1158 }
dkato 6:aa1fc6a5cc2a 1159 else
dkato 6:aa1fc6a5cc2a 1160 {
dkato 6:aa1fc6a5cc2a 1161 data_size = sizeof(uint32_t);
dkato 6:aa1fc6a5cc2a 1162 }
dkato 6:aa1fc6a5cc2a 1163
dkato 6:aa1fc6a5cc2a 1164 process_delay = (process_delay * ((p_scux_info_ch->output_rate * SCUX_RATE_INT_CONV_VALUE) / p_scux_info_ch->input_rate));
dkato 6:aa1fc6a5cc2a 1165 if (0U != (process_delay % SCUX_RATE_INT_CONV_VALUE))
dkato 6:aa1fc6a5cc2a 1166 {
dkato 6:aa1fc6a5cc2a 1167 /* A redundant value is added that delay size below a decimal point may come out */
dkato 6:aa1fc6a5cc2a 1168 process_delay = ((process_delay / SCUX_RATE_INT_CONV_VALUE) + SCUX_ADJUST_REST_VALUE);
dkato 6:aa1fc6a5cc2a 1169 }
dkato 6:aa1fc6a5cc2a 1170 else
dkato 6:aa1fc6a5cc2a 1171 {
dkato 6:aa1fc6a5cc2a 1172 process_delay = (process_delay / SCUX_RATE_INT_CONV_VALUE);
dkato 6:aa1fc6a5cc2a 1173 }
dkato 6:aa1fc6a5cc2a 1174
dkato 6:aa1fc6a5cc2a 1175 p_scux_info_ch->flush_stop_size = (p_scux_info_ch->src_cfg.use_ch * (data_size * (process_delay + SCUX_LOGIC_DELAY_BYPASS_OFF)));
dkato 6:aa1fc6a5cc2a 1176 if (0U != (p_scux_info_ch->flush_stop_size % SCUX_EVEN_VALUE_DIV))
dkato 6:aa1fc6a5cc2a 1177 {
dkato 6:aa1fc6a5cc2a 1178 /* set even value */
dkato 6:aa1fc6a5cc2a 1179 p_scux_info_ch->flush_stop_size++;
dkato 6:aa1fc6a5cc2a 1180 }
dkato 6:aa1fc6a5cc2a 1181 }
dkato 6:aa1fc6a5cc2a 1182 else
dkato 6:aa1fc6a5cc2a 1183 {
dkato 6:aa1fc6a5cc2a 1184 /* set dummy data size for flush */
dkato 6:aa1fc6a5cc2a 1185 if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
dkato 6:aa1fc6a5cc2a 1186 {
dkato 6:aa1fc6a5cc2a 1187 data_size = sizeof(uint16_t);
dkato 6:aa1fc6a5cc2a 1188 }
dkato 6:aa1fc6a5cc2a 1189 else
dkato 6:aa1fc6a5cc2a 1190 {
dkato 6:aa1fc6a5cc2a 1191 data_size = sizeof(uint32_t);
dkato 6:aa1fc6a5cc2a 1192 }
dkato 6:aa1fc6a5cc2a 1193
dkato 6:aa1fc6a5cc2a 1194 p_scux_info_ch->flush_stop_size = (p_scux_info_ch->src_cfg.use_ch * (data_size * SCUX_LOGIC_DELAY_BYPASS_ON));
dkato 6:aa1fc6a5cc2a 1195 if (0U != (p_scux_info_ch->flush_stop_size % SCUX_EVEN_VALUE_DIV))
dkato 6:aa1fc6a5cc2a 1196 {
dkato 6:aa1fc6a5cc2a 1197 /* set even value */
dkato 6:aa1fc6a5cc2a 1198 p_scux_info_ch->flush_stop_size++;
dkato 6:aa1fc6a5cc2a 1199 }
dkato 6:aa1fc6a5cc2a 1200 }
dkato 6:aa1fc6a5cc2a 1201
dkato 6:aa1fc6a5cc2a 1202 p_scux_info_ch->tx_dummy_run_flag = false;
dkato 6:aa1fc6a5cc2a 1203
dkato 6:aa1fc6a5cc2a 1204 /* set FFD & FFU parameter depend on the combination of route and sync mode */
dkato 6:aa1fc6a5cc2a 1205 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 1206 {
dkato 6:aa1fc6a5cc2a 1207 if (false != p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 1208 {
dkato 6:aa1fc6a5cc2a 1209 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_SYNC;
dkato 6:aa1fc6a5cc2a 1210 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_PASS_SET_SYNC;
dkato 6:aa1fc6a5cc2a 1211 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_SYNC;
dkato 6:aa1fc6a5cc2a 1212 p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_SYNC;
dkato 6:aa1fc6a5cc2a 1213 }
dkato 6:aa1fc6a5cc2a 1214 else
dkato 6:aa1fc6a5cc2a 1215 {
dkato 6:aa1fc6a5cc2a 1216 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_ASYNC;
dkato 6:aa1fc6a5cc2a 1217 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_PASS_SET_ASYNC;
dkato 6:aa1fc6a5cc2a 1218 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_ASYNC;
dkato 6:aa1fc6a5cc2a 1219 p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_ASYNC;
dkato 6:aa1fc6a5cc2a 1220 }
dkato 6:aa1fc6a5cc2a 1221 }
dkato 6:aa1fc6a5cc2a 1222 else
dkato 6:aa1fc6a5cc2a 1223 {
dkato 6:aa1fc6a5cc2a 1224 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_ASYNC;
dkato 6:aa1fc6a5cc2a 1225 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = 0;
dkato 6:aa1fc6a5cc2a 1226 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_ASYNC;
dkato 6:aa1fc6a5cc2a 1227 p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_DIRECT;
dkato 6:aa1fc6a5cc2a 1228 }
dkato 6:aa1fc6a5cc2a 1229
dkato 6:aa1fc6a5cc2a 1230 /* set route CIM register for SSIF channel and MIX */
dkato 6:aa1fc6a5cc2a 1231 switch (p_scux_info_ch->route_set)
dkato 6:aa1fc6a5cc2a 1232 {
dkato 6:aa1fc6a5cc2a 1233 case SCUX_ROUTE_SRC0_MEM :
dkato 6:aa1fc6a5cc2a 1234 /* fall through */
dkato 6:aa1fc6a5cc2a 1235 case SCUX_ROUTE_SRC1_MEM :
dkato 6:aa1fc6a5cc2a 1236 /* fall through */
dkato 6:aa1fc6a5cc2a 1237 case SCUX_ROUTE_SRC2_MEM :
dkato 6:aa1fc6a5cc2a 1238 /* fall through */
dkato 6:aa1fc6a5cc2a 1239 case SCUX_ROUTE_SRC3_MEM :
dkato 6:aa1fc6a5cc2a 1240 /* do nothing, when mem to mem route is setting */
dkato 6:aa1fc6a5cc2a 1241 break;
dkato 6:aa1fc6a5cc2a 1242
dkato 6:aa1fc6a5cc2a 1243 case SCUX_ROUTE_SRC0_SSIF0 :
dkato 6:aa1fc6a5cc2a 1244 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
dkato 6:aa1fc6a5cc2a 1245 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_SRC0_SET;
dkato 6:aa1fc6a5cc2a 1246 break;
dkato 6:aa1fc6a5cc2a 1247
dkato 6:aa1fc6a5cc2a 1248 case SCUX_ROUTE_SRC0_SSIF012 :
dkato 6:aa1fc6a5cc2a 1249 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
dkato 6:aa1fc6a5cc2a 1250 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_SRC0_SET | SSIRSEL_CIM_SOSEL1_SRC0_SET | SSIRSEL_CIM_SOSEL2_SRC0_SET);
dkato 6:aa1fc6a5cc2a 1251 break;
dkato 6:aa1fc6a5cc2a 1252
dkato 6:aa1fc6a5cc2a 1253 case SCUX_ROUTE_SRC0_SSIF3 :
dkato 6:aa1fc6a5cc2a 1254 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
dkato 6:aa1fc6a5cc2a 1255 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_SRC0_SET;
dkato 6:aa1fc6a5cc2a 1256 break;
dkato 6:aa1fc6a5cc2a 1257
dkato 6:aa1fc6a5cc2a 1258 case SCUX_ROUTE_SRC0_SSIF345 :
dkato 6:aa1fc6a5cc2a 1259 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
dkato 6:aa1fc6a5cc2a 1260 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_SRC0_SET | SSIRSEL_CIM_SOSEL4_SRC0_SET | SSIRSEL_CIM_SOSEL5_SRC0_SET);
dkato 6:aa1fc6a5cc2a 1261 break;
dkato 6:aa1fc6a5cc2a 1262
dkato 6:aa1fc6a5cc2a 1263 case SCUX_ROUTE_SRC1_SSIF0 :
dkato 6:aa1fc6a5cc2a 1264 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
dkato 6:aa1fc6a5cc2a 1265 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_SRC1_SET;
dkato 6:aa1fc6a5cc2a 1266 break;
dkato 6:aa1fc6a5cc2a 1267
dkato 6:aa1fc6a5cc2a 1268 case SCUX_ROUTE_SRC1_SSIF012 :
dkato 6:aa1fc6a5cc2a 1269 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
dkato 6:aa1fc6a5cc2a 1270 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_SRC1_SET | SSIRSEL_CIM_SOSEL1_SRC1_SET | SSIRSEL_CIM_SOSEL2_SRC1_SET);
dkato 6:aa1fc6a5cc2a 1271 break;
dkato 6:aa1fc6a5cc2a 1272
dkato 6:aa1fc6a5cc2a 1273 case SCUX_ROUTE_SRC1_SSIF3 :
dkato 6:aa1fc6a5cc2a 1274 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
dkato 6:aa1fc6a5cc2a 1275 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_SRC1_SET;
dkato 6:aa1fc6a5cc2a 1276 break;
dkato 6:aa1fc6a5cc2a 1277
dkato 6:aa1fc6a5cc2a 1278 case SCUX_ROUTE_SRC1_SSIF345 :
dkato 6:aa1fc6a5cc2a 1279 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
dkato 6:aa1fc6a5cc2a 1280 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_SRC1_SET | SSIRSEL_CIM_SOSEL4_SRC1_SET | SSIRSEL_CIM_SOSEL5_SRC1_SET);
dkato 6:aa1fc6a5cc2a 1281 break;
dkato 6:aa1fc6a5cc2a 1282
dkato 6:aa1fc6a5cc2a 1283 case SCUX_ROUTE_SRC2_SSIF1 :
dkato 6:aa1fc6a5cc2a 1284 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL1_MASK;
dkato 6:aa1fc6a5cc2a 1285 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL1_SRC2_SET;
dkato 6:aa1fc6a5cc2a 1286 break;
dkato 6:aa1fc6a5cc2a 1287
dkato 6:aa1fc6a5cc2a 1288 case SCUX_ROUTE_SRC2_SSIF4 :
dkato 6:aa1fc6a5cc2a 1289 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL4_MASK;
dkato 6:aa1fc6a5cc2a 1290 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL4_SRC2_SET;
dkato 6:aa1fc6a5cc2a 1291 break;
dkato 6:aa1fc6a5cc2a 1292
dkato 6:aa1fc6a5cc2a 1293 case SCUX_ROUTE_SRC3_SSIF2 :
dkato 6:aa1fc6a5cc2a 1294 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL2_MASK;
dkato 6:aa1fc6a5cc2a 1295 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL2_SRC3_SET;
dkato 6:aa1fc6a5cc2a 1296 break;
dkato 6:aa1fc6a5cc2a 1297
dkato 6:aa1fc6a5cc2a 1298 case SCUX_ROUTE_SRC3_SSIF5 :
dkato 6:aa1fc6a5cc2a 1299 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL5_MASK;
dkato 6:aa1fc6a5cc2a 1300 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL5_SRC3_SET;
dkato 6:aa1fc6a5cc2a 1301 break;
dkato 6:aa1fc6a5cc2a 1302
dkato 6:aa1fc6a5cc2a 1303 case SCUX_ROUTE_SRC0_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1304 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
dkato 6:aa1fc6a5cc2a 1305 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
dkato 6:aa1fc6a5cc2a 1306 break;
dkato 6:aa1fc6a5cc2a 1307
dkato 6:aa1fc6a5cc2a 1308 case SCUX_ROUTE_SRC0_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1309 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
dkato 6:aa1fc6a5cc2a 1310 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
dkato 6:aa1fc6a5cc2a 1311 break;
dkato 6:aa1fc6a5cc2a 1312
dkato 6:aa1fc6a5cc2a 1313 case SCUX_ROUTE_SRC0_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1314 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
dkato 6:aa1fc6a5cc2a 1315 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
dkato 6:aa1fc6a5cc2a 1316 break;
dkato 6:aa1fc6a5cc2a 1317
dkato 6:aa1fc6a5cc2a 1318 case SCUX_ROUTE_SRC0_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1319 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
dkato 6:aa1fc6a5cc2a 1320 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
dkato 6:aa1fc6a5cc2a 1321 break;
dkato 6:aa1fc6a5cc2a 1322
dkato 6:aa1fc6a5cc2a 1323 case SCUX_ROUTE_SRC1_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1324 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
dkato 6:aa1fc6a5cc2a 1325 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
dkato 6:aa1fc6a5cc2a 1326 break;
dkato 6:aa1fc6a5cc2a 1327
dkato 6:aa1fc6a5cc2a 1328 case SCUX_ROUTE_SRC1_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1329 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
dkato 6:aa1fc6a5cc2a 1330 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
dkato 6:aa1fc6a5cc2a 1331 break;
dkato 6:aa1fc6a5cc2a 1332
dkato 6:aa1fc6a5cc2a 1333 case SCUX_ROUTE_SRC1_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1334 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
dkato 6:aa1fc6a5cc2a 1335 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
dkato 6:aa1fc6a5cc2a 1336 break;
dkato 6:aa1fc6a5cc2a 1337
dkato 6:aa1fc6a5cc2a 1338 case SCUX_ROUTE_SRC1_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1339 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
dkato 6:aa1fc6a5cc2a 1340 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
dkato 6:aa1fc6a5cc2a 1341 break;
dkato 6:aa1fc6a5cc2a 1342
dkato 6:aa1fc6a5cc2a 1343 case SCUX_ROUTE_SRC2_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1344 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
dkato 6:aa1fc6a5cc2a 1345 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
dkato 6:aa1fc6a5cc2a 1346 break;
dkato 6:aa1fc6a5cc2a 1347
dkato 6:aa1fc6a5cc2a 1348 case SCUX_ROUTE_SRC2_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1349 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
dkato 6:aa1fc6a5cc2a 1350 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
dkato 6:aa1fc6a5cc2a 1351 break;
dkato 6:aa1fc6a5cc2a 1352
dkato 6:aa1fc6a5cc2a 1353 case SCUX_ROUTE_SRC2_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1354 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
dkato 6:aa1fc6a5cc2a 1355 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
dkato 6:aa1fc6a5cc2a 1356 break;
dkato 6:aa1fc6a5cc2a 1357
dkato 6:aa1fc6a5cc2a 1358 case SCUX_ROUTE_SRC2_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1359 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
dkato 6:aa1fc6a5cc2a 1360 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
dkato 6:aa1fc6a5cc2a 1361 break;
dkato 6:aa1fc6a5cc2a 1362
dkato 6:aa1fc6a5cc2a 1363 case SCUX_ROUTE_SRC3_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1364 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
dkato 6:aa1fc6a5cc2a 1365 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
dkato 6:aa1fc6a5cc2a 1366 break;
dkato 6:aa1fc6a5cc2a 1367
dkato 6:aa1fc6a5cc2a 1368 case SCUX_ROUTE_SRC3_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1369 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
dkato 6:aa1fc6a5cc2a 1370 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
dkato 6:aa1fc6a5cc2a 1371 break;
dkato 6:aa1fc6a5cc2a 1372
dkato 6:aa1fc6a5cc2a 1373 case SCUX_ROUTE_SRC3_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1374 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
dkato 6:aa1fc6a5cc2a 1375 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
dkato 6:aa1fc6a5cc2a 1376 break;
dkato 6:aa1fc6a5cc2a 1377
dkato 6:aa1fc6a5cc2a 1378 case SCUX_ROUTE_SRC3_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1379 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
dkato 6:aa1fc6a5cc2a 1380 *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
dkato 6:aa1fc6a5cc2a 1381 break;
dkato 6:aa1fc6a5cc2a 1382
dkato 6:aa1fc6a5cc2a 1383 default :
dkato 6:aa1fc6a5cc2a 1384 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 1385 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 1386 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 1387 break;
dkato 6:aa1fc6a5cc2a 1388 }
dkato 6:aa1fc6a5cc2a 1389
dkato 6:aa1fc6a5cc2a 1390 SCUX_SetupDataPosition(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 1391
dkato 6:aa1fc6a5cc2a 1392 /* set route SSICTRL register for each route */
dkato 6:aa1fc6a5cc2a 1393 if (false == p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 1394 {
dkato 6:aa1fc6a5cc2a 1395 switch (p_scux_info_ch->route_set)
dkato 6:aa1fc6a5cc2a 1396 {
dkato 6:aa1fc6a5cc2a 1397 case SCUX_ROUTE_SRC0_MEM :
dkato 6:aa1fc6a5cc2a 1398 /* fall through */
dkato 6:aa1fc6a5cc2a 1399 case SCUX_ROUTE_SRC1_MEM :
dkato 6:aa1fc6a5cc2a 1400 /* fall through */
dkato 6:aa1fc6a5cc2a 1401 case SCUX_ROUTE_SRC2_MEM :
dkato 6:aa1fc6a5cc2a 1402 /* fall through */
dkato 6:aa1fc6a5cc2a 1403 case SCUX_ROUTE_SRC3_MEM :
dkato 6:aa1fc6a5cc2a 1404 /* do nothing, when mem to mem route is setting */
dkato 6:aa1fc6a5cc2a 1405 break;
dkato 6:aa1fc6a5cc2a 1406
dkato 6:aa1fc6a5cc2a 1407 case SCUX_ROUTE_SRC0_SSIF0 :
dkato 6:aa1fc6a5cc2a 1408 /* fall through */
dkato 6:aa1fc6a5cc2a 1409 case SCUX_ROUTE_SRC0_SSIF012 :
dkato 6:aa1fc6a5cc2a 1410 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
dkato 6:aa1fc6a5cc2a 1411 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1412 break;
dkato 6:aa1fc6a5cc2a 1413
dkato 6:aa1fc6a5cc2a 1414 case SCUX_ROUTE_SRC0_SSIF3 :
dkato 6:aa1fc6a5cc2a 1415 /* fall through */
dkato 6:aa1fc6a5cc2a 1416 case SCUX_ROUTE_SRC0_SSIF345 :
dkato 6:aa1fc6a5cc2a 1417 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
dkato 6:aa1fc6a5cc2a 1418 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1419 break;
dkato 6:aa1fc6a5cc2a 1420
dkato 6:aa1fc6a5cc2a 1421 case SCUX_ROUTE_SRC1_SSIF0 :
dkato 6:aa1fc6a5cc2a 1422 /* fall through */
dkato 6:aa1fc6a5cc2a 1423 case SCUX_ROUTE_SRC1_SSIF012 :
dkato 6:aa1fc6a5cc2a 1424 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
dkato 6:aa1fc6a5cc2a 1425 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1426 break;
dkato 6:aa1fc6a5cc2a 1427
dkato 6:aa1fc6a5cc2a 1428 case SCUX_ROUTE_SRC1_SSIF3 :
dkato 6:aa1fc6a5cc2a 1429 /* fall through */
dkato 6:aa1fc6a5cc2a 1430 case SCUX_ROUTE_SRC1_SSIF345 :
dkato 6:aa1fc6a5cc2a 1431 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
dkato 6:aa1fc6a5cc2a 1432 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1433 break;
dkato 6:aa1fc6a5cc2a 1434
dkato 6:aa1fc6a5cc2a 1435 case SCUX_ROUTE_SRC2_SSIF1 :
dkato 6:aa1fc6a5cc2a 1436 /* fall through */
dkato 6:aa1fc6a5cc2a 1437 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI1TX_SET;
dkato 6:aa1fc6a5cc2a 1438 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1439 break;
dkato 6:aa1fc6a5cc2a 1440
dkato 6:aa1fc6a5cc2a 1441 case SCUX_ROUTE_SRC2_SSIF4 :
dkato 6:aa1fc6a5cc2a 1442 /* fall through */
dkato 6:aa1fc6a5cc2a 1443 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI4TX_SET;
dkato 6:aa1fc6a5cc2a 1444 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1445 break;
dkato 6:aa1fc6a5cc2a 1446
dkato 6:aa1fc6a5cc2a 1447 case SCUX_ROUTE_SRC3_SSIF2 :
dkato 6:aa1fc6a5cc2a 1448 /* fall through */
dkato 6:aa1fc6a5cc2a 1449 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI2TX_SET;
dkato 6:aa1fc6a5cc2a 1450 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1451 break;
dkato 6:aa1fc6a5cc2a 1452
dkato 6:aa1fc6a5cc2a 1453 case SCUX_ROUTE_SRC3_SSIF5 :
dkato 6:aa1fc6a5cc2a 1454 /* fall through */
dkato 6:aa1fc6a5cc2a 1455 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI5TX_SET;
dkato 6:aa1fc6a5cc2a 1456 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1457 break;
dkato 6:aa1fc6a5cc2a 1458
dkato 6:aa1fc6a5cc2a 1459 case SCUX_ROUTE_SRC0_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1460 /* fall through */
dkato 6:aa1fc6a5cc2a 1461 case SCUX_ROUTE_SRC0_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1462 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
dkato 6:aa1fc6a5cc2a 1463 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1464 break;
dkato 6:aa1fc6a5cc2a 1465
dkato 6:aa1fc6a5cc2a 1466 case SCUX_ROUTE_SRC0_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1467 /* fall through */
dkato 6:aa1fc6a5cc2a 1468 case SCUX_ROUTE_SRC0_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1469 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
dkato 6:aa1fc6a5cc2a 1470 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1471 break;
dkato 6:aa1fc6a5cc2a 1472
dkato 6:aa1fc6a5cc2a 1473 case SCUX_ROUTE_SRC1_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1474 /* fall through */
dkato 6:aa1fc6a5cc2a 1475 case SCUX_ROUTE_SRC1_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1476 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
dkato 6:aa1fc6a5cc2a 1477 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1478 break;
dkato 6:aa1fc6a5cc2a 1479
dkato 6:aa1fc6a5cc2a 1480 case SCUX_ROUTE_SRC1_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1481 /* fall through */
dkato 6:aa1fc6a5cc2a 1482 case SCUX_ROUTE_SRC1_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1483 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
dkato 6:aa1fc6a5cc2a 1484 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1485 break;
dkato 6:aa1fc6a5cc2a 1486
dkato 6:aa1fc6a5cc2a 1487 case SCUX_ROUTE_SRC2_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1488 /* fall through */
dkato 6:aa1fc6a5cc2a 1489 case SCUX_ROUTE_SRC2_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1490 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
dkato 6:aa1fc6a5cc2a 1491 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1492 break;
dkato 6:aa1fc6a5cc2a 1493
dkato 6:aa1fc6a5cc2a 1494 case SCUX_ROUTE_SRC2_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1495 /* fall through */
dkato 6:aa1fc6a5cc2a 1496 case SCUX_ROUTE_SRC2_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1497 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
dkato 6:aa1fc6a5cc2a 1498 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1499 break;
dkato 6:aa1fc6a5cc2a 1500
dkato 6:aa1fc6a5cc2a 1501 case SCUX_ROUTE_SRC3_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1502 /* fall through */
dkato 6:aa1fc6a5cc2a 1503 case SCUX_ROUTE_SRC3_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1504 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
dkato 6:aa1fc6a5cc2a 1505 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1506 break;
dkato 6:aa1fc6a5cc2a 1507
dkato 6:aa1fc6a5cc2a 1508 case SCUX_ROUTE_SRC3_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1509 /* fall through */
dkato 6:aa1fc6a5cc2a 1510 case SCUX_ROUTE_SRC3_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1511 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
dkato 6:aa1fc6a5cc2a 1512 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 1513 break;
dkato 6:aa1fc6a5cc2a 1514
dkato 6:aa1fc6a5cc2a 1515 default :
dkato 6:aa1fc6a5cc2a 1516 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 1517 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 1518 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 1519 break;
dkato 6:aa1fc6a5cc2a 1520 }
dkato 6:aa1fc6a5cc2a 1521 }
dkato 6:aa1fc6a5cc2a 1522
dkato 6:aa1fc6a5cc2a 1523 SCUX_SetupSrcClk(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 1524
dkato 6:aa1fc6a5cc2a 1525 /* set pin mode for each route */
dkato 6:aa1fc6a5cc2a 1526 switch (p_scux_info_ch->route_set)
dkato 6:aa1fc6a5cc2a 1527 {
dkato 6:aa1fc6a5cc2a 1528 case SCUX_ROUTE_SRC0_MEM :
dkato 6:aa1fc6a5cc2a 1529 /* fall through */
dkato 6:aa1fc6a5cc2a 1530 case SCUX_ROUTE_SRC1_MEM :
dkato 6:aa1fc6a5cc2a 1531 /* fall through */
dkato 6:aa1fc6a5cc2a 1532 case SCUX_ROUTE_SRC2_MEM :
dkato 6:aa1fc6a5cc2a 1533 /* fall through */
dkato 6:aa1fc6a5cc2a 1534 case SCUX_ROUTE_SRC3_MEM :
dkato 6:aa1fc6a5cc2a 1535 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1536 break;
dkato 6:aa1fc6a5cc2a 1537
dkato 6:aa1fc6a5cc2a 1538 case SCUX_ROUTE_SRC0_SSIF0 :
dkato 6:aa1fc6a5cc2a 1539 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1540 break;
dkato 6:aa1fc6a5cc2a 1541
dkato 6:aa1fc6a5cc2a 1542 case SCUX_ROUTE_SRC0_SSIF012 :
dkato 6:aa1fc6a5cc2a 1543 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
dkato 6:aa1fc6a5cc2a 1544 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
dkato 6:aa1fc6a5cc2a 1545 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
dkato 6:aa1fc6a5cc2a 1546 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 1547 {
dkato 6:aa1fc6a5cc2a 1548 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1549 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1550 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1551 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1552 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1553 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1554 }
dkato 6:aa1fc6a5cc2a 1555 else
dkato 6:aa1fc6a5cc2a 1556 {
dkato 6:aa1fc6a5cc2a 1557 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1558 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1559 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1560 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1561 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1562 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1563 }
dkato 6:aa1fc6a5cc2a 1564 break;
dkato 6:aa1fc6a5cc2a 1565
dkato 6:aa1fc6a5cc2a 1566 case SCUX_ROUTE_SRC0_SSIF3 :
dkato 6:aa1fc6a5cc2a 1567 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1568 break;
dkato 6:aa1fc6a5cc2a 1569
dkato 6:aa1fc6a5cc2a 1570 case SCUX_ROUTE_SRC0_SSIF345 :
dkato 6:aa1fc6a5cc2a 1571 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
dkato 6:aa1fc6a5cc2a 1572 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
dkato 6:aa1fc6a5cc2a 1573 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
dkato 6:aa1fc6a5cc2a 1574 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 1575 {
dkato 6:aa1fc6a5cc2a 1576 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1577 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1578 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1579 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1580 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1581 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1582 }
dkato 6:aa1fc6a5cc2a 1583 else
dkato 6:aa1fc6a5cc2a 1584 {
dkato 6:aa1fc6a5cc2a 1585 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1586 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1587 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1588 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1589 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1590 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1591 }
dkato 6:aa1fc6a5cc2a 1592 break;
dkato 6:aa1fc6a5cc2a 1593
dkato 6:aa1fc6a5cc2a 1594 case SCUX_ROUTE_SRC1_SSIF0 :
dkato 6:aa1fc6a5cc2a 1595 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1596 break;
dkato 6:aa1fc6a5cc2a 1597
dkato 6:aa1fc6a5cc2a 1598 case SCUX_ROUTE_SRC1_SSIF012 :
dkato 6:aa1fc6a5cc2a 1599 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
dkato 6:aa1fc6a5cc2a 1600 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
dkato 6:aa1fc6a5cc2a 1601 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
dkato 6:aa1fc6a5cc2a 1602 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 1603 {
dkato 6:aa1fc6a5cc2a 1604 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1605 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1606 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1607 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1608 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1609 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1610 }
dkato 6:aa1fc6a5cc2a 1611 else
dkato 6:aa1fc6a5cc2a 1612 {
dkato 6:aa1fc6a5cc2a 1613 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1614 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1615 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1616 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1617 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1618 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1619 }
dkato 6:aa1fc6a5cc2a 1620 break;
dkato 6:aa1fc6a5cc2a 1621
dkato 6:aa1fc6a5cc2a 1622 case SCUX_ROUTE_SRC1_SSIF3 :
dkato 6:aa1fc6a5cc2a 1623 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1624 break;
dkato 6:aa1fc6a5cc2a 1625
dkato 6:aa1fc6a5cc2a 1626 case SCUX_ROUTE_SRC1_SSIF345 :
dkato 6:aa1fc6a5cc2a 1627 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
dkato 6:aa1fc6a5cc2a 1628 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
dkato 6:aa1fc6a5cc2a 1629 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
dkato 6:aa1fc6a5cc2a 1630 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 1631 {
dkato 6:aa1fc6a5cc2a 1632 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1633 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1634 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1635 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1636 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1637 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1638 }
dkato 6:aa1fc6a5cc2a 1639 else
dkato 6:aa1fc6a5cc2a 1640 {
dkato 6:aa1fc6a5cc2a 1641 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1642 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1643 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1644 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1645 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1646 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1647 }
dkato 6:aa1fc6a5cc2a 1648 break;
dkato 6:aa1fc6a5cc2a 1649
dkato 6:aa1fc6a5cc2a 1650 case SCUX_ROUTE_SRC2_SSIF1 :
dkato 6:aa1fc6a5cc2a 1651 /* fall through */
dkato 6:aa1fc6a5cc2a 1652 case SCUX_ROUTE_SRC2_SSIF4 :
dkato 6:aa1fc6a5cc2a 1653 /* fall through */
dkato 6:aa1fc6a5cc2a 1654 case SCUX_ROUTE_SRC3_SSIF2 :
dkato 6:aa1fc6a5cc2a 1655 /* fall through */
dkato 6:aa1fc6a5cc2a 1656 case SCUX_ROUTE_SRC3_SSIF5 :
dkato 6:aa1fc6a5cc2a 1657 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1658 break;
dkato 6:aa1fc6a5cc2a 1659
dkato 6:aa1fc6a5cc2a 1660 case SCUX_ROUTE_SRC0_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1661 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1662 break;
dkato 6:aa1fc6a5cc2a 1663
dkato 6:aa1fc6a5cc2a 1664 case SCUX_ROUTE_SRC0_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1665 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
dkato 6:aa1fc6a5cc2a 1666 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
dkato 6:aa1fc6a5cc2a 1667 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
dkato 6:aa1fc6a5cc2a 1668 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 1669 {
dkato 6:aa1fc6a5cc2a 1670 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1671 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1672 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1673 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1674 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1675 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1676 }
dkato 6:aa1fc6a5cc2a 1677 else
dkato 6:aa1fc6a5cc2a 1678 {
dkato 6:aa1fc6a5cc2a 1679 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1680 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1681 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1682 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1683 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1684 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1685 }
dkato 6:aa1fc6a5cc2a 1686 break;
dkato 6:aa1fc6a5cc2a 1687
dkato 6:aa1fc6a5cc2a 1688 case SCUX_ROUTE_SRC0_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1689 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1690 break;
dkato 6:aa1fc6a5cc2a 1691
dkato 6:aa1fc6a5cc2a 1692 case SCUX_ROUTE_SRC0_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1693 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
dkato 6:aa1fc6a5cc2a 1694 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
dkato 6:aa1fc6a5cc2a 1695 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
dkato 6:aa1fc6a5cc2a 1696 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 1697 {
dkato 6:aa1fc6a5cc2a 1698 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1699 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1700 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1701 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1702 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1703 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1704 }
dkato 6:aa1fc6a5cc2a 1705 else
dkato 6:aa1fc6a5cc2a 1706 {
dkato 6:aa1fc6a5cc2a 1707 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1708 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1709 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1710 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1711 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1712 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1713 }
dkato 6:aa1fc6a5cc2a 1714 break;
dkato 6:aa1fc6a5cc2a 1715
dkato 6:aa1fc6a5cc2a 1716 case SCUX_ROUTE_SRC1_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1717 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1718 break;
dkato 6:aa1fc6a5cc2a 1719
dkato 6:aa1fc6a5cc2a 1720 case SCUX_ROUTE_SRC1_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1721 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
dkato 6:aa1fc6a5cc2a 1722 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
dkato 6:aa1fc6a5cc2a 1723 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
dkato 6:aa1fc6a5cc2a 1724 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 1725 {
dkato 6:aa1fc6a5cc2a 1726 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1727 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1728 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1729 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1730 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1731 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1732 }
dkato 6:aa1fc6a5cc2a 1733 else
dkato 6:aa1fc6a5cc2a 1734 {
dkato 6:aa1fc6a5cc2a 1735 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1736 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1737 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1738 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1739 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1740 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1741 }
dkato 6:aa1fc6a5cc2a 1742 break;
dkato 6:aa1fc6a5cc2a 1743
dkato 6:aa1fc6a5cc2a 1744 case SCUX_ROUTE_SRC1_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1745 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1746 break;
dkato 6:aa1fc6a5cc2a 1747
dkato 6:aa1fc6a5cc2a 1748 case SCUX_ROUTE_SRC1_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1749 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
dkato 6:aa1fc6a5cc2a 1750 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
dkato 6:aa1fc6a5cc2a 1751 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
dkato 6:aa1fc6a5cc2a 1752 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 1753 {
dkato 6:aa1fc6a5cc2a 1754 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1755 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1756 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1757 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1758 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1759 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1760 }
dkato 6:aa1fc6a5cc2a 1761 else
dkato 6:aa1fc6a5cc2a 1762 {
dkato 6:aa1fc6a5cc2a 1763 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1764 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1765 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1766 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1767 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1768 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1769 }
dkato 6:aa1fc6a5cc2a 1770 break;
dkato 6:aa1fc6a5cc2a 1771
dkato 6:aa1fc6a5cc2a 1772 case SCUX_ROUTE_SRC2_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1773 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1774 break;
dkato 6:aa1fc6a5cc2a 1775
dkato 6:aa1fc6a5cc2a 1776 case SCUX_ROUTE_SRC2_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1777 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
dkato 6:aa1fc6a5cc2a 1778 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
dkato 6:aa1fc6a5cc2a 1779 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
dkato 6:aa1fc6a5cc2a 1780 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 1781 {
dkato 6:aa1fc6a5cc2a 1782 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1783 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1784 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1785 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1786 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1787 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1788 }
dkato 6:aa1fc6a5cc2a 1789 else
dkato 6:aa1fc6a5cc2a 1790 {
dkato 6:aa1fc6a5cc2a 1791 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1792 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1793 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1794 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1795 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1796 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1797 }
dkato 6:aa1fc6a5cc2a 1798 break;
dkato 6:aa1fc6a5cc2a 1799
dkato 6:aa1fc6a5cc2a 1800 case SCUX_ROUTE_SRC2_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1801 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1802 break;
dkato 6:aa1fc6a5cc2a 1803
dkato 6:aa1fc6a5cc2a 1804 case SCUX_ROUTE_SRC2_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1805 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
dkato 6:aa1fc6a5cc2a 1806 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
dkato 6:aa1fc6a5cc2a 1807 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
dkato 6:aa1fc6a5cc2a 1808 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 1809 {
dkato 6:aa1fc6a5cc2a 1810 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1811 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1812 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1813 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1814 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1815 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1816 }
dkato 6:aa1fc6a5cc2a 1817 else
dkato 6:aa1fc6a5cc2a 1818 {
dkato 6:aa1fc6a5cc2a 1819 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1820 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1821 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1822 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1823 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1824 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1825 }
dkato 6:aa1fc6a5cc2a 1826 break;
dkato 6:aa1fc6a5cc2a 1827
dkato 6:aa1fc6a5cc2a 1828 case SCUX_ROUTE_SRC3_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 1829 /* fall through */
dkato 6:aa1fc6a5cc2a 1830 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1831 break;
dkato 6:aa1fc6a5cc2a 1832
dkato 6:aa1fc6a5cc2a 1833 case SCUX_ROUTE_SRC3_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 1834 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
dkato 6:aa1fc6a5cc2a 1835 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
dkato 6:aa1fc6a5cc2a 1836 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
dkato 6:aa1fc6a5cc2a 1837 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 1838 {
dkato 6:aa1fc6a5cc2a 1839 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1840 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1841 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1842 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1843 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1844 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1845 }
dkato 6:aa1fc6a5cc2a 1846 else
dkato 6:aa1fc6a5cc2a 1847 {
dkato 6:aa1fc6a5cc2a 1848 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1849 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1850 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1851 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1852 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1853 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1854 }
dkato 6:aa1fc6a5cc2a 1855 break;
dkato 6:aa1fc6a5cc2a 1856
dkato 6:aa1fc6a5cc2a 1857 case SCUX_ROUTE_SRC3_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 1858 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
dkato 6:aa1fc6a5cc2a 1859 break;
dkato 6:aa1fc6a5cc2a 1860
dkato 6:aa1fc6a5cc2a 1861 case SCUX_ROUTE_SRC3_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 1862 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
dkato 6:aa1fc6a5cc2a 1863 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
dkato 6:aa1fc6a5cc2a 1864 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
dkato 6:aa1fc6a5cc2a 1865 if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 1866 {
dkato 6:aa1fc6a5cc2a 1867 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1868 (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1869 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1870 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1871 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1872 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
dkato 6:aa1fc6a5cc2a 1873 }
dkato 6:aa1fc6a5cc2a 1874 else
dkato 6:aa1fc6a5cc2a 1875 {
dkato 6:aa1fc6a5cc2a 1876 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
dkato 6:aa1fc6a5cc2a 1877 (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
dkato 6:aa1fc6a5cc2a 1878 p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
dkato 6:aa1fc6a5cc2a 1879 p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1880 p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
dkato 6:aa1fc6a5cc2a 1881 p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
dkato 6:aa1fc6a5cc2a 1882 }
dkato 6:aa1fc6a5cc2a 1883 break;
dkato 6:aa1fc6a5cc2a 1884
dkato 6:aa1fc6a5cc2a 1885 default :
dkato 6:aa1fc6a5cc2a 1886 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 1887 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 1888 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 1889 break;
dkato 6:aa1fc6a5cc2a 1890 }
dkato 6:aa1fc6a5cc2a 1891
dkato 6:aa1fc6a5cc2a 1892 SCUX_SetupFifo(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 1893 SCUX_SetupSrcFunction(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 1894 }
dkato 6:aa1fc6a5cc2a 1895
dkato 6:aa1fc6a5cc2a 1896 return;
dkato 6:aa1fc6a5cc2a 1897 }
dkato 6:aa1fc6a5cc2a 1898
dkato 6:aa1fc6a5cc2a 1899 /******************************************************************************
dkato 6:aa1fc6a5cc2a 1900 End of function SCUX_SetupSrc
dkato 6:aa1fc6a5cc2a 1901 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1902
dkato 6:aa1fc6a5cc2a 1903 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 1904 * Function Name: SCUX_SetupDataPosition
dkato 6:aa1fc6a5cc2a 1905 * @brief Audio data position setup.
dkato 6:aa1fc6a5cc2a 1906 *
dkato 6:aa1fc6a5cc2a 1907 * Description:<br>
dkato 6:aa1fc6a5cc2a 1908 *
dkato 6:aa1fc6a5cc2a 1909 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 1910 * @retval None.
dkato 6:aa1fc6a5cc2a 1911 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1912
dkato 6:aa1fc6a5cc2a 1913 static void SCUX_SetupDataPosition(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 1914 {
dkato 6:aa1fc6a5cc2a 1915 int_t audio_ch;
dkato 6:aa1fc6a5cc2a 1916 uint32_t audio_place = 0;
dkato 6:aa1fc6a5cc2a 1917 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
dkato 6:aa1fc6a5cc2a 1918
dkato 6:aa1fc6a5cc2a 1919 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
dkato 6:aa1fc6a5cc2a 1920 {
dkato 6:aa1fc6a5cc2a 1921 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 1922 }
dkato 6:aa1fc6a5cc2a 1923 else
dkato 6:aa1fc6a5cc2a 1924 {
dkato 6:aa1fc6a5cc2a 1925 /* set data posion for SRC */
dkato 6:aa1fc6a5cc2a 1926 for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
dkato 6:aa1fc6a5cc2a 1927 {
dkato 6:aa1fc6a5cc2a 1928 audio_place |= (((uint32_t)p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch] & SRCRSEL_CIM_PLACE_N_MASK) << ((uint32_t)audio_ch * SRCRSEL_CIM_PLACE_N_SHIFT));
dkato 6:aa1fc6a5cc2a 1929 }
dkato 6:aa1fc6a5cc2a 1930 *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = audio_place;
dkato 6:aa1fc6a5cc2a 1931
dkato 6:aa1fc6a5cc2a 1932 /* set data position for MIX */
dkato 6:aa1fc6a5cc2a 1933 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 1934 {
dkato 6:aa1fc6a5cc2a 1935 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 1936 {
dkato 6:aa1fc6a5cc2a 1937 audio_place = 0;
dkato 6:aa1fc6a5cc2a 1938 for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
dkato 6:aa1fc6a5cc2a 1939 {
dkato 6:aa1fc6a5cc2a 1940 audio_place |= (((uint32_t)p_info_drv->shared_info.select_out_data_ch[audio_ch] & MIXRSEL_CIM_PLACE_N_MASK) << ((uint32_t)audio_ch * MIXRSEL_CIM_PLACE_N_SHIFT));
dkato 6:aa1fc6a5cc2a 1941 }
dkato 6:aa1fc6a5cc2a 1942 *(p_scux_info_ch->p_scux_reg->mixrsel_cim) = audio_place;
dkato 6:aa1fc6a5cc2a 1943 }
dkato 6:aa1fc6a5cc2a 1944 }
dkato 6:aa1fc6a5cc2a 1945 }
dkato 6:aa1fc6a5cc2a 1946
dkato 6:aa1fc6a5cc2a 1947 return;
dkato 6:aa1fc6a5cc2a 1948 }
dkato 6:aa1fc6a5cc2a 1949
dkato 6:aa1fc6a5cc2a 1950 /******************************************************************************
dkato 6:aa1fc6a5cc2a 1951 End of function SCUX_SetupDataPosition
dkato 6:aa1fc6a5cc2a 1952 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1953
dkato 6:aa1fc6a5cc2a 1954 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 1955 * Function Name: SCUX_SetupSrcClk
dkato 6:aa1fc6a5cc2a 1956 * @brief SRC clock setup.
dkato 6:aa1fc6a5cc2a 1957 *
dkato 6:aa1fc6a5cc2a 1958 * Description:<br>
dkato 6:aa1fc6a5cc2a 1959 *
dkato 6:aa1fc6a5cc2a 1960 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 1961 * @retval None.
dkato 6:aa1fc6a5cc2a 1962 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 1963
dkato 6:aa1fc6a5cc2a 1964 static void SCUX_SetupSrcClk(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 1965 {
dkato 6:aa1fc6a5cc2a 1966 uint32_t fdtsel_value = 0;
dkato 6:aa1fc6a5cc2a 1967
dkato 6:aa1fc6a5cc2a 1968 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 1969 {
dkato 6:aa1fc6a5cc2a 1970 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 1971 }
dkato 6:aa1fc6a5cc2a 1972 else
dkato 6:aa1fc6a5cc2a 1973 {
dkato 6:aa1fc6a5cc2a 1974 /* set input timing clock */
dkato 6:aa1fc6a5cc2a 1975 if (false == p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 1976 {
dkato 6:aa1fc6a5cc2a 1977 /* get value of register setting */
dkato 6:aa1fc6a5cc2a 1978 switch (p_scux_info_ch->src_cfg.input_clk_async)
dkato 6:aa1fc6a5cc2a 1979 {
dkato 6:aa1fc6a5cc2a 1980
dkato 6:aa1fc6a5cc2a 1981 case SCUX_CLK_AUDIO_CLK :
dkato 6:aa1fc6a5cc2a 1982 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 1983 FDTSEL_CIM_SCKSEL_AUDIO_CLK_SET);
dkato 6:aa1fc6a5cc2a 1984 break;
dkato 6:aa1fc6a5cc2a 1985
dkato 6:aa1fc6a5cc2a 1986 case SCUX_CLK_AUDIO_X1 :
dkato 6:aa1fc6a5cc2a 1987 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 1988 FDTSEL_CIM_SCKSEL_AUDIO_X1_SET);
dkato 6:aa1fc6a5cc2a 1989 break;
dkato 6:aa1fc6a5cc2a 1990
dkato 6:aa1fc6a5cc2a 1991 case SCUX_CLK_MLB_CLK :
dkato 6:aa1fc6a5cc2a 1992 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 1993 FDTSEL_CIM_SCKSEL_MLB_CLK_SET);
dkato 6:aa1fc6a5cc2a 1994 break;
dkato 6:aa1fc6a5cc2a 1995
dkato 6:aa1fc6a5cc2a 1996 case SCUX_CLK_USB_X1 :
dkato 6:aa1fc6a5cc2a 1997 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 1998 FDTSEL_CIM_SCKSEL_USB_X1_SET);
dkato 6:aa1fc6a5cc2a 1999 break;
dkato 6:aa1fc6a5cc2a 2000
dkato 6:aa1fc6a5cc2a 2001 case SCUX_CLK_CLKP1_2 :
dkato 6:aa1fc6a5cc2a 2002 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 2003 FDTSEL_CIM_SCKSEL_CLKP1_2_SET);
dkato 6:aa1fc6a5cc2a 2004 break;
dkato 6:aa1fc6a5cc2a 2005
dkato 6:aa1fc6a5cc2a 2006 case SCUX_CLK_MTU_TIOC3A :
dkato 6:aa1fc6a5cc2a 2007 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 2008 FDTSEL_CIM_SCKSEL_MTUSEL2_SET |
dkato 6:aa1fc6a5cc2a 2009 FDTSEL_CIM_MTUSEL_SET_TIOC3A);
dkato 6:aa1fc6a5cc2a 2010 break;
dkato 6:aa1fc6a5cc2a 2011
dkato 6:aa1fc6a5cc2a 2012 case SCUX_CLK_MTU_TIOC4A :
dkato 6:aa1fc6a5cc2a 2013 fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 2014 FDTSEL_CIM_SCKSEL_MTUSEL2_SET |
dkato 6:aa1fc6a5cc2a 2015 FDTSEL_CIM_MTUSEL_SET_TIOC4A);
dkato 6:aa1fc6a5cc2a 2016 break;
dkato 6:aa1fc6a5cc2a 2017
dkato 6:aa1fc6a5cc2a 2018 case SCUX_CLK_SSIF0_WS :
dkato 6:aa1fc6a5cc2a 2019 fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF0_WS_SET;
dkato 6:aa1fc6a5cc2a 2020 break;
dkato 6:aa1fc6a5cc2a 2021
dkato 6:aa1fc6a5cc2a 2022 case SCUX_CLK_SSIF1_WS :
dkato 6:aa1fc6a5cc2a 2023 fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF1_WS_SET;
dkato 6:aa1fc6a5cc2a 2024 break;
dkato 6:aa1fc6a5cc2a 2025
dkato 6:aa1fc6a5cc2a 2026 case SCUX_CLK_SSIF2_WS :
dkato 6:aa1fc6a5cc2a 2027 fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF2_WS_SET;
dkato 6:aa1fc6a5cc2a 2028 break;
dkato 6:aa1fc6a5cc2a 2029
dkato 6:aa1fc6a5cc2a 2030 case SCUX_CLK_SSIF3_WS :
dkato 6:aa1fc6a5cc2a 2031 fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF3_WS_SET;
dkato 6:aa1fc6a5cc2a 2032 break;
dkato 6:aa1fc6a5cc2a 2033
dkato 6:aa1fc6a5cc2a 2034 case SCUX_CLK_SSIF4_WS :
dkato 6:aa1fc6a5cc2a 2035 fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF4_WS_SET;
dkato 6:aa1fc6a5cc2a 2036 break;
dkato 6:aa1fc6a5cc2a 2037
dkato 6:aa1fc6a5cc2a 2038 case SCUX_CLK_SSIF5_WS :
dkato 6:aa1fc6a5cc2a 2039 fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF5_WS_SET;
dkato 6:aa1fc6a5cc2a 2040 break;
dkato 6:aa1fc6a5cc2a 2041
dkato 6:aa1fc6a5cc2a 2042 default :
dkato 6:aa1fc6a5cc2a 2043 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 2044 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 2045 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2046 break;
dkato 6:aa1fc6a5cc2a 2047 }
dkato 6:aa1fc6a5cc2a 2048 *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) = fdtsel_value;
dkato 6:aa1fc6a5cc2a 2049 }
dkato 6:aa1fc6a5cc2a 2050
dkato 6:aa1fc6a5cc2a 2051 /* set output timing clock on MIX */
dkato 6:aa1fc6a5cc2a 2052 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 2053 {
dkato 6:aa1fc6a5cc2a 2054 p_scux_info_ch->futsel_cim_value = (((0 << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 2055 (((uint32_t)p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num | FUTSEL_CIM_SCKSEL_SSIF0_WS_SET) & FUTSEL_CIM_SCKSEL_MASK));
dkato 6:aa1fc6a5cc2a 2056 *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
dkato 6:aa1fc6a5cc2a 2057 }
dkato 6:aa1fc6a5cc2a 2058 else if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 2059 {
dkato 6:aa1fc6a5cc2a 2060 /* set output timing clock on other MIX */
dkato 6:aa1fc6a5cc2a 2061 if (false == p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 2062 {
dkato 6:aa1fc6a5cc2a 2063 switch (p_scux_info_ch->src_cfg.output_clk_async)
dkato 6:aa1fc6a5cc2a 2064 {
dkato 6:aa1fc6a5cc2a 2065 case SCUX_CLK_AUDIO_CLK :
dkato 6:aa1fc6a5cc2a 2066 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 2067 FUTSEL_CIM_SCKSEL_AUDIO_CLK_SET);
dkato 6:aa1fc6a5cc2a 2068 break;
dkato 6:aa1fc6a5cc2a 2069
dkato 6:aa1fc6a5cc2a 2070 case SCUX_CLK_AUDIO_X1 :
dkato 6:aa1fc6a5cc2a 2071 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 2072 FUTSEL_CIM_SCKSEL_AUDIO_X1_SET);
dkato 6:aa1fc6a5cc2a 2073 break;
dkato 6:aa1fc6a5cc2a 2074
dkato 6:aa1fc6a5cc2a 2075 case SCUX_CLK_MLB_CLK :
dkato 6:aa1fc6a5cc2a 2076 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 2077 FUTSEL_CIM_SCKSEL_MLB_CLK_SET);
dkato 6:aa1fc6a5cc2a 2078 break;
dkato 6:aa1fc6a5cc2a 2079
dkato 6:aa1fc6a5cc2a 2080 case SCUX_CLK_USB_X1 :
dkato 6:aa1fc6a5cc2a 2081 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 2082 FUTSEL_CIM_SCKSEL_USB_X1_SET);
dkato 6:aa1fc6a5cc2a 2083 break;
dkato 6:aa1fc6a5cc2a 2084
dkato 6:aa1fc6a5cc2a 2085 case SCUX_CLK_CLKP1_2 :
dkato 6:aa1fc6a5cc2a 2086 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 2087 FUTSEL_CIM_SCKSEL_CLKP1_2_SET);
dkato 6:aa1fc6a5cc2a 2088 break;
dkato 6:aa1fc6a5cc2a 2089
dkato 6:aa1fc6a5cc2a 2090 case SCUX_CLK_MTU_TIOC3A :
dkato 6:aa1fc6a5cc2a 2091 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 2092 FUTSEL_CIM_SCKSEL_MTUSEL2_SET |
dkato 6:aa1fc6a5cc2a 2093 FUTSEL_CIM_MTUSEL_SET_TIOC3A);
dkato 6:aa1fc6a5cc2a 2094 break;
dkato 6:aa1fc6a5cc2a 2095
dkato 6:aa1fc6a5cc2a 2096 case SCUX_CLK_MTU_TIOC4A :
dkato 6:aa1fc6a5cc2a 2097 p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
dkato 6:aa1fc6a5cc2a 2098 FUTSEL_CIM_SCKSEL_MTUSEL2_SET |
dkato 6:aa1fc6a5cc2a 2099 FUTSEL_CIM_MTUSEL_SET_TIOC4A);
dkato 6:aa1fc6a5cc2a 2100 break;
dkato 6:aa1fc6a5cc2a 2101
dkato 6:aa1fc6a5cc2a 2102 case SCUX_CLK_SSIF0_WS :
dkato 6:aa1fc6a5cc2a 2103 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF0_WS_SET;
dkato 6:aa1fc6a5cc2a 2104 break;
dkato 6:aa1fc6a5cc2a 2105
dkato 6:aa1fc6a5cc2a 2106 case SCUX_CLK_SSIF1_WS :
dkato 6:aa1fc6a5cc2a 2107 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF1_WS_SET;
dkato 6:aa1fc6a5cc2a 2108 break;
dkato 6:aa1fc6a5cc2a 2109
dkato 6:aa1fc6a5cc2a 2110 case SCUX_CLK_SSIF2_WS :
dkato 6:aa1fc6a5cc2a 2111 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF2_WS_SET;
dkato 6:aa1fc6a5cc2a 2112 break;
dkato 6:aa1fc6a5cc2a 2113
dkato 6:aa1fc6a5cc2a 2114 case SCUX_CLK_SSIF3_WS :
dkato 6:aa1fc6a5cc2a 2115 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF3_WS_SET;
dkato 6:aa1fc6a5cc2a 2116 break;
dkato 6:aa1fc6a5cc2a 2117
dkato 6:aa1fc6a5cc2a 2118 case SCUX_CLK_SSIF4_WS :
dkato 6:aa1fc6a5cc2a 2119 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF4_WS_SET;
dkato 6:aa1fc6a5cc2a 2120 break;
dkato 6:aa1fc6a5cc2a 2121
dkato 6:aa1fc6a5cc2a 2122 case SCUX_CLK_SSIF5_WS :
dkato 6:aa1fc6a5cc2a 2123 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF5_WS_SET;
dkato 6:aa1fc6a5cc2a 2124 break;
dkato 6:aa1fc6a5cc2a 2125
dkato 6:aa1fc6a5cc2a 2126 default :
dkato 6:aa1fc6a5cc2a 2127 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 2128 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 2129 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2130 break;
dkato 6:aa1fc6a5cc2a 2131 }
dkato 6:aa1fc6a5cc2a 2132 *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
dkato 6:aa1fc6a5cc2a 2133 }
dkato 6:aa1fc6a5cc2a 2134 }
dkato 6:aa1fc6a5cc2a 2135 else
dkato 6:aa1fc6a5cc2a 2136 {
dkato 6:aa1fc6a5cc2a 2137 /* do nothing for SSIF route */
dkato 6:aa1fc6a5cc2a 2138 }
dkato 6:aa1fc6a5cc2a 2139 }
dkato 6:aa1fc6a5cc2a 2140
dkato 6:aa1fc6a5cc2a 2141 return;
dkato 6:aa1fc6a5cc2a 2142 }
dkato 6:aa1fc6a5cc2a 2143
dkato 6:aa1fc6a5cc2a 2144 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2145 End of function SCUX_SetupSrcClk
dkato 6:aa1fc6a5cc2a 2146 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2147
dkato 6:aa1fc6a5cc2a 2148 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2149 * Function Name: SCUX_SetupFifo
dkato 6:aa1fc6a5cc2a 2150 * @brief SRC FIFO setup.
dkato 6:aa1fc6a5cc2a 2151 *
dkato 6:aa1fc6a5cc2a 2152 * Description:<br>
dkato 6:aa1fc6a5cc2a 2153 *
dkato 6:aa1fc6a5cc2a 2154 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 2155 * @retval None.
dkato 6:aa1fc6a5cc2a 2156 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2157
dkato 6:aa1fc6a5cc2a 2158 static void SCUX_SetupFifo(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2159 {
dkato 6:aa1fc6a5cc2a 2160 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2161 {
dkato 6:aa1fc6a5cc2a 2162 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 2163 }
dkato 6:aa1fc6a5cc2a 2164 else
dkato 6:aa1fc6a5cc2a 2165 {
dkato 6:aa1fc6a5cc2a 2166 /* set FFD register */
dkato 6:aa1fc6a5cc2a 2167 p_scux_info_ch->p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = p_scux_info_ch->src_cfg.use_ch;
dkato 6:aa1fc6a5cc2a 2168 p_scux_info_ch->p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = SCUX_FIFO_REQ_SIZE_128_32;
dkato 6:aa1fc6a5cc2a 2169
dkato 6:aa1fc6a5cc2a 2170 GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]);
dkato 6:aa1fc6a5cc2a 2171
dkato 6:aa1fc6a5cc2a 2172 /* set FFU register */
dkato 6:aa1fc6a5cc2a 2173 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 2174 {
dkato 6:aa1fc6a5cc2a 2175 p_scux_info_ch->p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = p_scux_info_ch->src_cfg.use_ch;
dkato 6:aa1fc6a5cc2a 2176 p_scux_info_ch->p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = SCUX_FIFO_REQ_SIZE_128_32;
dkato 6:aa1fc6a5cc2a 2177
dkato 6:aa1fc6a5cc2a 2178 GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]);
dkato 6:aa1fc6a5cc2a 2179 }
dkato 6:aa1fc6a5cc2a 2180
dkato 6:aa1fc6a5cc2a 2181 p_scux_info_ch->tx_fifo_total_size = 0;
dkato 6:aa1fc6a5cc2a 2182 p_scux_info_ch->rx_fifo_total_size = 0;
dkato 6:aa1fc6a5cc2a 2183 }
dkato 6:aa1fc6a5cc2a 2184
dkato 6:aa1fc6a5cc2a 2185 return;
dkato 6:aa1fc6a5cc2a 2186 }
dkato 6:aa1fc6a5cc2a 2187
dkato 6:aa1fc6a5cc2a 2188 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2189 End of function SCUX_SetupFifo
dkato 6:aa1fc6a5cc2a 2190 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2191
dkato 6:aa1fc6a5cc2a 2192 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2193 * Function Name: SCUX_SetupSrcFunction
dkato 6:aa1fc6a5cc2a 2194 * @brief SRC function setup.
dkato 6:aa1fc6a5cc2a 2195 *
dkato 6:aa1fc6a5cc2a 2196 * Description:<br>
dkato 6:aa1fc6a5cc2a 2197 *
dkato 6:aa1fc6a5cc2a 2198 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 2199 * @retval None.
dkato 6:aa1fc6a5cc2a 2200 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2201
dkato 6:aa1fc6a5cc2a 2202 static void SCUX_SetupSrcFunction(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2203 {
dkato 6:aa1fc6a5cc2a 2204 float32_t ifs_calc_value;
dkato 6:aa1fc6a5cc2a 2205 uint32_t ifs_value;
dkato 6:aa1fc6a5cc2a 2206 uint32_t sadir_value;
dkato 6:aa1fc6a5cc2a 2207 uint32_t srccr_value = 0;
dkato 6:aa1fc6a5cc2a 2208 uint32_t bfssr_value;
dkato 6:aa1fc6a5cc2a 2209
dkato 6:aa1fc6a5cc2a 2210 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2211 {
dkato 6:aa1fc6a5cc2a 2212 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 2213 }
dkato 6:aa1fc6a5cc2a 2214 else
dkato 6:aa1fc6a5cc2a 2215 {
dkato 6:aa1fc6a5cc2a 2216 if (false == p_scux_info_ch->src_cfg.src_enable)
dkato 6:aa1fc6a5cc2a 2217 {
dkato 6:aa1fc6a5cc2a 2218 /* set bypass mode */
dkato 6:aa1fc6a5cc2a 2219 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
dkato 6:aa1fc6a5cc2a 2220 {
dkato 6:aa1fc6a5cc2a 2221 p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 |= SRCBR_2SRC0_BYPASS_SET;
dkato 6:aa1fc6a5cc2a 2222 }
dkato 6:aa1fc6a5cc2a 2223 else
dkato 6:aa1fc6a5cc2a 2224 {
dkato 6:aa1fc6a5cc2a 2225 p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 |= SRCBR_2SRC0_BYPASS_SET;
dkato 6:aa1fc6a5cc2a 2226 }
dkato 6:aa1fc6a5cc2a 2227 }
dkato 6:aa1fc6a5cc2a 2228 else
dkato 6:aa1fc6a5cc2a 2229 {
dkato 6:aa1fc6a5cc2a 2230 /* calculate sampling rate convert rate parameter */
dkato 6:aa1fc6a5cc2a 2231 ifs_calc_value = ((float32_t)p_scux_info_ch->input_rate / (float32_t)p_scux_info_ch->output_rate);
dkato 6:aa1fc6a5cc2a 2232 /* ->IPA R2.4.1 float value is intentionall casted to uint32_t value, because it is resigter value. */
dkato 6:aa1fc6a5cc2a 2233 ifs_value = (uint32_t)(ifs_calc_value * (float32_t)SCUX_RATE_CONVERT_CALC_VALUE);
dkato 6:aa1fc6a5cc2a 2234 /* <-IPA R2.4.1 */
dkato 6:aa1fc6a5cc2a 2235 if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
dkato 6:aa1fc6a5cc2a 2236 {
dkato 6:aa1fc6a5cc2a 2237 sadir_value = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & SADIR_2SRC0_CHNUM_MASK) | SADIR_2SRC0_OTBL_SET_16BIT);
dkato 6:aa1fc6a5cc2a 2238 }
dkato 6:aa1fc6a5cc2a 2239 else
dkato 6:aa1fc6a5cc2a 2240 {
dkato 6:aa1fc6a5cc2a 2241 sadir_value = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & SADIR_2SRC0_CHNUM_MASK) | SADIR_2SRC0_OTBL_SET_24BIT);
dkato 6:aa1fc6a5cc2a 2242 }
dkato 6:aa1fc6a5cc2a 2243
dkato 6:aa1fc6a5cc2a 2244 /* setting of sync mode bit */
dkato 6:aa1fc6a5cc2a 2245 if (false != p_scux_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 2246 {
dkato 6:aa1fc6a5cc2a 2247 /* set sync mode */
dkato 6:aa1fc6a5cc2a 2248 srccr_value |= SRCCR_2SRC0_SRCMD_SET;
dkato 6:aa1fc6a5cc2a 2249 }
dkato 6:aa1fc6a5cc2a 2250 else
dkato 6:aa1fc6a5cc2a 2251 {
dkato 6:aa1fc6a5cc2a 2252 /* set async mode (bit clear) */
dkato 6:aa1fc6a5cc2a 2253 srccr_value &= ~SRCCR_2SRC0_SRCMD_SET;
dkato 6:aa1fc6a5cc2a 2254 }
dkato 6:aa1fc6a5cc2a 2255
dkato 6:aa1fc6a5cc2a 2256 /* setting of buffer for delay mode */
dkato 6:aa1fc6a5cc2a 2257 if (SCUX_DELAY_NORMAL == p_scux_info_ch->src_cfg.delay_mode)
dkato 6:aa1fc6a5cc2a 2258 {
dkato 6:aa1fc6a5cc2a 2259 /* delay normal setting (bit clear) */
dkato 6:aa1fc6a5cc2a 2260 srccr_value &= ~SRCCR_2SRC0_BUFMD_SET;
dkato 6:aa1fc6a5cc2a 2261 }
dkato 6:aa1fc6a5cc2a 2262 else
dkato 6:aa1fc6a5cc2a 2263 {
dkato 6:aa1fc6a5cc2a 2264 /* delay setting (bit set) */
dkato 6:aa1fc6a5cc2a 2265 srccr_value |= SRCCR_2SRC0_BUFMD_SET;
dkato 6:aa1fc6a5cc2a 2266 }
dkato 6:aa1fc6a5cc2a 2267
dkato 6:aa1fc6a5cc2a 2268 /* setting enable bit for wait mode */
dkato 6:aa1fc6a5cc2a 2269 if ((0U == p_scux_info_ch->src_cfg.wait_sample) || (false != p_scux_info_ch->cancel_operate_flag))
dkato 6:aa1fc6a5cc2a 2270 {
dkato 6:aa1fc6a5cc2a 2271 /* clear wait mode enable bit when wait value is 0 or cancel operatin on going */
dkato 6:aa1fc6a5cc2a 2272 srccr_value &= ~SRCCR_2SRC0_WATMD_SET;
dkato 6:aa1fc6a5cc2a 2273 }
dkato 6:aa1fc6a5cc2a 2274 else
dkato 6:aa1fc6a5cc2a 2275 {
dkato 6:aa1fc6a5cc2a 2276 /* set wait mode enable bit when wait value is other than 0 */
dkato 6:aa1fc6a5cc2a 2277 srccr_value |= SRCCR_2SRC0_WATMD_SET;
dkato 6:aa1fc6a5cc2a 2278 }
dkato 6:aa1fc6a5cc2a 2279
dkato 6:aa1fc6a5cc2a 2280 /* setting buffer value for delay mode */
dkato 6:aa1fc6a5cc2a 2281 if (SCUX_DELAY_NORMAL == p_scux_info_ch->src_cfg.delay_mode)
dkato 6:aa1fc6a5cc2a 2282 {
dkato 6:aa1fc6a5cc2a 2283 /* set 0 to BFSSR register on delay normal */
dkato 6:aa1fc6a5cc2a 2284 bfssr_value = 0;
dkato 6:aa1fc6a5cc2a 2285 }
dkato 6:aa1fc6a5cc2a 2286 else if (SCUX_DELAY_LOW_DELAY1 == p_scux_info_ch->src_cfg.delay_mode)
dkato 6:aa1fc6a5cc2a 2287 {
dkato 6:aa1fc6a5cc2a 2288 /* set delay mode 1 setting to BFSSR register on delay mode1 */
dkato 6:aa1fc6a5cc2a 2289 bfssr_value = ((BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE1 & BFSSR_2SRC0_BUFDATA_MASK) |
dkato 6:aa1fc6a5cc2a 2290 (BFSSR_2SRC0_BUFIN_SET_DELAY_MODE & BFSSR_2SRC0_BUFIN_MASK));
dkato 6:aa1fc6a5cc2a 2291 }
dkato 6:aa1fc6a5cc2a 2292 else
dkato 6:aa1fc6a5cc2a 2293 {
dkato 6:aa1fc6a5cc2a 2294 /* set delay mode 2 setting to BFSSR register on delay mode2 */
dkato 6:aa1fc6a5cc2a 2295 bfssr_value = ((BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE2 & BFSSR_2SRC0_BUFDATA_MASK) |
dkato 6:aa1fc6a5cc2a 2296 (BFSSR_2SRC0_BUFIN_SET_DELAY_MODE & BFSSR_2SRC0_BUFIN_MASK));
dkato 6:aa1fc6a5cc2a 2297 }
dkato 6:aa1fc6a5cc2a 2298
dkato 6:aa1fc6a5cc2a 2299 /* set register */
dkato 6:aa1fc6a5cc2a 2300 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
dkato 6:aa1fc6a5cc2a 2301 {
dkato 6:aa1fc6a5cc2a 2302 p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 &= ~SRCBR_2SRC0_BYPASS_SET;
dkato 6:aa1fc6a5cc2a 2303 p_scux_info_ch->p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = sadir_value;
dkato 6:aa1fc6a5cc2a 2304 p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 |= IFSCR_2SRC0_INTIFSEN_SET;
dkato 6:aa1fc6a5cc2a 2305 p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = ifs_value;
dkato 6:aa1fc6a5cc2a 2306 p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = ((ifs_value * (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage)
dkato 6:aa1fc6a5cc2a 2307 / SCUX_CALC_MINFS_VALUE);
dkato 6:aa1fc6a5cc2a 2308 p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_BASE_VALUE | srccr_value);
dkato 6:aa1fc6a5cc2a 2309 p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = bfssr_value;
dkato 6:aa1fc6a5cc2a 2310 if (false != p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 2311 {
dkato 6:aa1fc6a5cc2a 2312 /* set 0 to register compulsorily when cancel operation on going */
dkato 6:aa1fc6a5cc2a 2313 p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = 0U;
dkato 6:aa1fc6a5cc2a 2314 }
dkato 6:aa1fc6a5cc2a 2315 else
dkato 6:aa1fc6a5cc2a 2316 {
dkato 6:aa1fc6a5cc2a 2317 /* set wait value to register when cancel operation on going */
dkato 6:aa1fc6a5cc2a 2318 p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = (p_scux_info_ch->src_cfg.wait_sample & WATSR_2SRC0_WTIME_MASK);
dkato 6:aa1fc6a5cc2a 2319 }
dkato 6:aa1fc6a5cc2a 2320 }
dkato 6:aa1fc6a5cc2a 2321 else
dkato 6:aa1fc6a5cc2a 2322 {
dkato 6:aa1fc6a5cc2a 2323 p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 &= ~SRCBR_2SRC0_BYPASS_SET;
dkato 6:aa1fc6a5cc2a 2324 p_scux_info_ch->p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = sadir_value;
dkato 6:aa1fc6a5cc2a 2325 p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 |= IFSCR_2SRC0_INTIFSEN_SET;
dkato 6:aa1fc6a5cc2a 2326 p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = ifs_value;
dkato 6:aa1fc6a5cc2a 2327 p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = ((ifs_value * (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage)
dkato 6:aa1fc6a5cc2a 2328 / SCUX_CALC_MINFS_VALUE);
dkato 6:aa1fc6a5cc2a 2329 p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_BASE_VALUE | srccr_value);
dkato 6:aa1fc6a5cc2a 2330 p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = bfssr_value;
dkato 6:aa1fc6a5cc2a 2331 if (false != p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 2332 {
dkato 6:aa1fc6a5cc2a 2333 /* set 0 to register compulsorily when cancel operation on going */
dkato 6:aa1fc6a5cc2a 2334 p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = 0U;
dkato 6:aa1fc6a5cc2a 2335 }
dkato 6:aa1fc6a5cc2a 2336 else
dkato 6:aa1fc6a5cc2a 2337 {
dkato 6:aa1fc6a5cc2a 2338 /* set wait value to register when cancel operation on going */
dkato 6:aa1fc6a5cc2a 2339 p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = (p_scux_info_ch->src_cfg.wait_sample & WATSR_2SRC0_WTIME_MASK);
dkato 6:aa1fc6a5cc2a 2340 }
dkato 6:aa1fc6a5cc2a 2341 }
dkato 6:aa1fc6a5cc2a 2342 }
dkato 6:aa1fc6a5cc2a 2343 }
dkato 6:aa1fc6a5cc2a 2344
dkato 6:aa1fc6a5cc2a 2345 return;
dkato 6:aa1fc6a5cc2a 2346 }
dkato 6:aa1fc6a5cc2a 2347
dkato 6:aa1fc6a5cc2a 2348 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2349 End of function SCUX_SetupSrcFunction
dkato 6:aa1fc6a5cc2a 2350 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2351
dkato 6:aa1fc6a5cc2a 2352 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2353 * Function Name: SCUX_SetupDvu
dkato 6:aa1fc6a5cc2a 2354 * @brief DVU module setup.
dkato 6:aa1fc6a5cc2a 2355 *
dkato 6:aa1fc6a5cc2a 2356 * Description:<br>
dkato 6:aa1fc6a5cc2a 2357 *
dkato 6:aa1fc6a5cc2a 2358 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 2359 * @retval None.
dkato 6:aa1fc6a5cc2a 2360 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2361
dkato 6:aa1fc6a5cc2a 2362 void SCUX_SetupDvu(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2363 {
dkato 6:aa1fc6a5cc2a 2364 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2365 {
dkato 6:aa1fc6a5cc2a 2366 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 2367 }
dkato 6:aa1fc6a5cc2a 2368 else
dkato 6:aa1fc6a5cc2a 2369 {
dkato 6:aa1fc6a5cc2a 2370 if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
dkato 6:aa1fc6a5cc2a 2371 {
dkato 6:aa1fc6a5cc2a 2372 p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & VADIR_DVU0_CHNUM_MASK) |
dkato 6:aa1fc6a5cc2a 2373 VADIR_DVU0_OTBL_SET_16BIT);
dkato 6:aa1fc6a5cc2a 2374 }
dkato 6:aa1fc6a5cc2a 2375 else
dkato 6:aa1fc6a5cc2a 2376 {
dkato 6:aa1fc6a5cc2a 2377 p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & VADIR_DVU0_CHNUM_MASK) |
dkato 6:aa1fc6a5cc2a 2378 VADIR_DVU0_OTBL_SET_24BIT);
dkato 6:aa1fc6a5cc2a 2379 }
dkato 6:aa1fc6a5cc2a 2380
dkato 6:aa1fc6a5cc2a 2381 if (false == p_scux_info_ch->dvu_cfg.dvu_enable)
dkato 6:aa1fc6a5cc2a 2382 {
dkato 6:aa1fc6a5cc2a 2383 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 |= DVUBR_DVU0_BYPASS_SET;
dkato 6:aa1fc6a5cc2a 2384 }
dkato 6:aa1fc6a5cc2a 2385 else
dkato 6:aa1fc6a5cc2a 2386 {
dkato 6:aa1fc6a5cc2a 2387 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 &= ~DVUBR_DVU0_BYPASS_SET;
dkato 6:aa1fc6a5cc2a 2388 }
dkato 6:aa1fc6a5cc2a 2389 }
dkato 6:aa1fc6a5cc2a 2390
dkato 6:aa1fc6a5cc2a 2391 return;
dkato 6:aa1fc6a5cc2a 2392 }
dkato 6:aa1fc6a5cc2a 2393
dkato 6:aa1fc6a5cc2a 2394 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2395 End of function SCUX_SetupDvu
dkato 6:aa1fc6a5cc2a 2396 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2397
dkato 6:aa1fc6a5cc2a 2398 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2399 * Function Name: SCUX_SetupDvuVolume
dkato 6:aa1fc6a5cc2a 2400 * @brief DVU volume setup.
dkato 6:aa1fc6a5cc2a 2401 *
dkato 6:aa1fc6a5cc2a 2402 * Description:<br>
dkato 6:aa1fc6a5cc2a 2403 *
dkato 6:aa1fc6a5cc2a 2404 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 2405 * @retval None.
dkato 6:aa1fc6a5cc2a 2406 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2407
dkato 6:aa1fc6a5cc2a 2408 static void SCUX_SetupDvuVolume(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2409 {
dkato 6:aa1fc6a5cc2a 2410 int_t audio_ch;
dkato 6:aa1fc6a5cc2a 2411 uint32_t vrctr_value = 0;
dkato 6:aa1fc6a5cc2a 2412
dkato 6:aa1fc6a5cc2a 2413 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2414 {
dkato 6:aa1fc6a5cc2a 2415 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 2416 }
dkato 6:aa1fc6a5cc2a 2417 else
dkato 6:aa1fc6a5cc2a 2418 {
dkato 6:aa1fc6a5cc2a 2419 /* init DVU module */
dkato 6:aa1fc6a5cc2a 2420 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 &= ~DVUIR_DVU0_INIT_SET;
dkato 6:aa1fc6a5cc2a 2421 if (false != p_scux_info_ch->dvu_cfg.dvu_enable)
dkato 6:aa1fc6a5cc2a 2422 {
dkato 6:aa1fc6a5cc2a 2423 /* set digital volume */
dkato 6:aa1fc6a5cc2a 2424 SCUX_SetDigiVolRegister(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 2425
dkato 6:aa1fc6a5cc2a 2426 /* dummy setting to volume ramp */
dkato 6:aa1fc6a5cc2a 2427 for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
dkato 6:aa1fc6a5cc2a 2428 {
dkato 6:aa1fc6a5cc2a 2429 vrctr_value |= (VRCTR_DVU0_VREN_SET << audio_ch);
dkato 6:aa1fc6a5cc2a 2430 }
dkato 6:aa1fc6a5cc2a 2431
dkato 6:aa1fc6a5cc2a 2432 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_VRMD_SET;
dkato 6:aa1fc6a5cc2a 2433 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = vrctr_value;
dkato 6:aa1fc6a5cc2a 2434
dkato 6:aa1fc6a5cc2a 2435 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = 0;
dkato 6:aa1fc6a5cc2a 2436 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = 0;
dkato 6:aa1fc6a5cc2a 2437 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = 0;
dkato 6:aa1fc6a5cc2a 2438
dkato 6:aa1fc6a5cc2a 2439 /* set zerocross mute */
dkato 6:aa1fc6a5cc2a 2440 SCUX_SetZerocrossMuteRegister(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 2441
dkato 6:aa1fc6a5cc2a 2442 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
dkato 6:aa1fc6a5cc2a 2443 GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_DVI]);
dkato 6:aa1fc6a5cc2a 2444 }
dkato 6:aa1fc6a5cc2a 2445 }
dkato 6:aa1fc6a5cc2a 2446
dkato 6:aa1fc6a5cc2a 2447 return;
dkato 6:aa1fc6a5cc2a 2448 }
dkato 6:aa1fc6a5cc2a 2449
dkato 6:aa1fc6a5cc2a 2450 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2451 End of function SCUX_SetupDvu
dkato 6:aa1fc6a5cc2a 2452 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2453
dkato 6:aa1fc6a5cc2a 2454 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2455 * Function Name: SCUX_SetupMix
dkato 6:aa1fc6a5cc2a 2456 * @brief MIX module setup.
dkato 6:aa1fc6a5cc2a 2457 *
dkato 6:aa1fc6a5cc2a 2458 * Description:<br>
dkato 6:aa1fc6a5cc2a 2459 *
dkato 6:aa1fc6a5cc2a 2460 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 2461 * @retval None.
dkato 6:aa1fc6a5cc2a 2462 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2463
dkato 6:aa1fc6a5cc2a 2464 static void SCUX_SetupMix(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2465 {
dkato 6:aa1fc6a5cc2a 2466 int_t scux_ch;
dkato 6:aa1fc6a5cc2a 2467 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
dkato 6:aa1fc6a5cc2a 2468
dkato 6:aa1fc6a5cc2a 2469 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
dkato 6:aa1fc6a5cc2a 2470 {
dkato 6:aa1fc6a5cc2a 2471 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 2472 }
dkato 6:aa1fc6a5cc2a 2473 else
dkato 6:aa1fc6a5cc2a 2474 {
dkato 6:aa1fc6a5cc2a 2475 /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */
dkato 6:aa1fc6a5cc2a 2476 if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag))
dkato 6:aa1fc6a5cc2a 2477 {
dkato 6:aa1fc6a5cc2a 2478 *(p_scux_info_ch->p_scux_reg->madir_mix0_0) = ((uint32_t)p_scux_info_ch->src_cfg.use_ch & MADIR_MIX0_CHNUM_MASK);
dkato 6:aa1fc6a5cc2a 2479 *(p_scux_info_ch->p_scux_reg->mixir_mix0_0) &= ~MIXIR_MIX0_INIT_SET;
dkato 6:aa1fc6a5cc2a 2480 }
dkato 6:aa1fc6a5cc2a 2481
dkato 6:aa1fc6a5cc2a 2482 for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++)
dkato 6:aa1fc6a5cc2a 2483 {
dkato 6:aa1fc6a5cc2a 2484 /* register set on the channel itself which sets up or channel which has already MIX operated */
dkato 6:aa1fc6a5cc2a 2485 if ((scux_ch == p_scux_info_ch->channel) ||
dkato 6:aa1fc6a5cc2a 2486 (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch))))
dkato 6:aa1fc6a5cc2a 2487 {
dkato 6:aa1fc6a5cc2a 2488 SCUX_SetMixVolRegister(scux_ch);
dkato 6:aa1fc6a5cc2a 2489 }
dkato 6:aa1fc6a5cc2a 2490 }
dkato 6:aa1fc6a5cc2a 2491
dkato 6:aa1fc6a5cc2a 2492 /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */
dkato 6:aa1fc6a5cc2a 2493 if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag))
dkato 6:aa1fc6a5cc2a 2494 {
dkato 6:aa1fc6a5cc2a 2495 *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET;
dkato 6:aa1fc6a5cc2a 2496
dkato 6:aa1fc6a5cc2a 2497 if (false != p_info_drv->shared_info.mixmode_ramp)
dkato 6:aa1fc6a5cc2a 2498 {
dkato 6:aa1fc6a5cc2a 2499 /* set ramp mode */
dkato 6:aa1fc6a5cc2a 2500 *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) |= MIXMR_MIX0_MIXMODE_SET;
dkato 6:aa1fc6a5cc2a 2501 *(p_scux_info_ch->p_scux_reg->mvpdr_mix0_0) = (uint32_t)((((uint32_t)p_info_drv->shared_info.up_period << MVPDR_MIX0_MXPDUP_SHIFT) & MVPDR_MIX0_MXPDUP_MASK) |
dkato 6:aa1fc6a5cc2a 2502 (((uint32_t)p_info_drv->shared_info.down_period << MVPDR_MIX0_MXPDDW_SHIFT) & MVPDR_MIX0_MXPDDW_MASK));
dkato 6:aa1fc6a5cc2a 2503 }
dkato 6:aa1fc6a5cc2a 2504 else
dkato 6:aa1fc6a5cc2a 2505 {
dkato 6:aa1fc6a5cc2a 2506 /* set step mode */
dkato 6:aa1fc6a5cc2a 2507 *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) &= ~MIXMR_MIX0_MIXMODE_SET;
dkato 6:aa1fc6a5cc2a 2508 }
dkato 6:aa1fc6a5cc2a 2509
dkato 6:aa1fc6a5cc2a 2510 *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) |= MDBER_MIX0_MIXDBEN_SET;
dkato 6:aa1fc6a5cc2a 2511 }
dkato 6:aa1fc6a5cc2a 2512 /* set bit SCUX channel which useing MIX */
dkato 6:aa1fc6a5cc2a 2513 p_info_drv->shared_info.mix_run_ch |= (1U << p_scux_info_ch->channel);
dkato 6:aa1fc6a5cc2a 2514 }
dkato 6:aa1fc6a5cc2a 2515
dkato 6:aa1fc6a5cc2a 2516 return;
dkato 6:aa1fc6a5cc2a 2517 }
dkato 6:aa1fc6a5cc2a 2518
dkato 6:aa1fc6a5cc2a 2519 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2520 End of function SCUX_SetupMix
dkato 6:aa1fc6a5cc2a 2521 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2522
dkato 6:aa1fc6a5cc2a 2523 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2524 * Function Name: SCUX_SetupSsif
dkato 6:aa1fc6a5cc2a 2525 * @brief SSIF module setup.
dkato 6:aa1fc6a5cc2a 2526 *
dkato 6:aa1fc6a5cc2a 2527 * Description:<br>
dkato 6:aa1fc6a5cc2a 2528 *
dkato 6:aa1fc6a5cc2a 2529 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 2530 * @retval None.
dkato 6:aa1fc6a5cc2a 2531 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2532
dkato 6:aa1fc6a5cc2a 2533 void SCUX_SetupSsif(const scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2534 {
dkato 6:aa1fc6a5cc2a 2535 scux_ssif_info_t *p_set_ssif;
dkato 6:aa1fc6a5cc2a 2536 volatile uint8_t dummy_buf;
dkato 6:aa1fc6a5cc2a 2537 uint32_t ssif_arrange_num;
dkato 6:aa1fc6a5cc2a 2538 uint32_t ssicr_value = 0;
dkato 6:aa1fc6a5cc2a 2539 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
dkato 6:aa1fc6a5cc2a 2540 int_t was_masked;
dkato 6:aa1fc6a5cc2a 2541
dkato 6:aa1fc6a5cc2a 2542 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
dkato 6:aa1fc6a5cc2a 2543 {
dkato 6:aa1fc6a5cc2a 2544 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 2545 }
dkato 6:aa1fc6a5cc2a 2546 else
dkato 6:aa1fc6a5cc2a 2547 {
dkato 6:aa1fc6a5cc2a 2548 for (ssif_arrange_num = 0; ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT; ssif_arrange_num++)
dkato 6:aa1fc6a5cc2a 2549 {
dkato 6:aa1fc6a5cc2a 2550 switch (ssif_arrange_num)
dkato 6:aa1fc6a5cc2a 2551 {
dkato 6:aa1fc6a5cc2a 2552 case SCUX_SSIF_CH_ARRANGEMENT1:
dkato 6:aa1fc6a5cc2a 2553 p_set_ssif = p_scux_info_ch->p_ssif_info1;
dkato 6:aa1fc6a5cc2a 2554 break;
dkato 6:aa1fc6a5cc2a 2555
dkato 6:aa1fc6a5cc2a 2556 case SCUX_SSIF_CH_ARRANGEMENT2:
dkato 6:aa1fc6a5cc2a 2557 p_set_ssif = p_scux_info_ch->p_ssif_info2;
dkato 6:aa1fc6a5cc2a 2558 break;
dkato 6:aa1fc6a5cc2a 2559
dkato 6:aa1fc6a5cc2a 2560 case SCUX_SSIF_CH_ARRANGEMENT3:
dkato 6:aa1fc6a5cc2a 2561 p_set_ssif = p_scux_info_ch->p_ssif_info3;
dkato 6:aa1fc6a5cc2a 2562 break;
dkato 6:aa1fc6a5cc2a 2563
dkato 6:aa1fc6a5cc2a 2564 default :
dkato 6:aa1fc6a5cc2a 2565 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 2566 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 2567 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2568 break;
dkato 6:aa1fc6a5cc2a 2569 }
dkato 6:aa1fc6a5cc2a 2570
dkato 6:aa1fc6a5cc2a 2571 /* check wherher SSIF pointer 1, 2, 3 is NULL */
dkato 6:aa1fc6a5cc2a 2572 if (NULL != p_set_ssif)
dkato 6:aa1fc6a5cc2a 2573 {
dkato 6:aa1fc6a5cc2a 2574 /* check SSIF is used on other MIX SCUX channel */
dkato 6:aa1fc6a5cc2a 2575 if (0U == ((uint32_t)p_set_ssif->scux_channel & ~(1U << p_scux_info_ch->channel)))
dkato 6:aa1fc6a5cc2a 2576 {
dkato 6:aa1fc6a5cc2a 2577 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 2578 {
dkato 6:aa1fc6a5cc2a 2579 p_info_drv->shared_info.mix_ssif_ch |= (1U << p_set_ssif->ssif_cfg.ssif_ch_num);
dkato 6:aa1fc6a5cc2a 2580 }
dkato 6:aa1fc6a5cc2a 2581
dkato 6:aa1fc6a5cc2a 2582 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 2583 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 2584 #else
dkato 6:aa1fc6a5cc2a 2585 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 2586 #endif
dkato 6:aa1fc6a5cc2a 2587
dkato 6:aa1fc6a5cc2a 2588 /* input clock */
dkato 6:aa1fc6a5cc2a 2589 CPGSTBCR11 &= (uint8_t)~((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
dkato 6:aa1fc6a5cc2a 2590 dummy_buf = CPGSTBCR11;
dkato 6:aa1fc6a5cc2a 2591
dkato 6:aa1fc6a5cc2a 2592 /* SSIF rest */
dkato 6:aa1fc6a5cc2a 2593 CPGSWRSTCR1 |= (uint8_t)gb_cpg_scux_ssif_swrst_bit[p_set_ssif->ssif_cfg.ssif_ch_num];
dkato 6:aa1fc6a5cc2a 2594 dummy_buf = CPGSWRSTCR1;
dkato 6:aa1fc6a5cc2a 2595
dkato 6:aa1fc6a5cc2a 2596 CPGSWRSTCR1 &= (uint8_t)~((uint8_t)gb_cpg_scux_ssif_swrst_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
dkato 6:aa1fc6a5cc2a 2597 dummy_buf = CPGSWRSTCR1;
dkato 6:aa1fc6a5cc2a 2598
dkato 6:aa1fc6a5cc2a 2599 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 2600 {
dkato 6:aa1fc6a5cc2a 2601 __enable_irq();
dkato 6:aa1fc6a5cc2a 2602 }
dkato 6:aa1fc6a5cc2a 2603
dkato 6:aa1fc6a5cc2a 2604 SCUX_SetupSsifGpio(p_set_ssif->ssif_cfg.ssif_ch_num);
dkato 6:aa1fc6a5cc2a 2605
dkato 6:aa1fc6a5cc2a 2606 /* if mode is master mode, WS continue mode is enabled */
dkato 6:aa1fc6a5cc2a 2607 if (false != p_set_ssif->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 2608 {
dkato 6:aa1fc6a5cc2a 2609 p_set_ssif->p_scux_ssif_reg->SSITDMR |= SCUX_SSITDMR_CONT_SET;
dkato 6:aa1fc6a5cc2a 2610 }
dkato 6:aa1fc6a5cc2a 2611 else
dkato 6:aa1fc6a5cc2a 2612 {
dkato 6:aa1fc6a5cc2a 2613 p_set_ssif->p_scux_ssif_reg->SSITDMR &= ~SCUX_SSITDMR_CONT_SET;
dkato 6:aa1fc6a5cc2a 2614 }
dkato 6:aa1fc6a5cc2a 2615
dkato 6:aa1fc6a5cc2a 2616 /* TDM mode is set according to use_tdm */
dkato 6:aa1fc6a5cc2a 2617 if (false != p_set_ssif->ssif_cfg.use_tdm)
dkato 6:aa1fc6a5cc2a 2618 {
dkato 6:aa1fc6a5cc2a 2619 p_set_ssif->p_scux_ssif_reg->SSITDMR |= SCUX_SSITDMR_TDM_SET;
dkato 6:aa1fc6a5cc2a 2620 }
dkato 6:aa1fc6a5cc2a 2621 else
dkato 6:aa1fc6a5cc2a 2622 {
dkato 6:aa1fc6a5cc2a 2623 p_set_ssif->p_scux_ssif_reg->SSITDMR &= ~SCUX_SSITDMR_TDM_SET;
dkato 6:aa1fc6a5cc2a 2624 }
dkato 6:aa1fc6a5cc2a 2625
dkato 6:aa1fc6a5cc2a 2626 /* over sample clock is set according to select_audio_clk */
dkato 6:aa1fc6a5cc2a 2627 /* if select_audio_clk is 0, set AUDIO_X1 */
dkato 6:aa1fc6a5cc2a 2628 /* if select_audio_clk is 0, set AUDIO_CLK */
dkato 6:aa1fc6a5cc2a 2629 if (false != p_set_ssif->ssif_cfg.select_audio_clk)
dkato 6:aa1fc6a5cc2a 2630 {
dkato 6:aa1fc6a5cc2a 2631 ssicr_value |= SCUX_SSICR_CKS_SET;
dkato 6:aa1fc6a5cc2a 2632 }
dkato 6:aa1fc6a5cc2a 2633 else
dkato 6:aa1fc6a5cc2a 2634 {
dkato 6:aa1fc6a5cc2a 2635 ssicr_value &= ~SCUX_SSICR_CKS_SET;
dkato 6:aa1fc6a5cc2a 2636 }
dkato 6:aa1fc6a5cc2a 2637
dkato 6:aa1fc6a5cc2a 2638 if (NULL == p_scux_info_ch->p_ssif_info2)
dkato 6:aa1fc6a5cc2a 2639 {
dkato 6:aa1fc6a5cc2a 2640 /* in case single channel, SSIF channel is set as use_ch kinds */
dkato 6:aa1fc6a5cc2a 2641 switch (p_scux_info_ch->src_cfg.use_ch)
dkato 6:aa1fc6a5cc2a 2642 {
dkato 6:aa1fc6a5cc2a 2643 case SCUX_USE_CH_1:
dkato 6:aa1fc6a5cc2a 2644 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2645 break;
dkato 6:aa1fc6a5cc2a 2646
dkato 6:aa1fc6a5cc2a 2647 case SCUX_USE_CH_2:
dkato 6:aa1fc6a5cc2a 2648 /* if TDM mode is used on audio 2ch , error occured in SCUX_CheckSrcParam */
dkato 6:aa1fc6a5cc2a 2649 ssicr_value |= SCUX_SSICR_CHNL_SET_1CH;
dkato 6:aa1fc6a5cc2a 2650 break;
dkato 6:aa1fc6a5cc2a 2651
dkato 6:aa1fc6a5cc2a 2652 case SCUX_USE_CH_4:
dkato 6:aa1fc6a5cc2a 2653 ssicr_value |= SCUX_SSICR_CHNL_SET_2CH;
dkato 6:aa1fc6a5cc2a 2654 break;
dkato 6:aa1fc6a5cc2a 2655
dkato 6:aa1fc6a5cc2a 2656 case SCUX_USE_CH_6:
dkato 6:aa1fc6a5cc2a 2657 ssicr_value |= SCUX_SSICR_CHNL_SET_3CH;
dkato 6:aa1fc6a5cc2a 2658 break;
dkato 6:aa1fc6a5cc2a 2659
dkato 6:aa1fc6a5cc2a 2660 case SCUX_USE_CH_8:
dkato 6:aa1fc6a5cc2a 2661 ssicr_value |= SCUX_SSICR_CHNL_SET_4CH;
dkato 6:aa1fc6a5cc2a 2662 break;
dkato 6:aa1fc6a5cc2a 2663
dkato 6:aa1fc6a5cc2a 2664 default :
dkato 6:aa1fc6a5cc2a 2665 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 2666 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 2667 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2668 break;
dkato 6:aa1fc6a5cc2a 2669 }
dkato 6:aa1fc6a5cc2a 2670 }
dkato 6:aa1fc6a5cc2a 2671 else
dkato 6:aa1fc6a5cc2a 2672 {
dkato 6:aa1fc6a5cc2a 2673 /* in case multi channel, SSIF channel is set 1ch compulsorily */
dkato 6:aa1fc6a5cc2a 2674 ssicr_value |= SCUX_SSICR_CHNL_SET_1CH;
dkato 6:aa1fc6a5cc2a 2675 }
dkato 6:aa1fc6a5cc2a 2676
dkato 6:aa1fc6a5cc2a 2677 /* set data word */
dkato 6:aa1fc6a5cc2a 2678 if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
dkato 6:aa1fc6a5cc2a 2679 {
dkato 6:aa1fc6a5cc2a 2680 ssicr_value |= SCUX_SSICR_DWL_16BIT_SET;
dkato 6:aa1fc6a5cc2a 2681 }
dkato 6:aa1fc6a5cc2a 2682 else
dkato 6:aa1fc6a5cc2a 2683 {
dkato 6:aa1fc6a5cc2a 2684 ssicr_value |= SCUX_SSICR_DWL_24BIT_SET;
dkato 6:aa1fc6a5cc2a 2685 }
dkato 6:aa1fc6a5cc2a 2686
dkato 6:aa1fc6a5cc2a 2687 ssicr_value |= ((uint32_t)p_set_ssif->ssif_cfg.system_word << SCUX_SSICR_SWL_SHIFT);
dkato 6:aa1fc6a5cc2a 2688
dkato 6:aa1fc6a5cc2a 2689
dkato 6:aa1fc6a5cc2a 2690 if (SCUX_PIN_MODE_INDEPEND == p_set_ssif->pin_mode)
dkato 6:aa1fc6a5cc2a 2691 {
dkato 6:aa1fc6a5cc2a 2692 /* in case pin synchronization is slave, SSIF mode is set mode following mode_master */
dkato 6:aa1fc6a5cc2a 2693 if (false != p_set_ssif->ssif_cfg.mode_master)
dkato 6:aa1fc6a5cc2a 2694 {
dkato 6:aa1fc6a5cc2a 2695 ssicr_value |= (SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET);
dkato 6:aa1fc6a5cc2a 2696 }
dkato 6:aa1fc6a5cc2a 2697 else
dkato 6:aa1fc6a5cc2a 2698 {
dkato 6:aa1fc6a5cc2a 2699 ssicr_value &= ~(SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET);
dkato 6:aa1fc6a5cc2a 2700 }
dkato 6:aa1fc6a5cc2a 2701 }
dkato 6:aa1fc6a5cc2a 2702 else
dkato 6:aa1fc6a5cc2a 2703 {
dkato 6:aa1fc6a5cc2a 2704 /* in case pin synchronization is slave, SSIF mode is set slave mode compulsorily */
dkato 6:aa1fc6a5cc2a 2705 ssicr_value &= ~(SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET);
dkato 6:aa1fc6a5cc2a 2706 }
dkato 6:aa1fc6a5cc2a 2707
dkato 6:aa1fc6a5cc2a 2708 /* set serial bit clock polarity */
dkato 6:aa1fc6a5cc2a 2709 if (false != p_set_ssif->ssif_cfg.sck_polarity_rise)
dkato 6:aa1fc6a5cc2a 2710 {
dkato 6:aa1fc6a5cc2a 2711 ssicr_value |= SCUX_SSICR_SCKP_SET;
dkato 6:aa1fc6a5cc2a 2712 }
dkato 6:aa1fc6a5cc2a 2713 else
dkato 6:aa1fc6a5cc2a 2714 {
dkato 6:aa1fc6a5cc2a 2715 ssicr_value &= ~SCUX_SSICR_SCKP_SET;
dkato 6:aa1fc6a5cc2a 2716 }
dkato 6:aa1fc6a5cc2a 2717
dkato 6:aa1fc6a5cc2a 2718 /* set WS signal polarity */
dkato 6:aa1fc6a5cc2a 2719 if (false != p_set_ssif->ssif_cfg.ws_polarity_high)
dkato 6:aa1fc6a5cc2a 2720 {
dkato 6:aa1fc6a5cc2a 2721 ssicr_value |= SCUX_SSICR_SWSP_SET;
dkato 6:aa1fc6a5cc2a 2722 }
dkato 6:aa1fc6a5cc2a 2723 else
dkato 6:aa1fc6a5cc2a 2724 {
dkato 6:aa1fc6a5cc2a 2725 ssicr_value &= ~SCUX_SSICR_SWSP_SET;
dkato 6:aa1fc6a5cc2a 2726 }
dkato 6:aa1fc6a5cc2a 2727
dkato 6:aa1fc6a5cc2a 2728 /* set serial padding polarity */
dkato 6:aa1fc6a5cc2a 2729 if (false != p_set_ssif->ssif_cfg.padding_high)
dkato 6:aa1fc6a5cc2a 2730 {
dkato 6:aa1fc6a5cc2a 2731 ssicr_value |= SCUX_SSICR_SPDP_SET;
dkato 6:aa1fc6a5cc2a 2732 }
dkato 6:aa1fc6a5cc2a 2733 else
dkato 6:aa1fc6a5cc2a 2734 {
dkato 6:aa1fc6a5cc2a 2735 ssicr_value &= ~SCUX_SSICR_SPDP_SET;
dkato 6:aa1fc6a5cc2a 2736 }
dkato 6:aa1fc6a5cc2a 2737
dkato 6:aa1fc6a5cc2a 2738 /* set serial data align polarity */
dkato 6:aa1fc6a5cc2a 2739 if (false != p_set_ssif->ssif_cfg.serial_data_align)
dkato 6:aa1fc6a5cc2a 2740 {
dkato 6:aa1fc6a5cc2a 2741 ssicr_value &= ~SCUX_SSICR_SDTA_SET;
dkato 6:aa1fc6a5cc2a 2742 }
dkato 6:aa1fc6a5cc2a 2743 else
dkato 6:aa1fc6a5cc2a 2744 {
dkato 6:aa1fc6a5cc2a 2745 ssicr_value |= SCUX_SSICR_SDTA_SET;
dkato 6:aa1fc6a5cc2a 2746 }
dkato 6:aa1fc6a5cc2a 2747
dkato 6:aa1fc6a5cc2a 2748 /* set WS delay setting */
dkato 6:aa1fc6a5cc2a 2749 if (false == p_set_ssif->ssif_cfg.ws_delay)
dkato 6:aa1fc6a5cc2a 2750 {
dkato 6:aa1fc6a5cc2a 2751 ssicr_value |= SCUX_SSICR_DEL_SET;
dkato 6:aa1fc6a5cc2a 2752 }
dkato 6:aa1fc6a5cc2a 2753 else
dkato 6:aa1fc6a5cc2a 2754 {
dkato 6:aa1fc6a5cc2a 2755 ssicr_value &= ~SCUX_SSICR_DEL_SET;
dkato 6:aa1fc6a5cc2a 2756 }
dkato 6:aa1fc6a5cc2a 2757
dkato 6:aa1fc6a5cc2a 2758 /* set SSIF devide rate */
dkato 6:aa1fc6a5cc2a 2759 ssicr_value |= ((uint32_t)p_set_ssif->clk_div << SCUX_SSICR_CKDV_SHIFT);
dkato 6:aa1fc6a5cc2a 2760
dkato 6:aa1fc6a5cc2a 2761 p_set_ssif->p_scux_ssif_reg->SSICR = ssicr_value;
dkato 6:aa1fc6a5cc2a 2762
dkato 6:aa1fc6a5cc2a 2763 /* set noise cancel setting */
dkato 6:aa1fc6a5cc2a 2764 if ((false == p_set_ssif->ssif_cfg.mode_master) && (false != p_set_ssif->ssif_cfg.use_noise_cancel))
dkato 6:aa1fc6a5cc2a 2765 {
dkato 6:aa1fc6a5cc2a 2766 GPIO.SNCR |= (1U << gb_cpg_scux_ssif_sncr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
dkato 6:aa1fc6a5cc2a 2767 }
dkato 6:aa1fc6a5cc2a 2768 else
dkato 6:aa1fc6a5cc2a 2769 {
dkato 6:aa1fc6a5cc2a 2770 GPIO.SNCR &= ~(1U << gb_cpg_scux_ssif_sncr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
dkato 6:aa1fc6a5cc2a 2771 }
dkato 6:aa1fc6a5cc2a 2772 }
dkato 6:aa1fc6a5cc2a 2773 }
dkato 6:aa1fc6a5cc2a 2774 }
dkato 6:aa1fc6a5cc2a 2775 }
dkato 6:aa1fc6a5cc2a 2776
dkato 6:aa1fc6a5cc2a 2777 return;
dkato 6:aa1fc6a5cc2a 2778 }
dkato 6:aa1fc6a5cc2a 2779
dkato 6:aa1fc6a5cc2a 2780 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2781 End of function SCUX_SetupSsif
dkato 6:aa1fc6a5cc2a 2782 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2783
dkato 6:aa1fc6a5cc2a 2784 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2785 * Function Name: SCUX_SetupDma
dkato 6:aa1fc6a5cc2a 2786 * @brief DMA setup.
dkato 6:aa1fc6a5cc2a 2787 *
dkato 6:aa1fc6a5cc2a 2788 * Description:<br>
dkato 6:aa1fc6a5cc2a 2789 *
dkato 6:aa1fc6a5cc2a 2790 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 2791 * @retval None.
dkato 6:aa1fc6a5cc2a 2792 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2793
dkato 6:aa1fc6a5cc2a 2794 int_t SCUX_SetupDma(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2795 {
dkato 6:aa1fc6a5cc2a 2796 int_t retval = ESUCCESS;
dkato 6:aa1fc6a5cc2a 2797 AIOCB *dma_aio;
dkato 6:aa1fc6a5cc2a 2798 uint32_t dmacr_cim_value = 0;
dkato 6:aa1fc6a5cc2a 2799
dkato 6:aa1fc6a5cc2a 2800 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2801 {
dkato 6:aa1fc6a5cc2a 2802 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 2803 }
dkato 6:aa1fc6a5cc2a 2804 else
dkato 6:aa1fc6a5cc2a 2805 {
dkato 6:aa1fc6a5cc2a 2806 dma_aio = &gb_scux_write_dma_aio[p_scux_info_ch->channel];
dkato 6:aa1fc6a5cc2a 2807 /* dummy data write start */
dkato 6:aa1fc6a5cc2a 2808 dma_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
dkato 6:aa1fc6a5cc2a 2809 dma_aio->aio_sigevent.sigev_value.sival_int = p_scux_info_ch->channel;
dkato 6:aa1fc6a5cc2a 2810 if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 2811 {
dkato 6:aa1fc6a5cc2a 2812 dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_DirectTxCallBack;
dkato 6:aa1fc6a5cc2a 2813 }
dkato 6:aa1fc6a5cc2a 2814 else
dkato 6:aa1fc6a5cc2a 2815 {
dkato 6:aa1fc6a5cc2a 2816 dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_CopyTxCallBack;
dkato 6:aa1fc6a5cc2a 2817 }
dkato 6:aa1fc6a5cc2a 2818 p_scux_info_ch->dma_tx_setup.resource = p_scux_info_ch->dma_resource_tx;
dkato 6:aa1fc6a5cc2a 2819 p_scux_info_ch->dma_tx_setup.direction = DMA_REQ_DES;
dkato 6:aa1fc6a5cc2a 2820
dkato 6:aa1fc6a5cc2a 2821 switch (p_scux_info_ch->src_cfg.word_len)
dkato 6:aa1fc6a5cc2a 2822 {
dkato 6:aa1fc6a5cc2a 2823 case SCUX_DATA_LEN_16 :
dkato 6:aa1fc6a5cc2a 2824 /* fall through */
dkato 6:aa1fc6a5cc2a 2825 case SCUX_DATA_LEN_16_TO_24 :
dkato 6:aa1fc6a5cc2a 2826 p_scux_info_ch->dma_tx_setup.dst_width = DMA_UNIT_2;
dkato 6:aa1fc6a5cc2a 2827 p_scux_info_ch->dma_tx_setup.src_width = DMA_UNIT_2;
dkato 6:aa1fc6a5cc2a 2828 break;
dkato 6:aa1fc6a5cc2a 2829
dkato 6:aa1fc6a5cc2a 2830 case SCUX_DATA_LEN_24 :
dkato 6:aa1fc6a5cc2a 2831 p_scux_info_ch->dma_tx_setup.dst_width = DMA_UNIT_4;
dkato 6:aa1fc6a5cc2a 2832 p_scux_info_ch->dma_tx_setup.src_width = DMA_UNIT_4;
dkato 6:aa1fc6a5cc2a 2833 break;
dkato 6:aa1fc6a5cc2a 2834
dkato 6:aa1fc6a5cc2a 2835 default :
dkato 6:aa1fc6a5cc2a 2836 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2837 break;
dkato 6:aa1fc6a5cc2a 2838 }
dkato 6:aa1fc6a5cc2a 2839
dkato 6:aa1fc6a5cc2a 2840 p_scux_info_ch->dma_tx_setup.dst_cnt = DMA_ADDR_FIX;
dkato 6:aa1fc6a5cc2a 2841 p_scux_info_ch->dma_tx_setup.src_cnt = DMA_ADDR_INCREMENT;
dkato 6:aa1fc6a5cc2a 2842 p_scux_info_ch->dma_tx_setup.p_aio = dma_aio;
dkato 6:aa1fc6a5cc2a 2843
dkato 6:aa1fc6a5cc2a 2844 /* get read DMA channel */
dkato 6:aa1fc6a5cc2a 2845 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 2846 {
dkato 6:aa1fc6a5cc2a 2847 p_scux_info_ch->dma_rx_ch = R_DMA_Alloc(DMA_ALLOC_CH, NULL);
dkato 6:aa1fc6a5cc2a 2848 if (EERROR == p_scux_info_ch->dma_rx_ch)
dkato 6:aa1fc6a5cc2a 2849 {
dkato 6:aa1fc6a5cc2a 2850 retval = EMFILE;
dkato 6:aa1fc6a5cc2a 2851 }
dkato 6:aa1fc6a5cc2a 2852 else
dkato 6:aa1fc6a5cc2a 2853 {
dkato 6:aa1fc6a5cc2a 2854 dma_aio = &gb_scux_read_dma_aio[p_scux_info_ch->channel];
dkato 6:aa1fc6a5cc2a 2855 dma_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
dkato 6:aa1fc6a5cc2a 2856 dma_aio->aio_sigevent.sigev_value.sival_int = p_scux_info_ch->channel;
dkato 6:aa1fc6a5cc2a 2857 dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_CopyRxCallBack;
dkato 6:aa1fc6a5cc2a 2858 p_scux_info_ch->dma_rx_setup.resource = p_scux_info_ch->dma_resource_rx;
dkato 6:aa1fc6a5cc2a 2859 p_scux_info_ch->dma_rx_setup.direction = DMA_REQ_SRC;
dkato 6:aa1fc6a5cc2a 2860
dkato 6:aa1fc6a5cc2a 2861 switch (p_scux_info_ch->src_cfg.word_len)
dkato 6:aa1fc6a5cc2a 2862 {
dkato 6:aa1fc6a5cc2a 2863 case SCUX_DATA_LEN_16 :
dkato 6:aa1fc6a5cc2a 2864 p_scux_info_ch->dma_rx_setup.dst_width = DMA_UNIT_2;
dkato 6:aa1fc6a5cc2a 2865 p_scux_info_ch->dma_rx_setup.src_width = DMA_UNIT_2;
dkato 6:aa1fc6a5cc2a 2866 break;
dkato 6:aa1fc6a5cc2a 2867
dkato 6:aa1fc6a5cc2a 2868 case SCUX_DATA_LEN_24 :
dkato 6:aa1fc6a5cc2a 2869 /* fall through */
dkato 6:aa1fc6a5cc2a 2870 case SCUX_DATA_LEN_16_TO_24 :
dkato 6:aa1fc6a5cc2a 2871 p_scux_info_ch->dma_rx_setup.dst_width = DMA_UNIT_4;
dkato 6:aa1fc6a5cc2a 2872 p_scux_info_ch->dma_rx_setup.src_width = DMA_UNIT_4;
dkato 6:aa1fc6a5cc2a 2873 break;
dkato 6:aa1fc6a5cc2a 2874
dkato 6:aa1fc6a5cc2a 2875 default :
dkato 6:aa1fc6a5cc2a 2876 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 2877 break;
dkato 6:aa1fc6a5cc2a 2878 }
dkato 6:aa1fc6a5cc2a 2879
dkato 6:aa1fc6a5cc2a 2880 p_scux_info_ch->dma_rx_setup.dst_cnt = DMA_ADDR_INCREMENT;
dkato 6:aa1fc6a5cc2a 2881 p_scux_info_ch->dma_rx_setup.src_cnt = DMA_ADDR_FIX;
dkato 6:aa1fc6a5cc2a 2882 p_scux_info_ch->dma_rx_setup.p_aio = dma_aio;
dkato 6:aa1fc6a5cc2a 2883 }
dkato 6:aa1fc6a5cc2a 2884 }
dkato 6:aa1fc6a5cc2a 2885
dkato 6:aa1fc6a5cc2a 2886 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2887 {
dkato 6:aa1fc6a5cc2a 2888 dmacr_cim_value = *(p_scux_info_ch->p_scux_reg->dmacr_cim);
dkato 6:aa1fc6a5cc2a 2889 /* set write DMA param */
dkato 6:aa1fc6a5cc2a 2890 dmacr_cim_value |= (DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel);
dkato 6:aa1fc6a5cc2a 2891
dkato 6:aa1fc6a5cc2a 2892 /* set read DMA param */
dkato 6:aa1fc6a5cc2a 2893 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 2894 {
dkato 6:aa1fc6a5cc2a 2895 dmacr_cim_value |= (DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel);
dkato 6:aa1fc6a5cc2a 2896 }
dkato 6:aa1fc6a5cc2a 2897 }
dkato 6:aa1fc6a5cc2a 2898
dkato 6:aa1fc6a5cc2a 2899 if (ESUCCESS == retval)
dkato 6:aa1fc6a5cc2a 2900 {
dkato 6:aa1fc6a5cc2a 2901 *(p_scux_info_ch->p_scux_reg->dmacr_cim) = dmacr_cim_value;
dkato 6:aa1fc6a5cc2a 2902 }
dkato 6:aa1fc6a5cc2a 2903 }
dkato 6:aa1fc6a5cc2a 2904
dkato 6:aa1fc6a5cc2a 2905 return retval;
dkato 6:aa1fc6a5cc2a 2906 }
dkato 6:aa1fc6a5cc2a 2907
dkato 6:aa1fc6a5cc2a 2908 /******************************************************************************
dkato 6:aa1fc6a5cc2a 2909 End of function SCUX_SetupDma
dkato 6:aa1fc6a5cc2a 2910 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2911
dkato 6:aa1fc6a5cc2a 2912 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 2913 * Function Name: SCUX_InitHw
dkato 6:aa1fc6a5cc2a 2914 * @brief Initialize HW .
dkato 6:aa1fc6a5cc2a 2915 *
dkato 6:aa1fc6a5cc2a 2916 * Description:<br>
dkato 6:aa1fc6a5cc2a 2917 *
dkato 6:aa1fc6a5cc2a 2918 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 2919 * @retval None.
dkato 6:aa1fc6a5cc2a 2920 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 2921
dkato 6:aa1fc6a5cc2a 2922 void SCUX_InitHw(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 2923 {
dkato 6:aa1fc6a5cc2a 2924 scux_ssif_info_t *p_set_ssif;
dkato 6:aa1fc6a5cc2a 2925 uint32_t ssif_arrange_num;
dkato 6:aa1fc6a5cc2a 2926 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
dkato 6:aa1fc6a5cc2a 2927
dkato 6:aa1fc6a5cc2a 2928 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
dkato 6:aa1fc6a5cc2a 2929 {
dkato 6:aa1fc6a5cc2a 2930 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 2931 }
dkato 6:aa1fc6a5cc2a 2932 else
dkato 6:aa1fc6a5cc2a 2933 {
dkato 6:aa1fc6a5cc2a 2934 /* init FFD register */
dkato 6:aa1fc6a5cc2a 2935 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2936 p_scux_info_ch->p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2937 p_scux_info_ch->p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2938 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2939 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2940 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2941 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2942 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2943 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2944 *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2945 *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2946
dkato 6:aa1fc6a5cc2a 2947 /* check usc_ch ,and init SRC register */
dkato 6:aa1fc6a5cc2a 2948 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
dkato 6:aa1fc6a5cc2a 2949 {
dkato 6:aa1fc6a5cc2a 2950 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2951 p_scux_info_ch->p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2952 p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2953 p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2954 p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2955 p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
dkato 6:aa1fc6a5cc2a 2956 p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2957 p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2958 p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2959 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2960 p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2961 }
dkato 6:aa1fc6a5cc2a 2962 else
dkato 6:aa1fc6a5cc2a 2963 {
dkato 6:aa1fc6a5cc2a 2964 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2965 p_scux_info_ch->p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2966 p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2967 p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2968 p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2969 p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
dkato 6:aa1fc6a5cc2a 2970 p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2971 p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2972 p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2973 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2974 p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2975 p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2976 }
dkato 6:aa1fc6a5cc2a 2977
dkato 6:aa1fc6a5cc2a 2978 /* init FFU register */
dkato 6:aa1fc6a5cc2a 2979 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 2980 {
dkato 6:aa1fc6a5cc2a 2981 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2982 p_scux_info_ch->p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2983 p_scux_info_ch->p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2984 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2985 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2986 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2987 p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2988 p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2989 *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2990 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2991 }
dkato 6:aa1fc6a5cc2a 2992 else
dkato 6:aa1fc6a5cc2a 2993 {
dkato 6:aa1fc6a5cc2a 2994 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2995 p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2996 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2997 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2998 p_scux_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 2999 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3000 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3001 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3002 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3003 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3004 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3005 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3006 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3007 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3008 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3009 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3010 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3011 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3012 p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3013 p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3014
dkato 6:aa1fc6a5cc2a 3015 for (ssif_arrange_num = 0; ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT; ssif_arrange_num++)
dkato 6:aa1fc6a5cc2a 3016 {
dkato 6:aa1fc6a5cc2a 3017 switch (ssif_arrange_num)
dkato 6:aa1fc6a5cc2a 3018 {
dkato 6:aa1fc6a5cc2a 3019 case SCUX_SSIF_CH_ARRANGEMENT1:
dkato 6:aa1fc6a5cc2a 3020 p_set_ssif = p_scux_info_ch->p_ssif_info1;
dkato 6:aa1fc6a5cc2a 3021 break;
dkato 6:aa1fc6a5cc2a 3022
dkato 6:aa1fc6a5cc2a 3023 case SCUX_SSIF_CH_ARRANGEMENT2:
dkato 6:aa1fc6a5cc2a 3024 p_set_ssif = p_scux_info_ch->p_ssif_info2;
dkato 6:aa1fc6a5cc2a 3025 break;
dkato 6:aa1fc6a5cc2a 3026
dkato 6:aa1fc6a5cc2a 3027 case SCUX_SSIF_CH_ARRANGEMENT3:
dkato 6:aa1fc6a5cc2a 3028 p_set_ssif = p_scux_info_ch->p_ssif_info3;
dkato 6:aa1fc6a5cc2a 3029 break;
dkato 6:aa1fc6a5cc2a 3030
dkato 6:aa1fc6a5cc2a 3031 default :
dkato 6:aa1fc6a5cc2a 3032 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 3033 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 3034 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 3035 break;
dkato 6:aa1fc6a5cc2a 3036 }
dkato 6:aa1fc6a5cc2a 3037
dkato 6:aa1fc6a5cc2a 3038 if (NULL != p_set_ssif)
dkato 6:aa1fc6a5cc2a 3039 {
dkato 6:aa1fc6a5cc2a 3040 /* check SSIF is used on other MIX SCUX channel */
dkato 6:aa1fc6a5cc2a 3041 if (0U == ((uint32_t)p_set_ssif->scux_channel & ~(1U << p_scux_info_ch->channel)))
dkato 6:aa1fc6a5cc2a 3042 {
dkato 6:aa1fc6a5cc2a 3043 /* init SSIF register */
dkato 6:aa1fc6a5cc2a 3044 p_set_ssif->p_scux_ssif_reg->SSICR = SCUX_SSICR_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3045 p_set_ssif->p_scux_ssif_reg->SSIFCR = SCUX_SSIFCR_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3046 p_set_ssif->p_scux_ssif_reg->SSIFTDR = SCUX_SSIFTDR_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3047 p_set_ssif->p_scux_ssif_reg->SSITDMR = SCUX_SSITDMR_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3048 p_set_ssif->p_scux_ssif_reg->SSIFCCR = SCUX_SSIFCCR_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3049 p_set_ssif->p_scux_ssif_reg->SSIFCMR = SCUX_SSIFCMR_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3050 }
dkato 6:aa1fc6a5cc2a 3051 }
dkato 6:aa1fc6a5cc2a 3052 }
dkato 6:aa1fc6a5cc2a 3053 }
dkato 6:aa1fc6a5cc2a 3054
dkato 6:aa1fc6a5cc2a 3055 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 3056 {
dkato 6:aa1fc6a5cc2a 3057 /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */
dkato 6:aa1fc6a5cc2a 3058 if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag))
dkato 6:aa1fc6a5cc2a 3059 {
dkato 6:aa1fc6a5cc2a 3060 *(p_scux_info_ch->p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3061 *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3062 p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3063 *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3064 *(p_scux_info_ch->p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3065 *(p_scux_info_ch->p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3066 *(p_scux_info_ch->p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3067 *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3068 *(p_scux_info_ch->p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3069 *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3070 *(p_scux_info_ch->p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
dkato 6:aa1fc6a5cc2a 3071 }
dkato 6:aa1fc6a5cc2a 3072 }
dkato 6:aa1fc6a5cc2a 3073 }
dkato 6:aa1fc6a5cc2a 3074
dkato 6:aa1fc6a5cc2a 3075 return;
dkato 6:aa1fc6a5cc2a 3076 }
dkato 6:aa1fc6a5cc2a 3077
dkato 6:aa1fc6a5cc2a 3078 /******************************************************************************
dkato 6:aa1fc6a5cc2a 3079 End of function SCUX_InitHw
dkato 6:aa1fc6a5cc2a 3080 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 3081
dkato 6:aa1fc6a5cc2a 3082 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 3083 * Function Name: SCUX_SyncStartHw
dkato 6:aa1fc6a5cc2a 3084 * @brief Start Hw on sync mode.
dkato 6:aa1fc6a5cc2a 3085 *
dkato 6:aa1fc6a5cc2a 3086 * Description:<br>
dkato 6:aa1fc6a5cc2a 3087 *
dkato 6:aa1fc6a5cc2a 3088 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 3089 * @retval None.
dkato 6:aa1fc6a5cc2a 3090 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 3091
dkato 6:aa1fc6a5cc2a 3092 void SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 3093 {
dkato 6:aa1fc6a5cc2a 3094 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 3095 {
dkato 6:aa1fc6a5cc2a 3096 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 3097 }
dkato 6:aa1fc6a5cc2a 3098 else
dkato 6:aa1fc6a5cc2a 3099 {
dkato 6:aa1fc6a5cc2a 3100 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 &= ~FFDIR_FFD0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3101 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 |= FFDBR_FFD0_BOOT_SET;
dkato 6:aa1fc6a5cc2a 3102 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 &= ~FFUIR_FFU0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3103
dkato 6:aa1fc6a5cc2a 3104 /* check usc_ch ,and init SRC register */
dkato 6:aa1fc6a5cc2a 3105 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
dkato 6:aa1fc6a5cc2a 3106 {
dkato 6:aa1fc6a5cc2a 3107 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3108 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
dkato 6:aa1fc6a5cc2a 3109 }
dkato 6:aa1fc6a5cc2a 3110 else
dkato 6:aa1fc6a5cc2a 3111 {
dkato 6:aa1fc6a5cc2a 3112 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3113 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
dkato 6:aa1fc6a5cc2a 3114 }
dkato 6:aa1fc6a5cc2a 3115 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 &= ~IPCIR_IPC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3116 p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 &= ~OPCIR_OPC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3117
dkato 6:aa1fc6a5cc2a 3118 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 &= ~SRCIRR_2SRC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3119
dkato 6:aa1fc6a5cc2a 3120 GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
dkato 6:aa1fc6a5cc2a 3121 }
dkato 6:aa1fc6a5cc2a 3122
dkato 6:aa1fc6a5cc2a 3123 return;
dkato 6:aa1fc6a5cc2a 3124 }
dkato 6:aa1fc6a5cc2a 3125
dkato 6:aa1fc6a5cc2a 3126 /******************************************************************************
dkato 6:aa1fc6a5cc2a 3127 End of function SCUX_SyncStartHw
dkato 6:aa1fc6a5cc2a 3128 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 3129
dkato 6:aa1fc6a5cc2a 3130 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 3131 * Function Name: SCUX_AsyncStartHw
dkato 6:aa1fc6a5cc2a 3132 * @brief Start Hw on async mode.
dkato 6:aa1fc6a5cc2a 3133 *
dkato 6:aa1fc6a5cc2a 3134 * Description:<br>
dkato 6:aa1fc6a5cc2a 3135 *
dkato 6:aa1fc6a5cc2a 3136 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 3137 * @retval None.
dkato 6:aa1fc6a5cc2a 3138 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 3139
dkato 6:aa1fc6a5cc2a 3140 void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 3141 {
dkato 6:aa1fc6a5cc2a 3142 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
dkato 6:aa1fc6a5cc2a 3143
dkato 6:aa1fc6a5cc2a 3144 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
dkato 6:aa1fc6a5cc2a 3145 {
dkato 6:aa1fc6a5cc2a 3146 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 3147 }
dkato 6:aa1fc6a5cc2a 3148 else
dkato 6:aa1fc6a5cc2a 3149 {
dkato 6:aa1fc6a5cc2a 3150 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 &= ~FFDIR_FFD0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3151 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 |= FFDBR_FFD0_BOOT_SET;
dkato 6:aa1fc6a5cc2a 3152
dkato 6:aa1fc6a5cc2a 3153 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 3154 {
dkato 6:aa1fc6a5cc2a 3155 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 &= ~FFUIR_FFU0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3156 }
dkato 6:aa1fc6a5cc2a 3157
dkato 6:aa1fc6a5cc2a 3158 /* check usc_ch ,and init SRC register */
dkato 6:aa1fc6a5cc2a 3159 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
dkato 6:aa1fc6a5cc2a 3160 {
dkato 6:aa1fc6a5cc2a 3161 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3162 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
dkato 6:aa1fc6a5cc2a 3163 }
dkato 6:aa1fc6a5cc2a 3164 else
dkato 6:aa1fc6a5cc2a 3165 {
dkato 6:aa1fc6a5cc2a 3166 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3167 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
dkato 6:aa1fc6a5cc2a 3168 }
dkato 6:aa1fc6a5cc2a 3169
dkato 6:aa1fc6a5cc2a 3170 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 &= ~SRCIRR_2SRC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3171
dkato 6:aa1fc6a5cc2a 3172 GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
dkato 6:aa1fc6a5cc2a 3173
dkato 6:aa1fc6a5cc2a 3174 if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 3175 {
dkato 6:aa1fc6a5cc2a 3176 SCUX_SetupDvuVolume(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 3177
dkato 6:aa1fc6a5cc2a 3178 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 3179 {
dkato 6:aa1fc6a5cc2a 3180 SCUX_SetupMix(p_scux_info_ch);
dkato 6:aa1fc6a5cc2a 3181 }
dkato 6:aa1fc6a5cc2a 3182 }
dkato 6:aa1fc6a5cc2a 3183
dkato 6:aa1fc6a5cc2a 3184 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 &= ~IPCIR_IPC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3185 p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 &= ~OPCIR_OPC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3186
dkato 6:aa1fc6a5cc2a 3187 if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 3188 {
dkato 6:aa1fc6a5cc2a 3189 /* check used SSIF is only 1 ch */
dkato 6:aa1fc6a5cc2a 3190 if (NULL == p_scux_info_ch->p_ssif_info2)
dkato 6:aa1fc6a5cc2a 3191 {
dkato 6:aa1fc6a5cc2a 3192 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR |= SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3193 }
dkato 6:aa1fc6a5cc2a 3194 else
dkato 6:aa1fc6a5cc2a 3195 {
dkato 6:aa1fc6a5cc2a 3196 if (SCUX_SSIF_CH_0 == p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num)
dkato 6:aa1fc6a5cc2a 3197 {
dkato 6:aa1fc6a5cc2a 3198 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI012TEN_SET;
dkato 6:aa1fc6a5cc2a 3199 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3200 }
dkato 6:aa1fc6a5cc2a 3201 else
dkato 6:aa1fc6a5cc2a 3202 {
dkato 6:aa1fc6a5cc2a 3203 p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI345TEN_SET;
dkato 6:aa1fc6a5cc2a 3204 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3205 }
dkato 6:aa1fc6a5cc2a 3206 }
dkato 6:aa1fc6a5cc2a 3207 }
dkato 6:aa1fc6a5cc2a 3208 }
dkato 6:aa1fc6a5cc2a 3209
dkato 6:aa1fc6a5cc2a 3210 return;
dkato 6:aa1fc6a5cc2a 3211 }
dkato 6:aa1fc6a5cc2a 3212
dkato 6:aa1fc6a5cc2a 3213 /******************************************************************************
dkato 6:aa1fc6a5cc2a 3214 End of function SCUX_AsyncStartHw
dkato 6:aa1fc6a5cc2a 3215 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 3216
dkato 6:aa1fc6a5cc2a 3217 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 3218 * Function Name: SCUX_SyncStopHw
dkato 6:aa1fc6a5cc2a 3219 * @brief Stop Hw on sync mode.
dkato 6:aa1fc6a5cc2a 3220 *
dkato 6:aa1fc6a5cc2a 3221 * Description:<br>
dkato 6:aa1fc6a5cc2a 3222 *
dkato 6:aa1fc6a5cc2a 3223 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 3224 * @retval None.
dkato 6:aa1fc6a5cc2a 3225 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 3226
dkato 6:aa1fc6a5cc2a 3227 void SCUX_SyncStopHw(const scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 3228 {
dkato 6:aa1fc6a5cc2a 3229 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 3230 {
dkato 6:aa1fc6a5cc2a 3231 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 3232 }
dkato 6:aa1fc6a5cc2a 3233 else
dkato 6:aa1fc6a5cc2a 3234 {
dkato 6:aa1fc6a5cc2a 3235 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET |
dkato 6:aa1fc6a5cc2a 3236 UEVMR_FFU0_UEVMOF_SET |
dkato 6:aa1fc6a5cc2a 3237 UEVMR_FFU0_UEVMOL_SET);
dkato 6:aa1fc6a5cc2a 3238 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]);
dkato 6:aa1fc6a5cc2a 3239
dkato 6:aa1fc6a5cc2a 3240 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 |= FFUIR_FFU0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3241 p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 |= OPCIR_OPC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3242
dkato 6:aa1fc6a5cc2a 3243 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET |
dkato 6:aa1fc6a5cc2a 3244 DEVMR_FFD0_DEVMOF_SET |
dkato 6:aa1fc6a5cc2a 3245 DEVMR_FFD0_DEVMOL_SET |
dkato 6:aa1fc6a5cc2a 3246 DEVMR_FFD0_DEVMIUF_SET);
dkato 6:aa1fc6a5cc2a 3247 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]);
dkato 6:aa1fc6a5cc2a 3248
dkato 6:aa1fc6a5cc2a 3249 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 |= FFDIR_FFD0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3250 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 |= IPCIR_IPC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3251
dkato 6:aa1fc6a5cc2a 3252 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 &= ~FFDBR_FFD0_BOOT_SET;
dkato 6:aa1fc6a5cc2a 3253
dkato 6:aa1fc6a5cc2a 3254 /* check usc_ch ,and init SRC register */
dkato 6:aa1fc6a5cc2a 3255 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
dkato 6:aa1fc6a5cc2a 3256 {
dkato 6:aa1fc6a5cc2a 3257 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3258 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET |
dkato 6:aa1fc6a5cc2a 3259 SEVMR_2SRC0_EVMOF_SET);
dkato 6:aa1fc6a5cc2a 3260 }
dkato 6:aa1fc6a5cc2a 3261 else
dkato 6:aa1fc6a5cc2a 3262 {
dkato 6:aa1fc6a5cc2a 3263 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3264 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET |
dkato 6:aa1fc6a5cc2a 3265 SEVMR_2SRC0_EVMOF_SET);
dkato 6:aa1fc6a5cc2a 3266 }
dkato 6:aa1fc6a5cc2a 3267
dkato 6:aa1fc6a5cc2a 3268 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 |= SRCIRR_2SRC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3269
dkato 6:aa1fc6a5cc2a 3270 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
dkato 6:aa1fc6a5cc2a 3271 }
dkato 6:aa1fc6a5cc2a 3272
dkato 6:aa1fc6a5cc2a 3273 return;
dkato 6:aa1fc6a5cc2a 3274 }
dkato 6:aa1fc6a5cc2a 3275
dkato 6:aa1fc6a5cc2a 3276 /******************************************************************************
dkato 6:aa1fc6a5cc2a 3277 End of function SCUX_SyncStopHw
dkato 6:aa1fc6a5cc2a 3278 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 3279
dkato 6:aa1fc6a5cc2a 3280 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 3281 * Function Name: SCUX_AsyncStopHw
dkato 6:aa1fc6a5cc2a 3282 * @brief Stop Hw on async mode.
dkato 6:aa1fc6a5cc2a 3283 *
dkato 6:aa1fc6a5cc2a 3284 * Description:<br>
dkato 6:aa1fc6a5cc2a 3285 *
dkato 6:aa1fc6a5cc2a 3286 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 3287 * @retval None.
dkato 6:aa1fc6a5cc2a 3288 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 3289
dkato 6:aa1fc6a5cc2a 3290 void SCUX_AsyncStopHw(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 3291 {
dkato 6:aa1fc6a5cc2a 3292 uint32_t scux_check_ch;
dkato 6:aa1fc6a5cc2a 3293 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
dkato 6:aa1fc6a5cc2a 3294 uint32_t ssipmd_mask_ssif2 = 0;
dkato 6:aa1fc6a5cc2a 3295 uint32_t ssipmd_mask_ssif3 = 0;
dkato 6:aa1fc6a5cc2a 3296 uint32_t ssipmd_shift_ssif2 = 0;
dkato 6:aa1fc6a5cc2a 3297 uint32_t ssipmd_shift_ssif3 = 0;
dkato 6:aa1fc6a5cc2a 3298 uint32_t ssipmd_reg;
dkato 6:aa1fc6a5cc2a 3299 scux_info_ch_t *p_pair_scux_ch;
dkato 6:aa1fc6a5cc2a 3300 int_t was_masked;
dkato 6:aa1fc6a5cc2a 3301
dkato 6:aa1fc6a5cc2a 3302 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
dkato 6:aa1fc6a5cc2a 3303 {
dkato 6:aa1fc6a5cc2a 3304 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 3305 }
dkato 6:aa1fc6a5cc2a 3306 else
dkato 6:aa1fc6a5cc2a 3307 {
dkato 6:aa1fc6a5cc2a 3308 if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 3309 {
dkato 6:aa1fc6a5cc2a 3310 p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET |
dkato 6:aa1fc6a5cc2a 3311 UEVMR_FFU0_UEVMOF_SET |
dkato 6:aa1fc6a5cc2a 3312 UEVMR_FFU0_UEVMOL_SET);
dkato 6:aa1fc6a5cc2a 3313 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]);
dkato 6:aa1fc6a5cc2a 3314 p_scux_info_ch->futsel_cim_value &= ~FUTSEL_CIM_DIVEN_SET;
dkato 6:aa1fc6a5cc2a 3315 *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
dkato 6:aa1fc6a5cc2a 3316
dkato 6:aa1fc6a5cc2a 3317 p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 |= FFUIR_FFU0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3318 }
dkato 6:aa1fc6a5cc2a 3319
dkato 6:aa1fc6a5cc2a 3320 p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 |= OPCIR_OPC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3321
dkato 6:aa1fc6a5cc2a 3322 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 3323 {
dkato 6:aa1fc6a5cc2a 3324 p_info_drv->shared_info.mix_run_ch &= ~(1U << p_scux_info_ch->channel);
dkato 6:aa1fc6a5cc2a 3325 }
dkato 6:aa1fc6a5cc2a 3326
dkato 6:aa1fc6a5cc2a 3327 switch (p_scux_info_ch->route_set)
dkato 6:aa1fc6a5cc2a 3328 {
dkato 6:aa1fc6a5cc2a 3329 case SCUX_ROUTE_SRC0_MEM :
dkato 6:aa1fc6a5cc2a 3330 /* fall through */
dkato 6:aa1fc6a5cc2a 3331 case SCUX_ROUTE_SRC1_MEM :
dkato 6:aa1fc6a5cc2a 3332 /* fall through */
dkato 6:aa1fc6a5cc2a 3333 case SCUX_ROUTE_SRC2_MEM :
dkato 6:aa1fc6a5cc2a 3334 /* fall through */
dkato 6:aa1fc6a5cc2a 3335 case SCUX_ROUTE_SRC3_MEM :
dkato 6:aa1fc6a5cc2a 3336 /* do nothing, when mem to mem route is setting */
dkato 6:aa1fc6a5cc2a 3337 break;
dkato 6:aa1fc6a5cc2a 3338
dkato 6:aa1fc6a5cc2a 3339 case SCUX_ROUTE_SRC0_SSIF0 :
dkato 6:aa1fc6a5cc2a 3340 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
dkato 6:aa1fc6a5cc2a 3341 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3342 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3343 break;
dkato 6:aa1fc6a5cc2a 3344
dkato 6:aa1fc6a5cc2a 3345 case SCUX_ROUTE_SRC0_SSIF012 :
dkato 6:aa1fc6a5cc2a 3346 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
dkato 6:aa1fc6a5cc2a 3347 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3348 break;
dkato 6:aa1fc6a5cc2a 3349
dkato 6:aa1fc6a5cc2a 3350 case SCUX_ROUTE_SRC0_SSIF3 :
dkato 6:aa1fc6a5cc2a 3351 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
dkato 6:aa1fc6a5cc2a 3352 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3353 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3354 break;
dkato 6:aa1fc6a5cc2a 3355
dkato 6:aa1fc6a5cc2a 3356 case SCUX_ROUTE_SRC0_SSIF345 :
dkato 6:aa1fc6a5cc2a 3357 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
dkato 6:aa1fc6a5cc2a 3358 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3359 break;
dkato 6:aa1fc6a5cc2a 3360
dkato 6:aa1fc6a5cc2a 3361 case SCUX_ROUTE_SRC1_SSIF0 :
dkato 6:aa1fc6a5cc2a 3362 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
dkato 6:aa1fc6a5cc2a 3363 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3364 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3365 break;
dkato 6:aa1fc6a5cc2a 3366
dkato 6:aa1fc6a5cc2a 3367 case SCUX_ROUTE_SRC1_SSIF012 :
dkato 6:aa1fc6a5cc2a 3368 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
dkato 6:aa1fc6a5cc2a 3369 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3370 break;
dkato 6:aa1fc6a5cc2a 3371
dkato 6:aa1fc6a5cc2a 3372 case SCUX_ROUTE_SRC1_SSIF3 :
dkato 6:aa1fc6a5cc2a 3373 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
dkato 6:aa1fc6a5cc2a 3374 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3375 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3376 break;
dkato 6:aa1fc6a5cc2a 3377
dkato 6:aa1fc6a5cc2a 3378 case SCUX_ROUTE_SRC1_SSIF345 :
dkato 6:aa1fc6a5cc2a 3379 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
dkato 6:aa1fc6a5cc2a 3380 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3381 break;
dkato 6:aa1fc6a5cc2a 3382
dkato 6:aa1fc6a5cc2a 3383 case SCUX_ROUTE_SRC2_SSIF1 :
dkato 6:aa1fc6a5cc2a 3384 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI1TX_SET;
dkato 6:aa1fc6a5cc2a 3385 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3386 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3387 break;
dkato 6:aa1fc6a5cc2a 3388
dkato 6:aa1fc6a5cc2a 3389 case SCUX_ROUTE_SRC2_SSIF4 :
dkato 6:aa1fc6a5cc2a 3390 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI4TX_SET;
dkato 6:aa1fc6a5cc2a 3391 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3392 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3393 break;
dkato 6:aa1fc6a5cc2a 3394
dkato 6:aa1fc6a5cc2a 3395 case SCUX_ROUTE_SRC3_SSIF2 :
dkato 6:aa1fc6a5cc2a 3396 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI2TX_SET;
dkato 6:aa1fc6a5cc2a 3397 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3398 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3399 break;
dkato 6:aa1fc6a5cc2a 3400
dkato 6:aa1fc6a5cc2a 3401 case SCUX_ROUTE_SRC3_SSIF5 :
dkato 6:aa1fc6a5cc2a 3402 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI5TX_SET;
dkato 6:aa1fc6a5cc2a 3403 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3404 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3405 break;
dkato 6:aa1fc6a5cc2a 3406
dkato 6:aa1fc6a5cc2a 3407 case SCUX_ROUTE_SRC0_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 3408 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3409 {
dkato 6:aa1fc6a5cc2a 3410 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
dkato 6:aa1fc6a5cc2a 3411 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3412 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3413 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3414 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3415 {
dkato 6:aa1fc6a5cc2a 3416 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3417 }
dkato 6:aa1fc6a5cc2a 3418 }
dkato 6:aa1fc6a5cc2a 3419 break;
dkato 6:aa1fc6a5cc2a 3420
dkato 6:aa1fc6a5cc2a 3421 case SCUX_ROUTE_SRC0_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 3422 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3423 {
dkato 6:aa1fc6a5cc2a 3424 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
dkato 6:aa1fc6a5cc2a 3425 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3426 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3427 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3428 {
dkato 6:aa1fc6a5cc2a 3429 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3430 }
dkato 6:aa1fc6a5cc2a 3431 }
dkato 6:aa1fc6a5cc2a 3432 break;
dkato 6:aa1fc6a5cc2a 3433
dkato 6:aa1fc6a5cc2a 3434 case SCUX_ROUTE_SRC0_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 3435 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3436 {
dkato 6:aa1fc6a5cc2a 3437 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
dkato 6:aa1fc6a5cc2a 3438 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3439 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3440 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3441 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3442 {
dkato 6:aa1fc6a5cc2a 3443 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3444 }
dkato 6:aa1fc6a5cc2a 3445 }
dkato 6:aa1fc6a5cc2a 3446 break;
dkato 6:aa1fc6a5cc2a 3447
dkato 6:aa1fc6a5cc2a 3448 case SCUX_ROUTE_SRC0_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 3449 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3450 {
dkato 6:aa1fc6a5cc2a 3451 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
dkato 6:aa1fc6a5cc2a 3452 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3453 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3454 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3455 {
dkato 6:aa1fc6a5cc2a 3456 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3457 }
dkato 6:aa1fc6a5cc2a 3458 }
dkato 6:aa1fc6a5cc2a 3459 break;
dkato 6:aa1fc6a5cc2a 3460
dkato 6:aa1fc6a5cc2a 3461 case SCUX_ROUTE_SRC1_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 3462 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3463 {
dkato 6:aa1fc6a5cc2a 3464 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
dkato 6:aa1fc6a5cc2a 3465 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3466 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3467 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3468 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3469 {
dkato 6:aa1fc6a5cc2a 3470 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3471 }
dkato 6:aa1fc6a5cc2a 3472 }
dkato 6:aa1fc6a5cc2a 3473 break;
dkato 6:aa1fc6a5cc2a 3474
dkato 6:aa1fc6a5cc2a 3475 case SCUX_ROUTE_SRC1_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 3476 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3477 {
dkato 6:aa1fc6a5cc2a 3478 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
dkato 6:aa1fc6a5cc2a 3479 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3480 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3481 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3482 {
dkato 6:aa1fc6a5cc2a 3483 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3484 }
dkato 6:aa1fc6a5cc2a 3485 }
dkato 6:aa1fc6a5cc2a 3486 break;
dkato 6:aa1fc6a5cc2a 3487
dkato 6:aa1fc6a5cc2a 3488 case SCUX_ROUTE_SRC1_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 3489 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3490 {
dkato 6:aa1fc6a5cc2a 3491 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
dkato 6:aa1fc6a5cc2a 3492 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3493 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3494 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3495 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3496 {
dkato 6:aa1fc6a5cc2a 3497 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3498 }
dkato 6:aa1fc6a5cc2a 3499 }
dkato 6:aa1fc6a5cc2a 3500 break;
dkato 6:aa1fc6a5cc2a 3501
dkato 6:aa1fc6a5cc2a 3502 case SCUX_ROUTE_SRC1_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 3503 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3504 {
dkato 6:aa1fc6a5cc2a 3505 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
dkato 6:aa1fc6a5cc2a 3506 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3507 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3508 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3509 {
dkato 6:aa1fc6a5cc2a 3510 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3511 }
dkato 6:aa1fc6a5cc2a 3512 }
dkato 6:aa1fc6a5cc2a 3513 break;
dkato 6:aa1fc6a5cc2a 3514
dkato 6:aa1fc6a5cc2a 3515 case SCUX_ROUTE_SRC2_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 3516 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3517 {
dkato 6:aa1fc6a5cc2a 3518 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
dkato 6:aa1fc6a5cc2a 3519 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3520 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3521 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3522 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3523 {
dkato 6:aa1fc6a5cc2a 3524 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3525 }
dkato 6:aa1fc6a5cc2a 3526 }
dkato 6:aa1fc6a5cc2a 3527 break;
dkato 6:aa1fc6a5cc2a 3528
dkato 6:aa1fc6a5cc2a 3529 case SCUX_ROUTE_SRC2_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 3530 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3531 {
dkato 6:aa1fc6a5cc2a 3532 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
dkato 6:aa1fc6a5cc2a 3533 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3534 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3535 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3536 {
dkato 6:aa1fc6a5cc2a 3537 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3538 }
dkato 6:aa1fc6a5cc2a 3539 }
dkato 6:aa1fc6a5cc2a 3540 break;
dkato 6:aa1fc6a5cc2a 3541
dkato 6:aa1fc6a5cc2a 3542 case SCUX_ROUTE_SRC2_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 3543 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3544 {
dkato 6:aa1fc6a5cc2a 3545 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
dkato 6:aa1fc6a5cc2a 3546 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3547 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3548 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3549 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3550 {
dkato 6:aa1fc6a5cc2a 3551 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3552 }
dkato 6:aa1fc6a5cc2a 3553 }
dkato 6:aa1fc6a5cc2a 3554 break;
dkato 6:aa1fc6a5cc2a 3555
dkato 6:aa1fc6a5cc2a 3556 case SCUX_ROUTE_SRC2_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 3557 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3558 {
dkato 6:aa1fc6a5cc2a 3559 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
dkato 6:aa1fc6a5cc2a 3560 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3561 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3562 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3563 {
dkato 6:aa1fc6a5cc2a 3564 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3565 }
dkato 6:aa1fc6a5cc2a 3566 }
dkato 6:aa1fc6a5cc2a 3567 break;
dkato 6:aa1fc6a5cc2a 3568
dkato 6:aa1fc6a5cc2a 3569 case SCUX_ROUTE_SRC3_MIX_SSIF0 :
dkato 6:aa1fc6a5cc2a 3570 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3571 {
dkato 6:aa1fc6a5cc2a 3572 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
dkato 6:aa1fc6a5cc2a 3573 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3574 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3575 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3576 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3577 {
dkato 6:aa1fc6a5cc2a 3578 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3579 }
dkato 6:aa1fc6a5cc2a 3580 }
dkato 6:aa1fc6a5cc2a 3581 break;
dkato 6:aa1fc6a5cc2a 3582
dkato 6:aa1fc6a5cc2a 3583 case SCUX_ROUTE_SRC3_MIX_SSIF012 :
dkato 6:aa1fc6a5cc2a 3584 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3585 {
dkato 6:aa1fc6a5cc2a 3586 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
dkato 6:aa1fc6a5cc2a 3587 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3588 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3589 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3590 {
dkato 6:aa1fc6a5cc2a 3591 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3592 }
dkato 6:aa1fc6a5cc2a 3593 }
dkato 6:aa1fc6a5cc2a 3594 break;
dkato 6:aa1fc6a5cc2a 3595
dkato 6:aa1fc6a5cc2a 3596 case SCUX_ROUTE_SRC3_MIX_SSIF3 :
dkato 6:aa1fc6a5cc2a 3597 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3598 {
dkato 6:aa1fc6a5cc2a 3599 p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
dkato 6:aa1fc6a5cc2a 3600 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3601 p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
dkato 6:aa1fc6a5cc2a 3602 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3603 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3604 {
dkato 6:aa1fc6a5cc2a 3605 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3606 }
dkato 6:aa1fc6a5cc2a 3607 }
dkato 6:aa1fc6a5cc2a 3608 break;
dkato 6:aa1fc6a5cc2a 3609
dkato 6:aa1fc6a5cc2a 3610 case SCUX_ROUTE_SRC3_MIX_SSIF345 :
dkato 6:aa1fc6a5cc2a 3611 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3612 {
dkato 6:aa1fc6a5cc2a 3613 p_info_drv->shared_info.ssictrl_cim_value &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
dkato 6:aa1fc6a5cc2a 3614 *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
dkato 6:aa1fc6a5cc2a 3615 /* initialized MIX parameter not on going cancel */
dkato 6:aa1fc6a5cc2a 3616 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3617 {
dkato 6:aa1fc6a5cc2a 3618 p_info_drv->shared_info.mix_ssif_ch = 0;
dkato 6:aa1fc6a5cc2a 3619 }
dkato 6:aa1fc6a5cc2a 3620 }
dkato 6:aa1fc6a5cc2a 3621 break;
dkato 6:aa1fc6a5cc2a 3622
dkato 6:aa1fc6a5cc2a 3623 default :
dkato 6:aa1fc6a5cc2a 3624 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 3625 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 3626 /* do nothing, when mem to mem route is setting */
dkato 6:aa1fc6a5cc2a 3627 break;
dkato 6:aa1fc6a5cc2a 3628 }
dkato 6:aa1fc6a5cc2a 3629
dkato 6:aa1fc6a5cc2a 3630 p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET |
dkato 6:aa1fc6a5cc2a 3631 DEVMR_FFD0_DEVMOF_SET |
dkato 6:aa1fc6a5cc2a 3632 DEVMR_FFD0_DEVMOL_SET |
dkato 6:aa1fc6a5cc2a 3633 DEVMR_FFD0_DEVMIUF_SET);
dkato 6:aa1fc6a5cc2a 3634 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]);
dkato 6:aa1fc6a5cc2a 3635
dkato 6:aa1fc6a5cc2a 3636 *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) &= ~FDTSEL_CIM_DIVEN_SET;
dkato 6:aa1fc6a5cc2a 3637
dkato 6:aa1fc6a5cc2a 3638 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 |= FFDIR_FFD0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3639 p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 |= IPCIR_IPC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3640
dkato 6:aa1fc6a5cc2a 3641 p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 &= ~FFDBR_FFD0_BOOT_SET;
dkato 6:aa1fc6a5cc2a 3642
dkato 6:aa1fc6a5cc2a 3643 /* check usc_ch ,and init SRC register */
dkato 6:aa1fc6a5cc2a 3644 if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
dkato 6:aa1fc6a5cc2a 3645 {
dkato 6:aa1fc6a5cc2a 3646 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET |
dkato 6:aa1fc6a5cc2a 3647 SEVMR_2SRC0_EVMOF_SET);
dkato 6:aa1fc6a5cc2a 3648 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3649 }
dkato 6:aa1fc6a5cc2a 3650 else
dkato 6:aa1fc6a5cc2a 3651 {
dkato 6:aa1fc6a5cc2a 3652 p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET |
dkato 6:aa1fc6a5cc2a 3653 SEVMR_2SRC0_EVMOF_SET);
dkato 6:aa1fc6a5cc2a 3654 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3655 }
dkato 6:aa1fc6a5cc2a 3656
dkato 6:aa1fc6a5cc2a 3657 /* if pair channel is stopped, common SRC unit is initialized */
dkato 6:aa1fc6a5cc2a 3658 if (SCUX_CH_0 == p_scux_info_ch->channel)
dkato 6:aa1fc6a5cc2a 3659 {
dkato 6:aa1fc6a5cc2a 3660 p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_1);
dkato 6:aa1fc6a5cc2a 3661 }
dkato 6:aa1fc6a5cc2a 3662 else if (SCUX_CH_1 == p_scux_info_ch->channel)
dkato 6:aa1fc6a5cc2a 3663 {
dkato 6:aa1fc6a5cc2a 3664 p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_0);
dkato 6:aa1fc6a5cc2a 3665 }
dkato 6:aa1fc6a5cc2a 3666 else if (SCUX_CH_2 == p_scux_info_ch->channel)
dkato 6:aa1fc6a5cc2a 3667 {
dkato 6:aa1fc6a5cc2a 3668 p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_3);
dkato 6:aa1fc6a5cc2a 3669 }
dkato 6:aa1fc6a5cc2a 3670 else
dkato 6:aa1fc6a5cc2a 3671 {
dkato 6:aa1fc6a5cc2a 3672 p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_2);
dkato 6:aa1fc6a5cc2a 3673 }
dkato 6:aa1fc6a5cc2a 3674
dkato 6:aa1fc6a5cc2a 3675 if (NULL != p_pair_scux_ch)
dkato 6:aa1fc6a5cc2a 3676 {
dkato 6:aa1fc6a5cc2a 3677 if ((SCUX_CH_UNINIT == p_pair_scux_ch->ch_stat) ||
dkato 6:aa1fc6a5cc2a 3678 (SCUX_CH_INIT == p_pair_scux_ch->ch_stat) ||
dkato 6:aa1fc6a5cc2a 3679 (SCUX_CH_STOP == p_pair_scux_ch->ch_stat))
dkato 6:aa1fc6a5cc2a 3680 {
dkato 6:aa1fc6a5cc2a 3681 p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 |= SRCIRR_2SRC0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3682 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
dkato 6:aa1fc6a5cc2a 3683 }
dkato 6:aa1fc6a5cc2a 3684 }
dkato 6:aa1fc6a5cc2a 3685 else
dkato 6:aa1fc6a5cc2a 3686 {
dkato 6:aa1fc6a5cc2a 3687 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 3688 }
dkato 6:aa1fc6a5cc2a 3689
dkato 6:aa1fc6a5cc2a 3690 if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 3691 {
dkato 6:aa1fc6a5cc2a 3692 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 |= DVUIR_DVU0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3693
dkato 6:aa1fc6a5cc2a 3694 p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = 0;
dkato 6:aa1fc6a5cc2a 3695 GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_DVI]);
dkato 6:aa1fc6a5cc2a 3696
dkato 6:aa1fc6a5cc2a 3697 scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info1->scux_channel;
dkato 6:aa1fc6a5cc2a 3698 scux_check_ch &= ~(1U << p_scux_info_ch->channel);
dkato 6:aa1fc6a5cc2a 3699 p_scux_info_ch->p_ssif_info1->scux_channel = (int_t)scux_check_ch;
dkato 6:aa1fc6a5cc2a 3700 if (0 == p_scux_info_ch->p_ssif_info1->scux_channel)
dkato 6:aa1fc6a5cc2a 3701 {
dkato 6:aa1fc6a5cc2a 3702 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 3703 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 3704 #else
dkato 6:aa1fc6a5cc2a 3705 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 3706 #endif
dkato 6:aa1fc6a5cc2a 3707
dkato 6:aa1fc6a5cc2a 3708 /* clock mask on all used SSIF channel shutdown */
dkato 6:aa1fc6a5cc2a 3709 CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num]);
dkato 6:aa1fc6a5cc2a 3710
dkato 6:aa1fc6a5cc2a 3711 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 3712 {
dkato 6:aa1fc6a5cc2a 3713 __enable_irq();
dkato 6:aa1fc6a5cc2a 3714 }
dkato 6:aa1fc6a5cc2a 3715 }
dkato 6:aa1fc6a5cc2a 3716
dkato 6:aa1fc6a5cc2a 3717 if (NULL != p_scux_info_ch->p_ssif_info2)
dkato 6:aa1fc6a5cc2a 3718 {
dkato 6:aa1fc6a5cc2a 3719 /* clear multiple SSIF setting */
dkato 6:aa1fc6a5cc2a 3720 scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info2->scux_channel;
dkato 6:aa1fc6a5cc2a 3721 scux_check_ch &= ~(1U << p_scux_info_ch->channel);
dkato 6:aa1fc6a5cc2a 3722 p_scux_info_ch->p_ssif_info2->scux_channel = (int_t)scux_check_ch;
dkato 6:aa1fc6a5cc2a 3723 p_scux_info_ch->p_ssif_info2->pin_mode = p_scux_info_ch->p_ssif_info2->pin_mode_backup;
dkato 6:aa1fc6a5cc2a 3724
dkato 6:aa1fc6a5cc2a 3725 switch (p_scux_info_ch->p_ssif_info2->ssif_cfg.ssif_ch_num)
dkato 6:aa1fc6a5cc2a 3726 {
dkato 6:aa1fc6a5cc2a 3727 case SCUX_SSIF_CH_1 :
dkato 6:aa1fc6a5cc2a 3728 ssipmd_mask_ssif2 = SSIPMD_CIM_SSI1PMD_MASK;
dkato 6:aa1fc6a5cc2a 3729 ssipmd_shift_ssif2 = SSIPMD_CIM_SSI1PMD_SHIFT;
dkato 6:aa1fc6a5cc2a 3730 break;
dkato 6:aa1fc6a5cc2a 3731
dkato 6:aa1fc6a5cc2a 3732 case SCUX_SSIF_CH_2 :
dkato 6:aa1fc6a5cc2a 3733 ssipmd_mask_ssif2 = SSIPMD_CIM_SSI2PMD_MASK;
dkato 6:aa1fc6a5cc2a 3734 ssipmd_shift_ssif2 = SSIPMD_CIM_SSI2PMD_SHIFT;
dkato 6:aa1fc6a5cc2a 3735 break;
dkato 6:aa1fc6a5cc2a 3736
dkato 6:aa1fc6a5cc2a 3737 case SCUX_SSIF_CH_3 :
dkato 6:aa1fc6a5cc2a 3738 ssipmd_mask_ssif2 = SSIPMD_CIM_SSI3PMD_MASK;
dkato 6:aa1fc6a5cc2a 3739 ssipmd_shift_ssif2 = SSIPMD_CIM_SSI3PMD_SHIFT;
dkato 6:aa1fc6a5cc2a 3740 break;
dkato 6:aa1fc6a5cc2a 3741
dkato 6:aa1fc6a5cc2a 3742 case SCUX_SSIF_CH_4 :
dkato 6:aa1fc6a5cc2a 3743 ssipmd_mask_ssif2 = SSIPMD_CIM_SSI4PMD_MASK;
dkato 6:aa1fc6a5cc2a 3744 ssipmd_shift_ssif2 = SSIPMD_CIM_SSI4PMD_SHIFT;
dkato 6:aa1fc6a5cc2a 3745 break;
dkato 6:aa1fc6a5cc2a 3746
dkato 6:aa1fc6a5cc2a 3747 case SCUX_SSIF_CH_5 :
dkato 6:aa1fc6a5cc2a 3748 ssipmd_mask_ssif2 = SSIPMD_CIM_SSI5PMD_MASK;
dkato 6:aa1fc6a5cc2a 3749 ssipmd_shift_ssif2 = SSIPMD_CIM_SSI5PMD_SHIFT;
dkato 6:aa1fc6a5cc2a 3750 break;
dkato 6:aa1fc6a5cc2a 3751
dkato 6:aa1fc6a5cc2a 3752 default :
dkato 6:aa1fc6a5cc2a 3753 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 3754 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 3755 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 3756 break;
dkato 6:aa1fc6a5cc2a 3757 }
dkato 6:aa1fc6a5cc2a 3758
dkato 6:aa1fc6a5cc2a 3759 scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info3->scux_channel;
dkato 6:aa1fc6a5cc2a 3760 scux_check_ch &= ~(1U << p_scux_info_ch->channel);
dkato 6:aa1fc6a5cc2a 3761 p_scux_info_ch->p_ssif_info3->scux_channel = (int_t)scux_check_ch;
dkato 6:aa1fc6a5cc2a 3762 p_scux_info_ch->p_ssif_info3->pin_mode = p_scux_info_ch->p_ssif_info3->pin_mode_backup;
dkato 6:aa1fc6a5cc2a 3763
dkato 6:aa1fc6a5cc2a 3764 switch (p_scux_info_ch->p_ssif_info3->ssif_cfg.ssif_ch_num)
dkato 6:aa1fc6a5cc2a 3765 {
dkato 6:aa1fc6a5cc2a 3766 case SCUX_SSIF_CH_1 :
dkato 6:aa1fc6a5cc2a 3767 ssipmd_mask_ssif3 = SSIPMD_CIM_SSI1PMD_MASK;
dkato 6:aa1fc6a5cc2a 3768 ssipmd_shift_ssif3 = SSIPMD_CIM_SSI1PMD_SHIFT;
dkato 6:aa1fc6a5cc2a 3769 break;
dkato 6:aa1fc6a5cc2a 3770
dkato 6:aa1fc6a5cc2a 3771 case SCUX_SSIF_CH_2 :
dkato 6:aa1fc6a5cc2a 3772 ssipmd_mask_ssif3 = SSIPMD_CIM_SSI2PMD_MASK;
dkato 6:aa1fc6a5cc2a 3773 ssipmd_shift_ssif3 = SSIPMD_CIM_SSI2PMD_SHIFT;
dkato 6:aa1fc6a5cc2a 3774 break;
dkato 6:aa1fc6a5cc2a 3775
dkato 6:aa1fc6a5cc2a 3776 case SCUX_SSIF_CH_3 :
dkato 6:aa1fc6a5cc2a 3777 ssipmd_mask_ssif3 = SSIPMD_CIM_SSI3PMD_MASK;
dkato 6:aa1fc6a5cc2a 3778 ssipmd_shift_ssif3 = SSIPMD_CIM_SSI3PMD_SHIFT;
dkato 6:aa1fc6a5cc2a 3779 break;
dkato 6:aa1fc6a5cc2a 3780
dkato 6:aa1fc6a5cc2a 3781 case SCUX_SSIF_CH_4 :
dkato 6:aa1fc6a5cc2a 3782 ssipmd_mask_ssif3 = SSIPMD_CIM_SSI4PMD_MASK;
dkato 6:aa1fc6a5cc2a 3783 ssipmd_shift_ssif3 = SSIPMD_CIM_SSI4PMD_SHIFT;
dkato 6:aa1fc6a5cc2a 3784 break;
dkato 6:aa1fc6a5cc2a 3785
dkato 6:aa1fc6a5cc2a 3786 case SCUX_SSIF_CH_5 :
dkato 6:aa1fc6a5cc2a 3787 ssipmd_mask_ssif3 = SSIPMD_CIM_SSI5PMD_MASK;
dkato 6:aa1fc6a5cc2a 3788 ssipmd_shift_ssif3 = SSIPMD_CIM_SSI5PMD_SHIFT;
dkato 6:aa1fc6a5cc2a 3789 break;
dkato 6:aa1fc6a5cc2a 3790
dkato 6:aa1fc6a5cc2a 3791 default :
dkato 6:aa1fc6a5cc2a 3792 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 3793 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 3794 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 3795 break;
dkato 6:aa1fc6a5cc2a 3796 }
dkato 6:aa1fc6a5cc2a 3797 ssipmd_reg = *(p_scux_info_ch->p_scux_reg->ssipmd_cim);
dkato 6:aa1fc6a5cc2a 3798 ssipmd_reg &= ~(ssipmd_mask_ssif2 | ssipmd_mask_ssif3);
dkato 6:aa1fc6a5cc2a 3799
dkato 6:aa1fc6a5cc2a 3800 /* ->IPA R2.4.1 Even if pinmode and ssipmd_shift are max value, omission dose not occur. */
dkato 6:aa1fc6a5cc2a 3801 *(p_scux_info_ch->p_scux_reg->ssipmd_cim) = (ssipmd_reg |
dkato 6:aa1fc6a5cc2a 3802 ((uint32_t)p_scux_info_ch->p_ssif_info2->pin_mode << ssipmd_shift_ssif2) |
dkato 6:aa1fc6a5cc2a 3803 ((uint32_t)p_scux_info_ch->p_ssif_info3->pin_mode << ssipmd_shift_ssif3));
dkato 6:aa1fc6a5cc2a 3804 /* <-IPA R2.4.1 */
dkato 6:aa1fc6a5cc2a 3805
dkato 6:aa1fc6a5cc2a 3806 if (0 == p_scux_info_ch->p_ssif_info2->scux_channel)
dkato 6:aa1fc6a5cc2a 3807 {
dkato 6:aa1fc6a5cc2a 3808 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 3809 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 3810 #else
dkato 6:aa1fc6a5cc2a 3811 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 3812 #endif
dkato 6:aa1fc6a5cc2a 3813
dkato 6:aa1fc6a5cc2a 3814 /* clock mask */
dkato 6:aa1fc6a5cc2a 3815 CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info2->ssif_cfg.ssif_ch_num]);
dkato 6:aa1fc6a5cc2a 3816
dkato 6:aa1fc6a5cc2a 3817 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 3818 {
dkato 6:aa1fc6a5cc2a 3819 __enable_irq();
dkato 6:aa1fc6a5cc2a 3820 }
dkato 6:aa1fc6a5cc2a 3821 }
dkato 6:aa1fc6a5cc2a 3822
dkato 6:aa1fc6a5cc2a 3823 if (0 == p_scux_info_ch->p_ssif_info3->scux_channel)
dkato 6:aa1fc6a5cc2a 3824 {
dkato 6:aa1fc6a5cc2a 3825 #if defined (__ICCARM__)
dkato 6:aa1fc6a5cc2a 3826 was_masked = __disable_irq_iar();
dkato 6:aa1fc6a5cc2a 3827 #else
dkato 6:aa1fc6a5cc2a 3828 was_masked = __disable_irq();
dkato 6:aa1fc6a5cc2a 3829 #endif
dkato 6:aa1fc6a5cc2a 3830
dkato 6:aa1fc6a5cc2a 3831 CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info3->ssif_cfg.ssif_ch_num]);
dkato 6:aa1fc6a5cc2a 3832
dkato 6:aa1fc6a5cc2a 3833 if (0 == was_masked)
dkato 6:aa1fc6a5cc2a 3834 {
dkato 6:aa1fc6a5cc2a 3835 __enable_irq();
dkato 6:aa1fc6a5cc2a 3836 }
dkato 6:aa1fc6a5cc2a 3837 }
dkato 6:aa1fc6a5cc2a 3838
dkato 6:aa1fc6a5cc2a 3839 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3840 {
dkato 6:aa1fc6a5cc2a 3841 /* set NULL to SSIF information when cancel not on going */
dkato 6:aa1fc6a5cc2a 3842 p_scux_info_ch->p_ssif_info2 = NULL;
dkato 6:aa1fc6a5cc2a 3843 p_scux_info_ch->p_ssif_info3 = NULL;
dkato 6:aa1fc6a5cc2a 3844 }
dkato 6:aa1fc6a5cc2a 3845 }
dkato 6:aa1fc6a5cc2a 3846 if (false == p_scux_info_ch->cancel_operate_flag)
dkato 6:aa1fc6a5cc2a 3847 {
dkato 6:aa1fc6a5cc2a 3848 /* set NULL to SSIF information when cancel not on going */
dkato 6:aa1fc6a5cc2a 3849 p_scux_info_ch->p_ssif_info1 = NULL;
dkato 6:aa1fc6a5cc2a 3850 }
dkato 6:aa1fc6a5cc2a 3851
dkato 6:aa1fc6a5cc2a 3852 if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
dkato 6:aa1fc6a5cc2a 3853 {
dkato 6:aa1fc6a5cc2a 3854 if (0U == p_info_drv->shared_info.mix_run_ch)
dkato 6:aa1fc6a5cc2a 3855 {
dkato 6:aa1fc6a5cc2a 3856 *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) |= MIXIR_MIX0_INIT_SET;
dkato 6:aa1fc6a5cc2a 3857 *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET;
dkato 6:aa1fc6a5cc2a 3858 }
dkato 6:aa1fc6a5cc2a 3859 }
dkato 6:aa1fc6a5cc2a 3860 }
dkato 6:aa1fc6a5cc2a 3861 }
dkato 6:aa1fc6a5cc2a 3862
dkato 6:aa1fc6a5cc2a 3863 return;
dkato 6:aa1fc6a5cc2a 3864 }
dkato 6:aa1fc6a5cc2a 3865
dkato 6:aa1fc6a5cc2a 3866 /******************************************************************************
dkato 6:aa1fc6a5cc2a 3867 End of function SCUX_AsyncStopHw
dkato 6:aa1fc6a5cc2a 3868 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 3869
dkato 6:aa1fc6a5cc2a 3870 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 3871 * Function Name: SCUX_SetDigiVolRegister
dkato 6:aa1fc6a5cc2a 3872 * @brief Set digital volume register.
dkato 6:aa1fc6a5cc2a 3873 *
dkato 6:aa1fc6a5cc2a 3874 * Description:<br>
dkato 6:aa1fc6a5cc2a 3875 *
dkato 6:aa1fc6a5cc2a 3876 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 3877 * @retval none.
dkato 6:aa1fc6a5cc2a 3878 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 3879
dkato 6:aa1fc6a5cc2a 3880 void SCUX_SetDigiVolRegister(const scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 3881 {
dkato 6:aa1fc6a5cc2a 3882 int_t audio_ch;
dkato 6:aa1fc6a5cc2a 3883
dkato 6:aa1fc6a5cc2a 3884 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 3885 {
dkato 6:aa1fc6a5cc2a 3886 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 3887 }
dkato 6:aa1fc6a5cc2a 3888 else
dkato 6:aa1fc6a5cc2a 3889 {
dkato 6:aa1fc6a5cc2a 3890 /* check and set digital volume */
dkato 6:aa1fc6a5cc2a 3891 if (false != p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable)
dkato 6:aa1fc6a5cc2a 3892 {
dkato 6:aa1fc6a5cc2a 3893 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_VVMD_SET;
dkato 6:aa1fc6a5cc2a 3894
dkato 6:aa1fc6a5cc2a 3895 for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
dkato 6:aa1fc6a5cc2a 3896 {
dkato 6:aa1fc6a5cc2a 3897 switch (audio_ch)
dkato 6:aa1fc6a5cc2a 3898 {
dkato 6:aa1fc6a5cc2a 3899 case SCUX_AUDIO_CH_0 :
dkato 6:aa1fc6a5cc2a 3900 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
dkato 6:aa1fc6a5cc2a 3901 break;
dkato 6:aa1fc6a5cc2a 3902
dkato 6:aa1fc6a5cc2a 3903 case SCUX_AUDIO_CH_1 :
dkato 6:aa1fc6a5cc2a 3904 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
dkato 6:aa1fc6a5cc2a 3905 break;
dkato 6:aa1fc6a5cc2a 3906
dkato 6:aa1fc6a5cc2a 3907 case SCUX_AUDIO_CH_2 :
dkato 6:aa1fc6a5cc2a 3908 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
dkato 6:aa1fc6a5cc2a 3909 break;
dkato 6:aa1fc6a5cc2a 3910
dkato 6:aa1fc6a5cc2a 3911 case SCUX_AUDIO_CH_3 :
dkato 6:aa1fc6a5cc2a 3912 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
dkato 6:aa1fc6a5cc2a 3913 break;
dkato 6:aa1fc6a5cc2a 3914
dkato 6:aa1fc6a5cc2a 3915 case SCUX_AUDIO_CH_4 :
dkato 6:aa1fc6a5cc2a 3916 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
dkato 6:aa1fc6a5cc2a 3917 break;
dkato 6:aa1fc6a5cc2a 3918
dkato 6:aa1fc6a5cc2a 3919 case SCUX_AUDIO_CH_5 :
dkato 6:aa1fc6a5cc2a 3920 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
dkato 6:aa1fc6a5cc2a 3921 break;
dkato 6:aa1fc6a5cc2a 3922
dkato 6:aa1fc6a5cc2a 3923 case SCUX_AUDIO_CH_6 :
dkato 6:aa1fc6a5cc2a 3924 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
dkato 6:aa1fc6a5cc2a 3925 break;
dkato 6:aa1fc6a5cc2a 3926
dkato 6:aa1fc6a5cc2a 3927 case SCUX_AUDIO_CH_7 :
dkato 6:aa1fc6a5cc2a 3928 p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
dkato 6:aa1fc6a5cc2a 3929 break;
dkato 6:aa1fc6a5cc2a 3930
dkato 6:aa1fc6a5cc2a 3931 default :
dkato 6:aa1fc6a5cc2a 3932 /* ->IPA R3.5.2 Nothing is being processed intentionally. */
dkato 6:aa1fc6a5cc2a 3933 /* <-IPA R3.5.2 */
dkato 6:aa1fc6a5cc2a 3934 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 3935 break;
dkato 6:aa1fc6a5cc2a 3936 }
dkato 6:aa1fc6a5cc2a 3937 }
dkato 6:aa1fc6a5cc2a 3938 }
dkato 6:aa1fc6a5cc2a 3939 else
dkato 6:aa1fc6a5cc2a 3940 {
dkato 6:aa1fc6a5cc2a 3941 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 &= ~DVUCR_DVU0_VVMD_SET;
dkato 6:aa1fc6a5cc2a 3942 }
dkato 6:aa1fc6a5cc2a 3943 }
dkato 6:aa1fc6a5cc2a 3944
dkato 6:aa1fc6a5cc2a 3945 return;
dkato 6:aa1fc6a5cc2a 3946 }
dkato 6:aa1fc6a5cc2a 3947
dkato 6:aa1fc6a5cc2a 3948 /******************************************************************************
dkato 6:aa1fc6a5cc2a 3949 End of function SCUX_SetDigiVolRegister
dkato 6:aa1fc6a5cc2a 3950 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 3951
dkato 6:aa1fc6a5cc2a 3952 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 3953 * Function Name: SCUX_SetRampVolRegister
dkato 6:aa1fc6a5cc2a 3954 * @brief Set ramp volume register.
dkato 6:aa1fc6a5cc2a 3955 *
dkato 6:aa1fc6a5cc2a 3956 * Description:<br>
dkato 6:aa1fc6a5cc2a 3957 *
dkato 6:aa1fc6a5cc2a 3958 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 3959 * @retval none.
dkato 6:aa1fc6a5cc2a 3960 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 3961
dkato 6:aa1fc6a5cc2a 3962 void SCUX_SetRampVolRegister(scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 3963 {
dkato 6:aa1fc6a5cc2a 3964 int_t audio_ch;
dkato 6:aa1fc6a5cc2a 3965 uint32_t vrctr_value = 0;
dkato 6:aa1fc6a5cc2a 3966
dkato 6:aa1fc6a5cc2a 3967 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 3968 {
dkato 6:aa1fc6a5cc2a 3969 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 3970 }
dkato 6:aa1fc6a5cc2a 3971 else
dkato 6:aa1fc6a5cc2a 3972 {
dkato 6:aa1fc6a5cc2a 3973 for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
dkato 6:aa1fc6a5cc2a 3974 {
dkato 6:aa1fc6a5cc2a 3975 if (false != p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch])
dkato 6:aa1fc6a5cc2a 3976 {
dkato 6:aa1fc6a5cc2a 3977 vrctr_value |= (VRCTR_DVU0_VREN_SET << audio_ch);
dkato 6:aa1fc6a5cc2a 3978 }
dkato 6:aa1fc6a5cc2a 3979 else
dkato 6:aa1fc6a5cc2a 3980 {
dkato 6:aa1fc6a5cc2a 3981 vrctr_value &= ~(VRCTR_DVU0_VREN_SET << audio_ch);
dkato 6:aa1fc6a5cc2a 3982 }
dkato 6:aa1fc6a5cc2a 3983 }
dkato 6:aa1fc6a5cc2a 3984
dkato 6:aa1fc6a5cc2a 3985 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = vrctr_value;
dkato 6:aa1fc6a5cc2a 3986
dkato 6:aa1fc6a5cc2a 3987 if (false == p_scux_info_ch->restart_ramp_flag)
dkato 6:aa1fc6a5cc2a 3988 {
dkato 6:aa1fc6a5cc2a 3989 /* set ramp paramteter to register when timming isn't restart after cancel */
dkato 6:aa1fc6a5cc2a 3990 /* ->IPA R2.4.1 Even if each parameters are max value, omission dose not occur. */
dkato 6:aa1fc6a5cc2a 3991 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = (uint32_t)((((uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period << VRPDR_DVU0_VRPDUP_SHIFT) & VRPDR_DVU0_VRPDUP_MASK) |
dkato 6:aa1fc6a5cc2a 3992 (((uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period << VRPDR_DVU0_VRPDDW_SHIFT) & VRPDR_DVU0_VRPDDW_MASK));
dkato 6:aa1fc6a5cc2a 3993 /* <-IPA R2.4.1 */
dkato 6:aa1fc6a5cc2a 3994 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time & VRWTR_DVU0_VRWT_MASK);
dkato 6:aa1fc6a5cc2a 3995 }
dkato 6:aa1fc6a5cc2a 3996 else
dkato 6:aa1fc6a5cc2a 3997 {
dkato 6:aa1fc6a5cc2a 3998 /* set fatest ramp parameter to register when timming is restart after cancel */
dkato 6:aa1fc6a5cc2a 3999 /* ->IPA R2.4.1 Even if each parameters are max value, omission dose not occur. */
dkato 6:aa1fc6a5cc2a 4000 /* when restart ,volume is changed immedeatly */
dkato 6:aa1fc6a5cc2a 4001 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = (uint32_t)((((uint32_t)SCUX_DVU_TIME_128DB_1STEP << VRPDR_DVU0_VRPDUP_SHIFT) & VRPDR_DVU0_VRPDUP_MASK) |
dkato 6:aa1fc6a5cc2a 4002 (((uint32_t)SCUX_DVU_TIME_128DB_1STEP << VRPDR_DVU0_VRPDDW_SHIFT) & VRPDR_DVU0_VRPDDW_MASK));
dkato 6:aa1fc6a5cc2a 4003 /* <-IPA R2.4.1 */
dkato 6:aa1fc6a5cc2a 4004 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = 0U;
dkato 6:aa1fc6a5cc2a 4005 p_scux_info_ch->restart_ramp_flag = false;
dkato 6:aa1fc6a5cc2a 4006 }
dkato 6:aa1fc6a5cc2a 4007 p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol;
dkato 6:aa1fc6a5cc2a 4008 }
dkato 6:aa1fc6a5cc2a 4009
dkato 6:aa1fc6a5cc2a 4010 return;
dkato 6:aa1fc6a5cc2a 4011 }
dkato 6:aa1fc6a5cc2a 4012
dkato 6:aa1fc6a5cc2a 4013 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4014 End of function SCUX_SetRampVolRegister
dkato 6:aa1fc6a5cc2a 4015 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4016
dkato 6:aa1fc6a5cc2a 4017 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 4018 * Function Name: SCUX_SetZerocrossMuteRegister
dkato 6:aa1fc6a5cc2a 4019 * @brief Set zerocross mute register.
dkato 6:aa1fc6a5cc2a 4020 *
dkato 6:aa1fc6a5cc2a 4021 * Description:<br>
dkato 6:aa1fc6a5cc2a 4022 *
dkato 6:aa1fc6a5cc2a 4023 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 4024 * @retval None.
dkato 6:aa1fc6a5cc2a 4025 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4026
dkato 6:aa1fc6a5cc2a 4027 void SCUX_SetZerocrossMuteRegister(const scux_info_ch_t * const p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 4028 {
dkato 6:aa1fc6a5cc2a 4029 int_t audio_ch;
dkato 6:aa1fc6a5cc2a 4030 uint32_t zcmcr_value = 0;
dkato 6:aa1fc6a5cc2a 4031 uint32_t vevmr_value = 0;
dkato 6:aa1fc6a5cc2a 4032
dkato 6:aa1fc6a5cc2a 4033 if (NULL == p_scux_info_ch)
dkato 6:aa1fc6a5cc2a 4034 {
dkato 6:aa1fc6a5cc2a 4035 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4036 }
dkato 6:aa1fc6a5cc2a 4037 else
dkato 6:aa1fc6a5cc2a 4038 {
dkato 6:aa1fc6a5cc2a 4039 for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
dkato 6:aa1fc6a5cc2a 4040 {
dkato 6:aa1fc6a5cc2a 4041 if (false != p_scux_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch])
dkato 6:aa1fc6a5cc2a 4042 {
dkato 6:aa1fc6a5cc2a 4043 zcmcr_value |= (ZCMCR_DVU0_ZCEN_SET << audio_ch);
dkato 6:aa1fc6a5cc2a 4044 vevmr_value |= (VEVMR_DVU0_VEVMZCM_SET << audio_ch);
dkato 6:aa1fc6a5cc2a 4045 }
dkato 6:aa1fc6a5cc2a 4046 else
dkato 6:aa1fc6a5cc2a 4047 {
dkato 6:aa1fc6a5cc2a 4048 zcmcr_value &= ~(ZCMCR_DVU0_ZCEN_SET << audio_ch);
dkato 6:aa1fc6a5cc2a 4049 vevmr_value &= ~(VEVMR_DVU0_VEVMZCM_SET << audio_ch);
dkato 6:aa1fc6a5cc2a 4050 }
dkato 6:aa1fc6a5cc2a 4051 }
dkato 6:aa1fc6a5cc2a 4052 p_scux_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = zcmcr_value;
dkato 6:aa1fc6a5cc2a 4053 p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = vevmr_value;
dkato 6:aa1fc6a5cc2a 4054
dkato 6:aa1fc6a5cc2a 4055 if (0U != zcmcr_value)
dkato 6:aa1fc6a5cc2a 4056 {
dkato 6:aa1fc6a5cc2a 4057 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_ZCMD_SET;
dkato 6:aa1fc6a5cc2a 4058 }
dkato 6:aa1fc6a5cc2a 4059 else
dkato 6:aa1fc6a5cc2a 4060 {
dkato 6:aa1fc6a5cc2a 4061 p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 &= ~DVUCR_DVU0_ZCMD_SET;
dkato 6:aa1fc6a5cc2a 4062 }
dkato 6:aa1fc6a5cc2a 4063
dkato 6:aa1fc6a5cc2a 4064 }
dkato 6:aa1fc6a5cc2a 4065
dkato 6:aa1fc6a5cc2a 4066 return;
dkato 6:aa1fc6a5cc2a 4067 }
dkato 6:aa1fc6a5cc2a 4068
dkato 6:aa1fc6a5cc2a 4069 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4070 End of function SCUX_SetZerocrossMuteRegister
dkato 6:aa1fc6a5cc2a 4071 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4072
dkato 6:aa1fc6a5cc2a 4073 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 4074 * Function Name: SCUX_SetMixVolRegister
dkato 6:aa1fc6a5cc2a 4075 * @brief Set MIX volume register.
dkato 6:aa1fc6a5cc2a 4076 *
dkato 6:aa1fc6a5cc2a 4077 * Description:<br>
dkato 6:aa1fc6a5cc2a 4078 *
dkato 6:aa1fc6a5cc2a 4079 * @param[in] channel : SCUX channel number.
dkato 6:aa1fc6a5cc2a 4080 * @retval None.
dkato 6:aa1fc6a5cc2a 4081 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4082
dkato 6:aa1fc6a5cc2a 4083 void SCUX_SetMixVolRegister(const int_t channel)
dkato 6:aa1fc6a5cc2a 4084 {
dkato 6:aa1fc6a5cc2a 4085 scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
dkato 6:aa1fc6a5cc2a 4086 scux_info_ch_t * const p_scux_info_ch = SCUX_GetDrvChInfo(channel);
dkato 6:aa1fc6a5cc2a 4087
dkato 6:aa1fc6a5cc2a 4088 if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
dkato 6:aa1fc6a5cc2a 4089 {
dkato 6:aa1fc6a5cc2a 4090 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4091 }
dkato 6:aa1fc6a5cc2a 4092 else
dkato 6:aa1fc6a5cc2a 4093 {
dkato 6:aa1fc6a5cc2a 4094 *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET;
dkato 6:aa1fc6a5cc2a 4095 *(p_scux_info_ch->p_scux_reg->mdb_n_r_mix0_0) = p_info_drv->shared_info.mix_vol[channel];
dkato 6:aa1fc6a5cc2a 4096 *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) |= MDBER_MIX0_MIXDBEN_SET;
dkato 6:aa1fc6a5cc2a 4097 }
dkato 6:aa1fc6a5cc2a 4098
dkato 6:aa1fc6a5cc2a 4099 return;
dkato 6:aa1fc6a5cc2a 4100 }
dkato 6:aa1fc6a5cc2a 4101
dkato 6:aa1fc6a5cc2a 4102 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4103 End of function SCUX_SetMixVolRegister
dkato 6:aa1fc6a5cc2a 4104 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4105
dkato 6:aa1fc6a5cc2a 4106 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 4107 * Function Name: SCUX_DMA_RxCallBack
dkato 6:aa1fc6a5cc2a 4108 * @brief Read request callback (mem to mem).
dkato 6:aa1fc6a5cc2a 4109 *
dkato 6:aa1fc6a5cc2a 4110 * Description:<br>
dkato 6:aa1fc6a5cc2a 4111 *
dkato 6:aa1fc6a5cc2a 4112 * @param[in] param : SCUX channel number.
dkato 6:aa1fc6a5cc2a 4113 * @retval None.
dkato 6:aa1fc6a5cc2a 4114 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4115
dkato 6:aa1fc6a5cc2a 4116 static void SCUX_DMA_CopyRxCallBack(union sigval const param)
dkato 6:aa1fc6a5cc2a 4117 {
dkato 6:aa1fc6a5cc2a 4118 dma_trans_data_t dma_address_param;
dkato 6:aa1fc6a5cc2a 4119 int_t retval;
dkato 6:aa1fc6a5cc2a 4120 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int);
dkato 6:aa1fc6a5cc2a 4121
dkato 6:aa1fc6a5cc2a 4122 if (NULL == p_info_ch)
dkato 6:aa1fc6a5cc2a 4123 {
dkato 6:aa1fc6a5cc2a 4124 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4125 }
dkato 6:aa1fc6a5cc2a 4126 else
dkato 6:aa1fc6a5cc2a 4127 {
dkato 6:aa1fc6a5cc2a 4128 if (NULL != p_info_ch->p_rx_aio)
dkato 6:aa1fc6a5cc2a 4129 {
dkato 6:aa1fc6a5cc2a 4130 p_info_ch->p_rx_aio->aio_return = (ssize_t)p_info_ch->p_rx_aio->aio_nbytes;
dkato 6:aa1fc6a5cc2a 4131 ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio);
dkato 6:aa1fc6a5cc2a 4132 p_info_ch->first_rx_flag = false;
dkato 6:aa1fc6a5cc2a 4133 }
dkato 6:aa1fc6a5cc2a 4134
dkato 6:aa1fc6a5cc2a 4135 p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size;
dkato 6:aa1fc6a5cc2a 4136 p_info_ch->dma_rx_current_size = 0;
dkato 6:aa1fc6a5cc2a 4137 p_info_ch->p_rx_aio = ahf_removehead(&p_info_ch->rx_que);
dkato 6:aa1fc6a5cc2a 4138
dkato 6:aa1fc6a5cc2a 4139 if (NULL != p_info_ch->p_rx_aio)
dkato 6:aa1fc6a5cc2a 4140 {
dkato 6:aa1fc6a5cc2a 4141 /* set nect data read */
dkato 6:aa1fc6a5cc2a 4142 dma_address_param.src_addr = (void *)p_info_ch->p_scux_reg->dmatu_n_cim;
dkato 6:aa1fc6a5cc2a 4143 dma_address_param.dst_addr = (void *)(p_info_ch->p_rx_aio->aio_buf);
dkato 6:aa1fc6a5cc2a 4144 dma_address_param.count = p_info_ch->p_rx_aio->aio_nbytes;
dkato 6:aa1fc6a5cc2a 4145
dkato 6:aa1fc6a5cc2a 4146 retval = R_DMA_Start(p_info_ch->dma_rx_ch, &dma_address_param, NULL);
dkato 6:aa1fc6a5cc2a 4147 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 4148 {
dkato 6:aa1fc6a5cc2a 4149 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4150 }
dkato 6:aa1fc6a5cc2a 4151 else
dkato 6:aa1fc6a5cc2a 4152 {
dkato 6:aa1fc6a5cc2a 4153 p_info_ch->dma_rx_current_size = dma_address_param.count;
dkato 6:aa1fc6a5cc2a 4154 }
dkato 6:aa1fc6a5cc2a 4155 }
dkato 6:aa1fc6a5cc2a 4156 else
dkato 6:aa1fc6a5cc2a 4157 {
dkato 6:aa1fc6a5cc2a 4158 switch (p_info_ch->ch_stat)
dkato 6:aa1fc6a5cc2a 4159 {
dkato 6:aa1fc6a5cc2a 4160 case SCUX_CH_UNINIT :
dkato 6:aa1fc6a5cc2a 4161 /* fall through */
dkato 6:aa1fc6a5cc2a 4162 case SCUX_CH_INIT :
dkato 6:aa1fc6a5cc2a 4163 /* fall through */
dkato 6:aa1fc6a5cc2a 4164 case SCUX_CH_STOP :
dkato 6:aa1fc6a5cc2a 4165 /* fall through */
dkato 6:aa1fc6a5cc2a 4166 case SCUX_CH_TRANS_IDLE :
dkato 6:aa1fc6a5cc2a 4167 /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 4168 break;
dkato 6:aa1fc6a5cc2a 4169
dkato 6:aa1fc6a5cc2a 4170 case SCUX_CH_TRANS_RD :
dkato 6:aa1fc6a5cc2a 4171 p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
dkato 6:aa1fc6a5cc2a 4172 break;
dkato 6:aa1fc6a5cc2a 4173
dkato 6:aa1fc6a5cc2a 4174 case SCUX_CH_TRANS_WR :
dkato 6:aa1fc6a5cc2a 4175 /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 4176 break;
dkato 6:aa1fc6a5cc2a 4177
dkato 6:aa1fc6a5cc2a 4178 case SCUX_CH_TRANS_RDWR :
dkato 6:aa1fc6a5cc2a 4179 p_info_ch->ch_stat = SCUX_CH_TRANS_WR;
dkato 6:aa1fc6a5cc2a 4180 break;
dkato 6:aa1fc6a5cc2a 4181
dkato 6:aa1fc6a5cc2a 4182 case SCUX_CH_STOP_WAIT :
dkato 6:aa1fc6a5cc2a 4183 p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE;
dkato 6:aa1fc6a5cc2a 4184 break;
dkato 6:aa1fc6a5cc2a 4185
dkato 6:aa1fc6a5cc2a 4186 case SCUX_CH_STOP_WAIT_IDLE :
dkato 6:aa1fc6a5cc2a 4187 /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 4188 break;
dkato 6:aa1fc6a5cc2a 4189
dkato 6:aa1fc6a5cc2a 4190 default :
dkato 6:aa1fc6a5cc2a 4191 /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 4192 break;
dkato 6:aa1fc6a5cc2a 4193 }
dkato 6:aa1fc6a5cc2a 4194 }
dkato 6:aa1fc6a5cc2a 4195 }
dkato 6:aa1fc6a5cc2a 4196 }
dkato 6:aa1fc6a5cc2a 4197
dkato 6:aa1fc6a5cc2a 4198 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4199 End of function SCUX_DMA_CopyRxCallBack
dkato 6:aa1fc6a5cc2a 4200 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4201
dkato 6:aa1fc6a5cc2a 4202 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 4203 * Function Name: SCUX_DMA_CommonTxNextDummyData
dkato 6:aa1fc6a5cc2a 4204 * @brief Set next dummy data for flush (mem to mem , SSIF direct route).
dkato 6:aa1fc6a5cc2a 4205 *
dkato 6:aa1fc6a5cc2a 4206 * Description:<br>
dkato 6:aa1fc6a5cc2a 4207 *
dkato 6:aa1fc6a5cc2a 4208 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 4209 * @retval None.
dkato 6:aa1fc6a5cc2a 4210 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4211
dkato 6:aa1fc6a5cc2a 4212 static void SCUX_DMA_CommonTxNextDummyData(scux_info_ch_t * const p_info_ch)
dkato 6:aa1fc6a5cc2a 4213 {
dkato 6:aa1fc6a5cc2a 4214 int_t retval;
dkato 6:aa1fc6a5cc2a 4215
dkato 6:aa1fc6a5cc2a 4216 if (NULL == p_info_ch)
dkato 6:aa1fc6a5cc2a 4217 {
dkato 6:aa1fc6a5cc2a 4218 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4219 }
dkato 6:aa1fc6a5cc2a 4220 else
dkato 6:aa1fc6a5cc2a 4221 {
dkato 6:aa1fc6a5cc2a 4222 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
dkato 6:aa1fc6a5cc2a 4223 p_info_ch->dma_tx_current_size = 0;
dkato 6:aa1fc6a5cc2a 4224
dkato 6:aa1fc6a5cc2a 4225 retval = SCUX_FlushWriteStart(p_info_ch);
dkato 6:aa1fc6a5cc2a 4226 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 4227 {
dkato 6:aa1fc6a5cc2a 4228 /* NON_NOTICE_ASSERT: DMA operation failed */
dkato 6:aa1fc6a5cc2a 4229 }
dkato 6:aa1fc6a5cc2a 4230 }
dkato 6:aa1fc6a5cc2a 4231 }
dkato 6:aa1fc6a5cc2a 4232
dkato 6:aa1fc6a5cc2a 4233 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4234 End of function SCUX_DMA_CommonTxNextDummyData
dkato 6:aa1fc6a5cc2a 4235 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4236
dkato 6:aa1fc6a5cc2a 4237 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 4238 * Function Name: SCUX_DMA_CopyTxEndFlush
dkato 6:aa1fc6a5cc2a 4239 * @brief End of flush operation (mem to mem route).
dkato 6:aa1fc6a5cc2a 4240 *
dkato 6:aa1fc6a5cc2a 4241 * Description:<br>
dkato 6:aa1fc6a5cc2a 4242 *
dkato 6:aa1fc6a5cc2a 4243 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 4244 * @retval None.
dkato 6:aa1fc6a5cc2a 4245 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4246
dkato 6:aa1fc6a5cc2a 4247 static void SCUX_DMA_CopyTxEndFlush(scux_info_ch_t * const p_info_ch)
dkato 6:aa1fc6a5cc2a 4248 {
dkato 6:aa1fc6a5cc2a 4249 int_t retval;
dkato 6:aa1fc6a5cc2a 4250 int_t dma_ercd;
dkato 6:aa1fc6a5cc2a 4251 uint32_t tx_remain_size = 0;
dkato 6:aa1fc6a5cc2a 4252 uint32_t rx_remain_size = 0;
dkato 6:aa1fc6a5cc2a 4253
dkato 6:aa1fc6a5cc2a 4254 if (NULL == p_info_ch)
dkato 6:aa1fc6a5cc2a 4255 {
dkato 6:aa1fc6a5cc2a 4256 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4257 }
dkato 6:aa1fc6a5cc2a 4258 else
dkato 6:aa1fc6a5cc2a 4259 {
dkato 6:aa1fc6a5cc2a 4260 /* finish send dummy data process, and SCUX stop process */
dkato 6:aa1fc6a5cc2a 4261 retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
dkato 6:aa1fc6a5cc2a 4262 /* It isn't an error even if error code is EBADF, because it is already stopped. */
dkato 6:aa1fc6a5cc2a 4263 if ((ESUCCESS != retval) && (EBADF != dma_ercd))
dkato 6:aa1fc6a5cc2a 4264 {
dkato 6:aa1fc6a5cc2a 4265 /* NON_NOTICE_ASSERT: DMA operation failed */
dkato 6:aa1fc6a5cc2a 4266 }
dkato 6:aa1fc6a5cc2a 4267
dkato 6:aa1fc6a5cc2a 4268 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
dkato 6:aa1fc6a5cc2a 4269 p_info_ch->dma_tx_current_size = 0;
dkato 6:aa1fc6a5cc2a 4270
dkato 6:aa1fc6a5cc2a 4271 retval = R_DMA_Cancel(p_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd);
dkato 6:aa1fc6a5cc2a 4272 /* It isn't an error even if error code is EBADF, because it is already stopped. */
dkato 6:aa1fc6a5cc2a 4273 if ((ESUCCESS != retval) && (EBADF != dma_ercd))
dkato 6:aa1fc6a5cc2a 4274 {
dkato 6:aa1fc6a5cc2a 4275 /* NON_NOTICE_ASSERT: DMA operation failed */
dkato 6:aa1fc6a5cc2a 4276 }
dkato 6:aa1fc6a5cc2a 4277 else
dkato 6:aa1fc6a5cc2a 4278 {
dkato 6:aa1fc6a5cc2a 4279 retval = R_DMA_Free(p_info_ch->dma_rx_ch, NULL);
dkato 6:aa1fc6a5cc2a 4280 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 4281 {
dkato 6:aa1fc6a5cc2a 4282 /* NON_NOTICE_ASSERT: DMA operation failed */
dkato 6:aa1fc6a5cc2a 4283 }
dkato 6:aa1fc6a5cc2a 4284 }
dkato 6:aa1fc6a5cc2a 4285 p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size;
dkato 6:aa1fc6a5cc2a 4286 p_info_ch->dma_rx_current_size = 0;
dkato 6:aa1fc6a5cc2a 4287
dkato 6:aa1fc6a5cc2a 4288 if (NULL != p_info_ch->p_rx_aio)
dkato 6:aa1fc6a5cc2a 4289 {
dkato 6:aa1fc6a5cc2a 4290 /* in case NULL, dummy data read */
dkato 6:aa1fc6a5cc2a 4291 p_info_ch->p_rx_aio->aio_return = (ssize_t)(p_info_ch->p_rx_aio->aio_nbytes - rx_remain_size);
dkato 6:aa1fc6a5cc2a 4292 ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio);
dkato 6:aa1fc6a5cc2a 4293 }
dkato 6:aa1fc6a5cc2a 4294 ahf_cancelall(&p_info_ch->rx_que);
dkato 6:aa1fc6a5cc2a 4295 p_info_ch->p_rx_aio = NULL;
dkato 6:aa1fc6a5cc2a 4296
dkato 6:aa1fc6a5cc2a 4297 SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, rx_remain_size);
dkato 6:aa1fc6a5cc2a 4298
dkato 6:aa1fc6a5cc2a 4299 if (false != p_info_ch->src_cfg.mode_sync)
dkato 6:aa1fc6a5cc2a 4300 {
dkato 6:aa1fc6a5cc2a 4301 SCUX_SyncStopHw(p_info_ch);
dkato 6:aa1fc6a5cc2a 4302 }
dkato 6:aa1fc6a5cc2a 4303 else
dkato 6:aa1fc6a5cc2a 4304 {
dkato 6:aa1fc6a5cc2a 4305 SCUX_AsyncStopHw(p_info_ch);
dkato 6:aa1fc6a5cc2a 4306 }
dkato 6:aa1fc6a5cc2a 4307
dkato 6:aa1fc6a5cc2a 4308 p_info_ch->ch_stat = SCUX_CH_STOP;
dkato 6:aa1fc6a5cc2a 4309 if (NULL != p_info_ch->p_flush_callback)
dkato 6:aa1fc6a5cc2a 4310 {
dkato 6:aa1fc6a5cc2a 4311 p_info_ch->p_flush_callback(ESUCCESS);
dkato 6:aa1fc6a5cc2a 4312 }
dkato 6:aa1fc6a5cc2a 4313 }
dkato 6:aa1fc6a5cc2a 4314 }
dkato 6:aa1fc6a5cc2a 4315
dkato 6:aa1fc6a5cc2a 4316 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4317 End of function SCUX_DMA_CopyTxEndFlush
dkato 6:aa1fc6a5cc2a 4318 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4319
dkato 6:aa1fc6a5cc2a 4320 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 4321 * Function Name: SCUX_DMA_CopyTxNextRemainData
dkato 6:aa1fc6a5cc2a 4322 * @brief Set next remain data for flush (mem to mem route).
dkato 6:aa1fc6a5cc2a 4323 *
dkato 6:aa1fc6a5cc2a 4324 * Description:<br>
dkato 6:aa1fc6a5cc2a 4325 *
dkato 6:aa1fc6a5cc2a 4326 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 4327 * @retval None.
dkato 6:aa1fc6a5cc2a 4328 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4329
dkato 6:aa1fc6a5cc2a 4330 static void SCUX_DMA_CopyTxNextRemainData(scux_info_ch_t * const p_info_ch)
dkato 6:aa1fc6a5cc2a 4331 {
dkato 6:aa1fc6a5cc2a 4332 dma_trans_data_t dma_address_param;
dkato 6:aa1fc6a5cc2a 4333 int_t retval;
dkato 6:aa1fc6a5cc2a 4334
dkato 6:aa1fc6a5cc2a 4335 if (NULL == p_info_ch)
dkato 6:aa1fc6a5cc2a 4336 {
dkato 6:aa1fc6a5cc2a 4337 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4338 }
dkato 6:aa1fc6a5cc2a 4339 else
dkato 6:aa1fc6a5cc2a 4340 {
dkato 6:aa1fc6a5cc2a 4341 /* send remain tx data prcess for flush */
dkato 6:aa1fc6a5cc2a 4342 if (NULL != p_info_ch->p_tx_aio)
dkato 6:aa1fc6a5cc2a 4343 {
dkato 6:aa1fc6a5cc2a 4344 p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
dkato 6:aa1fc6a5cc2a 4345 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
dkato 6:aa1fc6a5cc2a 4346 }
dkato 6:aa1fc6a5cc2a 4347
dkato 6:aa1fc6a5cc2a 4348 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
dkato 6:aa1fc6a5cc2a 4349 p_info_ch->dma_tx_current_size = 0;
dkato 6:aa1fc6a5cc2a 4350 p_info_ch->p_tx_aio = ahf_removehead(&p_info_ch->tx_que);
dkato 6:aa1fc6a5cc2a 4351
dkato 6:aa1fc6a5cc2a 4352 if (NULL == p_info_ch->p_tx_aio)
dkato 6:aa1fc6a5cc2a 4353 {
dkato 6:aa1fc6a5cc2a 4354 retval = SCUX_FlushWriteStart(p_info_ch);
dkato 6:aa1fc6a5cc2a 4355 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 4356 {
dkato 6:aa1fc6a5cc2a 4357 /* NON_NOTICE_ASSERT: DMA operation failed */
dkato 6:aa1fc6a5cc2a 4358 }
dkato 6:aa1fc6a5cc2a 4359 }
dkato 6:aa1fc6a5cc2a 4360 else
dkato 6:aa1fc6a5cc2a 4361 {
dkato 6:aa1fc6a5cc2a 4362 dma_address_param.src_addr = (void *)(p_info_ch->p_tx_aio->aio_buf);
dkato 6:aa1fc6a5cc2a 4363 dma_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
dkato 6:aa1fc6a5cc2a 4364 dma_address_param.count = p_info_ch->p_tx_aio->aio_nbytes;
dkato 6:aa1fc6a5cc2a 4365
dkato 6:aa1fc6a5cc2a 4366 retval = R_DMA_Start(p_info_ch->dma_tx_ch, &dma_address_param, NULL);
dkato 6:aa1fc6a5cc2a 4367 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 4368 {
dkato 6:aa1fc6a5cc2a 4369 /* NON_NOTICE_ASSERT: DMA operation failed */
dkato 6:aa1fc6a5cc2a 4370 }
dkato 6:aa1fc6a5cc2a 4371 else
dkato 6:aa1fc6a5cc2a 4372 {
dkato 6:aa1fc6a5cc2a 4373 p_info_ch->dma_tx_current_size = dma_address_param.count;
dkato 6:aa1fc6a5cc2a 4374 }
dkato 6:aa1fc6a5cc2a 4375 }
dkato 6:aa1fc6a5cc2a 4376 }
dkato 6:aa1fc6a5cc2a 4377 }
dkato 6:aa1fc6a5cc2a 4378
dkato 6:aa1fc6a5cc2a 4379 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4380 End of function SCUX_DMA_CopyTxNextRemainData
dkato 6:aa1fc6a5cc2a 4381 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4382
dkato 6:aa1fc6a5cc2a 4383 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 4384 * Function Name: SCUX_DMA_CopyTxNextData
dkato 6:aa1fc6a5cc2a 4385 * @brief Set next data for normal operation (mem to mem route).
dkato 6:aa1fc6a5cc2a 4386 *
dkato 6:aa1fc6a5cc2a 4387 * Description:<br>
dkato 6:aa1fc6a5cc2a 4388 *
dkato 6:aa1fc6a5cc2a 4389 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 4390 * @retval None.
dkato 6:aa1fc6a5cc2a 4391 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4392
dkato 6:aa1fc6a5cc2a 4393 static void SCUX_DMA_CopyTxNextData(scux_info_ch_t * const p_info_ch)
dkato 6:aa1fc6a5cc2a 4394 {
dkato 6:aa1fc6a5cc2a 4395 dma_trans_data_t dma_address_param;
dkato 6:aa1fc6a5cc2a 4396 int_t retval;
dkato 6:aa1fc6a5cc2a 4397
dkato 6:aa1fc6a5cc2a 4398 if (NULL == p_info_ch)
dkato 6:aa1fc6a5cc2a 4399 {
dkato 6:aa1fc6a5cc2a 4400 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4401 }
dkato 6:aa1fc6a5cc2a 4402 else
dkato 6:aa1fc6a5cc2a 4403 {
dkato 6:aa1fc6a5cc2a 4404 /* normal send process */
dkato 6:aa1fc6a5cc2a 4405 if (NULL != p_info_ch->p_tx_aio)
dkato 6:aa1fc6a5cc2a 4406 {
dkato 6:aa1fc6a5cc2a 4407 p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
dkato 6:aa1fc6a5cc2a 4408 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
dkato 6:aa1fc6a5cc2a 4409 }
dkato 6:aa1fc6a5cc2a 4410
dkato 6:aa1fc6a5cc2a 4411 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
dkato 6:aa1fc6a5cc2a 4412 p_info_ch->dma_tx_current_size = 0;
dkato 6:aa1fc6a5cc2a 4413 p_info_ch->p_tx_aio = ahf_removehead(&p_info_ch->tx_que);
dkato 6:aa1fc6a5cc2a 4414
dkato 6:aa1fc6a5cc2a 4415 if (NULL != p_info_ch->p_tx_aio)
dkato 6:aa1fc6a5cc2a 4416 {
dkato 6:aa1fc6a5cc2a 4417 dma_address_param.src_addr = (void *)(p_info_ch->p_tx_aio->aio_buf);
dkato 6:aa1fc6a5cc2a 4418 dma_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
dkato 6:aa1fc6a5cc2a 4419 dma_address_param.count = p_info_ch->p_tx_aio->aio_nbytes;
dkato 6:aa1fc6a5cc2a 4420
dkato 6:aa1fc6a5cc2a 4421 retval = R_DMA_Start(p_info_ch->dma_tx_ch, &dma_address_param, NULL);
dkato 6:aa1fc6a5cc2a 4422 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 4423 {
dkato 6:aa1fc6a5cc2a 4424 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4425 }
dkato 6:aa1fc6a5cc2a 4426 else
dkato 6:aa1fc6a5cc2a 4427 {
dkato 6:aa1fc6a5cc2a 4428 p_info_ch->dma_tx_current_size = dma_address_param.count;
dkato 6:aa1fc6a5cc2a 4429 }
dkato 6:aa1fc6a5cc2a 4430 }
dkato 6:aa1fc6a5cc2a 4431 else
dkato 6:aa1fc6a5cc2a 4432 {
dkato 6:aa1fc6a5cc2a 4433 switch (p_info_ch->ch_stat)
dkato 6:aa1fc6a5cc2a 4434 {
dkato 6:aa1fc6a5cc2a 4435 case SCUX_CH_UNINIT :
dkato 6:aa1fc6a5cc2a 4436 /* fall through */
dkato 6:aa1fc6a5cc2a 4437 case SCUX_CH_INIT :
dkato 6:aa1fc6a5cc2a 4438 /* fall through */
dkato 6:aa1fc6a5cc2a 4439 case SCUX_CH_STOP :
dkato 6:aa1fc6a5cc2a 4440 /* fall through */
dkato 6:aa1fc6a5cc2a 4441 case SCUX_CH_TRANS_IDLE :
dkato 6:aa1fc6a5cc2a 4442 /* fall through */
dkato 6:aa1fc6a5cc2a 4443 case SCUX_CH_TRANS_RD :
dkato 6:aa1fc6a5cc2a 4444 /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 4445 break;
dkato 6:aa1fc6a5cc2a 4446
dkato 6:aa1fc6a5cc2a 4447 case SCUX_CH_TRANS_WR :
dkato 6:aa1fc6a5cc2a 4448 p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
dkato 6:aa1fc6a5cc2a 4449 break;
dkato 6:aa1fc6a5cc2a 4450
dkato 6:aa1fc6a5cc2a 4451 case SCUX_CH_TRANS_RDWR :
dkato 6:aa1fc6a5cc2a 4452 p_info_ch->ch_stat = SCUX_CH_TRANS_RD;
dkato 6:aa1fc6a5cc2a 4453 break;
dkato 6:aa1fc6a5cc2a 4454
dkato 6:aa1fc6a5cc2a 4455 case SCUX_CH_STOP_WAIT :
dkato 6:aa1fc6a5cc2a 4456 /* fall through */
dkato 6:aa1fc6a5cc2a 4457 case SCUX_CH_STOP_WAIT_IDLE :
dkato 6:aa1fc6a5cc2a 4458 /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 4459 break;
dkato 6:aa1fc6a5cc2a 4460
dkato 6:aa1fc6a5cc2a 4461 default :
dkato 6:aa1fc6a5cc2a 4462 /* NOTREACHED on At the time of a normal performance */
dkato 6:aa1fc6a5cc2a 4463 break;
dkato 6:aa1fc6a5cc2a 4464 }
dkato 6:aa1fc6a5cc2a 4465 }
dkato 6:aa1fc6a5cc2a 4466 }
dkato 6:aa1fc6a5cc2a 4467 }
dkato 6:aa1fc6a5cc2a 4468
dkato 6:aa1fc6a5cc2a 4469 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4470 End of function SCUX_DMA_CopyTxNextData
dkato 6:aa1fc6a5cc2a 4471 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4472
dkato 6:aa1fc6a5cc2a 4473 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 4474 * Function Name: SCUX_DMA_CopyTxCallBack
dkato 6:aa1fc6a5cc2a 4475 * @brief Write request callback (mem to mem route).
dkato 6:aa1fc6a5cc2a 4476 *
dkato 6:aa1fc6a5cc2a 4477 * Description:<br>
dkato 6:aa1fc6a5cc2a 4478 *
dkato 6:aa1fc6a5cc2a 4479 * @param[in] param : SCUX channel number.
dkato 6:aa1fc6a5cc2a 4480 * @retval None.
dkato 6:aa1fc6a5cc2a 4481 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4482
dkato 6:aa1fc6a5cc2a 4483 static void SCUX_DMA_CopyTxCallBack(union sigval const param)
dkato 6:aa1fc6a5cc2a 4484 {
dkato 6:aa1fc6a5cc2a 4485 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int);
dkato 6:aa1fc6a5cc2a 4486
dkato 6:aa1fc6a5cc2a 4487 if (NULL == p_info_ch)
dkato 6:aa1fc6a5cc2a 4488 {
dkato 6:aa1fc6a5cc2a 4489 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4490 }
dkato 6:aa1fc6a5cc2a 4491 else
dkato 6:aa1fc6a5cc2a 4492 {
dkato 6:aa1fc6a5cc2a 4493 if ((SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) || (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat))
dkato 6:aa1fc6a5cc2a 4494 {
dkato 6:aa1fc6a5cc2a 4495 /* data flush process */
dkato 6:aa1fc6a5cc2a 4496 if (false != p_info_ch->tx_dummy_run_flag)
dkato 6:aa1fc6a5cc2a 4497 {
dkato 6:aa1fc6a5cc2a 4498 if (0U == p_info_ch->flush_stop_size)
dkato 6:aa1fc6a5cc2a 4499 {
dkato 6:aa1fc6a5cc2a 4500 SCUX_DMA_CopyTxEndFlush(p_info_ch);
dkato 6:aa1fc6a5cc2a 4501 }
dkato 6:aa1fc6a5cc2a 4502 else
dkato 6:aa1fc6a5cc2a 4503 {
dkato 6:aa1fc6a5cc2a 4504 SCUX_DMA_CommonTxNextDummyData(p_info_ch);
dkato 6:aa1fc6a5cc2a 4505 }
dkato 6:aa1fc6a5cc2a 4506 }
dkato 6:aa1fc6a5cc2a 4507 else
dkato 6:aa1fc6a5cc2a 4508 {
dkato 6:aa1fc6a5cc2a 4509 SCUX_DMA_CopyTxNextRemainData(p_info_ch);
dkato 6:aa1fc6a5cc2a 4510 }
dkato 6:aa1fc6a5cc2a 4511 }
dkato 6:aa1fc6a5cc2a 4512 else
dkato 6:aa1fc6a5cc2a 4513 {
dkato 6:aa1fc6a5cc2a 4514 SCUX_DMA_CopyTxNextData(p_info_ch);
dkato 6:aa1fc6a5cc2a 4515 }
dkato 6:aa1fc6a5cc2a 4516 }
dkato 6:aa1fc6a5cc2a 4517 }
dkato 6:aa1fc6a5cc2a 4518
dkato 6:aa1fc6a5cc2a 4519 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4520 End of function SCUX_DMA_CopyTxCallBack
dkato 6:aa1fc6a5cc2a 4521 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4522
dkato 6:aa1fc6a5cc2a 4523 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 4524 * Function Name: SCUX_DMA_DirectTxEndFlush
dkato 6:aa1fc6a5cc2a 4525 * @brief End of flush operation (SSIF Direct route).
dkato 6:aa1fc6a5cc2a 4526 *
dkato 6:aa1fc6a5cc2a 4527 * Description:<br>
dkato 6:aa1fc6a5cc2a 4528 *
dkato 6:aa1fc6a5cc2a 4529 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 4530 * @retval None.
dkato 6:aa1fc6a5cc2a 4531 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4532
dkato 6:aa1fc6a5cc2a 4533 static void SCUX_DMA_DirectTxEndFlush(scux_info_ch_t * const p_info_ch)
dkato 6:aa1fc6a5cc2a 4534 {
dkato 6:aa1fc6a5cc2a 4535 int_t retval;
dkato 6:aa1fc6a5cc2a 4536 int_t dma_ercd;
dkato 6:aa1fc6a5cc2a 4537 uint32_t tx_remain_size = 0;
dkato 6:aa1fc6a5cc2a 4538
dkato 6:aa1fc6a5cc2a 4539 if (NULL == p_info_ch)
dkato 6:aa1fc6a5cc2a 4540 {
dkato 6:aa1fc6a5cc2a 4541 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4542 }
dkato 6:aa1fc6a5cc2a 4543 else
dkato 6:aa1fc6a5cc2a 4544 {
dkato 6:aa1fc6a5cc2a 4545 /* finish send dummy data process, and SCUX stop process */
dkato 6:aa1fc6a5cc2a 4546 retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
dkato 6:aa1fc6a5cc2a 4547 /* It isn't an error even if error code is EBADF, because it is already stopped. */
dkato 6:aa1fc6a5cc2a 4548 if ((ESUCCESS != retval) && (EBADF != dma_ercd))
dkato 6:aa1fc6a5cc2a 4549 {
dkato 6:aa1fc6a5cc2a 4550 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4551 }
dkato 6:aa1fc6a5cc2a 4552 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
dkato 6:aa1fc6a5cc2a 4553 p_info_ch->dma_tx_current_size = 0;
dkato 6:aa1fc6a5cc2a 4554
dkato 6:aa1fc6a5cc2a 4555 SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, 0);
dkato 6:aa1fc6a5cc2a 4556
dkato 6:aa1fc6a5cc2a 4557 SCUX_AsyncStopHw(p_info_ch);
dkato 6:aa1fc6a5cc2a 4558
dkato 6:aa1fc6a5cc2a 4559 p_info_ch->ch_stat = SCUX_CH_STOP;
dkato 6:aa1fc6a5cc2a 4560 if (NULL != p_info_ch->p_flush_callback)
dkato 6:aa1fc6a5cc2a 4561 {
dkato 6:aa1fc6a5cc2a 4562 p_info_ch->p_flush_callback(ESUCCESS);
dkato 6:aa1fc6a5cc2a 4563 }
dkato 6:aa1fc6a5cc2a 4564 }
dkato 6:aa1fc6a5cc2a 4565 }
dkato 6:aa1fc6a5cc2a 4566
dkato 6:aa1fc6a5cc2a 4567 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4568 End of function SCUX_DMA_DirectTxEndFlush
dkato 6:aa1fc6a5cc2a 4569 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4570
dkato 6:aa1fc6a5cc2a 4571 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 4572 * Function Name: SCUX_DMA_DirectTxNextRemainData
dkato 6:aa1fc6a5cc2a 4573 * @brief Set next remain data for flush (SSIF Direct route).
dkato 6:aa1fc6a5cc2a 4574 *
dkato 6:aa1fc6a5cc2a 4575 * Description:<br>
dkato 6:aa1fc6a5cc2a 4576 *
dkato 6:aa1fc6a5cc2a 4577 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 4578 * @retval None.
dkato 6:aa1fc6a5cc2a 4579 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4580
dkato 6:aa1fc6a5cc2a 4581 static void SCUX_DMA_DirectTxNextRemainData(scux_info_ch_t * const p_info_ch)
dkato 6:aa1fc6a5cc2a 4582 {
dkato 6:aa1fc6a5cc2a 4583 dma_trans_data_t dma_next_address_param;
dkato 6:aa1fc6a5cc2a 4584 int_t retval;
dkato 6:aa1fc6a5cc2a 4585
dkato 6:aa1fc6a5cc2a 4586 if (NULL == p_info_ch)
dkato 6:aa1fc6a5cc2a 4587 {
dkato 6:aa1fc6a5cc2a 4588 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4589 }
dkato 6:aa1fc6a5cc2a 4590 else
dkato 6:aa1fc6a5cc2a 4591 {
dkato 6:aa1fc6a5cc2a 4592 if (NULL != p_info_ch->p_tx_aio)
dkato 6:aa1fc6a5cc2a 4593 {
dkato 6:aa1fc6a5cc2a 4594 p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
dkato 6:aa1fc6a5cc2a 4595 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
dkato 6:aa1fc6a5cc2a 4596 p_info_ch->first_tx_flag = false;
dkato 6:aa1fc6a5cc2a 4597 }
dkato 6:aa1fc6a5cc2a 4598
dkato 6:aa1fc6a5cc2a 4599
dkato 6:aa1fc6a5cc2a 4600 /* send remain tx data prcess for flush */
dkato 6:aa1fc6a5cc2a 4601 p_info_ch->p_tx_aio = p_info_ch->p_tx_next_aio;
dkato 6:aa1fc6a5cc2a 4602 p_info_ch->p_tx_next_aio = ahf_removehead(&p_info_ch->tx_que);
dkato 6:aa1fc6a5cc2a 4603 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
dkato 6:aa1fc6a5cc2a 4604 p_info_ch->dma_tx_current_size = 0;
dkato 6:aa1fc6a5cc2a 4605
dkato 6:aa1fc6a5cc2a 4606 if ((NULL != p_info_ch->p_tx_next_aio) && (NULL != p_info_ch->p_tx_aio))
dkato 6:aa1fc6a5cc2a 4607 {
dkato 6:aa1fc6a5cc2a 4608 /* 1.
dkato 6:aa1fc6a5cc2a 4609 * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio isn't NULL.
dkato 6:aa1fc6a5cc2a 4610 * Since, Next DMA is effective and p_info_ch->p_tx_aio is set to Next DMA
dkato 6:aa1fc6a5cc2a 4611 * The vaule of p_info_ch->dma_tx_current_size is updated to the value of
dkato 6:aa1fc6a5cc2a 4612 * p_info_ch->dma_tx_next_size.
dkato 6:aa1fc6a5cc2a 4613 * The vaule of p_info_ch->dma_tx_next_size is updated to the value of DMA size
dkato 6:aa1fc6a5cc2a 4614 * on Next DMA.
dkato 6:aa1fc6a5cc2a 4615 */
dkato 6:aa1fc6a5cc2a 4616 dma_next_address_param.src_addr = (void *)(p_info_ch->p_tx_next_aio->aio_buf);
dkato 6:aa1fc6a5cc2a 4617 dma_next_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
dkato 6:aa1fc6a5cc2a 4618 dma_next_address_param.count = p_info_ch->p_tx_next_aio->aio_nbytes;
dkato 6:aa1fc6a5cc2a 4619
dkato 6:aa1fc6a5cc2a 4620 retval = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_next_address_param, NULL);
dkato 6:aa1fc6a5cc2a 4621 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 4622 {
dkato 6:aa1fc6a5cc2a 4623 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4624 }
dkato 6:aa1fc6a5cc2a 4625 else
dkato 6:aa1fc6a5cc2a 4626 {
dkato 6:aa1fc6a5cc2a 4627 p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
dkato 6:aa1fc6a5cc2a 4628 p_info_ch->dma_tx_next_size = dma_next_address_param.count;
dkato 6:aa1fc6a5cc2a 4629 }
dkato 6:aa1fc6a5cc2a 4630 }
dkato 6:aa1fc6a5cc2a 4631 else if ((NULL != p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
dkato 6:aa1fc6a5cc2a 4632 {
dkato 6:aa1fc6a5cc2a 4633 /* 2.
dkato 6:aa1fc6a5cc2a 4634 * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio is NULL.
dkato 6:aa1fc6a5cc2a 4635 * Since, Next DMA is Stopped and DMA is restarted to p_info_ch->p_tx_aio
dkato 6:aa1fc6a5cc2a 4636 * The vaule of p_info_ch->dma_tx_current_size and p_info_ch->dma_tx_next_size
dkato 6:aa1fc6a5cc2a 4637 * are updated to restart DMA value.
dkato 6:aa1fc6a5cc2a 4638 */
dkato 6:aa1fc6a5cc2a 4639 retval = SCUX_DirectWriteStart(p_info_ch, p_info_ch->p_tx_next_aio);
dkato 6:aa1fc6a5cc2a 4640 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 4641 {
dkato 6:aa1fc6a5cc2a 4642 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4643 }
dkato 6:aa1fc6a5cc2a 4644 }
dkato 6:aa1fc6a5cc2a 4645 else if ((NULL == p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
dkato 6:aa1fc6a5cc2a 4646 {
dkato 6:aa1fc6a5cc2a 4647 /* 3.
dkato 6:aa1fc6a5cc2a 4648 * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio is NULL.
dkato 6:aa1fc6a5cc2a 4649 * Since, all request finished, and flush data write start.
dkato 6:aa1fc6a5cc2a 4650 * The vaule of p_info_ch->dma_tx_current_size is updated to flush DMA value.
dkato 6:aa1fc6a5cc2a 4651 */
dkato 6:aa1fc6a5cc2a 4652
dkato 6:aa1fc6a5cc2a 4653 retval = SCUX_FlushWriteStart(p_info_ch);
dkato 6:aa1fc6a5cc2a 4654 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 4655 {
dkato 6:aa1fc6a5cc2a 4656 /* NON_NOTICE_ASSERT: DMA operation failed */
dkato 6:aa1fc6a5cc2a 4657 }
dkato 6:aa1fc6a5cc2a 4658 }
dkato 6:aa1fc6a5cc2a 4659 else
dkato 6:aa1fc6a5cc2a 4660 {
dkato 6:aa1fc6a5cc2a 4661 /* 4.
dkato 6:aa1fc6a5cc2a 4662 * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio isn't NULL.
dkato 6:aa1fc6a5cc2a 4663 * Since, Nothing new aio request, and processing of 2. or 3. is performed
dkato 6:aa1fc6a5cc2a 4664 * in the next loop.
dkato 6:aa1fc6a5cc2a 4665 * The vaule of p_info_ch->dma_tx_current_size is updated to the value of
dkato 6:aa1fc6a5cc2a 4666 * p_info_ch->dma_tx_next_size.
dkato 6:aa1fc6a5cc2a 4667 */
dkato 6:aa1fc6a5cc2a 4668
dkato 6:aa1fc6a5cc2a 4669 p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
dkato 6:aa1fc6a5cc2a 4670 p_info_ch->dma_tx_next_size = 0;
dkato 6:aa1fc6a5cc2a 4671 }
dkato 6:aa1fc6a5cc2a 4672 }
dkato 6:aa1fc6a5cc2a 4673 }
dkato 6:aa1fc6a5cc2a 4674
dkato 6:aa1fc6a5cc2a 4675 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4676 End of function SCUX_DMA_DirectTxNextRemainData
dkato 6:aa1fc6a5cc2a 4677 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4678
dkato 6:aa1fc6a5cc2a 4679 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 4680 * Function Name: SCUX_DMA_DirectTxNextData
dkato 6:aa1fc6a5cc2a 4681 * @brief Set next data normal operation (SSIF Direct route).
dkato 6:aa1fc6a5cc2a 4682 *
dkato 6:aa1fc6a5cc2a 4683 * Description:<br>
dkato 6:aa1fc6a5cc2a 4684 *
dkato 6:aa1fc6a5cc2a 4685 * @param[in] *p_scux_info_ch : SCUX channel information.
dkato 6:aa1fc6a5cc2a 4686 * @retval None.
dkato 6:aa1fc6a5cc2a 4687 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4688
dkato 6:aa1fc6a5cc2a 4689 static void SCUX_DMA_DirectTxNextData(scux_info_ch_t * const p_info_ch)
dkato 6:aa1fc6a5cc2a 4690 {
dkato 6:aa1fc6a5cc2a 4691 dma_trans_data_t dma_next_address_param;
dkato 6:aa1fc6a5cc2a 4692 int_t retval;
dkato 6:aa1fc6a5cc2a 4693
dkato 6:aa1fc6a5cc2a 4694 if (NULL == p_info_ch)
dkato 6:aa1fc6a5cc2a 4695 {
dkato 6:aa1fc6a5cc2a 4696 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4697 }
dkato 6:aa1fc6a5cc2a 4698 else
dkato 6:aa1fc6a5cc2a 4699 {
dkato 6:aa1fc6a5cc2a 4700 if (NULL != p_info_ch->p_tx_aio)
dkato 6:aa1fc6a5cc2a 4701 {
dkato 6:aa1fc6a5cc2a 4702 p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
dkato 6:aa1fc6a5cc2a 4703 ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
dkato 6:aa1fc6a5cc2a 4704 p_info_ch->first_tx_flag = false;
dkato 6:aa1fc6a5cc2a 4705 }
dkato 6:aa1fc6a5cc2a 4706
dkato 6:aa1fc6a5cc2a 4707 /* normal send process */
dkato 6:aa1fc6a5cc2a 4708 p_info_ch->p_tx_aio = p_info_ch->p_tx_next_aio;
dkato 6:aa1fc6a5cc2a 4709 p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
dkato 6:aa1fc6a5cc2a 4710 p_info_ch->p_tx_next_aio = ahf_removehead(&p_info_ch->tx_que);
dkato 6:aa1fc6a5cc2a 4711
dkato 6:aa1fc6a5cc2a 4712 if ((NULL != p_info_ch->p_tx_next_aio) && (NULL != p_info_ch->p_tx_aio))
dkato 6:aa1fc6a5cc2a 4713 {
dkato 6:aa1fc6a5cc2a 4714 /* 1.
dkato 6:aa1fc6a5cc2a 4715 * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio isn't NULL.
dkato 6:aa1fc6a5cc2a 4716 . * Since, Next DMA is effective and p_info_ch->p_tx_aio is set to Next DMA
dkato 6:aa1fc6a5cc2a 4717 * The vaule of p_info_ch->dma_tx_current_size is updated to the value of
dkato 6:aa1fc6a5cc2a 4718 * p_info_ch->dma_tx_next_size.
dkato 6:aa1fc6a5cc2a 4719 * The vaule of p_info_ch->dma_tx_next_size is updated to the value of DMA size
dkato 6:aa1fc6a5cc2a 4720 * on Next DMA.
dkato 6:aa1fc6a5cc2a 4721 */
dkato 6:aa1fc6a5cc2a 4722 dma_next_address_param.src_addr = (void *)(p_info_ch->p_tx_next_aio->aio_buf);
dkato 6:aa1fc6a5cc2a 4723 dma_next_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
dkato 6:aa1fc6a5cc2a 4724 dma_next_address_param.count = p_info_ch->p_tx_next_aio->aio_nbytes;
dkato 6:aa1fc6a5cc2a 4725
dkato 6:aa1fc6a5cc2a 4726 retval = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_next_address_param, NULL);
dkato 6:aa1fc6a5cc2a 4727 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 4728 {
dkato 6:aa1fc6a5cc2a 4729 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4730 }
dkato 6:aa1fc6a5cc2a 4731 else
dkato 6:aa1fc6a5cc2a 4732 {
dkato 6:aa1fc6a5cc2a 4733 p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
dkato 6:aa1fc6a5cc2a 4734 p_info_ch->dma_tx_next_size = dma_next_address_param.count;
dkato 6:aa1fc6a5cc2a 4735 }
dkato 6:aa1fc6a5cc2a 4736 }
dkato 6:aa1fc6a5cc2a 4737 else if ((NULL != p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
dkato 6:aa1fc6a5cc2a 4738 {
dkato 6:aa1fc6a5cc2a 4739 /* 2.
dkato 6:aa1fc6a5cc2a 4740 * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio is NULL.
dkato 6:aa1fc6a5cc2a 4741 * Since, Next DMA is Stopped and DMA is restarted to p_info_ch->p_tx_aio
dkato 6:aa1fc6a5cc2a 4742 * The vaule of p_info_ch->dma_tx_current_size and p_info_ch->dma_tx_next_size
dkato 6:aa1fc6a5cc2a 4743 * are updated to restart DMA value.
dkato 6:aa1fc6a5cc2a 4744 */
dkato 6:aa1fc6a5cc2a 4745
dkato 6:aa1fc6a5cc2a 4746 retval = SCUX_DirectWriteStart(p_info_ch, p_info_ch->p_tx_next_aio);
dkato 6:aa1fc6a5cc2a 4747 if (ESUCCESS != retval)
dkato 6:aa1fc6a5cc2a 4748 {
dkato 6:aa1fc6a5cc2a 4749 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4750 }
dkato 6:aa1fc6a5cc2a 4751 }
dkato 6:aa1fc6a5cc2a 4752 else if((NULL == p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
dkato 6:aa1fc6a5cc2a 4753 {
dkato 6:aa1fc6a5cc2a 4754 /* 3.
dkato 6:aa1fc6a5cc2a 4755 * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio is NULL.
dkato 6:aa1fc6a5cc2a 4756 * Since, all request finished, and status is made to change IDLE.
dkato 6:aa1fc6a5cc2a 4757 * The vaule of p_info_ch->dma_tx_current_size is updated to 0.
dkato 6:aa1fc6a5cc2a 4758 */
dkato 6:aa1fc6a5cc2a 4759 p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
dkato 6:aa1fc6a5cc2a 4760 p_info_ch->dma_tx_current_size = 0;
dkato 6:aa1fc6a5cc2a 4761
dkato 6:aa1fc6a5cc2a 4762 }
dkato 6:aa1fc6a5cc2a 4763 else
dkato 6:aa1fc6a5cc2a 4764 {
dkato 6:aa1fc6a5cc2a 4765 /* 4.
dkato 6:aa1fc6a5cc2a 4766 * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio isn't NULL.
dkato 6:aa1fc6a5cc2a 4767 * Since, Nothing new aio request, and processing of 2. or 3. is performed
dkato 6:aa1fc6a5cc2a 4768 * in the next loop.
dkato 6:aa1fc6a5cc2a 4769 * The vaule of p_info_ch->dma_tx_current_size is updated to the value of
dkato 6:aa1fc6a5cc2a 4770 * p_info_ch->dma_tx_next_size.
dkato 6:aa1fc6a5cc2a 4771 */
dkato 6:aa1fc6a5cc2a 4772
dkato 6:aa1fc6a5cc2a 4773 p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
dkato 6:aa1fc6a5cc2a 4774 p_info_ch->dma_tx_next_size = 0;
dkato 6:aa1fc6a5cc2a 4775 }
dkato 6:aa1fc6a5cc2a 4776 }
dkato 6:aa1fc6a5cc2a 4777 }
dkato 6:aa1fc6a5cc2a 4778
dkato 6:aa1fc6a5cc2a 4779 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4780 End of function SCUX_DMA_DirectTxNextData
dkato 6:aa1fc6a5cc2a 4781 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4782
dkato 6:aa1fc6a5cc2a 4783 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 4784 * Function Name: SCUX_DMA_DirectTxCallBack
dkato 6:aa1fc6a5cc2a 4785 * @brief Write request callback (SSIF Direct route).
dkato 6:aa1fc6a5cc2a 4786 *
dkato 6:aa1fc6a5cc2a 4787 * Description:<br>
dkato 6:aa1fc6a5cc2a 4788 *
dkato 6:aa1fc6a5cc2a 4789 * @param[in] param : SCUX channel number.
dkato 6:aa1fc6a5cc2a 4790 * @retval None.
dkato 6:aa1fc6a5cc2a 4791 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4792
dkato 6:aa1fc6a5cc2a 4793 static void SCUX_DMA_DirectTxCallBack(union sigval const param)
dkato 6:aa1fc6a5cc2a 4794 {
dkato 6:aa1fc6a5cc2a 4795 scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int);
dkato 6:aa1fc6a5cc2a 4796
dkato 6:aa1fc6a5cc2a 4797 if (NULL == p_info_ch)
dkato 6:aa1fc6a5cc2a 4798 {
dkato 6:aa1fc6a5cc2a 4799 /* NON_NOTICE_ASSERT: NULL pointer */
dkato 6:aa1fc6a5cc2a 4800 }
dkato 6:aa1fc6a5cc2a 4801 else
dkato 6:aa1fc6a5cc2a 4802 {
dkato 6:aa1fc6a5cc2a 4803 if (SCUX_CH_STOP_WAIT == p_info_ch->ch_stat)
dkato 6:aa1fc6a5cc2a 4804 {
dkato 6:aa1fc6a5cc2a 4805 /* data flush process */
dkato 6:aa1fc6a5cc2a 4806 if (false != p_info_ch->tx_dummy_run_flag)
dkato 6:aa1fc6a5cc2a 4807 {
dkato 6:aa1fc6a5cc2a 4808 if (0U == p_info_ch->flush_stop_size)
dkato 6:aa1fc6a5cc2a 4809 {
dkato 6:aa1fc6a5cc2a 4810 SCUX_DMA_DirectTxEndFlush(p_info_ch);
dkato 6:aa1fc6a5cc2a 4811 }
dkato 6:aa1fc6a5cc2a 4812 else
dkato 6:aa1fc6a5cc2a 4813 {
dkato 6:aa1fc6a5cc2a 4814 SCUX_DMA_CommonTxNextDummyData(p_info_ch);
dkato 6:aa1fc6a5cc2a 4815 }
dkato 6:aa1fc6a5cc2a 4816 }
dkato 6:aa1fc6a5cc2a 4817 else
dkato 6:aa1fc6a5cc2a 4818 {
dkato 6:aa1fc6a5cc2a 4819 SCUX_DMA_DirectTxNextRemainData(p_info_ch);
dkato 6:aa1fc6a5cc2a 4820 }
dkato 6:aa1fc6a5cc2a 4821 }
dkato 6:aa1fc6a5cc2a 4822 else
dkato 6:aa1fc6a5cc2a 4823 {
dkato 6:aa1fc6a5cc2a 4824 SCUX_DMA_DirectTxNextData(p_info_ch);
dkato 6:aa1fc6a5cc2a 4825 }
dkato 6:aa1fc6a5cc2a 4826 }
dkato 6:aa1fc6a5cc2a 4827 }
dkato 6:aa1fc6a5cc2a 4828
dkato 6:aa1fc6a5cc2a 4829 /******************************************************************************
dkato 6:aa1fc6a5cc2a 4830 End of function SCUX_DMA_DirextTxCallBack
dkato 6:aa1fc6a5cc2a 4831 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 4832