The "GR-PEACH_Audio_Playback_7InchLCD_Sample" is a sample code that can provides high-resolution audio playback of FLAC format files. It also allows the user to audio-playback control functions such as play, pause, and stop by manipulating key switches.

Dependencies:   GR-PEACH_video R_BSP TLV320_RBSP USBHost_custom

Fork of GR-PEACH_Audio_Playback_Sample by Renesas

Note

For a sample program of without LCD Board, please refer to GR-PEACH_Audio_Playback_Sample.

Introduction

The "GR-PEACH_Audio_Playback_7InchLCD_Sample" is a sample code that can provides high-resolution audio playback of FLAC format files. It also allows the user to audio-playback control functions such as play, pause, and stop by manipulating key switches.

1. Overview of the Sample Code

1.1 Software Block Diagram

Figure 1.1 shows the software block diagram.

/media/uploads/1050186/lcd_figure1_1.png

1.2 Pin Definitions

Table 1.1 shows the pins used in this sample code.

/media/uploads/1050186/lcd_table1_1.png

2. Sample Code Operating Environment

In order to operate this sample code, GR-PEACH, Audio Camera Shield and 7.1 inch LCD Shield must be needed. For details on Audio Camera Shield and 7.1 inch LCD Shield, please refer to the following links, respectively:

In this section, it is described that how board is configured and to control audio playback via command line and touch screen.

2.1 Operating Environment

Figure 2.1 shows the overview of the operating environment for this sample code.

/media/uploads/1050186/lcd_figure2_1.png

Figure 2.2 and 2.3 show how to configure GR-PEACH, Audio Camera Shield and 7.1 inch LCD shield when using USB0 and USB1, respectively.

/media/uploads/1050186/lcd_figure2_2.png /media/uploads/1050186/lcd_figure2_3.png

Table 2.1 lists the overview of Graphical User Interface (GUI) of this sample code.

/media/uploads/1050186/lcd_table2_1.png

2.2 List of User Operations

Table 2.2 shows the relationship among Audio Playback, Command Line and Onboard Switch.

/media/uploads/1050186/lcd_table2_2.png

3. Function Outline

Table 3.1, 3.2 and 3.3 shows the overview of functions implemented in this sample code.

/media/uploads/1050186/lcd_table3_1.png /media/uploads/1050186/lcd_table3_2.png /media/uploads/1050186/lcd_table3_3.png /media/uploads/1050186/lcd_figure3_1.png

3.1 Playback Control

This sample program supports the operation "play", "pause", "stop", "play next song" and "play previous song".

3.2 Trick Play Control

In order to enable/disable Repeat Mode, user need to type "repeat" on command line or click the corresponding icon shown in Table 2.2. By derault, Repeat Mode is enabled. When Repeat Mode is enabled, the first song is played back after the playback of the last song is finished. Otherwise, the playback is shopped when finishing to play back the last song.

3.3 How to see Song Information

The information of the song being played back can be seen by typing playinfo on command line. Table 3.4 lists the items user can see on the terminal.

/media/uploads/dkato/audioplayback_table3_4.png

3.4 How to analyze the folder structure in USB stick

In this sample code, the folder structure in USB stick is analyzed in the breadth-first order. Table 3.5 shows how the files in USB stick are numbered.

/media/uploads/dkato/audioplayback_table3_5.png

4.Others

4.1 Serial Communication Setting

With respect to the default serial communication related setting on mbed, please refer to the follwing link:
https://developer.mbed.org/teams/Renesas/wiki/GR-PEACH-Getting-Started#install-the-usb-serial-communication
Please set up the terminal software you would like to use on your PC in consideration of the above. For example, 9600 should be specified for the baud rate on the terminal in order to control this sample via command line.

4.2 Necessary modification when using GCC ARM Embedded

If you would like to use GCC ARM Embedded, you must revise the following linker script incorporated in mbed OS 5 package as follows:

  • Linker Script to be modified
    $(PROJECT_ROOT)/mbed-os/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld

    Please note that $(PROJECT_ROOT) in the above denotes the root directory of this sample code

  • Before Modification

RZA1H.ld

/* Linker script for mbed RZ_A1H */

/* Linker script to configure memory regions. */
MEMORY
{
  ROM   (rx)  : ORIGIN = 0x00000000, LENGTH = 0x02000000
  BOOT_LOADER (rx) : ORIGIN = 0x18000000, LENGTH = 0x00004000 
  SFLASH (rx) : ORIGIN = 0x18004000, LENGTH = 0x07FFC000 
  L_TTB (rw)  : ORIGIN = 0x20000000, LENGTH = 0x00004000 
  RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00700000
  RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000
}
(snip)
  • After Modification

RZA1H.ld

/* Linker script for mbed RZ_A1H */

/* Linker script to configure memory regions. */
MEMORY
{
  ROM   (rx)  : ORIGIN = 0x00000000, LENGTH = 0x02000000
  BOOT_LOADER (rx) : ORIGIN = 0x18000000, LENGTH = 0x00004000 
  SFLASH (rx) : ORIGIN = 0x18004000, LENGTH = 0x07FFC000 
  L_TTB (rw)  : ORIGIN = 0x20000000, LENGTH = 0x00004000 
  RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00180000
  RAM_NC (rwx) : ORIGIN = 0x20200000, LENGTH = 0x00680000
}
(snip)
Committer:
Osamu Nakamura
Date:
Tue Apr 11 12:42:10 2017 +0900
Revision:
6:a957aaa284f0
Parent:
4:2672de88a46b
Update R-BSP from rev. cbb9d60c8748 to fb9eda52224e so that this program can be compiled with IAR toolchain.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
1050186 4:2672de88a46b 1 /*******************************************************************************
1050186 4:2672de88a46b 2 * DISCLAIMER
1050186 4:2672de88a46b 3 * This software is supplied by Renesas Electronics Corporation and is only
1050186 4:2672de88a46b 4 * intended for use with Renesas products. No other uses are authorized. This
1050186 4:2672de88a46b 5 * software is owned by Renesas Electronics Corporation and is protected under
1050186 4:2672de88a46b 6 * all applicable laws, including copyright laws.
1050186 4:2672de88a46b 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
1050186 4:2672de88a46b 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
1050186 4:2672de88a46b 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
1050186 4:2672de88a46b 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
1050186 4:2672de88a46b 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
1050186 4:2672de88a46b 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
1050186 4:2672de88a46b 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
1050186 4:2672de88a46b 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
1050186 4:2672de88a46b 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
1050186 4:2672de88a46b 16 * Renesas reserves the right, without notice, to make changes to this software
1050186 4:2672de88a46b 17 * and to discontinue the availability of this software. By using this software,
1050186 4:2672de88a46b 18 * you agree to the additional terms and conditions found by accessing the
1050186 4:2672de88a46b 19 * following link:
1050186 4:2672de88a46b 20 * http://www.renesas.com/disclaimer*
1050186 4:2672de88a46b 21 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
1050186 4:2672de88a46b 22 *******************************************************************************/
1050186 4:2672de88a46b 23
1050186 4:2672de88a46b 24 #include "mbed.h"
1050186 4:2672de88a46b 25 #include "rtos.h"
1050186 4:2672de88a46b 26 #include "misratypes.h"
1050186 4:2672de88a46b 27 #include "DisplayBace.h"
1050186 4:2672de88a46b 28 #include "display.h"
1050186 4:2672de88a46b 29 #include "disp_tft.h"
1050186 4:2672de88a46b 30 #include "disp_tft_scrn.h"
1050186 4:2672de88a46b 31
1050186 4:2672de88a46b 32 /*--- Macro definition of LCD display driver ---*/
1050186 4:2672de88a46b 33 #define LCD_INPUT_CLK (66.67) /* Input clock: P1 clk [MHz] */
1050186 4:2672de88a46b 34 #define LCD_OUTPUT_CLK (33.26) /* Output clock: LCD clk [MHz] */
1050186 4:2672de88a46b 35 #define LCD_HSYNC_PERIOD (1056) /* Free-running Hsync period: 800 + 92 + 128 + 36 */
1050186 4:2672de88a46b 36 #define LCD_VSYNC_PERIOD (525) /* Free-running Vsync period: 480 + 5 + 35 + 5 */
1050186 4:2672de88a46b 37 #define LCD_H_BACK_PORCH (164) /* LCD display horizontal back porch period: 128 + 36 */
1050186 4:2672de88a46b 38 #define LCD_V_BACK_PORCH (40) /* LCD display vertical back porch period: 35 + 5 */
1050186 4:2672de88a46b 39 #define LCD_PIN_NUM (8)
1050186 4:2672de88a46b 40 #define LCD_INPUT_FORMAT_SIZE (4u)
1050186 4:2672de88a46b 41
1050186 4:2672de88a46b 42 /* Power ON sequence */
1050186 4:2672de88a46b 43 #define BLON_WAIT_TIME_MS (200) /* Wait time of milisecond before the backlight ON. */
1050186 4:2672de88a46b 44
1050186 4:2672de88a46b 45 /* Frame buffer stride: Frame buffer stride should be set to a multiple of 32 or 128 */
1050186 4:2672de88a46b 46 /* in accordance with the frame buffer burst transfer mode. */
1050186 4:2672de88a46b 47 #define BUF_STRIDE (((DSP_TFT_WIDTH * LCD_INPUT_FORMAT_SIZE) + 31u) & ~31u)
1050186 4:2672de88a46b 48 #define BUF_HEIGHT (DSP_TFT_HEIGHT)
1050186 4:2672de88a46b 49 #define BUF_SIZE (BUF_STRIDE * BUF_HEIGHT)
1050186 4:2672de88a46b 50
1050186 4:2672de88a46b 51 #if defined( __CC_ARM )
1050186 4:2672de88a46b 52 #define VRAM_SECTION1 __attribute((at(0x60100000)))
1050186 4:2672de88a46b 53 #define VRAM_SECTION2 __attribute((at(0x60480000)))
1050186 4:2672de88a46b 54 #define VRAM_SECTION3 __attribute((at(0x60600000)))
1050186 4:2672de88a46b 55 #define VRAM_SECTION4 __attribute((at(0x60780000)))
1050186 4:2672de88a46b 56 #else /* !defined( __CC_ARM ) */
1050186 4:2672de88a46b 57 /* CAUTION! */
1050186 4:2672de88a46b 58 /* Modify the start address of "NC_BSS" section in "RZA1H.ld" file. */
1050186 4:2672de88a46b 59 #define VRAM_SECTION __attribute((section("NC_BSS"),aligned(16)))
1050186 4:2672de88a46b 60 #define VRAM_SECTION1 VRAM_SECTION
1050186 4:2672de88a46b 61 #define VRAM_SECTION2 VRAM_SECTION
1050186 4:2672de88a46b 62 #define VRAM_SECTION3 VRAM_SECTION
1050186 4:2672de88a46b 63 #define VRAM_SECTION4 VRAM_SECTION
1050186 4:2672de88a46b 64 #endif /* defined( __CC_ARM ) */
1050186 4:2672de88a46b 65
1050186 4:2672de88a46b 66 #define SHIFT_1BIT_SIZE (1u)
1050186 4:2672de88a46b 67
1050186 4:2672de88a46b 68 static void init_lcd_driver(const dsp_tft_ctrl_t * const p_tft);
1050186 4:2672de88a46b 69 static void update_tft_display(dsp_tft_ctrl_t * const p_tft, const uint32_t layer_id);
1050186 4:2672de88a46b 70 static void update_tft_audio_data(const dsp_com_ctrl_t * const p_com, dsp_tft_ctrl_t * const p_tft);
1050186 4:2672de88a46b 71 static void vsync_callback(DisplayBase::int_type_t int_type);
1050186 4:2672de88a46b 72 static DisplayBase::graphics_layer_t convert_layer_id(const uint32_t layer_id);
1050186 4:2672de88a46b 73 static void swap_frame_buffer(dsp_tftlayer_t * const p_info);
1050186 4:2672de88a46b 74
1050186 4:2672de88a46b 75 static DisplayBase lcd;
1050186 4:2672de88a46b 76
1050186 4:2672de88a46b 77 void dsp_init_tft(dsp_tft_ctrl_t * const p_tft)
1050186 4:2672de88a46b 78 {
1050186 4:2672de88a46b 79 static uint32_t VRAM_SECTION1 frame_buffer_1[BUF_SIZE/sizeof(uint32_t)];
1050186 4:2672de88a46b 80 static uint32_t VRAM_SECTION2 frame_buffer_2[BUF_SIZE/sizeof(uint32_t)];
1050186 4:2672de88a46b 81 static uint32_t VRAM_SECTION3 frame_buffer_3[BUF_SIZE/sizeof(uint32_t)];
1050186 4:2672de88a46b 82 static uint32_t VRAM_SECTION4 frame_buffer_4[BUF_SIZE/sizeof(uint32_t)];
1050186 4:2672de88a46b 83 uint32_t i;
1050186 4:2672de88a46b 84
1050186 4:2672de88a46b 85 if (p_tft != NULL) {
1050186 4:2672de88a46b 86 p_tft->key_code = SYS_KEYCODE_NON;
1050186 4:2672de88a46b 87 (void) memset(frame_buffer_1, 0, sizeof(frame_buffer_1));
1050186 4:2672de88a46b 88 (void) memset(frame_buffer_2, 0, sizeof(frame_buffer_2));
1050186 4:2672de88a46b 89 (void) memset(frame_buffer_3, 0, sizeof(frame_buffer_3));
1050186 4:2672de88a46b 90 (void) memset(frame_buffer_4, 0, sizeof(frame_buffer_4));
1050186 4:2672de88a46b 91 p_tft->tft_info[DSP_TFT_LAYER_0].p_disp_buf = &frame_buffer_1[0];
1050186 4:2672de88a46b 92 p_tft->tft_info[DSP_TFT_LAYER_0].p_back_buf = &frame_buffer_2[0];
1050186 4:2672de88a46b 93 p_tft->tft_info[DSP_TFT_LAYER_1].p_disp_buf = &frame_buffer_3[0];
1050186 4:2672de88a46b 94 p_tft->tft_info[DSP_TFT_LAYER_1].p_back_buf = &frame_buffer_4[0];
1050186 4:2672de88a46b 95 for (i = 0u; i < DSP_TFT_LAYER_NUM; i++) {
1050186 4:2672de88a46b 96 p_tft->tft_info[i].width = DSP_TFT_WIDTH;
1050186 4:2672de88a46b 97 p_tft->tft_info[i].height = DSP_TFT_HEIGHT;
1050186 4:2672de88a46b 98 p_tft->tft_info[i].stride = BUF_STRIDE;
1050186 4:2672de88a46b 99 }
1050186 4:2672de88a46b 100 init_lcd_driver(p_tft);
1050186 4:2672de88a46b 101 dsp_init_tft_scrn(p_tft);
1050186 4:2672de88a46b 102 }
1050186 4:2672de88a46b 103 }
1050186 4:2672de88a46b 104
1050186 4:2672de88a46b 105 void dsp_output_tft(const DSP_MAIL_ID mail_id,
1050186 4:2672de88a46b 106 const dsp_com_ctrl_t * const p_com, dsp_tft_ctrl_t * const p_tft)
1050186 4:2672de88a46b 107 {
1050186 4:2672de88a46b 108 uint32_t result = DSP_TFT_LAYER_NON;
1050186 4:2672de88a46b 109
1050186 4:2672de88a46b 110 if ((p_com != NULL) && (p_tft != NULL)) {
1050186 4:2672de88a46b 111 switch (mail_id) {
1050186 4:2672de88a46b 112 case DSP_MAILID_CYCLE_IND :
1050186 4:2672de88a46b 113 /* Executes main function of the playback screen. */
1050186 4:2672de88a46b 114 result = dsp_make_tft_scrn(p_com, p_tft);
1050186 4:2672de88a46b 115 break;
1050186 4:2672de88a46b 116 case DSP_MAILID_PLAY_TIME :
1050186 4:2672de88a46b 117 case DSP_MAILID_PLAY_INFO :
1050186 4:2672de88a46b 118 case DSP_MAILID_PLAY_STAT :
1050186 4:2672de88a46b 119 if (p_com->edge_track_change == true) {
1050186 4:2672de88a46b 120 dsp_clear_tft_audio_data(p_tft);
1050186 4:2672de88a46b 121 }
1050186 4:2672de88a46b 122 result = DSP_TFT_LAYER_NON;
1050186 4:2672de88a46b 123 break;
1050186 4:2672de88a46b 124 case DSP_MAILID_AUDIO_FIN:
1050186 4:2672de88a46b 125 update_tft_audio_data(p_com, p_tft);
1050186 4:2672de88a46b 126 result = DSP_TFT_LAYER_NON;
1050186 4:2672de88a46b 127 break;
1050186 4:2672de88a46b 128 case DSP_MAILID_CMD_STR :
1050186 4:2672de88a46b 129 case DSP_MAILID_PRINT_STR :
1050186 4:2672de88a46b 130 case DSP_MAILID_FILE_NAME :
1050186 4:2672de88a46b 131 default :
1050186 4:2672de88a46b 132 result = DSP_TFT_LAYER_NON;
1050186 4:2672de88a46b 133 break;
1050186 4:2672de88a46b 134 }
1050186 4:2672de88a46b 135 if (result < DSP_TFT_LAYER_NUM) {
1050186 4:2672de88a46b 136 /* Updates the TFT display. */
1050186 4:2672de88a46b 137 update_tft_display(p_tft, result);
1050186 4:2672de88a46b 138 }
1050186 4:2672de88a46b 139 }
1050186 4:2672de88a46b 140 }
1050186 4:2672de88a46b 141
1050186 4:2672de88a46b 142 SYS_KeyCode dsp_convert_key_tft(const uint32_t disp_mode, const uint32_t pos_x, const uint32_t pos_y)
1050186 4:2672de88a46b 143 {
1050186 4:2672de88a46b 144 SYS_KeyCode ret;
1050186 4:2672de88a46b 145
1050186 4:2672de88a46b 146 switch (disp_mode) {
1050186 4:2672de88a46b 147 case DSP_DISPMODE_1:
1050186 4:2672de88a46b 148 case DSP_DISPMODE_2:
1050186 4:2672de88a46b 149 case DSP_DISPMODE_3:
1050186 4:2672de88a46b 150 ret = dsp_convert_key_tft_scrn(pos_x, pos_y);
1050186 4:2672de88a46b 151 break;
1050186 4:2672de88a46b 152 default:
1050186 4:2672de88a46b 153 ret = SYS_KEYCODE_NON;
1050186 4:2672de88a46b 154 break;
1050186 4:2672de88a46b 155 }
1050186 4:2672de88a46b 156 return ret;
1050186 4:2672de88a46b 157 }
1050186 4:2672de88a46b 158
1050186 4:2672de88a46b 159 void dsp_clear_tft_audio_data(dsp_tft_ctrl_t * const p_tft)
1050186 4:2672de88a46b 160 {
1050186 4:2672de88a46b 161 dsp_audio_t *p_aud;
1050186 4:2672de88a46b 162
1050186 4:2672de88a46b 163 if (p_tft != NULL) {
1050186 4:2672de88a46b 164 p_aud = &p_tft->audio_data;
1050186 4:2672de88a46b 165 p_aud->m2_buf_cnt = 0u;
1050186 4:2672de88a46b 166 (void) memset(&p_aud->m2_buf[0], 0u, sizeof(p_aud->m2_buf));
1050186 4:2672de88a46b 167 p_aud->m3_buf_cnt = 0u;
1050186 4:2672de88a46b 168 (void) memset(&p_aud->m3_buf[0], 0u, sizeof(p_aud->m3_buf));
1050186 4:2672de88a46b 169 p_aud->m3_sample_cnt = 0u;
1050186 4:2672de88a46b 170 p_aud->m3_target_cnt = 0u;
1050186 4:2672de88a46b 171 p_aud->m3_pause_flag = false;
1050186 4:2672de88a46b 172 }
1050186 4:2672de88a46b 173 }
1050186 4:2672de88a46b 174
1050186 4:2672de88a46b 175 /** Initializes LCD driver using DisplayBase class.
1050186 4:2672de88a46b 176 *
1050186 4:2672de88a46b 177 * @param p_tft Pointer to management data of TFT module.
1050186 4:2672de88a46b 178 */
1050186 4:2672de88a46b 179 static void init_lcd_driver(const dsp_tft_ctrl_t * const p_tft)
1050186 4:2672de88a46b 180 {
1050186 4:2672de88a46b 181 DisplayBase::graphics_error_t grap_err;
1050186 4:2672de88a46b 182 DisplayBase::rect_t rect;
1050186 4:2672de88a46b 183 DisplayBase::lcd_config_t lcd_config = {
1050186 4:2672de88a46b 184 DisplayBase::LCD_TYPE_LVDS, /* LVDS or Pararel RGB */
1050186 4:2672de88a46b 185 LCD_INPUT_CLK, /* P1 clk [MHz] */
1050186 4:2672de88a46b 186 LCD_OUTPUT_CLK, /* LCD clk [MHz] */
1050186 4:2672de88a46b 187
1050186 4:2672de88a46b 188 DisplayBase::LCD_OUTFORMAT_RGB888, /* Output format select */
1050186 4:2672de88a46b 189 DisplayBase::EDGE_RISING, /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
1050186 4:2672de88a46b 190
1050186 4:2672de88a46b 191 LCD_HSYNC_PERIOD, /* Free-running Hsync period */
1050186 4:2672de88a46b 192 LCD_VSYNC_PERIOD, /* Free-running Vsync period */
1050186 4:2672de88a46b 193 (uint16_t)DSP_TFT_WIDTH, /* LCD display area size, horizontal width */
1050186 4:2672de88a46b 194 (uint16_t)DSP_TFT_HEIGHT, /* LCD display area size, vertical width */
1050186 4:2672de88a46b 195 LCD_H_BACK_PORCH, /* LCD display horizontal back porch period */
1050186 4:2672de88a46b 196 LCD_V_BACK_PORCH, /* LCD display vertical back porch period */
1050186 4:2672de88a46b 197
1050186 4:2672de88a46b 198 DisplayBase::LCD_TCON_PIN_NON, /* TCONn or Not use(-1) */
1050186 4:2672de88a46b 199 DisplayBase::SIG_POL_NOT_INVERTED, /* Polarity inversion control of signal */
1050186 4:2672de88a46b 200 0, /* Hsync width */
1050186 4:2672de88a46b 201
1050186 4:2672de88a46b 202 DisplayBase::LCD_TCON_PIN_NON, /* TCONn or Not use(-1) */
1050186 4:2672de88a46b 203 DisplayBase::SIG_POL_NOT_INVERTED, /* Polarity inversion control of signal */
1050186 4:2672de88a46b 204 0, /* Vsync width */
1050186 4:2672de88a46b 205
1050186 4:2672de88a46b 206 DisplayBase::LCD_TCON_PIN_3, /* TCONn or Not use(-1) */
1050186 4:2672de88a46b 207 DisplayBase::SIG_POL_NOT_INVERTED /* Polarity inversion control of signal */
1050186 4:2672de88a46b 208 };
1050186 4:2672de88a46b 209 PinName lvds_pin[LCD_PIN_NUM] = {
1050186 4:2672de88a46b 210 P5_7, P5_6, P5_5, P5_4, P5_3, P5_2, P5_1, P5_0 /* Data pin */
1050186 4:2672de88a46b 211 };
1050186 4:2672de88a46b 212 static DigitalOut lcd_pwon(P7_15);
1050186 4:2672de88a46b 213 static DigitalOut lcd_blon(P8_1);
1050186 4:2672de88a46b 214 static PwmOut lcd_cntrst(P8_15);
1050186 4:2672de88a46b 215 uint32_t i;
1050186 4:2672de88a46b 216 DisplayBase::graphics_layer_t layer_id;
1050186 4:2672de88a46b 217
1050186 4:2672de88a46b 218 if (p_tft != NULL) {
1050186 4:2672de88a46b 219 lcd_pwon.write(1); /* LCD panel power ON. */
1050186 4:2672de88a46b 220 /* Graphics initialization process */
1050186 4:2672de88a46b 221 grap_err = lcd.Graphics_init(&lcd_config);
1050186 4:2672de88a46b 222 if (grap_err == DisplayBase::GRAPHICS_OK) {
1050186 4:2672de88a46b 223 /* Interrupt callback function setting (Vsync signal output from scaler 0) */
1050186 4:2672de88a46b 224 grap_err = lcd.Graphics_Irq_Handler_Set(DisplayBase::INT_TYPE_S0_LO_VSYNC, 0, &vsync_callback);
1050186 4:2672de88a46b 225 if (grap_err == DisplayBase::GRAPHICS_OK) {
1050186 4:2672de88a46b 226 lcd.Graphics_Lvds_Port_Init(lvds_pin, LCD_PIN_NUM);
1050186 4:2672de88a46b 227 rect.vs = 0;
1050186 4:2672de88a46b 228 rect.vw = (uint16_t)DSP_TFT_HEIGHT;
1050186 4:2672de88a46b 229 rect.hs = 0;
1050186 4:2672de88a46b 230 rect.hw = (uint16_t)DSP_TFT_WIDTH;
1050186 4:2672de88a46b 231 for (i = 0u; i < DSP_TFT_LAYER_NUM; i++) {
1050186 4:2672de88a46b 232 layer_id = convert_layer_id(i);
1050186 4:2672de88a46b 233 lcd.Graphics_Read_Setting(layer_id, (void *)p_tft->tft_info[i].p_disp_buf,
1050186 4:2672de88a46b 234 BUF_STRIDE, DisplayBase::GRAPHICS_FORMAT_ARGB8888,
1050186 4:2672de88a46b 235 DisplayBase::WR_RD_WRSWA_32BIT, &rect);
1050186 4:2672de88a46b 236 lcd.Graphics_Start(layer_id);
1050186 4:2672de88a46b 237 }
1050186 4:2672de88a46b 238
1050186 4:2672de88a46b 239 Thread::wait(BLON_WAIT_TIME_MS);
1050186 4:2672de88a46b 240 lcd_blon.write(1); /* LCD panel backlight ON. */
1050186 4:2672de88a46b 241 lcd_cntrst.write(1.0);
1050186 4:2672de88a46b 242 }
1050186 4:2672de88a46b 243 }
1050186 4:2672de88a46b 244 }
1050186 4:2672de88a46b 245 }
1050186 4:2672de88a46b 246
1050186 4:2672de88a46b 247 /** Interrupt callback function for Vsync interruption.
1050186 4:2672de88a46b 248 *
1050186 4:2672de88a46b 249 * @param int_type The number of VDC5 interrupt types
1050186 4:2672de88a46b 250 */
1050186 4:2672de88a46b 251 static void vsync_callback(DisplayBase::int_type_t int_type)
1050186 4:2672de88a46b 252 {
1050186 4:2672de88a46b 253 UNUSED_ARG(int_type);
1050186 4:2672de88a46b 254 (void) dsp_notify_cycle_time();
1050186 4:2672de88a46b 255 }
1050186 4:2672de88a46b 256
1050186 4:2672de88a46b 257 /** Updates the display of the specified layer.
1050186 4:2672de88a46b 258 *
1050186 4:2672de88a46b 259 * @param p_tft Pointer to management data of TFT module.
1050186 4:2672de88a46b 260 * @param layer_id The number of the display layer of TFT module.
1050186 4:2672de88a46b 261 */
1050186 4:2672de88a46b 262 static void update_tft_display(dsp_tft_ctrl_t * const p_tft, const uint32_t layer_id)
1050186 4:2672de88a46b 263 {
1050186 4:2672de88a46b 264 DisplayBase::graphics_layer_t result;
1050186 4:2672de88a46b 265 DisplayBase::graphics_error_t grap_err;
1050186 4:2672de88a46b 266
1050186 4:2672de88a46b 267 if ((p_tft != NULL) && (layer_id < DSP_TFT_LAYER_NUM)) {
1050186 4:2672de88a46b 268 result = convert_layer_id(layer_id);
1050186 4:2672de88a46b 269 grap_err = lcd.Graphics_Read_Change(result, p_tft->tft_info[layer_id].p_back_buf);
1050186 4:2672de88a46b 270 if (grap_err == DisplayBase::GRAPHICS_OK) {
1050186 4:2672de88a46b 271 swap_frame_buffer(&p_tft->tft_info[layer_id]);
1050186 4:2672de88a46b 272 }
1050186 4:2672de88a46b 273 }
1050186 4:2672de88a46b 274 }
1050186 4:2672de88a46b 275
1050186 4:2672de88a46b 276 /** Updates the audio data.
1050186 4:2672de88a46b 277 *
1050186 4:2672de88a46b 278 * @param p_com Pointer to common data in all display module.
1050186 4:2672de88a46b 279 * @param p_tft Pointer to management data of TFT module.
1050186 4:2672de88a46b 280 */
1050186 4:2672de88a46b 281 static void update_tft_audio_data(const dsp_com_ctrl_t * const p_com, dsp_tft_ctrl_t * const p_tft)
1050186 4:2672de88a46b 282 {
1050186 4:2672de88a46b 283 dsp_audio_t *p_aud;
1050186 4:2672de88a46b 284 uint32_t i;
1050186 4:2672de88a46b 285 uint32_t buf_id;
1050186 4:2672de88a46b 286 int32_t total_val;
1050186 4:2672de88a46b 287 bool update_flag;
1050186 4:2672de88a46b 288 int16_t new_data[DSP_TFT_M3_AUDIO_SAMPLE_PER_100MS];
1050186 4:2672de88a46b 289 uint32_t valid_data;
1050186 4:2672de88a46b 290
1050186 4:2672de88a46b 291 if ((p_com != NULL) && (p_tft != NULL)) {
1050186 4:2672de88a46b 292 p_aud = &p_tft->audio_data;
1050186 4:2672de88a46b 293 /* Stores the display data using the display mode 2. */
1050186 4:2672de88a46b 294 (void) memcpy(&p_aud->m2_buf[0], &p_aud->req_buf[0], sizeof(p_aud->m2_buf));
1050186 4:2672de88a46b 295 p_aud->m2_buf_cnt = sizeof(p_aud->m2_buf)/sizeof(p_aud->m2_buf[0]);
1050186 4:2672de88a46b 296 /* Stores the display data using the display mode 3. */
1050186 4:2672de88a46b 297 buf_id = 0u;
1050186 4:2672de88a46b 298 valid_data = 0u;
1050186 4:2672de88a46b 299 for (i = 0u; i < DSP_TFT_M3_AUDIO_SAMPLE_PER_100MS; i++) {
1050186 4:2672de88a46b 300 /* Calculates the average of 2 channels. */
1050186 4:2672de88a46b 301 total_val = p_aud->req_buf[buf_id] + p_aud->req_buf[buf_id + 1u];
1050186 4:2672de88a46b 302 new_data[i] = (int16_t)((uint32_t)total_val >> SHIFT_1BIT_SIZE);
1050186 4:2672de88a46b 303 buf_id += (DSP_TFT_M2_AUDIO_BUF_SIZE / DSP_TFT_M3_AUDIO_SAMPLE_PER_100MS);
1050186 4:2672de88a46b 304 /* Checks the zero data */
1050186 4:2672de88a46b 305 valid_data |= (uint32_t)new_data[i];
1050186 4:2672de88a46b 306 }
1050186 4:2672de88a46b 307 update_flag = false;
1050186 4:2672de88a46b 308 if (p_com->play_stat == SYS_PLAYSTAT_PAUSE) {
1050186 4:2672de88a46b 309 p_aud->m3_pause_flag = true;
1050186 4:2672de88a46b 310 if (valid_data == 0u) {
1050186 4:2672de88a46b 311 /* Current sampling data are not used. */
1050186 4:2672de88a46b 312 } else {
1050186 4:2672de88a46b 313 update_flag = true;
1050186 4:2672de88a46b 314 }
1050186 4:2672de88a46b 315 } else if (p_com->play_stat == SYS_PLAYSTAT_PLAY) {
1050186 4:2672de88a46b 316 if ((p_aud->m3_pause_flag == true) &&
1050186 4:2672de88a46b 317 (p_aud->m3_sample_cnt > (p_aud->m3_target_cnt + DSP_TFT_M3_AUDIO_SAMPLE_PER_100MS))) {
1050186 4:2672de88a46b 318 /* Current sampling data are not used. */
1050186 4:2672de88a46b 319 } else if ((p_aud->m3_pause_flag == true) && (valid_data == 0u)) {
1050186 4:2672de88a46b 320 /* Current sampling data are not used. */
1050186 4:2672de88a46b 321 p_aud->m3_pause_flag = false;
1050186 4:2672de88a46b 322 } else {
1050186 4:2672de88a46b 323 update_flag = true;
1050186 4:2672de88a46b 324 p_aud->m3_pause_flag = false;
1050186 4:2672de88a46b 325 }
1050186 4:2672de88a46b 326 } else {
1050186 4:2672de88a46b 327 p_aud->m3_pause_flag = false;
1050186 4:2672de88a46b 328 }
1050186 4:2672de88a46b 329 if (update_flag == true) {
1050186 4:2672de88a46b 330 if (p_aud->m3_buf_cnt >= DSP_TFT_M3_AUDIO_BUF_SIZE) {
1050186 4:2672de88a46b 331 p_aud->m3_buf_cnt = DSP_TFT_M3_AUDIO_BUF_SIZE - DSP_TFT_M3_AUDIO_SAMPLE_PER_100MS;
1050186 4:2672de88a46b 332 for (i = 0u; i < p_aud->m3_buf_cnt; i++) {
1050186 4:2672de88a46b 333 p_aud->m3_buf[i] = p_aud->m3_buf[i + DSP_TFT_M3_AUDIO_SAMPLE_PER_100MS];
1050186 4:2672de88a46b 334 }
1050186 4:2672de88a46b 335 }
1050186 4:2672de88a46b 336 for (i = 0u; i < DSP_TFT_M3_AUDIO_SAMPLE_PER_100MS; i++) {
1050186 4:2672de88a46b 337 p_aud->m3_buf[p_aud->m3_buf_cnt] = new_data[i];
1050186 4:2672de88a46b 338 p_aud->m3_buf_cnt++;
1050186 4:2672de88a46b 339 }
1050186 4:2672de88a46b 340 p_aud->m3_sample_cnt += DSP_TFT_M3_AUDIO_SAMPLE_PER_100MS;
1050186 4:2672de88a46b 341 p_aud->m3_target_cnt += DSP_TFT_M3_AUDIO_SAMPLE_PER_100MS;
1050186 4:2672de88a46b 342 }
1050186 4:2672de88a46b 343 }
1050186 4:2672de88a46b 344 }
1050186 4:2672de88a46b 345
1050186 4:2672de88a46b 346 /** Converts the layer number of TFT module into the layer number of DisplayBase class.
1050186 4:2672de88a46b 347 *
1050186 4:2672de88a46b 348 * @param layer_id The number of the display layer of TFT module.
1050186 4:2672de88a46b 349 *
1050186 4:2672de88a46b 350 * @returns
1050186 4:2672de88a46b 351 * Returns the layer number of DisplayBase class.
1050186 4:2672de88a46b 352 */
1050186 4:2672de88a46b 353 static DisplayBase::graphics_layer_t convert_layer_id(const uint32_t layer_id)
1050186 4:2672de88a46b 354 {
1050186 4:2672de88a46b 355 DisplayBase::graphics_layer_t ret;
1050186 4:2672de88a46b 356
1050186 4:2672de88a46b 357 switch (layer_id) {
1050186 4:2672de88a46b 358 case DSP_TFT_LAYER_1:
1050186 4:2672de88a46b 359 ret = DisplayBase::GRAPHICS_LAYER_1;
1050186 4:2672de88a46b 360 break;
1050186 4:2672de88a46b 361 case DSP_TFT_LAYER_0:
1050186 4:2672de88a46b 362 default:
1050186 4:2672de88a46b 363 ret = DisplayBase::GRAPHICS_LAYER_0;
1050186 4:2672de88a46b 364 break;
1050186 4:2672de88a46b 365 }
1050186 4:2672de88a46b 366 return ret;
1050186 4:2672de88a46b 367 }
1050186 4:2672de88a46b 368
1050186 4:2672de88a46b 369 /** Swaps the frame buffers
1050186 4:2672de88a46b 370 *
1050186 4:2672de88a46b 371 * @param p_info Pointer to VRAM structure
1050186 4:2672de88a46b 372 */
1050186 4:2672de88a46b 373 static void swap_frame_buffer(dsp_tftlayer_t * const p_info)
1050186 4:2672de88a46b 374 {
1050186 4:2672de88a46b 375 uint32_t *p_tmp;
1050186 4:2672de88a46b 376
1050186 4:2672de88a46b 377 if (p_info != NULL) {
1050186 4:2672de88a46b 378 p_tmp = p_info->p_disp_buf;
1050186 4:2672de88a46b 379 p_info->p_disp_buf = p_info->p_back_buf;
1050186 4:2672de88a46b 380 p_info->p_back_buf = p_tmp;
1050186 4:2672de88a46b 381 }
1050186 4:2672de88a46b 382 }