r_vdc5_register_address.c

00001 /*******************************************************************************
00002 * DISCLAIMER
00003 * This software is supplied by Renesas Electronics Corporation and is only
00004 * intended for use with Renesas products. No other uses are authorized. This
00005 * software is owned by Renesas Electronics Corporation and is protected under
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00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
00016 * Renesas reserves the right, without notice, to make changes to this software
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00018 * you agree to the additional terms and conditions found by accessing the
00019 * following link:
00020 * http://www.renesas.com/disclaimer
00021 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
00022 *******************************************************************************/
00023 /**************************************************************************//**
00024 * @file         r_vdc5_register_address.c
00025 * @version      1.00
00026 * $Rev: 199 $
00027 * $Date:: 2014-05-23 16:33:52 +0900#$
00028 * @brief        VDC5 driver register address table
00029 ******************************************************************************/
00030 
00031 /******************************************************************************
00032 Includes   <System Includes> , "Project Includes"
00033 ******************************************************************************/
00034 #include    "r_vdc5.h"
00035 #include    "r_vdc5_user.h"
00036 #include    "r_vdc5_register.h"
00037 
00038 
00039 /******************************************************************************
00040 Macro definitions
00041 ******************************************************************************/
00042 #define     VDC5_CH0_GR0_CLUT_TBL           (*(uint32_t*)0xFCFF6000u)
00043 #define     VDC5_CH0_GR1_CLUT_TBL           (*(uint32_t*)0xFCFF6400u)
00044 #define     VDC5_CH0_GR2_CLUT_TBL           (*(uint32_t*)0xFCFF6800u)
00045 #define     VDC5_CH0_GR3_CLUT_TBL           (*(uint32_t*)0xFCFF6C00u)
00046 #define     VDC5_CH0_GR_OIR_CLUT_TBL        (*(uint32_t*)0xFCFF7000u)
00047 #define     VDC5_CH1_GR0_CLUT_TBL           (*(uint32_t*)0xFCFF8000u)
00048 #define     VDC5_CH1_GR1_CLUT_TBL           (*(uint32_t*)0xFCFF8400u)
00049 #define     VDC5_CH1_GR2_CLUT_TBL           (*(uint32_t*)0xFCFF8800u)
00050 #define     VDC5_CH1_GR3_CLUT_TBL           (*(uint32_t*)0xFCFF8C00u)
00051 #define     VDC5_CH1_GR_OIR_CLUT_TBL        (*(uint32_t*)0xFCFF9000u)
00052 
00053 
00054 /******************************************************************************
00055 Typedef definitions
00056 ******************************************************************************/
00057 
00058 /******************************************************************************
00059 Exported global variables and functions (to be accessed by other files)
00060 ******************************************************************************/
00061 /* VDC5 input controller register address list */
00062 const vdc5_regaddr_input_ctrl_t  vdc5_regaddr_input_ctrl[VDC5_CHANNEL_NUM ] = {
00063     {   /* Channel 0 */
00064         &VDC50.INP_UPDATE,
00065         &VDC50.INP_SEL_CNT,
00066         &VDC50.INP_EXT_SYNC_CNT,
00067         &VDC50.INP_VSYNC_PH_ADJ,
00068         &VDC50.INP_DLY_ADJ,
00069         &VDC50.IMGCNT_UPDATE,
00070         &VDC50.IMGCNT_NR_CNT0,
00071         &VDC50.IMGCNT_NR_CNT1
00072     },
00073     {   /* Channel 1 */
00074         &VDC51.INP_UPDATE,
00075         &VDC51.INP_SEL_CNT,
00076         &VDC51.INP_EXT_SYNC_CNT,
00077         &VDC51.INP_VSYNC_PH_ADJ,
00078         &VDC51.INP_DLY_ADJ,
00079         &VDC51.IMGCNT_UPDATE,
00080         &VDC51.IMGCNT_NR_CNT0,
00081         &VDC51.IMGCNT_NR_CNT1
00082     }
00083 };
00084 
00085 /* VDC5 scaler register address list */
00086 const vdc5_regaddr_scaler_t  vdc5_regaddr_scaler[VDC5_CHANNEL_NUM ][VDC5_SC_TYPE_NUM ] = {
00087     {   /* Channel 0 */
00088         {   /* SC0 */
00089             &VDC50.SC0_SCL0_UPDATE,
00090             &VDC50.SC0_SCL0_FRC1,
00091             &VDC50.SC0_SCL0_FRC2,
00092             &VDC50.SC0_SCL0_FRC3,
00093             &VDC50.SC0_SCL0_FRC4,
00094             &VDC50.SC0_SCL0_FRC5,
00095             &VDC50.SC0_SCL0_FRC6,
00096             &VDC50.SC0_SCL0_FRC7,
00097             &VDC50.SC0_SCL0_FRC9,
00098             &VDC50.SC0_SCL0_MON0,
00099             &VDC50.SC0_SCL0_INT,
00100             &VDC50.SC0_SCL0_DS1,
00101             &VDC50.SC0_SCL0_DS2,
00102             &VDC50.SC0_SCL0_DS3,
00103             &VDC50.SC0_SCL0_DS4,
00104             &VDC50.SC0_SCL0_DS5,
00105             &VDC50.SC0_SCL0_DS6,
00106             &VDC50.SC0_SCL0_DS7,
00107             &VDC50.SC0_SCL0_US1,
00108             &VDC50.SC0_SCL0_US2,
00109             &VDC50.SC0_SCL0_US3,
00110             &VDC50.SC0_SCL0_US4,
00111             &VDC50.SC0_SCL0_US5,
00112             &VDC50.SC0_SCL0_US6,
00113             &VDC50.SC0_SCL0_US7,
00114             &VDC50.SC0_SCL0_US8,
00115             &VDC50.SC0_SCL0_OVR1,
00116             &VDC50.SC0_SCL1_UPDATE,
00117             &VDC50.SC0_SCL1_WR1,
00118             &VDC50.SC0_SCL1_WR2,
00119             &VDC50.SC0_SCL1_WR3,
00120             &VDC50.SC0_SCL1_WR4,
00121             &VDC50.SC0_SCL1_WR5,
00122             &VDC50.SC0_SCL1_WR6,
00123             &VDC50.SC0_SCL1_WR7,
00124             &VDC50.SC0_SCL1_WR8,
00125             &VDC50.SC0_SCL1_WR9,
00126             &VDC50.SC0_SCL1_WR10,
00127             &VDC50.SC0_SCL1_WR11,
00128             &VDC50.SC0_SCL1_MON1,
00129             &VDC50.SC0_SCL1_PBUF0,
00130             &VDC50.SC0_SCL1_PBUF1,
00131             &VDC50.SC0_SCL1_PBUF2,
00132             &VDC50.SC0_SCL1_PBUF3,
00133             &VDC50.SC0_SCL1_PBUF_FLD,
00134             &VDC50.SC0_SCL1_PBUF_CNT
00135         },
00136         {   /* SC1 */
00137             &VDC50.SC1_SCL0_UPDATE,
00138             &VDC50.SC1_SCL0_FRC1,
00139             &VDC50.SC1_SCL0_FRC2,
00140             &VDC50.SC1_SCL0_FRC3,
00141             &VDC50.SC1_SCL0_FRC4,
00142             &VDC50.SC1_SCL0_FRC5,
00143             &VDC50.SC1_SCL0_FRC6,
00144             &VDC50.SC1_SCL0_FRC7,
00145             &VDC50.SC1_SCL0_FRC9,
00146             &VDC50.SC1_SCL0_MON0,
00147             &VDC50.SC1_SCL0_INT,
00148             &VDC50.SC1_SCL0_DS1,
00149             &VDC50.SC1_SCL0_DS2,
00150             &VDC50.SC1_SCL0_DS3,
00151             &VDC50.SC1_SCL0_DS4,
00152             &VDC50.SC1_SCL0_DS5,
00153             &VDC50.SC1_SCL0_DS6,
00154             &VDC50.SC1_SCL0_DS7,
00155             &VDC50.SC1_SCL0_US1,
00156             &VDC50.SC1_SCL0_US2,
00157             &VDC50.SC1_SCL0_US3,
00158             &VDC50.SC1_SCL0_US4,
00159             &VDC50.SC1_SCL0_US5,
00160             &VDC50.SC1_SCL0_US6,
00161             &VDC50.SC1_SCL0_US7,
00162             &VDC50.SC1_SCL0_US8,
00163             &VDC50.SC1_SCL0_OVR1,
00164             &VDC50.SC1_SCL1_UPDATE,
00165             &VDC50.SC1_SCL1_WR1,
00166             &VDC50.SC1_SCL1_WR2,
00167             &VDC50.SC1_SCL1_WR3,
00168             &VDC50.SC1_SCL1_WR4,
00169             &VDC50.SC1_SCL1_WR5,
00170             &VDC50.SC1_SCL1_WR6,
00171             &VDC50.SC1_SCL1_WR7,
00172             &VDC50.SC1_SCL1_WR8,
00173             &VDC50.SC1_SCL1_WR9,
00174             &VDC50.SC1_SCL1_WR10,
00175             &VDC50.SC1_SCL1_WR11,
00176             &VDC50.SC1_SCL1_MON1,
00177             &VDC50.SC1_SCL1_PBUF0,
00178             &VDC50.SC1_SCL1_PBUF1,
00179             &VDC50.SC1_SCL1_PBUF2,
00180             &VDC50.SC1_SCL1_PBUF3,
00181             &VDC50.SC1_SCL1_PBUF_FLD,
00182             &VDC50.SC1_SCL1_PBUF_CNT
00183         },
00184         {   /* OIR */
00185             &VDC50.OIR_SCL0_UPDATE,
00186             &VDC50.OIR_SCL0_FRC1,
00187             &VDC50.OIR_SCL0_FRC2,
00188             &VDC50.OIR_SCL0_FRC3,
00189             &VDC50.OIR_SCL0_FRC4,
00190             &VDC50.OIR_SCL0_FRC5,
00191             &VDC50.OIR_SCL0_FRC6,
00192             &VDC50.OIR_SCL0_FRC7,
00193             NULL,
00194             NULL,
00195             NULL,
00196             &VDC50.OIR_SCL0_DS1,
00197             &VDC50.OIR_SCL0_DS2,
00198             &VDC50.OIR_SCL0_DS3,
00199             NULL,
00200             NULL,
00201             NULL,
00202             &VDC50.OIR_SCL0_DS7,
00203             &VDC50.OIR_SCL0_US1,
00204             &VDC50.OIR_SCL0_US2,
00205             &VDC50.OIR_SCL0_US3,
00206             NULL,
00207             NULL,
00208             NULL,
00209             NULL,
00210             &VDC50.OIR_SCL0_US8,
00211             &VDC50.OIR_SCL0_OVR1,
00212             &VDC50.OIR_SCL1_UPDATE,
00213             &VDC50.OIR_SCL1_WR1,
00214             &VDC50.OIR_SCL1_WR2,
00215             &VDC50.OIR_SCL1_WR3,
00216             &VDC50.OIR_SCL1_WR4,
00217             &VDC50.OIR_SCL1_WR5,
00218             &VDC50.OIR_SCL1_WR6,
00219             &VDC50.OIR_SCL1_WR7,
00220             NULL,
00221             NULL,
00222             NULL,
00223             NULL,
00224             NULL,
00225             NULL,
00226             NULL,
00227             NULL,
00228             NULL,
00229             NULL,
00230             NULL
00231         }
00232     },
00233     {   /* Channel 1 */
00234         {   /* SC0 */
00235             &VDC51.SC0_SCL0_UPDATE,
00236             &VDC51.SC0_SCL0_FRC1,
00237             &VDC51.SC0_SCL0_FRC2,
00238             &VDC51.SC0_SCL0_FRC3,
00239             &VDC51.SC0_SCL0_FRC4,
00240             &VDC51.SC0_SCL0_FRC5,
00241             &VDC51.SC0_SCL0_FRC6,
00242             &VDC51.SC0_SCL0_FRC7,
00243             &VDC51.SC0_SCL0_FRC9,
00244             &VDC51.SC0_SCL0_MON0,
00245             &VDC51.SC0_SCL0_INT,
00246             &VDC51.SC0_SCL0_DS1,
00247             &VDC51.SC0_SCL0_DS2,
00248             &VDC51.SC0_SCL0_DS3,
00249             &VDC51.SC0_SCL0_DS4,
00250             &VDC51.SC0_SCL0_DS5,
00251             &VDC51.SC0_SCL0_DS6,
00252             &VDC51.SC0_SCL0_DS7,
00253             &VDC51.SC0_SCL0_US1,
00254             &VDC51.SC0_SCL0_US2,
00255             &VDC51.SC0_SCL0_US3,
00256             &VDC51.SC0_SCL0_US4,
00257             &VDC51.SC0_SCL0_US5,
00258             &VDC51.SC0_SCL0_US6,
00259             &VDC51.SC0_SCL0_US7,
00260             &VDC51.SC0_SCL0_US8,
00261             &VDC51.SC0_SCL0_OVR1,
00262             &VDC51.SC0_SCL1_UPDATE,
00263             &VDC51.SC0_SCL1_WR1,
00264             &VDC51.SC0_SCL1_WR2,
00265             &VDC51.SC0_SCL1_WR3,
00266             &VDC51.SC0_SCL1_WR4,
00267             &VDC51.SC0_SCL1_WR5,
00268             &VDC51.SC0_SCL1_WR6,
00269             &VDC51.SC0_SCL1_WR7,
00270             &VDC51.SC0_SCL1_WR8,
00271             &VDC51.SC0_SCL1_WR9,
00272             &VDC51.SC0_SCL1_WR10,
00273             &VDC51.SC0_SCL1_WR11,
00274             &VDC51.SC0_SCL1_MON1,
00275             &VDC51.SC0_SCL1_PBUF0,
00276             &VDC51.SC0_SCL1_PBUF1,
00277             &VDC51.SC0_SCL1_PBUF2,
00278             &VDC51.SC0_SCL1_PBUF3,
00279             &VDC51.SC0_SCL1_PBUF_FLD,
00280             &VDC51.SC0_SCL1_PBUF_CNT
00281         },
00282         {   /* SC1 */
00283             &VDC51.SC1_SCL0_UPDATE,
00284             &VDC51.SC1_SCL0_FRC1,
00285             &VDC51.SC1_SCL0_FRC2,
00286             &VDC51.SC1_SCL0_FRC3,
00287             &VDC51.SC1_SCL0_FRC4,
00288             &VDC51.SC1_SCL0_FRC5,
00289             &VDC51.SC1_SCL0_FRC6,
00290             &VDC51.SC1_SCL0_FRC7,
00291             &VDC51.SC1_SCL0_FRC9,
00292             &VDC51.SC1_SCL0_MON0,
00293             &VDC51.SC1_SCL0_INT,
00294             &VDC51.SC1_SCL0_DS1,
00295             &VDC51.SC1_SCL0_DS2,
00296             &VDC51.SC1_SCL0_DS3,
00297             &VDC51.SC1_SCL0_DS4,
00298             &VDC51.SC1_SCL0_DS5,
00299             &VDC51.SC1_SCL0_DS6,
00300             &VDC51.SC1_SCL0_DS7,
00301             &VDC51.SC1_SCL0_US1,
00302             &VDC51.SC1_SCL0_US2,
00303             &VDC51.SC1_SCL0_US3,
00304             &VDC51.SC1_SCL0_US4,
00305             &VDC51.SC1_SCL0_US5,
00306             &VDC51.SC1_SCL0_US6,
00307             &VDC51.SC1_SCL0_US7,
00308             &VDC51.SC1_SCL0_US8,
00309             &VDC51.SC1_SCL0_OVR1,
00310             &VDC51.SC1_SCL1_UPDATE,
00311             &VDC51.SC1_SCL1_WR1,
00312             &VDC51.SC1_SCL1_WR2,
00313             &VDC51.SC1_SCL1_WR3,
00314             &VDC51.SC1_SCL1_WR4,
00315             &VDC51.SC1_SCL1_WR5,
00316             &VDC51.SC1_SCL1_WR6,
00317             &VDC51.SC1_SCL1_WR7,
00318             &VDC51.SC1_SCL1_WR8,
00319             &VDC51.SC1_SCL1_WR9,
00320             &VDC51.SC1_SCL1_WR10,
00321             &VDC51.SC1_SCL1_WR11,
00322             &VDC51.SC1_SCL1_MON1,
00323             &VDC51.SC1_SCL1_PBUF0,
00324             &VDC51.SC1_SCL1_PBUF1,
00325             &VDC51.SC1_SCL1_PBUF2,
00326             &VDC51.SC1_SCL1_PBUF3,
00327             &VDC51.SC1_SCL1_PBUF_FLD,
00328             &VDC51.SC1_SCL1_PBUF_CNT
00329         },
00330         {   /* OIR */
00331             &VDC51.OIR_SCL0_UPDATE,
00332             &VDC51.OIR_SCL0_FRC1,
00333             &VDC51.OIR_SCL0_FRC2,
00334             &VDC51.OIR_SCL0_FRC3,
00335             &VDC51.OIR_SCL0_FRC4,
00336             &VDC51.OIR_SCL0_FRC5,
00337             &VDC51.OIR_SCL0_FRC6,
00338             &VDC51.OIR_SCL0_FRC7,
00339             NULL,
00340             NULL,
00341             NULL,
00342             &VDC51.OIR_SCL0_DS1,
00343             &VDC51.OIR_SCL0_DS2,
00344             &VDC51.OIR_SCL0_DS3,
00345             NULL,
00346             NULL,
00347             NULL,
00348             &VDC51.OIR_SCL0_DS7,
00349             &VDC51.OIR_SCL0_US1,
00350             &VDC51.OIR_SCL0_US2,
00351             &VDC51.OIR_SCL0_US3,
00352             NULL,
00353             NULL,
00354             NULL,
00355             NULL,
00356             &VDC51.OIR_SCL0_US8,
00357             &VDC51.OIR_SCL0_OVR1,
00358             &VDC51.OIR_SCL1_UPDATE,
00359             &VDC51.OIR_SCL1_WR1,
00360             &VDC51.OIR_SCL1_WR2,
00361             &VDC51.OIR_SCL1_WR3,
00362             &VDC51.OIR_SCL1_WR4,
00363             &VDC51.OIR_SCL1_WR5,
00364             &VDC51.OIR_SCL1_WR6,
00365             &VDC51.OIR_SCL1_WR7,
00366             NULL,
00367             NULL,
00368             NULL,
00369             NULL,
00370             NULL,
00371             NULL,
00372             NULL,
00373             NULL,
00374             NULL,
00375             NULL,
00376             NULL
00377         }
00378     }
00379 };
00380 
00381 /* VDC5 image quality improver register address list */
00382 const vdc5_regaddr_img_qlty_imp_t  vdc5_regaddr_img_qlty_imp[VDC5_CHANNEL_NUM ][VDC5_IMG_IMPRV_NUM ] = {
00383     {   /* Channel 0 */
00384         {   /* SC0 */
00385             &VDC50.ADJ0_UPDATE,
00386             &VDC50.ADJ0_BKSTR_SET,
00387             &VDC50.ADJ0_ENH_TIM1,
00388             &VDC50.ADJ0_ENH_TIM2,
00389             &VDC50.ADJ0_ENH_TIM3,
00390             &VDC50.ADJ0_ENH_SHP1,
00391             &VDC50.ADJ0_ENH_SHP2,
00392             &VDC50.ADJ0_ENH_SHP3,
00393             &VDC50.ADJ0_ENH_SHP4,
00394             &VDC50.ADJ0_ENH_SHP5,
00395             &VDC50.ADJ0_ENH_SHP6,
00396             &VDC50.ADJ0_ENH_LTI1,
00397             &VDC50.ADJ0_ENH_LTI2
00398         },
00399         {   /* SC1 */
00400             &VDC50.ADJ1_UPDATE,
00401             &VDC50.ADJ1_BKSTR_SET,
00402             &VDC50.ADJ1_ENH_TIM1,
00403             &VDC50.ADJ1_ENH_TIM2,
00404             &VDC50.ADJ1_ENH_TIM3,
00405             &VDC50.ADJ1_ENH_SHP1,
00406             &VDC50.ADJ1_ENH_SHP2,
00407             &VDC50.ADJ1_ENH_SHP3,
00408             &VDC50.ADJ1_ENH_SHP4,
00409             &VDC50.ADJ1_ENH_SHP5,
00410             &VDC50.ADJ1_ENH_SHP6,
00411             &VDC50.ADJ1_ENH_LTI1,
00412             &VDC50.ADJ1_ENH_LTI2
00413         }
00414     },
00415     {   /* Channel 1 */
00416         {   /* SC0 */
00417             &VDC51.ADJ0_UPDATE,
00418             &VDC51.ADJ0_BKSTR_SET,
00419             &VDC51.ADJ0_ENH_TIM1,
00420             &VDC51.ADJ0_ENH_TIM2,
00421             &VDC51.ADJ0_ENH_TIM3,
00422             &VDC51.ADJ0_ENH_SHP1,
00423             &VDC51.ADJ0_ENH_SHP2,
00424             &VDC51.ADJ0_ENH_SHP3,
00425             &VDC51.ADJ0_ENH_SHP4,
00426             &VDC51.ADJ0_ENH_SHP5,
00427             &VDC51.ADJ0_ENH_SHP6,
00428             &VDC51.ADJ0_ENH_LTI1,
00429             &VDC51.ADJ0_ENH_LTI2
00430         },
00431         {   /* SC1 */
00432             &VDC51.ADJ1_UPDATE,
00433             &VDC51.ADJ1_BKSTR_SET,
00434             &VDC51.ADJ1_ENH_TIM1,
00435             &VDC51.ADJ1_ENH_TIM2,
00436             &VDC51.ADJ1_ENH_TIM3,
00437             &VDC51.ADJ1_ENH_SHP1,
00438             &VDC51.ADJ1_ENH_SHP2,
00439             &VDC51.ADJ1_ENH_SHP3,
00440             &VDC51.ADJ1_ENH_SHP4,
00441             &VDC51.ADJ1_ENH_SHP5,
00442             &VDC51.ADJ1_ENH_SHP6,
00443             &VDC51.ADJ1_ENH_LTI1,
00444             &VDC51.ADJ1_ENH_LTI2
00445         }
00446     }
00447 };
00448 
00449 /* VDC5 color matrix register address list */
00450 const vdc5_regaddr_color_matrix_t  vdc5_regaddr_color_matrix[VDC5_CHANNEL_NUM ][VDC5_COLORMTX_NUM] = {
00451     {   /* Channel 0 */
00452         {   /* Input Controller */
00453             &VDC50.IMGCNT_UPDATE,
00454             &VDC50.IMGCNT_MTX_MODE,
00455             &VDC50.IMGCNT_MTX_YG_ADJ0,
00456             &VDC50.IMGCNT_MTX_YG_ADJ1,
00457             &VDC50.IMGCNT_MTX_CBB_ADJ0,
00458             &VDC50.IMGCNT_MTX_CBB_ADJ1,
00459             &VDC50.IMGCNT_MTX_CRR_ADJ0,
00460             &VDC50.IMGCNT_MTX_CRR_ADJ1
00461         },
00462         {   /* Image quality improver 0 */
00463             &VDC50.ADJ0_UPDATE,
00464             &VDC50.ADJ0_MTX_MODE,
00465             &VDC50.ADJ0_MTX_YG_ADJ0,
00466             &VDC50.ADJ0_MTX_YG_ADJ1,
00467             &VDC50.ADJ0_MTX_CBB_ADJ0,
00468             &VDC50.ADJ0_MTX_CBB_ADJ1,
00469             &VDC50.ADJ0_MTX_CRR_ADJ0,
00470             &VDC50.ADJ0_MTX_CRR_ADJ1
00471         },
00472         {   /* Image quality improver 1 */
00473             &VDC50.ADJ1_UPDATE,
00474             &VDC50.ADJ1_MTX_MODE,
00475             &VDC50.ADJ1_MTX_YG_ADJ0,
00476             &VDC50.ADJ1_MTX_YG_ADJ1,
00477             &VDC50.ADJ1_MTX_CBB_ADJ0,
00478             &VDC50.ADJ1_MTX_CBB_ADJ1,
00479             &VDC50.ADJ1_MTX_CRR_ADJ0,
00480             &VDC50.ADJ1_MTX_CRR_ADJ1
00481         }
00482     },
00483     {   /* Channel 1 */
00484         {   /* Input Controller */
00485             &VDC51.IMGCNT_UPDATE,
00486             &VDC51.IMGCNT_MTX_MODE,
00487             &VDC51.IMGCNT_MTX_YG_ADJ0,
00488             &VDC51.IMGCNT_MTX_YG_ADJ1,
00489             &VDC51.IMGCNT_MTX_CBB_ADJ0,
00490             &VDC51.IMGCNT_MTX_CBB_ADJ1,
00491             &VDC51.IMGCNT_MTX_CRR_ADJ0,
00492             &VDC51.IMGCNT_MTX_CRR_ADJ1
00493         },
00494         {   /* Image quality improver 0 */
00495             &VDC51.ADJ0_UPDATE,
00496             &VDC51.ADJ0_MTX_MODE,
00497             &VDC51.ADJ0_MTX_YG_ADJ0,
00498             &VDC51.ADJ0_MTX_YG_ADJ1,
00499             &VDC51.ADJ0_MTX_CBB_ADJ0,
00500             &VDC51.ADJ0_MTX_CBB_ADJ1,
00501             &VDC51.ADJ0_MTX_CRR_ADJ0,
00502             &VDC51.ADJ0_MTX_CRR_ADJ1
00503         },
00504         {   /* Image quality improver 1 */
00505             &VDC51.ADJ1_UPDATE,
00506             &VDC51.ADJ1_MTX_MODE,
00507             &VDC51.ADJ1_MTX_YG_ADJ0,
00508             &VDC51.ADJ1_MTX_YG_ADJ1,
00509             &VDC51.ADJ1_MTX_CBB_ADJ0,
00510             &VDC51.ADJ1_MTX_CBB_ADJ1,
00511             &VDC51.ADJ1_MTX_CRR_ADJ0,
00512             &VDC51.ADJ1_MTX_CRR_ADJ1
00513         }
00514     }
00515 };
00516 
00517 /* VDC5 image synthesizer register address list */
00518 const vdc5_regaddr_img_synthesizer_t  vdc5_regaddr_img_synthesizer[VDC5_CHANNEL_NUM ][VDC5_GR_TYPE_NUM ] = {
00519     {   /* Channel 0 */
00520         {   /* GR0 */
00521             &VDC50.GR0_UPDATE,
00522             &VDC50.GR0_FLM_RD,
00523             &VDC50.GR0_FLM1,
00524             &VDC50.GR0_FLM2,
00525             &VDC50.GR0_FLM3,
00526             &VDC50.GR0_FLM4,
00527             &VDC50.GR0_FLM5,
00528             &VDC50.GR0_FLM6,
00529             &VDC50.GR0_AB1,
00530             &VDC50.GR0_AB2,
00531             &VDC50.GR0_AB3,
00532             NULL,
00533             NULL,
00534             NULL,
00535             &VDC50.GR0_AB7,
00536             &VDC50.GR0_AB8,
00537             &VDC50.GR0_AB9,
00538             &VDC50.GR0_AB10,
00539             &VDC50.GR0_AB11,
00540             &VDC50.GR0_BASE,
00541             &VDC50.GR0_CLUT,
00542             NULL
00543         },
00544         {   /* GR1 */
00545             &VDC50.GR1_UPDATE,
00546             &VDC50.GR1_FLM_RD,
00547             &VDC50.GR1_FLM1,
00548             &VDC50.GR1_FLM2,
00549             &VDC50.GR1_FLM3,
00550             &VDC50.GR1_FLM4,
00551             &VDC50.GR1_FLM5,
00552             &VDC50.GR1_FLM6,
00553             &VDC50.GR1_AB1,
00554             &VDC50.GR1_AB2,
00555             &VDC50.GR1_AB3,
00556             &VDC50.GR1_AB4,
00557             &VDC50.GR1_AB5,
00558             &VDC50.GR1_AB6,
00559             &VDC50.GR1_AB7,
00560             &VDC50.GR1_AB8,
00561             &VDC50.GR1_AB9,
00562             &VDC50.GR1_AB10,
00563             &VDC50.GR1_AB11,
00564             &VDC50.GR1_BASE,
00565             &VDC50.GR1_CLUT,
00566             &VDC50.GR1_MON
00567         },
00568         {   /* GR2 */
00569             &VDC50.GR2_UPDATE,
00570             &VDC50.GR2_FLM_RD,
00571             &VDC50.GR2_FLM1,
00572             &VDC50.GR2_FLM2,
00573             &VDC50.GR2_FLM3,
00574             &VDC50.GR2_FLM4,
00575             &VDC50.GR2_FLM5,
00576             &VDC50.GR2_FLM6,
00577             &VDC50.GR2_AB1,
00578             &VDC50.GR2_AB2,
00579             &VDC50.GR2_AB3,
00580             &VDC50.GR2_AB4,
00581             &VDC50.GR2_AB5,
00582             &VDC50.GR2_AB6,
00583             &VDC50.GR2_AB7,
00584             &VDC50.GR2_AB8,
00585             &VDC50.GR2_AB9,
00586             &VDC50.GR2_AB10,
00587             &VDC50.GR2_AB11,
00588             &VDC50.GR2_BASE,
00589             &VDC50.GR2_CLUT,
00590             &VDC50.GR2_MON
00591         },
00592         {   /* GR3 */
00593             &VDC50.GR3_UPDATE,
00594             &VDC50.GR3_FLM_RD,
00595             &VDC50.GR3_FLM1,
00596             &VDC50.GR3_FLM2,
00597             &VDC50.GR3_FLM3,
00598             &VDC50.GR3_FLM4,
00599             &VDC50.GR3_FLM5,
00600             &VDC50.GR3_FLM6,
00601             &VDC50.GR3_AB1,
00602             &VDC50.GR3_AB2,
00603             &VDC50.GR3_AB3,
00604             &VDC50.GR3_AB4,
00605             &VDC50.GR3_AB5,
00606             &VDC50.GR3_AB6,
00607             &VDC50.GR3_AB7,
00608             &VDC50.GR3_AB8,
00609             &VDC50.GR3_AB9,
00610             &VDC50.GR3_AB10,
00611             &VDC50.GR3_AB11,
00612             &VDC50.GR3_BASE,
00613             &VDC50.GR3_CLUT_INT,
00614             &VDC50.GR3_MON
00615         },
00616         {   /* VIN */
00617             &VDC50.GR_VIN_UPDATE,
00618             NULL,
00619             NULL,
00620             NULL,
00621             NULL,
00622             NULL,
00623             NULL,
00624             NULL,
00625             &VDC50.GR_VIN_AB1,
00626             &VDC50.GR_VIN_AB2,
00627             &VDC50.GR_VIN_AB3,
00628             &VDC50.GR_VIN_AB4,
00629             &VDC50.GR_VIN_AB5,
00630             &VDC50.GR_VIN_AB6,
00631             &VDC50.GR_VIN_AB7,
00632             NULL,
00633             NULL,
00634             NULL,
00635             NULL,
00636             &VDC50.GR_VIN_BASE,
00637             NULL,
00638             &VDC50.GR_VIN_MON
00639         },
00640         {   /* OIR */
00641             &VDC50.GR_OIR_UPDATE,
00642             &VDC50.GR_OIR_FLM_RD,
00643             &VDC50.GR_OIR_FLM1,
00644             &VDC50.GR_OIR_FLM2,
00645             &VDC50.GR_OIR_FLM3,
00646             &VDC50.GR_OIR_FLM4,
00647             &VDC50.GR_OIR_FLM5,
00648             &VDC50.GR_OIR_FLM6,
00649             &VDC50.GR_OIR_AB1,
00650             &VDC50.GR_OIR_AB2,
00651             &VDC50.GR_OIR_AB3,
00652             NULL,
00653             NULL,
00654             NULL,
00655             &VDC50.GR_OIR_AB7,
00656             &VDC50.GR_OIR_AB8,
00657             &VDC50.GR_OIR_AB9,
00658             &VDC50.GR_OIR_AB10,
00659             &VDC50.GR_OIR_AB11,
00660             &VDC50.GR_OIR_BASE,
00661             &VDC50.GR_OIR_CLUT,
00662             &VDC50.GR_OIR_MON
00663         }
00664     },
00665     {   /* Channel 1 */
00666         {   /* GR0 */
00667             &VDC51.GR0_UPDATE,
00668             &VDC51.GR0_FLM_RD,
00669             &VDC51.GR0_FLM1,
00670             &VDC51.GR0_FLM2,
00671             &VDC51.GR0_FLM3,
00672             &VDC51.GR0_FLM4,
00673             &VDC51.GR0_FLM5,
00674             &VDC51.GR0_FLM6,
00675             &VDC51.GR0_AB1,
00676             &VDC51.GR0_AB2,
00677             &VDC51.GR0_AB3,
00678             NULL,
00679             NULL,
00680             NULL,
00681             &VDC51.GR0_AB7,
00682             &VDC51.GR0_AB8,
00683             &VDC51.GR0_AB9,
00684             &VDC51.GR0_AB10,
00685             &VDC51.GR0_AB11,
00686             &VDC51.GR0_BASE,
00687             &VDC51.GR0_CLUT,
00688             NULL
00689         },
00690         {   /* GR1 */
00691             &VDC51.GR1_UPDATE,
00692             &VDC51.GR1_FLM_RD,
00693             &VDC51.GR1_FLM1,
00694             &VDC51.GR1_FLM2,
00695             &VDC51.GR1_FLM3,
00696             &VDC51.GR1_FLM4,
00697             &VDC51.GR1_FLM5,
00698             &VDC51.GR1_FLM6,
00699             &VDC51.GR1_AB1,
00700             &VDC51.GR1_AB2,
00701             &VDC51.GR1_AB3,
00702             &VDC51.GR1_AB4,
00703             &VDC51.GR1_AB5,
00704             &VDC51.GR1_AB6,
00705             &VDC51.GR1_AB7,
00706             &VDC51.GR1_AB8,
00707             &VDC51.GR1_AB9,
00708             &VDC51.GR1_AB10,
00709             &VDC51.GR1_AB11,
00710             &VDC51.GR1_BASE,
00711             &VDC51.GR1_CLUT,
00712             &VDC51.GR1_MON
00713         },
00714         {   /* GR2 */
00715             &VDC51.GR2_UPDATE,
00716             &VDC51.GR2_FLM_RD,
00717             &VDC51.GR2_FLM1,
00718             &VDC51.GR2_FLM2,
00719             &VDC51.GR2_FLM3,
00720             &VDC51.GR2_FLM4,
00721             &VDC51.GR2_FLM5,
00722             &VDC51.GR2_FLM6,
00723             &VDC51.GR2_AB1,
00724             &VDC51.GR2_AB2,
00725             &VDC51.GR2_AB3,
00726             &VDC51.GR2_AB4,
00727             &VDC51.GR2_AB5,
00728             &VDC51.GR2_AB6,
00729             &VDC51.GR2_AB7,
00730             &VDC51.GR2_AB8,
00731             &VDC51.GR2_AB9,
00732             &VDC51.GR2_AB10,
00733             &VDC51.GR2_AB11,
00734             &VDC51.GR2_BASE,
00735             &VDC51.GR2_CLUT,
00736             &VDC51.GR2_MON
00737         },
00738         {   /* GR3 */
00739             &VDC51.GR3_UPDATE,
00740             &VDC51.GR3_FLM_RD,
00741             &VDC51.GR3_FLM1,
00742             &VDC51.GR3_FLM2,
00743             &VDC51.GR3_FLM3,
00744             &VDC51.GR3_FLM4,
00745             &VDC51.GR3_FLM5,
00746             &VDC51.GR3_FLM6,
00747             &VDC51.GR3_AB1,
00748             &VDC51.GR3_AB2,
00749             &VDC51.GR3_AB3,
00750             &VDC51.GR3_AB4,
00751             &VDC51.GR3_AB5,
00752             &VDC51.GR3_AB6,
00753             &VDC51.GR3_AB7,
00754             &VDC51.GR3_AB8,
00755             &VDC51.GR3_AB9,
00756             &VDC51.GR3_AB10,
00757             &VDC51.GR3_AB11,
00758             &VDC51.GR3_BASE,
00759             &VDC51.GR3_CLUT_INT,
00760             &VDC51.GR3_MON
00761         },
00762         {   /* VIN */
00763             &VDC51.GR_VIN_UPDATE,
00764             NULL,
00765             NULL,
00766             NULL,
00767             NULL,
00768             NULL,
00769             NULL,
00770             NULL,
00771             &VDC51.GR_VIN_AB1,
00772             &VDC51.GR_VIN_AB2,
00773             &VDC51.GR_VIN_AB3,
00774             &VDC51.GR_VIN_AB4,
00775             &VDC51.GR_VIN_AB5,
00776             &VDC51.GR_VIN_AB6,
00777             &VDC51.GR_VIN_AB7,
00778             NULL,
00779             NULL,
00780             NULL,
00781             NULL,
00782             &VDC51.GR_VIN_BASE,
00783             NULL,
00784             &VDC51.GR_VIN_MON
00785         },
00786         {   /* OIR */
00787             &VDC51.GR_OIR_UPDATE,
00788             &VDC51.GR_OIR_FLM_RD,
00789             &VDC51.GR_OIR_FLM1,
00790             &VDC51.GR_OIR_FLM2,
00791             &VDC51.GR_OIR_FLM3,
00792             &VDC51.GR_OIR_FLM4,
00793             &VDC51.GR_OIR_FLM5,
00794             &VDC51.GR_OIR_FLM6,
00795             &VDC51.GR_OIR_AB1,
00796             &VDC51.GR_OIR_AB2,
00797             &VDC51.GR_OIR_AB3,
00798             NULL,
00799             NULL,
00800             NULL,
00801             &VDC51.GR_OIR_AB7,
00802             &VDC51.GR_OIR_AB8,
00803             &VDC51.GR_OIR_AB9,
00804             &VDC51.GR_OIR_AB10,
00805             &VDC51.GR_OIR_AB11,
00806             &VDC51.GR_OIR_BASE,
00807             &VDC51.GR_OIR_CLUT,
00808             &VDC51.GR_OIR_MON
00809         }
00810     }
00811 };
00812 
00813 /* VDC5 CLUT register address list */
00814 uint32_t * const vdc5_regaddr_clut[VDC5_CHANNEL_NUM ][VDC5_GR_TYPE_NUM ] = {
00815     {   /* Channel 0 */
00816         &VDC5_CH0_GR0_CLUT_TBL,
00817         &VDC5_CH0_GR1_CLUT_TBL,
00818         &VDC5_CH0_GR2_CLUT_TBL,
00819         &VDC5_CH0_GR3_CLUT_TBL,
00820         NULL,
00821         &VDC5_CH0_GR_OIR_CLUT_TBL
00822     },
00823     {   /* Channel 1 */
00824         &VDC5_CH1_GR0_CLUT_TBL,
00825         &VDC5_CH1_GR1_CLUT_TBL,
00826         &VDC5_CH1_GR2_CLUT_TBL,
00827         &VDC5_CH1_GR3_CLUT_TBL,
00828         NULL,
00829         &VDC5_CH1_GR_OIR_CLUT_TBL
00830     }
00831 };
00832 
00833 /* VDC5 output controller register address list */
00834 const vdc5_regaddr_output_ctrl_t  vdc5_regaddr_output_ctrl[VDC5_CHANNEL_NUM ] = {
00835     {   /* Channel 0 */
00836         &VDC50.TCON_UPDATE,
00837         &VDC50.TCON_TIM,
00838         &VDC50.TCON_TIM_STVA1,
00839         &VDC50.TCON_TIM_STVA2,
00840         &VDC50.TCON_TIM_STVB1,
00841         &VDC50.TCON_TIM_STVB2,
00842         &VDC50.TCON_TIM_STH1,
00843         &VDC50.TCON_TIM_STH2,
00844         &VDC50.TCON_TIM_STB1,
00845         &VDC50.TCON_TIM_STB2,
00846         &VDC50.TCON_TIM_CPV1,
00847         &VDC50.TCON_TIM_CPV2,
00848         &VDC50.TCON_TIM_POLA1,
00849         &VDC50.TCON_TIM_POLA2,
00850         &VDC50.TCON_TIM_POLB1,
00851         &VDC50.TCON_TIM_POLB2,
00852         &VDC50.TCON_TIM_DE,
00853         &VDC50.OUT_UPDATE,
00854         &VDC50.OUT_SET,
00855         &VDC50.OUT_BRIGHT1,
00856         &VDC50.OUT_BRIGHT2,
00857         &VDC50.OUT_CONTRAST,
00858         &VDC50.OUT_PDTHA,
00859         &VDC50.OUT_CLK_PHASE
00860     },
00861     {   /* Channel 1 */
00862         &VDC51.TCON_UPDATE,
00863         &VDC51.TCON_TIM,
00864         &VDC51.TCON_TIM_STVA1,
00865         &VDC51.TCON_TIM_STVA2,
00866         &VDC51.TCON_TIM_STVB1,
00867         &VDC51.TCON_TIM_STVB2,
00868         &VDC51.TCON_TIM_STH1,
00869         &VDC51.TCON_TIM_STH2,
00870         &VDC51.TCON_TIM_STB1,
00871         &VDC51.TCON_TIM_STB2,
00872         &VDC51.TCON_TIM_CPV1,
00873         &VDC51.TCON_TIM_CPV2,
00874         &VDC51.TCON_TIM_POLA1,
00875         &VDC51.TCON_TIM_POLA2,
00876         &VDC51.TCON_TIM_POLB1,
00877         &VDC51.TCON_TIM_POLB2,
00878         &VDC51.TCON_TIM_DE,
00879         &VDC51.OUT_UPDATE,
00880         &VDC51.OUT_SET,
00881         &VDC51.OUT_BRIGHT1,
00882         &VDC51.OUT_BRIGHT2,
00883         &VDC51.OUT_CONTRAST,
00884         &VDC51.OUT_PDTHA,
00885         &VDC51.OUT_CLK_PHASE
00886     }
00887 };
00888 
00889 /* VDC5 gamma correction register address list */
00890 const vdc5_regaddr_gamma_t  vdc5_regaddr_gamma[VDC5_CHANNEL_NUM ] = {
00891     {   /* Channel 0 */
00892         &VDC50.GAM_SW,
00893         &VDC50.GAM_G_UPDATE,
00894         {
00895             &VDC50.GAM_G_LUT1,
00896             &VDC50.GAM_G_LUT2,
00897             &VDC50.GAM_G_LUT3,
00898             &VDC50.GAM_G_LUT4,
00899             &VDC50.GAM_G_LUT5,
00900             &VDC50.GAM_G_LUT6,
00901             &VDC50.GAM_G_LUT7,
00902             &VDC50.GAM_G_LUT8,
00903             &VDC50.GAM_G_LUT9,
00904             &VDC50.GAM_G_LUT10,
00905             &VDC50.GAM_G_LUT11,
00906             &VDC50.GAM_G_LUT12,
00907             &VDC50.GAM_G_LUT13,
00908             &VDC50.GAM_G_LUT14,
00909             &VDC50.GAM_G_LUT15,
00910             &VDC50.GAM_G_LUT16
00911         },
00912         {
00913             &VDC50.GAM_G_AREA1,
00914             &VDC50.GAM_G_AREA2,
00915             &VDC50.GAM_G_AREA3,
00916             &VDC50.GAM_G_AREA4,
00917             &VDC50.GAM_G_AREA5,
00918             &VDC50.GAM_G_AREA6,
00919             &VDC50.GAM_G_AREA7,
00920             &VDC50.GAM_G_AREA8
00921         },
00922         &VDC50.GAM_B_UPDATE,
00923         {
00924             &VDC50.GAM_B_LUT1,
00925             &VDC50.GAM_B_LUT2,
00926             &VDC50.GAM_B_LUT3,
00927             &VDC50.GAM_B_LUT4,
00928             &VDC50.GAM_B_LUT5,
00929             &VDC50.GAM_B_LUT6,
00930             &VDC50.GAM_B_LUT7,
00931             &VDC50.GAM_B_LUT8,
00932             &VDC50.GAM_B_LUT9,
00933             &VDC50.GAM_B_LUT10,
00934             &VDC50.GAM_B_LUT11,
00935             &VDC50.GAM_B_LUT12,
00936             &VDC50.GAM_B_LUT13,
00937             &VDC50.GAM_B_LUT14,
00938             &VDC50.GAM_B_LUT15,
00939             &VDC50.GAM_B_LUT16
00940         },
00941         {
00942             &VDC50.GAM_B_AREA1,
00943             &VDC50.GAM_B_AREA2,
00944             &VDC50.GAM_B_AREA3,
00945             &VDC50.GAM_B_AREA4,
00946             &VDC50.GAM_B_AREA5,
00947             &VDC50.GAM_B_AREA6,
00948             &VDC50.GAM_B_AREA7,
00949             &VDC50.GAM_B_AREA8
00950         },
00951         &VDC50.GAM_R_UPDATE,
00952         {
00953             &VDC50.GAM_R_LUT1,
00954             &VDC50.GAM_R_LUT2,
00955             &VDC50.GAM_R_LUT3,
00956             &VDC50.GAM_R_LUT4,
00957             &VDC50.GAM_R_LUT5,
00958             &VDC50.GAM_R_LUT6,
00959             &VDC50.GAM_R_LUT7,
00960             &VDC50.GAM_R_LUT8,
00961             &VDC50.GAM_R_LUT9,
00962             &VDC50.GAM_R_LUT10,
00963             &VDC50.GAM_R_LUT11,
00964             &VDC50.GAM_R_LUT12,
00965             &VDC50.GAM_R_LUT13,
00966             &VDC50.GAM_R_LUT14,
00967             &VDC50.GAM_R_LUT15,
00968             &VDC50.GAM_R_LUT16
00969         },
00970         {
00971             &VDC50.GAM_R_AREA1,
00972             &VDC50.GAM_R_AREA2,
00973             &VDC50.GAM_R_AREA3,
00974             &VDC50.GAM_R_AREA4,
00975             &VDC50.GAM_R_AREA5,
00976             &VDC50.GAM_R_AREA6,
00977             &VDC50.GAM_R_AREA7,
00978             &VDC50.GAM_R_AREA8
00979         }
00980     },
00981     {   /* Channel 1 */
00982         &VDC51.GAM_SW,
00983         &VDC51.GAM_G_UPDATE,
00984         {
00985             &VDC51.GAM_G_LUT1,
00986             &VDC51.GAM_G_LUT2,
00987             &VDC51.GAM_G_LUT3,
00988             &VDC51.GAM_G_LUT4,
00989             &VDC51.GAM_G_LUT5,
00990             &VDC51.GAM_G_LUT6,
00991             &VDC51.GAM_G_LUT7,
00992             &VDC51.GAM_G_LUT8,
00993             &VDC51.GAM_G_LUT9,
00994             &VDC51.GAM_G_LUT10,
00995             &VDC51.GAM_G_LUT11,
00996             &VDC51.GAM_G_LUT12,
00997             &VDC51.GAM_G_LUT13,
00998             &VDC51.GAM_G_LUT14,
00999             &VDC51.GAM_G_LUT15,
01000             &VDC51.GAM_G_LUT16
01001         },
01002         {
01003             &VDC51.GAM_G_AREA1,
01004             &VDC51.GAM_G_AREA2,
01005             &VDC51.GAM_G_AREA3,
01006             &VDC51.GAM_G_AREA4,
01007             &VDC51.GAM_G_AREA5,
01008             &VDC51.GAM_G_AREA6,
01009             &VDC51.GAM_G_AREA7,
01010             &VDC51.GAM_G_AREA8
01011         },
01012         &VDC51.GAM_B_UPDATE,
01013         {
01014             &VDC51.GAM_B_LUT1,
01015             &VDC51.GAM_B_LUT2,
01016             &VDC51.GAM_B_LUT3,
01017             &VDC51.GAM_B_LUT4,
01018             &VDC51.GAM_B_LUT5,
01019             &VDC51.GAM_B_LUT6,
01020             &VDC51.GAM_B_LUT7,
01021             &VDC51.GAM_B_LUT8,
01022             &VDC51.GAM_B_LUT9,
01023             &VDC51.GAM_B_LUT10,
01024             &VDC51.GAM_B_LUT11,
01025             &VDC51.GAM_B_LUT12,
01026             &VDC51.GAM_B_LUT13,
01027             &VDC51.GAM_B_LUT14,
01028             &VDC51.GAM_B_LUT15,
01029             &VDC51.GAM_B_LUT16
01030         },
01031         {
01032             &VDC51.GAM_B_AREA1,
01033             &VDC51.GAM_B_AREA2,
01034             &VDC51.GAM_B_AREA3,
01035             &VDC51.GAM_B_AREA4,
01036             &VDC51.GAM_B_AREA5,
01037             &VDC51.GAM_B_AREA6,
01038             &VDC51.GAM_B_AREA7,
01039             &VDC51.GAM_B_AREA8
01040         },
01041         &VDC51.GAM_R_UPDATE,
01042         {
01043             &VDC51.GAM_R_LUT1,
01044             &VDC51.GAM_R_LUT2,
01045             &VDC51.GAM_R_LUT3,
01046             &VDC51.GAM_R_LUT4,
01047             &VDC51.GAM_R_LUT5,
01048             &VDC51.GAM_R_LUT6,
01049             &VDC51.GAM_R_LUT7,
01050             &VDC51.GAM_R_LUT8,
01051             &VDC51.GAM_R_LUT9,
01052             &VDC51.GAM_R_LUT10,
01053             &VDC51.GAM_R_LUT11,
01054             &VDC51.GAM_R_LUT12,
01055             &VDC51.GAM_R_LUT13,
01056             &VDC51.GAM_R_LUT14,
01057             &VDC51.GAM_R_LUT15,
01058             &VDC51.GAM_R_LUT16
01059         },
01060         {
01061             &VDC51.GAM_R_AREA1,
01062             &VDC51.GAM_R_AREA2,
01063             &VDC51.GAM_R_AREA3,
01064             &VDC51.GAM_R_AREA4,
01065             &VDC51.GAM_R_AREA5,
01066             &VDC51.GAM_R_AREA6,
01067             &VDC51.GAM_R_AREA7,
01068             &VDC51.GAM_R_AREA8
01069         }
01070     }
01071 };
01072 
01073 /* VDC5 system controller register address list */
01074 const vdc5_regaddr_system_ctrl_t  vdc5_regaddr_system_ctrl[VDC5_CHANNEL_NUM ] = {
01075     {   /* Channel 0 */
01076         &VDC50.SYSCNT_INT1,
01077         &VDC50.SYSCNT_INT2,
01078         &VDC50.SYSCNT_INT3,
01079         &VDC50.SYSCNT_INT4,
01080         &VDC50.SYSCNT_INT5,
01081         &VDC50.SYSCNT_INT6,
01082         &VDC50.SYSCNT_PANEL_CLK,
01083         &VDC50.SYSCNT_CLUT
01084     },
01085     {   /* Channel 1 */
01086         &VDC51.SYSCNT_INT1,
01087         &VDC51.SYSCNT_INT2,
01088         &VDC51.SYSCNT_INT3,
01089         &VDC51.SYSCNT_INT4,
01090         &VDC51.SYSCNT_INT5,
01091         &VDC51.SYSCNT_INT6,
01092         &VDC51.SYSCNT_PANEL_CLK,
01093         &VDC51.SYSCNT_CLUT
01094     }
01095 };
01096 
01097 /* LVDS register address list */
01098 const vdc5_regaddr_lvds_t  vdc5_regaddr_lvds = {
01099     &LVDS.LVDS_UPDATE,
01100     &LVDS.LVDSFCL,
01101     &LVDS.LCLKSELR,
01102     &LVDS.LPLLSETR,
01103     &LVDS.LPHYACC
01104 };
01105