lcd_gr_peach_ch0.h

00001 /*******************************************************************************
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00021 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
00022 *******************************************************************************/
00023 /**************************************************************************//**
00024 * @file         lcd_gr_peach_ch0.h
00025 * @version      1.00
00026 * $Rev: 199 $
00027 * $Date:: 2014-05-23 16:33:52 +0900#$
00028 * @brief        LCD panel for vdc5 channel 0 definition header
00029 ******************************************************************************/
00030 
00031 #ifndef LCD_GR_PEACH_CH0_H
00032 #define LCD_GR_PEACH_CH0_H
00033 
00034 #ifndef LCD_PANEL_H
00035 #error  Do not include this file directly!
00036 #else
00037 /******************************************************************************
00038 Includes   <System Includes> , "Project Includes"
00039 ******************************************************************************/
00040 #include    <stdlib.h>
00041 
00042 #include    "r_typedefs.h"
00043 
00044 #include    "r_vdc5.h"
00045 
00046 
00047 /******************************************************************************
00048 Macro definitions
00049 ******************************************************************************/
00050 /* Not support */
00051 #define     LCD_CH0_DISP_HS         (128u)                      /* LCD display area size, horizontal start position */
00052 #define     LCD_CH0_DISP_HW         (800u)                      /* LCD display area size, horizontal width */
00053 #define     LCD_CH0_DISP_VS         (10u)                       /* LCD display area size, vertical start position */
00054 #define     LCD_CH0_DISP_VW         (480u)                      /* LCD display area size, height (vertical width) */
00055 #define     LCD_CH0_SIG_FV          (525u - 1u)                 /* Free-running Vsync period */
00056 #define     LCD_CH0_SIG_FH          (1056u - 1u)                /* Hsync period */
00057 /* Pixel data is latched in the falling edge of pixel clock.
00058    Therefore, pixel data should be output from VDC5 at the rising edge of the clock. */
00059 #define     LCD_CH0_OUT_EDGE        VDC5_EDGE_RISING            /* Output phase control of LCD_DATA[23:0] signal */
00060 #define     LCD_CH0_OUT_FORMAT      VDC5_LCD_OUTFORMAT_RGB666   /* LCD output format select */
00061 
00062 #define     LCD_CH0_PANEL_CLK       VDC5_PANEL_ICKSEL_PERI      /* Panel clock select */
00063 #define     LCD_CH0_PANEL_CLK_DIV   VDC5_PANEL_CLKDIV_1_2       /* Panel clock frequency division ratio */
00064 
00065 #define     LCD_CH0_TCON_HALF       (LCD_CH0_SIG_FH / 2u)       /* TCON reference timing, 1/2fH timing */
00066 #define     LCD_CH0_TCON_OFFSET     (0u)                        /* TCON reference timing, offset Hsync signal timing */
00067 
00068 
00069 /******************************************************************************
00070 Typedef definitions
00071 ******************************************************************************/
00072 
00073 /******************************************************************************
00074 Exported global functions (to be accessed by other files)
00075 ******************************************************************************/
00076 void GRAPHICS_SetLcdPanel_Ch0(void);
00077 void GRAPHICS_SetLcdTconSettings_Ch0(const vdc5_lcd_tcon_timing_t  * * const outctrl);
00078 
00079 
00080 #endif  /* LCD_PANEL_H not defined */
00081 #endif  /* LCD_GR_PEACH_CH0_H */