Renesas GR-PEACH OpenCV Development
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gr-peach-opencv-project-sd-card_update
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DisplayBace.h
00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer 00021 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 /**************************************************************************//** 00024 * @file DisplayBase.h 00025 * @brief Display driver wrapper class for GR-PEACH 00026 ******************************************************************************/ 00027 00028 #ifndef MBED_DISPLAYBASE_H 00029 #define MBED_DISPLAYBASE_H 00030 00031 #include "pinmap.h" 00032 00033 /*! @class DisplayBase 00034 * @brief Display driver wrapper class for GR-PEACH 00035 */ 00036 class DisplayBase 00037 { 00038 00039 public: 00040 /*! @enum video_input_channel_t 00041 @brief Video input channel select 00042 */ 00043 typedef enum { 00044 VIDEO_INPUT_CHANNEL_0 = 0, /*!< Video input channel 0 */ 00045 VIDEO_INPUT_CHANNEL_1 /*!< Video input channel 1 */ 00046 } video_input_channel_t; 00047 00048 /*! @enum video_adc_vinsel_t 00049 @brief Input pin control 00050 */ 00051 typedef enum { 00052 VIDEO_ADC_VINSEL_VIN1 = 0, /*!< VIN1 input */ 00053 VIDEO_ADC_VINSEL_VIN2 /*!< VIN2 input */ 00054 } video_adc_vinsel_t; 00055 00056 /*! @enum graphics_layer_t 00057 @brief Graphics layer select 00058 */ 00059 typedef enum { 00060 GRAPHICS_LAYER_0 = 0, /*!< Graphics layer 0 */ 00061 GRAPHICS_LAYER_1 , /*!< Graphics layer 1 */ 00062 GRAPHICS_LAYER_2 , /*!< Graphics layer 2 */ 00063 GRAPHICS_LAYER_3 /*!< Graphics layer 3 */ 00064 } graphics_layer_t; 00065 00066 /*! @enum graphics_error_t 00067 @brief Error codes 00068 */ 00069 typedef enum { 00070 GRAPHICS_OK = 0, /*!< Normal termination */ 00071 GRAPHICS_VDC5_ERR = -1, /*!< VDC5 driver error */ 00072 GRAPHICS_FORMA_ERR = -2, /*!< Not support format */ 00073 GRAPHICS_LAYER_ERR = -3, /*!< Invalid layer ID error */ 00074 GRAPHICS_CHANNLE_ERR = -4, /*!< Invalid channel error */ 00075 GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /*!< Video write size(vw) error */ 00076 GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, /*!< Video Write size(vw) error */ 00077 GRAPHICS_PARAM_RANGE_ERR = -7 /*!< Parameter range error */ 00078 } graphics_error_t; 00079 00080 /*! @enum graphics_format_t 00081 @brief Graphics layer read format selects 00082 */ 00083 typedef enum { 00084 GRAPHICS_FORMAT_YCBCR422 = 0, /*!< YCbCr422 (2byte / px) */ 00085 GRAPHICS_FORMAT_RGB565 , /*!< RGB565 (2byte / px) */ 00086 GRAPHICS_FORMAT_RGB888 , /*!< RGB888 (4byte / px) */ 00087 GRAPHICS_FORMAT_ARGB8888 , /*!< ARGB8888 (4byte / px) */ 00088 GRAPHICS_FORMAT_ARGB4444 /*!< ARGB4444 (2byte / px) */ 00089 } graphics_format_t; 00090 00091 /*! @enum video_format_t 00092 @brief Video writing format selects 00093 */ 00094 typedef enum { 00095 VIDEO_FORMAT_YCBCR422 = 0, /*!< YCbCr422 (2byte / px) */ 00096 VIDEO_FORMAT_RGB565 , /*!< RGB565 (2byte / px) */ 00097 VIDEO_FORMAT_RGB888 /*!< RGB888 (4byte / px) */ 00098 } video_format_t; 00099 00100 /*! @enum wr_rd_swa_t 00101 @brief Frame buffer swap setting 00102 */ 00103 typedef enum { 00104 WR_RD_WRSWA_NON = 0, /*!< Not swapped: 1-2-3-4-5-6-7-8 */ 00105 WR_RD_WRSWA_8BIT , /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */ 00106 WR_RD_WRSWA_16BIT , /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */ 00107 WR_RD_WRSWA_16_8BIT , /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */ 00108 WR_RD_WRSWA_32BIT , /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */ 00109 WR_RD_WRSWA_32_8BIT , /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */ 00110 WR_RD_WRSWA_32_16BIT , /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */ 00111 WR_RD_WRSWA_32_16_8BIT , /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */ 00112 } wr_rd_swa_t; 00113 00114 /*! @enum lcd_tcon_pin_t 00115 @brief LCD tcon output pin selects 00116 */ 00117 typedef enum { 00118 LCD_TCON_PIN_NON = -1, /*!< Not using output */ 00119 LCD_TCON_PIN_0 , /*!< LCD_TCON0 */ 00120 LCD_TCON_PIN_1 , /*!< LCD_TCON1 */ 00121 LCD_TCON_PIN_2 , /*!< LCD_TCON2 */ 00122 LCD_TCON_PIN_3 , /*!< LCD_TCON3 */ 00123 LCD_TCON_PIN_4 , /*!< LCD_TCON4 */ 00124 } lcd_tcon_pin_t; 00125 00126 /*! @enum lcd_outformat_t 00127 @brief LCD output format selects 00128 */ 00129 typedef enum { 00130 LCD_OUTFORMAT_RGB888 = 0, /*!< RGB888 or LVDS */ 00131 LCD_OUTFORMAT_RGB666 , /*!< RGB666 */ 00132 LCD_OUTFORMAT_RGB565 /*!< RGB565 */ 00133 } lcd_outformat_t; 00134 00135 /*! @enum edge_t 00136 @brief Edge of a signal 00137 */ 00138 typedef enum { 00139 EDGE_RISING = 0, /*!< Rising edge */ 00140 EDGE_FALLING = 1 /*!< Falling edge */ 00141 } edge_t; 00142 00143 /*! @enum lcd_type_t 00144 @brief LCD type 00145 */ 00146 typedef enum { 00147 LCD_TYPE_LVDS = 0, /*!< LVDS control */ 00148 LCD_TYPE_PARALLEL_RGB /*!< RGB parallel signal control */ 00149 } lcd_type_t; 00150 00151 /*! @enum sig_pol_t 00152 @brief Polarity of a signal 00153 */ 00154 typedef enum { 00155 SIG_POL_NOT_INVERTED = 0, /*!< Not inverted */ 00156 SIG_POL_INVERTED /*!< Inverted */ 00157 } sig_pol_t; 00158 00159 /*! @enum int_type_t 00160 @brief Interrupt type 00161 */ 00162 typedef enum { 00163 INT_TYPE_S0_VI_VSYNC = 0, /*!< Vsync signal input to scaler 0 */ 00164 INT_TYPE_S0_LO_VSYNC , /*!< Vsync signal output from scaler 0 */ 00165 INT_TYPE_S0_VSYNCERR , /*!< Missing Vsync signal for scaler 0 */ 00166 INT_TYPE_VLINE , /*!< Specified line signal for panel output in graphics 3 */ 00167 INT_TYPE_S0_VFIELD , /*!< Field end signal for recording function in scaler 0 */ 00168 INT_TYPE_IV1_VBUFERR , /*!< Frame buffer write overflow signal for scaler 0 */ 00169 INT_TYPE_IV3_VBUFERR , /*!< Frame buffer read underflow signal for graphics 0 */ 00170 INT_TYPE_IV5_VBUFERR , /*!< Frame buffer read underflow signal for graphics 2 */ 00171 INT_TYPE_IV6_VBUFERR , /*!< Frame buffer read underflow signal for graphics 3 */ 00172 INT_TYPE_S0_WLINE , /*!< Write specification line signal input to scaling-down control block in scaler 0 */ 00173 INT_TYPE_S1_VI_VSYNC , /*!< Vsync signal input to scaler 1 */ 00174 INT_TYPE_S1_LO_VSYNC , /*!< Vsync signal output from scaler 1 */ 00175 INT_TYPE_S1_VSYNCERR , /*!< Missing Vsync signal for scaler 1 */ 00176 INT_TYPE_S1_VFIELD , /*!< Field end signal for recording function in scaler 1 */ 00177 INT_TYPE_IV2_VBUFERR , /*!< Frame buffer write overflow signal for scaler 1 */ 00178 INT_TYPE_IV4_VBUFERR , /*!< Frame buffer read underflow signal for graphics 1 */ 00179 INT_TYPE_S1_WLINE , /*!< Write specification line signal input to scaling-down control block in scaler 1 */ 00180 INT_TYPE_OIR_VI_VSYNC , /*!< Vsync signal input to output image generator */ 00181 INT_TYPE_OIR_LO_VSYNC , /*!< Vsync signal output from output image generator */ 00182 INT_TYPE_OIR_VLINE , /*!< Specified line signal for panel output in output image generator */ 00183 INT_TYPE_OIR_VFIELD , /*!< Field end signal for recording function in output image generator */ 00184 INT_TYPE_IV7_VBUFERR , /*!< Frame buffer write overflow signal for output image generator */ 00185 INT_TYPE_IV8_VBUFERR , /*!< Frame buffer read underflow signal for graphics (OIR) */ 00186 INT_TYPE_NUM /*!< The number of VDC5 interrupt types */ 00187 } int_type_t; 00188 00189 /*! @enum graphics_video_col_sys_t 00190 @brief Video color system 00191 */ 00192 typedef enum { 00193 COL_SYS_NTSC_358 = 0, /*!< NTSC-3.58 */ 00194 COL_SYS_NTSC_443 = 1, /*!< NTSC-4.43 */ 00195 COL_SYS_PAL_443 = 2, /*!< PAL-4.43 */ 00196 COL_SYS_PAL_M = 3, /*!< PAL-M */ 00197 COL_SYS_PAL_N = 4, /*!< PAL-N */ 00198 COL_SYS_SECAM = 5, /*!< SECAM */ 00199 COL_SYS_NTSC_443_60 = 6, /*!< NTSC-4.43 (60Hz) */ 00200 COL_SYS_PAL_60 = 7, /*!< PAL-60 */ 00201 } graphics_video_col_sys_t; 00202 00203 /*! @enum video_input_sel_t 00204 @brief External Input select 00205 */ 00206 typedef enum { 00207 INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */ 00208 INPUT_SEL_EXT = 1 /*!< Signals supplied via the external input pins */ 00209 } video_input_sel_t; 00210 00211 /*! @enum video_extin_format_t 00212 @brief External input format select 00213 */ 00214 typedef enum { 00215 VIDEO_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 Not support */ 00216 VIDEO_EXTIN_FORMAT_RGB666 , /*!< RGB666 */ 00217 VIDEO_EXTIN_FORMAT_RGB565 , /*!< RGB565 */ 00218 VIDEO_EXTIN_FORMAT_BT656 , /*!< BT6556 */ 00219 VIDEO_EXTIN_FORMAT_BT601 , /*!< BT6501 */ 00220 VIDEO_EXTIN_FORMAT_YCBCR422 , /*!< YCbCr422 */ 00221 VIDEO_EXTIN_FORMAT_YCBCR444 , /*!< YCbCr444 Not support */ 00222 } video_extin_format_t; 00223 00224 /*! @enum onoff_t 00225 @brief On/off 00226 */ 00227 typedef enum { 00228 OFF = 0, /*!< Off */ 00229 ON = 1 /*!< On */ 00230 } onoff_t; 00231 00232 /*! @enum extin_input_line_t 00233 @brief Number of lines for BT.656 external input 00234 */ 00235 typedef enum { 00236 EXTIN_LINE_525 = 0, /*!< 525 lines */ 00237 EXTIN_LINE_625 = 1 /*!< 625 lines */ 00238 } extin_input_line_t; 00239 00240 /*! @enum extin_h_pos_t 00241 @brief Y/Cb/Y/Cr data string start timing 00242 */ 00243 typedef enum { 00244 EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */ 00245 EXTIN_H_POS_YCRYCB , /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */ 00246 EXTIN_H_POS_CRYCBY , /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */ 00247 EXTIN_H_POS_YCBYCR , /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */ 00248 EXTIN_H_POS_NUM 00249 } extin_h_pos_t; 00250 00251 /*! @struct rect_t 00252 @brief The relative position within the graphics display area 00253 */ 00254 typedef struct { 00255 unsigned short vs ; /*!< Vertical start pos */ 00256 unsigned short vw ; /*!< Vertical width (height) */ 00257 unsigned short hs ; /*!< Horizontal start pos */ 00258 unsigned short hw ; /*!< Horizontal width */ 00259 } rect_t; 00260 00261 /*! @struct lcd_config_t 00262 @brief LCD configuration 00263 */ 00264 typedef struct { 00265 lcd_type_t lcd_type ; /*!< LVDS or Pararel RGB */ 00266 double intputClock ; /*!< P1 clk [MHz] ex. 66.67f */ 00267 double outputClock ; /*!< LCD clk [MHz] ex. 33.33f */ 00268 00269 lcd_outformat_t lcd_outformat ; /*!< Output format select */ 00270 edge_t lcd_edge ; /*!< Output phase control of LCD_DATA23 to LCD_DATA0 pin */ 00271 00272 unsigned short h_toatal_period ; /*!< Free-running Hsync period */ 00273 unsigned short v_toatal_period ; /*!< Free-running Vsync period */ 00274 unsigned short h_disp_widht ; /*!< LCD display area size, horizontal width */ 00275 unsigned short v_disp_widht ; /*!< LCD display area size, vertical width */ 00276 unsigned short h_back_porch ; /*!< LCD display horizontal back porch period */ 00277 unsigned short v_back_porch ; /*!< LCD display vertical back porch period */ 00278 00279 lcd_tcon_pin_t h_sync_port ; /*!< TCONn or Not use(-1) */ 00280 sig_pol_t h_sync_port_polarity ; /*!< Polarity inversion control of signal */ 00281 unsigned short h_sync_width ; /*!< Hsync width */ 00282 00283 lcd_tcon_pin_t v_sync_port ; /*!< TCONn or Not use(-1) */ 00284 sig_pol_t v_sync_port_polarity ; /*!< Polarity inversion control of signal */ 00285 unsigned short v_sync_width ; /*!< Vsync width */ 00286 00287 lcd_tcon_pin_t de_port ; /*!< TCONn or Not use(-1) */ 00288 sig_pol_t de_port_polarity ; /*!< Polarity inversion control of signal */ 00289 } lcd_config_t; 00290 00291 /*! @struct video_ext_in_config_t 00292 @brief Digital Video Input configuration 00293 */ 00294 typedef struct { 00295 video_extin_format_t inp_format ; /*!< External Input Format Select */ 00296 edge_t inp_pxd_edge ; /*!< Clock Edge Select for Capturing External Input Video Image */ 00297 edge_t inp_vs_edge ; /*!< Clock Edge Select for Capturing External Input Vsync Signal */ 00298 edge_t inp_hs_edge ; /*!< Clock Edge Select for Capturing External Input Hsync Signal */ 00299 onoff_t inp_endian_on ; /*!< External Input B/R Signal Swap On/Off Control */ 00300 onoff_t inp_swap_on ; /*!< External Input Bit Endian Change On/Off Control */ 00301 sig_pol_t inp_vs_inv ; /*!< External Input Vsync Signal DV_VSYNC Inversion Control */ 00302 sig_pol_t inp_hs_inv ; /*!< External Input Hsync Signal DV_HSYNC Inversion Control */ 00303 extin_input_line_t inp_f525_625 ; /*!< Number of lines for BT.656 external input */ 00304 extin_h_pos_t inp_h_pos ; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */ 00305 unsigned short cap_vs_pos ; /*!< Capture start position from Vsync */ 00306 unsigned short cap_hs_pos ; /*!< Capture start position form Hsync */ 00307 unsigned short cap_width ; /*!< Capture width */ 00308 unsigned short cap_height ; /*!< Capture height should be a multiple of 4.*/ 00309 } video_ext_in_config_t; 00310 00311 /** Constructor method of display base object 00312 */ 00313 DisplayBase( void ); 00314 00315 /** Graphics initialization processing<br> 00316 * If not using display, set NULL in parameter. 00317 * @param[in] lcd_config : LCD configuration 00318 * @retval Error code 00319 */ 00320 graphics_error_t Graphics_init( lcd_config_t * lcd_config ); 00321 00322 /** Graphics Video initialization processing<br> 00323 * If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter. 00324 * @param[in] video_input_sel : Input select 00325 * @param[in] video_ext_in_config : Video configuration 00326 * @retval error code 00327 */ 00328 graphics_error_t Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config ); 00329 00330 /** LCD output port initialization processing 00331 * @param[in] pin : Pin assign for LCD output 00332 * @param[in] pin_count : Total number of pin assign 00333 * @retval Error code 00334 */ 00335 graphics_error_t Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count ); 00336 00337 /** LVDS output port initialization processing 00338 * @param[in] pin : Pin assign for LVDS output 00339 * @param[in] pin_count : Total number of pin assign 00340 * @retval Error code 00341 */ 00342 graphics_error_t Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count ); 00343 00344 /** Digital video input port initialization processing 00345 * @param[in] pin : Pin assign for digital video input port 00346 * @param[in] pin_count : Total number of pin assign 00347 * @retval Error code 00348 */ 00349 graphics_error_t Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count ); 00350 00351 /** Interrupt callback setup 00352 * This function performs the following processing: 00353 * - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.<br> 00354 * - Registers the specified interrupt callback function.<br> 00355 * - Disables the interrupt when the pointer to the corresponding interrupt callback function is not specified.<br> 00356 * @param[in] Graphics_Irq_Handler_Set : VDC5 interrupt type 00357 * @param[in] num : Interrupt line number 00358 * @param[in] callback : Interrupt callback function pointer 00359 * @retval Error code 00360 */ 00361 graphics_error_t Graphics_Irq_Handler_Set( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void (* callback)(int_type_t) ); 00362 00363 /** Start the graphics surface read process 00364 * @param[in] layer_id : Graphics layer ID <br /> 00365 * - GRAPHICS_LAYER_0 : Layer 0 00366 * - GRAPHICS_LAYER_1 : Layer 1 00367 * - GRAPHICS_LAYER_2 : Layer 2 00368 * - GRAPHICS_LAYER_3 : Layer 3 00369 * @retval Error code 00370 */ 00371 graphics_error_t Graphics_Start( graphics_layer_t layer_id ); 00372 00373 /** Stop the graphics surface read process 00374 * @param[in] layer_id : Graphics layer ID <br /> 00375 * - GRAPHICS_LAYER_0 : Layer 0 00376 * - GRAPHICS_LAYER_1 : Layer 1 00377 * - GRAPHICS_LAYER_2 : Layer 2 00378 * - GRAPHICS_LAYER_3 : Layer 3 00379 * @retval Error code 00380 */ 00381 graphics_error_t Graphics_Stop( graphics_layer_t layer_id ); 00382 00383 /** Start the video surface write process 00384 * @param[in] video_input_channel : Video input channel <br /> 00385 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0 00386 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1 00387 * @retval Error code 00388 */ 00389 graphics_error_t Video_Start ( video_input_channel_t video_input_channel ); 00390 00391 /** Stop the video surface write process 00392 * @param[in] video_input_channel : Video input channel <br /> 00393 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0 00394 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1 00395 * @retval Error code 00396 */ 00397 graphics_error_t Video_Stop ( video_input_channel_t video_input_channel ); 00398 00399 /** Graphics surface read process setting 00400 * @param[in] layer_id : Graphics layer ID <br /> 00401 * - GRAPHICS_LAYER_0 : Layer 0 00402 * - GRAPHICS_LAYER_1 : Layer 1 00403 * - GRAPHICS_LAYER_2 : Layer 2 00404 * - GRAPHICS_LAYER_3 : Layer 3 00405 * @param[in] framebuff : Base address of the frame buffer(Not set NULL) 00406 * @param[in] fb_stride : Line offset address of the frame buffer[byte] <br /> 00407 * Frame buffer stride should be set to a multiple of 32 or 128 00408 * in accordance with the frame buffer burst transfer mode. 00409 * @param[in] gr_format : Format of the frame buffer read signal <br /> 00410 * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px) 00411 * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px) 00412 * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px) 00413 * - VIDEO_FORMAT_ARGB8888 : ARGB8888 (4byte/px) 00414 * @param[in] wr_rd_swa : frame buffer swap setting <br /> 00415 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8 00416 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7 00417 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6 00418 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 00419 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4 00420 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 00421 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 00422 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 00423 * @param[in] gr_rect : Graphics display area 00424 * @retval Error code 00425 */ 00426 graphics_error_t Graphics_Read_Setting ( 00427 graphics_layer_t layer_id, 00428 void * framebuff, 00429 unsigned int fb_stride, 00430 graphics_format_t gr_format, 00431 wr_rd_swa_t wr_rd_swa, 00432 rect_t * gr_rect ); 00433 00434 /** Graphics surface read buffer change process 00435 * @param[in] layer_id : Graphics layer ID <br /> 00436 * - GRAPHICS_LAYER_0 : Layer 0 00437 * - GRAPHICS_LAYER_1 : Layer 1 00438 * - GRAPHICS_LAYER_2 : Layer 2 00439 * - GRAPHICS_LAYER_3 : Layer 3 00440 * @param[in] framebuff : Base address of the frame buffer(Not set NULL) 00441 * @retval Error code 00442 */ 00443 graphics_error_t Graphics_Read_Change ( 00444 graphics_layer_t layer_id, 00445 void * framebuff); 00446 00447 /** Video surface write process setting 00448 * @param[in] video_input_channel : Video input channel <br /> 00449 * If using digital input, this parameter is not referenced. <br /> 00450 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0 00451 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1 00452 * @param[in] col_sys : Analog video signal color system <br /> 00453 * If using digital input, this parameter is not referenced. <br /> 00454 * - COL_SYS_NTSC_358 : NTSC-3.58 00455 * - COL_SYS_NTSC_443 : NTSC-4.43 00456 * - COL_SYS_PAL_443 : PAL-4.43 00457 * - COL_SYS_PAL_M : PAL-M 00458 * - COL_SYS_PAL_N : PAL-N 00459 * - COL_SYS_SECAM : SECAM 00460 * - COL_SYS_NTSC_443_60 : NTSC-4.43 (60Hz) 00461 * - COL_SYS_PAL_60 : PAL-60 00462 * @param[in] framebuff : Base address of the frame buffer(Not set NULL) 00463 * @param[in] fb_stride : Line offset address of the frame buffer[byte] <br /> 00464 * Frame buffer stride should be set to a multiple of 32 or 128 00465 * in accordance with the frame buffer burst transfer mode. 00466 * @param[in] video_format : Frame buffer video-signal writing format <br /> 00467 * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px) 00468 * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px) 00469 * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px) 00470 * @param[in] wr_rd_swa : frame buffer swap setting <br /> 00471 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8 00472 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7 00473 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6 00474 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 00475 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4 00476 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 00477 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 00478 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 00479 * @param[in] video_write_buff_vw : Output height[px] <br /> 00480 * - NTSC format : Max height is 480[px] 00481 * - PAL format : Max height is 520[px] 00482 * @param[in] video_write_buff_hw : Output width[px] <br /> 00483 * - Max width : 800[px] 00484 * @param[in] video_adc_vinsel : Input pin control <br /> 00485 * - VIDEO_ADC_VINSEL_VIN1 : VIN1 input 00486 * - VIDEO_ADC_VINSEL_VIN2 : VIN2 input 00487 * @retval Error code 00488 */ 00489 graphics_error_t Video_Write_Setting ( 00490 video_input_channel_t video_input_channel, 00491 graphics_video_col_sys_t col_sys, 00492 void * framebuff, 00493 unsigned int fb_stride, 00494 video_format_t video_format, 00495 wr_rd_swa_t wr_rd_swa, 00496 unsigned short video_write_buff_vw, 00497 unsigned short video_write_buff_hw, 00498 video_adc_vinsel_t video_adc_vinsel = VIDEO_ADC_VINSEL_VIN1 ); 00499 00500 /** Video surface write buffer change process 00501 * @param[in] video_input_channel : Video input channel <br /> 00502 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0 00503 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1 00504 * @param[in] framebuff : Base address of the frame buffer(Not set NULL) 00505 * @param[in] fb_stride : Line offset address of the frame buffer <br /> 00506 * Frame buffer stride should be set to a multiple of 32 or 128 00507 * in accordance with the frame buffer burst transfer mode. 00508 * @retval Error code 00509 */ 00510 graphics_error_t Video_Write_Change ( 00511 video_input_channel_t video_input_channel, 00512 void * framebuff, 00513 uint32_t fb_stride ); 00514 00515 protected: 00516 lcd_config_t _lcd_config; 00517 video_input_sel_t _video_input_sel; 00518 video_ext_in_config_t _video_ext_in_config; 00519 }; 00520 00521 00522 #endif /* MBED_DISPLAYBASE_H */
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