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Revision 167:2ee3e82cb6f5, committed 2017-07-21
- Comitter:
- thedo
- Date:
- Fri Jul 21 01:26:54 2017 +0000
- Parent:
- 166:240bc5a0f42a
- Commit message:
- gr-peach-opencv-project-sd-card
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/AnalogIn.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "drivers/AnalogIn.h"
+
+#if DEVICE_ANALOGIN
+
+namespace mbed {
+
+SingletonPtr<PlatformMutex> AnalogIn::_mutex;
+
+};
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/AnalogIn.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,131 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_H
+#define MBED_ANALOGIN_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_ANALOGIN) || defined(DOXYGEN_ONLY)
+
+#include "hal/analogin_api.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An analog input, used for reading the voltage on a pin
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Print messages when the AnalogIn is greater than 50%
+ *
+ * #include "mbed.h"
+ *
+ * AnalogIn temperature(p20);
+ *
+ * int main() {
+ * while(1) {
+ * if(temperature > 0.5) {
+ * printf("Too hot! (%f)", temperature.read());
+ * }
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class AnalogIn {
+
+public:
+
+ /** Create an AnalogIn, connected to the specified pin
+ *
+ * @param pin AnalogIn pin to connect to
+ */
+ AnalogIn(PinName pin) {
+ lock();
+ analogin_init(&_adc, pin);
+ unlock();
+ }
+
+ /** Read the input voltage, represented as a float in the range [0.0, 1.0]
+ *
+ * @returns A floating-point value representing the current input voltage, measured as a percentage
+ */
+ float read() {
+ lock();
+ float ret = analogin_read(&_adc);
+ unlock();
+ return ret;
+ }
+
+ /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+ *
+ * @returns
+ * 16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
+ */
+ unsigned short read_u16() {
+ lock();
+ unsigned short ret = analogin_read_u16(&_adc);
+ unlock();
+ return ret;
+ }
+
+ /** An operator shorthand for read()
+ *
+ * The float() operator can be used as a shorthand for read() to simplify common code sequences
+ *
+ * Example:
+ * @code
+ * float x = volume.read();
+ * float x = volume;
+ *
+ * if(volume.read() > 0.25) { ... }
+ * if(volume > 0.25) { ... }
+ * @endcode
+ */
+ operator float() {
+ // Underlying call is thread safe
+ return read();
+ }
+
+ virtual ~AnalogIn() {
+ // Do nothing
+ }
+
+protected:
+
+ virtual void lock() {
+ _mutex->lock();
+ }
+
+ virtual void unlock() {
+ _mutex->unlock();
+ }
+
+ analogin_t _adc;
+ static SingletonPtr<PlatformMutex> _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/AnalogOut.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,149 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_H
+#define MBED_ANALOGOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_ANALOGOUT) || defined(DOXYGEN_ONLY)
+
+#include "hal/analogout_api.h"
+#include "platform/PlatformMutex.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An analog output, used for setting the voltage on a pin
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Make a sawtooth output
+ *
+ * #include "mbed.h"
+ *
+ * AnalogOut tri(p18);
+ * int main() {
+ * while(1) {
+ * tri = tri + 0.01;
+ * wait_us(1);
+ * if(tri == 1) {
+ * tri = 0;
+ * }
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class AnalogOut {
+
+public:
+
+ /** Create an AnalogOut connected to the specified pin
+ *
+ * @param pin AnalogOut pin to connect to
+ */
+ AnalogOut(PinName pin) {
+ analogout_init(&_dac, pin);
+ }
+
+ /** Set the output voltage, specified as a percentage (float)
+ *
+ * @param value A floating-point value representing the output voltage,
+ * specified as a percentage. The value should lie between
+ * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+ * Values outside this range will be saturated to 0.0f or 1.0f.
+ */
+ void write(float value) {
+ lock();
+ analogout_write(&_dac, value);
+ unlock();
+ }
+
+ /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+ *
+ * @param value 16-bit unsigned short representing the output voltage,
+ * normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
+ */
+ void write_u16(unsigned short value) {
+ lock();
+ analogout_write_u16(&_dac, value);
+ unlock();
+ }
+
+ /** Return the current output voltage setting, measured as a percentage (float)
+ *
+ * @returns
+ * A floating-point value representing the current voltage being output on the pin,
+ * measured as a percentage. The returned value will lie between
+ * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+ *
+ * @note
+ * This value may not match exactly the value set by a previous write().
+ */
+ float read() {
+ lock();
+ float ret = analogout_read(&_dac);
+ unlock();
+ return ret;
+ }
+
+ /** An operator shorthand for write()
+ */
+ AnalogOut& operator= (float percent) {
+ // Underlying write call is thread safe
+ write(percent);
+ return *this;
+ }
+
+ AnalogOut& operator= (AnalogOut& rhs) {
+ // Underlying write call is thread safe
+ write(rhs.read());
+ return *this;
+ }
+
+ /** An operator shorthand for read()
+ */
+ operator float() {
+ // Underlying read call is thread safe
+ return read();
+ }
+
+ virtual ~AnalogOut() {
+ // Do nothing
+ }
+
+protected:
+
+ virtual void lock() {
+ _mutex.lock();
+ }
+
+ virtual void unlock() {
+ _mutex.unlock();
+ }
+
+ dac_t _dac;
+ PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/BusIn.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,97 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/BusIn.h"
+#include "platform/mbed_assert.h"
+
+namespace mbed {
+
+BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+ PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+ // No lock needed in the constructor
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusIn::BusIn(PinName pins[16]) {
+ // No lock needed in the constructor
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusIn::~BusIn() {
+ // No lock needed in the destructor
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ delete _pin[i];
+ }
+ }
+}
+
+int BusIn::read() {
+ int v = 0;
+ lock();
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ v |= _pin[i]->read() << i;
+ }
+ }
+ unlock();
+ return v;
+}
+
+void BusIn::mode(PinMode pull) {
+ lock();
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->mode(pull);
+ }
+ }
+ unlock();
+}
+
+void BusIn::lock() {
+ _mutex.lock();
+}
+
+void BusIn::unlock() {
+ _mutex.unlock();
+}
+
+BusIn::operator int() {
+ // Underlying read is thread safe
+ return read();
+}
+
+DigitalIn& BusIn::operator[] (int index) {
+ // No lock needed since _pin is not modified outside the constructor
+ MBED_ASSERT(index >= 0 && index <= 16);
+ MBED_ASSERT(_pin[index]);
+ return *_pin[index];
+}
+
+} // namespace mbed
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/BusIn.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,128 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSIN_H
+#define MBED_BUSIN_H
+
+#include "platform/platform.h"
+#include "drivers/DigitalIn.h"
+#include "platform/PlatformMutex.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital input bus, used for reading the state of a collection of pins
+ *
+ * @note Synchronization level: Thread safe
+ * @ingroup drivers
+ */
+class BusIn {
+
+public:
+ /* Group: Configuration Methods */
+
+ /** Create an BusIn, connected to the specified pins
+ *
+ * @param p0 DigitalIn pin to connect to bus bit
+ * @param p1 DigitalIn pin to connect to bus bit
+ * @param p2 DigitalIn pin to connect to bus bit
+ * @param p3 DigitalIn pin to connect to bus bit
+ * @param p4 DigitalIn pin to connect to bus bit
+ * @param p5 DigitalIn pin to connect to bus bit
+ * @param p6 DigitalIn pin to connect to bus bit
+ * @param p7 DigitalIn pin to connect to bus bit
+ * @param p8 DigitalIn pin to connect to bus bit
+ * @param p9 DigitalIn pin to connect to bus bit
+ * @param p10 DigitalIn pin to connect to bus bit
+ * @param p11 DigitalIn pin to connect to bus bit
+ * @param p12 DigitalIn pin to connect to bus bit
+ * @param p13 DigitalIn pin to connect to bus bit
+ * @param p14 DigitalIn pin to connect to bus bit
+ * @param p15 DigitalIn pin to connect to bus bit
+ *
+ * @note
+ * It is only required to specify as many pin variables as is required
+ * for the bus; the rest will default to NC (not connected)
+ */
+ BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+ PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+ PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+ PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+
+ /** Create an BusIn, connected to the specified pins
+ *
+ * @param pins An array of pins to connect to bus bit
+ */
+ BusIn(PinName pins[16]);
+
+ virtual ~BusIn();
+
+ /** Read the value of the input bus
+ *
+ * @returns
+ * An integer with each bit corresponding to the value read from the associated DigitalIn pin
+ */
+ int read();
+
+ /** Set the input pin mode
+ *
+ * @param pull PullUp, PullDown, PullNone
+ */
+ void mode(PinMode pull);
+
+ /** Binary mask of bus pins connected to actual pins (not NC pins)
+ * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+ *
+ * @returns
+ * Binary mask of connected pins
+ */
+ int mask() {
+ // No lock needed since _nc_mask is not modified outside the constructor
+ return _nc_mask;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int();
+
+ /** Access to particular bit in random-iterator fashion
+ */
+ DigitalIn & operator[] (int index);
+
+protected:
+ DigitalIn* _pin[16];
+
+ /* Mask of bus's NC pins
+ * If bit[n] is set to 1 - pin is connected
+ * if bit[n] is cleared - pin is not connected (NC)
+ */
+ int _nc_mask;
+
+ PlatformMutex _mutex;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ virtual void lock();
+ virtual void unlock();
+ BusIn(const BusIn&);
+ BusIn & operator = (const BusIn&);
+};
+
+} // namespace mbed
+
+#endif
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/BusInOut.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/BusInOut.h"
+#include "platform/mbed_assert.h"
+
+namespace mbed {
+
+BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+ PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+ // No lock needed in the constructor
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusInOut::BusInOut(PinName pins[16]) {
+ // No lock needed in the constructor
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusInOut::~BusInOut() {
+ // No lock needed in the destructor
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ delete _pin[i];
+ }
+ }
+}
+
+void BusInOut::write(int value) {
+ lock();
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->write((value >> i) & 1);
+ }
+ }
+ unlock();
+}
+
+int BusInOut::read() {
+ lock();
+ int v = 0;
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ v |= _pin[i]->read() << i;
+ }
+ }
+ unlock();
+ return v;
+}
+
+void BusInOut::output() {
+ lock();
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->output();
+ }
+ }
+ unlock();
+}
+
+void BusInOut::input() {
+ lock();
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->input();
+ }
+ }
+ unlock();
+}
+
+void BusInOut::mode(PinMode pull) {
+ lock();
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->mode(pull);
+ }
+ }
+ unlock();
+}
+
+BusInOut& BusInOut::operator= (int v) {
+ // Underlying write is thread safe
+ write(v);
+ return *this;
+}
+
+BusInOut& BusInOut::operator= (BusInOut& rhs) {
+ // Underlying read is thread safe
+ write(rhs.read());
+ return *this;
+}
+
+DigitalInOut& BusInOut::operator[] (int index) {
+ // No lock needed since _pin is not modified outside the constructor
+ MBED_ASSERT(index >= 0 && index <= 16);
+ MBED_ASSERT(_pin[index]);
+ return *_pin[index];
+}
+
+BusInOut::operator int() {
+ // Underlying read is thread safe
+ return read();
+}
+
+void BusInOut::lock() {
+ _mutex.lock();
+}
+
+void BusInOut::unlock() {
+ _mutex.unlock();
+}
+
+} // namespace mbed
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/BusInOut.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,145 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSINOUT_H
+#define MBED_BUSINOUT_H
+
+#include "drivers/DigitalInOut.h"
+#include "platform/PlatformMutex.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital input output bus, used for setting the state of a collection of pins
+ *
+ * @note Synchronization level: Thread safe
+ * @ingroup drivers
+ */
+class BusInOut {
+
+public:
+
+ /** Create an BusInOut, connected to the specified pins
+ *
+ * @param p0 DigitalInOut pin to connect to bus bit
+ * @param p1 DigitalInOut pin to connect to bus bit
+ * @param p2 DigitalInOut pin to connect to bus bit
+ * @param p3 DigitalInOut pin to connect to bus bit
+ * @param p4 DigitalInOut pin to connect to bus bit
+ * @param p5 DigitalInOut pin to connect to bus bit
+ * @param p6 DigitalInOut pin to connect to bus bit
+ * @param p7 DigitalInOut pin to connect to bus bit
+ * @param p8 DigitalInOut pin to connect to bus bit
+ * @param p9 DigitalInOut pin to connect to bus bit
+ * @param p10 DigitalInOut pin to connect to bus bit
+ * @param p11 DigitalInOut pin to connect to bus bit
+ * @param p12 DigitalInOut pin to connect to bus bit
+ * @param p13 DigitalInOut pin to connect to bus bit
+ * @param p14 DigitalInOut pin to connect to bus bit
+ * @param p15 DigitalInOut pin to connect to bus bit
+ *
+ * @note
+ * It is only required to specify as many pin variables as is required
+ * for the bus; the rest will default to NC (not connected)
+ */
+ BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+ PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+ PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+ PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+ /** Create an BusInOut, connected to the specified pins
+ *
+ * @param pins An array of pins to construct a BusInOut from
+ */
+ BusInOut(PinName pins[16]);
+
+ virtual ~BusInOut();
+
+ /* Group: Access Methods */
+
+ /** Write the value to the output bus
+ *
+ * @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
+ */
+ void write(int value);
+
+ /** Read the value currently output on the bus
+ *
+ * @returns
+ * An integer with each bit corresponding to associated DigitalInOut pin setting
+ */
+ int read();
+
+ /** Set as an output
+ */
+ void output();
+
+ /** Set as an input
+ */
+ void input();
+
+ /** Set the input pin mode
+ *
+ * @param pull PullUp, PullDown, PullNone
+ */
+ void mode(PinMode pull);
+
+ /** Binary mask of bus pins connected to actual pins (not NC pins)
+ * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+ *
+ * @returns
+ * Binary mask of connected pins
+ */
+ int mask() {
+ // No lock needed since _nc_mask is not modified outside the constructor
+ return _nc_mask;
+ }
+
+ /** A shorthand for write()
+ */
+ BusInOut& operator= (int v);
+ BusInOut& operator= (BusInOut& rhs);
+
+ /** Access to particular bit in random-iterator fashion
+ */
+ DigitalInOut& operator[] (int index);
+
+ /** A shorthand for read()
+ */
+ operator int();
+
+protected:
+ virtual void lock();
+ virtual void unlock();
+ DigitalInOut* _pin[16];
+
+ /* Mask of bus's NC pins
+ * If bit[n] is set to 1 - pin is connected
+ * if bit[n] is cleared - pin is not connected (NC)
+ */
+ int _nc_mask;
+
+ PlatformMutex _mutex;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ BusInOut(const BusInOut&);
+ BusInOut & operator = (const BusInOut&);
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/BusOut.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,109 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/BusOut.h"
+#include "platform/mbed_assert.h"
+
+namespace mbed {
+
+BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+ PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+ // No lock needed in the constructor
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusOut::BusOut(PinName pins[16]) {
+ // No lock needed in the constructor
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusOut::~BusOut() {
+ // No lock needed in the destructor
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ delete _pin[i];
+ }
+ }
+}
+
+void BusOut::write(int value) {
+ lock();
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->write((value >> i) & 1);
+ }
+ }
+ unlock();
+}
+
+int BusOut::read() {
+ lock();
+ int v = 0;
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ v |= _pin[i]->read() << i;
+ }
+ }
+ unlock();
+ return v;
+}
+
+BusOut& BusOut::operator= (int v) {
+ // Underlying write is thread safe
+ write(v);
+ return *this;
+}
+
+BusOut& BusOut::operator= (BusOut& rhs) {
+ // Underlying write is thread safe
+ write(rhs.read());
+ return *this;
+}
+
+DigitalOut& BusOut::operator[] (int index) {
+ // No lock needed since _pin is not modified outside the constructor
+ MBED_ASSERT(index >= 0 && index <= 16);
+ MBED_ASSERT(_pin[index]);
+ return *_pin[index];
+}
+
+BusOut::operator int() {
+ // Underlying read is thread safe
+ return read();
+}
+
+void BusOut::lock() {
+ _mutex.lock();
+}
+
+void BusOut::unlock() {
+ _mutex.unlock();
+}
+
+} // namespace mbed
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/BusOut.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,129 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSOUT_H
+#define MBED_BUSOUT_H
+
+#include "drivers/DigitalOut.h"
+#include "platform/PlatformMutex.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital output bus, used for setting the state of a collection of pins
+ * @ingroup drivers
+ */
+class BusOut {
+
+public:
+
+ /** Create an BusOut, connected to the specified pins
+ *
+ * @param p0 DigitalOut pin to connect to bus bit
+ * @param p1 DigitalOut pin to connect to bus bit
+ * @param p2 DigitalOut pin to connect to bus bit
+ * @param p3 DigitalOut pin to connect to bus bit
+ * @param p4 DigitalOut pin to connect to bus bit
+ * @param p5 DigitalOut pin to connect to bus bit
+ * @param p6 DigitalOut pin to connect to bus bit
+ * @param p7 DigitalOut pin to connect to bus bit
+ * @param p8 DigitalOut pin to connect to bus bit
+ * @param p9 DigitalOut pin to connect to bus bit
+ * @param p10 DigitalOut pin to connect to bus bit
+ * @param p11 DigitalOut pin to connect to bus bit
+ * @param p12 DigitalOut pin to connect to bus bit
+ * @param p13 DigitalOut pin to connect to bus bit
+ * @param p14 DigitalOut pin to connect to bus bit
+ * @param p15 DigitalOut pin to connect to bus bit
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * @note
+ * It is only required to specify as many pin variables as is required
+ * for the bus; the rest will default to NC (not connected)
+ */
+ BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+ PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+ PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+ PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+ /** Create an BusOut, connected to the specified pins
+ *
+ * @param pins An array of pins to connect to bus the bit
+ */
+ BusOut(PinName pins[16]);
+
+ virtual ~BusOut();
+
+ /** Write the value to the output bus
+ *
+ * @param value An integer specifying a bit to write for every corresponding DigitalOut pin
+ */
+ void write(int value);
+
+ /** Read the value currently output on the bus
+ *
+ * @returns
+ * An integer with each bit corresponding to associated DigitalOut pin setting
+ */
+ int read();
+
+ /** Binary mask of bus pins connected to actual pins (not NC pins)
+ * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+ *
+ * @returns
+ * Binary mask of connected pins
+ */
+ int mask() {
+ // No lock needed since _nc_mask is not modified outside the constructor
+ return _nc_mask;
+ }
+
+ /** A shorthand for write()
+ */
+ BusOut& operator= (int v);
+ BusOut& operator= (BusOut& rhs);
+
+ /** Access to particular bit in random-iterator fashion
+ */
+ DigitalOut& operator[] (int index);
+
+ /** A shorthand for read()
+ */
+ operator int();
+
+protected:
+ virtual void lock();
+ virtual void unlock();
+ DigitalOut* _pin[16];
+
+ /* Mask of bus's NC pins
+ * If bit[n] is set to 1 - pin is connected
+ * if bit[n] is cleared - pin is not connected (NC)
+ */
+ int _nc_mask;
+
+ PlatformMutex _mutex;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ BusOut(const BusOut&);
+ BusOut & operator = (const BusOut&);
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/CAN.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,143 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/CAN.h"
+
+#if DEVICE_CAN
+
+#include "cmsis.h"
+
+namespace mbed {
+
+static void donothing() {}
+
+CAN::CAN(PinName rd, PinName td) : _can(), _irq() {
+ // No lock needed in constructor
+
+ for (int i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
+ _irq[i] = callback(donothing);
+ }
+
+ can_init(&_can, rd, td);
+ can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
+}
+
+CAN::CAN(PinName rd, PinName td, int hz) : _can(), _irq() {
+ // No lock needed in constructor
+
+ for (int i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
+ _irq[i].attach(donothing);
+ }
+
+ can_init_freq(&_can, rd, td, hz);
+ can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
+}
+
+CAN::~CAN() {
+ // No lock needed in destructor
+ can_irq_free(&_can);
+ can_free(&_can);
+}
+
+int CAN::frequency(int f) {
+ lock();
+ int ret = can_frequency(&_can, f);
+ unlock();
+ return ret;
+}
+
+int CAN::write(CANMessage msg) {
+ lock();
+ int ret = can_write(&_can, msg, 0);
+ unlock();
+ return ret;
+}
+
+int CAN::read(CANMessage &msg, int handle) {
+ lock();
+ int ret = can_read(&_can, &msg, handle);
+ unlock();
+ return ret;
+}
+
+void CAN::reset() {
+ lock();
+ can_reset(&_can);
+ unlock();
+}
+
+unsigned char CAN::rderror() {
+ lock();
+ int ret = can_rderror(&_can);
+ unlock();
+ return ret;
+}
+
+unsigned char CAN::tderror() {
+ lock();
+ int ret = can_tderror(&_can);
+ unlock();
+ return ret;
+}
+
+void CAN::monitor(bool silent) {
+ lock();
+ can_monitor(&_can, (silent) ? 1 : 0);
+ unlock();
+}
+
+int CAN::mode(Mode mode) {
+ lock();
+ int ret = can_mode(&_can, (CanMode)mode);
+ unlock();
+ return ret;
+}
+
+int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle) {
+ lock();
+ int ret = can_filter(&_can, id, mask, format, handle);
+ unlock();
+ return ret;
+}
+
+void CAN::attach(Callback<void()> func, IrqType type) {
+ lock();
+ if (func) {
+ _irq[(CanIrqType)type] = func;
+ can_irq_set(&_can, (CanIrqType)type, 1);
+ } else {
+ _irq[(CanIrqType)type] = callback(donothing);
+ can_irq_set(&_can, (CanIrqType)type, 0);
+ }
+ unlock();
+}
+
+void CAN::_irq_handler(uint32_t id, CanIrqType type) {
+ CAN *handler = (CAN*)id;
+ handler->_irq[type].call();
+}
+
+void CAN::lock() {
+ _mutex.lock();
+}
+
+void CAN::unlock() {
+ _mutex.unlock();
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/CAN.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,284 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_H
+#define MBED_CAN_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_CAN) || defined(DOXYGEN_ONLY)
+
+#include "hal/can_api.h"
+#include "platform/Callback.h"
+#include "platform/PlatformMutex.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** CANMessage class
+ *
+ * @note Synchronization level: Thread safe
+ * @ingroup drivers
+ */
+class CANMessage : public CAN_Message {
+
+public:
+ /** Creates empty CAN message.
+ */
+ CANMessage() : CAN_Message() {
+ len = 8;
+ type = CANData;
+ format = CANStandard;
+ id = 0;
+ memset(data, 0, 8);
+ }
+
+ /** Creates CAN message with specific content.
+ */
+ CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
+ len = _len & 0xF;
+ type = _type;
+ format = _format;
+ id = _id;
+ memcpy(data, _data, _len);
+ }
+
+ /** Creates CAN remote message.
+ */
+ CANMessage(int _id, CANFormat _format = CANStandard) {
+ len = 0;
+ type = CANRemote;
+ format = _format;
+ id = _id;
+ memset(data, 0, 8);
+ }
+};
+
+/** A can bus client, used for communicating with can devices
+ * @ingroup drivers
+ */
+class CAN {
+
+public:
+ /** Creates an CAN interface connected to specific pins.
+ *
+ * @param rd read from transmitter
+ * @param td transmit to transmitter
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * Ticker ticker;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ * CAN can1(p9, p10);
+ * CAN can2(p30, p29);
+ *
+ * char counter = 0;
+ *
+ * void send() {
+ * if(can1.write(CANMessage(1337, &counter, 1))) {
+ * printf("Message sent: %d\n", counter);
+ * counter++;
+ * }
+ * led1 = !led1;
+ * }
+ *
+ * int main() {
+ * ticker.attach(&send, 1);
+ * CANMessage msg;
+ * while(1) {
+ * if(can2.read(msg)) {
+ * printf("Message received: %d\n\n", msg.data[0]);
+ * led2 = !led2;
+ * }
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ */
+ CAN(PinName rd, PinName td);
+
+ /** Initialize CAN interface and set the frequency
+ *
+ * @param rd the rd pin
+ * @param td the td pin
+ * @param hz the bus frequency in hertz
+ */
+ CAN(PinName rd, PinName td, int hz);
+
+ virtual ~CAN();
+
+ /** Set the frequency of the CAN interface
+ *
+ * @param hz The bus frequency in hertz
+ *
+ * @returns
+ * 1 if successful,
+ * 0 otherwise
+ */
+ int frequency(int hz);
+
+ /** Write a CANMessage to the bus.
+ *
+ * @param msg The CANMessage to write.
+ *
+ * @returns
+ * 0 if write failed,
+ * 1 if write was successful
+ */
+ int write(CANMessage msg);
+
+ /** Read a CANMessage from the bus.
+ *
+ * @param msg A CANMessage to read to.
+ * @param handle message filter handle (0 for any message)
+ *
+ * @returns
+ * 0 if no message arrived,
+ * 1 if message arrived
+ */
+ int read(CANMessage &msg, int handle = 0);
+
+ /** Reset CAN interface.
+ *
+ * To use after error overflow.
+ */
+ void reset();
+
+ /** Puts or removes the CAN interface into silent monitoring mode
+ *
+ * @param silent boolean indicating whether to go into silent mode or not
+ */
+ void monitor(bool silent);
+
+ enum Mode {
+ Reset = 0,
+ Normal,
+ Silent,
+ LocalTest,
+ GlobalTest,
+ SilentTest
+ };
+
+ /** Change CAN operation to the specified mode
+ *
+ * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
+ *
+ * @returns
+ * 0 if mode change failed or unsupported,
+ * 1 if mode change was successful
+ */
+ int mode(Mode mode);
+
+ /** Filter out incomming messages
+ *
+ * @param id the id to filter on
+ * @param mask the mask applied to the id
+ * @param format format to filter on (Default CANAny)
+ * @param handle message filter handle (Optional)
+ *
+ * @returns
+ * 0 if filter change failed or unsupported,
+ * new filter handle if successful
+ */
+ int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
+
+ /** Returns number of read errors to detect read overflow errors.
+ */
+ unsigned char rderror();
+
+ /** Returns number of write errors to detect write overflow errors.
+ */
+ unsigned char tderror();
+
+ enum IrqType {
+ RxIrq = 0,
+ TxIrq,
+ EwIrq,
+ DoIrq,
+ WuIrq,
+ EpIrq,
+ AlIrq,
+ BeIrq,
+ IdIrq,
+
+ IrqCnt
+ };
+
+ /** Attach a function to call whenever a CAN frame received interrupt is
+ * generated.
+ *
+ * @param func A pointer to a void function, or 0 to set as none
+ * @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
+ */
+ void attach(Callback<void()> func, IrqType type=RxIrq);
+
+ /** Attach a member function to call whenever a CAN frame received interrupt
+ * is generated.
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+ * @deprecated
+ * The attach function does not support cv-qualifiers. Replaced by
+ * attach(callback(obj, method), type).
+ */
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The attach function does not support cv-qualifiers. Replaced by "
+ "attach(callback(obj, method), type).")
+ void attach(T* obj, void (T::*method)(), IrqType type=RxIrq) {
+ // Underlying call thread safe
+ attach(callback(obj, method), type);
+ }
+
+ /** Attach a member function to call whenever a CAN frame received interrupt
+ * is generated.
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+ * @deprecated
+ * The attach function does not support cv-qualifiers. Replaced by
+ * attach(callback(obj, method), type).
+ */
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The attach function does not support cv-qualifiers. Replaced by "
+ "attach(callback(obj, method), type).")
+ void attach(T* obj, void (*method)(T*), IrqType type=RxIrq) {
+ // Underlying call thread safe
+ attach(callback(obj, method), type);
+ }
+
+ static void _irq_handler(uint32_t id, CanIrqType type);
+
+protected:
+ virtual void lock();
+ virtual void unlock();
+ can_t _can;
+ Callback<void()> _irq[IrqCnt];
+ PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif // MBED_CAN_H
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/DigitalIn.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,118 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALIN_H
+#define MBED_DIGITALIN_H
+
+#include "platform/platform.h"
+
+#include "hal/gpio_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital input, used for reading the state of a pin
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Flash an LED while a DigitalIn is true
+ *
+ * #include "mbed.h"
+ *
+ * DigitalIn enable(p5);
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ * while(1) {
+ * if(enable) {
+ * led = !led;
+ * }
+ * wait(0.25);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class DigitalIn {
+
+public:
+ /** Create a DigitalIn connected to the specified pin
+ *
+ * @param pin DigitalIn pin to connect to
+ */
+ DigitalIn(PinName pin) : gpio() {
+ // No lock needed in the constructor
+ gpio_init_in(&gpio, pin);
+ }
+
+ /** Create a DigitalIn connected to the specified pin
+ *
+ * @param pin DigitalIn pin to connect to
+ * @param mode the initial mode of the pin
+ */
+ DigitalIn(PinName pin, PinMode mode) : gpio() {
+ // No lock needed in the constructor
+ gpio_init_in_ex(&gpio, pin, mode);
+ }
+ /** Read the input, represented as 0 or 1 (int)
+ *
+ * @returns
+ * An integer representing the state of the input pin,
+ * 0 for logical 0, 1 for logical 1
+ */
+ int read() {
+ // Thread safe / atomic HAL call
+ return gpio_read(&gpio);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param pull PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode pull) {
+ core_util_critical_section_enter();
+ gpio_mode(&gpio, pull);
+ core_util_critical_section_exit();
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * Non zero value if pin is connected to uc GPIO
+ * 0 if gpio object was initialized with NC
+ */
+ int is_connected() {
+ // Thread safe / atomic HAL call
+ return gpio_is_connected(&gpio);
+ }
+
+ /** An operator shorthand for read()
+ */
+ operator int() {
+ // Underlying read is thread safe
+ return read();
+ }
+
+protected:
+ gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/DigitalInOut.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,143 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALINOUT_H
+#define MBED_DIGITALINOUT_H
+
+#include "platform/platform.h"
+
+#include "hal/gpio_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital input/output, used for setting or reading a bi-directional pin
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class DigitalInOut {
+
+public:
+ /** Create a DigitalInOut connected to the specified pin
+ *
+ * @param pin DigitalInOut pin to connect to
+ */
+ DigitalInOut(PinName pin) : gpio() {
+ // No lock needed in the constructor
+ gpio_init_in(&gpio, pin);
+ }
+
+ /** Create a DigitalInOut connected to the specified pin
+ *
+ * @param pin DigitalInOut pin to connect to
+ * @param direction the initial direction of the pin
+ * @param mode the initial mode of the pin
+ * @param value the initial value of the pin if is an output
+ */
+ DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {
+ // No lock needed in the constructor
+ gpio_init_inout(&gpio, pin, direction, mode, value);
+ }
+
+ /** Set the output, specified as 0 or 1 (int)
+ *
+ * @param value An integer specifying the pin output value,
+ * 0 for logical 0, 1 (or any other non-zero value) for logical 1
+ */
+ void write(int value) {
+ // Thread safe / atomic HAL call
+ gpio_write(&gpio, value);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * an integer representing the output setting of the pin if it is an output,
+ * or read the input if set as an input
+ */
+ int read() {
+ // Thread safe / atomic HAL call
+ return gpio_read(&gpio);
+ }
+
+ /** Set as an output
+ */
+ void output() {
+ core_util_critical_section_enter();
+ gpio_dir(&gpio, PIN_OUTPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Set as an input
+ */
+ void input() {
+ core_util_critical_section_enter();
+ gpio_dir(&gpio, PIN_INPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the input pin mode
+ *
+ * @param pull PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode pull) {
+ core_util_critical_section_enter();
+ gpio_mode(&gpio, pull);
+ core_util_critical_section_exit();
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * Non zero value if pin is connected to uc GPIO
+ * 0 if gpio object was initialized with NC
+ */
+ int is_connected() {
+ // Thread safe / atomic HAL call
+ return gpio_is_connected(&gpio);
+ }
+
+ /** A shorthand for write()
+ */
+ DigitalInOut& operator= (int value) {
+ // Underlying write is thread safe
+ write(value);
+ return *this;
+ }
+
+ DigitalInOut& operator= (DigitalInOut& rhs) {
+ core_util_critical_section_enter();
+ write(rhs.read());
+ core_util_critical_section_exit();
+ return *this;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ // Underlying call is thread safe
+ return read();
+ }
+
+protected:
+ gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/DigitalOut.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,129 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALOUT_H
+#define MBED_DIGITALOUT_H
+
+#include "platform/platform.h"
+#include "hal/gpio_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital output, used for setting the state of a pin
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Toggle a LED
+ * #include "mbed.h"
+ *
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ * while(1) {
+ * led = !led;
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class DigitalOut {
+
+public:
+ /** Create a DigitalOut connected to the specified pin
+ *
+ * @param pin DigitalOut pin to connect to
+ */
+ DigitalOut(PinName pin) : gpio() {
+ // No lock needed in the constructor
+ gpio_init_out(&gpio, pin);
+ }
+
+ /** Create a DigitalOut connected to the specified pin
+ *
+ * @param pin DigitalOut pin to connect to
+ * @param value the initial pin value
+ */
+ DigitalOut(PinName pin, int value) : gpio() {
+ // No lock needed in the constructor
+ gpio_init_out_ex(&gpio, pin, value);
+ }
+
+ /** Set the output, specified as 0 or 1 (int)
+ *
+ * @param value An integer specifying the pin output value,
+ * 0 for logical 0, 1 (or any other non-zero value) for logical 1
+ */
+ void write(int value) {
+ // Thread safe / atomic HAL call
+ gpio_write(&gpio, value);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * an integer representing the output setting of the pin,
+ * 0 for logical 0, 1 for logical 1
+ */
+ int read() {
+ // Thread safe / atomic HAL call
+ return gpio_read(&gpio);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * Non zero value if pin is connected to uc GPIO
+ * 0 if gpio object was initialized with NC
+ */
+ int is_connected() {
+ // Thread safe / atomic HAL call
+ return gpio_is_connected(&gpio);
+ }
+
+ /** A shorthand for write()
+ */
+ DigitalOut& operator= (int value) {
+ // Underlying write is thread safe
+ write(value);
+ return *this;
+ }
+
+ DigitalOut& operator= (DigitalOut& rhs) {
+ core_util_critical_section_enter();
+ write(rhs.read());
+ core_util_critical_section_exit();
+ return *this;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ // Underlying call is thread safe
+ return read();
+ }
+
+protected:
+ gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/Ethernet.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,74 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Ethernet.h"
+
+#if DEVICE_ETHERNET
+
+#include "hal/ethernet_api.h"
+
+namespace mbed {
+
+Ethernet::Ethernet() {
+ ethernet_init();
+}
+
+Ethernet::~Ethernet() {
+ ethernet_free();
+}
+
+int Ethernet::write(const char *data, int size) {
+ return ethernet_write(data, size);
+}
+
+int Ethernet::send() {
+ return ethernet_send();
+}
+
+int Ethernet::receive() {
+ return ethernet_receive();
+}
+
+int Ethernet::read(char *data, int size) {
+ return ethernet_read(data, size);
+}
+
+void Ethernet::address(char *mac) {
+ return ethernet_address(mac);
+}
+
+int Ethernet::link() {
+ return ethernet_link();
+}
+
+void Ethernet::set_link(Mode mode) {
+ int speed = -1;
+ int duplex = 0;
+
+ switch(mode) {
+ case AutoNegotiate : speed = -1; duplex = 0; break;
+ case HalfDuplex10 : speed = 0; duplex = 0; break;
+ case FullDuplex10 : speed = 0; duplex = 1; break;
+ case HalfDuplex100 : speed = 1; duplex = 0; break;
+ case FullDuplex100 : speed = 1; duplex = 1; break;
+ }
+
+ ethernet_set_link(speed, duplex);
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/Ethernet.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,175 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_H
+#define MBED_ETHERNET_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_ETHERNET) || defined(DOXYGEN_ONLY)
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An ethernet interface, to use with the ethernet pins.
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Read destination and source from every ethernet packet
+ *
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ * char buf[0x600];
+ *
+ * while(1) {
+ * int size = eth.receive();
+ * if(size > 0) {
+ * eth.read(buf, size);
+ * printf("Destination: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ * buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ * printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ * buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
+ * }
+ *
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Ethernet {
+
+public:
+
+ /** Initialise the ethernet interface.
+ */
+ Ethernet();
+
+ /** Powers the hardware down.
+ */
+ virtual ~Ethernet();
+
+ enum Mode {
+ AutoNegotiate,
+ HalfDuplex10,
+ FullDuplex10,
+ HalfDuplex100,
+ FullDuplex100
+ };
+
+ /** Writes into an outgoing ethernet packet.
+ *
+ * It will append size bytes of data to the previously written bytes.
+ *
+ * @param data An array to write.
+ * @param size The size of data.
+ *
+ * @returns
+ * The number of written bytes.
+ */
+ int write(const char *data, int size);
+
+ /** Send an outgoing ethernet packet.
+ *
+ * After filling in the data in an ethernet packet it must be send.
+ * Send will provide a new packet to write to.
+ *
+ * @returns
+ * 0 if the sending was failed,
+ * or the size of the packet successfully sent.
+ */
+ int send();
+
+ /** Recevies an arrived ethernet packet.
+ *
+ * Receiving an ethernet packet will drop the last received ethernet packet
+ * and make a new ethernet packet ready to read.
+ * If no ethernet packet is arrived it will return 0.
+ *
+ * @returns
+ * 0 if no ethernet packet is arrived,
+ * or the size of the arrived packet.
+ */
+ int receive();
+
+ /** Read from an recevied ethernet packet.
+ *
+ * After receive returnd a number bigger than 0it is
+ * possible to read bytes from this packet.
+ * Read will write up to size bytes into data.
+ *
+ * It is possible to use read multible times.
+ * Each time read will start reading after the last read byte before.
+ *
+ * @returns
+ * The number of byte read.
+ */
+ int read(char *data, int size);
+
+ /** Gives the ethernet address of the mbed.
+ *
+ * @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
+ */
+ void address(char *mac);
+
+ /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
+ *
+ * @returns
+ * 0 if no ethernet link is pressent,
+ * 1 if an ethernet link is pressent.
+ *
+ * Example:
+ * @code
+ * // Using the Ethernet link function
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ * wait(1); // Needed after startup.
+ * if (eth.link()) {
+ * printf("online\n");
+ * } else {
+ * printf("offline\n");
+ * }
+ * }
+ * @endcode
+ */
+ int link();
+
+ /** Sets the speed and duplex parameters of an ethernet link
+ *
+ * - AutoNegotiate Auto negotiate speed and duplex
+ * - HalfDuplex10 10 Mbit, half duplex
+ * - FullDuplex10 10 Mbit, full duplex
+ * - HalfDuplex100 100 Mbit, half duplex
+ * - FullDuplex100 100 Mbit, full duplex
+ *
+ * @param mode the speed and duplex mode to set the link to:
+ */
+ void set_link(Mode mode);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/FlashIAP.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,168 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <string.h>
+#include "FlashIAP.h"
+#include "mbed_assert.h"
+
+
+#ifdef DEVICE_FLASH
+
+namespace mbed {
+
+SingletonPtr<PlatformMutex> FlashIAP::_mutex;
+
+static inline bool is_aligned(uint32_t number, uint32_t alignment)
+{
+ if ((number % alignment) != 0) {
+ return false;
+ } else {
+ return true;
+ }
+}
+
+FlashIAP::FlashIAP()
+{
+
+}
+
+FlashIAP::~FlashIAP()
+{
+
+}
+
+int FlashIAP::init()
+{
+ int ret = 0;
+ _mutex->lock();
+ if (flash_init(&_flash)) {
+ ret = -1;
+ }
+ _mutex->unlock();
+ return ret;
+}
+
+int FlashIAP::deinit()
+{
+ int ret = 0;
+ _mutex->lock();
+ if (flash_free(&_flash)) {
+ ret = -1;
+ }
+ _mutex->unlock();
+ return ret;
+}
+
+
+int FlashIAP::read(void *buffer, uint32_t addr, uint32_t size)
+{
+ _mutex->lock();
+ memcpy(buffer, (const void *)addr, size);
+ _mutex->unlock();
+ return 0;
+}
+
+int FlashIAP::program(const void *buffer, uint32_t addr, uint32_t size)
+{
+ uint32_t page_size = get_page_size();
+ uint32_t current_sector_size = flash_get_sector_size(&_flash, addr);
+ // addr and size should be aligned to page size, and multiple of page size
+ // page program should not cross sector boundaries
+ if (!is_aligned(addr, page_size) ||
+ !is_aligned(size, page_size) ||
+ (size < page_size) ||
+ (((addr % current_sector_size) + size) > current_sector_size)) {
+ return -1;
+ }
+
+ int ret = 0;
+ _mutex->lock();
+ if (flash_program_page(&_flash, addr, (const uint8_t *)buffer, size)) {
+ ret = -1;
+ }
+ _mutex->unlock();
+ return ret;
+}
+
+bool FlashIAP::is_aligned_to_sector(uint32_t addr, uint32_t size)
+{
+ uint32_t current_sector_size = flash_get_sector_size(&_flash, addr);
+ if (!is_aligned(size, current_sector_size) ||
+ !is_aligned(addr, current_sector_size)) {
+ return false;
+ } else {
+ return true;
+ }
+}
+
+int FlashIAP::erase(uint32_t addr, uint32_t size)
+{
+ uint32_t current_sector_size = 0UL;
+
+ if (!is_aligned_to_sector(addr, size)) {
+ return -1;
+ }
+
+ int32_t ret = 0;
+ _mutex->lock();
+ while (size) {
+ ret = flash_erase_sector(&_flash, addr);
+ if (ret != 0) {
+ ret = -1;
+ break;
+ }
+ current_sector_size = flash_get_sector_size(&_flash, addr);
+ if (!is_aligned_to_sector(addr, size)) {
+ ret = -1;
+ break;
+ }
+ size -= current_sector_size;
+ addr += current_sector_size;
+ }
+ _mutex->unlock();
+ return ret;
+}
+
+uint32_t FlashIAP::get_page_size() const
+{
+ return flash_get_page_size(&_flash);
+}
+
+uint32_t FlashIAP::get_sector_size(uint32_t addr) const
+{
+ return flash_get_sector_size(&_flash, addr);
+}
+
+uint32_t FlashIAP::get_flash_start() const
+{
+ return flash_get_start_address(&_flash);
+}
+
+uint32_t FlashIAP::get_flash_size() const
+{
+ return flash_get_size(&_flash);
+}
+
+}
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/FlashIAP.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,137 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_FLASHIAP_H
+#define MBED_FLASHIAP_H
+
+#if defined (DEVICE_FLASH) || defined(DOXYGEN_ONLY)
+
+#include "flash_api.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+
+namespace mbed {
+
+/** \addtogroup drivers */
+
+/** Flash IAP driver. It invokes flash HAL functions.
+ *
+ * @note Synchronization level: Thread safe
+ * @ingroup drivers
+ */
+class FlashIAP {
+public:
+ FlashIAP();
+ ~FlashIAP();
+
+ /** Initialize a flash IAP device
+ *
+ * Should be called once per lifetime of the object.
+ * @return 0 on success or a negative error code on failure
+ */
+ int init();
+
+ /** Deinitialize a flash IAP device
+ *
+ * @return 0 on success or a negative error code on failure
+ */
+ int deinit();
+
+ /** Read data from a flash device.
+ *
+ * This method invokes memcpy - reads number of bytes from the address
+ *
+ * @param buffer Buffer to write to
+ * @param addr Flash address to begin reading from
+ * @param size Size to read in bytes
+ * @return 0 on success, negative error code on failure
+ */
+ int read(void *buffer, uint32_t addr, uint32_t size);
+
+ /** Program data to pages
+ *
+ * The sectors must have been erased prior to being programmed
+ *
+ * @param buffer Buffer of data to be written
+ * @param addr Address of a page to begin writing to, must be a multiple of program and sector sizes
+ * @param size Size to write in bytes, must be a multiple of program and sector sizes
+ * @return 0 on success, negative error code on failure
+ */
+ int program(const void *buffer, uint32_t addr, uint32_t size);
+
+ /** Erase sectors
+ *
+ * The state of an erased sector is undefined until it has been programmed
+ *
+ * @param addr Address of a sector to begin erasing, must be a multiple of the sector size
+ * @param size Size to erase in bytes, must be a multiple of the sector size
+ * @return 0 on success, negative error code on failure
+ */
+ int erase(uint32_t addr, uint32_t size);
+
+ /** Get the sector size at the defined address
+ *
+ * Sector size might differ at address ranges.
+ * An example <0-0x1000, sector size=1024; 0x10000-0x20000, size=2048>
+ *
+ * @param addr Address of or inside the sector to query
+ * @return Size of a sector in bytes or MBED_FLASH_INVALID_SIZE if not mapped
+ */
+ uint32_t get_sector_size(uint32_t addr) const;
+
+ /** Get the flash start address
+ *
+ * @return Flash start address
+ */
+ uint32_t get_flash_start() const;
+
+ /** Get the flash size
+ *
+ * @return Flash size
+ */
+ uint32_t get_flash_size() const;
+
+ /** Get the program page size
+ *
+ * @return Size of a program page in bytes
+ */
+ uint32_t get_page_size() const;
+
+private:
+
+ /* Check if address and size are aligned to a sector
+ *
+ * @param addr Address of block to check for alignment
+ * @param size Size of block to check for alignment
+ * @return true if the block is sector aligned, false otherwise
+ */
+ bool is_aligned_to_sector(uint32_t addr, uint32_t size);
+
+ flash_t _flash;
+ static SingletonPtr<PlatformMutex> _mutex;
+};
+
+} /* namespace mbed */
+
+#endif /* DEVICE_FLASH */
+
+#endif /* MBED_FLASHIAP_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/I2C.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,164 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/I2C.h"
+
+#if DEVICE_I2C
+
+namespace mbed {
+
+I2C *I2C::_owner = NULL;
+SingletonPtr<PlatformMutex> I2C::_mutex;
+
+I2C::I2C(PinName sda, PinName scl) :
+#if DEVICE_I2C_ASYNCH
+ _irq(this), _usage(DMA_USAGE_NEVER),
+#endif
+ _i2c(), _hz(100000) {
+ // No lock needed in the constructor
+
+ // The init function also set the frequency to 100000
+ i2c_init(&_i2c, sda, scl);
+
+ // Used to avoid unnecessary frequency updates
+ _owner = this;
+}
+
+void I2C::frequency(int hz) {
+ lock();
+ _hz = hz;
+
+ // We want to update the frequency even if we are already the bus owners
+ i2c_frequency(&_i2c, _hz);
+
+ // Updating the frequency of the bus we become the owners of it
+ _owner = this;
+ unlock();
+}
+
+void I2C::aquire() {
+ lock();
+ if (_owner != this) {
+ i2c_frequency(&_i2c, _hz);
+ _owner = this;
+ }
+ unlock();
+}
+
+// write - Master Transmitter Mode
+int I2C::write(int address, const char* data, int length, bool repeated) {
+ lock();
+ aquire();
+
+ int stop = (repeated) ? 0 : 1;
+ int written = i2c_write(&_i2c, address, data, length, stop);
+
+ unlock();
+ return length != written;
+}
+
+int I2C::write(int data) {
+ lock();
+ int ret = i2c_byte_write(&_i2c, data);
+ unlock();
+ return ret;
+}
+
+// read - Master Reciever Mode
+int I2C::read(int address, char* data, int length, bool repeated) {
+ lock();
+ aquire();
+
+ int stop = (repeated) ? 0 : 1;
+ int read = i2c_read(&_i2c, address, data, length, stop);
+
+ unlock();
+ return length != read;
+}
+
+int I2C::read(int ack) {
+ lock();
+ int ret;
+ if (ack) {
+ ret = i2c_byte_read(&_i2c, 0);
+ } else {
+ ret = i2c_byte_read(&_i2c, 1);
+ }
+ unlock();
+ return ret;
+}
+
+void I2C::start(void) {
+ lock();
+ i2c_start(&_i2c);
+ unlock();
+}
+
+void I2C::stop(void) {
+ lock();
+ i2c_stop(&_i2c);
+ unlock();
+}
+
+void I2C::lock() {
+ _mutex->lock();
+}
+
+void I2C::unlock() {
+ _mutex->unlock();
+}
+
+#if DEVICE_I2C_ASYNCH
+
+int I2C::transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event, bool repeated)
+{
+ lock();
+ if (i2c_active(&_i2c)) {
+ unlock();
+ return -1; // transaction ongoing
+ }
+ aquire();
+
+ _callback = callback;
+ int stop = (repeated) ? 0 : 1;
+ _irq.callback(&I2C::irq_handler_asynch);
+ i2c_transfer_asynch(&_i2c, (void *)tx_buffer, tx_length, (void *)rx_buffer, rx_length, address, stop, _irq.entry(), event, _usage);
+ unlock();
+ return 0;
+}
+
+void I2C::abort_transfer(void)
+{
+ lock();
+ i2c_abort_asynch(&_i2c);
+ unlock();
+}
+
+void I2C::irq_handler_asynch(void)
+{
+ int event = i2c_irq_handler_asynch(&_i2c);
+ if (_callback && event) {
+ _callback.call(event);
+ }
+
+}
+
+
+#endif
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/I2C.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,197 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_H
+#define MBED_I2C_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_I2C) || defined(DOXYGEN_ONLY)
+
+#include "hal/i2c_api.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+
+#if DEVICE_I2C_ASYNCH
+#include "platform/CThunk.h"
+#include "hal/dma_api.h"
+#include "platform/FunctionPointer.h"
+#endif
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An I2C Master, used for communicating with I2C slave devices
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Read from I2C slave at address 0x62
+ *
+ * #include "mbed.h"
+ *
+ * I2C i2c(p28, p27);
+ *
+ * int main() {
+ * int address = 0x62;
+ * char data[2];
+ * i2c.read(address, data, 2);
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class I2C {
+
+public:
+ enum RxStatus {
+ NoData,
+ MasterGeneralCall,
+ MasterWrite,
+ MasterRead
+ };
+
+ enum Acknowledge {
+ NoACK = 0,
+ ACK = 1
+ };
+
+ /** Create an I2C Master interface, connected to the specified pins
+ *
+ * @param sda I2C data line pin
+ * @param scl I2C clock line pin
+ */
+ I2C(PinName sda, PinName scl);
+
+ /** Set the frequency of the I2C interface
+ *
+ * @param hz The bus frequency in hertz
+ */
+ void frequency(int hz);
+
+ /** Read from an I2C slave
+ *
+ * Performs a complete read transaction. The bottom bit of
+ * the address is forced to 1 to indicate a read.
+ *
+ * @param address 8-bit I2C slave address [ addr | 1 ]
+ * @param data Pointer to the byte-array to read data in to
+ * @param length Number of bytes to read
+ * @param repeated Repeated start, true - don't send stop at end
+ *
+ * @returns
+ * 0 on success (ack),
+ * non-0 on failure (nack)
+ */
+ int read(int address, char *data, int length, bool repeated = false);
+
+ /** Read a single byte from the I2C bus
+ *
+ * @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
+ *
+ * @returns
+ * the byte read
+ */
+ int read(int ack);
+
+ /** Write to an I2C slave
+ *
+ * Performs a complete write transaction. The bottom bit of
+ * the address is forced to 0 to indicate a write.
+ *
+ * @param address 8-bit I2C slave address [ addr | 0 ]
+ * @param data Pointer to the byte-array data to send
+ * @param length Number of bytes to send
+ * @param repeated Repeated start, true - do not send stop at end
+ *
+ * @returns
+ * 0 on success (ack),
+ * non-0 on failure (nack)
+ */
+ int write(int address, const char *data, int length, bool repeated = false);
+
+ /** Write single byte out on the I2C bus
+ *
+ * @param data data to write out on bus
+ *
+ * @returns
+ * '0' - NAK was received
+ * '1' - ACK was received,
+ * '2' - timeout
+ */
+ int write(int data);
+
+ /** Creates a start condition on the I2C bus
+ */
+
+ void start(void);
+
+ /** Creates a stop condition on the I2C bus
+ */
+ void stop(void);
+
+ /** Acquire exclusive access to this I2C bus
+ */
+ virtual void lock(void);
+
+ /** Release exclusive access to this I2C bus
+ */
+ virtual void unlock(void);
+
+ virtual ~I2C() {
+ // Do nothing
+ }
+
+#if DEVICE_I2C_ASYNCH
+
+ /** Start non-blocking I2C transfer.
+ *
+ * @param address 8/10 bit I2c slave address
+ * @param tx_buffer The TX buffer with data to be transfered
+ * @param tx_length The length of TX buffer in bytes
+ * @param rx_buffer The RX buffer which is used for received data
+ * @param rx_length The length of RX buffer in bytes
+ * @param event The logical OR of events to modify
+ * @param callback The event callback function
+ * @param repeated Repeated start, true - do not send stop at end
+ * @return Zero if the transfer has started, or -1 if I2C peripheral is busy
+ */
+ int transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event = I2C_EVENT_TRANSFER_COMPLETE, bool repeated = false);
+
+ /** Abort the on-going I2C transfer
+ */
+ void abort_transfer();
+protected:
+ void irq_handler_asynch(void);
+ event_callback_t _callback;
+ CThunk<I2C> _irq;
+ DMAUsage _usage;
+#endif
+
+protected:
+ void aquire();
+
+ i2c_t _i2c;
+ static I2C *_owner;
+ int _hz;
+ static SingletonPtr<PlatformMutex> _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/I2CSlave.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/I2CSlave.h"
+
+#if DEVICE_I2CSLAVE
+
+namespace mbed {
+
+I2CSlave::I2CSlave(PinName sda, PinName scl) : _i2c() {
+ i2c_init(&_i2c, sda, scl);
+ i2c_frequency(&_i2c, 100000);
+ i2c_slave_mode(&_i2c, 1);
+}
+
+void I2CSlave::frequency(int hz) {
+ i2c_frequency(&_i2c, hz);
+}
+
+void I2CSlave::address(int address) {
+ int addr = (address & 0xFF) | 1;
+ i2c_slave_address(&_i2c, 0, addr, 0);
+}
+
+int I2CSlave::receive(void) {
+ return i2c_slave_receive(&_i2c);
+}
+
+int I2CSlave::read(char *data, int length) {
+ return i2c_slave_read(&_i2c, data, length) != length;
+}
+
+int I2CSlave::read(void) {
+ return i2c_byte_read(&_i2c, 0);
+}
+
+int I2CSlave::write(const char *data, int length) {
+ return i2c_slave_write(&_i2c, data, length) != length;
+}
+
+int I2CSlave::write(int data) {
+ return i2c_byte_write(&_i2c, data);
+}
+
+void I2CSlave::stop(void) {
+ i2c_stop(&_i2c);
+}
+
+}
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/I2CSlave.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,159 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_SLAVE_H
+#define MBED_I2C_SLAVE_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_I2CSLAVE) || defined(DOXYGEN_ONLY)
+
+#include "hal/i2c_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** An I2C Slave, used for communicating with an I2C Master device
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Simple I2C responder
+ * #include <mbed.h>
+ *
+ * I2CSlave slave(p9, p10);
+ *
+ * int main() {
+ * char buf[10];
+ * char msg[] = "Slave!";
+ *
+ * slave.address(0xA0);
+ * while (1) {
+ * int i = slave.receive();
+ * switch (i) {
+ * case I2CSlave::ReadAddressed:
+ * slave.write(msg, strlen(msg) + 1); // Includes null char
+ * break;
+ * case I2CSlave::WriteGeneral:
+ * slave.read(buf, 10);
+ * printf("Read G: %s\n", buf);
+ * break;
+ * case I2CSlave::WriteAddressed:
+ * slave.read(buf, 10);
+ * printf("Read A: %s\n", buf);
+ * break;
+ * }
+ * for(int i = 0; i < 10; i++) buf[i] = 0; // Clear buffer
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class I2CSlave {
+
+public:
+ enum RxStatus {
+ NoData = 0,
+ ReadAddressed = 1,
+ WriteGeneral = 2,
+ WriteAddressed = 3
+ };
+
+ /** Create an I2C Slave interface, connected to the specified pins.
+ *
+ * @param sda I2C data line pin
+ * @param scl I2C clock line pin
+ */
+ I2CSlave(PinName sda, PinName scl);
+
+ /** Set the frequency of the I2C interface
+ *
+ * @param hz The bus frequency in hertz
+ */
+ void frequency(int hz);
+
+ /** Checks to see if this I2C Slave has been addressed.
+ *
+ * @returns
+ * A status indicating if the device has been addressed, and how
+ * - NoData - the slave has not been addressed
+ * - ReadAddressed - the master has requested a read from this slave
+ * - WriteAddressed - the master is writing to this slave
+ * - WriteGeneral - the master is writing to all slave
+ */
+ int receive(void);
+
+ /** Read from an I2C master.
+ *
+ * @param data pointer to the byte array to read data in to
+ * @param length maximum number of bytes to read
+ *
+ * @returns
+ * 0 on success,
+ * non-0 otherwise
+ */
+ int read(char *data, int length);
+
+ /** Read a single byte from an I2C master.
+ *
+ * @returns
+ * the byte read
+ */
+ int read(void);
+
+ /** Write to an I2C master.
+ *
+ * @param data pointer to the byte array to be transmitted
+ * @param length the number of bytes to transmite
+ *
+ * @returns
+ * 0 on success,
+ * non-0 otherwise
+ */
+ int write(const char *data, int length);
+
+ /** Write a single byte to an I2C master.
+ *
+ * @param data the byte to write
+ *
+ * @returns
+ * '1' if an ACK was received,
+ * '0' otherwise
+ */
+ int write(int data);
+
+ /** Sets the I2C slave address.
+ *
+ * @param address The address to set for the slave (ignoring the least
+ * signifcant bit). If set to 0, the slave will only respond to the
+ * general call address.
+ */
+ void address(int address);
+
+ /** Reset the I2C slave back into the known ready receiving state.
+ */
+ void stop(void);
+
+protected:
+ i2c_t _i2c;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/InterruptIn.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/InterruptIn.h"
+
+#if DEVICE_INTERRUPTIN
+
+namespace mbed {
+
+static void donothing() {}
+
+InterruptIn::InterruptIn(PinName pin) : gpio(),
+ gpio_irq(),
+ _rise(),
+ _fall() {
+ // No lock needed in the constructor
+
+ _rise = donothing;
+ _fall = donothing;
+
+ gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
+ gpio_init_in(&gpio, pin);
+}
+
+InterruptIn::~InterruptIn() {
+ // No lock needed in the destructor
+ gpio_irq_free(&gpio_irq);
+}
+
+int InterruptIn::read() {
+ // Read only
+ return gpio_read(&gpio);
+}
+
+void InterruptIn::mode(PinMode pull) {
+ core_util_critical_section_enter();
+ gpio_mode(&gpio, pull);
+ core_util_critical_section_exit();
+}
+
+void InterruptIn::rise(Callback<void()> func) {
+ core_util_critical_section_enter();
+ if (func) {
+ _rise = func;
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+ } else {
+ _rise = donothing;
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
+ }
+ core_util_critical_section_exit();
+}
+
+void InterruptIn::fall(Callback<void()> func) {
+ core_util_critical_section_enter();
+ if (func) {
+ _fall = func;
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+ } else {
+ _fall = donothing;
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
+ }
+ core_util_critical_section_exit();
+}
+
+void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
+ InterruptIn *handler = (InterruptIn*)id;
+ switch (event) {
+ case IRQ_RISE: handler->_rise(); break;
+ case IRQ_FALL: handler->_fall(); break;
+ case IRQ_NONE: break;
+ }
+}
+
+void InterruptIn::enable_irq() {
+ core_util_critical_section_enter();
+ gpio_irq_enable(&gpio_irq);
+ core_util_critical_section_exit();
+}
+
+void InterruptIn::disable_irq() {
+ core_util_critical_section_enter();
+ gpio_irq_disable(&gpio_irq);
+ core_util_critical_section_exit();
+}
+
+InterruptIn::operator int() {
+ // Underlying call is atomic
+ return read();
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/InterruptIn.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,162 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERRUPTIN_H
+#define MBED_INTERRUPTIN_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_INTERRUPTIN) || defined(DOXYGEN_ONLY)
+
+#include "hal/gpio_api.h"
+#include "hal/gpio_irq_api.h"
+#include "platform/Callback.h"
+#include "platform/mbed_critical.h"
+#include "platform/mbed_toolchain.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A digital interrupt input, used to call a function on a rising or falling edge
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Flash an LED while waiting for events
+ *
+ * #include "mbed.h"
+ *
+ * InterruptIn event(p16);
+ * DigitalOut led(LED1);
+ *
+ * void trigger() {
+ * printf("triggered!\n");
+ * }
+ *
+ * int main() {
+ * event.rise(&trigger);
+ * while(1) {
+ * led = !led;
+ * wait(0.25);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class InterruptIn {
+
+public:
+
+ /** Create an InterruptIn connected to the specified pin
+ *
+ * @param pin InterruptIn pin to connect to
+ */
+ InterruptIn(PinName pin);
+ virtual ~InterruptIn();
+
+ /** Read the input, represented as 0 or 1 (int)
+ *
+ * @returns
+ * An integer representing the state of the input pin,
+ * 0 for logical 0, 1 for logical 1
+ */
+ int read();
+
+ /** An operator shorthand for read()
+ */
+ operator int();
+
+
+ /** Attach a function to call when a rising edge occurs on the input
+ *
+ * @param func A pointer to a void function, or 0 to set as none
+ */
+ void rise(Callback<void()> func);
+
+ /** Attach a member function to call when a rising edge occurs on the input
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @deprecated
+ * The rise function does not support cv-qualifiers. Replaced by
+ * rise(callback(obj, method)).
+ */
+ template<typename T, typename M>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The rise function does not support cv-qualifiers. Replaced by "
+ "rise(callback(obj, method)).")
+ void rise(T *obj, M method) {
+ core_util_critical_section_enter();
+ rise(callback(obj, method));
+ core_util_critical_section_exit();
+ }
+
+ /** Attach a function to call when a falling edge occurs on the input
+ *
+ * @param func A pointer to a void function, or 0 to set as none
+ */
+ void fall(Callback<void()> func);
+
+ /** Attach a member function to call when a falling edge occurs on the input
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @deprecated
+ * The rise function does not support cv-qualifiers. Replaced by
+ * rise(callback(obj, method)).
+ */
+ template<typename T, typename M>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The fall function does not support cv-qualifiers. Replaced by "
+ "fall(callback(obj, method)).")
+ void fall(T *obj, M method) {
+ core_util_critical_section_enter();
+ fall(callback(obj, method));
+ core_util_critical_section_exit();
+ }
+
+ /** Set the input pin mode
+ *
+ * @param pull PullUp, PullDown, PullNone
+ */
+ void mode(PinMode pull);
+
+ /** Enable IRQ. This method depends on hw implementation, might enable one
+ * port interrupts. For further information, check gpio_irq_enable().
+ */
+ void enable_irq();
+
+ /** Disable IRQ. This method depends on hw implementation, might disable one
+ * port interrupts. For further information, check gpio_irq_disable().
+ */
+ void disable_irq();
+
+ static void _irq_handler(uint32_t id, gpio_irq_event event);
+
+protected:
+ gpio_t gpio;
+ gpio_irq_t gpio_irq;
+
+ Callback<void()> _rise;
+ Callback<void()> _fall;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/InterruptManager.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,138 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#if defined(NVIC_NUM_VECTORS)
+
+#include "drivers/InterruptManager.h"
+#include "platform/mbed_critical.h"
+#include <string.h>
+
+#define CHAIN_INITIAL_SIZE 4
+
+namespace mbed {
+
+typedef void (*pvoidf)(void);
+
+InterruptManager* InterruptManager::_instance = (InterruptManager*)NULL;
+
+InterruptManager* InterruptManager::get() {
+
+ if (NULL == _instance) {
+ InterruptManager* temp = new InterruptManager();
+
+ // Atomically set _instance
+ core_util_critical_section_enter();
+ if (NULL == _instance) {
+ _instance = temp;
+ }
+ core_util_critical_section_exit();
+
+ // Another thread got there first so delete ours
+ if (temp != _instance) {
+ delete temp;
+ }
+
+ }
+ return _instance;
+}
+
+InterruptManager::InterruptManager() {
+ // No mutex needed in constructor
+ memset(_chains, 0, NVIC_NUM_VECTORS * sizeof(CallChain*));
+}
+
+void InterruptManager::destroy() {
+ // Not a good idea to call this unless NO interrupt at all
+ // is under the control of the handler; otherwise, a system crash
+ // is very likely to occur
+ if (NULL != _instance) {
+ delete _instance;
+ _instance = (InterruptManager*)NULL;
+ }
+}
+
+InterruptManager::~InterruptManager() {
+ for(int i = 0; i < NVIC_NUM_VECTORS; i++)
+ if (NULL != _chains[i])
+ delete _chains[i];
+}
+
+bool InterruptManager::must_replace_vector(IRQn_Type irq) {
+ lock();
+
+ int ret = false;
+ int irq_pos = get_irq_index(irq);
+ if (NULL == _chains[irq_pos]) {
+ _chains[irq_pos] = new CallChain(CHAIN_INITIAL_SIZE);
+ _chains[irq_pos]->add((pvoidf)NVIC_GetVector(irq));
+ ret = true;
+ }
+ unlock();
+ return ret;
+}
+
+pFunctionPointer_t InterruptManager::add_common(void (*function)(void), IRQn_Type irq, bool front) {
+ lock();
+ int irq_pos = get_irq_index(irq);
+ bool change = must_replace_vector(irq);
+
+ pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(function) : _chains[irq_pos]->add(function);
+ if (change)
+ NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+ unlock();
+ return pf;
+}
+
+bool InterruptManager::remove_handler(pFunctionPointer_t handler, IRQn_Type irq) {
+ int irq_pos = get_irq_index(irq);
+ bool ret = false;
+
+ lock();
+ if (_chains[irq_pos] != NULL) {
+ if (_chains[irq_pos]->remove(handler)) {
+ ret = true;
+ }
+ }
+ unlock();
+
+ return ret;
+}
+
+void InterruptManager::irq_helper() {
+ _chains[__get_IPSR()]->call();
+}
+
+int InterruptManager::get_irq_index(IRQn_Type irq) {
+ // Pure function - no lock needed
+ return (int)irq + NVIC_USER_IRQ_OFFSET;
+}
+
+void InterruptManager::static_irq_helper() {
+ InterruptManager::get()->irq_helper();
+}
+
+void InterruptManager::lock() {
+ _mutex.lock();
+}
+
+void InterruptManager::unlock() {
+ _mutex.unlock();
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/InterruptManager.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,173 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERRUPTMANAGER_H
+#define MBED_INTERRUPTMANAGER_H
+
+#include "cmsis.h"
+#include "platform/CallChain.h"
+#include "platform/PlatformMutex.h"
+#include <string.h>
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Use this singleton if you need to chain interrupt handlers.
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example (for LPC1768):
+ * @code
+ * #include "InterruptManager.h"
+ * #include "mbed.h"
+ *
+ * Ticker flipper;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * void flip(void) {
+ * led1 = !led1;
+ * }
+ *
+ * void handler(void) {
+ * led2 = !led1;
+ * }
+ *
+ * int main() {
+ * led1 = led2 = 0;
+ * flipper.attach(&flip, 1.0);
+ * InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class InterruptManager {
+public:
+ /** Return the only instance of this class
+ */
+ static InterruptManager* get();
+
+ /** Destroy the current instance of the interrupt manager
+ */
+ static void destroy();
+
+ /** Add a handler for an interrupt at the end of the handler list
+ *
+ * @param function the handler to add
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
+ // Underlying call is thread safe
+ return add_common(function, irq);
+ }
+
+ /** Add a handler for an interrupt at the beginning of the handler list
+ *
+ * @param function the handler to add
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
+ // Underlying call is thread safe
+ return add_common(function, irq, true);
+ }
+
+ /** Add a handler for an interrupt at the end of the handler list
+ *
+ * @param tptr pointer to the object that has the handler function
+ * @param mptr pointer to the actual handler function
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+ // Underlying call is thread safe
+ return add_common(tptr, mptr, irq);
+ }
+
+ /** Add a handler for an interrupt at the beginning of the handler list
+ *
+ * @param tptr pointer to the object that has the handler function
+ * @param mptr pointer to the actual handler function
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+ // Underlying call is thread safe
+ return add_common(tptr, mptr, irq, true);
+ }
+
+ /** Remove a handler from an interrupt
+ *
+ * @param handler the function object for the handler to remove
+ * @param irq the interrupt number
+ *
+ * @returns
+ * true if the handler was found and removed, false otherwise
+ */
+ bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
+
+private:
+ InterruptManager();
+ ~InterruptManager();
+
+ void lock();
+ void unlock();
+
+ // We declare the copy contructor and the assignment operator, but we don't
+ // implement them. This way, if someone tries to copy/assign our instance,
+ // he will get an error at compile time.
+ InterruptManager(const InterruptManager&);
+ InterruptManager& operator =(const InterruptManager&);
+
+ template<typename T>
+ pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
+ _mutex.lock();
+ int irq_pos = get_irq_index(irq);
+ bool change = must_replace_vector(irq);
+
+ pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
+ if (change)
+ NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+ _mutex.unlock();
+ return pf;
+ }
+
+ pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
+ bool must_replace_vector(IRQn_Type irq);
+ int get_irq_index(IRQn_Type irq);
+ void irq_helper();
+ void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
+ static void static_irq_helper();
+
+ CallChain* _chains[NVIC_NUM_VECTORS];
+ static InterruptManager* _instance;
+ PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/LowPowerTicker.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTICKER_H
+#define MBED_LOWPOWERTICKER_H
+
+#include "platform/platform.h"
+#include "drivers/Ticker.h"
+
+#if defined (DEVICE_LOWPOWERTIMER) || defined(DOXYGEN_ONLY)
+
+#include "hal/lp_ticker_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Low Power Ticker
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class LowPowerTicker : public Ticker {
+
+public:
+ LowPowerTicker() : Ticker(get_lp_ticker_data()) {
+ }
+
+ virtual ~LowPowerTicker() {
+ }
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/LowPowerTimeout.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTIMEOUT_H
+#define MBED_LOWPOWERTIMEOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_LOWPOWERTIMER) || defined(DOXYGEN_ONLY)
+
+#include "hal/lp_ticker_api.h"
+#include "drivers/LowPowerTicker.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Low Power Timout
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class LowPowerTimeout : public LowPowerTicker {
+
+private:
+ virtual void handler(void) {
+ _function.call();
+ }
+};
+
+}
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/LowPowerTimer.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTIMER_H
+#define MBED_LOWPOWERTIMER_H
+
+#include "platform/platform.h"
+#include "drivers/Timer.h"
+
+#if defined (DEVICE_LOWPOWERTIMER) || defined(DOXYGEN_ONLY)
+
+#include "hal/lp_ticker_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Low power timer
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class LowPowerTimer : public Timer {
+
+public:
+ LowPowerTimer() : Timer(get_lp_ticker_data()) {
+ }
+
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/PortIn.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTIN_H
+#define MBED_PORTIN_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_PORTIN) || defined(DOXYGEN_ONLY)
+
+#include "hal/port_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A multiple pin digital input
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Switch on an LED if any of mbed pins 21-26 is high
+ *
+ * #include "mbed.h"
+ *
+ * PortIn p(Port2, 0x0000003F); // p21-p26
+ * DigitalOut ind(LED4);
+ *
+ * int main() {
+ * while(1) {
+ * int pins = p.read();
+ * if(pins) {
+ * ind = 1;
+ * } else {
+ * ind = 0;
+ * }
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class PortIn {
+public:
+
+ /** Create an PortIn, connected to the specified port
+ *
+ * @param port Port to connect to (Port0-Port5)
+ * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ */
+ PortIn(PortName port, int mask = 0xFFFFFFFF) {
+ core_util_critical_section_enter();
+ port_init(&_port, port, mask, PIN_INPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Read the value currently output on the port
+ *
+ * @returns
+ * An integer with each bit corresponding to associated port pin setting
+ */
+ int read() {
+ return port_read(&_port);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode mode) {
+ core_util_critical_section_enter();
+ port_mode(&_port, mode);
+ core_util_critical_section_exit();
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+
+private:
+ port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/PortInOut.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,118 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTINOUT_H
+#define MBED_PORTINOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_PORTINOUT) || defined(DOXYGEN_ONLY)
+
+#include "hal/port_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A multiple pin digital in/out used to set/read multiple bi-directional pins
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class PortInOut {
+public:
+
+ /** Create an PortInOut, connected to the specified port
+ *
+ * @param port Port to connect to (Port0-Port5)
+ * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ */
+ PortInOut(PortName port, int mask = 0xFFFFFFFF) {
+ core_util_critical_section_enter();
+ port_init(&_port, port, mask, PIN_INPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Write the value to the output port
+ *
+ * @param value An integer specifying a bit to write for every corresponding port pin
+ */
+ void write(int value) {
+ port_write(&_port, value);
+ }
+
+ /** Read the value currently output on the port
+ *
+ * @returns
+ * An integer with each bit corresponding to associated port pin setting
+ */
+ int read() {
+ return port_read(&_port);
+ }
+
+ /** Set as an output
+ */
+ void output() {
+ core_util_critical_section_enter();
+ port_dir(&_port, PIN_OUTPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Set as an input
+ */
+ void input() {
+ core_util_critical_section_enter();
+ port_dir(&_port, PIN_INPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode mode) {
+ core_util_critical_section_enter();
+ port_mode(&_port, mode);
+ core_util_critical_section_exit();
+ }
+
+ /** A shorthand for write()
+ */
+ PortInOut& operator= (int value) {
+ write(value);
+ return *this;
+ }
+
+ PortInOut& operator= (PortInOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+
+private:
+ port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/PortOut.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,112 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTOUT_H
+#define MBED_PORTOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_PORTOUT) || defined(DOXYGEN_ONLY)
+
+#include "hal/port_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+/** A multiple pin digital out
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Toggle all four LEDs
+ *
+ * #include "mbed.h"
+ *
+ * // LED1 = P1.18 LED2 = P1.20 LED3 = P1.21 LED4 = P1.23
+ * #define LED_MASK 0x00B40000
+ *
+ * PortOut ledport(Port1, LED_MASK);
+ *
+ * int main() {
+ * while(1) {
+ * ledport = LED_MASK;
+ * wait(1);
+ * ledport = 0;
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class PortOut {
+public:
+
+ /** Create an PortOut, connected to the specified port
+ *
+ * @param port Port to connect to (Port0-Port5)
+ * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ */
+ PortOut(PortName port, int mask = 0xFFFFFFFF) {
+ core_util_critical_section_enter();
+ port_init(&_port, port, mask, PIN_OUTPUT);
+ core_util_critical_section_exit();
+ }
+
+ /** Write the value to the output port
+ *
+ * @param value An integer specifying a bit to write for every corresponding PortOut pin
+ */
+ void write(int value) {
+ port_write(&_port, value);
+ }
+
+ /** Read the value currently output on the port
+ *
+ * @returns
+ * An integer with each bit corresponding to associated PortOut pin setting
+ */
+ int read() {
+ return port_read(&_port);
+ }
+
+ /** A shorthand for write()
+ */
+ PortOut& operator= (int value) {
+ write(value);
+ return *this;
+ }
+
+ PortOut& operator= (PortOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+
+private:
+ port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/PwmOut.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,185 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_H
+#define MBED_PWMOUT_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_PWMOUT) || defined(DOXYGEN_ONLY)
+#include "hal/pwmout_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A pulse-width modulation digital output
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example
+ * @code
+ * // Fade a led on.
+ * #include "mbed.h"
+ *
+ * PwmOut led(LED1);
+ *
+ * int main() {
+ * while(1) {
+ * led = led + 0.01;
+ * wait(0.2);
+ * if(led == 1.0) {
+ * led = 0;
+ * }
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class PwmOut {
+
+public:
+
+ /** Create a PwmOut connected to the specified pin
+ *
+ * @param pin PwmOut pin to connect to
+ */
+ PwmOut(PinName pin) {
+ core_util_critical_section_enter();
+ pwmout_init(&_pwm, pin);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the ouput duty-cycle, specified as a percentage (float)
+ *
+ * @param value A floating-point value representing the output duty-cycle,
+ * specified as a percentage. The value should lie between
+ * 0.0f (representing on 0%) and 1.0f (representing on 100%).
+ * Values outside this range will be saturated to 0.0f or 1.0f.
+ */
+ void write(float value) {
+ core_util_critical_section_enter();
+ pwmout_write(&_pwm, value);
+ core_util_critical_section_exit();
+ }
+
+ /** Return the current output duty-cycle setting, measured as a percentage (float)
+ *
+ * @returns
+ * A floating-point value representing the current duty-cycle being output on the pin,
+ * measured as a percentage. The returned value will lie between
+ * 0.0f (representing on 0%) and 1.0f (representing on 100%).
+ *
+ * @note
+ * This value may not match exactly the value set by a previous write().
+ */
+ float read() {
+ core_util_critical_section_enter();
+ float val = pwmout_read(&_pwm);
+ core_util_critical_section_exit();
+ return val;
+ }
+
+ /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
+ *
+ * @param seconds Change the period of a PWM signal in seconds (float) without modifying the duty cycle
+ * @note
+ * The resolution is currently in microseconds; periods smaller than this
+ * will be set to zero.
+ */
+ void period(float seconds) {
+ core_util_critical_section_enter();
+ pwmout_period(&_pwm, seconds);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
+ * @param ms Change the period of a PWM signal in milli-seconds without modifying the duty cycle
+ */
+ void period_ms(int ms) {
+ core_util_critical_section_enter();
+ pwmout_period_ms(&_pwm, ms);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
+ * @param us Change the period of a PWM signal in micro-seconds without modifying the duty cycle
+ */
+ void period_us(int us) {
+ core_util_critical_section_enter();
+ pwmout_period_us(&_pwm, us);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
+ * @param seconds Change the pulse width of a PWM signal specified in seconds (float)
+ */
+ void pulsewidth(float seconds) {
+ core_util_critical_section_enter();
+ pwmout_pulsewidth(&_pwm, seconds);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
+ * @param ms Change the pulse width of a PWM signal specified in milli-seconds
+ */
+ void pulsewidth_ms(int ms) {
+ core_util_critical_section_enter();
+ pwmout_pulsewidth_ms(&_pwm, ms);
+ core_util_critical_section_exit();
+ }
+
+ /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
+ * @param us Change the pulse width of a PWM signal specified in micro-seconds
+ */
+ void pulsewidth_us(int us) {
+ core_util_critical_section_enter();
+ pwmout_pulsewidth_us(&_pwm, us);
+ core_util_critical_section_exit();
+ }
+
+ /** A operator shorthand for write()
+ */
+ PwmOut& operator= (float value) {
+ // Underlying call is thread safe
+ write(value);
+ return *this;
+ }
+
+ /** A operator shorthand for write()
+ */
+ PwmOut& operator= (PwmOut& rhs) {
+ // Underlying call is thread safe
+ write(rhs.read());
+ return *this;
+ }
+
+ /** An operator shorthand for read()
+ */
+ operator float() {
+ // Underlying call is thread safe
+ return read();
+ }
+
+protected:
+ pwmout_t _pwm;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/RawSerial.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,96 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/RawSerial.h"
+#include "platform/mbed_wait_api.h"
+#include <stdio.h>
+#include <cstdarg>
+
+
+#if DEVICE_SERIAL
+
+#define STRING_STACK_LIMIT 120
+
+namespace mbed {
+
+RawSerial::RawSerial(PinName tx, PinName rx, int baud) : SerialBase(tx, rx, baud) {
+ // No lock needed in the constructor
+}
+
+int RawSerial::getc() {
+ lock();
+ int ret = _base_getc();
+ unlock();
+ return ret;
+}
+
+int RawSerial::putc(int c) {
+ lock();
+ int ret = _base_putc(c);
+ unlock();
+ return ret;
+}
+
+int RawSerial::puts(const char *str) {
+ lock();
+ while (*str)
+ putc(*str ++);
+ unlock();
+ return 0;
+}
+
+// Experimental support for printf in RawSerial. No Stream inheritance
+// means we can't call printf() directly, so we use sprintf() instead.
+// We only call malloc() for the sprintf() buffer if the buffer
+// length is above a certain threshold, otherwise we use just the stack.
+int RawSerial::printf(const char *format, ...) {
+ lock();
+ std::va_list arg;
+ va_start(arg, format);
+ // ARMCC microlib does not properly handle a size of 0.
+ // As a workaround supply a dummy buffer with a size of 1.
+ char dummy_buf[1];
+ int len = vsnprintf(dummy_buf, sizeof(dummy_buf), format, arg);
+ if (len < STRING_STACK_LIMIT) {
+ char temp[STRING_STACK_LIMIT];
+ vsprintf(temp, format, arg);
+ puts(temp);
+ } else {
+ char *temp = new char[len + 1];
+ vsprintf(temp, format, arg);
+ puts(temp);
+ delete[] temp;
+ }
+ va_end(arg);
+ unlock();
+ return len;
+}
+
+/** Acquire exclusive access to this serial port
+ */
+void RawSerial::lock() {
+ // No lock used - external synchronization required
+}
+
+/** Release exclusive access to this serial port
+ */
+void RawSerial::unlock() {
+ // No lock used - external synchronization required
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/RawSerial.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RAW_SERIAL_H
+#define MBED_RAW_SERIAL_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY)
+
+#include "drivers/SerialBase.h"
+#include "hal/serial_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A serial port (UART) for communication with other serial devices
+ * This is a variation of the Serial class that doesn't use streams,
+ * thus making it safe to use in interrupt handlers with the RTOS.
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Send a char to the PC
+ *
+ * #include "mbed.h"
+ *
+ * RawSerial pc(USBTX, USBRX);
+ *
+ * int main() {
+ * pc.putc('A');
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class RawSerial: public SerialBase {
+
+public:
+ /** Create a RawSerial port, connected to the specified transmit and receive pins, with the specified baud.
+ *
+ * @param tx Transmit pin
+ * @param rx Receive pin
+ * @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE)
+ *
+ * @note
+ * Either tx or rx may be specified as NC if unused
+ */
+ RawSerial(PinName tx, PinName rx, int baud = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
+
+ /** Write a char to the serial port
+ *
+ * @param c The char to write
+ *
+ * @returns The written char or -1 if an error occured
+ */
+ int putc(int c);
+
+ /** Read a char from the serial port
+ *
+ * @returns The char read from the serial port
+ */
+ int getc();
+
+ /** Write a string to the serial port
+ *
+ * @param str The string to write
+ *
+ * @returns 0 if the write succeeds, EOF for error
+ */
+ int puts(const char *str);
+
+ int printf(const char *format, ...);
+
+protected:
+
+ /* Acquire exclusive access to this serial port
+ */
+ virtual void lock(void);
+
+ /* Release exclusive access to this serial port
+ */
+ virtual void unlock(void);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/SPI.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,214 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/SPI.h"
+#include "platform/mbed_critical.h"
+
+#if DEVICE_SPI
+
+namespace mbed {
+
+#if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
+CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
+#endif
+
+SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
+ _spi(),
+#if DEVICE_SPI_ASYNCH
+ _irq(this),
+ _usage(DMA_USAGE_NEVER),
+#endif
+ _bits(8),
+ _mode(0),
+ _hz(1000000) {
+ // No lock needed in the constructor
+
+ spi_init(&_spi, mosi, miso, sclk, ssel);
+ aquire();
+}
+
+void SPI::format(int bits, int mode) {
+ lock();
+ _bits = bits;
+ _mode = mode;
+ SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+ aquire();
+ unlock();
+}
+
+void SPI::frequency(int hz) {
+ lock();
+ _hz = hz;
+ SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+ aquire();
+ unlock();
+}
+
+SPI* SPI::_owner = NULL;
+SingletonPtr<PlatformMutex> SPI::_mutex;
+
+// ignore the fact there are multiple physical spis, and always update if it wasnt us last
+void SPI::aquire() {
+ lock();
+ if (_owner != this) {
+ spi_format(&_spi, _bits, _mode, 0);
+ spi_frequency(&_spi, _hz);
+ _owner = this;
+ }
+ unlock();
+}
+
+int SPI::write(int value) {
+ lock();
+ aquire();
+ int ret = spi_master_write(&_spi, value);
+ unlock();
+ return ret;
+}
+
+int SPI::write(const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+ lock();
+ aquire();
+ int ret = spi_master_block_write(&_spi, tx_buffer, tx_length, rx_buffer, rx_length);
+ unlock();
+ return ret;
+}
+
+void SPI::lock() {
+ _mutex->lock();
+}
+
+void SPI::unlock() {
+ _mutex->unlock();
+}
+
+#if DEVICE_SPI_ASYNCH
+
+int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
+{
+ if (spi_active(&_spi)) {
+ return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
+ }
+ start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
+ return 0;
+}
+
+void SPI::abort_transfer()
+{
+ spi_abort_asynch(&_spi);
+#if TRANSACTION_QUEUE_SIZE_SPI
+ dequeue_transaction();
+#endif
+}
+
+
+void SPI::clear_transfer_buffer()
+{
+#if TRANSACTION_QUEUE_SIZE_SPI
+ _transaction_buffer.reset();
+#endif
+}
+
+void SPI::abort_all_transfers()
+{
+ clear_transfer_buffer();
+ abort_transfer();
+}
+
+int SPI::set_dma_usage(DMAUsage usage)
+{
+ if (spi_active(&_spi)) {
+ return -1;
+ }
+ _usage = usage;
+ return 0;
+}
+
+int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
+{
+#if TRANSACTION_QUEUE_SIZE_SPI
+ transaction_t t;
+
+ t.tx_buffer = const_cast<void *>(tx_buffer);
+ t.tx_length = tx_length;
+ t.rx_buffer = rx_buffer;
+ t.rx_length = rx_length;
+ t.event = event;
+ t.callback = callback;
+ t.width = bit_width;
+ Transaction<SPI> transaction(this, t);
+ if (_transaction_buffer.full()) {
+ return -1; // the buffer is full
+ } else {
+ core_util_critical_section_enter();
+ _transaction_buffer.push(transaction);
+ if (!spi_active(&_spi)) {
+ dequeue_transaction();
+ }
+ core_util_critical_section_exit();
+ return 0;
+ }
+#else
+ return -1;
+#endif
+}
+
+void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
+{
+ aquire();
+ _callback = callback;
+ _irq.callback(&SPI::irq_handler_asynch);
+ spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
+}
+
+#if TRANSACTION_QUEUE_SIZE_SPI
+
+void SPI::start_transaction(transaction_t *data)
+{
+ start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
+}
+
+void SPI::dequeue_transaction()
+{
+ Transaction<SPI> t;
+ if (_transaction_buffer.pop(t)) {
+ SPI* obj = t.get_object();
+ transaction_t* data = t.get_transaction();
+ obj->start_transaction(data);
+ }
+}
+
+#endif
+
+void SPI::irq_handler_asynch(void)
+{
+ int event = spi_irq_handler_asynch(&_spi);
+ if (_callback && (event & SPI_EVENT_ALL)) {
+ _callback.call(event & SPI_EVENT_ALL);
+ }
+#if TRANSACTION_QUEUE_SIZE_SPI
+ if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
+ // SPI peripheral is free (event happend), dequeue transaction
+ dequeue_transaction();
+ }
+#endif
+}
+
+#endif
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/SPI.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,280 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_H
+#define MBED_SPI_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SPI) || defined(DOXYGEN_ONLY)
+
+#include "platform/PlatformMutex.h"
+#include "hal/spi_api.h"
+#include "platform/SingletonPtr.h"
+
+#if DEVICE_SPI_ASYNCH
+#include "platform/CThunk.h"
+#include "hal/dma_api.h"
+#include "platform/CircularBuffer.h"
+#include "platform/FunctionPointer.h"
+#include "platform/Transaction.h"
+#endif
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A SPI Master, used for communicating with SPI slave devices
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Most SPI devices will also require Chip Select and Reset signals. These
+ * can be controlled using DigitalOut pins
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Send a byte to a SPI slave, and record the response
+ *
+ * #include "mbed.h"
+ *
+ * // hardware ssel (where applicable)
+ * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * // software ssel
+ * SPI device(p5, p6, p7); // mosi, miso, sclk
+ * DigitalOut cs(p8); // ssel
+ *
+ * int main() {
+ * // hardware ssel (where applicable)
+ * //int response = device.write(0xFF);
+ *
+ * device.lock();
+ * // software ssel
+ * cs = 0;
+ * int response = device.write(0xFF);
+ * cs = 1;
+ * device.unlock();
+ *
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class SPI {
+
+public:
+
+ /** Create a SPI master connected to the specified pins
+ *
+ * mosi or miso can be specfied as NC if not used
+ *
+ * @param mosi SPI Master Out, Slave In pin
+ * @param miso SPI Master In, Slave Out pin
+ * @param sclk SPI Clock pin
+ * @param ssel SPI chip select pin
+ */
+ SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
+
+ /** Configure the data transmission format
+ *
+ * @param bits Number of bits per SPI frame (4 - 16)
+ * @param mode Clock polarity and phase mode (0 - 3)
+ *
+ * @code
+ * mode | POL PHA
+ * -----+--------
+ * 0 | 0 0
+ * 1 | 0 1
+ * 2 | 1 0
+ * 3 | 1 1
+ * @endcode
+ */
+ void format(int bits, int mode = 0);
+
+ /** Set the spi bus clock frequency
+ *
+ * @param hz SCLK frequency in hz (default = 1MHz)
+ */
+ void frequency(int hz = 1000000);
+
+ /** Write to the SPI Slave and return the response
+ *
+ * @param value Data to be sent to the SPI slave
+ *
+ * @returns
+ * Response from the SPI slave
+ */
+ virtual int write(int value);
+
+ /** Write to the SPI Slave and obtain the response
+ *
+ * The total number of bytes sent and recieved will be the maximum of
+ * tx_length and rx_length. The bytes written will be padded with the
+ * value 0xff.
+ *
+ * @param tx_buffer Pointer to the byte-array of data to write to the device
+ * @param tx_length Number of bytes to write, may be zero
+ * @param rx_buffer Pointer to the byte-array of data to read from the device
+ * @param rx_length Number of bytes to read, may be zero
+ * @returns
+ * The number of bytes written and read from the device. This is
+ * maximum of tx_length and rx_length.
+ */
+ virtual int write(const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length);
+
+ /** Acquire exclusive access to this SPI bus
+ */
+ virtual void lock(void);
+
+ /** Release exclusive access to this SPI bus
+ */
+ virtual void unlock(void);
+
+#if DEVICE_SPI_ASYNCH
+
+ /** Start non-blocking SPI transfer using 8bit buffers.
+ *
+ * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+ * the default SPI value is sent
+ * @param tx_length The length of TX buffer in bytes
+ * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+ * received data are ignored
+ * @param rx_length The length of RX buffer in bytes
+ * @param callback The event callback function
+ * @param event The logical OR of events to modify. Look at spi hal header file for SPI events.
+ * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
+ */
+ template<typename Type>
+ int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {
+ if (spi_active(&_spi)) {
+ return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
+ }
+ start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
+ return 0;
+ }
+
+ /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
+ */
+ void abort_transfer();
+
+ /** Clear the transaction buffer
+ */
+ void clear_transfer_buffer();
+
+ /** Clear the transaction buffer and abort on-going transfer.
+ */
+ void abort_all_transfers();
+
+ /** Configure DMA usage suggestion for non-blocking transfers
+ *
+ * @param usage The usage DMA hint for peripheral
+ * @return Zero if the usage was set, -1 if a transaction is on-going
+ */
+ int set_dma_usage(DMAUsage usage);
+
+protected:
+ /** SPI IRQ handler
+ *
+ */
+ void irq_handler_asynch(void);
+
+ /** Common transfer method
+ *
+ * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+ * the default SPI value is sent
+ * @param tx_length The length of TX buffer in bytes
+ * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+ * received data are ignored
+ * @param rx_length The length of RX buffer in bytes
+ * @param bit_width The buffers element width
+ * @param callback The event callback function
+ * @param event The logical OR of events to modify
+ * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
+ */
+ int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
+
+ /**
+ *
+ * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+ * the default SPI value is sent
+ * @param tx_length The length of TX buffer in bytes
+ * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+ * received data are ignored
+ * @param rx_length The length of RX buffer in bytes
+ * @param bit_width The buffers element width
+ * @param callback The event callback function
+ * @param event The logical OR of events to modify
+ * @return Zero if a transfer was added to the queue, or -1 if the queue is full
+ */
+ int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
+
+ /** Configures a callback, spi peripheral and initiate a new transfer
+ *
+ * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+ * the default SPI value is sent
+ * @param tx_length The length of TX buffer in bytes
+ * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+ * received data are ignored
+ * @param rx_length The length of RX buffer in bytes
+ * @param bit_width The buffers element width
+ * @param callback The event callback function
+ * @param event The logical OR of events to modify
+ */
+ void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
+
+#if TRANSACTION_QUEUE_SIZE_SPI
+
+ /** Start a new transaction
+ *
+ * @param data Transaction data
+ */
+ void start_transaction(transaction_t *data);
+
+ /** Dequeue a transaction
+ *
+ */
+ void dequeue_transaction();
+ static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
+#endif
+
+#endif
+
+public:
+ virtual ~SPI() {
+ }
+
+protected:
+ spi_t _spi;
+
+#if DEVICE_SPI_ASYNCH
+ CThunk<SPI> _irq;
+ event_callback_t _callback;
+ DMAUsage _usage;
+#endif
+
+ void aquire(void);
+ static SPI *_owner;
+ static SingletonPtr<PlatformMutex> _mutex;
+ int _bits;
+ int _mode;
+ int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/SPISlave.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/SPISlave.h"
+
+#if DEVICE_SPISLAVE
+
+namespace mbed {
+
+SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
+ _spi(),
+ _bits(8),
+ _mode(0),
+ _hz(1000000)
+ {
+ spi_init(&_spi, mosi, miso, sclk, ssel);
+ spi_format(&_spi, _bits, _mode, 1);
+ spi_frequency(&_spi, _hz);
+}
+
+void SPISlave::format(int bits, int mode) {
+ _bits = bits;
+ _mode = mode;
+ spi_format(&_spi, _bits, _mode, 1);
+}
+
+void SPISlave::frequency(int hz) {
+ _hz = hz;
+ spi_frequency(&_spi, _hz);
+}
+
+int SPISlave::receive(void) {
+ return(spi_slave_receive(&_spi));
+}
+
+int SPISlave::read(void) {
+ return(spi_slave_read(&_spi));
+}
+
+void SPISlave::reply(int value) {
+ spi_slave_write(&_spi, value);
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/SPISlave.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPISLAVE_H
+#define MBED_SPISLAVE_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SPISLAVE) || defined(DOXYGEN_ONLY)
+
+#include "hal/spi_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A SPI slave, used for communicating with a SPI Master device
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Reply to a SPI master as slave
+ *
+ * #include "mbed.h"
+ *
+ * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * int main() {
+ * device.reply(0x00); // Prime SPI with first reply
+ * while(1) {
+ * if(device.receive()) {
+ * int v = device.read(); // Read byte from master
+ * v = (v + 1) % 0x100; // Add one to it, modulo 256
+ * device.reply(v); // Make this the next reply
+ * }
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class SPISlave {
+
+public:
+
+ /** Create a SPI slave connected to the specified pins
+ *
+ * mosi or miso can be specfied as NC if not used
+ *
+ * @param mosi SPI Master Out, Slave In pin
+ * @param miso SPI Master In, Slave Out pin
+ * @param sclk SPI Clock pin
+ * @param ssel SPI chip select pin
+ */
+ SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+ /** Configure the data transmission format
+ *
+ * @param bits Number of bits per SPI frame (4 - 16)
+ * @param mode Clock polarity and phase mode (0 - 3)
+ *
+ * @code
+ * mode | POL PHA
+ * -----+--------
+ * 0 | 0 0
+ * 1 | 0 1
+ * 2 | 1 0
+ * 3 | 1 1
+ * @endcode
+ */
+ void format(int bits, int mode = 0);
+
+ /** Set the spi bus clock frequency
+ *
+ * @param hz SCLK frequency in hz (default = 1MHz)
+ */
+ void frequency(int hz = 1000000);
+
+ /** Polls the SPI to see if data has been received
+ *
+ * @returns
+ * 0 if no data,
+ * 1 otherwise
+ */
+ int receive(void);
+
+ /** Retrieve data from receive buffer as slave
+ *
+ * @returns
+ * the data in the receive buffer
+ */
+ int read(void);
+
+ /** Fill the transmission buffer with the value to be written out
+ * as slave on the next received message from the master.
+ *
+ * @param value the data to be transmitted next
+ */
+ void reply(int value);
+
+protected:
+ spi_t _spi;
+
+ int _bits;
+ int _mode;
+ int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/Serial.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,50 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Serial.h"
+#include "platform/mbed_wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+Serial::Serial(PinName tx, PinName rx, const char *name, int baud) : SerialBase(tx, rx, baud), Stream(name) {
+}
+
+Serial::Serial(PinName tx, PinName rx, int baud): SerialBase(tx, rx, baud), Stream(NULL) {
+}
+
+int Serial::_getc() {
+ // Mutex is already held
+ return _base_getc();
+}
+
+int Serial::_putc(int c) {
+ // Mutex is already held
+ return _base_putc(c);
+}
+
+void Serial::lock() {
+ _mutex.lock();
+}
+
+void Serial::unlock() {
+ _mutex.unlock();
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/Serial.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_H
+#define MBED_SERIAL_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY)
+
+#include "Stream.h"
+#include "SerialBase.h"
+#include "PlatformMutex.h"
+#include "serial_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A serial port (UART) for communication with other serial devices
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Print "Hello World" to the PC
+ *
+ * #include "mbed.h"
+ *
+ * Serial pc(USBTX, USBRX);
+ *
+ * int main() {
+ * pc.printf("Hello World\n");
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Serial : public SerialBase, public Stream {
+
+public:
+#if DEVICE_SERIAL_ASYNCH
+ using SerialBase::read;
+ using SerialBase::write;
+#endif
+
+ /** Create a Serial port, connected to the specified transmit and receive pins
+ *
+ * @param tx Transmit pin
+ * @param rx Receive pin
+ * @param name The name of the stream associated with this serial port (optional)
+ * @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE)
+ *
+ * @note
+ * Either tx or rx may be specified as NC if unused
+ */
+ Serial(PinName tx, PinName rx, const char *name=NULL, int baud = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
+
+
+ /** Create a Serial port, connected to the specified transmit and receive pins, with the specified baud
+ *
+ * @param tx Transmit pin
+ * @param rx Receive pin
+ * @param baud The baud rate of the serial port
+ *
+ * @note
+ * Either tx or rx may be specified as NC if unused
+ */
+ Serial(PinName tx, PinName rx, int baud);
+
+ /* Stream gives us a FileHandle with non-functional poll()/readable()/writable. Pass through
+ * the calls from the SerialBase instead for backwards compatibility. This problem is
+ * part of why Stream and Serial should be deprecated.
+ */
+ bool readable()
+ {
+ return SerialBase::readable();
+ }
+ bool writable()
+ {
+ return SerialBase::writeable();
+ }
+ bool writeable()
+ {
+ return SerialBase::writeable();
+ }
+
+protected:
+ virtual int _getc();
+ virtual int _putc(int c);
+ virtual void lock();
+ virtual void unlock();
+
+ PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/SerialBase.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,253 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/SerialBase.h"
+#include "platform/mbed_wait_api.h"
+#include "platform/mbed_critical.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+static void donothing() {};
+
+SerialBase::SerialBase(PinName tx, PinName rx, int baud) :
+#if DEVICE_SERIAL_ASYNCH
+ _thunk_irq(this), _tx_usage(DMA_USAGE_NEVER),
+ _rx_usage(DMA_USAGE_NEVER),
+#endif
+ _serial(), _baud(baud) {
+ // No lock needed in the constructor
+
+ for (size_t i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
+ _irq[i] = donothing;
+ }
+
+ serial_init(&_serial, tx, rx);
+ serial_baud(&_serial, _baud);
+ serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this);
+}
+
+void SerialBase::baud(int baudrate) {
+ lock();
+ serial_baud(&_serial, baudrate);
+ _baud = baudrate;
+ unlock();
+}
+
+void SerialBase::format(int bits, Parity parity, int stop_bits) {
+ lock();
+ serial_format(&_serial, bits, (SerialParity)parity, stop_bits);
+ unlock();
+}
+
+int SerialBase::readable() {
+ lock();
+ int ret = serial_readable(&_serial);
+ unlock();
+ return ret;
+}
+
+
+int SerialBase::writeable() {
+ lock();
+ int ret = serial_writable(&_serial);
+ unlock();
+ return ret;
+}
+
+void SerialBase::attach(Callback<void()> func, IrqType type) {
+ lock();
+ // Disable interrupts when attaching interrupt handler
+ core_util_critical_section_enter();
+ if (func) {
+ _irq[type] = func;
+ serial_irq_set(&_serial, (SerialIrq)type, 1);
+ } else {
+ _irq[type] = donothing;
+ serial_irq_set(&_serial, (SerialIrq)type, 0);
+ }
+ core_util_critical_section_exit();
+ unlock();
+}
+
+void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) {
+ SerialBase *handler = (SerialBase*)id;
+ handler->_irq[irq_type]();
+}
+
+int SerialBase::_base_getc() {
+ // Mutex is already held
+ return serial_getc(&_serial);
+}
+
+int SerialBase::_base_putc(int c) {
+ // Mutex is already held
+ serial_putc(&_serial, c);
+ return c;
+}
+
+void SerialBase::send_break() {
+ lock();
+ // Wait for 1.5 frames before clearing the break condition
+ // This will have different effects on our platforms, but should
+ // ensure that we keep the break active for at least one frame.
+ // We consider a full frame (1 start bit + 8 data bits bits +
+ // 1 parity bit + 2 stop bits = 12 bits) for computation.
+ // One bit time (in us) = 1000000/_baud
+ // Twelve bits: 12000000/baud delay
+ // 1.5 frames: 18000000/baud delay
+ serial_break_set(&_serial);
+ wait_us(18000000/_baud);
+ serial_break_clear(&_serial);
+ unlock();
+}
+
+void SerialBase::lock() {
+ // Stub
+}
+
+void SerialBase:: unlock() {
+ // Stub
+}
+
+#if DEVICE_SERIAL_FC
+void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
+ lock();
+ FlowControl flow_type = (FlowControl)type;
+ switch(type) {
+ case RTS:
+ serial_set_flow_control(&_serial, flow_type, flow1, NC);
+ break;
+
+ case CTS:
+ serial_set_flow_control(&_serial, flow_type, NC, flow1);
+ break;
+
+ case RTSCTS:
+ case Disabled:
+ serial_set_flow_control(&_serial, flow_type, flow1, flow2);
+ break;
+
+ default:
+ break;
+ }
+ unlock();
+}
+#endif
+
+#if DEVICE_SERIAL_ASYNCH
+
+int SerialBase::write(const uint8_t *buffer, int length, const event_callback_t& callback, int event)
+{
+ if (serial_tx_active(&_serial)) {
+ return -1; // transaction ongoing
+ }
+ start_write((void *)buffer, length, 8, callback, event);
+ return 0;
+}
+
+int SerialBase::write(const uint16_t *buffer, int length, const event_callback_t& callback, int event)
+{
+ if (serial_tx_active(&_serial)) {
+ return -1; // transaction ongoing
+ }
+ start_write((void *)buffer, length, 16, callback, event);
+ return 0;
+}
+
+void SerialBase::start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event)
+{
+ _tx_callback = callback;
+
+ _thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
+ serial_tx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, _tx_usage);
+}
+
+void SerialBase::abort_write(void)
+{
+ serial_tx_abort_asynch(&_serial);
+}
+
+void SerialBase::abort_read(void)
+{
+ serial_rx_abort_asynch(&_serial);
+}
+
+int SerialBase::set_dma_usage_tx(DMAUsage usage)
+{
+ if (serial_tx_active(&_serial)) {
+ return -1;
+ }
+ _tx_usage = usage;
+ return 0;
+}
+
+int SerialBase::set_dma_usage_rx(DMAUsage usage)
+{
+ if (serial_tx_active(&_serial)) {
+ return -1;
+ }
+ _rx_usage = usage;
+ return 0;
+}
+
+int SerialBase::read(uint8_t *buffer, int length, const event_callback_t& callback, int event, unsigned char char_match)
+{
+ if (serial_rx_active(&_serial)) {
+ return -1; // transaction ongoing
+ }
+ start_read((void*)buffer, length, 8, callback, event, char_match);
+ return 0;
+}
+
+
+int SerialBase::read(uint16_t *buffer, int length, const event_callback_t& callback, int event, unsigned char char_match)
+{
+ if (serial_rx_active(&_serial)) {
+ return -1; // transaction ongoing
+ }
+ start_read((void*)buffer, length, 16, callback, event, char_match);
+ return 0;
+}
+
+
+void SerialBase::start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match)
+{
+ _rx_callback = callback;
+ _thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
+ serial_rx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, char_match, _rx_usage);
+}
+
+void SerialBase::interrupt_handler_asynch(void)
+{
+ int event = serial_irq_handler_asynch(&_serial);
+ int rx_event = event & SERIAL_EVENT_RX_MASK;
+ if (_rx_callback && rx_event) {
+ _rx_callback.call(rx_event);
+ }
+
+ int tx_event = event & SERIAL_EVENT_TX_MASK;
+ if (_tx_callback && tx_event) {
+ _tx_callback.call(tx_event);
+ }
+}
+
+#endif
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/SerialBase.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,260 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIALBASE_H
+#define MBED_SERIALBASE_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY)
+
+#include "Callback.h"
+#include "serial_api.h"
+#include "mbed_toolchain.h"
+
+#if DEVICE_SERIAL_ASYNCH
+#include "CThunk.h"
+#include "dma_api.h"
+#endif
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A base class for serial port implementations
+ * Can't be instantiated directly (use Serial or RawSerial)
+ *
+ * @note Synchronization level: Set by subclass
+ * @ingroup drivers
+ */
+class SerialBase {
+
+public:
+ /** Set the baud rate of the serial port
+ *
+ * @param baudrate The baudrate of the serial port (default = 9600).
+ */
+ void baud(int baudrate);
+
+ enum Parity {
+ None = 0,
+ Odd,
+ Even,
+ Forced1,
+ Forced0
+ };
+
+ enum IrqType {
+ RxIrq = 0,
+ TxIrq,
+
+ IrqCnt
+ };
+
+ enum Flow {
+ Disabled = 0,
+ RTS,
+ CTS,
+ RTSCTS
+ };
+
+ /** Set the transmission format used by the serial port
+ *
+ * @param bits The number of bits in a word (5-8; default = 8)
+ * @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
+ * @param stop_bits The number of stop bits (1 or 2; default = 1)
+ */
+ void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1);
+
+ /** Determine if there is a character available to read
+ *
+ * @returns
+ * 1 if there is a character available to read,
+ * 0 otherwise
+ */
+ int readable();
+
+ /** Determine if there is space available to write a character
+ *
+ * @returns
+ * 1 if there is space to write a character,
+ * 0 otherwise
+ */
+ int writeable();
+
+ /** Attach a function to call whenever a serial interrupt is generated
+ *
+ * @param func A pointer to a void function, or 0 to set as none
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ */
+ void attach(Callback<void()> func, IrqType type=RxIrq);
+
+ /** Attach a member function to call whenever a serial interrupt is generated
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ * @deprecated
+ * The attach function does not support cv-qualifiers. Replaced by
+ * attach(callback(obj, method), type).
+ */
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The attach function does not support cv-qualifiers. Replaced by "
+ "attach(callback(obj, method), type).")
+ void attach(T *obj, void (T::*method)(), IrqType type=RxIrq) {
+ attach(callback(obj, method), type);
+ }
+
+ /** Attach a member function to call whenever a serial interrupt is generated
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ * @deprecated
+ * The attach function does not support cv-qualifiers. Replaced by
+ * attach(callback(obj, method), type).
+ */
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The attach function does not support cv-qualifiers. Replaced by "
+ "attach(callback(obj, method), type).")
+ void attach(T *obj, void (*method)(T*), IrqType type=RxIrq) {
+ attach(callback(obj, method), type);
+ }
+
+ /** Generate a break condition on the serial line
+ */
+ void send_break();
+
+protected:
+
+ /** Acquire exclusive access to this serial port
+ */
+ virtual void lock(void);
+
+ /** Release exclusive access to this serial port
+ */
+ virtual void unlock(void);
+
+public:
+
+#if DEVICE_SERIAL_FC
+ /** Set the flow control type on the serial port
+ *
+ * @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
+ * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
+ * @param flow2 the second flow control pin (CTS for RTSCTS)
+ */
+ void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
+#endif
+
+ static void _irq_handler(uint32_t id, SerialIrq irq_type);
+
+#if DEVICE_SERIAL_ASYNCH
+
+ /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback
+ *
+ * @param buffer The buffer where received data will be stored
+ * @param length The buffer length in bytes
+ * @param callback The event callback function
+ * @param event The logical OR of TX events
+ */
+ int write(const uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
+
+ /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback
+ *
+ * @param buffer The buffer where received data will be stored
+ * @param length The buffer length in bytes
+ * @param callback The event callback function
+ * @param event The logical OR of TX events
+ */
+ int write(const uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
+
+ /** Abort the on-going write transfer
+ */
+ void abort_write();
+
+ /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback.
+ *
+ * @param buffer The buffer where received data will be stored
+ * @param length The buffer length in bytes
+ * @param callback The event callback function
+ * @param event The logical OR of RX events
+ * @param char_match The matching character
+ */
+ int read(uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
+
+ /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback.
+ *
+ * @param buffer The buffer where received data will be stored
+ * @param length The buffer length in bytes
+ * @param callback The event callback function
+ * @param event The logical OR of RX events
+ * @param char_match The matching character
+ */
+ int read(uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
+
+ /** Abort the on-going read transfer
+ */
+ void abort_read();
+
+ /** Configure DMA usage suggestion for non-blocking TX transfers
+ *
+ * @param usage The usage DMA hint for peripheral
+ * @return Zero if the usage was set, -1 if a transaction is on-going
+ */
+ int set_dma_usage_tx(DMAUsage usage);
+
+ /** Configure DMA usage suggestion for non-blocking RX transfers
+ *
+ * @param usage The usage DMA hint for peripheral
+ * @return Zero if the usage was set, -1 if a transaction is on-going
+ */
+ int set_dma_usage_rx(DMAUsage usage);
+
+protected:
+ void start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match);
+ void start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event);
+ void interrupt_handler_asynch(void);
+#endif
+
+protected:
+ SerialBase(PinName tx, PinName rx, int baud);
+ virtual ~SerialBase() {
+ }
+
+ int _base_getc();
+ int _base_putc(int c);
+
+#if DEVICE_SERIAL_ASYNCH
+ CThunk<SerialBase> _thunk_irq;
+ event_callback_t _tx_callback;
+ event_callback_t _rx_callback;
+ DMAUsage _tx_usage;
+ DMAUsage _rx_usage;
+#endif
+
+ serial_t _serial;
+ Callback<void()> _irq[IrqCnt];
+ int _baud;
+
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/Ticker.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Ticker.h"
+
+#include "drivers/TimerEvent.h"
+#include "platform/FunctionPointer.h"
+#include "hal/ticker_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+void Ticker::detach() {
+ core_util_critical_section_enter();
+ remove();
+ _function = 0;
+ core_util_critical_section_exit();
+}
+
+void Ticker::setup(us_timestamp_t t) {
+ core_util_critical_section_enter();
+ remove();
+ _delay = t;
+ insert_absolute(_delay + ticker_read_us(_ticker_data));
+ core_util_critical_section_exit();
+}
+
+void Ticker::handler() {
+ insert_absolute(event.timestamp + _delay);
+ _function();
+}
+
+} // namespace mbed
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/Ticker.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,145 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_H
+#define MBED_TICKER_H
+
+#include "drivers/TimerEvent.h"
+#include "platform/Callback.h"
+#include "platform/mbed_toolchain.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A Ticker is used to call a function at a recurring interval
+ *
+ * You can use as many seperate Ticker objects as you require.
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Toggle the blinking led after 5 seconds
+ *
+ * #include "mbed.h"
+ *
+ * Ticker timer;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * int flip = 0;
+ *
+ * void attime() {
+ * flip = !flip;
+ * }
+ *
+ * int main() {
+ * timer.attach(&attime, 5);
+ * while(1) {
+ * if(flip == 0) {
+ * led1 = !led1;
+ * } else {
+ * led2 = !led2;
+ * }
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Ticker : public TimerEvent {
+
+public:
+ Ticker() : TimerEvent() {
+ }
+
+ Ticker(const ticker_data_t *data) : TimerEvent(data) {
+ data->interface->init();
+ }
+
+ /** Attach a function to be called by the Ticker, specifiying the interval in seconds
+ *
+ * @param func pointer to the function to be called
+ * @param t the time between calls in seconds
+ */
+ void attach(Callback<void()> func, float t) {
+ attach_us(func, t * 1000000.0f);
+ }
+
+ /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @param t the time between calls in seconds
+ * @deprecated
+ * The attach function does not support cv-qualifiers. Replaced by
+ * attach(callback(obj, method), t).
+ */
+ template<typename T, typename M>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The attach function does not support cv-qualifiers. Replaced by "
+ "attach(callback(obj, method), t).")
+ void attach(T *obj, M method, float t) {
+ attach(callback(obj, method), t);
+ }
+
+ /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
+ *
+ * @param func pointer to the function to be called
+ * @param t the time between calls in micro-seconds
+ */
+ void attach_us(Callback<void()> func, us_timestamp_t t) {
+ _function = func;
+ setup(t);
+ }
+
+ /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ * @param t the time between calls in micro-seconds
+ * @deprecated
+ * The attach_us function does not support cv-qualifiers. Replaced by
+ * attach_us(callback(obj, method), t).
+ */
+ template<typename T, typename M>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The attach_us function does not support cv-qualifiers. Replaced by "
+ "attach_us(callback(obj, method), t).")
+ void attach_us(T *obj, M method, us_timestamp_t t) {
+ attach_us(Callback<void()>(obj, method), t);
+ }
+
+ virtual ~Ticker() {
+ detach();
+ }
+
+ /** Detach the function
+ */
+ void detach();
+
+protected:
+ void setup(us_timestamp_t t);
+ virtual void handler();
+
+protected:
+ us_timestamp_t _delay; /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
+ Callback<void()> _function; /**< Callback. */
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/Timeout.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,25 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Timeout.h"
+
+namespace mbed {
+
+void Timeout::handler() {
+ _function.call();
+}
+
+} // namespace mbed
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/Timeout.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEOUT_H
+#define MBED_TIMEOUT_H
+
+#include "drivers/Ticker.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A Timeout is used to call a function at a point in the future
+ *
+ * You can use as many seperate Timeout objects as you require.
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Blink until timeout.
+ *
+ * #include "mbed.h"
+ *
+ * Timeout timeout;
+ * DigitalOut led(LED1);
+ *
+ * int on = 1;
+ *
+ * void attimeout() {
+ * on = 0;
+ * }
+ *
+ * int main() {
+ * timeout.attach(&attimeout, 5);
+ * while(on) {
+ * led = !led;
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Timeout : public Ticker {
+
+protected:
+ virtual void handler();
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/Timer.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,88 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/Timer.h"
+#include "hal/ticker_api.h"
+#include "hal/us_ticker_api.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+Timer::Timer() : _running(), _start(), _time(), _ticker_data(get_us_ticker_data()) {
+ reset();
+}
+
+Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker_data(data) {
+ reset();
+}
+
+void Timer::start() {
+ core_util_critical_section_enter();
+ if (!_running) {
+ _start = ticker_read_us(_ticker_data);
+ _running = 1;
+ }
+ core_util_critical_section_exit();
+}
+
+void Timer::stop() {
+ core_util_critical_section_enter();
+ _time += slicetime();
+ _running = 0;
+ core_util_critical_section_exit();
+}
+
+int Timer::read_us() {
+ return read_high_resolution_us();
+}
+
+float Timer::read() {
+ return (float)read_us() / 1000000.0f;
+}
+
+int Timer::read_ms() {
+ return read_high_resolution_us() / 1000;
+}
+
+us_timestamp_t Timer::read_high_resolution_us() {
+ core_util_critical_section_enter();
+ us_timestamp_t time = _time + slicetime();
+ core_util_critical_section_exit();
+ return time;
+}
+
+us_timestamp_t Timer::slicetime() {
+ us_timestamp_t ret = 0;
+ core_util_critical_section_enter();
+ if (_running) {
+ ret = ticker_read_us(_ticker_data) - _start;
+ }
+ core_util_critical_section_exit();
+ return ret;
+}
+
+void Timer::reset() {
+ core_util_critical_section_enter();
+ _start = ticker_read_us(_ticker_data);
+ _time = 0;
+ core_util_critical_section_exit();
+}
+
+Timer::operator float() {
+ return read();
+}
+
+} // namespace mbed
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/Timer.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,100 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMER_H
+#define MBED_TIMER_H
+
+#include "platform/platform.h"
+#include "hal/ticker_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** A general purpose timer
+ *
+ * @note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Count the time to toggle a LED
+ *
+ * #include "mbed.h"
+ *
+ * Timer timer;
+ * DigitalOut led(LED1);
+ * int begin, end;
+ *
+ * int main() {
+ * timer.start();
+ * begin = timer.read_us();
+ * led = !led;
+ * end = timer.read_us();
+ * printf("Toggle the led takes %d us", end - begin);
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class Timer {
+
+public:
+ Timer();
+ Timer(const ticker_data_t *data);
+
+ /** Start the timer
+ */
+ void start();
+
+ /** Stop the timer
+ */
+ void stop();
+
+ /** Reset the timer to 0.
+ *
+ * If it was already counting, it will continue
+ */
+ void reset();
+
+ /** Get the time passed in seconds
+ */
+ float read();
+
+ /** Get the time passed in mili-seconds
+ */
+ int read_ms();
+
+ /** Get the time passed in micro-seconds
+ */
+ int read_us();
+
+ /** An operator shorthand for read()
+ */
+ operator float();
+
+ /** Get in a high resolution type the time passed in micro-seconds.
+ */
+ us_timestamp_t read_high_resolution_us();
+
+protected:
+ us_timestamp_t slicetime();
+ int _running; // whether the timer is running
+ us_timestamp_t _start; // the start time of the latest slice
+ us_timestamp_t _time; // any accumulated time from previous slices
+ const ticker_data_t *_ticker_data;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/TimerEvent.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "drivers/TimerEvent.h"
+#include "cmsis.h"
+
+#include <stddef.h>
+#include "hal/ticker_api.h"
+#include "hal/us_ticker_api.h"
+
+namespace mbed {
+
+TimerEvent::TimerEvent() : event(), _ticker_data(get_us_ticker_data()) {
+ ticker_set_handler(_ticker_data, (&TimerEvent::irq));
+}
+
+TimerEvent::TimerEvent(const ticker_data_t *data) : event(), _ticker_data(data) {
+ ticker_set_handler(_ticker_data, (&TimerEvent::irq));
+}
+
+void TimerEvent::irq(uint32_t id) {
+ TimerEvent *timer_event = (TimerEvent*)id;
+ timer_event->handler();
+}
+
+TimerEvent::~TimerEvent() {
+ remove();
+}
+
+// insert in to linked list
+void TimerEvent::insert(timestamp_t timestamp) {
+ ticker_insert_event(_ticker_data, &event, timestamp, (uint32_t)this);
+}
+
+void TimerEvent::insert_absolute(us_timestamp_t timestamp) {
+ ticker_insert_event_us(_ticker_data, &event, timestamp, (uint32_t)this);
+}
+
+void TimerEvent::remove() {
+ ticker_remove_event(_ticker_data, &event);
+}
+
+} // namespace mbed
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/TimerEvent.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEREVENT_H
+#define MBED_TIMEREVENT_H
+
+#include "hal/ticker_api.h"
+#include "hal/us_ticker_api.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+
+/** Base abstraction for timer interrupts
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup drivers
+ */
+class TimerEvent {
+public:
+ TimerEvent();
+ TimerEvent(const ticker_data_t *data);
+
+ /** The handler registered with the underlying timer interrupt
+ */
+ static void irq(uint32_t id);
+
+ /** Destruction removes it...
+ */
+ virtual ~TimerEvent();
+
+protected:
+ // The handler called to service the timer event of the derived class
+ virtual void handler() = 0;
+
+ // insert relative timestamp in to linked list
+ void insert(timestamp_t timestamp);
+
+ // insert absolute timestamp into linked list
+ void insert_absolute(us_timestamp_t timestamp);
+
+ // remove from linked list, if in it
+ void remove();
+
+ ticker_event_t event;
+
+ const ticker_data_t *_ticker_data;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,170 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "flash_data.h"
+#include "mbed_critical.h"
+
+#define MBED_FLASH_ALGO_ERASE 1UL
+#define MBED_FLASH_ALGO_PROGRAM 2UL
+
+extern uint32_t SystemCoreClock;
+
+/*
+ This binary blob (thumb code) sets r9 (static base) as the code we are jumping to
+ is PIC (position independent code).
+
+ These are the instructions (r0 is a pointer to arg_t):
+ push {r5, lr, r4}
+ mov r5, r9
+ push {r5}
+ ldr r5, [r0, #20]
+ ldr r3, [r0, #16]
+ mov r9, r3
+ ldr r3, [r0, #12]
+ ldr r2, [r0, #8]
+ ldr r1, [r0, #4]
+ ldr r0, [r0, #0]
+ blx r5
+ pop {r5}
+ mov r9, r5
+ pop {r4-r5, pc}
+ bx r14
+*/
+static uint32_t jump_to_flash_algo[] = {
+ 0x464DB530,
+ 0x6945B420,
+ 0x46996903,
+ 0x688268C3,
+ 0x68006841,
+ 0xBC2047A8,
+ 0xBD3046A9
+};
+
+// should be called within critical section
+static int32_t flash_algo_init(flash_t *obj, uint32_t address, uint32_t function)
+{
+ args_t arguments = {
+ .r0 = address,
+ .r1 = SystemCoreClock,
+ .r2 = function,
+ .r3 = 0,
+ .r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
+ .pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->init
+ };
+ return ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
+}
+
+// should be called within critical section
+static int32_t flash_algo_uninit(flash_t *obj, uint32_t address, uint32_t function)
+{
+ args_t arguments = {
+ .r0 = address,
+ .r1 = SystemCoreClock,
+ .r2 = function,
+ .r3 = 0,
+ .r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
+ .pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->uninit
+ };
+ return ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
+}
+
+
+int32_t flash_init(flash_t *obj)
+{
+ flash_set_target_config(obj);
+ return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+ return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+ core_util_critical_section_enter();
+ flash_algo_init(obj, address, MBED_FLASH_ALGO_ERASE);
+
+ args_t arguments = {
+ .r0 = address,
+ .r1 = 0,
+ .r2 = 0,
+ .r3 = 0,
+ .r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
+ .pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->erase_sector
+ };
+ int32_t ret = ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
+
+ flash_algo_uninit(obj, address, MBED_FLASH_ALGO_ERASE);
+ core_util_critical_section_exit();
+ return ret ? -1 : 0;
+}
+
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+ core_util_critical_section_enter();
+ flash_algo_init(obj, address, MBED_FLASH_ALGO_PROGRAM);
+
+ args_t arguments = {
+ .r0 = address,
+ .r1 = size,
+ .r2 = (uint32_t)data,
+ .r3 = 0,
+ .r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
+ .pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->program_page
+ };
+ int32_t ret = ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
+
+ flash_algo_uninit(obj, address, MBED_FLASH_ALGO_PROGRAM);
+ core_util_critical_section_exit();
+ return ret ? -1 : 0;
+}
+
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+ const sector_info_t *sectors = obj->target_config->sectors;
+
+ if (address >= obj->target_config->flash_start + obj->target_config->flash_size) {
+ return MBED_FLASH_INVALID_SIZE;
+ }
+
+ int sector_index = obj->target_config->sector_info_count - 1;
+ for (; sector_index >= 0; sector_index--) {
+ if (address >= sectors[sector_index].start) {
+ return sectors[sector_index].size;
+ }
+ }
+ return MBED_FLASH_INVALID_SIZE;
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+ return obj->target_config->page_size;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+ return obj->target_config->flash_start;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+ return obj->target_config->flash_size;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/TARGET_FLASH_CMSIS_ALGO/flash_data.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,84 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FLASH_DATA_H
+#define MBED_FLASH_DATA_H
+
+#include <stdint.h>
+
+// Target flash algorithm structure
+typedef struct {
+ const uint32_t init;
+ const uint32_t uninit;
+ const uint32_t erase_sector;
+ const uint32_t program_page;
+ const uint32_t static_base;
+ uint32_t *algo_blob;
+} flash_algo_t;
+
+typedef struct {
+ const uint32_t start;
+ const uint32_t size;
+} sector_info_t;
+
+typedef struct {
+ const uint32_t page_size;
+ const uint32_t flash_start;
+ const uint32_t flash_size;
+ const sector_info_t *sectors;
+ const uint32_t sector_info_count;
+} flash_target_config_t;
+
+// Target flash configuration
+struct flash_s {
+ const flash_target_config_t *target_config;
+ const flash_algo_t *flash_algo;
+};
+
+typedef struct {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r9;
+ uint32_t pc;
+} args_t;
+
+typedef int32_t (*flash_algo_jump_t)(args_t*);
+
+// prototypes for flash algo CMSIS API
+
+typedef int (*CMSIS_Algo_Function_Init)(unsigned long adr, unsigned long clk, unsigned long fnc);
+typedef int (*CMSIS_Algo_Function_UnInit)(unsigned long fnc);
+typedef int (*CMSIS_Algo_Function_EraseSector)(unsigned long adr);
+typedef int (*CMSIS_Algo_Function_EraseChip)(void);
+typedef int (*CMSIS_Algo_Function_ProgramPage)(unsigned long adr, unsigned long sz, unsigned char *buf);
+typedef unsigned long (*CMSIS_Algo_Function_Verify)(unsigned long adr, unsigned long sz, unsigned char *buf);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Set target configuration
+ */
+void flash_set_target_config(flash_t *obj);
+
+#ifdef __cplusplus
+};
+#endif
+
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/analogin_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,72 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_API_H
+#define MBED_ANALOGIN_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Analogin hal structure. analogin_s is declared in the target's hal
+ */
+typedef struct analogin_s analogin_t;
+
+/**
+ * \defgroup hal_analogin Analogin hal functions
+ * @{
+ */
+
+/** Initialize the analogin peripheral
+ *
+ * Configures the pin used by analogin.
+ * @param obj The analogin object to initialize
+ * @param pin The analogin pin name
+ */
+void analogin_init(analogin_t *obj, PinName pin);
+
+/** Read the input voltage, represented as a float in the range [0.0, 1.0]
+ *
+ * @param obj The analogin object
+ * @return A floating value representing the current input voltage
+ */
+float analogin_read(analogin_t *obj);
+
+/** Read the value from analogin pin, represented as an unsigned 16bit value
+ *
+ * @param obj The analogin object
+ * @return An unsigned 16bit value representing the current input voltage
+ */
+uint16_t analogin_read_u16(analogin_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/analogout_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,94 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_API_H
+#define MBED_ANALOGOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Analogout hal structure. dac_s is declared in the target's hal
+ */
+typedef struct dac_s dac_t;
+
+/**
+ * \defgroup hal_analogout Analogout hal functions
+ * @{
+ */
+
+/** Initialize the analogout peripheral
+ *
+ * Configures the pin used by analogout.
+ * @param obj The analogout object to initialize
+ * @param pin The analogout pin name
+ */
+void analogout_init(dac_t *obj, PinName pin);
+
+/** Release the analogout object
+ *
+ * Note: This is not currently used in the mbed-drivers
+ * @param obj The analogout object
+ */
+void analogout_free(dac_t *obj);
+
+/** Set the output voltage, specified as a percentage (float)
+ *
+ * @param obj The analogin object
+ * @param value The floating-point output voltage to be set
+ */
+void analogout_write(dac_t *obj, float value);
+
+/** Set the output voltage, specified as unsigned 16-bit
+ *
+ * @param obj The analogin object
+ * @param value The unsigned 16-bit output voltage to be set
+ */
+void analogout_write_u16(dac_t *obj, uint16_t value);
+
+/** Read the current voltage value on the pin
+ *
+ * @param obj The analogin object
+ * @return A floating-point value representing the current voltage on the pin,
+ * measured as a percentage
+ */
+float analogout_read(dac_t *obj);
+
+/** Read the current voltage value on the pin, as a normalized unsigned 16bit value
+ *
+ * @param obj The analogin object
+ * @return An unsigned 16-bit value representing the current voltage on the pin
+ */
+uint16_t analogout_read_u16(dac_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/buffer.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,36 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUFFER_H
+#define MBED_BUFFER_H
+
+#include <stddef.h>
+
+/** Generic buffer structure
+ */
+typedef struct buffer_s {
+ void *buffer; /**< the pointer to a buffer */
+ size_t length; /**< the buffer length */
+ size_t pos; /**< actual buffer position */
+ uint8_t width; /**< The buffer unit width (8, 16, 32, 64), used for proper *buffer casting */
+} buffer_t;
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/can_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,87 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_API_H
+#define MBED_CAN_API_H
+
+#include "device.h"
+
+#if DEVICE_CAN
+
+#include "PinNames.h"
+#include "PeripheralNames.h"
+#include "hal/can_helper.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ IRQ_RX,
+ IRQ_TX,
+ IRQ_ERROR,
+ IRQ_OVERRUN,
+ IRQ_WAKEUP,
+ IRQ_PASSIVE,
+ IRQ_ARB,
+ IRQ_BUS,
+ IRQ_READY
+} CanIrqType;
+
+
+typedef enum {
+ MODE_RESET,
+ MODE_NORMAL,
+ MODE_SILENT,
+ MODE_TEST_LOCAL,
+ MODE_TEST_GLOBAL,
+ MODE_TEST_SILENT
+} CanMode;
+
+typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
+
+typedef struct can_s can_t;
+
+void can_init (can_t *obj, PinName rd, PinName td);
+void can_init_freq (can_t *obj, PinName rd, PinName td, int hz);
+void can_free (can_t *obj);
+int can_frequency (can_t *obj, int hz);
+
+void can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
+void can_irq_free (can_t *obj);
+void can_irq_set (can_t *obj, CanIrqType irq, uint32_t enable);
+
+int can_write (can_t *obj, CAN_Message, int cc);
+int can_read (can_t *obj, CAN_Message *msg, int handle);
+int can_mode (can_t *obj, CanMode mode);
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);
+void can_reset (can_t *obj);
+unsigned char can_rderror (can_t *obj);
+unsigned char can_tderror (can_t *obj);
+void can_monitor (can_t *obj, int silent);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif // MBED_CAN_API_H
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/can_helper.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,59 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_HELPER_H
+#define MBED_CAN_HELPER_H
+
+#if DEVICE_CAN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum CANFormat {
+ CANStandard = 0,
+ CANExtended = 1,
+ CANAny = 2
+};
+typedef enum CANFormat CANFormat;
+
+enum CANType {
+ CANData = 0,
+ CANRemote = 1
+};
+typedef enum CANType CANType;
+
+struct CAN_Message {
+ unsigned int id; // 29 bit identifier
+ unsigned char data[8]; // Data field
+ unsigned char len; // Length of data field in bytes
+ CANFormat format; // 0 - STANDARD, 1- EXTENDED IDENTIFIER
+ CANType type; // 0 - DATA FRAME, 1 - REMOTE FRAME
+};
+typedef struct CAN_Message CAN_Message;
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+
+#endif // MBED_CAN_HELPER_H
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/dma_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,51 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DMA_API_H
+#define MBED_DMA_API_H
+
+#include <stdint.h>
+
+#define DMA_ERROR_OUT_OF_CHANNELS (-1)
+
+typedef enum {
+ DMA_USAGE_NEVER,
+ DMA_USAGE_OPPORTUNISTIC,
+ DMA_USAGE_ALWAYS,
+ DMA_USAGE_TEMPORARY_ALLOCATED,
+ DMA_USAGE_ALLOCATED
+} DMAUsage;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void dma_init(void);
+
+int dma_channel_allocate(uint32_t capabilities);
+
+int dma_channel_free(int channelid);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/emac_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,161 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_EMAC_API_H
+#define MBED_EMAC_API_H
+
+#if DEVICE_EMAC
+
+#include <stdbool.h>
+#include "emac_stack_mem.h"
+
+typedef struct emac_interface emac_interface_t;
+
+/**
+ * EmacInterface
+ *
+ * This interface should be used to abstract low level access to networking hardware
+ */
+
+/**
+ * Callback to be register with Emac interface and to be called fore received packets
+ *
+ * @param data Arbitrary user data (IP stack)
+ * @param buf Received data
+ */
+typedef void (*emac_link_input_fn)(void *data, emac_stack_mem_chain_t *buf);
+
+/**
+ * Callback to be register with Emac interface and to be called for link status changes
+ *
+ * @param data Arbitrary user data (IP stack)
+ * @param up Link status
+ */
+typedef void (*emac_link_state_change_fn)(void *data, bool up);
+
+/**
+ * Return maximum transmission unit
+ *
+ * @param emac Emac interface
+ * @return MTU in bytes
+ */
+typedef uint32_t (*emac_get_mtu_size_fn)(emac_interface_t *emac);
+
+/**
+ * Return interface name
+ *
+ * @param emac Emac interface
+ * @param name Pointer to where the name should be written
+ * @param size Maximum number of character to copy
+ */
+typedef void (*emac_get_ifname_fn)(emac_interface_t *emac, char *name, uint8_t size);
+
+/**
+ * Returns size of the underlying interface HW address size
+ *
+ * @param emac Emac interface
+ * @return HW address size in bytes
+ */
+typedef uint8_t (*emac_get_hwaddr_size_fn)(emac_interface_t *emac);
+
+/**
+ * Return interface hw address
+ *
+ * Copies HW address to provided memory, @param addr has to be of correct size see @a get_hwaddr_size
+ *
+ * @param emac Emac interface
+ * @param addr HW address for underlying interface
+ */
+typedef void (*emac_get_hwaddr_fn)(emac_interface_t *emac, uint8_t *addr);
+
+/**
+ * Set HW address for interface
+ *
+ * Provided address has to be of correct size, see @a get_hwaddr_size
+ *
+ * @param emac Emac interface
+ * @param addr Address to be set
+ */
+typedef void (*emac_set_hwaddr_fn)(emac_interface_t *emac, uint8_t *addr);
+
+/**
+ * Sends the packet over the link
+ *
+ * That can not be called from an interrupt context.
+ *
+ * @param emac Emac interface
+ * @param buf Packet to be send
+ * @return True if the packet was send successfully, False otherwise
+ */
+typedef bool (*emac_link_out_fn)(emac_interface_t *emac, emac_stack_mem_t *buf);
+
+/**
+ * Initializes the HW
+ *
+ * @return True on success, False in case of an error.
+ */
+typedef bool (*emac_power_up_fn)(emac_interface_t *emac);
+
+/**
+ * Deinitializes the HW
+ *
+ * @param emac Emac interface
+ */
+typedef void (*emac_power_down_fn)(emac_interface_t *emac);
+
+/**
+ * Sets a callback that needs to be called for packets received for that interface
+ *
+ * @param emac Emac interface
+ * @param input_cb Function to be register as a callback
+ * @param data Arbitrary user data to be passed to the callback
+ */
+typedef void (*emac_set_link_input_cb_fn)(emac_interface_t *emac, emac_link_input_fn input_cb, void *data);
+
+/**
+ * Sets a callback that needs to be called on link status changes for given interface
+ *
+ * @param emac Emac interface
+ * @param state_cb Function to be register as a callback
+ * @param data Arbitrary user data to be passed to the callback
+ */
+typedef void (*emac_set_link_state_cb_fn)(emac_interface_t *emac, emac_link_state_change_fn state_cb, void *data);
+
+typedef struct emac_interface_ops {
+ emac_get_mtu_size_fn get_mtu_size;
+ emac_get_ifname_fn get_ifname;
+ emac_get_hwaddr_size_fn get_hwaddr_size;
+ emac_get_hwaddr_fn get_hwaddr;
+ emac_set_hwaddr_fn set_hwaddr;
+ emac_link_out_fn link_out;
+ emac_power_up_fn power_up;
+ emac_power_down_fn power_down;
+ emac_set_link_input_cb_fn set_link_input_cb;
+ emac_set_link_state_cb_fn set_link_state_cb;
+} emac_interface_ops_t;
+
+typedef struct emac_interface {
+ const emac_interface_ops_t ops;
+ void *hw;
+} emac_interface_t;
+
+#else
+
+typedef void *emac_interface_t;
+
+#endif /* DEVICE_EMAC */
+#endif /* MBED_EMAC_API_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/ethernet_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,69 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_API_H
+#define MBED_ETHERNET_API_H
+
+#include "device.h"
+
+#if DEVICE_ETHERNET
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Connection constants
+
+int ethernet_init(void);
+void ethernet_free(void);
+
+// write size bytes from data to ethernet buffer
+// return num bytes written
+// or -1 if size is too big
+int ethernet_write(const char *data, int size);
+
+// send ethernet write buffer, returning the packet size sent
+int ethernet_send(void);
+
+// recieve from ethernet buffer, returning packet size, or 0 if no packet
+int ethernet_receive(void);
+
+// read size bytes in to data, return actual num bytes read (0..size)
+// if data == NULL, throw the bytes away
+int ethernet_read(char *data, int size);
+
+// get the ethernet address
+void ethernet_address(char *mac);
+
+// see if the link is up
+int ethernet_link(void);
+
+// force link settings
+void ethernet_set_link(int speed, int duplex);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/flash_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,120 @@
+/** \addtogroup hal */
+/** @{*/
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FLASH_API_H
+#define MBED_FLASH_API_H
+
+#include "device.h"
+#include <stdint.h>
+
+#if DEVICE_FLASH
+
+#define MBED_FLASH_INVALID_SIZE 0xFFFFFFFF
+
+typedef struct flash_s flash_t;
+
+#if TARGET_FLASH_CMSIS_ALGO
+#include "flash_data.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup flash_hal Flash HAL API
+ * @{
+ */
+
+/** Initialize the flash peripheral and the flash_t object
+ *
+ * @param obj The flash object
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_init(flash_t *obj);
+
+/** Uninitialize the flash peripheral and the flash_t object
+ *
+ * @param obj The flash object
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_free(flash_t *obj);
+
+/** Erase one sector starting at defined address
+ *
+ * The address should be at sector boundary. This function does not do any check for address alignments
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_erase_sector(flash_t *obj, uint32_t address);
+
+/** Program one page starting at defined address
+ *
+ * The page should be at page boundary, should not cross multiple sectors.
+ * This function does not do any check for address alignments or if size is aligned to a page size.
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @param data The data buffer to be programmed
+ * @param size The number of bytes to program
+ * @return 0 for success, -1 for error
+ */
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size);
+
+/** Get sector size
+ *
+ * @param obj The flash object
+ * @param address The sector starting address
+ * @return The size of a sector
+ */
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address);
+
+/** Get page size
+ *
+ * @param obj The flash object
+ * @param address The page starting address
+ * @return The size of a page
+ */
+uint32_t flash_get_page_size(const flash_t *obj);
+
+/** Get start address for the flash region
+ *
+ * @param obj The flash object
+ * @return The start address for the flash region
+ */
+uint32_t flash_get_start_address(const flash_t *obj);
+
+/** Get the flash region size
+ *
+ * @param obj The flash object
+ * @return The flash region size
+ */
+uint32_t flash_get_size(const flash_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/gpio_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,134 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_API_H
+#define MBED_GPIO_API_H
+
+#include <stdint.h>
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_gpio GPIO HAL functions
+ * @{
+ */
+
+/** Set the given pin as GPIO
+ *
+ * @param pin The pin to be set as GPIO
+ * @return The GPIO port mask for this pin
+ **/
+uint32_t gpio_set(PinName pin);
+/* Checks if gpio object is connected (pin was not initialized with NC)
+ * @param pin The pin to be set as GPIO
+ * @return 0 if port is initialized with NC
+ **/
+int gpio_is_connected(const gpio_t *obj);
+
+/** Initialize the GPIO pin
+ *
+ * @param obj The GPIO object to initialize
+ * @param pin The GPIO pin to initialize
+ */
+void gpio_init(gpio_t *obj, PinName pin);
+
+/** Set the input pin mode
+ *
+ * @param obj The GPIO object
+ * @param mode The pin mode to be set
+ */
+void gpio_mode(gpio_t *obj, PinMode mode);
+
+/** Set the pin direction
+ *
+ * @param obj The GPIO object
+ * @param direction The pin direction to be set
+ */
+void gpio_dir(gpio_t *obj, PinDirection direction);
+
+/** Set the output value
+ *
+ * @param obj The GPIO object
+ * @param value The value to be set
+ */
+void gpio_write(gpio_t *obj, int value);
+
+/** Read the input value
+ *
+ * @param obj The GPIO object
+ * @return An integer value 1 or 0
+ */
+int gpio_read(gpio_t *obj);
+
+// the following functions are generic and implemented in the common gpio.c file
+// TODO: fix, will be moved to the common gpio header file
+
+/** Init the input pin and set mode to PullDefault
+ *
+ * @param obj The GPIO object
+ * @param pin The pin name
+ */
+void gpio_init_in(gpio_t* gpio, PinName pin);
+
+/** Init the input pin and set the mode
+ *
+ * @param obj The GPIO object
+ * @param pin The pin name
+ * @param mode The pin mode to be set
+ */
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);
+
+/** Init the output pin as an output, with predefined output value 0
+ *
+ * @param obj The GPIO object
+ * @param pin The pin name
+ * @return An integer value 1 or 0
+ */
+void gpio_init_out(gpio_t* gpio, PinName pin);
+
+/** Init the pin as an output and set the output value
+ *
+ * @param obj The GPIO object
+ * @param pin The pin name
+ * @param value The value to be set
+ */
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);
+
+/** Init the pin to be in/out
+ *
+ * @param obj The GPIO object
+ * @param pin The pin name
+ * @param direction The pin direction to be set
+ * @param mode The pin mode to be set
+ * @param value The value to be set for an output pin
+ */
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/gpio_irq_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,98 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_IRQ_API_H
+#define MBED_GPIO_IRQ_API_H
+
+#include "device.h"
+
+#if DEVICE_INTERRUPTIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIO IRQ events
+ */
+typedef enum {
+ IRQ_NONE,
+ IRQ_RISE,
+ IRQ_FALL
+} gpio_irq_event;
+
+/** GPIO IRQ HAL structure. gpio_irq_s is declared in the target's HAL
+ */
+typedef struct gpio_irq_s gpio_irq_t;
+
+typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
+
+/**
+ * \defgroup hal_gpioirq GPIO IRQ HAL functions
+ * @{
+ */
+
+/** Initialize the GPIO IRQ pin
+ *
+ * @param obj The GPIO object to initialize
+ * @param pin The GPIO pin name
+ * @param handler The handler to be attached to GPIO IRQ
+ * @param id The object ID (id != 0, 0 is reserved)
+ * @return -1 if pin is NC, 0 otherwise
+ */
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
+
+/** Release the GPIO IRQ PIN
+ *
+ * @param obj The gpio object
+ */
+void gpio_irq_free(gpio_irq_t *obj);
+
+/** Enable/disable pin IRQ event
+ *
+ * @param obj The GPIO object
+ * @param event The GPIO IRQ event
+ * @param enable The enable flag
+ */
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
+
+/** Enable GPIO IRQ
+ *
+ * This is target dependent, as it might enable the entire port or just a pin
+ * @param obj The GPIO object
+ */
+void gpio_irq_enable(gpio_irq_t *obj);
+
+/** Disable GPIO IRQ
+ *
+ * This is target dependent, as it might disable the entire port or just a pin
+ * @param obj The GPIO object
+ */
+void gpio_irq_disable(gpio_irq_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/i2c_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,249 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_API_H
+#define MBED_I2C_API_H
+
+#include "device.h"
+#include "hal/buffer.h"
+
+#if DEVICE_I2C_ASYNCH
+#include "hal/dma_api.h"
+#endif
+
+#if DEVICE_I2C
+
+/**
+ * @defgroup hal_I2CEvents I2C Events Macros
+ *
+ * @{
+ */
+#define I2C_EVENT_ERROR (1 << 1)
+#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2)
+#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3)
+#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4)
+#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
+
+/**@}*/
+
+#if DEVICE_I2C_ASYNCH
+/** Asynch I2C HAL structure
+ */
+typedef struct {
+ struct i2c_s i2c; /**< Target specific I2C structure */
+ struct buffer_s tx_buff; /**< Tx buffer */
+ struct buffer_s rx_buff; /**< Rx buffer */
+} i2c_t;
+
+#else
+/** Non-asynch I2C HAL structure
+ */
+typedef struct i2c_s i2c_t;
+
+#endif
+
+enum {
+ I2C_ERROR_NO_SLAVE = -1,
+ I2C_ERROR_BUS_BUSY = -2
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_GeneralI2C I2C Configuration Functions
+ * @{
+ */
+
+/** Initialize the I2C peripheral. It sets the default parameters for I2C
+ * peripheral, and configures its specifieds pins.
+ *
+ * @param obj The I2C object
+ * @param sda The sda pin
+ * @param scl The scl pin
+ */
+void i2c_init(i2c_t *obj, PinName sda, PinName scl);
+
+/** Configure the I2C frequency
+ *
+ * @param obj The I2C object
+ * @param hz Frequency in Hz
+ */
+void i2c_frequency(i2c_t *obj, int hz);
+
+/** Send START command
+ *
+ * @param obj The I2C object
+ */
+int i2c_start(i2c_t *obj);
+
+/** Send STOP command
+ *
+ * @param obj The I2C object
+ */
+int i2c_stop(i2c_t *obj);
+
+/** Blocking reading data
+ *
+ * @param obj The I2C object
+ * @param address 7-bit address (last bit is 1)
+ * @param data The buffer for receiving
+ * @param length Number of bytes to read
+ * @param stop Stop to be generated after the transfer is done
+ * @return Number of read bytes
+ */
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop);
+
+/** Blocking sending data
+ *
+ * @param obj The I2C object
+ * @param address 7-bit address (last bit is 0)
+ * @param data The buffer for sending
+ * @param length Number of bytes to write
+ * @param stop Stop to be generated after the transfer is done
+ * @return
+ * zero or non-zero - Number of written bytes
+ * negative - I2C_ERROR_XXX status
+ */
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop);
+
+/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop()
+ *
+ * @param obj The I2C object
+ */
+void i2c_reset(i2c_t *obj);
+
+/** Read one byte
+ *
+ * @param obj The I2C object
+ * @param last Acknoledge
+ * @return The read byte
+ */
+int i2c_byte_read(i2c_t *obj, int last);
+
+/** Write one byte
+ *
+ * @param obj The I2C object
+ * @param data Byte to be written
+ * @return 0 if NAK was received, 1 if ACK was received, 2 for timeout.
+ */
+int i2c_byte_write(i2c_t *obj, int data);
+
+/**@}*/
+
+#if DEVICE_I2CSLAVE
+
+/**
+ * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
+ * @{
+ */
+
+/** Configure I2C as slave or master.
+ * @param obj The I2C object
+ * @return non-zero if a value is available
+ */
+void i2c_slave_mode(i2c_t *obj, int enable_slave);
+
+/** Check to see if the I2C slave has been addressed.
+ * @param obj The I2C object
+ * @return The status - 1 - read addresses, 2 - write to all slaves,
+ * 3 write addressed, 0 - the slave has not been addressed
+ */
+int i2c_slave_receive(i2c_t *obj);
+
+/** Configure I2C as slave or master.
+ * @param obj The I2C object
+ * @return non-zero if a value is available
+ */
+int i2c_slave_read(i2c_t *obj, char *data, int length);
+
+/** Configure I2C as slave or master.
+ * @param obj The I2C object
+ * @return non-zero if a value is available
+ */
+int i2c_slave_write(i2c_t *obj, const char *data, int length);
+
+/** Configure I2C address.
+ * @param obj The I2C object
+ * @param idx Currently not used
+ * @param address The address to be set
+ * @param mask Currently not used
+ */
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
+
+#endif
+
+/**@}*/
+
+#if DEVICE_I2C_ASYNCH
+
+/**
+ * \defgroup hal_AsynchI2C Asynchronous I2C Hardware Abstraction Layer
+ * @{
+ */
+
+/** Start I2C asynchronous transfer
+ *
+ * @param obj The I2C object
+ * @param tx The transmit buffer
+ * @param tx_length The number of bytes to transmit
+ * @param rx The receive buffer
+ * @param rx_length The number of bytes to receive
+ * @param address The address to be set - 7bit or 9bit
+ * @param stop If true, stop will be generated after the transfer is done
+ * @param handler The I2C IRQ handler to be set
+ * @param hint DMA hint usage
+ */
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** The asynchronous IRQ handler
+ *
+ * @param obj The I2C object which holds the transfer information
+ * @return Event flags if a transfer termination condition was met, otherwise return 0.
+ */
+uint32_t i2c_irq_handler_asynch(i2c_t *obj);
+
+/** Attempts to determine if the I2C peripheral is already in use
+ *
+ * @param obj The I2C object
+ * @return Non-zero if the I2C module is active or zero if it is not
+ */
+uint8_t i2c_active(i2c_t *obj);
+
+/** Abort asynchronous transfer
+ *
+ * This function does not perform any check - that should happen in upper layers.
+ * @param obj The I2C object
+ */
+void i2c_abort_asynch(i2c_t *obj);
+
+#endif
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/lp_ticker_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,88 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LPTICKER_API_H
+#define MBED_LPTICKER_API_H
+
+#include "device.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "hal/ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_LpTicker Low Power Ticker Functions
+ * @{
+ */
+
+/** Get low power ticker's data
+ *
+ * @return The low power ticker data
+ */
+const ticker_data_t* get_lp_ticker_data(void);
+
+/** The wrapper for ticker_irq_handler, to pass lp ticker's data
+ *
+ */
+void lp_ticker_irq_handler(void);
+
+/* HAL lp ticker */
+
+/** Initialize the low power ticker
+ *
+ */
+void lp_ticker_init(void);
+
+/** Read the current counter
+ *
+ * @return The current timer's counter value in microseconds
+ */
+uint32_t lp_ticker_read(void);
+
+/** Set interrupt for specified timestamp
+ *
+ * @param timestamp The time in microseconds to be set
+ */
+void lp_ticker_set_interrupt(timestamp_t timestamp);
+
+/** Disable low power ticker interrupt
+ *
+ */
+void lp_ticker_disable_interrupt(void);
+
+/** Clear the low power ticker interrupt
+ *
+ */
+void lp_ticker_clear_interrupt(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/mbed_gpio.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/gpio_api.h"
+
+static inline void _gpio_init_in(gpio_t* gpio, PinName pin, PinMode mode)
+{
+ gpio_init(gpio, pin);
+ if (pin != NC) {
+ gpio_dir(gpio, PIN_INPUT);
+ gpio_mode(gpio, mode);
+ }
+}
+
+static inline void _gpio_init_out(gpio_t* gpio, PinName pin, PinMode mode, int value)
+{
+ gpio_init(gpio, pin);
+ if (pin != NC) {
+ gpio_write(gpio, value);
+ gpio_dir(gpio, PIN_OUTPUT);
+ gpio_mode(gpio, mode);
+ }
+}
+
+void gpio_init_in(gpio_t* gpio, PinName pin) {
+ gpio_init_in_ex(gpio, pin, PullDefault);
+}
+
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode) {
+ _gpio_init_in(gpio, pin, mode);
+}
+
+void gpio_init_out(gpio_t* gpio, PinName pin) {
+ gpio_init_out_ex(gpio, pin, 0);
+}
+
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value) {
+ _gpio_init_out(gpio, pin, PullNone, value);
+}
+
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value) {
+ if (direction == PIN_INPUT) {
+ _gpio_init_in(gpio, pin, mode);
+ if (pin != NC)
+ gpio_write(gpio, value); // we prepare the value in case it is switched later
+ } else {
+ _gpio_init_out(gpio, pin, mode, value);
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/mbed_lp_ticker_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/lp_ticker_api.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+static ticker_event_queue_t events = { 0 };
+
+static const ticker_interface_t lp_interface = {
+ .init = lp_ticker_init,
+ .read = lp_ticker_read,
+ .disable_interrupt = lp_ticker_disable_interrupt,
+ .clear_interrupt = lp_ticker_clear_interrupt,
+ .set_interrupt = lp_ticker_set_interrupt,
+};
+
+static const ticker_data_t lp_data = {
+ .interface = &lp_interface,
+ .queue = &events,
+};
+
+const ticker_data_t* get_lp_ticker_data(void)
+{
+ return &lp_data;
+}
+
+void lp_ticker_irq_handler(void)
+{
+ ticker_irq_handler(&lp_data);
+}
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/mbed_pinmap_common.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/pinmap.h"
+#include "platform/mbed_error.h"
+
+void pinmap_pinout(PinName pin, const PinMap *map) {
+ if (pin == NC)
+ return;
+
+ while (map->pin != NC) {
+ if (map->pin == pin) {
+ pin_function(pin, map->function);
+
+ pin_mode(pin, PullNone);
+ return;
+ }
+ map++;
+ }
+ error("could not pinout");
+}
+
+uint32_t pinmap_merge(uint32_t a, uint32_t b) {
+ // both are the same (inc both NC)
+ if (a == b)
+ return a;
+
+ // one (or both) is not connected
+ if (a == (uint32_t)NC)
+ return b;
+ if (b == (uint32_t)NC)
+ return a;
+
+ // mis-match error case
+ error("pinmap mis-match");
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
+ while (map->pin != NC) {
+ if (map->pin == pin)
+ return map->peripheral;
+ map++;
+ }
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
+ uint32_t peripheral = (uint32_t)NC;
+
+ if (pin == (PinName)NC)
+ return (uint32_t)NC;
+ peripheral = pinmap_find_peripheral(pin, map);
+ if ((uint32_t)NC == peripheral) // no mapping available
+ error("pinmap not found for peripheral");
+ return peripheral;
+}
+
+uint32_t pinmap_find_function(PinName pin, const PinMap* map) {
+ while (map->pin != NC) {
+ if (map->pin == pin)
+ return map->function;
+ map++;
+ }
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_function(PinName pin, const PinMap* map) {
+ uint32_t function = (uint32_t)NC;
+
+ if (pin == (PinName)NC)
+ return (uint32_t)NC;
+ function = pinmap_find_function(pin, map);
+ if ((uint32_t)NC == function) // no mapping available
+ error("pinmap not found for function");
+ return function;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/mbed_ticker_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,275 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include <stddef.h>
+#include "hal/ticker_api.h"
+#include "platform/mbed_critical.h"
+
+static void schedule_interrupt(const ticker_data_t *const ticker);
+static void update_present_time(const ticker_data_t *const ticker);
+
+/*
+ * Initialize a ticker instance.
+ */
+static void initialize(const ticker_data_t *ticker)
+{
+ // return if the queue has already been initialized, in that case the
+ // interface used by the queue is already initialized.
+ if (ticker->queue->initialized) {
+ return;
+ }
+
+ ticker->interface->init();
+
+ ticker->queue->event_handler = NULL;
+ ticker->queue->head = NULL;
+ ticker->queue->present_time = 0;
+ ticker->queue->initialized = true;
+
+ update_present_time(ticker);
+ schedule_interrupt(ticker);
+}
+
+/**
+ * Set the event handler function of a ticker instance.
+ */
+static void set_handler(const ticker_data_t *const ticker, ticker_event_handler handler)
+{
+ ticker->queue->event_handler = handler;
+}
+
+/*
+ * Convert a 32 bit timestamp into a 64 bit timestamp.
+ *
+ * A 64 bit timestamp is used as the point of time of reference while the
+ * timestamp to convert is relative to this point of time.
+ *
+ * The lower 32 bits of the timestamp returned will be equal to the timestamp to
+ * convert.
+ *
+ * If the timestamp to convert is less than the lower 32 bits of the time
+ * reference then the timestamp to convert is seen as an overflowed value and
+ * the upper 32 bit of the timestamp returned will be equal to the upper 32 bit
+ * of the reference point + 1.
+ * Otherwise, the upper 32 bit returned will be equal to the upper 32 bit of the
+ * reference point.
+ *
+ * @param ref: The 64 bit timestamp of reference.
+ * @param timestamp: The timestamp to convert.
+ */
+static us_timestamp_t convert_timestamp(us_timestamp_t ref, timestamp_t timestamp)
+{
+ bool overflow = timestamp < ((timestamp_t) ref) ? true : false;
+
+ us_timestamp_t result = (ref & ~((us_timestamp_t)UINT32_MAX)) | timestamp;
+ if (overflow) {
+ result += (1ULL<<32);
+ }
+
+ return result;
+}
+
+/**
+ * Update the present timestamp value of a ticker.
+ */
+static void update_present_time(const ticker_data_t *const ticker)
+{
+ ticker->queue->present_time = convert_timestamp(
+ ticker->queue->present_time,
+ ticker->interface->read()
+ );
+}
+
+/**
+ * Compute the time when the interrupt has to be triggered and schedule it.
+ *
+ * If there is no event in the queue or the next event to execute is in more
+ * than MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA us from now then the ticker
+ * irq will be scheduled in MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA us.
+ * Otherwise the irq will be scheduled to happen when the running counter reach
+ * the timestamp of the first event in the queue.
+ *
+ * @note If there is no event in the queue then the interrupt is scheduled to
+ * in MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA. This is necessary to keep track
+ * of the timer overflow.
+ */
+static void schedule_interrupt(const ticker_data_t *const ticker)
+{
+ update_present_time(ticker);
+ uint32_t relative_timeout = MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA;
+
+ if (ticker->queue->head) {
+ us_timestamp_t present = ticker->queue->present_time;
+ us_timestamp_t next_event_timestamp = ticker->queue->head->timestamp;
+
+ // if the event at the head of the queue is in the past then schedule
+ // it immediately.
+ if (next_event_timestamp < present) {
+ relative_timeout = 0;
+ } else if ((next_event_timestamp - present) < MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA) {
+ relative_timeout = next_event_timestamp - present;
+ }
+ }
+
+ ticker->interface->set_interrupt(ticker->queue->present_time + relative_timeout);
+}
+
+void ticker_set_handler(const ticker_data_t *const ticker, ticker_event_handler handler)
+{
+ initialize(ticker);
+ set_handler(ticker, handler);
+}
+
+void ticker_irq_handler(const ticker_data_t *const ticker)
+{
+ ticker->interface->clear_interrupt();
+
+ /* Go through all the pending TimerEvents */
+ while (1) {
+ if (ticker->queue->head == NULL) {
+ break;
+ }
+
+ // update the current timestamp used by the queue
+ update_present_time(ticker);
+
+ if (ticker->queue->head->timestamp <= ticker->queue->present_time) {
+ // This event was in the past:
+ // point to the following one and execute its handler
+ ticker_event_t *p = ticker->queue->head;
+ ticker->queue->head = ticker->queue->head->next;
+ if (ticker->queue->event_handler != NULL) {
+ (*ticker->queue->event_handler)(p->id); // NOTE: the handler can set new events
+ }
+ /* Note: We continue back to examining the head because calling the
+ * event handler may have altered the chain of pending events. */
+ } else {
+ break;
+ }
+ }
+
+ schedule_interrupt(ticker);
+}
+
+void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uint32_t id)
+{
+ core_util_critical_section_enter();
+
+ // update the current timestamp
+ update_present_time(ticker);
+ us_timestamp_t absolute_timestamp = convert_timestamp(
+ ticker->queue->present_time,
+ timestamp
+ );
+ core_util_critical_section_exit();
+
+ // defer to ticker_insert_event_us
+ ticker_insert_event_us(
+ ticker,
+ obj, absolute_timestamp, id
+ );
+}
+
+void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id)
+{
+ core_util_critical_section_enter();
+
+ // update the current timestamp
+ update_present_time(ticker);
+
+ // initialise our data
+ obj->timestamp = timestamp;
+ obj->id = id;
+
+ /* Go through the list until we either reach the end, or find
+ an element this should come before (which is possibly the
+ head). */
+ ticker_event_t *prev = NULL, *p = ticker->queue->head;
+ while (p != NULL) {
+ /* check if we come before p */
+ if (timestamp < p->timestamp) {
+ break;
+ }
+ /* go to the next element */
+ prev = p;
+ p = p->next;
+ }
+
+ /* if we're at the end p will be NULL, which is correct */
+ obj->next = p;
+
+ /* if prev is NULL we're at the head */
+ if (prev == NULL) {
+ ticker->queue->head = obj;
+ } else {
+ prev->next = obj;
+ }
+
+ schedule_interrupt(ticker);
+
+ core_util_critical_section_exit();
+}
+
+void ticker_remove_event(const ticker_data_t *const ticker, ticker_event_t *obj)
+{
+ core_util_critical_section_enter();
+
+ // remove this object from the list
+ if (ticker->queue->head == obj) {
+ // first in the list, so just drop me
+ ticker->queue->head = obj->next;
+ schedule_interrupt(ticker);
+ } else {
+ // find the object before me, then drop me
+ ticker_event_t* p = ticker->queue->head;
+ while (p != NULL) {
+ if (p->next == obj) {
+ p->next = obj->next;
+ break;
+ }
+ p = p->next;
+ }
+ }
+
+ core_util_critical_section_exit();
+}
+
+timestamp_t ticker_read(const ticker_data_t *const ticker)
+{
+ return ticker_read_us(ticker);
+}
+
+us_timestamp_t ticker_read_us(const ticker_data_t *const ticker)
+{
+ update_present_time(ticker);
+ return ticker->queue->present_time;
+}
+
+int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp)
+{
+ int ret = 0;
+
+ /* if head is NULL, there are no pending events */
+ core_util_critical_section_enter();
+ if (data->queue->head != NULL) {
+ *timestamp = data->queue->head->timestamp;
+ ret = 1;
+ }
+ core_util_critical_section_exit();
+
+ return ret;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/mbed_us_ticker_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/us_ticker_api.h"
+
+static ticker_event_queue_t events = { 0 };
+
+static const ticker_interface_t us_interface = {
+ .init = us_ticker_init,
+ .read = us_ticker_read,
+ .disable_interrupt = us_ticker_disable_interrupt,
+ .clear_interrupt = us_ticker_clear_interrupt,
+ .set_interrupt = us_ticker_set_interrupt,
+};
+
+static const ticker_data_t us_data = {
+ .interface = &us_interface,
+ .queue = &events
+};
+
+const ticker_data_t* get_us_ticker_data(void)
+{
+ return &us_data;
+}
+
+void us_ticker_irq_handler(void)
+{
+ ticker_irq_handler(&us_data);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/pinmap.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,51 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINMAP_H
+#define MBED_PINMAP_H
+
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ int peripheral;
+ int function;
+} PinMap;
+
+void pin_function(PinName pin, int function);
+void pin_mode (PinName pin, PinMode mode);
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_function(PinName pin, const PinMap* map);
+uint32_t pinmap_merge (uint32_t a, uint32_t b);
+void pinmap_pinout (PinName pin, const PinMap *map);
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_find_function(PinName pin, const PinMap* map);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/port_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,94 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTMAP_H
+#define MBED_PORTMAP_H
+
+#include "device.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Port HAL structure. port_s is declared in the target's HAL
+ */
+typedef struct port_s port_t;
+
+/**
+ * \defgroup hal_port Port HAL functions
+ * @{
+ */
+
+/** Get the pin name from the port's pin number
+ *
+ * @param port The port name
+ * @param pin_n The pin number within the specified port
+ * @return The pin name for the port's pin number
+ */
+PinName port_pin(PortName port, int pin_n);
+
+/** Initilize the port
+ *
+ * @param obj The port object to initialize
+ * @param port The port name
+ * @param mask The bitmask to identify which bits in the port should be included (0 - ignore)
+ * @param dir The port direction
+ */
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir);
+
+/** Set the input port mode
+ *
+ * @param obj The port object
+ * @param mode THe port mode to be set
+ */
+void port_mode(port_t *obj, PinMode mode);
+
+/** Set port direction (in/out)
+ *
+ * @param obj The port object
+ * @param dir The port direction to be set
+ */
+void port_dir(port_t *obj, PinDirection dir);
+
+/** Write value to the port
+ *
+ * @param obj The port object
+ * @param value The value to be set
+ */
+void port_write(port_t *obj, int value);
+
+/** Read the current value on the port
+ *
+ * @param obj The port object
+ * @return An integer with each bit corresponding to an associated port pin setting
+ */
+int port_read(port_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/pwmout_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,121 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_API_H
+#define MBED_PWMOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_PWMOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Pwmout hal structure. pwmout_s is declared in the target's hal
+ */
+typedef struct pwmout_s pwmout_t;
+
+/**
+ * \defgroup hal_pwmout Pwmout hal functions
+ * @{
+ */
+
+/** Initialize the pwm out peripheral and configure the pin
+ *
+ * @param obj The pwmout object to initialize
+ * @param pin The pwmout pin to initialize
+ */
+void pwmout_init(pwmout_t *obj, PinName pin);
+
+/** Deinitialize the pwmout object
+ *
+ * @param obj The pwmout object
+ */
+void pwmout_free(pwmout_t *obj);
+
+/** Set the output duty-cycle in range <0.0f, 1.0f>
+ *
+ * Value 0.0f represents 0 percentage, 1.0f represents 100 percent.
+ * @param obj The pwmout object
+ * @param percent The floating-point percentage number
+ */
+void pwmout_write(pwmout_t *obj, float percent);
+
+/** Read the current float-point output duty-cycle
+ *
+ * @param obj The pwmout object
+ * @return A floating-point output duty-cycle
+ */
+float pwmout_read(pwmout_t *obj);
+
+/** Set the PWM period specified in seconds, keeping the duty cycle the same
+ *
+ * Periods smaller than microseconds (the lowest resolution) are set to zero.
+ * @param obj The pwmout object
+ * @param seconds The floating-point seconds period
+ */
+void pwmout_period(pwmout_t *obj, float seconds);
+
+/** Set the PWM period specified in miliseconds, keeping the duty cycle the same
+ *
+ * @param obj The pwmout object
+ * @param ms The milisecond period
+ */
+void pwmout_period_ms(pwmout_t *obj, int ms);
+
+/** Set the PWM period specified in microseconds, keeping the duty cycle the same
+ *
+ * @param obj The pwmout object
+ * @param us The microsecond period
+ */
+void pwmout_period_us(pwmout_t *obj, int us);
+
+/** Set the PWM pulsewidth specified in seconds, keeping the period the same.
+ *
+ * @param obj The pwmout object
+ * @param seconds The floating-point pulsewidth in seconds
+ */
+void pwmout_pulsewidth(pwmout_t *obj, float seconds);
+
+/** Set the PWM pulsewidth specified in miliseconds, keeping the period the same.
+ *
+ * @param obj The pwmout object
+ * @param ms The floating-point pulsewidth in miliseconds
+ */
+void pwmout_pulsewidth_ms(pwmout_t *obj, int ms);
+
+/** Set the PWM pulsewidth specified in microseconds, keeping the period the same.
+ *
+ * @param obj The pwmout object
+ * @param us The floating-point pulsewidth in microseconds
+ */
+void pwmout_pulsewidth_us(pwmout_t *obj, int us);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/rtc_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,78 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RTC_API_H
+#define MBED_RTC_API_H
+
+#include "device.h"
+
+#if DEVICE_RTC
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_rtc RTC hal functions
+ * @{
+ */
+
+/** Initialize the RTC peripheral
+ *
+ */
+void rtc_init(void);
+
+/** Deinitialize RTC
+ *
+ * TODO: The function is not used by rtc api in mbed-drivers.
+ */
+void rtc_free(void);
+
+/** Get the RTC enable status
+ *
+ * @retval 0 disabled
+ * @retval 1 enabled
+ */
+int rtc_isenabled(void);
+
+/** Get the current time from the RTC peripheral
+ *
+ * @return The current time
+ */
+time_t rtc_read(void);
+
+/** Set the current time to the RTC peripheral
+ *
+ * @param t The current time to be set
+ */
+void rtc_write(time_t t);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/serial_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,308 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_API_H
+#define MBED_SERIAL_API_H
+
+#include "device.h"
+#include "hal/buffer.h"
+#include "hal/dma_api.h"
+
+#if DEVICE_SERIAL
+
+#define SERIAL_EVENT_TX_SHIFT (2)
+#define SERIAL_EVENT_RX_SHIFT (8)
+
+#define SERIAL_EVENT_TX_MASK (0x00FC)
+#define SERIAL_EVENT_RX_MASK (0x3F00)
+
+#define SERIAL_EVENT_ERROR (1 << 1)
+
+/**
+ * @defgroup SerialTXEvents Serial TX Events Macros
+ *
+ * @{
+ */
+#define SERIAL_EVENT_TX_COMPLETE (1 << (SERIAL_EVENT_TX_SHIFT + 0))
+#define SERIAL_EVENT_TX_ALL (SERIAL_EVENT_TX_COMPLETE)
+/**@}*/
+
+/**
+ * @defgroup SerialRXEvents Serial RX Events Macros
+ *
+ * @{
+ */
+#define SERIAL_EVENT_RX_COMPLETE (1 << (SERIAL_EVENT_RX_SHIFT + 0))
+#define SERIAL_EVENT_RX_OVERRUN_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 1))
+#define SERIAL_EVENT_RX_FRAMING_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 2))
+#define SERIAL_EVENT_RX_PARITY_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 3))
+#define SERIAL_EVENT_RX_OVERFLOW (1 << (SERIAL_EVENT_RX_SHIFT + 4))
+#define SERIAL_EVENT_RX_CHARACTER_MATCH (1 << (SERIAL_EVENT_RX_SHIFT + 5))
+#define SERIAL_EVENT_RX_ALL (SERIAL_EVENT_RX_OVERFLOW | SERIAL_EVENT_RX_PARITY_ERROR | \
+ SERIAL_EVENT_RX_FRAMING_ERROR | SERIAL_EVENT_RX_OVERRUN_ERROR | \
+ SERIAL_EVENT_RX_COMPLETE | SERIAL_EVENT_RX_CHARACTER_MATCH)
+/**@}*/
+
+#define SERIAL_RESERVED_CHAR_MATCH (255)
+
+typedef enum {
+ ParityNone = 0,
+ ParityOdd = 1,
+ ParityEven = 2,
+ ParityForced1 = 3,
+ ParityForced0 = 4
+} SerialParity;
+
+typedef enum {
+ RxIrq,
+ TxIrq
+} SerialIrq;
+
+typedef enum {
+ FlowControlNone,
+ FlowControlRTS,
+ FlowControlCTS,
+ FlowControlRTSCTS
+} FlowControl;
+
+typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
+
+#if DEVICE_SERIAL_ASYNCH
+/** Asynch serial HAL structure
+ */
+typedef struct {
+ struct serial_s serial; /**< Target specific serial structure */
+ struct buffer_s tx_buff; /**< TX buffer */
+ struct buffer_s rx_buff; /**< RX buffer */
+ uint8_t char_match; /**< Character to be matched */
+ uint8_t char_found; /**< State of the matched character */
+} serial_t;
+
+#else
+/** Non-asynch serial HAL structure
+ */
+typedef struct serial_s serial_t;
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_GeneralSerial Serial Configuration Functions
+ * @{
+ */
+
+/** Initialize the serial peripheral. It sets the default parameters for serial
+ * peripheral, and configures its specifieds pins.
+ *
+ * @param obj The serial object
+ * @param tx The TX pin name
+ * @param rx The RX pin name
+ */
+void serial_init(serial_t *obj, PinName tx, PinName rx);
+
+/** Release the serial peripheral, not currently invoked. It requires further
+ * resource management.
+ *
+ * @param obj The serial object
+ */
+void serial_free(serial_t *obj);
+
+/** Configure the baud rate
+ *
+ * @param obj The serial object
+ * @param baudrate The baud rate to be configured
+ */
+void serial_baud(serial_t *obj, int baudrate);
+
+/** Configure the format. Set the number of bits, parity and the number of stop bits
+ *
+ * @param obj The serial object
+ * @param data_bits The number of data bits
+ * @param parity The parity
+ * @param stop_bits The number of stop bits
+ */
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
+
+/** The serial interrupt handler registration
+ *
+ * @param obj The serial object
+ * @param handler The interrupt handler which will be invoked when the interrupt fires
+ * @param id The SerialBase object
+ */
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
+
+/** Configure serial interrupt. This function is used for word-approach
+ *
+ * @param obj The serial object
+ * @param irq The serial IRQ type (RX or TX)
+ * @param enable Set to non-zero to enable events, or zero to disable them
+ */
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable);
+
+/** Get character. This is a blocking call, waiting for a character
+ *
+ * @param obj The serial object
+ */
+int serial_getc(serial_t *obj);
+
+/** Send a character. This is a blocking call, waiting for a peripheral to be available
+ * for writing
+ *
+ * @param obj The serial object
+ * @param c The character to be sent
+ */
+void serial_putc(serial_t *obj, int c);
+
+/** Check if the serial peripheral is readable
+ *
+ * @param obj The serial object
+ * @return Non-zero value if a character can be read, 0 if nothing to read
+ */
+int serial_readable(serial_t *obj);
+
+/** Check if the serial peripheral is writable
+ *
+ * @param obj The serial object
+ * @return Non-zero value if a character can be written, 0 otherwise.
+ */
+int serial_writable(serial_t *obj);
+
+/** Clear the serial peripheral
+ *
+ * @param obj The serial object
+ */
+void serial_clear(serial_t *obj);
+
+/** Set the break
+ *
+ * @param obj The serial object
+ */
+void serial_break_set(serial_t *obj);
+
+/** Clear the break
+ *
+ * @param obj The serial object
+ */
+void serial_break_clear(serial_t *obj);
+
+/** Configure the TX pin for UART function.
+ *
+ * @param tx The pin name used for TX
+ */
+void serial_pinout_tx(PinName tx);
+
+/** Configure the serial for the flow control. It sets flow control in the hardware
+ * if a serial peripheral supports it, otherwise software emulation is used.
+ *
+ * @param obj The serial object
+ * @param type The type of the flow control. Look at the available FlowControl types.
+ * @param rxflow The TX pin name
+ * @param txflow The RX pin name
+ */
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
+
+#if DEVICE_SERIAL_ASYNCH
+
+/**@}*/
+
+/**
+ * \defgroup hal_AsynchSerial Asynchronous Serial Hardware Abstraction Layer
+ * @{
+ */
+
+/** Begin asynchronous TX transfer. The used buffer is specified in the serial object,
+ * tx_buff
+ *
+ * @param obj The serial object
+ * @param tx The transmit buffer
+ * @param tx_length The number of bytes to transmit
+ * @param tx_width Deprecated argument
+ * @param handler The serial handler
+ * @param event The logical OR of events to be registered
+ * @param hint A suggestion for how to use DMA with this transfer
+ * @return Returns number of data transfered, otherwise returns 0
+ */
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** Begin asynchronous RX transfer (enable interrupt for data collecting)
+ * The used buffer is specified in the serial object - rx_buff
+ *
+ * @param obj The serial object
+ * @param rx The receive buffer
+ * @param rx_length The number of bytes to receive
+ * @param rx_width Deprecated argument
+ * @param handler The serial handler
+ * @param event The logical OR of events to be registered
+ * @param handler The serial handler
+ * @param char_match A character in range 0-254 to be matched
+ * @param hint A suggestion for how to use DMA with this transfer
+ */
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint);
+
+/** Attempts to determine if the serial peripheral is already in use for TX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_tx_active(serial_t *obj);
+
+/** Attempts to determine if the serial peripheral is already in use for RX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_rx_active(serial_t *obj);
+
+/** The asynchronous TX and RX handler.
+ *
+ * @param obj The serial object
+ * @return Returns event flags if an RX transfer termination condition was met; otherwise returns 0
+ */
+int serial_irq_handler_asynch(serial_t *obj);
+
+/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and
+ * flushes the TX hardware buffer if TX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_tx_abort_asynch(serial_t *obj);
+
+/** Abort the ongoing RX transaction. It disables the enabled interrupt for RX and
+ * flushes the RX hardware buffer if RX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_rx_abort_asynch(serial_t *obj);
+
+/**@}*/
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/sleep_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,70 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SLEEP_API_H
+#define MBED_SLEEP_API_H
+
+#include "device.h"
+
+#if DEVICE_SLEEP
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Send the microcontroller to sleep
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void hal_sleep(void);
+
+/** Send the microcontroller to deep sleep
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void hal_deepsleep(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/spi_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,237 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_API_H
+#define MBED_SPI_API_H
+
+#include "device.h"
+#include "hal/dma_api.h"
+#include "hal/buffer.h"
+
+#if DEVICE_SPI
+
+#define SPI_EVENT_ERROR (1 << 1)
+#define SPI_EVENT_COMPLETE (1 << 2)
+#define SPI_EVENT_RX_OVERFLOW (1 << 3)
+#define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
+
+#define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
+
+#define SPI_FILL_WORD (0xFFFF)
+
+#if DEVICE_SPI_ASYNCH
+/** Asynch SPI HAL structure
+ */
+typedef struct {
+ struct spi_s spi; /**< Target specific SPI structure */
+ struct buffer_s tx_buff; /**< Tx buffer */
+ struct buffer_s rx_buff; /**< Rx buffer */
+} spi_t;
+
+#else
+/** Non-asynch SPI HAL structure
+ */
+typedef struct spi_s spi_t;
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_GeneralSPI SPI Configuration Functions
+ * @{
+ */
+
+/** Initialize the SPI peripheral
+ *
+ * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
+ * @param[out] obj The SPI object to initialize
+ * @param[in] mosi The pin to use for MOSI
+ * @param[in] miso The pin to use for MISO
+ * @param[in] sclk The pin to use for SCLK
+ * @param[in] ssel The pin to use for SSEL
+ */
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+/** Release a SPI object
+ *
+ * TODO: spi_free is currently unimplemented
+ * This will require reference counting at the C++ level to be safe
+ *
+ * Return the pins owned by the SPI object to their reset state
+ * Disable the SPI peripheral
+ * Disable the SPI clock
+ * @param[in] obj The SPI object to deinitialize
+ */
+void spi_free(spi_t *obj);
+
+/** Configure the SPI format
+ *
+ * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
+ * The default bit order is MSB.
+ * @param[in,out] obj The SPI object to configure
+ * @param[in] bits The number of bits per frame
+ * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
+ * @param[in] slave Zero for master mode or non-zero for slave mode
+ */
+void spi_format(spi_t *obj, int bits, int mode, int slave);
+
+/** Set the SPI baud rate
+ *
+ * Actual frequency may differ from the desired frequency due to available dividers and bus clock
+ * Configures the SPI peripheral's baud rate
+ * @param[in,out] obj The SPI object to configure
+ * @param[in] hz The baud rate in Hz
+ */
+void spi_frequency(spi_t *obj, int hz);
+
+/**@}*/
+/**
+ * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Write a byte out in master mode and receive a value
+ *
+ * @param[in] obj The SPI peripheral to use for sending
+ * @param[in] value The value to send
+ * @return Returns the value received during send
+ */
+int spi_master_write(spi_t *obj, int value);
+
+/** Write a block out in master mode and receive a value
+ *
+ * The total number of bytes sent and recieved will be the maximum of
+ * tx_length and rx_length. The bytes written will be padded with the
+ * value 0xff.
+ *
+ * @param[in] obj The SPI peripheral to use for sending
+ * @param[in] tx_buffer Pointer to the byte-array of data to write to the device
+ * @param[in] tx_length Number of bytes to write, may be zero
+ * @param[in] rx_buffer Pointer to the byte-array of data to read from the device
+ * @param[in] rx_length Number of bytes to read, may be zero
+ * @returns
+ * The number of bytes written and read from the device. This is
+ * maximum of tx_length and rx_length.
+ */
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length);
+
+/** Check if a value is available to read
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if a value is available
+ */
+int spi_slave_receive(spi_t *obj);
+
+/** Get a received value out of the SPI receive buffer in slave mode
+ *
+ * Blocks until a value is available
+ * @param[in] obj The SPI peripheral to read
+ * @return The value received
+ */
+int spi_slave_read(spi_t *obj);
+
+/** Write a value to the SPI peripheral in slave mode
+ *
+ * Blocks until the SPI peripheral can be written to
+ * @param[in] obj The SPI peripheral to write
+ * @param[in] value The value to write
+ */
+void spi_slave_write(spi_t *obj, int value);
+
+/** Checks if the specified SPI peripheral is in use
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if the peripheral is currently transmitting
+ */
+int spi_busy(spi_t *obj);
+
+/** Get the module number
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return The module number
+ */
+uint8_t spi_get_module(spi_t *obj);
+
+/**@}*/
+
+#if DEVICE_SPI_ASYNCH
+/**
+ * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
+ *
+ * @param[in] obj The SPI object that holds the transfer information
+ * @param[in] tx The transmit buffer
+ * @param[in] tx_length The number of bytes to transmit
+ * @param[in] rx The receive buffer
+ * @param[in] rx_length The number of bytes to receive
+ * @param[in] bit_width The bit width of buffer words
+ * @param[in] event The logical OR of events to be registered
+ * @param[in] handler SPI interrupt handler
+ * @param[in] hint A suggestion for how to use DMA with this transfer
+ */
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** The asynchronous IRQ handler
+ *
+ * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
+ * conditions, such as buffer overflows or transfer complete.
+ * @param[in] obj The SPI object that holds the transfer information
+ * @return Event flags if a transfer termination condition was met; otherwise 0.
+ */
+uint32_t spi_irq_handler_asynch(spi_t *obj);
+
+/** Attempts to determine if the SPI peripheral is already in use
+ *
+ * If a temporary DMA channel has been allocated, peripheral is in use.
+ * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
+ * channel were allocated.
+ * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
+ * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
+ * there are any bytes in the FIFOs.
+ * @param[in] obj The SPI object to check for activity
+ * @return Non-zero if the SPI port is active or zero if it is not.
+ */
+uint8_t spi_active(spi_t *obj);
+
+/** Abort an SPI transfer
+ *
+ * @param obj The SPI peripheral to stop
+ */
+void spi_abort_asynch(spi_t *obj);
+
+
+#endif
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // SPI_DEVICE
+
+#endif // MBED_SPI_API_H
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/storage_abstraction/Driver_Common.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,61 @@
+
+/** \addtogroup hal */
+/** @{*/
+/*
+ * Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_COMMON_H
+#define __DRIVER_COMMON_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/****** This file has been deprecated since mbed-os-5.5 *****/
+
+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct _ARM_DRIVER_VERSION {
+ uint16_t api; ///< API version
+ uint16_t drv; ///< Driver version
+} ARM_DRIVER_VERSION;
+
+/* General return codes */
+#define ARM_DRIVER_OK 0 ///< Operation succeeded
+#define ARM_DRIVER_ERROR -1 ///< Unspecified error
+#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy
+#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred
+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
+#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error
+#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors
+
+/**
+\brief General power states
+*/
+typedef enum _ARM_POWER_STATE {
+ ARM_POWER_OFF, ///< Power off: no operation possible
+ ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
+ ARM_POWER_FULL ///< Power on: full operation at maximum performance
+} ARM_POWER_STATE;
+
+#endif /* __DRIVER_COMMON_H */
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/storage_abstraction/Driver_Storage.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,776 @@
+
+/** \addtogroup hal */
+/** @{*/
+/*
+ * Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_STORAGE_H
+#define __DRIVER_STORAGE_H
+
+#include <stdint.h>
+
+/****** This file has been deprecated since mbed-os-5.5 *****/
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "Driver_Common.h"
+
+#define ARM_STORAGE_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,00) /* API version */
+
+
+#define _ARM_Driver_Storage_(n) Driver_Storage##n
+#define ARM_Driver_Storage_(n) _ARM_Driver_Storage_(n)
+
+#define ARM_STORAGE_INVALID_OFFSET (0xFFFFFFFFFFFFFFFFULL) ///< Invalid address (relative to a storage controller's
+ ///< address space). A storage block may never start at this address.
+
+#define ARM_STORAGE_INVALID_ADDRESS (0xFFFFFFFFUL) ///< Invalid address within the processor's memory address space.
+ ///< Refer to memory-mapped storage, i.e. < \ref ARM_DRIVER_STORAGE::ResolveAddress().
+
+/****** Storage specific error codes *****/
+#define ARM_STORAGE_ERROR_NOT_ERASABLE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Part (or all) of the range provided to Erase() isn't erasable.
+#define ARM_STORAGE_ERROR_NOT_PROGRAMMABLE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Part (or all) of the range provided to ProgramData() isn't programmable.
+#define ARM_STORAGE_ERROR_PROTECTED (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Part (or all) of the range to Erase() or ProgramData() is protected.
+#define ARM_STORAGE_ERROR_RUNTIME_OR_INTEGRITY_FAILURE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Runtime or sanity-check failure.
+
+/**
+ * \brief Attributes of the storage range within a storage block.
+ */
+typedef struct _ARM_STORAGE_BLOCK_ATTRIBUTES {
+ uint32_t erasable : 1; ///< Erasing blocks is permitted with a minimum granularity of 'erase_unit'.
+ ///< @note: if 'erasable' is 0--i.e. the 'erase' operation isn't available--then
+ ///< 'erase_unit' (see below) is immaterial and should be 0.
+ uint32_t programmable : 1; ///< Writing to ranges is permitted with a minimum granularity of 'program_unit'.
+ ///< Writes are typically achieved through the ProgramData operation (following an erase);
+ ///< if storage isn't erasable (see 'erasable' above) but is memory-mapped
+ ///< (i.e. 'memory_mapped'), it can be written directly using memory-store operations.
+ uint32_t executable : 1; ///< This storage block can hold program data; the processor can fetch and execute code
+ ///< sourced from it. Often this is accompanied with the device being 'memory_mapped' (see \ref ARM_STORAGE_INFO).
+ uint32_t protectable : 1; ///< The entire block can be protected from program and erase operations. Once protection
+ ///< is enabled for a block, its 'erasable' and 'programmable' bits are turned off.
+ uint32_t reserved : 28;
+ uint32_t erase_unit; ///< Minimum erase size in bytes.
+ ///< The offset of the start of the erase-range should also be aligned with this value.
+ ///< Applicable if the 'erasable' attribute is set for the block.
+ ///< @note: if 'erasable' (see above) is 0--i.e. the 'erase' operation isn't available--then
+ ///< 'erase_unit' is immaterial and should be 0.
+ uint32_t protection_unit; ///< Minimum protectable size in bytes. Applicable if the 'protectable'
+ ///< attribute is set for the block. This should be a divisor of the block's size. A
+ ///< block can be considered to be made up of consecutive, individually-protectable fragments.
+} ARM_STORAGE_BLOCK_ATTRIBUTES;
+
+/**
+ * \brief A storage block is a range of memory with uniform attributes. Storage blocks
+ * combine to make up the address map of a storage controller.
+ */
+typedef struct _ARM_STORAGE_BLOCK {
+ uint64_t addr; ///< This is the start address of the storage block. It is
+ ///< expressed as an offset from the start of the storage map
+ ///< maintained by the owning storage controller.
+ uint64_t size; ///< This is the size of the storage block, in units of bytes.
+ ///< Together with addr, it describes a range [addr, addr+size).
+ ARM_STORAGE_BLOCK_ATTRIBUTES attributes; ///< Attributes for this block.
+} ARM_STORAGE_BLOCK;
+
+/**
+ * The check for a valid ARM_STORAGE_BLOCK.
+ */
+#define ARM_STORAGE_VALID_BLOCK(BLK) (((BLK)->addr != ARM_STORAGE_INVALID_OFFSET) && ((BLK)->size != 0))
+
+/**
+ * \brief Values for encoding storage memory-types with respect to programmability.
+ *
+ * Please ensure that the maximum of the following memory types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::programmability.
+ */
+#define ARM_STORAGE_PROGRAMMABILITY_RAM (0x0)
+#define ARM_STORAGE_PROGRAMMABILITY_ROM (0x1) ///< Read-only memory.
+#define ARM_STORAGE_PROGRAMMABILITY_WORM (0x2) ///< write-once-read-only-memory (WORM).
+#define ARM_STORAGE_PROGRAMMABILITY_ERASABLE (0x3) ///< re-programmable based on erase. Supports multiple writes.
+
+/**
+ * Values for encoding data-retention levels for storage blocks.
+ *
+ * Please ensure that the maximum of the following retention types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::retention_level.
+ */
+#define ARM_RETENTION_WHILE_DEVICE_ACTIVE (0x0) ///< Data is retained only during device activity.
+#define ARM_RETENTION_ACROSS_SLEEP (0x1) ///< Data is retained across processor sleep.
+#define ARM_RETENTION_ACROSS_DEEP_SLEEP (0x2) ///< Data is retained across processor deep-sleep.
+#define ARM_RETENTION_BATTERY_BACKED (0x3) ///< Data is battery-backed. Device can be powered off.
+#define ARM_RETENTION_NVM (0x4) ///< Data is retained in non-volatile memory.
+
+/**
+ * Device Data Security Protection Features. Applicable mostly to EXTERNAL_NVM.
+ */
+typedef struct _ARM_STORAGE_SECURITY_FEATURES {
+ uint32_t acls : 1; ///< Protection against internal software attacks using ACLs.
+ uint32_t rollback_protection : 1; ///< Roll-back protection. Set to true if the creator of the storage
+ ///< can ensure that an external attacker can't force an
+ ///< older firmware to run or to revert back to a previous state.
+ uint32_t tamper_proof : 1; ///< Tamper-proof memory (will be deleted on tamper-attempts using board level or chip level sensors).
+ uint32_t internal_flash : 1; ///< Internal flash.
+ uint32_t reserved1 : 12;
+
+ /**
+ * Encode support for hardening against various classes of attacks.
+ */
+ uint32_t software_attacks : 1; ///< device software (malware running on the device).
+ uint32_t board_level_attacks : 1; ///< board level attacks (debug probes, copy protection fuses.)
+ uint32_t chip_level_attacks : 1; ///< chip level attacks (tamper-protection).
+ uint32_t side_channel_attacks : 1; ///< side channel attacks.
+ uint32_t reserved2 : 12;
+} ARM_STORAGE_SECURITY_FEATURES;
+
+#define ARM_STORAGE_PROGRAM_CYCLES_INFINITE (0UL) /**< Infinite or unknown endurance for reprogramming. */
+
+/**
+ * \brief Storage information. This contains device-metadata. It is the return
+ * value from calling GetInfo() on the storage driver.
+ *
+ * \details These fields serve a different purpose than the ones contained in
+ * \ref ARM_STORAGE_CAPABILITIES, which is another structure containing
+ * device-level metadata. ARM_STORAGE_CAPABILITIES describes the API
+ * capabilities, whereas ARM_STORAGE_INFO describes the device. Furthermore
+ * ARM_STORAGE_CAPABILITIES fits within a single word, and is designed to be
+ * passed around by value; ARM_STORAGE_INFO, on the other hand, contains
+ * metadata which doesn't fit into a single word and requires the use of
+ * pointers to be moved around.
+ */
+typedef struct _ARM_STORAGE_INFO {
+ uint64_t total_storage; ///< Total available storage, in bytes.
+ uint32_t program_unit; ///< Minimum programming size in bytes.
+ ///< The offset of the start of the program-range should also be aligned with this value.
+ ///< Applicable only if the 'programmable' attribute is set for a block.
+ ///< @note: setting program_unit to 0 has the effect of disabling the size and alignment
+ ///< restrictions (setting it to 1 also has the same effect).
+ uint32_t optimal_program_unit; ///< Optimal programming page-size in bytes. Some storage controllers
+ ///< have internal buffers into which to receive data. Writing in chunks of
+ ///< 'optimal_program_unit' would achieve maximum programming speed.
+ ///< Applicable only if the 'programmable' attribute is set for the underlying block(s).
+ uint32_t program_cycles; ///< A measure of endurance for reprogramming.
+ ///< Use ARM_STORAGE_PROGRAM_CYCLES_INFINITE for infinite or unknown endurance.
+ uint32_t erased_value : 1; ///< Contents of erased memory (usually 1 to indicate erased bytes with state 0xFF).
+ uint32_t memory_mapped : 1; ///< This storage device has a mapping onto the processor's memory address space.
+ ///< @note: For a memory-mapped block which isn't erasable but is programmable (i.e. if
+ ///< 'erasable' is set to 0, but 'programmable' is 1), writes should be possible directly to
+ ///< the memory-mapped storage without going through the ProgramData operation.
+ uint32_t programmability : 4; ///< A value to indicate storage programmability.
+ uint32_t retention_level : 4;
+ uint32_t reserved : 22;
+ ARM_STORAGE_SECURITY_FEATURES security; ///< \ref ARM_STORAGE_SECURITY_FEATURES
+} ARM_STORAGE_INFO;
+
+/**
+\brief Operating status of the storage controller.
+*/
+typedef struct _ARM_STORAGE_STATUS {
+ uint32_t busy : 1; ///< Controller busy flag
+ uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation)
+} ARM_STORAGE_STATUS;
+
+/**
+ * \brief Storage Driver API Capabilities.
+ *
+ * This data structure is designed to fit within a single word so that it can be
+ * fetched cheaply using a call to driver->GetCapabilities().
+ */
+typedef struct _ARM_STORAGE_CAPABILITIES {
+ uint32_t asynchronous_ops : 1; ///< Used to indicate if APIs like initialize,
+ ///< read, erase, program, etc. can operate in asynchronous mode.
+ ///< Setting this bit to 1 means that the driver is capable
+ ///< of launching asynchronous operations; command completion is
+ ///< signaled by the invocation of a completion callback. If
+ ///< set to 1, drivers may still complete asynchronous
+ ///< operations synchronously as necessary--in which case they
+ ///< return a positive error code to indicate synchronous completion.
+ uint32_t erase_all : 1; ///< Supports EraseAll operation.
+ uint32_t reserved : 30;
+} ARM_STORAGE_CAPABILITIES;
+
+/**
+ * Command opcodes for Storage. Completion callbacks use these codes to refer to
+ * completing commands. Refer to \ref ARM_Storage_Callback_t.
+ */
+typedef enum _ARM_STORAGE_OPERATION {
+ ARM_STORAGE_OPERATION_GET_VERSION,
+ ARM_STORAGE_OPERATION_GET_CAPABILITIES,
+ ARM_STORAGE_OPERATION_INITIALIZE,
+ ARM_STORAGE_OPERATION_UNINITIALIZE,
+ ARM_STORAGE_OPERATION_POWER_CONTROL,
+ ARM_STORAGE_OPERATION_READ_DATA,
+ ARM_STORAGE_OPERATION_PROGRAM_DATA,
+ ARM_STORAGE_OPERATION_ERASE,
+ ARM_STORAGE_OPERATION_ERASE_ALL,
+ ARM_STORAGE_OPERATION_GET_STATUS,
+ ARM_STORAGE_OPERATION_GET_INFO,
+ ARM_STORAGE_OPERATION_RESOLVE_ADDRESS,
+ ARM_STORAGE_OPERATION_GET_NEXT_BLOCK,
+ ARM_STORAGE_OPERATION_GET_BLOCK
+} ARM_STORAGE_OPERATION;
+
+/**
+ * Declaration of the callback-type for command completion.
+ *
+ * @param [in] status
+ * A code to indicate the status of the completed operation. For data
+ * transfer operations, the status field is overloaded in case of
+ * success to return the count of items successfully transferred; this
+ * can be done safely because error codes are negative values.
+ *
+ * @param [in] operation
+ * The command op-code. This value isn't essential for the callback in
+ * the presence of the command instance-id, but it is expected that
+ * this information could be a quick and useful filter.
+ */
+typedef void (*ARM_Storage_Callback_t)(int32_t status, ARM_STORAGE_OPERATION operation);
+
+/**
+ * This is the set of operations constituting the Storage driver. Their
+ * implementation is platform-specific, and needs to be supplied by the
+ * porting effort.
+ *
+ * Some APIs within `ARM_DRIVER_STORAGE` will always operate synchronously:
+ * GetVersion, GetCapabilities, GetStatus, GetInfo, ResolveAddress,
+ * GetNextBlock, and GetBlock. This means that control returns to the caller
+ * with a relevant status code only after the completion of the operation (or
+ * the discovery of a failure condition).
+ *
+ * The remainder of the APIs: Initialize, Uninitialize, PowerControl, ReadData,
+ * ProgramData, Erase, EraseAll, can function asynchronously if the underlying
+ * controller supports it--i.e. if ARM_STORAGE_CAPABILITIES::asynchronous_ops is
+ * set. In the case of asynchronous operation, the invocation returns early
+ * (with ARM_DRIVER_OK) and results in a completion callback later. If
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is not set, then all such APIs
+ * execute synchronously, and control returns to the caller with a status code
+ * only after the completion of the operation (or the discovery of a failure
+ * condition).
+ *
+ * If ARM_STORAGE_CAPABILITIES::asynchronous_ops is set, a storage driver may
+ * still choose to execute asynchronous operations in a synchronous manner. If
+ * so, the driver returns a positive value to indicate successful synchronous
+ * completion (or an error code in case of failure) and no further invocation of
+ * completion callback should be expected. The expected return value for
+ * synchronous completion of such asynchronous operations varies depending on
+ * the operation. For operations involving data access, it often equals the
+ * amount of data transferred or affected. For non data-transfer operations,
+ * such as EraseAll or Initialize, it is usually 1.
+ *
+ * Here's a code snippet to suggest how asynchronous APIs might be used by
+ * callers to handle both synchronous and asynchronous execution by the
+ * underlying storage driver:
+ * \code
+ * ASSERT(ARM_DRIVER_OK == 0); // this is a precondition; it doesn't need to be put in code
+ * int32_t returnValue = drv->asynchronousAPI(...);
+ * if (returnValue < ARM_DRIVER_OK) {
+ * // handle error.
+ * } else if (returnValue == ARM_DRIVER_OK) {
+ * ASSERT(drv->GetCapabilities().asynchronous_ops == 1);
+ * // handle early return from asynchronous execution; remainder of the work is done in the callback handler.
+ * } else {
+ * ASSERT(returnValue == EXPECTED_RETURN_VALUE_FOR_SYNCHRONOUS_COMPLETION);
+ * // handle synchronous completion.
+ * }
+ * \endcode
+ */
+typedef struct _ARM_DRIVER_STORAGE {
+ /**
+ * \brief Get driver version.
+ *
+ * The function GetVersion() returns version information of the driver implementation in ARM_DRIVER_VERSION.
+ *
+ * - API version is the version of the CMSIS-Driver specification used to implement this driver.
+ * - Driver version is source code version of the actual driver implementation.
+ *
+ * Example:
+ * \code
+ * extern ARM_DRIVER_STORAGE *drv_info;
+ *
+ * void read_version (void) {
+ * ARM_DRIVER_VERSION version;
+ *
+ * version = drv_info->GetVersion ();
+ * if (version.api < 0x10A) { // requires at minimum API version 1.10 or higher
+ * // error handling
+ * return;
+ * }
+ * }
+ * \endcode
+ *
+ * @return \ref ARM_DRIVER_VERSION.
+ *
+ * @note This API returns synchronously--it does not result in an invocation
+ * of a completion callback.
+ *
+ * @note The function GetVersion() can be called any time to obtain the
+ * required information from the driver (even before initialization). It
+ * always returns the same information.
+ */
+ ARM_DRIVER_VERSION (*GetVersion)(void);
+
+ /**
+ * \brief Get driver capabilities.
+ *
+ * \details The function GetCapabilities() returns information about
+ * capabilities in this driver implementation. The data fields of the struct
+ * ARM_STORAGE_CAPABILITIES encode various capabilities, for example if the device
+ * is able to execute operations asynchronously.
+ *
+ * Example:
+ * \code
+ * extern ARM_DRIVER_STORAGE *drv_info;
+ *
+ * void read_capabilities (void) {
+ * ARM_STORAGE_CAPABILITIES drv_capabilities;
+ *
+ * drv_capabilities = drv_info->GetCapabilities ();
+ * // interrogate capabilities
+ *
+ * }
+ * \endcode
+ *
+ * @return \ref ARM_STORAGE_CAPABILITIES.
+ *
+ * @note This API returns synchronously--it does not result in an invocation
+ * of a completion callback.
+ *
+ * @note The function GetCapabilities() can be called any time to obtain the
+ * required information from the driver (even before initialization). It
+ * always returns the same information.
+ */
+ ARM_STORAGE_CAPABILITIES (*GetCapabilities)(void);
+
+ /**
+ * \brief Initialize the Storage Interface.
+ *
+ * The function Initialize is called when the middleware component starts
+ * operation. In addition to bringing the controller to a ready state,
+ * Initialize() receives a callback handler to be invoked upon completion of
+ * asynchronous operations.
+ *
+ * Initialize() needs to be called explicitly before
+ * powering the peripheral using PowerControl(), and before initiating other
+ * accesses to the storage controller.
+ *
+ * The function performs the following operations:
+ * - Initializes the resources needed for the Storage interface.
+ * - Registers the \ref ARM_Storage_Callback_t callback function.
+ *
+ * To start working with a peripheral the functions Initialize and PowerControl need to be called in this order:
+ * drv->Initialize (...); // Allocate I/O pins
+ * drv->PowerControl (ARM_POWER_FULL); // Power up peripheral, setup IRQ/DMA
+ *
+ * - Initialize() typically allocates the I/O resources (pins) for the
+ * peripheral. The function can be called multiple times; if the I/O resources
+ * are already initialized it performs no operation and just returns with
+ * ARM_DRIVER_OK.
+ *
+ * - PowerControl (ARM_POWER_FULL) sets the peripheral registers including
+ * interrupt (NVIC) and optionally DMA. The function can be called multiple
+ * times; if the registers are already set it performs no operation and just
+ * returns with ARM_DRIVER_OK.
+ *
+ * To stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:
+ * drv->PowerControl (ARM_POWER_OFF); // Terminate any pending transfers, reset IRQ/DMA, power off peripheral
+ * drv->Uninitialize (...); // Release I/O pins
+ *
+ * The functions PowerControl and Uninitialize always execute and can be used
+ * to put the peripheral into a Safe State, for example after any data
+ * transmission errors. To restart the peripheral in an error condition,
+ * you should first execute the Stop Sequence and then the Start Sequence.
+ *
+ * @param [in] callback
+ * Caller-defined callback to be invoked upon command completion
+ * for asynchronous APIs (including the completion of
+ * initialization). Use a NULL pointer when no callback
+ * signals are required.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with a status value of ARM_DRIVER_OK or an error-code. In the
+ * case of synchronous execution, control returns after completion with a
+ * value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+ */
+ int32_t (*Initialize)(ARM_Storage_Callback_t callback);
+
+ /**
+ * \brief De-initialize the Storage Interface.
+ *
+ * The function Uninitialize() de-initializes the resources of Storage interface.
+ *
+ * It is called when the middleware component stops operation, and wishes to
+ * release the software resources used by the interface.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with a status value of ARM_DRIVER_OK or an error-code. In the
+ * case of synchronous execution, control returns after completion with a
+ * value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+ */
+ int32_t (*Uninitialize)(void);
+
+ /**
+ * \brief Control the Storage interface power.
+ *
+ * The function \b ARM_Storage_PowerControl operates the power modes of the Storage interface.
+ *
+ * To start working with a peripheral the functions Initialize and PowerControl need to be called in this order:
+ * drv->Initialize (...); // Allocate I/O pins
+ * drv->PowerControl (ARM_POWER_FULL); // Power up peripheral, setup IRQ/DMA
+ *
+ * - Initialize() typically allocates the I/O resources (pins) for the
+ * peripheral. The function can be called multiple times; if the I/O resources
+ * are already initialized it performs no operation and just returns with
+ * ARM_DRIVER_OK.
+ *
+ * - PowerControl (ARM_POWER_FULL) sets the peripheral registers including
+ * interrupt (NVIC) and optionally DMA. The function can be called multiple
+ * times; if the registers are already set it performs no operation and just
+ * returns with ARM_DRIVER_OK.
+ *
+ * To stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:
+ *
+ * drv->PowerControl (ARM_POWER_OFF); // Terminate any pending transfers, reset IRQ/DMA, power off peripheral
+ * drv->Uninitialize (...); // Release I/O pins
+ *
+ * The functions PowerControl and Uninitialize always execute and can be used
+ * to put the peripheral into a Safe State, for example after any data
+ * transmission errors. To restart the peripheral in an error condition,
+ * you should first execute the Stop Sequence and then the Start Sequence.
+ *
+ * @param state
+ * \ref ARM_POWER_STATE. The target power-state for the storage controller.
+ * The parameter state can have the following values:
+ * - ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts
+ * (NVIC) and optionally DMA. Can be called multiple times. If the peripheral
+ * is already in this mode, then the function performs no operation and returns
+ * with ARM_DRIVER_OK.
+ * - ARM_POWER_LOW : may use power saving. Returns ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.
+ * - ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with a status value of ARM_DRIVER_OK or an error-code. In the
+ * case of synchronous execution, control returns after completion with a
+ * value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+ */
+ int32_t (*PowerControl)(ARM_POWER_STATE state);
+
+ /**
+ * \brief read the contents of a given address range from the storage device.
+ *
+ * \details Read the contents of a range of storage memory into a buffer
+ * supplied by the caller. The buffer is owned by the caller and should
+ * remain accessible for the lifetime of this command.
+ *
+ * @param [in] addr
+ * This specifies the address from where to read data.
+ *
+ * @param [out] data
+ * The destination of the read operation. The buffer
+ * is owned by the caller and should remain accessible for the
+ * lifetime of this command.
+ *
+ * @param [in] size
+ * The number of bytes requested to read. The data buffer
+ * should be at least as large as this size.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with the number of successfully transferred bytes passed in as
+ * the 'status' parameter. In the case of synchronous execution, control
+ * returns after completion with a positive transfer-count. Return values
+ * less than ARM_DRIVER_OK (0) signify errors.
+ */
+ int32_t (*ReadData)(uint64_t addr, void *data, uint32_t size);
+
+ /**
+ * \brief program (write into) the contents of a given address range of the storage device.
+ *
+ * \details Write the contents of a given memory buffer into a range of
+ * storage memory. In the case of flash memory, the destination range in
+ * storage memory typically has its contents in an erased state from a
+ * preceding erase operation. The source memory buffer is owned by the
+ * caller and should remain accessible for the lifetime of this command.
+ *
+ * @param [in] addr
+ * This is the start address of the range to be written into. It
+ * needs to be aligned to the device's \em program_unit
+ * specified in \ref ARM_STORAGE_INFO.
+ *
+ * @param [in] data
+ * The source of the write operation. The buffer is owned by the
+ * caller and should remain accessible for the lifetime of this
+ * command.
+ *
+ * @param [in] size
+ * The number of bytes requested to be written. The buffer
+ * should be at least as large as this size. \note 'size' should
+ * be a multiple of the device's 'program_unit' (see \ref
+ * ARM_STORAGE_INFO).
+ *
+ * @note It is best for the middleware to write in units of
+ * 'optimal_program_unit' (\ref ARM_STORAGE_INFO) of the device.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with the number of successfully transferred bytes passed in as
+ * the 'status' parameter. In the case of synchronous execution, control
+ * returns after completion with a positive transfer-count. Return values
+ * less than ARM_DRIVER_OK (0) signify errors.
+ */
+ int32_t (*ProgramData)(uint64_t addr, const void *data, uint32_t size);
+
+ /**
+ * @brief Erase Storage range.
+ *
+ * @details This function erases a range of storage specified by [addr, addr +
+ * size). Both 'addr' and 'addr + size' should align with the
+ * 'erase_unit'(s) of the respective owning storage block(s) (see \ref
+ * ARM_STORAGE_BLOCK and \ref ARM_STORAGE_BLOCK_ATTRIBUTES). The range to
+ * be erased will have its contents returned to the un-programmed state--
+ * i.e. to 'erased_value' (see \ref ARM_STORAGE_BLOCK_ATTRIBUTES), which
+ * is usually 1 to indicate the pattern of all ones: 0xFF.
+ *
+ * @param [in] addr
+ * This is the start-address of the range to be erased. It must
+ * start at an 'erase_unit' boundary of the underlying block.
+ *
+ * @param [in] size
+ * Size (in bytes) of the range to be erased. 'addr + size'
+ * must be aligned with the 'erase_unit' of the underlying
+ * block.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return
+ * If the range to be erased doesn't align with the erase_units of the
+ * respective start and end blocks, ARM_DRIVER_ERROR_PARAMETER is returned.
+ * If any part of the range is protected, ARM_STORAGE_ERROR_PROTECTED is
+ * returned. If any part of the range is not erasable,
+ * ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All such sanity-check
+ * failures result in the error code being returned synchronously and the
+ * storage bytes within the range remain unaffected.
+ * Otherwise the function executes in the following ways:
+ * If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with the number of successfully erased bytes passed in as
+ * the 'status' parameter. In the case of synchronous execution, control
+ * returns after completion with a positive erase-count. Return values
+ * less than ARM_DRIVER_OK (0) signify errors.
+ *
+ * @note Erase() may return a smaller (positive) value than the size of the
+ * requested range. The returned value indicates the actual number of bytes
+ * erased. It is the caller's responsibility to follow up with an appropriate
+ * request to complete the operation.
+ *
+ * @note in the case of a failed erase (except when
+ * ARM_DRIVER_ERROR_PARAMETER, ARM_STORAGE_ERROR_PROTECTED, or
+ * ARM_STORAGE_ERROR_NOT_ERASABLE is returned synchronously), the
+ * requested range should be assumed to be in an unknown state. The
+ * previous contents may not be retained.
+ */
+ int32_t (*Erase)(uint64_t addr, uint32_t size);
+
+ /**
+ * @brief Erase complete storage. Optional function for faster erase of the complete device.
+ *
+ * This optional function erases the complete device. If the device does not
+ * support global erase then the function returns the error value \ref
+ * ARM_DRIVER_ERROR_UNSUPPORTED. The data field \em 'erase_all' =
+ * \token{1} of the structure \ref ARM_STORAGE_CAPABILITIES encodes that
+ * \ref ARM_STORAGE_EraseAll is supported.
+ *
+ * @note This API may execute asynchronously if
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+ * execution is optional even if 'asynchronous_ops' is set.
+ *
+ * @return
+ * If any part of the storage range is protected,
+ * ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the storage
+ * range is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All
+ * such sanity-check failures result in the error code being returned
+ * synchronously and the storage bytes within the range remain unaffected.
+ * Otherwise the function executes in the following ways:
+ * If asynchronous activity is launched, an invocation returns
+ * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+ * future with ARM_DRIVER_OK passed in as the 'status' parameter. In the
+ * case of synchronous execution, control returns after completion with a
+ * value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+ */
+ int32_t (*EraseAll)(void);
+
+ /**
+ * @brief Get the status of the current (or previous) command executed by the
+ * storage controller; stored in the structure \ref ARM_STORAGE_STATUS.
+ *
+ * @return
+ * The status of the underlying controller.
+ *
+ * @note This API returns synchronously--it does not result in an invocation
+ * of a completion callback.
+ */
+ ARM_STORAGE_STATUS (*GetStatus)(void);
+
+ /**
+ * @brief Get information about the Storage device; stored in the structure \ref ARM_STORAGE_INFO.
+ *
+ * @param [out] info
+ * A caller-supplied buffer capable of being filled in with an
+ * \ref ARM_STORAGE_INFO.
+ *
+ * @return ARM_DRIVER_OK if a ARM_STORAGE_INFO structure containing top level
+ * metadata about the storage controller is filled into the supplied
+ * buffer, else an appropriate error value.
+ *
+ * @note It is the caller's responsibility to ensure that the buffer passed in
+ * is able to be initialized with a \ref ARM_STORAGE_INFO.
+ *
+ * @note This API returns synchronously--it does not result in an invocation
+ * of a completion callback.
+ */
+ int32_t (*GetInfo)(ARM_STORAGE_INFO *info);
+
+ /**
+ * \brief For memory-mapped storage, resolve an address relative to
+ * the storage controller into a memory address.
+ *
+ * @param addr
+ * This is the address for which we want a resolution to the
+ * processor's physical address space. It is an offset from the
+ * start of the storage map maintained by the owning storage
+ * controller.
+ *
+ * @return
+ * The resolved address in the processor's address space; else
+ * ARM_STORAGE_INVALID_ADDRESS, if no resolution is possible.
+ *
+ * @note This API returns synchronously. The invocation should return quickly,
+ * and result in a resolved address.
+ */
+ uint32_t (*ResolveAddress)(uint64_t addr);
+
+ /**
+ * @brief Advance to the successor of the current block (iterator), or fetch
+ * the first block (if 'prev_block' is passed in as NULL).
+ *
+ * @details This helper function fetches (an iterator to) the next block (or
+ * the first block if 'prev_block' is passed in as NULL). In the failure
+ * case, a terminating, invalid block iterator is filled into the out
+ * parameter: 'next_block'. In combination with \ref
+ * ARM_STORAGE_VALID_BLOCK(), it can be used to iterate over the sequence
+ * of blocks within the storage map:
+ *
+ * \code
+ * ARM_STORAGE_BLOCK block;
+ * for (drv->GetNextBlock(NULL, &block); ARM_STORAGE_VALID_BLOCK(&block); drv->GetNextBlock(&block, &block)) {
+ * // make use of block
+ * }
+ * \endcode
+ *
+ * @param[in] prev_block
+ * An existing block (iterator) within the same storage
+ * controller. The memory buffer holding this block is owned
+ * by the caller. This pointer may be NULL; if so, the
+ * invocation fills in the first block into the out parameter:
+ * 'next_block'.
+ *
+ * @param[out] next_block
+ * A caller-owned buffer large enough to be filled in with
+ * the following ARM_STORAGE_BLOCK. It is legal to provide the
+ * same buffer using 'next_block' as was passed in with 'prev_block'. It
+ * is also legal to pass a NULL into this parameter if the
+ * caller isn't interested in populating a buffer with the next
+ * block--i.e. if the caller only wishes to establish the
+ * presence of a next block.
+ *
+ * @return ARM_DRIVER_OK if a valid next block is found (or first block, if
+ * prev_block is passed as NULL); upon successful operation, the contents
+ * of the next (or first) block are filled into the buffer pointed to by
+ * the parameter 'next_block' and ARM_STORAGE_VALID_BLOCK(next_block) is
+ * guaranteed to be true. Upon reaching the end of the sequence of blocks
+ * (iterators), or in case the driver is unable to fetch information about
+ * the next (or first) block, an error (negative) value is returned and an
+ * invalid StorageBlock is populated into the supplied buffer. If
+ * prev_block is NULL, the first block is returned.
+ *
+ * @note This API returns synchronously--it does not result in an invocation
+ * of a completion callback.
+ */
+ int32_t (*GetNextBlock)(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block);
+
+ /**
+ * @brief Find the storage block (iterator) encompassing a given storage address.
+ *
+ * @param[in] addr
+ * Storage address in bytes.
+ *
+ * @param[out] block
+ * A caller-owned buffer large enough to be filled in with the
+ * ARM_STORAGE_BLOCK encapsulating the given address. This value
+ * can also be passed in as NULL if the caller isn't interested
+ * in populating a buffer with the block--if the caller only
+ * wishes to establish the presence of a containing storage
+ * block.
+ *
+ * @return ARM_DRIVER_OK if a containing storage-block is found. In this case,
+ * if block is non-NULL, the buffer pointed to by it is populated with
+ * the contents of the storage block--i.e. if block is valid and a block is
+ * found, ARM_STORAGE_VALID_BLOCK(block) would return true following this
+ * call. If there is no storage block containing the given offset, or in
+ * case the driver is unable to resolve an address to a storage-block, an
+ * error (negative) value is returned and an invalid StorageBlock is
+ * populated into the supplied buffer.
+ *
+ * @note This API returns synchronously--it does not result in an invocation
+ * of a completion callback.
+ */
+ int32_t (*GetBlock)(uint64_t addr, ARM_STORAGE_BLOCK *block);
+} const ARM_DRIVER_STORAGE;
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif /* __DRIVER_STORAGE_H */
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/ticker_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,180 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_API_H
+#define MBED_TICKER_API_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "device.h"
+
+/**
+ * Maximum delta (in us) between too interrupts.
+ */
+#define MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA 0x70000000ULL
+
+/**
+ * Legacy format representing a timestamp in us.
+ * Given it is modeled as a 32 bit integer, this type can represent timestamp
+ * up to 4294 seconds (71 minutes).
+ * Prefer using us_timestamp_t which store timestamp as 64 bits integer.
+ */
+typedef uint32_t timestamp_t;
+
+/**
+ * A us timestamp stored in a 64 bit integer.
+ * Can store timestamp up to 584810 years.
+ */
+typedef uint64_t us_timestamp_t;
+
+/** Ticker's event structure
+ */
+typedef struct ticker_event_s {
+ us_timestamp_t timestamp; /**< Event's timestamp */
+ uint32_t id; /**< TimerEvent object */
+ struct ticker_event_s *next; /**< Next event in the queue */
+} ticker_event_t;
+
+typedef void (*ticker_event_handler)(uint32_t id);
+
+/** Ticker's interface structure - required API for a ticker
+ */
+typedef struct {
+ void (*init)(void); /**< Init function */
+ uint32_t (*read)(void); /**< Read function */
+ void (*disable_interrupt)(void); /**< Disable interrupt function */
+ void (*clear_interrupt)(void); /**< Clear interrupt function */
+ void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
+} ticker_interface_t;
+
+/** Ticker's event queue structure
+ */
+typedef struct {
+ ticker_event_handler event_handler; /**< Event handler */
+ ticker_event_t *head; /**< A pointer to head */
+ us_timestamp_t present_time; /**< Store the timestamp used for present time */
+ bool initialized; /**< Indicate if the instance is initialized */
+} ticker_event_queue_t;
+
+/** Ticker's data structure
+ */
+typedef struct {
+ const ticker_interface_t *interface; /**< Ticker's interface */
+ ticker_event_queue_t *queue; /**< Ticker's event queue */
+} ticker_data_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_ticker Ticker HAL functions
+ * @{
+ */
+
+/** Initialize a ticker and set the event handler
+ *
+ * @param ticker The ticker object.
+ * @param handler A handler to be set
+ */
+void ticker_set_handler(const ticker_data_t *const ticker, ticker_event_handler handler);
+
+/** IRQ handler that goes through the events to trigger overdue events.
+ *
+ * @param ticker The ticker object.
+ */
+void ticker_irq_handler(const ticker_data_t *const ticker);
+
+/** Remove an event from the queue
+ *
+ * @param ticker The ticker object.
+ * @param obj The event object to be removed from the queue
+ */
+void ticker_remove_event(const ticker_data_t *const ticker, ticker_event_t *obj);
+
+/** Insert an event to the queue
+ *
+ * The event will be executed in timestamp - ticker_read().
+ *
+ * @warning This function does not consider timestamp in the past. If an event
+ * is inserted with a timestamp less than the current timestamp then the event
+ * will be executed in timestamp - ticker_read() us.
+ * The internal counter wrap very quickly it is hard to decide weither an
+ * event is in the past or in 1 hour.
+ *
+ * @note prefer the use of ticker_insert_event_us which allows registration of
+ * absolute timestamp.
+ *
+ * @param ticker The ticker object.
+ * @param obj The event object to be inserted to the queue
+ * @param timestamp The event's timestamp
+ * @param id The event object
+ */
+void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
+
+/** Insert an event to the queue
+ *
+ * The event will be executed in timestamp - ticker_read_us() us.
+ *
+ * @warning If an event is inserted with a timestamp less than the current
+ * timestamp then the event will **not** be inserted.
+ *
+ * @param ticker The ticker object.
+ * @param obj The event object to be inserted to the queue
+ * @param timestamp The event's timestamp
+ * @param id The event object
+ */
+void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id);
+
+/** Read the current (relative) ticker's timestamp
+ *
+ * @warning Return a relative timestamp because the counter wrap every 4294
+ * seconds.
+ *
+ * @param ticker The ticker object.
+ * @return The current timestamp
+ */
+timestamp_t ticker_read(const ticker_data_t *const ticker);
+
+/** Read the current (absolute) ticker's timestamp
+ *
+ * @warning Return an absolute timestamp counting from the initialization of the
+ * ticker.
+ *
+ * @param ticker The ticker object.
+ * @return The current timestamp
+ */
+us_timestamp_t ticker_read_us(const ticker_data_t *const ticker);
+
+/** Read the next event's timestamp
+ *
+ * @param ticker The ticker object.
+ * @return 1 if timestamp is pending event, 0 if there's no event pending
+ */
+int ticker_get_next_timestamp(const ticker_data_t *const ticker, timestamp_t *timestamp);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/trng_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,73 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TRNG_API_H
+#define MBED_TRNG_API_H
+
+#include <stddef.h>
+#include "device.h"
+
+#if DEVICE_TRNG
+
+/** TRNG HAL structure. trng_s is declared in the target's HAL
+ */
+typedef struct trng_s trng_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_trng TRNG hal functions
+ * @{
+ */
+
+/** Initialize the TRNG peripheral
+ *
+ * @param obj The TRNG object
+ */
+void trng_init(trng_t *obj);
+
+/** Deinitialize the TRNG peripheral
+ *
+ * @param obj The TRNG object
+ */
+void trng_free(trng_t *obj);
+
+/** Get random data from TRNG peripheral
+ *
+ * @param obj The TRNG object
+ * @param output The pointer to an output array
+ * @param length The size of output data, to avoid buffer overwrite
+ * @param output_length The length of generated data
+ * @return 0 success, -1 fail
+ */
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/us_ticker_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,84 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_US_TICKER_API_H
+#define MBED_US_TICKER_API_H
+
+#include <stdint.h>
+#include "hal/ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_UsTicker Microseconds Ticker Functions
+ * @{
+ */
+
+/** Get ticker's data
+ *
+ * @return The low power ticker data
+ */
+const ticker_data_t* get_us_ticker_data(void);
+
+
+/** The wrapper for ticker_irq_handler, to pass us ticker's data
+ *
+ */
+void us_ticker_irq_handler(void);
+
+/* HAL us ticker */
+
+/** Initialize the ticker
+ *
+ */
+void us_ticker_init(void);
+
+/** Read the current counter
+ *
+ * @return The current timer's counter value in microseconds
+ */
+uint32_t us_ticker_read(void);
+
+/** Set interrupt for specified timestamp
+ *
+ * @param timestamp The time in microseconds to be set
+ */
+void us_ticker_set_interrupt(timestamp_t timestamp);
+
+/** Disable us ticker interrupt
+ *
+ */
+void us_ticker_disable_interrupt(void);
+
+/** Clear us ticker interrupt
+ *
+ */
+void us_ticker_clear_interrupt(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/CThunk.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,247 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* General C++ Object Thunking class
+ *
+ * - allows direct callbacks to non-static C++ class functions
+ * - keeps track for the corresponding class instance
+ * - supports an optional context parameter for the called function
+ * - ideally suited for class object receiving interrupts (NVIC_SetVector)
+ *
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* General C++ Object Thunking class
+ *
+ * - allows direct callbacks to non-static C++ class functions
+ * - keeps track for the corresponding class instance
+ * - supports an optional context parameter for the called function
+ * - ideally suited for class object receiving interrupts (NVIC_SetVector)
+ */
+
+#ifndef __CTHUNK_H__
+#define __CTHUNK_H__
+
+#define CTHUNK_ADDRESS 1
+#define CTHUNK_VARIABLES volatile uint32_t code[2]
+
+#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7) || defined(__CORTEX_A9))
+/**
+* CTHUNK disassembly for Cortex-M3/M4/M7/A9 (thumb2):
+* * adr r0, #4
+* * ldm r0, {r0, r1, r2, pc}
+*
+* This instruction loads the arguments for the static thunking function to r0-r2, and
+* branches to that function by loading its address into PC.
+*
+* This is safe for both regular calling and interrupt calling, since it only touches scratch registers
+* which should be saved by the caller, and are automatically saved as part of the IRQ context switch.
+*/
+#define CTHUNK_ASSIGMENT do { \
+ m_thunk.code[0] = 0xE890A001; \
+ m_thunk.code[1] = 0x00008007; \
+ } while (0)
+
+#elif (defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0))
+/*
+* CTHUNK disassembly for Cortex M0/M0+ (thumb):
+* * adr r0, #4
+* * ldm r0, {r0, r1, r2, r3}
+* * bx r3
+*/
+#define CTHUNK_ASSIGMENT do { \
+ m_thunk.code[0] = 0xC80FA001; \
+ m_thunk.code[1] = 0x00004718; \
+ } while (0)
+
+#else
+#error "Target is not currently suported."
+#endif
+
+/* IRQ/Exception compatible thunk entry function */
+typedef void (*CThunkEntry)(void);
+/** @}*/
+
+/**
+ * Class for created a pointer with data bound to it
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template<class T>
+class CThunk
+{
+ public:
+ typedef void (T::*CCallbackSimple)(void);
+ typedef void (T::*CCallback)(void* context);
+
+ inline CThunk(T *instance)
+ {
+ init(instance, NULL, NULL);
+ }
+
+ inline CThunk(T *instance, CCallback callback)
+ {
+ init(instance, callback, NULL);
+ }
+
+ ~CThunk() {
+
+ }
+
+ inline CThunk(T *instance, CCallbackSimple callback)
+ {
+ init(instance, (CCallback)callback, NULL);
+ }
+
+ inline CThunk(T &instance, CCallback callback)
+ {
+ init(instance, callback, NULL);
+ }
+
+ inline CThunk(T &instance, CCallbackSimple callback)
+ {
+ init(instance, (CCallback)callback, NULL);
+ }
+
+ inline CThunk(T &instance, CCallback callback, void* context)
+ {
+ init(instance, callback, context);
+ }
+
+ inline void callback(CCallback callback)
+ {
+ m_callback = callback;
+ }
+
+ inline void callback(CCallbackSimple callback)
+ {
+ m_callback = (CCallback)callback;
+ }
+
+ inline void context(void* context)
+ {
+ m_thunk.context = (uint32_t)context;
+ }
+
+ inline void context(uint32_t context)
+ {
+ m_thunk.context = context;
+ }
+
+ inline uint32_t entry(void)
+ {
+ return (((uint32_t)&m_thunk)|CTHUNK_ADDRESS);
+ }
+
+ /* get thunk entry point for connecting rhunk to an IRQ table */
+ inline operator CThunkEntry(void)
+ {
+ return (CThunkEntry)entry();
+ }
+
+ /* get thunk entry point for connecting rhunk to an IRQ table */
+ inline operator uint32_t(void)
+ {
+ return entry();
+ }
+
+ /* simple test function */
+ inline void call(void)
+ {
+ (((CThunkEntry)(entry()))());
+ }
+
+ private:
+ T* m_instance;
+ volatile CCallback m_callback;
+
+// TODO: this needs proper fix, to refactor toolchain header file and all its use
+// PACKED there is not defined properly for IAR
+#if defined (__ICCARM__)
+ typedef __packed struct
+ {
+ CTHUNK_VARIABLES;
+ volatile uint32_t instance;
+ volatile uint32_t context;
+ volatile uint32_t callback;
+ volatile uint32_t trampoline;
+ } CThunkTrampoline;
+#else
+ typedef struct
+ {
+ CTHUNK_VARIABLES;
+ volatile uint32_t instance;
+ volatile uint32_t context;
+ volatile uint32_t callback;
+ volatile uint32_t trampoline;
+ } __attribute__((__packed__)) CThunkTrampoline;
+#endif
+
+ static void trampoline(T* instance, void* context, CCallback* callback)
+ {
+ if(instance && *callback) {
+ (static_cast<T*>(instance)->**callback)(context);
+ }
+ }
+
+ volatile CThunkTrampoline m_thunk;
+
+ inline void init(T *instance, CCallback callback, void* context)
+ {
+ /* remember callback - need to add this level of redirection
+ as pointer size for member functions differs between platforms */
+ m_callback = callback;
+
+ /* populate thunking trampoline */
+ CTHUNK_ASSIGMENT;
+ m_thunk.context = (uint32_t)context;
+ m_thunk.instance = (uint32_t)instance;
+ m_thunk.callback = (uint32_t)&m_callback;
+ m_thunk.trampoline = (uint32_t)&trampoline;
+
+#if defined(__CORTEX_A9)
+ /* Data cache clean */
+ /* Cache control */
+ {
+ uint32_t start_addr = (uint32_t)&m_thunk & 0xFFFFFFE0;
+ uint32_t end_addr = (uint32_t)&m_thunk + sizeof(m_thunk);
+ uint32_t addr;
+
+ /* Data cache clean and invalid */
+ for (addr = start_addr; addr < end_addr; addr += 0x20) {
+ __v7_clean_inv_dcache_mva((void *)addr);
+ }
+ /* Instruction cache invalid */
+ __v7_inv_icache_all();
+ __ca9u_inv_tlb_all();
+ __v7_inv_btac();
+ }
+#endif
+#if defined(__CORTEX_M7)
+ /* Data cache clean and invalid */
+ SCB_CleanInvalidateDCache();
+
+ /* Instruction cache invalid */
+ SCB_InvalidateICache();
+#endif
+ __ISB();
+ __DSB();
+ }
+};
+
+#endif/*__CTHUNK_H__*/
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/CallChain.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,117 @@
+#include "platform/CallChain.h"
+#include "cmsis.h"
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+
+class CallChainLink {
+public:
+ CallChainLink(): cb(), next(NULL) {
+ // No work to do
+ }
+
+ CallChainLink(Callback<void()> &callback): cb(callback), next(NULL) {
+ // No work to do
+ }
+ Callback<void()> cb;
+ CallChainLink * next;
+};
+
+CallChain::CallChain(int size) : _chain(NULL) {
+ // No work to do
+}
+
+CallChain::~CallChain() {
+ clear();
+}
+
+pFunctionPointer_t CallChain::add(Callback<void()> func) {
+ CallChainLink *new_link = new CallChainLink(func);
+ if (NULL == _chain) {
+ _chain = new_link;
+ return &new_link->cb;
+ }
+
+ CallChainLink *link = _chain;
+ while (true) {
+ if (NULL == link->next) {
+ link->next = new_link;
+ return &new_link->cb;
+ }
+ link = link->next;
+ }
+}
+
+pFunctionPointer_t CallChain::add_front(Callback<void()> func) {
+ CallChainLink *link = new CallChainLink(func);
+ link->next = _chain;
+ _chain = link;
+ return &link->cb;
+}
+
+int CallChain::size() const {
+ CallChainLink *link = _chain;
+ int elements = 0;
+ while (link != NULL) {
+ elements++;
+ link = link->next;
+ }
+ return elements;
+}
+
+pFunctionPointer_t CallChain::get(int idx) const {
+ CallChainLink *link = _chain;
+ for (int i = 0; i < idx; i++) {
+ if (NULL == link) {
+ break;
+ }
+ link = link->next;
+ }
+ return &link->cb;
+}
+
+int CallChain::find(pFunctionPointer_t f) const {
+ CallChainLink *link = _chain;
+ int i = 0;
+ while (link != NULL) {
+ if (f == &link->cb) {
+ return i;
+ }
+ i++;
+ link = link->next;
+ }
+ return -1;
+}
+
+void CallChain::clear() {
+ CallChainLink *link = _chain;
+ _chain = NULL;
+ while (link != NULL) {
+ CallChainLink *temp = link->next;
+ delete link;
+ link = temp;
+ }
+}
+
+bool CallChain::remove(pFunctionPointer_t f) {
+ CallChainLink *link = _chain;
+ while (link != NULL) {
+ if (f == &link->cb) {
+ delete link;
+ return true;
+ }
+ link = link->next;
+ }
+ return false;
+}
+
+void CallChain::call() {
+ CallChainLink *link = _chain;
+ while (link != NULL) {
+ link->cb.call();
+ link = link->next;
+ }
+}
+
+} // namespace mbed
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/CallChain.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,192 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLCHAIN_H
+#define MBED_CALLCHAIN_H
+
+#include "platform/Callback.h"
+#include "platform/mbed_toolchain.h"
+#include <string.h>
+
+namespace mbed {
+/** \addtogroup platform */
+
+/** Group one or more functions in an instance of a CallChain, then call them in
+ * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
+ * but can be used for other purposes.
+ *
+ * @note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * CallChain chain;
+ *
+ * void first(void) {
+ * printf("'first' function.\n");
+ * }
+ *
+ * void second(void) {
+ * printf("'second' function.\n");
+ * }
+ *
+ * class Test {
+ * public:
+ * void f(void) {
+ * printf("A::f (class member).\n");
+ * }
+ * };
+ *
+ * int main() {
+ * Test test;
+ *
+ * chain.add(second);
+ * chain.add_front(first);
+ * chain.add(&test, &Test::f);
+ * chain.call();
+ * }
+ * @endcode
+ * @ingroup platform
+ */
+
+typedef Callback<void()> *pFunctionPointer_t;
+class CallChainLink;
+
+class CallChain {
+public:
+ /** Create an empty chain
+ *
+ * @param size (optional) Initial size of the chain
+ */
+ CallChain(int size = 4);
+ virtual ~CallChain();
+
+ /** Add a function at the end of the chain
+ *
+ * @param func A pointer to a void function
+ *
+ * @returns
+ * The function object created for 'func'
+ */
+ pFunctionPointer_t add(Callback<void()> func);
+
+ /** Add a function at the end of the chain
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'obj' and 'method'
+ *
+ * @deprecated
+ * The add function does not support cv-qualifiers. Replaced by
+ * add(callback(obj, method)).
+ */
+ template<typename T, typename M>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The add function does not support cv-qualifiers. Replaced by "
+ "add(callback(obj, method)).")
+ pFunctionPointer_t add(T *obj, M method) {
+ return add(callback(obj, method));
+ }
+
+ /** Add a function at the beginning of the chain
+ *
+ * @param func A pointer to a void function
+ *
+ * @returns
+ * The function object created for 'func'
+ */
+ pFunctionPointer_t add_front(Callback<void()> func);
+
+ /** Add a function at the beginning of the chain
+ *
+ * @param obj pointer to the object to call the member function on
+ * @param method pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ *
+ * @deprecated
+ * The add_front function does not support cv-qualifiers. Replaced by
+ * add_front(callback(obj, method)).
+ */
+ template<typename T, typename M>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "The add_front function does not support cv-qualifiers. Replaced by "
+ "add_front(callback(obj, method)).")
+ pFunctionPointer_t add_front(T *obj, M method) {
+ return add_front(callback(obj, method));
+ }
+
+ /** Get the number of functions in the chain
+ */
+ int size() const;
+
+ /** Get a function object from the chain
+ *
+ * @param i function object index
+ *
+ * @returns
+ * The function object at position 'i' in the chain
+ */
+ pFunctionPointer_t get(int i) const;
+
+ /** Look for a function object in the call chain
+ *
+ * @param f the function object to search
+ *
+ * @returns
+ * The index of the function object if found, -1 otherwise.
+ */
+ int find(pFunctionPointer_t f) const;
+
+ /** Clear the call chain (remove all functions in the chain).
+ */
+ void clear();
+
+ /** Remove a function object from the chain
+ *
+ * @arg f the function object to remove
+ *
+ * @returns
+ * true if the function object was found and removed, false otherwise.
+ */
+ bool remove(pFunctionPointer_t f);
+
+ /** Call all the functions in the chain in sequence
+ */
+ void call();
+
+ void operator ()(void) {
+ call();
+ }
+ pFunctionPointer_t operator [](int i) const {
+ return get(i);
+ }
+
+ /* disallow copy constructor and assignment operators */
+private:
+ CallChain(const CallChain&);
+ CallChain & operator = (const CallChain&);
+ CallChainLink *_chain;
+};
+
+} // namespace mbed
+
+#endif
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/Callback.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,4547 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLBACK_H
+#define MBED_CALLBACK_H
+
+#include <string.h>
+#include <stdint.h>
+#include <new>
+#include "platform/mbed_assert.h"
+#include "platform/mbed_toolchain.h"
+
+namespace mbed {
+/** \addtogroup platform */
+
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename F>
+class Callback;
+
+// Internal sfinae declarations
+//
+// These are used to eliminate overloads based on type attributes
+// 1. Does a function object have a call operator
+// 2. Does a function object fit in the available storage
+//
+// These eliminations are handled cleanly by the compiler and avoid
+// massive and misleading error messages when confronted with an
+// invalid type (or worse, runtime failures)
+namespace detail {
+ struct nil {};
+
+ template <bool B, typename R = nil>
+ struct enable_if { typedef R type; };
+
+ template <typename R>
+ struct enable_if<false, R> {};
+
+ template <typename M, M>
+ struct is_type {
+ static const bool value = true;
+ };
+}
+
+#define MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M) \
+ typename detail::enable_if< \
+ detail::is_type<M, &F::operator()>::value && \
+ sizeof(F) <= sizeof(uintptr_t) \
+ >::type = detail::nil()
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename R>
+class Callback<R()> {
+public:
+ /** Create a Callback with a static function
+ * @param func Static function to attach
+ */
+ Callback(R (*func)() = 0) {
+ if (!func) {
+ _ops = 0;
+ } else {
+ generate(func);
+ }
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ */
+ Callback(const Callback<R()> &func) {
+ if (func._ops) {
+ func._ops->move(this, &func);
+ }
+ _ops = func._ops;
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(U *obj, R (T::*method)()) {
+ generate(method_context<T, R (T::*)()>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const U *obj, R (T::*method)() const) {
+ generate(method_context<const T, R (T::*)() const>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(volatile U *obj, R (T::*method)() volatile) {
+ generate(method_context<volatile T, R (T::*)() volatile>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const volatile U *obj, R (T::*method)() const volatile) {
+ generate(method_context<const volatile T, R (T::*)() const volatile>(obj, method));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(T*), U *arg) {
+ generate(function_context<R (*)(T*), T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(const T*), const U *arg) {
+ generate(function_context<R (*)(const T*), const T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(volatile T*), volatile U *arg) {
+ generate(function_context<R (*)(volatile T*), volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(const volatile T*), const volatile U *arg) {
+ generate(function_context<R (*)(const volatile T*), const volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)())) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)() const)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)() volatile)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)() const volatile)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(U *obj, R (*func)(T*)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const U *obj, R (*func)(const T*)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(volatile U *obj, R (*func)(volatile T*)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const volatile U *obj, R (*func)(const volatile T*)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Destroy a callback
+ */
+ ~Callback() {
+ if (_ops) {
+ _ops->dtor(this);
+ }
+ }
+
+ /** Attach a static function
+ * @param func Static function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)()) {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const Callback<R()> &func) {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(U *obj, R (T::*method)()) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const U *obj, R (T::*method)() const) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile U *obj, R (T::*method)() volatile) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile U *obj, R (T::*method)() const volatile) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(T*), U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(const T*), const U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(volatile T*), volatile U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(const volatile T*), const volatile U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)())) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)() const)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)() volatile)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)() const volatile)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(U *obj, R (*func)(T*)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const U *obj, R (*func)(const T*)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(volatile U *obj, R (*func)(volatile T*)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const volatile U *obj, R (*func)(const volatile T*)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Assign a callback
+ */
+ Callback &operator=(const Callback &that) {
+ if (this != &that) {
+ this->~Callback();
+ new (this) Callback(that);
+ }
+
+ return *this;
+ }
+
+ /** Call the attached function
+ */
+ R call() const {
+ MBED_ASSERT(_ops);
+ return _ops->call(this);
+ }
+
+ /** Call the attached function
+ */
+ R operator()() const {
+ return call();
+ }
+
+ /** Test if function has been attached
+ */
+ operator bool() const {
+ return _ops;
+ }
+
+ /** Test for equality
+ */
+ friend bool operator==(const Callback &l, const Callback &r) {
+ return memcmp(&l, &r, sizeof(Callback)) == 0;
+ }
+
+ /** Test for inequality
+ */
+ friend bool operator!=(const Callback &l, const Callback &r) {
+ return !(l == r);
+ }
+
+ /** Static thunk for passing as C-style function
+ * @param func Callback to call passed as void pointer
+ * @return the value as determined by func which is of
+ * type and determined by the signiture of func
+ */
+ static R thunk(void *func) {
+ return static_cast<Callback*>(func)->call();
+ }
+
+private:
+ // Stored as pointer to function and pointer to optional object
+ // Function pointer is stored as union of possible function types
+ // to garuntee proper size and alignment
+ struct _class;
+ union {
+ void (*_staticfunc)();
+ void (*_boundfunc)(_class*);
+ void (_class::*_methodfunc)();
+ } _func;
+ void *_obj;
+
+ // Dynamically dispatched operations
+ const struct ops {
+ R (*call)(const void*);
+ void (*move)(void*, const void*);
+ void (*dtor)(void*);
+ } *_ops;
+
+ // Generate operations for function object
+ template <typename F>
+ void generate(const F &f) {
+ static const ops ops = {
+ &Callback::function_call<F>,
+ &Callback::function_move<F>,
+ &Callback::function_dtor<F>,
+ };
+
+ MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+ "Type F must not exceed the size of the Callback class");
+ new (this) F(f);
+ _ops = &ops;
+ }
+
+ // Function attributes
+ template <typename F>
+ static R function_call(const void *p) {
+ return (*(F*)p)();
+ }
+
+ template <typename F>
+ static void function_move(void *d, const void *p) {
+ new (d) F(*(F*)p);
+ }
+
+ template <typename F>
+ static void function_dtor(void *p) {
+ ((F*)p)->~F();
+ }
+
+ // Wrappers for functions with context
+ template <typename O, typename M>
+ struct method_context {
+ M method;
+ O *obj;
+
+ method_context(O *obj, M method)
+ : method(method), obj(obj) {}
+
+ R operator()() const {
+ return (obj->*method)();
+ }
+ };
+
+ template <typename F, typename A>
+ struct function_context {
+ F func;
+ A *arg;
+
+ function_context(F func, A *arg)
+ : func(func), arg(arg) {}
+
+ R operator()() const {
+ return func(arg);
+ }
+ };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename R, typename A0>
+class Callback<R(A0)> {
+public:
+ /** Create a Callback with a static function
+ * @param func Static function to attach
+ */
+ Callback(R (*func)(A0) = 0) {
+ if (!func) {
+ _ops = 0;
+ } else {
+ generate(func);
+ }
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ */
+ Callback(const Callback<R(A0)> &func) {
+ if (func._ops) {
+ func._ops->move(this, &func);
+ }
+ _ops = func._ops;
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(U *obj, R (T::*method)(A0)) {
+ generate(method_context<T, R (T::*)(A0)>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const U *obj, R (T::*method)(A0) const) {
+ generate(method_context<const T, R (T::*)(A0) const>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(volatile U *obj, R (T::*method)(A0) volatile) {
+ generate(method_context<volatile T, R (T::*)(A0) volatile>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const volatile U *obj, R (T::*method)(A0) const volatile) {
+ generate(method_context<const volatile T, R (T::*)(A0) const volatile>(obj, method));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(T*, A0), U *arg) {
+ generate(function_context<R (*)(T*, A0), T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(const T*, A0), const U *arg) {
+ generate(function_context<R (*)(const T*, A0), const T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(volatile T*, A0), volatile U *arg) {
+ generate(function_context<R (*)(volatile T*, A0), volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(const volatile T*, A0), const volatile U *arg) {
+ generate(function_context<R (*)(const volatile T*, A0), const volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0))) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0) const)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0) volatile)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0) const volatile)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(U *obj, R (*func)(T*, A0)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const U *obj, R (*func)(const T*, A0)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(volatile U *obj, R (*func)(volatile T*, A0)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const volatile U *obj, R (*func)(const volatile T*, A0)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Destroy a callback
+ */
+ ~Callback() {
+ if (_ops) {
+ _ops->dtor(this);
+ }
+ }
+
+ /** Attach a static function
+ * @param func Static function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(A0)) {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const Callback<R(A0)> &func) {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(U *obj, R (T::*method)(A0)) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const U *obj, R (T::*method)(A0) const) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile U *obj, R (T::*method)(A0) volatile) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile U *obj, R (T::*method)(A0) const volatile) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(T*, A0), U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(const T*, A0), const U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(volatile T*, A0), volatile U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(const volatile T*, A0), const volatile U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0))) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0) const)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0) volatile)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0) const volatile)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(U *obj, R (*func)(T*, A0)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const U *obj, R (*func)(const T*, A0)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(volatile U *obj, R (*func)(volatile T*, A0)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const volatile U *obj, R (*func)(const volatile T*, A0)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Assign a callback
+ */
+ Callback &operator=(const Callback &that) {
+ if (this != &that) {
+ this->~Callback();
+ new (this) Callback(that);
+ }
+
+ return *this;
+ }
+
+ /** Call the attached function
+ */
+ R call(A0 a0) const {
+ MBED_ASSERT(_ops);
+ return _ops->call(this, a0);
+ }
+
+ /** Call the attached function
+ */
+ R operator()(A0 a0) const {
+ return call(a0);
+ }
+
+ /** Test if function has been attached
+ */
+ operator bool() const {
+ return _ops;
+ }
+
+ /** Test for equality
+ */
+ friend bool operator==(const Callback &l, const Callback &r) {
+ return memcmp(&l, &r, sizeof(Callback)) == 0;
+ }
+
+ /** Test for inequality
+ */
+ friend bool operator!=(const Callback &l, const Callback &r) {
+ return !(l == r);
+ }
+
+ /** Static thunk for passing as C-style function
+ * @param func Callback to call passed as void pointer
+ * @param a0 An argument to be called with function func
+ * @return the value as determined by func which is of
+ * type and determined by the signiture of func
+ */
+ static R thunk(void *func, A0 a0) {
+ return static_cast<Callback*>(func)->call(a0);
+ }
+
+private:
+ // Stored as pointer to function and pointer to optional object
+ // Function pointer is stored as union of possible function types
+ // to garuntee proper size and alignment
+ struct _class;
+ union {
+ void (*_staticfunc)(A0);
+ void (*_boundfunc)(_class*, A0);
+ void (_class::*_methodfunc)(A0);
+ } _func;
+ void *_obj;
+
+ // Dynamically dispatched operations
+ const struct ops {
+ R (*call)(const void*, A0);
+ void (*move)(void*, const void*);
+ void (*dtor)(void*);
+ } *_ops;
+
+ // Generate operations for function object
+ template <typename F>
+ void generate(const F &f) {
+ static const ops ops = {
+ &Callback::function_call<F>,
+ &Callback::function_move<F>,
+ &Callback::function_dtor<F>,
+ };
+
+ MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+ "Type F must not exceed the size of the Callback class");
+ new (this) F(f);
+ _ops = &ops;
+ }
+
+ // Function attributes
+ template <typename F>
+ static R function_call(const void *p, A0 a0) {
+ return (*(F*)p)(a0);
+ }
+
+ template <typename F>
+ static void function_move(void *d, const void *p) {
+ new (d) F(*(F*)p);
+ }
+
+ template <typename F>
+ static void function_dtor(void *p) {
+ ((F*)p)->~F();
+ }
+
+ // Wrappers for functions with context
+ template <typename O, typename M>
+ struct method_context {
+ M method;
+ O *obj;
+
+ method_context(O *obj, M method)
+ : method(method), obj(obj) {}
+
+ R operator()(A0 a0) const {
+ return (obj->*method)(a0);
+ }
+ };
+
+ template <typename F, typename A>
+ struct function_context {
+ F func;
+ A *arg;
+
+ function_context(F func, A *arg)
+ : func(func), arg(arg) {}
+
+ R operator()(A0 a0) const {
+ return func(arg, a0);
+ }
+ };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename R, typename A0, typename A1>
+class Callback<R(A0, A1)> {
+public:
+ /** Create a Callback with a static function
+ * @param func Static function to attach
+ */
+ Callback(R (*func)(A0, A1) = 0) {
+ if (!func) {
+ _ops = 0;
+ } else {
+ generate(func);
+ }
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ */
+ Callback(const Callback<R(A0, A1)> &func) {
+ if (func._ops) {
+ func._ops->move(this, &func);
+ }
+ _ops = func._ops;
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(U *obj, R (T::*method)(A0, A1)) {
+ generate(method_context<T, R (T::*)(A0, A1)>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const U *obj, R (T::*method)(A0, A1) const) {
+ generate(method_context<const T, R (T::*)(A0, A1) const>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(volatile U *obj, R (T::*method)(A0, A1) volatile) {
+ generate(method_context<volatile T, R (T::*)(A0, A1) volatile>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const volatile U *obj, R (T::*method)(A0, A1) const volatile) {
+ generate(method_context<const volatile T, R (T::*)(A0, A1) const volatile>(obj, method));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(T*, A0, A1), U *arg) {
+ generate(function_context<R (*)(T*, A0, A1), T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(const T*, A0, A1), const U *arg) {
+ generate(function_context<R (*)(const T*, A0, A1), const T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(volatile T*, A0, A1), volatile U *arg) {
+ generate(function_context<R (*)(volatile T*, A0, A1), volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(const volatile T*, A0, A1), const volatile U *arg) {
+ generate(function_context<R (*)(const volatile T*, A0, A1), const volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1))) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1) const)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1) volatile)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1) const volatile)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(U *obj, R (*func)(T*, A0, A1)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const U *obj, R (*func)(const T*, A0, A1)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(volatile U *obj, R (*func)(volatile T*, A0, A1)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Destroy a callback
+ */
+ ~Callback() {
+ if (_ops) {
+ _ops->dtor(this);
+ }
+ }
+
+ /** Attach a static function
+ * @param func Static function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(A0, A1)) {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const Callback<R(A0, A1)> &func) {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(U *obj, R (T::*method)(A0, A1)) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const U *obj, R (T::*method)(A0, A1) const) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile U *obj, R (T::*method)(A0, A1) volatile) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile U *obj, R (T::*method)(A0, A1) const volatile) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(T*, A0, A1), U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(const T*, A0, A1), const U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(volatile T*, A0, A1), volatile U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(const volatile T*, A0, A1), const volatile U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1))) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1) const)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1) volatile)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1) const volatile)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(U *obj, R (*func)(T*, A0, A1)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const U *obj, R (*func)(const T*, A0, A1)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(volatile U *obj, R (*func)(volatile T*, A0, A1)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const volatile U *obj, R (*func)(const volatile T*, A0, A1)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Assign a callback
+ */
+ Callback &operator=(const Callback &that) {
+ if (this != &that) {
+ this->~Callback();
+ new (this) Callback(that);
+ }
+
+ return *this;
+ }
+
+ /** Call the attached function
+ */
+ R call(A0 a0, A1 a1) const {
+ MBED_ASSERT(_ops);
+ return _ops->call(this, a0, a1);
+ }
+
+ /** Call the attached function
+ */
+ R operator()(A0 a0, A1 a1) const {
+ return call(a0, a1);
+ }
+
+ /** Test if function has been attached
+ */
+ operator bool() const {
+ return _ops;
+ }
+
+ /** Test for equality
+ */
+ friend bool operator==(const Callback &l, const Callback &r) {
+ return memcmp(&l, &r, sizeof(Callback)) == 0;
+ }
+
+ /** Test for inequality
+ */
+ friend bool operator!=(const Callback &l, const Callback &r) {
+ return !(l == r);
+ }
+
+ /** Static thunk for passing as C-style function
+ * @param func Callback to call passed as void pointer
+ * @param a0 An argument to be called with function func
+ * @param a1 An argument to be called with function func
+ * @return the value as determined by func which is of
+ * type and determined by the signiture of func
+ */
+ static R thunk(void *func, A0 a0, A1 a1) {
+ return static_cast<Callback*>(func)->call(a0, a1);
+ }
+
+private:
+ // Stored as pointer to function and pointer to optional object
+ // Function pointer is stored as union of possible function types
+ // to garuntee proper size and alignment
+ struct _class;
+ union {
+ void (*_staticfunc)(A0, A1);
+ void (*_boundfunc)(_class*, A0, A1);
+ void (_class::*_methodfunc)(A0, A1);
+ } _func;
+ void *_obj;
+
+ // Dynamically dispatched operations
+ const struct ops {
+ R (*call)(const void*, A0, A1);
+ void (*move)(void*, const void*);
+ void (*dtor)(void*);
+ } *_ops;
+
+ // Generate operations for function object
+ template <typename F>
+ void generate(const F &f) {
+ static const ops ops = {
+ &Callback::function_call<F>,
+ &Callback::function_move<F>,
+ &Callback::function_dtor<F>,
+ };
+
+ MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+ "Type F must not exceed the size of the Callback class");
+ new (this) F(f);
+ _ops = &ops;
+ }
+
+ // Function attributes
+ template <typename F>
+ static R function_call(const void *p, A0 a0, A1 a1) {
+ return (*(F*)p)(a0, a1);
+ }
+
+ template <typename F>
+ static void function_move(void *d, const void *p) {
+ new (d) F(*(F*)p);
+ }
+
+ template <typename F>
+ static void function_dtor(void *p) {
+ ((F*)p)->~F();
+ }
+
+ // Wrappers for functions with context
+ template <typename O, typename M>
+ struct method_context {
+ M method;
+ O *obj;
+
+ method_context(O *obj, M method)
+ : method(method), obj(obj) {}
+
+ R operator()(A0 a0, A1 a1) const {
+ return (obj->*method)(a0, a1);
+ }
+ };
+
+ template <typename F, typename A>
+ struct function_context {
+ F func;
+ A *arg;
+
+ function_context(F func, A *arg)
+ : func(func), arg(arg) {}
+
+ R operator()(A0 a0, A1 a1) const {
+ return func(arg, a0, a1);
+ }
+ };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename R, typename A0, typename A1, typename A2>
+class Callback<R(A0, A1, A2)> {
+public:
+ /** Create a Callback with a static function
+ * @param func Static function to attach
+ */
+ Callback(R (*func)(A0, A1, A2) = 0) {
+ if (!func) {
+ _ops = 0;
+ } else {
+ generate(func);
+ }
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ */
+ Callback(const Callback<R(A0, A1, A2)> &func) {
+ if (func._ops) {
+ func._ops->move(this, &func);
+ }
+ _ops = func._ops;
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(U *obj, R (T::*method)(A0, A1, A2)) {
+ generate(method_context<T, R (T::*)(A0, A1, A2)>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const U *obj, R (T::*method)(A0, A1, A2) const) {
+ generate(method_context<const T, R (T::*)(A0, A1, A2) const>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(volatile U *obj, R (T::*method)(A0, A1, A2) volatile) {
+ generate(method_context<volatile T, R (T::*)(A0, A1, A2) volatile>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const volatile U *obj, R (T::*method)(A0, A1, A2) const volatile) {
+ generate(method_context<const volatile T, R (T::*)(A0, A1, A2) const volatile>(obj, method));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(T*, A0, A1, A2), U *arg) {
+ generate(function_context<R (*)(T*, A0, A1, A2), T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(const T*, A0, A1, A2), const U *arg) {
+ generate(function_context<R (*)(const T*, A0, A1, A2), const T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(volatile T*, A0, A1, A2), volatile U *arg) {
+ generate(function_context<R (*)(volatile T*, A0, A1, A2), volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(const volatile T*, A0, A1, A2), const volatile U *arg) {
+ generate(function_context<R (*)(const volatile T*, A0, A1, A2), const volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2))) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2) const)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2) volatile)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2) const volatile)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(U *obj, R (*func)(T*, A0, A1, A2)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const U *obj, R (*func)(const T*, A0, A1, A2)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(volatile U *obj, R (*func)(volatile T*, A0, A1, A2)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Destroy a callback
+ */
+ ~Callback() {
+ if (_ops) {
+ _ops->dtor(this);
+ }
+ }
+
+ /** Attach a static function
+ * @param func Static function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(A0, A1, A2)) {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const Callback<R(A0, A1, A2)> &func) {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(U *obj, R (T::*method)(A0, A1, A2)) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const U *obj, R (T::*method)(A0, A1, A2) const) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile U *obj, R (T::*method)(A0, A1, A2) volatile) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile U *obj, R (T::*method)(A0, A1, A2) const volatile) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(T*, A0, A1, A2), U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(const T*, A0, A1, A2), const U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(volatile T*, A0, A1, A2), volatile U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(const volatile T*, A0, A1, A2), const volatile U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2))) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2) const)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2) volatile)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2) const volatile)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(U *obj, R (*func)(T*, A0, A1, A2)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const U *obj, R (*func)(const T*, A0, A1, A2)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(volatile U *obj, R (*func)(volatile T*, A0, A1, A2)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Assign a callback
+ */
+ Callback &operator=(const Callback &that) {
+ if (this != &that) {
+ this->~Callback();
+ new (this) Callback(that);
+ }
+
+ return *this;
+ }
+
+ /** Call the attached function
+ */
+ R call(A0 a0, A1 a1, A2 a2) const {
+ MBED_ASSERT(_ops);
+ return _ops->call(this, a0, a1, a2);
+ }
+
+ /** Call the attached function
+ */
+ R operator()(A0 a0, A1 a1, A2 a2) const {
+ return call(a0, a1, a2);
+ }
+
+ /** Test if function has been attached
+ */
+ operator bool() const {
+ return _ops;
+ }
+
+ /** Test for equality
+ */
+ friend bool operator==(const Callback &l, const Callback &r) {
+ return memcmp(&l, &r, sizeof(Callback)) == 0;
+ }
+
+ /** Test for inequality
+ */
+ friend bool operator!=(const Callback &l, const Callback &r) {
+ return !(l == r);
+ }
+
+ /** Static thunk for passing as C-style function
+ * @param func Callback to call passed as void pointer
+ * @param a0 An argument to be called with function func
+ * @param a1 An argument to be called with function func
+ * @param a2 An argument to be called with function func
+ * @return the value as determined by func which is of
+ * type and determined by the signiture of func
+ */
+ static R thunk(void *func, A0 a0, A1 a1, A2 a2) {
+ return static_cast<Callback*>(func)->call(a0, a1, a2);
+ }
+
+private:
+ // Stored as pointer to function and pointer to optional object
+ // Function pointer is stored as union of possible function types
+ // to garuntee proper size and alignment
+ struct _class;
+ union {
+ void (*_staticfunc)(A0, A1, A2);
+ void (*_boundfunc)(_class*, A0, A1, A2);
+ void (_class::*_methodfunc)(A0, A1, A2);
+ } _func;
+ void *_obj;
+
+ // Dynamically dispatched operations
+ const struct ops {
+ R (*call)(const void*, A0, A1, A2);
+ void (*move)(void*, const void*);
+ void (*dtor)(void*);
+ } *_ops;
+
+ // Generate operations for function object
+ template <typename F>
+ void generate(const F &f) {
+ static const ops ops = {
+ &Callback::function_call<F>,
+ &Callback::function_move<F>,
+ &Callback::function_dtor<F>,
+ };
+
+ MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+ "Type F must not exceed the size of the Callback class");
+ new (this) F(f);
+ _ops = &ops;
+ }
+
+ // Function attributes
+ template <typename F>
+ static R function_call(const void *p, A0 a0, A1 a1, A2 a2) {
+ return (*(F*)p)(a0, a1, a2);
+ }
+
+ template <typename F>
+ static void function_move(void *d, const void *p) {
+ new (d) F(*(F*)p);
+ }
+
+ template <typename F>
+ static void function_dtor(void *p) {
+ ((F*)p)->~F();
+ }
+
+ // Wrappers for functions with context
+ template <typename O, typename M>
+ struct method_context {
+ M method;
+ O *obj;
+
+ method_context(O *obj, M method)
+ : method(method), obj(obj) {}
+
+ R operator()(A0 a0, A1 a1, A2 a2) const {
+ return (obj->*method)(a0, a1, a2);
+ }
+ };
+
+ template <typename F, typename A>
+ struct function_context {
+ F func;
+ A *arg;
+
+ function_context(F func, A *arg)
+ : func(func), arg(arg) {}
+
+ R operator()(A0 a0, A1 a1, A2 a2) const {
+ return func(arg, a0, a1, a2);
+ }
+ };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3>
+class Callback<R(A0, A1, A2, A3)> {
+public:
+ /** Create a Callback with a static function
+ * @param func Static function to attach
+ */
+ Callback(R (*func)(A0, A1, A2, A3) = 0) {
+ if (!func) {
+ _ops = 0;
+ } else {
+ generate(func);
+ }
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ */
+ Callback(const Callback<R(A0, A1, A2, A3)> &func) {
+ if (func._ops) {
+ func._ops->move(this, &func);
+ }
+ _ops = func._ops;
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(U *obj, R (T::*method)(A0, A1, A2, A3)) {
+ generate(method_context<T, R (T::*)(A0, A1, A2, A3)>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const U *obj, R (T::*method)(A0, A1, A2, A3) const) {
+ generate(method_context<const T, R (T::*)(A0, A1, A2, A3) const>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(volatile U *obj, R (T::*method)(A0, A1, A2, A3) volatile) {
+ generate(method_context<volatile T, R (T::*)(A0, A1, A2, A3) volatile>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const volatile U *obj, R (T::*method)(A0, A1, A2, A3) const volatile) {
+ generate(method_context<const volatile T, R (T::*)(A0, A1, A2, A3) const volatile>(obj, method));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(T*, A0, A1, A2, A3), U *arg) {
+ generate(function_context<R (*)(T*, A0, A1, A2, A3), T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(const T*, A0, A1, A2, A3), const U *arg) {
+ generate(function_context<R (*)(const T*, A0, A1, A2, A3), const T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(volatile T*, A0, A1, A2, A3), volatile U *arg) {
+ generate(function_context<R (*)(volatile T*, A0, A1, A2, A3), volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(const volatile T*, A0, A1, A2, A3), const volatile U *arg) {
+ generate(function_context<R (*)(const volatile T*, A0, A1, A2, A3), const volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3))) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3) const)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3) volatile)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3) const volatile)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(U *obj, R (*func)(T*, A0, A1, A2, A3)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const U *obj, R (*func)(const T*, A0, A1, A2, A3)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(volatile U *obj, R (*func)(volatile T*, A0, A1, A2, A3)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2, A3)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Destroy a callback
+ */
+ ~Callback() {
+ if (_ops) {
+ _ops->dtor(this);
+ }
+ }
+
+ /** Attach a static function
+ * @param func Static function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(A0, A1, A2, A3)) {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const Callback<R(A0, A1, A2, A3)> &func) {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(U *obj, R (T::*method)(A0, A1, A2, A3)) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const U *obj, R (T::*method)(A0, A1, A2, A3) const) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile U *obj, R (T::*method)(A0, A1, A2, A3) volatile) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile U *obj, R (T::*method)(A0, A1, A2, A3) const volatile) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(T*, A0, A1, A2, A3), U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(const T*, A0, A1, A2, A3), const U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(volatile T*, A0, A1, A2, A3), volatile U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(const volatile T*, A0, A1, A2, A3), const volatile U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3))) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3) const)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3) volatile)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3) const volatile)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(U *obj, R (*func)(T*, A0, A1, A2, A3)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const U *obj, R (*func)(const T*, A0, A1, A2, A3)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(volatile U *obj, R (*func)(volatile T*, A0, A1, A2, A3)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2, A3)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Assign a callback
+ */
+ Callback &operator=(const Callback &that) {
+ if (this != &that) {
+ this->~Callback();
+ new (this) Callback(that);
+ }
+
+ return *this;
+ }
+
+ /** Call the attached function
+ */
+ R call(A0 a0, A1 a1, A2 a2, A3 a3) const {
+ MBED_ASSERT(_ops);
+ return _ops->call(this, a0, a1, a2, a3);
+ }
+
+ /** Call the attached function
+ */
+ R operator()(A0 a0, A1 a1, A2 a2, A3 a3) const {
+ return call(a0, a1, a2, a3);
+ }
+
+ /** Test if function has been attached
+ */
+ operator bool() const {
+ return _ops;
+ }
+
+ /** Test for equality
+ */
+ friend bool operator==(const Callback &l, const Callback &r) {
+ return memcmp(&l, &r, sizeof(Callback)) == 0;
+ }
+
+ /** Test for inequality
+ */
+ friend bool operator!=(const Callback &l, const Callback &r) {
+ return !(l == r);
+ }
+
+ /** Static thunk for passing as C-style function
+ * @param func Callback to call passed as void pointer
+ * @param a0 An argument to be called with function func
+ * @param a1 An argument to be called with function func
+ * @param a2 An argument to be called with function func
+ * @param a3 An argument to be called with function func
+ * @return the value as determined by func which is of
+ * type and determined by the signiture of func
+ */
+ static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3) {
+ return static_cast<Callback*>(func)->call(a0, a1, a2, a3);
+ }
+
+private:
+ // Stored as pointer to function and pointer to optional object
+ // Function pointer is stored as union of possible function types
+ // to garuntee proper size and alignment
+ struct _class;
+ union {
+ void (*_staticfunc)(A0, A1, A2, A3);
+ void (*_boundfunc)(_class*, A0, A1, A2, A3);
+ void (_class::*_methodfunc)(A0, A1, A2, A3);
+ } _func;
+ void *_obj;
+
+ // Dynamically dispatched operations
+ const struct ops {
+ R (*call)(const void*, A0, A1, A2, A3);
+ void (*move)(void*, const void*);
+ void (*dtor)(void*);
+ } *_ops;
+
+ // Generate operations for function object
+ template <typename F>
+ void generate(const F &f) {
+ static const ops ops = {
+ &Callback::function_call<F>,
+ &Callback::function_move<F>,
+ &Callback::function_dtor<F>,
+ };
+
+ MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+ "Type F must not exceed the size of the Callback class");
+ new (this) F(f);
+ _ops = &ops;
+ }
+
+ // Function attributes
+ template <typename F>
+ static R function_call(const void *p, A0 a0, A1 a1, A2 a2, A3 a3) {
+ return (*(F*)p)(a0, a1, a2, a3);
+ }
+
+ template <typename F>
+ static void function_move(void *d, const void *p) {
+ new (d) F(*(F*)p);
+ }
+
+ template <typename F>
+ static void function_dtor(void *p) {
+ ((F*)p)->~F();
+ }
+
+ // Wrappers for functions with context
+ template <typename O, typename M>
+ struct method_context {
+ M method;
+ O *obj;
+
+ method_context(O *obj, M method)
+ : method(method), obj(obj) {}
+
+ R operator()(A0 a0, A1 a1, A2 a2, A3 a3) const {
+ return (obj->*method)(a0, a1, a2, a3);
+ }
+ };
+
+ template <typename F, typename A>
+ struct function_context {
+ F func;
+ A *arg;
+
+ function_context(F func, A *arg)
+ : func(func), arg(arg) {}
+
+ R operator()(A0 a0, A1 a1, A2 a2, A3 a3) const {
+ return func(arg, a0, a1, a2, a3);
+ }
+ };
+};
+
+/** Callback class based on template specialization
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+class Callback<R(A0, A1, A2, A3, A4)> {
+public:
+ /** Create a Callback with a static function
+ * @param func Static function to attach
+ */
+ Callback(R (*func)(A0, A1, A2, A3, A4) = 0) {
+ if (!func) {
+ _ops = 0;
+ } else {
+ generate(func);
+ }
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ */
+ Callback(const Callback<R(A0, A1, A2, A3, A4)> &func) {
+ if (func._ops) {
+ func._ops->move(this, &func);
+ }
+ _ops = func._ops;
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(U *obj, R (T::*method)(A0, A1, A2, A3, A4)) {
+ generate(method_context<T, R (T::*)(A0, A1, A2, A3, A4)>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const U *obj, R (T::*method)(A0, A1, A2, A3, A4) const) {
+ generate(method_context<const T, R (T::*)(A0, A1, A2, A3, A4) const>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(volatile U *obj, R (T::*method)(A0, A1, A2, A3, A4) volatile) {
+ generate(method_context<volatile T, R (T::*)(A0, A1, A2, A3, A4) volatile>(obj, method));
+ }
+
+ /** Create a Callback with a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ */
+ template<typename T, typename U>
+ Callback(const volatile U *obj, R (T::*method)(A0, A1, A2, A3, A4) const volatile) {
+ generate(method_context<const volatile T, R (T::*)(A0, A1, A2, A3, A4) const volatile>(obj, method));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(T*, A0, A1, A2, A3, A4), U *arg) {
+ generate(function_context<R (*)(T*, A0, A1, A2, A3, A4), T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(const T*, A0, A1, A2, A3, A4), const U *arg) {
+ generate(function_context<R (*)(const T*, A0, A1, A2, A3, A4), const T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(volatile T*, A0, A1, A2, A3, A4), volatile U *arg) {
+ generate(function_context<R (*)(volatile T*, A0, A1, A2, A3, A4), volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ */
+ template<typename T, typename U>
+ Callback(R (*func)(const volatile T*, A0, A1, A2, A3, A4), const volatile U *arg) {
+ generate(function_context<R (*)(const volatile T*, A0, A1, A2, A3, A4), const volatile T>(func, arg));
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4))) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4) const)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4) volatile)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ */
+ template <typename F>
+ Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4) const volatile)) {
+ generate(f);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(U *obj, R (*func)(T*, A0, A1, A2, A3, A4)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const U *obj, R (*func)(const T*, A0, A1, A2, A3, A4)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(volatile U *obj, R (*func)(volatile T*, A0, A1, A2, A3, A4)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Create a Callback with a static function and bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to Callback(func, arg)
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to Callback(func, arg)")
+ Callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2, A3, A4)) {
+ new (this) Callback(func, obj);
+ }
+
+ /** Destroy a callback
+ */
+ ~Callback() {
+ if (_ops) {
+ _ops->dtor(this);
+ }
+ }
+
+ /** Attach a static function
+ * @param func Static function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(A0, A1, A2, A3, A4)) {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a Callback
+ * @param func The Callback to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const Callback<R(A0, A1, A2, A3, A4)> &func) {
+ this->~Callback();
+ new (this) Callback(func);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(U *obj, R (T::*method)(A0, A1, A2, A3, A4)) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const U *obj, R (T::*method)(A0, A1, A2, A3, A4) const) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile U *obj, R (T::*method)(A0, A1, A2, A3, A4) volatile) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a member function
+ * @param obj Pointer to object to invoke member function on
+ * @param method Member function to attach
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template<typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile U *obj, R (T::*method)(A0, A1, A2, A3, A4) const volatile) {
+ this->~Callback();
+ new (this) Callback(obj, method);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(T*, A0, A1, A2, A3, A4), U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(const T*, A0, A1, A2, A3, A4), const U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(volatile T*, A0, A1, A2, A3, A4), volatile U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(R (*func)(const volatile T*, A0, A1, A2, A3, A4), const volatile U *arg) {
+ this->~Callback();
+ new (this) Callback(func, arg);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4))) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4) const)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4) volatile)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a function object
+ * @param f Function object to attach
+ * @note The function object is limited to a single word of storage
+ * @deprecated
+ * Replaced by simple assignment 'Callback cb = func'
+ */
+ template <typename F>
+ MBED_DEPRECATED_SINCE("mbed-os-5.4",
+ "Replaced by simple assignment 'Callback cb = func")
+ void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R (F::*)(A0, A1, A2, A3, A4) const volatile)) {
+ this->~Callback();
+ new (this) Callback(f);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(U *obj, R (*func)(T*, A0, A1, A2, A3, A4)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const U *obj, R (*func)(const T*, A0, A1, A2, A3, A4)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(volatile U *obj, R (*func)(volatile T*, A0, A1, A2, A3, A4)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Attach a static function with a bound pointer
+ * @param obj Pointer to object to bind to function
+ * @param func Static function to attach
+ * @deprecated
+ * Arguments to callback have been reordered to attach(func, arg)
+ */
+ template <typename T, typename U>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to attach(func, arg)")
+ void attach(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2, A3, A4)) {
+ this->~Callback();
+ new (this) Callback(func, obj);
+ }
+
+ /** Assign a callback
+ */
+ Callback &operator=(const Callback &that) {
+ if (this != &that) {
+ this->~Callback();
+ new (this) Callback(that);
+ }
+
+ return *this;
+ }
+
+ /** Call the attached function
+ */
+ R call(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const {
+ MBED_ASSERT(_ops);
+ return _ops->call(this, a0, a1, a2, a3, a4);
+ }
+
+ /** Call the attached function
+ */
+ R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const {
+ return call(a0, a1, a2, a3, a4);
+ }
+
+ /** Test if function has been attached
+ */
+ operator bool() const {
+ return _ops;
+ }
+
+ /** Test for equality
+ */
+ friend bool operator==(const Callback &l, const Callback &r) {
+ return memcmp(&l, &r, sizeof(Callback)) == 0;
+ }
+
+ /** Test for inequality
+ */
+ friend bool operator!=(const Callback &l, const Callback &r) {
+ return !(l == r);
+ }
+
+ /** Static thunk for passing as C-style function
+ * @param func Callback to call passed as void pointer
+ * @param a0 An argument to be called with function func
+ * @param a1 An argument to be called with function func
+ * @param a2 An argument to be called with function func
+ * @param a3 An argument to be called with function func
+ * @param a4 An argument to be called with function func
+ * @return the value as determined by func which is of
+ * type and determined by the signiture of func
+ */
+ static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+ return static_cast<Callback*>(func)->call(a0, a1, a2, a3, a4);
+ }
+
+private:
+ // Stored as pointer to function and pointer to optional object
+ // Function pointer is stored as union of possible function types
+ // to garuntee proper size and alignment
+ struct _class;
+ union {
+ void (*_staticfunc)(A0, A1, A2, A3, A4);
+ void (*_boundfunc)(_class*, A0, A1, A2, A3, A4);
+ void (_class::*_methodfunc)(A0, A1, A2, A3, A4);
+ } _func;
+ void *_obj;
+
+ // Dynamically dispatched operations
+ const struct ops {
+ R (*call)(const void*, A0, A1, A2, A3, A4);
+ void (*move)(void*, const void*);
+ void (*dtor)(void*);
+ } *_ops;
+
+ // Generate operations for function object
+ template <typename F>
+ void generate(const F &f) {
+ static const ops ops = {
+ &Callback::function_call<F>,
+ &Callback::function_move<F>,
+ &Callback::function_dtor<F>,
+ };
+
+ MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
+ "Type F must not exceed the size of the Callback class");
+ new (this) F(f);
+ _ops = &ops;
+ }
+
+ // Function attributes
+ template <typename F>
+ static R function_call(const void *p, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+ return (*(F*)p)(a0, a1, a2, a3, a4);
+ }
+
+ template <typename F>
+ static void function_move(void *d, const void *p) {
+ new (d) F(*(F*)p);
+ }
+
+ template <typename F>
+ static void function_dtor(void *p) {
+ ((F*)p)->~F();
+ }
+
+ // Wrappers for functions with context
+ template <typename O, typename M>
+ struct method_context {
+ M method;
+ O *obj;
+
+ method_context(O *obj, M method)
+ : method(method), obj(obj) {}
+
+ R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const {
+ return (obj->*method)(a0, a1, a2, a3, a4);
+ }
+ };
+
+ template <typename F, typename A>
+ struct function_context {
+ F func;
+ A *arg;
+
+ function_context(F func, A *arg)
+ : func(func), arg(arg) {}
+
+ R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const {
+ return func(arg, a0, a1, a2, a3, a4);
+ }
+ };
+};
+
+// Internally used event type
+typedef Callback<void(int)> event_callback_t;
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R>
+Callback<R()> callback(R (*func)() = 0) {
+ return Callback<R()>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R>
+Callback<R()> callback(const Callback<R()> &func) {
+ return Callback<R()>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R>
+Callback<R()> callback(U *obj, R (T::*method)()) {
+ return Callback<R()>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R>
+Callback<R()> callback(const U *obj, R (T::*method)() const) {
+ return Callback<R()>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R>
+Callback<R()> callback(volatile U *obj, R (T::*method)() volatile) {
+ return Callback<R()>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R>
+Callback<R()> callback(const volatile U *obj, R (T::*method)() const volatile) {
+ return Callback<R()>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R>
+Callback<R()> callback(R (*func)(T*), U *arg) {
+ return Callback<R()>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R>
+Callback<R()> callback(R (*func)(const T*), const U *arg) {
+ return Callback<R()>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R>
+Callback<R()> callback(R (*func)(volatile T*), volatile U *arg) {
+ return Callback<R()>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R>
+Callback<R()> callback(R (*func)(const volatile T*), const volatile U *arg) {
+ return Callback<R()>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R()> callback(U *obj, R (*func)(T*)) {
+ return Callback<R()>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R()> callback(const U *obj, R (*func)(const T*)) {
+ return Callback<R()>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R()> callback(volatile U *obj, R (*func)(volatile T*)) {
+ return Callback<R()>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R()> callback(const volatile U *obj, R (*func)(const volatile T*)) {
+ return Callback<R()>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0>
+Callback<R(A0)> callback(R (*func)(A0) = 0) {
+ return Callback<R(A0)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0>
+Callback<R(A0)> callback(const Callback<R(A0)> &func) {
+ return Callback<R(A0)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(U *obj, R (T::*method)(A0)) {
+ return Callback<R(A0)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(const U *obj, R (T::*method)(A0) const) {
+ return Callback<R(A0)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(volatile U *obj, R (T::*method)(A0) volatile) {
+ return Callback<R(A0)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(const volatile U *obj, R (T::*method)(A0) const volatile) {
+ return Callback<R(A0)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(R (*func)(T*, A0), U *arg) {
+ return Callback<R(A0)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(R (*func)(const T*, A0), const U *arg) {
+ return Callback<R(A0)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(R (*func)(volatile T*, A0), volatile U *arg) {
+ return Callback<R(A0)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0>
+Callback<R(A0)> callback(R (*func)(const volatile T*, A0), const volatile U *arg) {
+ return Callback<R(A0)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0)> callback(U *obj, R (*func)(T*, A0)) {
+ return Callback<R(A0)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0)> callback(const U *obj, R (*func)(const T*, A0)) {
+ return Callback<R(A0)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0)> callback(volatile U *obj, R (*func)(volatile T*, A0)) {
+ return Callback<R(A0)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0)> callback(const volatile U *obj, R (*func)(const volatile T*, A0)) {
+ return Callback<R(A0)>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R (*func)(A0, A1) = 0) {
+ return Callback<R(A0, A1)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(const Callback<R(A0, A1)> &func) {
+ return Callback<R(A0, A1)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(U *obj, R (T::*method)(A0, A1)) {
+ return Callback<R(A0, A1)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(const U *obj, R (T::*method)(A0, A1) const) {
+ return Callback<R(A0, A1)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(volatile U *obj, R (T::*method)(A0, A1) volatile) {
+ return Callback<R(A0, A1)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(const volatile U *obj, R (T::*method)(A0, A1) const volatile) {
+ return Callback<R(A0, A1)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R (*func)(T*, A0, A1), U *arg) {
+ return Callback<R(A0, A1)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R (*func)(const T*, A0, A1), const U *arg) {
+ return Callback<R(A0, A1)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R (*func)(volatile T*, A0, A1), volatile U *arg) {
+ return Callback<R(A0, A1)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+Callback<R(A0, A1)> callback(R (*func)(const volatile T*, A0, A1), const volatile U *arg) {
+ return Callback<R(A0, A1)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1)> callback(U *obj, R (*func)(T*, A0, A1)) {
+ return Callback<R(A0, A1)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1)> callback(const U *obj, R (*func)(const T*, A0, A1)) {
+ return Callback<R(A0, A1)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1)> callback(volatile U *obj, R (*func)(volatile T*, A0, A1)) {
+ return Callback<R(A0, A1)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1)> callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1)) {
+ return Callback<R(A0, A1)>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R (*func)(A0, A1, A2) = 0) {
+ return Callback<R(A0, A1, A2)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(const Callback<R(A0, A1, A2)> &func) {
+ return Callback<R(A0, A1, A2)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(U *obj, R (T::*method)(A0, A1, A2)) {
+ return Callback<R(A0, A1, A2)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(const U *obj, R (T::*method)(A0, A1, A2) const) {
+ return Callback<R(A0, A1, A2)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(volatile U *obj, R (T::*method)(A0, A1, A2) volatile) {
+ return Callback<R(A0, A1, A2)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(const volatile U *obj, R (T::*method)(A0, A1, A2) const volatile) {
+ return Callback<R(A0, A1, A2)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R (*func)(T*, A0, A1, A2), U *arg) {
+ return Callback<R(A0, A1, A2)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R (*func)(const T*, A0, A1, A2), const U *arg) {
+ return Callback<R(A0, A1, A2)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R (*func)(volatile T*, A0, A1, A2), volatile U *arg) {
+ return Callback<R(A0, A1, A2)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+Callback<R(A0, A1, A2)> callback(R (*func)(const volatile T*, A0, A1, A2), const volatile U *arg) {
+ return Callback<R(A0, A1, A2)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2)> callback(U *obj, R (*func)(T*, A0, A1, A2)) {
+ return Callback<R(A0, A1, A2)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2)> callback(const U *obj, R (*func)(const T*, A0, A1, A2)) {
+ return Callback<R(A0, A1, A2)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2)> callback(volatile U *obj, R (*func)(volatile T*, A0, A1, A2)) {
+ return Callback<R(A0, A1, A2)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2)> callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2)) {
+ return Callback<R(A0, A1, A2)>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R (*func)(A0, A1, A2, A3) = 0) {
+ return Callback<R(A0, A1, A2, A3)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(const Callback<R(A0, A1, A2, A3)> &func) {
+ return Callback<R(A0, A1, A2, A3)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(U *obj, R (T::*method)(A0, A1, A2, A3)) {
+ return Callback<R(A0, A1, A2, A3)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(const U *obj, R (T::*method)(A0, A1, A2, A3) const) {
+ return Callback<R(A0, A1, A2, A3)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(volatile U *obj, R (T::*method)(A0, A1, A2, A3) volatile) {
+ return Callback<R(A0, A1, A2, A3)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(const volatile U *obj, R (T::*method)(A0, A1, A2, A3) const volatile) {
+ return Callback<R(A0, A1, A2, A3)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R (*func)(T*, A0, A1, A2, A3), U *arg) {
+ return Callback<R(A0, A1, A2, A3)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R (*func)(const T*, A0, A1, A2, A3), const U *arg) {
+ return Callback<R(A0, A1, A2, A3)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R (*func)(volatile T*, A0, A1, A2, A3), volatile U *arg) {
+ return Callback<R(A0, A1, A2, A3)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+Callback<R(A0, A1, A2, A3)> callback(R (*func)(const volatile T*, A0, A1, A2, A3), const volatile U *arg) {
+ return Callback<R(A0, A1, A2, A3)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3)> callback(U *obj, R (*func)(T*, A0, A1, A2, A3)) {
+ return Callback<R(A0, A1, A2, A3)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3)> callback(const U *obj, R (*func)(const T*, A0, A1, A2, A3)) {
+ return Callback<R(A0, A1, A2, A3)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3)> callback(volatile U *obj, R (*func)(volatile T*, A0, A1, A2, A3)) {
+ return Callback<R(A0, A1, A2, A3)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3)> callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2, A3)) {
+ return Callback<R(A0, A1, A2, A3)>(func, obj);
+}
+
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R (*func)(A0, A1, A2, A3, A4) = 0) {
+ return Callback<R(A0, A1, A2, A3, A4)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @return Callback with infered type
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(const Callback<R(A0, A1, A2, A3, A4)> &func) {
+ return Callback<R(A0, A1, A2, A3, A4)>(func);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(U *obj, R (T::*method)(A0, A1, A2, A3, A4)) {
+ return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(const U *obj, R (T::*method)(A0, A1, A2, A3, A4) const) {
+ return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(volatile U *obj, R (T::*method)(A0, A1, A2, A3, A4) volatile) {
+ return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param method Member function to attach
+ * @return Callback with infered type
+ */
+template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(const volatile U *obj, R (T::*method)(A0, A1, A2, A3, A4) const volatile) {
+ return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R (*func)(T*, A0, A1, A2, A3, A4), U *arg) {
+ return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R (*func)(const T*, A0, A1, A2, A3, A4), const U *arg) {
+ return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R (*func)(volatile T*, A0, A1, A2, A3, A4), volatile U *arg) {
+ return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param func Static function to attach
+ * @param arg Pointer argument to function
+ * @return Callback with infered type
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+Callback<R(A0, A1, A2, A3, A4)> callback(R (*func)(const volatile T*, A0, A1, A2, A3, A4), const volatile U *arg) {
+ return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3, A4)> callback(U *obj, R (*func)(T*, A0, A1, A2, A3, A4)) {
+ return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3, A4)> callback(const U *obj, R (*func)(const T*, A0, A1, A2, A3, A4)) {
+ return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3, A4)> callback(volatile U *obj, R (*func)(volatile T*, A0, A1, A2, A3, A4)) {
+ return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
+}
+
+/** Create a callback class with type infered from the arguments
+ *
+ * @param obj Optional pointer to object to bind to function
+ * @param func Static function to attach
+ * @return Callback with infered type
+ * @deprecated
+ * Arguments to callback have been reordered to callback(func, arg)
+ */
+template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "Arguments to callback have been reordered to callback(func, arg)")
+Callback<R(A0, A1, A2, A3, A4)> callback(const volatile U *obj, R (*func)(const volatile T*, A0, A1, A2, A3, A4)) {
+ return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
+}
+
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/CircularBuffer.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CIRCULARBUFFER_H
+#define MBED_CIRCULARBUFFER_H
+
+#include "platform/mbed_critical.h"
+
+namespace mbed {
+/** \addtogroup platform */
+
+/** Templated Circular buffer class
+ *
+ * @note Synchronization level: Interrupt safe
+ * @ingroup platform
+ */
+template<typename T, uint32_t BufferSize, typename CounterType = uint32_t>
+class CircularBuffer {
+public:
+ CircularBuffer() : _head(0), _tail(0), _full(false) {
+ }
+
+ ~CircularBuffer() {
+ }
+
+ /** Push the transaction to the buffer. This overwrites the buffer if it's
+ * full
+ *
+ * @param data Data to be pushed to the buffer
+ */
+ void push(const T& data) {
+ core_util_critical_section_enter();
+ if (full()) {
+ _tail++;
+ _tail %= BufferSize;
+ }
+ _pool[_head++] = data;
+ _head %= BufferSize;
+ if (_head == _tail) {
+ _full = true;
+ }
+ core_util_critical_section_exit();
+ }
+
+ /** Pop the transaction from the buffer
+ *
+ * @param data Data to be pushed to the buffer
+ * @return True if the buffer is not empty and data contains a transaction, false otherwise
+ */
+ bool pop(T& data) {
+ bool data_popped = false;
+ core_util_critical_section_enter();
+ if (!empty()) {
+ data = _pool[_tail++];
+ _tail %= BufferSize;
+ _full = false;
+ data_popped = true;
+ }
+ core_util_critical_section_exit();
+ return data_popped;
+ }
+
+ /** Check if the buffer is empty
+ *
+ * @return True if the buffer is empty, false if not
+ */
+ bool empty() const {
+ core_util_critical_section_enter();
+ bool is_empty = (_head == _tail) && !_full;
+ core_util_critical_section_exit();
+ return is_empty;
+ }
+
+ /** Check if the buffer is full
+ *
+ * @return True if the buffer is full, false if not
+ */
+ bool full() const {
+ core_util_critical_section_enter();
+ bool full = _full;
+ core_util_critical_section_exit();
+ return full;
+ }
+
+ /** Reset the buffer
+ *
+ */
+ void reset() {
+ core_util_critical_section_enter();
+ _head = 0;
+ _tail = 0;
+ _full = false;
+ core_util_critical_section_exit();
+ }
+
+private:
+ T _pool[BufferSize];
+ volatile CounterType _head;
+ volatile CounterType _tail;
+ volatile bool _full;
+};
+
+}
+
+#endif
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/FunctionPointer.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FUNCTIONPOINTER_H
+#define MBED_FUNCTIONPOINTER_H
+
+#include "platform/Callback.h"
+#include "platform/mbed_toolchain.h"
+#include <string.h>
+#include <stdint.h>
+
+namespace mbed {
+/** \addtogroup platform */
+
+
+// Declarations for backwards compatibility
+// To be foward compatible, code should adopt the Callback class
+/**
+ * @ingroup platform
+ */
+template <typename R, typename A1>
+class FunctionPointerArg1 : public Callback<R(A1)> {
+public:
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "FunctionPointerArg1<R, A> has been replaced by Callback<R(A)>")
+ FunctionPointerArg1(R (*function)(A1) = 0)
+ : Callback<R(A1)>(function) {}
+
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "FunctionPointerArg1<R, A> has been replaced by Callback<R(A)>")
+ FunctionPointerArg1(T *object, R (T::*member)(A1))
+ : Callback<R(A1)>(object, member) {}
+
+ R (*get_function())(A1) {
+ return *reinterpret_cast<R (**)(A1)>(this);
+ }
+
+ R call(A1 a1) const {
+ if (!Callback<R(A1)>::operator bool()) {
+ return (R)0;
+ }
+
+ return Callback<R(A1)>::call(a1);
+ }
+
+ R operator()(A1 a1) const {
+ return Callback<R(A1)>::call(a1);
+ }
+};
+
+/**
+ * @ingroup platform
+ */
+template <typename R>
+class FunctionPointerArg1<R, void> : public Callback<R()> {
+public:
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "FunctionPointer has been replaced by Callback<void()>")
+ FunctionPointerArg1(R (*function)() = 0)
+ : Callback<R()>(function) {}
+
+ template<typename T>
+ MBED_DEPRECATED_SINCE("mbed-os-5.1",
+ "FunctionPointer has been replaced by Callback<void()>")
+ FunctionPointerArg1(T *object, R (T::*member)())
+ : Callback<R()>(object, member) {}
+
+ R (*get_function())() {
+ return *reinterpret_cast<R (**)()>(this);
+ }
+
+ R call() const {
+ if (!Callback<R()>::operator bool()) {
+ return (R)0;
+ }
+
+ return Callback<R()>::call();
+ }
+
+ R operator()() const {
+ return Callback<R()>::call();
+ }
+};
+
+typedef FunctionPointerArg1<void, void> FunctionPointer;
+
+
+} // namespace mbed
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/PlatformMutex.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,51 @@
+
+/** \addtogroup platform */
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef PLATFORM_MUTEX_H
+#define PLATFORM_MUTEX_H
+
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "rtos/Mutex.h"
+typedef rtos::Mutex PlatformMutex;
+#else
+/** A stub mutex for when an RTOS is not present
+ * @ingroup platform
+*/
+class PlatformMutex {
+public:
+ PlatformMutex() {
+ // Stub
+
+ }
+ ~PlatformMutex() {
+ // Stub
+ }
+
+ void lock() {
+ // Do nothing
+ }
+
+ void unlock() {
+ // Do nothing
+ }
+};
+
+#endif
+
+#endif
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/SingletonPtr.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,112 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef SINGLETONPTR_H
+#define SINGLETONPTR_H
+
+#include <stdint.h>
+#include <new>
+#include "platform/mbed_assert.h"
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "cmsis_os2.h"
+#endif
+
+#ifdef MBED_CONF_RTOS_PRESENT
+extern osMutexId_t singleton_mutex_id;
+#endif
+
+/** Lock the singleton mutex
+ *
+ * This function is typically used to provide
+ * exclusive access when initializing a
+ * global object.
+ */
+inline static void singleton_lock(void)
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ osMutexAcquire(singleton_mutex_id, osWaitForever);
+#endif
+}
+
+/** Unlock the singleton mutex
+ *
+ * This function is typically used to provide
+ * exclusive access when initializing a
+ * global object.
+ */
+inline static void singleton_unlock(void)
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+ osMutexRelease (singleton_mutex_id);
+#endif
+}
+/** @}*/
+
+/** Utility class for creating an using a singleton
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * @note: This class must only be used in a static context -
+ * this class must never be allocated or created on the
+ * stack.
+ *
+ * @note: This class is lazily initialized on first use.
+ * This class is a POD type so if it is not used it will
+ * be garbage collected.
+ * @ingroup platform
+ */
+template <class T>
+struct SingletonPtr {
+
+ /** Get a pointer to the underlying singleton
+ *
+ * @returns
+ * A pointer to the singleton
+ */
+ T* get() {
+ if (NULL == _ptr) {
+ singleton_lock();
+ if (NULL == _ptr) {
+ _ptr = new (_data) T();
+ }
+ singleton_unlock();
+ }
+ // _ptr was not zero initialized or was
+ // corrupted if this assert is hit
+ MBED_ASSERT(_ptr == (T *)&_data);
+ return _ptr;
+ }
+
+ /** Get a pointer to the underlying singleton
+ *
+ * @returns
+ * A pointer to the singleton
+ */
+ T* operator->() {
+ return get();
+ }
+
+ // This is zero initialized when in global scope
+ T *_ptr;
+ // Force data to be 4 byte aligned
+ uint32_t _data[(sizeof(T) + sizeof(uint32_t) - 1) / sizeof(uint32_t)];
+};
+
+#endif
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/Transaction.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TRANSACTION_H
+#define MBED_TRANSACTION_H
+
+#include "platform/platform.h"
+#include "platform/FunctionPointer.h"
+
+namespace mbed {
+/** \addtogroup platform */
+
+/** Transaction structure
+ * @ingroup platform
+ */
+typedef struct {
+ void *tx_buffer; /**< Tx buffer */
+ size_t tx_length; /**< Length of Tx buffer*/
+ void *rx_buffer; /**< Rx buffer */
+ size_t rx_length; /**< Length of Rx buffer */
+ uint32_t event; /**< Event for a transaction */
+ event_callback_t callback; /**< User's callback */
+ uint8_t width; /**< Buffer's word width (8, 16, 32, 64) */
+} transaction_t;
+
+/** Transaction class defines a transaction.
+ *
+ * @note Synchronization level: Not protected
+ * @ingroup platform
+ */
+template<typename Class>
+class Transaction {
+public:
+ Transaction(Class *tpointer, const transaction_t& transaction) : _obj(tpointer), _data(transaction) {
+ }
+
+ Transaction() : _obj(), _data() {
+ }
+
+ ~Transaction() {
+ }
+
+ /** Get object's instance for the transaction
+ *
+ * @return The object which was stored
+ */
+ Class* get_object() {
+ return _obj;
+ }
+
+ /** Get the transaction
+ *
+ * @return The transaction which was stored
+ */
+ transaction_t* get_transaction() {
+ return &_data;
+ }
+
+private:
+ Class* _obj;
+ transaction_t _data;
+};
+
+}
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/platform/critical.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OLD_CRITICAL_H +#define MBED_OLD_CRITICAL_H + +#warning critical.h has been replaced by mbed_critical.h, please update to mbed_critical.h [since mbed-os-5.3] +#include "platform/mbed_critical.h" + +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_alloc_wrappers.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,347 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/mbed_mem_trace.h"
+#include "platform/mbed_stats.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+/* There are two memory tracers in mbed OS:
+
+- the first can be used to detect the maximum heap usage at runtime. It is
+ activated by defining the MBED_HEAP_STATS_ENABLED macro.
+- the second can be used to trace each memory call by automatically invoking
+ a callback on each memory operation (see hal/api/mbed_mem_trace.h). It is
+ activated by defining the MBED_MEM_TRACING_ENABLED macro.
+
+Both tracers can be activated and deactivated in any combination. If both tracers
+are active, the second one (MBED_MEM_TRACING_ENABLED) will trace the first one's
+(MBED_HEAP_STATS_ENABLED) memory calls.*/
+
+/******************************************************************************/
+/* Implementation of the runtime max heap usage checker */
+/******************************************************************************/
+
+/* Size must be a multiple of 8 to keep alignment */
+typedef struct {
+ uint32_t size;
+ uint32_t pad;
+} alloc_info_t;
+
+#ifdef MBED_MEM_TRACING_ENABLED
+static SingletonPtr<PlatformMutex> mem_trace_mutex;
+#endif
+#ifdef MBED_HEAP_STATS_ENABLED
+static SingletonPtr<PlatformMutex> malloc_stats_mutex;
+static mbed_stats_heap_t heap_stats = {0, 0, 0, 0, 0};
+#endif
+
+void mbed_stats_heap_get(mbed_stats_heap_t *stats)
+{
+#ifdef MBED_HEAP_STATS_ENABLED
+ extern uint32_t mbed_heap_size;
+ heap_stats.reserved_size = mbed_heap_size;
+
+ malloc_stats_mutex->lock();
+ memcpy(stats, &heap_stats, sizeof(mbed_stats_heap_t));
+ malloc_stats_mutex->unlock();
+#else
+ memset(stats, 0, sizeof(mbed_stats_heap_t));
+#endif
+}
+
+/******************************************************************************/
+/* GCC memory allocation wrappers */
+/******************************************************************************/
+
+#if defined(TOOLCHAIN_GCC)
+
+#ifdef FEATURE_UVISOR
+#include "uvisor-lib/uvisor-lib.h"
+#endif/* FEATURE_UVISOR */
+
+extern "C" {
+ void * __real__malloc_r(struct _reent * r, size_t size);
+ void * __real__memalign_r(struct _reent * r, size_t alignment, size_t bytes);
+ void * __real__realloc_r(struct _reent * r, void * ptr, size_t size);
+ void __real__free_r(struct _reent * r, void * ptr);
+ void* __real__calloc_r(struct _reent * r, size_t nmemb, size_t size);
+}
+
+// TODO: memory tracing doesn't work with uVisor enabled.
+#if !defined(FEATURE_UVISOR)
+
+extern "C" void * __wrap__malloc_r(struct _reent * r, size_t size) {
+ void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+ malloc_stats_mutex->lock();
+ alloc_info_t *alloc_info = (alloc_info_t*)__real__malloc_r(r, size + sizeof(alloc_info_t));
+ if (alloc_info != NULL) {
+ alloc_info->size = size;
+ ptr = (void*)(alloc_info + 1);
+ heap_stats.current_size += size;
+ heap_stats.total_size += size;
+ heap_stats.alloc_cnt += 1;
+ if (heap_stats.current_size > heap_stats.max_size) {
+ heap_stats.max_size = heap_stats.current_size;
+ }
+ } else {
+ heap_stats.alloc_fail_cnt += 1;
+ }
+ malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ ptr = __real__malloc_r(r, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mem_trace_mutex->lock();
+ mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR());
+ mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+ return ptr;
+}
+
+extern "C" void * __wrap__realloc_r(struct _reent * r, void * ptr, size_t size) {
+ void *new_ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+ // Implement realloc_r with malloc and free.
+ // The function realloc_r can't be used here directly since
+ // it can call into __wrap__malloc_r (returns ptr + 4) or
+ // resize memory directly (returns ptr + 0).
+
+ // Note - no lock needed since malloc and free are thread safe
+
+ // Get old size
+ uint32_t old_size = 0;
+ if (ptr != NULL) {
+ alloc_info_t *alloc_info = ((alloc_info_t*)ptr) - 1;
+ old_size = alloc_info->size;
+ }
+
+ // Allocate space
+ if (size != 0) {
+ new_ptr = malloc(size);
+ }
+
+ // If the new buffer has been allocated copy the data to it
+ // and free the old buffer
+ if (new_ptr != NULL) {
+ uint32_t copy_size = (old_size < size) ? old_size : size;
+ memcpy(new_ptr, (void*)ptr, copy_size);
+ free(ptr);
+ }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ new_ptr = __real__realloc_r(r, ptr, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mem_trace_mutex->lock();
+ mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
+ mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+ return new_ptr;
+}
+
+extern "C" void __wrap__free_r(struct _reent * r, void * ptr) {
+#ifdef MBED_HEAP_STATS_ENABLED
+ malloc_stats_mutex->lock();
+ alloc_info_t *alloc_info = NULL;
+ if (ptr != NULL) {
+ alloc_info = ((alloc_info_t*)ptr) - 1;
+ heap_stats.current_size -= alloc_info->size;
+ heap_stats.alloc_cnt -= 1;
+ }
+ __real__free_r(r, (void*)alloc_info);
+ malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ __real__free_r(r, ptr);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mem_trace_mutex->lock();
+ mbed_mem_trace_free(ptr, MBED_CALLER_ADDR());
+ mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+}
+
+extern "C" void * __wrap__calloc_r(struct _reent * r, size_t nmemb, size_t size) {
+ void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+ // Note - no lock needed since malloc is thread safe
+
+ ptr = malloc(nmemb * size);
+ if (ptr != NULL) {
+ memset(ptr, 0, nmemb * size);
+ }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ ptr = __real__calloc_r(r, nmemb, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mem_trace_mutex->lock();
+ mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
+ mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+ return ptr;
+}
+
+extern "C" void * __wrap__memalign_r(struct _reent * r, size_t alignment, size_t bytes) {
+ return __real__memalign_r(r, alignment, bytes);
+}
+
+#endif // if !defined(FEATURE_UVISOR)
+
+
+/******************************************************************************/
+/* ARMCC memory allocation wrappers */
+/******************************************************************************/
+
+#elif defined(TOOLCHAIN_ARM) // #if defined(TOOLCHAIN_GCC)
+
+/* Enable hooking of memory function only if tracing is also enabled */
+#if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
+
+extern "C" {
+ void *$Super$$malloc(size_t size);
+ void *$Super$$realloc(void *ptr, size_t size);
+ void *$Super$$calloc(size_t nmemb, size_t size);
+ void $Super$$free(void *ptr);
+}
+
+extern "C" void* $Sub$$malloc(size_t size) {
+ void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+ malloc_stats_mutex->lock();
+ alloc_info_t *alloc_info = (alloc_info_t*)$Super$$malloc(size + sizeof(alloc_info_t));
+ if (alloc_info != NULL) {
+ alloc_info->size = size;
+ ptr = (void*)(alloc_info + 1);
+ heap_stats.current_size += size;
+ heap_stats.total_size += size;
+ heap_stats.alloc_cnt += 1;
+ if (heap_stats.current_size > heap_stats.max_size) {
+ heap_stats.max_size = heap_stats.current_size;
+ }
+ } else {
+ heap_stats.alloc_fail_cnt += 1;
+ }
+ malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ ptr = $Super$$malloc(size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mem_trace_mutex->lock();
+ mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR());
+ mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+ return ptr;
+}
+
+extern "C" void* $Sub$$realloc(void *ptr, size_t size) {
+ void *new_ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+ // Note - no lock needed since malloc and free are thread safe
+
+ // Get old size
+ uint32_t old_size = 0;
+ if (ptr != NULL) {
+ alloc_info_t *alloc_info = ((alloc_info_t*)ptr) - 1;
+ old_size = alloc_info->size;
+ }
+
+ // Allocate space
+ if (size != 0) {
+ new_ptr = malloc(size);
+ }
+
+ // If the new buffer has been allocated copy the data to it
+ // and free the old buffer
+ if (new_ptr != NULL) {
+ uint32_t copy_size = (old_size < size) ? old_size : size;
+ memcpy(new_ptr, (void*)ptr, copy_size);
+ free(ptr);
+ }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ new_ptr = $Super$$realloc(ptr, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mem_trace_mutex->lock();
+ mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
+ mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+ return new_ptr;
+}
+
+extern "C" void *$Sub$$calloc(size_t nmemb, size_t size) {
+ void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+ // Note - no lock needed since malloc is thread safe
+ ptr = malloc(nmemb * size);
+ if (ptr != NULL) {
+ memset(ptr, 0, nmemb * size);
+ }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ ptr = $Super$$calloc(nmemb, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mem_trace_mutex->lock();
+ mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
+ mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+ return ptr;
+}
+
+extern "C" void $Sub$$free(void *ptr) {
+#ifdef MBED_HEAP_STATS_ENABLED
+ malloc_stats_mutex->lock();
+ alloc_info_t *alloc_info = NULL;
+ if (ptr != NULL) {
+ alloc_info = ((alloc_info_t*)ptr) - 1;
+ heap_stats.current_size -= alloc_info->size;
+ heap_stats.alloc_cnt -= 1;
+ }
+ $Super$$free((void*)alloc_info);
+ malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+ $Super$$free(ptr);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+ mem_trace_mutex->lock();
+ mbed_mem_trace_free(ptr, MBED_CALLER_ADDR());
+ mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+}
+
+#endif // #if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
+
+/******************************************************************************/
+/* Allocation wrappers for other toolchains are not supported yet */
+/******************************************************************************/
+
+#else // #if defined(TOOLCHAIN_GCC)
+
+#ifdef MBED_MEM_TRACING_ENABLED
+#warning Memory tracing is not supported with the current toolchain.
+#endif
+
+#ifdef MBED_HEAP_STATS_ENABLED
+#warning Heap statistics are not supported with the current toolchain.
+#endif
+
+#endif // #if defined(TOOLCHAIN_GCC)
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_application.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,128 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdlib.h>
+#include <stdarg.h>
+#include "device.h"
+#include "platform/mbed_application.h"
+
+#if MBED_APPLICATION_SUPPORT
+
+static void powerdown_nvic(void);
+static void powerdown_scb(uint32_t vtor);
+static void start_new_application(void *sp, void *pc);
+
+void mbed_start_application(uintptr_t address)
+{
+ void *sp;
+ void *pc;
+
+ // Interrupts are re-enabled in start_new_application
+ __disable_irq();
+
+ SysTick->CTRL = 0x00000000;
+ powerdown_nvic();
+ powerdown_scb(address);
+
+ sp = *((void**)address + 0);
+ pc = *((void**)address + 1);
+ start_new_application(sp, pc);
+}
+
+static void powerdown_nvic()
+{
+ int isr_count;
+ int i;
+ int j;
+
+ isr_count = (SCnSCB->ICTR & SCnSCB_ICTR_INTLINESNUM_Msk) >> SCnSCB_ICTR_INTLINESNUM_Pos;
+ for (i = 0; i < isr_count; i++) {
+ NVIC->ICER[i] = 0xFFFFFFFF;
+ NVIC->ICPR[i] = 0xFFFFFFFF;
+ for (j = 0; j < 8; j++) {
+ NVIC->IP[i * 8 + j] = 0x00000000;
+ }
+ }
+}
+
+static void powerdown_scb(uint32_t vtor)
+{
+ int i;
+
+ // SCB->CPUID - Read only CPU ID register
+ SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk | SCB_ICSR_PENDSTCLR_Msk;
+ SCB->VTOR = vtor;
+ SCB->AIRCR = 0x05FA | 0x0000;
+ SCB->SCR = 0x00000000;
+ // SCB->CCR - Implementation defined value
+ for (i = 0; i < 12; i++) {
+#if defined(__CORTEX_M7)
+ SCB->SHPR[i] = 0x00;
+#else
+ SCB->SHP[i] = 0x00;
+#endif
+ }
+ SCB->SHCSR = 0x00000000;
+ SCB->CFSR = 0xFFFFFFFF;
+ SCB->HFSR = SCB_HFSR_DEBUGEVT_Msk | SCB_HFSR_FORCED_Msk | SCB_HFSR_VECTTBL_Msk;
+ SCB->DFSR = SCB_DFSR_EXTERNAL_Msk | SCB_DFSR_VCATCH_Msk |
+ SCB_DFSR_DWTTRAP_Msk | SCB_DFSR_BKPT_Msk | SCB_DFSR_HALTED_Msk;
+ // SCB->MMFAR - Implementation defined value
+ // SCB->BFAR - Implementation defined value
+ // SCB->AFSR - Implementation defined value
+ // SCB->PFR - Read only processor feature register
+ // SCB->DFR - Read only debug feature registers
+ // SCB->ADR - Read only auxiliary feature registers
+ // SCB->MMFR - Read only memory model feature registers
+ // SCB->ISAR - Read only instruction set attribute registers
+ // SCB->CPACR - Implementation defined value
+}
+
+#if defined (__CC_ARM)
+
+__asm static void start_new_application(void *sp, void *pc)
+{
+ MOV R2, #0
+ MSR CONTROL, R2 // Switch to main stack
+ MOV SP, R0
+ MSR PRIMASK, R2 // Enable interrupts
+ BX R1
+}
+
+#elif defined (__GNUC__) || defined (__ICCARM__)
+
+void start_new_application(void *sp, void *pc)
+{
+ __asm volatile (
+ "mov r2, #0 \n"
+ "msr control, r2 \n" // Switch to main stack
+ "mov sp, %0 \n"
+ "msr primask, r2 \n" // Enable interrupts
+ "bx %1 \n"
+ :
+ : "l" (sp), "l" (pc)
+ : "r2", "cc", "memory"
+ );
+}
+
+#else
+
+#error "Unsupported toolchain"
+
+#endif
+
+#endif /* MBED_APPLICATION_SUPPORT */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_application.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,51 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_APPLICATION_H
+#define MBED_APPLICATION_H
+
+#include<stdint.h>
+
+#define MBED_APPLICATION_SUPPORT defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7)
+#if MBED_APPLICATION_SUPPORT
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Start the application at the given address. This function does
+ * not return. It is the applications responsibility for flushing to
+ * or powering down external components such as filesystems or
+ * socket connections before calling this function. For Cortex-M
+ * devices this function powers down generic system components such as
+ * the NVIC and set the vector table to that of the new image followed
+ * by jumping to the reset handler of the new image.
+ *
+ * @param address Starting address of next application to run
+ */
+void mbed_start_application(uintptr_t address);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_assert.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform/mbed_assert.h"
+#include "device.h"
+
+#include "platform/mbed_interface.h"
+#include "platform/mbed_critical.h"
+
+void mbed_assert_internal(const char *expr, const char *file, int line)
+{
+ core_util_critical_section_enter();
+ mbed_error_printf("mbed assertation failed: %s, file: %s, line %d \n", expr, file, line);
+ mbed_die();
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_assert.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,114 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ASSERT_H
+#define MBED_ASSERT_H
+
+#include "mbed_preprocessor.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
+ * This function is active only if NDEBUG is not defined prior to including this
+ * assert header file.
+ * In case of MBED_ASSERT failing condition, error() is called with the assertation message.
+ * @param expr Expresion to be checked.
+ * @param file File where assertation failed.
+ * @param line Failing assertation line number.
+ */
+void mbed_assert_internal(const char *expr, const char *file, int line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifdef NDEBUG
+#define MBED_ASSERT(expr) ((void)0)
+
+#else
+#define MBED_ASSERT(expr) \
+do { \
+ if (!(expr)) { \
+ mbed_assert_internal(#expr, __FILE__, __LINE__); \
+ } \
+} while (0)
+#endif
+
+
+/** MBED_STATIC_ASSERT
+ * Declare compile-time assertions, results in compile-time error if condition is false
+ *
+ * The assertion acts as a declaration that can be placed at file scope, in a
+ * code block (except after a label), or as a member of a C++ class/struct/union.
+ *
+ * @note
+ * Use of MBED_STATIC_ASSERT as a member of a struct/union is limited:
+ * - In C++, MBED_STATIC_ASSERT is valid in class/struct/union scope.
+ * - In C, MBED_STATIC_ASSERT is not valid in struct/union scope, and
+ * MBED_STRUCT_STATIC_ASSERT is provided as an alternative that is valid
+ * in C and C++ class/struct/union scope.
+ *
+ * @code
+ * MBED_STATIC_ASSERT(MBED_LIBRARY_VERSION >= 120,
+ * "The mbed library must be at least version 120");
+ *
+ * int main() {
+ * MBED_STATIC_ASSERT(sizeof(int) >= sizeof(char),
+ * "An int must be larger than a char");
+ * }
+ * @endcode
+ */
+#if defined(__cplusplus) && (__cplusplus >= 201103L || __cpp_static_assert >= 200410L)
+#define MBED_STATIC_ASSERT(expr, msg) static_assert(expr, msg)
+#elif !defined(__cplusplus) && __STDC_VERSION__ >= 201112L
+#define MBED_STATIC_ASSERT(expr, msg) _Static_assert(expr, msg)
+#elif defined(__cplusplus) && defined(__GNUC__) && defined(__GXX_EXPERIMENTAL_CXX0X__) \
+ && (__GNUC__*100 + __GNUC_MINOR__) > 403L
+#define MBED_STATIC_ASSERT(expr, msg) __extension__ static_assert(expr, msg)
+#elif !defined(__cplusplus) && defined(__GNUC__) && !defined(__CC_ARM) \
+ && (__GNUC__*100 + __GNUC_MINOR__) > 406L
+#define MBED_STATIC_ASSERT(expr, msg) __extension__ _Static_assert(expr, msg)
+#elif defined(__ICCARM__)
+#define MBED_STATIC_ASSERT(expr, msg) static_assert(expr, msg)
+#else
+#define MBED_STATIC_ASSERT(expr, msg) \
+ enum {MBED_CONCAT(MBED_ASSERTION_AT_, __LINE__) = sizeof(char[(expr) ? 1 : -1])}
+#endif
+
+/** MBED_STRUCT_STATIC_ASSERT
+ * Declare compile-time assertions, results in compile-time error if condition is false
+ *
+ * Unlike MBED_STATIC_ASSERT, MBED_STRUCT_STATIC_ASSERT can and must be used
+ * as a member of a C/C++ class/struct/union.
+ *
+ * @code
+ * struct thing {
+ * MBED_STATIC_ASSERT(2 + 2 == 4,
+ * "Hopefully the universe is mathematically consistent");
+ * };
+ * @endcode
+ */
+#define MBED_STRUCT_STATIC_ASSERT(expr, msg) int : (expr) ? 0 : -1
+
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_board.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "hal/gpio_api.h"
+#include "platform/mbed_wait_api.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/mbed_interface.h"
+#include "platform/mbed_critical.h"
+#include "hal/serial_api.h"
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+#endif
+
+WEAK void mbed_die(void) {
+#if !defined (NRF51_H) && !defined(TARGET_EFM32)
+ core_util_critical_section_enter();
+#endif
+#if (DEVICE_ERROR_RED == 1)
+ gpio_t led_red; gpio_init_out(&led_red, LED_RED);
+#elif (DEVICE_ERROR_PATTERN == 1)
+ gpio_t led_1; gpio_init_out(&led_1, LED1);
+ gpio_t led_2; gpio_init_out(&led_2, LED2);
+ gpio_t led_3; gpio_init_out(&led_3, LED3);
+ gpio_t led_4; gpio_init_out(&led_4, LED4);
+#endif
+
+ while (1) {
+#if (DEVICE_ERROR_RED == 1)
+ gpio_write(&led_red, 1);
+
+#elif (DEVICE_ERROR_PATTERN == 1)
+ gpio_write(&led_1, 1);
+ gpio_write(&led_2, 0);
+ gpio_write(&led_3, 0);
+ gpio_write(&led_4, 1);
+#endif
+
+ wait_ms(150);
+
+#if (DEVICE_ERROR_RED == 1)
+ gpio_write(&led_red, 0);
+
+#elif (DEVICE_ERROR_PATTERN == 1)
+ gpio_write(&led_1, 0);
+ gpio_write(&led_2, 1);
+ gpio_write(&led_3, 1);
+ gpio_write(&led_4, 0);
+#endif
+
+ wait_ms(150);
+ }
+}
+
+void mbed_error_printf(const char* format, ...) {
+ va_list arg;
+ va_start(arg, format);
+ mbed_error_vfprintf(format, arg);
+ va_end(arg);
+}
+
+void mbed_error_vfprintf(const char * format, va_list arg) {
+#if DEVICE_SERIAL
+#define ERROR_BUF_SIZE (128)
+ core_util_critical_section_enter();
+ char buffer[ERROR_BUF_SIZE];
+ int size = vsnprintf(buffer, ERROR_BUF_SIZE, format, arg);
+ if (size > 0) {
+ if (!stdio_uart_inited) {
+ serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
+ }
+#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
+ char stdio_out_prev = '\0';
+ for (int i = 0; i < size; i++) {
+ if (buffer[i] == '\n' && stdio_out_prev != '\r') {
+ serial_putc(&stdio_uart, '\r');
+ }
+ serial_putc(&stdio_uart, buffer[i]);
+ stdio_out_prev = buffer[i];
+ }
+#else
+ for (int i = 0; i < size; i++) {
+ serial_putc(&stdio_uart, buffer[i]);
+ }
+#endif
+ }
+ core_util_critical_section_exit();
+#endif
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_critical.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,339 @@
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Declare __STDC_LIMIT_MACROS so stdint.h defines UINT32_MAX when using C++ */
+#define __STDC_LIMIT_MACROS
+#include "platform/mbed_critical.h"
+
+#include "cmsis.h"
+#include "platform/mbed_assert.h"
+#include "platform/mbed_toolchain.h"
+
+#define EXCLUSIVE_ACCESS (!defined (__CORTEX_M0) && !defined (__CORTEX_M0PLUS))
+
+static volatile uint32_t interrupt_enable_counter = 0;
+static volatile bool critical_interrupts_disabled = false;
+
+bool core_util_are_interrupts_enabled(void)
+{
+#if defined(__CORTEX_A9)
+ return ((__get_CPSR() & 0x80) == 0);
+#else
+ return ((__get_PRIMASK() & 0x1) == 0);
+#endif
+}
+
+bool core_util_is_isr_active(void)
+{
+#if defined(__CORTEX_A9)
+ switch(__get_CPSR() & 0x1FU) {
+ case MODE_USR:
+ case MODE_SYS:
+ return false;
+ case MODE_SVC:
+ default:
+ return true;
+ }
+#else
+ return (__get_IPSR() != 0U);
+#endif
+}
+
+MBED_WEAK void core_util_critical_section_enter(void)
+{
+ bool interrupts_disabled = !core_util_are_interrupts_enabled();
+ __disable_irq();
+
+ /* Save the interrupt disabled state as it was prior to any nested critical section lock use */
+ if (!interrupt_enable_counter) {
+ critical_interrupts_disabled = interrupts_disabled;
+ }
+
+ /* If the interrupt_enable_counter overflows or we are in a nested critical section and interrupts
+ are enabled, then something has gone badly wrong thus assert an error.
+ */
+ MBED_ASSERT(interrupt_enable_counter < UINT32_MAX);
+// FIXME
+#ifndef FEATURE_UVISOR
+ if (interrupt_enable_counter > 0) {
+ MBED_ASSERT(interrupts_disabled);
+ }
+#else
+#warning "core_util_critical_section_enter needs fixing to work from unprivileged code"
+#endif /* FEATURE_UVISOR */
+ interrupt_enable_counter++;
+}
+
+MBED_WEAK void core_util_critical_section_exit(void)
+{
+ /* If critical_section_enter has not previously been called, do nothing */
+ if (interrupt_enable_counter) {
+
+// FIXME
+#ifndef FEATURE_UVISOR
+ bool interrupts_disabled = !core_util_are_interrupts_enabled(); /* get the current interrupt disabled state */
+
+ MBED_ASSERT(interrupts_disabled); /* Interrupts must be disabled on invoking an exit from a critical section */
+#else
+#warning "core_util_critical_section_exit needs fixing to work from unprivileged code"
+#endif /* FEATURE_UVISOR */
+
+ interrupt_enable_counter--;
+
+ /* Only re-enable interrupts if we are exiting the last of the nested critical sections and
+ interrupts were enabled on entry to the first critical section.
+ */
+ if (!interrupt_enable_counter && !critical_interrupts_disabled) {
+ __enable_irq();
+ }
+ }
+}
+
+#if EXCLUSIVE_ACCESS
+
+/* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
+#if defined (__CC_ARM)
+#pragma diag_suppress 3731
+#endif
+
+bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
+{
+ uint8_t currentValue = __LDREXB((volatile uint8_t*)ptr);
+ if (currentValue != *expectedCurrentValue) {
+ *expectedCurrentValue = currentValue;
+ __CLREX();
+ return false;
+ }
+
+ return !__STREXB(desiredValue, (volatile uint8_t*)ptr);
+}
+
+bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
+{
+ uint16_t currentValue = __LDREXH((volatile uint16_t*)ptr);
+ if (currentValue != *expectedCurrentValue) {
+ *expectedCurrentValue = currentValue;
+ __CLREX();
+ return false;
+ }
+
+ return !__STREXH(desiredValue, (volatile uint16_t*)ptr);
+}
+
+
+bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
+{
+ uint32_t currentValue = __LDREXW((volatile uint32_t*)ptr);
+ if (currentValue != *expectedCurrentValue) {
+ *expectedCurrentValue = currentValue;
+ __CLREX();
+ return false;
+ }
+
+ return !__STREXW(desiredValue, (volatile uint32_t*)ptr);
+}
+
+uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
+{
+ uint8_t newValue;
+ do {
+ newValue = __LDREXB((volatile uint8_t*)valuePtr) + delta;
+ } while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
+ return newValue;
+}
+
+uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
+{
+ uint16_t newValue;
+ do {
+ newValue = __LDREXH((volatile uint16_t*)valuePtr) + delta;
+ } while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
+ return newValue;
+}
+
+uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
+{
+ uint32_t newValue;
+ do {
+ newValue = __LDREXW((volatile uint32_t*)valuePtr) + delta;
+ } while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
+ return newValue;
+}
+
+
+uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
+{
+ uint8_t newValue;
+ do {
+ newValue = __LDREXB((volatile uint8_t*)valuePtr) - delta;
+ } while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
+ return newValue;
+}
+
+uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
+{
+ uint16_t newValue;
+ do {
+ newValue = __LDREXH((volatile uint16_t*)valuePtr) - delta;
+ } while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
+ return newValue;
+}
+
+uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
+{
+ uint32_t newValue;
+ do {
+ newValue = __LDREXW((volatile uint32_t*)valuePtr) - delta;
+ } while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
+ return newValue;
+}
+
+#else
+
+bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
+{
+ bool success;
+ uint8_t currentValue;
+ core_util_critical_section_enter();
+ currentValue = *ptr;
+ if (currentValue == *expectedCurrentValue) {
+ *ptr = desiredValue;
+ success = true;
+ } else {
+ *expectedCurrentValue = currentValue;
+ success = false;
+ }
+ core_util_critical_section_exit();
+ return success;
+}
+
+bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
+{
+ bool success;
+ uint16_t currentValue;
+ core_util_critical_section_enter();
+ currentValue = *ptr;
+ if (currentValue == *expectedCurrentValue) {
+ *ptr = desiredValue;
+ success = true;
+ } else {
+ *expectedCurrentValue = currentValue;
+ success = false;
+ }
+ core_util_critical_section_exit();
+ return success;
+}
+
+
+bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
+{
+ bool success;
+ uint32_t currentValue;
+ core_util_critical_section_enter();
+ currentValue = *ptr;
+ if (currentValue == *expectedCurrentValue) {
+ *ptr = desiredValue;
+ success = true;
+ } else {
+ *expectedCurrentValue = currentValue;
+ success = false;
+ }
+ core_util_critical_section_exit();
+ return success;
+}
+
+
+uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
+{
+ uint8_t newValue;
+ core_util_critical_section_enter();
+ newValue = *valuePtr + delta;
+ *valuePtr = newValue;
+ core_util_critical_section_exit();
+ return newValue;
+}
+
+uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
+{
+ uint16_t newValue;
+ core_util_critical_section_enter();
+ newValue = *valuePtr + delta;
+ *valuePtr = newValue;
+ core_util_critical_section_exit();
+ return newValue;
+}
+
+uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
+{
+ uint32_t newValue;
+ core_util_critical_section_enter();
+ newValue = *valuePtr + delta;
+ *valuePtr = newValue;
+ core_util_critical_section_exit();
+ return newValue;
+}
+
+
+uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
+{
+ uint8_t newValue;
+ core_util_critical_section_enter();
+ newValue = *valuePtr - delta;
+ *valuePtr = newValue;
+ core_util_critical_section_exit();
+ return newValue;
+}
+
+uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
+{
+ uint16_t newValue;
+ core_util_critical_section_enter();
+ newValue = *valuePtr - delta;
+ *valuePtr = newValue;
+ core_util_critical_section_exit();
+ return newValue;
+}
+
+uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
+{
+ uint32_t newValue;
+ core_util_critical_section_enter();
+ newValue = *valuePtr - delta;
+ *valuePtr = newValue;
+ core_util_critical_section_exit();
+ return newValue;
+}
+
+#endif
+
+
+bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue) {
+ return core_util_atomic_cas_u32(
+ (uint32_t *)ptr,
+ (uint32_t *)expectedCurrentValue,
+ (uint32_t)desiredValue);
+}
+
+void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta) {
+ return (void *)core_util_atomic_incr_u32((uint32_t *)valuePtr, (uint32_t)delta);
+}
+
+void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta) {
+ return (void *)core_util_atomic_decr_u32((uint32_t *)valuePtr, (uint32_t)delta);
+}
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_critical.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,371 @@
+
+/** \addtogroup platform */
+/** @{*/
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MBED_UTIL_CRITICAL_H__
+#define __MBED_UTIL_CRITICAL_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** Determine the current interrupts enabled state
+ *
+ * This function can be called to determine whether or not interrupts are currently enabled.
+ * @note
+ * NOTE:
+ * This function works for both cortex-A and cortex-M, although the underlyng implementation
+ * differs.
+ * @return true if interrupts are enabled, false otherwise
+ */
+bool core_util_are_interrupts_enabled(void);
+
+/** Determine if this code is executing from an interrupt
+ *
+ * This function can be called to determine if the code is running on interrupt context.
+ * @note
+ * NOTE:
+ * This function works for both cortex-A and cortex-M, although the underlyng implementation
+ * differs.
+ * @return true if in an isr, false otherwise
+ */
+bool core_util_is_isr_active(void);
+
+/** Mark the start of a critical section
+ *
+ * This function should be called to mark the start of a critical section of code.
+ * @note
+ * NOTES:
+ * 1) The use of this style of critical section is targetted at C based implementations.
+ * 2) These critical sections can be nested.
+ * 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
+ * section) will be preserved on exit from the section.
+ * 4) This implementation will currently only work on code running in privileged mode.
+ */
+void core_util_critical_section_enter(void);
+
+/** Mark the end of a critical section
+ *
+ * This function should be called to mark the end of a critical section of code.
+ * @note
+ * NOTES:
+ * 1) The use of this style of critical section is targetted at C based implementations.
+ * 2) These critical sections can be nested.
+ * 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
+ * section) will be preserved on exit from the section.
+ * 4) This implementation will currently only work on code running in privileged mode.
+ */
+void core_util_critical_section_exit(void);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param ptr The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ * expected current value of the data being set atomically.
+ * The computed 'desiredValue' should be a function of this current value.
+ * @note: This is an in-out parameter. In the
+ * failure case of atomic_cas (where the
+ * destination isn't set), the pointee of expectedCurrentValue is
+ * updated with the current value.
+ * @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return true if the memory location was atomically
+ * updated with the desired value (after verifying
+ * that it contained the expectedCurrentValue),
+ * false otherwise. In the failure case,
+ * exepctedCurrentValue is updated with the new
+ * value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ * if *p != *old {
+ * *old = *p
+ * return false
+ * }
+ * *p = new
+ * return true
+ * }
+ *
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is still updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ * done = false
+ * value = *p // This fetch operation need not be atomic.
+ * while not done {
+ * done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ * }
+ * return value + a
+ * }
+ */
+bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param ptr The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ * expected current value of the data being set atomically.
+ * The computed 'desiredValue' should be a function of this current value.
+ * @note: This is an in-out parameter. In the
+ * failure case of atomic_cas (where the
+ * destination isn't set), the pointee of expectedCurrentValue is
+ * updated with the current value.
+ * @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return true if the memory location was atomically
+ * updated with the desired value (after verifying
+ * that it contained the expectedCurrentValue),
+ * false otherwise. In the failure case,
+ * exepctedCurrentValue is updated with the new
+ * value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ * if *p != *old {
+ * *old = *p
+ * return false
+ * }
+ * *p = new
+ * return true
+ * }
+ *
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is still updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ * done = false
+ * value = *p // This fetch operation need not be atomic.
+ * while not done {
+ * done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ * }
+ * return value + a
+ * }
+ */
+bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param ptr The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ * expected current value of the data being set atomically.
+ * The computed 'desiredValue' should be a function of this current value.
+ * @note: This is an in-out parameter. In the
+ * failure case of atomic_cas (where the
+ * destination isn't set), the pointee of expectedCurrentValue is
+ * updated with the current value.
+ * @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return true if the memory location was atomically
+ * updated with the desired value (after verifying
+ * that it contained the expectedCurrentValue),
+ * false otherwise. In the failure case,
+ * exepctedCurrentValue is updated with the new
+ * value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ * if *p != *old {
+ * *old = *p
+ * return false
+ * }
+ * *p = new
+ * return true
+ * }
+ *
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is still updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ * done = false
+ * value = *p // This fetch operation need not be atomic.
+ * while not done {
+ * done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ * }
+ * return value + a
+ * }
+ */
+bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param ptr The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ * expected current value of the data being set atomically.
+ * The computed 'desiredValue' should be a function of this current value.
+ * @note: This is an in-out parameter. In the
+ * failure case of atomic_cas (where the
+ * destination isn't set), the pointee of expectedCurrentValue is
+ * updated with the current value.
+ * @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return true if the memory location was atomically
+ * updated with the desired value (after verifying
+ * that it contained the expectedCurrentValue),
+ * false otherwise. In the failure case,
+ * exepctedCurrentValue is updated with the new
+ * value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ * if *p != *old {
+ * *old = *p
+ * return false
+ * }
+ * *p = new
+ * return true
+ * }
+ *
+ * @note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is still updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ * done = false
+ * value = *p // This fetch operation need not be atomic.
+ * while not done {
+ * done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ * }
+ * return value + a
+ * }
+ */
+bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue);
+
+/**
+ * Atomic increment.
+ * @param valuePtr Target memory location being incremented.
+ * @param delta The amount being incremented.
+ * @return The new incremented value.
+ */
+uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta);
+
+/**
+ * Atomic increment.
+ * @param valuePtr Target memory location being incremented.
+ * @param delta The amount being incremented.
+ * @return The new incremented value.
+ */
+uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta);
+
+/**
+ * Atomic increment.
+ * @param valuePtr Target memory location being incremented.
+ * @param delta The amount being incremented.
+ * @return The new incremented value.
+ */
+uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta);
+
+/**
+ * Atomic increment.
+ * @param valuePtr Target memory location being incremented.
+ * @param delta The amount being incremented in bytes.
+ * @return The new incremented value.
+ *
+ * @note The type of the pointer argument is not taken into account
+ * and the pointer is incremented by bytes.
+ */
+void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta);
+
+/**
+ * Atomic decrement.
+ * @param valuePtr Target memory location being decremented.
+ * @param delta The amount being decremented.
+ * @return The new decremented value.
+ */
+uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta);
+
+/**
+ * Atomic decrement.
+ * @param valuePtr Target memory location being decremented.
+ * @param delta The amount being decremented.
+ * @return The new decremented value.
+ */
+uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta);
+
+/**
+ * Atomic decrement.
+ * @param valuePtr Target memory location being decremented.
+ * @param delta The amount being decremented.
+ * @return The new decremented value.
+ */
+uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta);
+
+/**
+ * Atomic decrement.
+ * @param valuePtr Target memory location being decremented.
+ * @param delta The amount being decremented in bytes.
+ * @return The new decremented value.
+ *
+ * @note The type of the pointer argument is not taken into account
+ * and the pointer is decremented by bytes
+ */
+void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+
+#endif // __MBED_UTIL_CRITICAL_H__
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_debug.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,72 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEBUG_H
+#define MBED_DEBUG_H
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#include <stdarg.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** Output a debug message
+ *
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug(const char *format, ...) {
+#if DEVICE_STDIO_MESSAGES && !defined(NDEBUG)
+ va_list args;
+ va_start(args, format);
+ vfprintf(stderr, format, args);
+ va_end(args);
+#endif
+}
+
+
+/** Conditionally output a debug message
+ *
+ * NOTE: If the condition is constant false (== 0) and the compiler optimization
+ * level is greater than 0, then the whole function will be compiled away.
+ *
+ * @param condition output only if condition is true (!= 0)
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug_if(int condition, const char *format, ...) {
+#if DEVICE_STDIO_MESSAGES && !defined(NDEBUG)
+ if (condition) {
+ va_list args;
+ va_start(args, format);
+ vfprintf(stderr, format, args);
+ va_end(args);
+ }
+#endif
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_error.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <stdarg.h>
+#include "device.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_interface.h"
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+
+static uint8_t error_in_progress = 0;
+
+WEAK void error(const char* format, ...) {
+
+ // Prevent recursion if error is called again
+ if (error_in_progress) {
+ return;
+ }
+ error_in_progress = 1;
+
+#ifndef NDEBUG
+ va_list arg;
+ va_start(arg, format);
+ mbed_error_vfprintf(format, arg);
+ va_end(arg);
+#endif
+ exit(1);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_error.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,72 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ERROR_H
+#define MBED_ERROR_H
+
+/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
+ *
+ * @code
+ * #error "That shouldn't have happened!"
+ * @endcode
+ *
+ * If the compiler evaluates this line, it will report the error and stop the compile.
+ *
+ * For example, you could use this to check some user-defined compile-time variables:
+ *
+ * @code
+ * #define NUM_PORTS 7
+ * #if (NUM_PORTS > 4)
+ * #error "NUM_PORTS must be less than 4"
+ * #endif
+ * @endcode
+ *
+ * Reporting Run-Time Errors:
+ * To generate a fatal run-time error, you can use the mbed error() function.
+ *
+ * @code
+ * error("That shouldn't have happened!");
+ * @endcode
+ *
+ * If the mbed running the program executes this function, it will print the
+ * message via the USB serial port, and then die with the blue lights of death!
+ *
+ * The message can use printf-style formatting, so you can report variables in the
+ * message too. For example, you could use this to check a run-time condition:
+ *
+ * @code
+ * if(x >= 5) {
+ * error("expected x to be less than 5, but got %d", x);
+ * }
+ * @endcode
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void error(const char* format, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_interface.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,114 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "platform/mbed_interface.h"
+
+#include "hal/gpio_api.h"
+#include "platform/mbed_wait_api.h"
+#include "platform/mbed_semihost_api.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_toolchain.h"
+
+#if DEVICE_SEMIHOST
+
+// return true if a debugger is attached, indicating mbed interface is connected
+int mbed_interface_connected(void) {
+ return semihost_connected();
+}
+
+int mbed_interface_reset(void) {
+ if (mbed_interface_connected()) {
+ semihost_reset();
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+WEAK int mbed_interface_uid(char *uid) {
+ if (mbed_interface_connected()) {
+ return semihost_uid(uid); // Returns 0 if successful, -1 on failure
+ } else {
+ uid[0] = 0;
+ return -1;
+ }
+}
+
+int mbed_interface_disconnect(void) {
+ int res;
+ if (mbed_interface_connected()) {
+ if ((res = semihost_disabledebug()) != 0)
+ return res;
+ while (mbed_interface_connected());
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+int mbed_interface_powerdown(void) {
+ int res;
+ if (mbed_interface_connected()) {
+ if ((res = semihost_powerdown()) != 0)
+ return res;
+ while (mbed_interface_connected());
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+// for backward compatibility
+void mbed_reset(void) {
+ mbed_interface_reset();
+}
+
+WEAK int mbed_uid(char *uid) {
+ return mbed_interface_uid(uid);
+}
+#endif
+
+WEAK void mbed_mac_address(char *mac) {
+#if DEVICE_SEMIHOST
+ char uid[DEVICE_ID_LENGTH + 1];
+ int i;
+
+ // if we have a UID, extract the MAC
+ if (mbed_interface_uid(uid) == 0) {
+ char *p = uid;
+#if defined(DEVICE_MAC_OFFSET)
+ p += DEVICE_MAC_OFFSET;
+#endif
+ for (i=0; i<6; i++) {
+ int byte;
+ sscanf(p, "%2x", &byte);
+ mac[i] = byte;
+ p += 2;
+ }
+ mac[0] &= ~0x01; // reset the IG bit in the address; see IEE 802.3-2002, Section 3.2.3(b)
+ } else { // else return a default MAC
+#endif
+ mac[0] = 0x00;
+ mac[1] = 0x02;
+ mac[2] = 0xF7;
+ mac[3] = 0xF0;
+ mac[4] = 0x00;
+ mac[5] = 0x00;
+#if DEVICE_SEMIHOST
+ }
+#endif
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_interface.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,136 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERFACE_H
+#define MBED_INTERFACE_H
+
+#include <stdarg.h>
+
+#include "device.h"
+
+/* Mbed interface mac address
+ * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
+ * otherwise MAC_ADD_x are used.
+ */
+#define MBED_MAC_ADDR_INTERFACE 0x00
+#define MBED_MAC_ADDR_0 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_1 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_2 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_3 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_4 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_5 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+/** Functions to control the mbed interface
+ *
+ * mbed Microcontrollers have a built-in interface to provide functionality such as
+ * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
+ * system. These functions provide means to control the interface suing semihost
+ * calls it supports.
+ */
+
+/** Determine whether the mbed interface is connected, based on whether debug is enabled
+ *
+ * @returns
+ * 1 if interface is connected,
+ * 0 otherwise
+ */
+int mbed_interface_connected(void);
+
+/** Instruct the mbed interface to reset, as if the reset button had been pressed
+ *
+ * @returns
+ * 1 if successful,
+ * 0 otherwise (e.g. interface not present)
+ */
+int mbed_interface_reset(void);
+
+/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
+ * The interface will still support the USB serial aspect
+ *
+ * @returns
+ * 0 if successful,
+ * -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_disconnect(void);
+
+/** This will disconnect the debug aspect of the interface, and if the USB cable is not
+ * connected, also power down the interface. If the USB cable is connected, the interface
+ * will remain powered up and visible to the host
+ *
+ * @returns
+ * 0 if successful,
+ * -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_powerdown(void);
+
+/** This returns a string containing the 32-character UID of the mbed interface
+ * This is a weak function that can be overwritten if required
+ *
+ * @param uid A 33-byte array to write the null terminated 32-byte string
+ *
+ * @returns
+ * 0 if successful,
+ * -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_uid(char *uid);
+
+#endif
+
+/** This returns a unique 6-byte MAC address, based on the interface UID
+ * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
+ *
+ * This is a weak function that can be overwritten if you want to provide your own mechanism to
+ * provide a MAC address.
+ *
+ * @param mac A 6-byte array to write the MAC address
+ */
+void mbed_mac_address(char *mac);
+
+/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
+ */
+void mbed_die(void);
+
+/** Print out an error message. This is typically called when
+ * hanlding a crash.
+ *
+ * @note Synchronization level: Interrupt safe
+ */
+void mbed_error_printf(const char* format, ...);
+
+/** Print out an error message. Similar to mbed_error_printf
+ * but uses a va_list.
+ *
+ * @note Synchronization level: Interrupt safe
+ */
+void mbed_error_vfprintf(const char * format, va_list arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_lib.json Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,33 @@
+{
+ "name": "platform",
+ "config": {
+ "stdio-convert-newlines": {
+ "help": "Enable conversion to standard newlines on stdin/stdout",
+ "value": false
+ },
+
+ "stdio-baud-rate": {
+ "help": "Baud rate for stdio",
+ "value": 9600
+ },
+
+ "stdio-flush-at-exit": {
+ "help": "Enable or disable the flush of standard I/O's at exit.",
+ "value": true
+ },
+
+ "default-serial-baud-rate": {
+ "help": "Default baud rate for a Serial or RawSerial instance (if not specified in the constructor)",
+ "value": 9600
+ }
+ },
+ "target_overrides": {
+ "EFM32": {
+ "stdio-baud-rate": 115200
+ },
+ "EFR32": {
+ "stdio-baud-rate": 115200
+ }
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_mem_trace.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdlib.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include "platform/mbed_mem_trace.h"
+#include "platform/mbed_critical.h"
+
+/******************************************************************************
+ * Internal variables, functions and helpers
+ *****************************************************************************/
+
+/* The callback function that will be called after a traced memory operations finishes. */
+static mbed_mem_trace_cb_t mem_trace_cb;
+/* 'trave_level' guards "trace inside trace" situations (for example, the implementation
+ * of realloc() might call malloc() internally, and since malloc() is also traced, this could
+ * result in two calls to the callback function instead of one. */
+static uint8_t trace_level;
+
+/******************************************************************************
+ * Public interface
+ *****************************************************************************/
+
+void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb) {
+ mem_trace_cb = cb;
+}
+
+void *mbed_mem_trace_malloc(void *res, size_t size, void *caller) {
+ if (mem_trace_cb) {
+ if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+ mem_trace_cb(MBED_MEM_TRACE_MALLOC, res, caller, size);
+ }
+ core_util_atomic_decr_u8(&trace_level, 1);
+ }
+ return res;
+}
+
+void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller) {
+ if (mem_trace_cb) {
+ if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+ mem_trace_cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size);
+ }
+ core_util_atomic_decr_u8(&trace_level, 1);
+ }
+ return res;
+}
+
+void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller) {
+ if (mem_trace_cb) {
+ if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+ mem_trace_cb(MBED_MEM_TRACE_CALLOC, res, caller, num, size);
+ }
+ core_util_atomic_decr_u8(&trace_level, 1);
+ }
+ return res;
+}
+
+void mbed_mem_trace_free(void *ptr, void *caller) {
+ if (mem_trace_cb) {
+ if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+ mem_trace_cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr);
+ }
+ core_util_atomic_decr_u8(&trace_level, 1);
+ }
+}
+
+void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...) {
+ va_list va;
+ size_t temp_s1, temp_s2;
+ void *temp_ptr;
+
+ va_start(va, caller);
+ switch(op) {
+ case MBED_MEM_TRACE_MALLOC:
+ temp_s1 = va_arg(va, size_t);
+ printf(MBED_MEM_DEFAULT_TRACER_PREFIX "m:%p;%p-%u\n", res, caller, temp_s1);
+ break;
+
+ case MBED_MEM_TRACE_REALLOC:
+ temp_ptr = va_arg(va, void*);
+ temp_s1 = va_arg(va, size_t);
+ printf(MBED_MEM_DEFAULT_TRACER_PREFIX "r:%p;%p-%p;%u\n", res, caller, temp_ptr, temp_s1);
+ break;
+
+ case MBED_MEM_TRACE_CALLOC:
+ temp_s1 = va_arg(va, size_t);
+ temp_s2 = va_arg(va, size_t);
+ printf(MBED_MEM_DEFAULT_TRACER_PREFIX "c:%p;%p-%u;%u\n", res, caller, temp_s1, temp_s2);
+ break;
+
+ case MBED_MEM_TRACE_FREE:
+ temp_ptr = va_arg(va, void*);
+ printf(MBED_MEM_DEFAULT_TRACER_PREFIX "f:%p;%p-%p\n", res, caller, temp_ptr);
+ break;
+
+ default:
+ printf("?\n");
+ }
+ va_end(va);
+}
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_mem_trace.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,144 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MBED_MEM_TRACE_H__
+#define __MBED_MEM_TRACE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/* Operation types for tracer */
+enum {
+ MBED_MEM_TRACE_MALLOC,
+ MBED_MEM_TRACE_REALLOC,
+ MBED_MEM_TRACE_CALLOC,
+ MBED_MEM_TRACE_FREE
+};
+
+/* Prefix for the output of the default tracer */
+#define MBED_MEM_DEFAULT_TRACER_PREFIX "#"
+
+/**
+ * Type of the callback used by the memory tracer. This callback is called when a memory
+ * allocation operation (malloc, realloc, calloc, free) is called and tracing is enabled
+ * for that memory allocation function.
+ *
+ * @param op the ID of the operation (MBED_MEM_TRACE_MALLOC, MBED_MEM_TRACE_REALLOC,
+ * MBED_MEM_TRACE_CALLOC or MBED_MEM_TRACE_FREE).
+ * @param res the result that the memory operation returned (NULL for 'free').
+ * @param caller the caller of the memory operation. Note that the value of 'caller' might be
+ * unreliable.
+ *
+ * The rest of the parameters passed 'mbed_mem_trace_cb_t' are the same as the memory operations
+ * that triggered its call (see 'man malloc' for details):
+ *
+ * - for malloc: cb(MBED_MEM_TRACE_MALLOC, res, caller, size).
+ * - for realloc: cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size).
+ * - for calloc: cb(MBED_MEM_TRACE_CALLOC, res, caller, nmemb, size).
+ * - for free: cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr).
+ */
+typedef void (*mbed_mem_trace_cb_t)(uint8_t op, void *res, void* caller, ...);
+
+/**
+ * Set the callback used by the memory tracer (use NULL for disable tracing).
+ *
+ * @param cb the callback to call on each memory operation.
+ */
+void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb);
+
+/**
+ * Trace a call to 'malloc'.
+ * @param res the result of running 'malloc'.
+ * @param size the 'size' argument given to 'malloc'.
+ * @param caller the caller of the memory operation.
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_malloc(void *res, size_t size, void *caller);
+
+/**
+ * Trace a call to 'realloc'.
+ * @param res the result of running 'realloc'.
+ * @param ptr the 'ptr' argument given to 'realloc'.
+ * @param size the 'size' argument given to 'realloc'.
+ * @param caller the caller of the memory operation.
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller);
+
+/**
+ * Trace a call to 'calloc'.
+ * @param res the result of running 'calloc'.
+ * @param num the 'nmemb' argument given to 'calloc'.
+ * @param size the 'size' argument given to 'calloc'.
+ * @param caller the caller of the memory operation.
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller);
+
+/**
+ * Trace a call to 'free'.
+ * @param ptr the 'ptr' argument given to 'free'.
+ * @param caller the caller of the memory operation.
+ */
+void mbed_mem_trace_free(void *ptr, void *caller);
+
+/**
+ * Default memory trace callback. DO NOT CALL DIRECTLY. It is meant to be used
+ * as the second argument of 'mbed_mem_trace_setup'.
+ *
+ * The default callback outputs trace data using 'printf', in a format that's
+ * easily parsable by an external tool. For each memory operation, the callback
+ * outputs a line that begins with "#<op>:<0xresult>;<0xcaller>-":
+ *
+ * - 'op' identifies the memory operation ('m' for 'malloc', 'r' for 'realloc',
+ * 'c' for 'calloc' and 'f' for 'free').
+ * - 'result' (base 16) is the result of the memor operation. This is always NULL
+ * for 'free', since 'free' doesn't return anything.
+ * - 'caller' (base 16) is the caller of the memory operation. Note that the value
+ * of 'caller' might be unreliable.
+ *
+ * The rest of the output depends on the operation being traced:
+ *
+ * - for 'malloc': 'size', where 'size' is the original argument to 'malloc'.
+ * - for 'realloc': '0xptr;size', where 'ptr' (base 16) and 'size' are the original arguments to 'realloc'.
+ * - for 'calloc': 'nmemb;size', where 'nmemb' and 'size' are the original arguments to 'calloc'.
+ * - for 'free': '0xptr', where 'ptr' (base 16) is the original argument to 'free'.
+ *
+ * Examples:
+ *
+ * - "#m:0x20003240;0x600d-50" encodes a 'malloc' that returned 0x20003240, was called
+ * by the instruction at 0x600D with a the 'size' argument equal to 50.
+ * - "#f:0x0;0x602f-0x20003240" encodes a 'free' that was called by the instruction at
+ * 0x602f with the 'ptr' argument equal to 0x20003240.
+ */
+void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif// #ifndef __MBED_MEM_TRACE_H__
+
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_preprocessor.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,54 @@
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PREPROCESSOR_H
+#define MBED_PREPROCESSOR_H
+
+
+/** MBED_CONCAT
+ * Concatenate tokens together
+ *
+ * @note
+ * Expands tokens before concatenation
+ *
+ * @code
+ * // Creates a unique label based on the line number
+ * int MBED_CONCAT(UNIQUE_LABEL_, __LINE__) = 1;
+ * @endcode
+ */
+#define MBED_CONCAT(a, b) MBED_CONCAT_(a, b)
+#define MBED_CONCAT_(a, b) a##b
+
+/** MBED_STRINGIFY
+ * Converts tokens into strings
+ *
+ * @note
+ * Expands tokens before stringification
+ *
+ * @code
+ * // Creates a string based on the parameters
+ * const char *c = MBED_STRINGIFY(This is a ridiculous way to create a string)
+ * @endcode
+ */
+#define MBED_STRINGIFY(a) MBED_STRINGIFY_(a)
+#define MBED_STRINGIFY_(a) #a
+
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_retarget.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,1050 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform/platform.h"
+#include "platform/FilePath.h"
+#include "hal/serial_api.h"
+#include "platform/mbed_toolchain.h"
+#include "platform/mbed_semihost_api.h"
+#include "platform/mbed_interface.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_stats.h"
+#include "platform/mbed_critical.h"
+#include <stdlib.h>
+#include <string.h>
+#include <limits.h>
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+#include <errno.h>
+#include "platform/mbed_retarget.h"
+
+#if defined(__ARMCC_VERSION)
+# include <rt_sys.h>
+# define PREFIX(x) _sys##x
+# define OPEN_MAX _SYS_OPEN
+# ifdef __MICROLIB
+# pragma import(__use_full_stdio)
+# endif
+
+#elif defined(__ICCARM__)
+# include <yfuns.h>
+# define PREFIX(x) _##x
+# define OPEN_MAX 16
+
+# define STDIN_FILENO 0
+# define STDOUT_FILENO 1
+# define STDERR_FILENO 2
+
+#else
+# include <sys/stat.h>
+# include <sys/syslimits.h>
+# define PREFIX(x) x
+#endif
+
+#define FILE_HANDLE_RESERVED 0xFFFFFFFF
+
+using namespace mbed;
+
+#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+// Before version 5.03, we were using a patched version of microlib with proper names
+extern const char __stdin_name[] = ":tt";
+extern const char __stdout_name[] = ":tt";
+extern const char __stderr_name[] = ":tt";
+
+#else
+extern const char __stdin_name[] = "/stdin";
+extern const char __stdout_name[] = "/stdout";
+extern const char __stderr_name[] = "/stderr";
+#endif
+
+unsigned char *mbed_heap_start = 0;
+uint32_t mbed_heap_size = 0;
+
+/* newlib has the filehandle field in the FILE struct as a short, so
+ * we can't just return a Filehandle* from _open and instead have to
+ * put it in a filehandles array and return the index into that array
+ * (or rather index+3, as filehandles 0-2 are stdin/out/err).
+ */
+static FileHandle *filehandles[OPEN_MAX];
+static SingletonPtr<PlatformMutex> filehandle_mutex;
+
+namespace mbed {
+void remove_filehandle(FileHandle *file) {
+ filehandle_mutex->lock();
+ /* Remove all open filehandles for this */
+ for (unsigned int fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+ if (filehandles[fh_i] == file) {
+ filehandles[fh_i] = NULL;
+ }
+ }
+ filehandle_mutex->unlock();
+}
+}
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
+static char stdio_in_prev;
+static char stdio_out_prev;
+#endif
+#endif
+
+static void init_serial() {
+#if DEVICE_SERIAL
+ if (stdio_uart_inited) return;
+ serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
+#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE
+ serial_baud(&stdio_uart, MBED_CONF_PLATFORM_STDIO_BAUD_RATE);
+#endif
+#endif
+}
+
+/**
+ * Sets errno when file opening fails.
+ * Wipes out the filehandle too.
+ *
+ * @param error is a negative error code returned from an mbed function and
+ * will be negated to store a positive error code in errno
+ */
+static int handle_open_errors(int error, unsigned filehandle_idx) {
+ errno = -error;
+ // Free file handle
+ filehandles[filehandle_idx] = NULL;
+ return -1;
+}
+
+static inline int openmode_to_posix(int openmode) {
+ int posix = openmode;
+#ifdef __ARMCC_VERSION
+ if (openmode & OPEN_PLUS) {
+ posix = O_RDWR;
+ } else if(openmode & OPEN_W) {
+ posix = O_WRONLY;
+ } else if(openmode & OPEN_A) {
+ posix = O_WRONLY|O_APPEND;
+ } else {
+ posix = O_RDONLY;
+ }
+ /* a, w, a+, w+ all create if file does not already exist */
+ if (openmode & (OPEN_A|OPEN_W)) {
+ posix |= O_CREAT;
+ }
+ /* w and w+ truncate */
+ if (openmode & OPEN_W) {
+ posix |= O_TRUNC;
+ }
+#elif defined(__ICCARM__)
+ switch (openmode & _LLIO_RDWRMASK) {
+ case _LLIO_RDONLY: posix = O_RDONLY; break;
+ case _LLIO_WRONLY: posix = O_WRONLY; break;
+ case _LLIO_RDWR : posix = O_RDWR ; break;
+ }
+ if (openmode & _LLIO_CREAT ) posix |= O_CREAT;
+ if (openmode & _LLIO_APPEND) posix |= O_APPEND;
+ if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC;
+#elif defined(TOOLCHAIN_GCC)
+ posix &= ~O_BINARY;
+#endif
+ return posix;
+}
+
+// Internally used file objects with managed memory on close
+class ManagedFile : public FileHandle {
+public:
+ virtual int close() {
+ int err = FileHandle::close();
+ delete this;
+ return err;
+ }
+};
+
+class ManagedDir : public DirHandle {
+public:
+ virtual int close() {
+ int err = DirHandle::close();
+ delete this;
+ return err;
+ }
+};
+
+/* @brief standard c library fopen() retargeting function.
+ *
+ * This function is invoked by the standard c library retargeting to handle fopen()
+ *
+ * @return
+ * On success, a valid FILEHANDLE is returned.
+ * On failure, -1 is returned and errno is set to an appropriate value e.g.
+ * ENOENT file not found (default errno setting)
+ * EMFILE the maximum number of open files was exceeded.
+ *
+ * */
+extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
+ #if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+ // Before version 5.03, we were using a patched version of microlib with proper names
+ // This is the workaround that the microlib author suggested us
+ static int n = 0;
+ if (!std::strcmp(name, ":tt")) return n++;
+ #else
+ /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
+ */
+ if (std::strcmp(name, __stdin_name) == 0) {
+ init_serial();
+ return 0;
+ } else if (std::strcmp(name, __stdout_name) == 0) {
+ init_serial();
+ return 1;
+ } else if (std::strcmp(name, __stderr_name) == 0) {
+ init_serial();
+ return 2;
+ }
+ #endif
+
+ // find the first empty slot in filehandles
+ filehandle_mutex->lock();
+ unsigned int fh_i;
+ for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+ /* Take a next free filehandle slot available. */
+ if (filehandles[fh_i] == NULL) break;
+ }
+ if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) {
+ /* Too many file handles have been opened */
+ errno = EMFILE;
+ filehandle_mutex->unlock();
+ return -1;
+ }
+ filehandles[fh_i] = (FileHandle*)FILE_HANDLE_RESERVED;
+ filehandle_mutex->unlock();
+
+ FileHandle *res = NULL;
+
+ /* FILENAME: ":0x12345678" describes a FileHandle* */
+ if (name[0] == ':') {
+ void *p;
+ std::sscanf(name, ":%p", &p);
+ res = (FileHandle*)p;
+
+ /* FILENAME: "/file_system/file_name" */
+ } else {
+ FilePath path(name);
+
+ if (!path.exists()) {
+ /* The first part of the filename (between first 2 '/') is not a
+ * registered mount point in the namespace.
+ */
+ return handle_open_errors(-ENOENT, fh_i);
+ }
+
+ if (path.isFile()) {
+ res = path.file();
+ } else {
+ FileSystemHandle *fs = path.fileSystem();
+ if (fs == NULL) {
+ return handle_open_errors(-ENOENT, fh_i);
+ }
+ int posix_mode = openmode_to_posix(openmode);
+ int err = fs->open(&res, path.fileName(), posix_mode);
+ if (err) {
+ return handle_open_errors(err, fh_i);
+ }
+ }
+ }
+
+ filehandles[fh_i] = res;
+
+ return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err
+}
+
+extern "C" int PREFIX(_close)(FILEHANDLE fh) {
+ if (fh < 3) return 0;
+
+ FileHandle* fhc = filehandles[fh-3];
+ filehandles[fh-3] = NULL;
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ int err = fhc->close();
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t __write (int fh, const unsigned char *buffer, size_t length) {
+#else
+extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) {
+#endif
+ int n; // n is the number of bytes written
+
+#if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED
+ if (core_util_is_isr_active() || !core_util_are_interrupts_enabled()) {
+ error("Error - writing to a file in an ISR or critical section\r\n");
+ }
+#endif
+
+ if (fh < 3) {
+#if DEVICE_SERIAL
+ if (!stdio_uart_inited) init_serial();
+#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
+ for (unsigned int i = 0; i < length; i++) {
+ if (buffer[i] == '\n' && stdio_out_prev != '\r') {
+ serial_putc(&stdio_uart, '\r');
+ }
+ serial_putc(&stdio_uart, buffer[i]);
+ stdio_out_prev = buffer[i];
+ }
+#else
+ for (unsigned int i = 0; i < length; i++) {
+ serial_putc(&stdio_uart, buffer[i]);
+ }
+#endif
+#endif
+ n = length;
+ } else {
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ n = fhc->write(buffer, length);
+ if (n < 0) {
+ errno = -n;
+ }
+ }
+#ifdef __ARMCC_VERSION
+ return length-n;
+#else
+ return n;
+#endif
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t __read (int fh, unsigned char *buffer, size_t length) {
+#else
+extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) {
+#endif
+ int n; // n is the number of bytes read
+
+#if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED
+ if (core_util_is_isr_active() || !core_util_are_interrupts_enabled()) {
+ error("Error - reading from a file in an ISR or critical section\r\n");
+ }
+#endif
+
+ if (fh < 3) {
+ // only read a character at a time from stdin
+#if DEVICE_SERIAL
+ if (!stdio_uart_inited) init_serial();
+#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
+ while (true) {
+ char c = serial_getc(&stdio_uart);
+ if ((c == '\r' && stdio_in_prev != '\n') ||
+ (c == '\n' && stdio_in_prev != '\r')) {
+ stdio_in_prev = c;
+ *buffer = '\n';
+ break;
+ } else if ((c == '\r' && stdio_in_prev == '\n') ||
+ (c == '\n' && stdio_in_prev == '\r')) {
+ stdio_in_prev = c;
+ // onto next character
+ continue;
+ } else {
+ stdio_in_prev = c;
+ *buffer = c;
+ break;
+ }
+ }
+#else
+ *buffer = serial_getc(&stdio_uart);
+#endif
+#endif
+ n = 1;
+ } else {
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ n = fhc->read(buffer, length);
+ if (n < 0) {
+ errno = -n;
+ }
+ }
+#ifdef __ARMCC_VERSION
+ return length-n;
+#else
+ return n;
+#endif
+}
+
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_istty)(FILEHANDLE fh)
+#else
+extern "C" int _isatty(FILEHANDLE fh)
+#endif
+{
+ /* stdin, stdout and stderr should be tty */
+ if (fh < 3) return 1;
+
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) {
+ errno = EBADF;
+ return 0;
+ }
+
+ int tty = fhc->isatty();
+ if (tty < 0) {
+ errno = -tty;
+ return 0;
+ } else {
+ return tty;
+ }
+}
+
+extern "C"
+#if defined(__ARMCC_VERSION)
+int _sys_seek(FILEHANDLE fh, long offset)
+#elif defined(__ICCARM__)
+long __lseek(int fh, long offset, int whence)
+#else
+int _lseek(FILEHANDLE fh, int offset, int whence)
+#endif
+{
+#if defined(__ARMCC_VERSION)
+ int whence = SEEK_SET;
+#endif
+ if (fh < 3) {
+ errno = ESPIPE;
+ return -1;
+ }
+
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ off_t off = fhc->seek(offset, whence);
+ if (off < 0) {
+ errno = -off;
+ return -1;
+ }
+ // Assuming INT_MAX = LONG_MAX, so we don't care about prototype difference
+ if (off > INT_MAX) {
+ errno = EOVERFLOW;
+ return -1;
+ }
+ return off;
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_ensure)(FILEHANDLE fh) {
+ if (fh < 3) return 0;
+
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ int err = fhc->sync();
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+extern "C" long PREFIX(_flen)(FILEHANDLE fh) {
+ if (fh < 3) {
+ errno = EINVAL;
+ return -1;
+ }
+
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) {
+ errno = EBADF;
+ return -1;
+ }
+
+ off_t size = fhc->size();
+ if (size < 0) {
+ errno = -size;
+ return -1;
+ }
+ if (size > LONG_MAX) {
+ errno = EOVERFLOW;
+ return -1;
+ }
+ return size;
+}
+#endif
+
+
+#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
+extern "C" int _fstat(int fd, struct stat *st) {
+ if (fd < 3) {
+ st->st_mode = S_IFCHR;
+ return 0;
+ }
+ errno = EBADF;
+ return -1;
+}
+#endif
+
+namespace std {
+extern "C" int remove(const char *path) {
+ FilePath fp(path);
+ FileSystemHandle *fs = fp.fileSystem();
+ if (fs == NULL) {
+ errno = ENOENT;
+ return -1;
+ }
+
+ int err = fs->remove(fp.fileName());
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+extern "C" int rename(const char *oldname, const char *newname) {
+ FilePath fpOld(oldname);
+ FilePath fpNew(newname);
+ FileSystemHandle *fsOld = fpOld.fileSystem();
+ FileSystemHandle *fsNew = fpNew.fileSystem();
+
+ if (fsOld == NULL) {
+ errno = ENOENT;
+ return -1;
+ }
+
+ /* rename only if both files are on the same FS */
+ if (fsOld != fsNew) {
+ errno = EXDEV;
+ return -1;
+ }
+
+ int err = fsOld->rename(fpOld.fileName(), fpNew.fileName());
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+extern "C" char *tmpnam(char *s) {
+ errno = EBADF;
+ return NULL;
+}
+
+extern "C" FILE *tmpfile() {
+ errno = EBADF;
+ return NULL;
+}
+} // namespace std
+
+#ifdef __ARMCC_VERSION
+extern "C" char *_sys_command_string(char *cmd, int len) {
+ return NULL;
+}
+#endif
+
+extern "C" DIR *opendir(const char *path) {
+ FilePath fp(path);
+ FileSystemHandle* fs = fp.fileSystem();
+ if (fs == NULL) {
+ errno = ENOENT;
+ return NULL;
+ }
+
+ DirHandle *dir;
+ int err = fs->open(&dir, fp.fileName());
+ if (err < 0) {
+ errno = -err;
+ return NULL;
+ }
+
+ return dir;
+}
+
+extern "C" struct dirent *readdir(DIR *dir) {
+ static struct dirent ent;
+ int err = dir->read(&ent);
+ if (err < 1) {
+ if (err < 0) {
+ errno = -err;
+ }
+ return NULL;
+ }
+
+ return &ent;
+}
+
+extern "C" int closedir(DIR *dir) {
+ int err = dir->close();
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+extern "C" void rewinddir(DIR *dir) {
+ dir->rewind();
+}
+
+extern "C" off_t telldir(DIR *dir) {
+ return dir->tell();
+}
+
+extern "C" void seekdir(DIR *dir, off_t off) {
+ dir->seek(off);
+}
+
+extern "C" int mkdir(const char *path, mode_t mode) {
+ FilePath fp(path);
+ FileSystemHandle *fs = fp.fileSystem();
+ if (fs == NULL) return -1;
+
+ int err = fs->mkdir(fp.fileName(), mode);
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+extern "C" int stat(const char *path, struct stat *st) {
+ FilePath fp(path);
+ FileSystemHandle *fs = fp.fileSystem();
+ if (fs == NULL) return -1;
+
+ int err = fs->stat(fp.fileName(), st);
+ if (err < 0) {
+ errno = -err;
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+#if defined(TOOLCHAIN_GCC)
+/* prevents the exception handling name demangling code getting pulled in */
+#include "mbed_error.h"
+namespace __gnu_cxx {
+ void __verbose_terminate_handler() {
+ error("Exception");
+ }
+}
+extern "C" WEAK void __cxa_pure_virtual(void);
+extern "C" WEAK void __cxa_pure_virtual(void) {
+ exit(1);
+}
+
+#endif
+
+// Provide implementation of _sbrk (low-level dynamic memory allocation
+// routine) for GCC_ARM which compares new heap pointer with MSP instead of
+// SP. This make it compatible with RTX RTOS thread stacks.
+#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR)
+
+#if defined(TARGET_CORTEX_A)
+extern "C" uint32_t __HeapLimit;
+#endif
+
+// Turn off the errno macro and use actual global variable instead.
+#undef errno
+extern "C" int errno;
+
+// Dynamic memory allocation related syscall.
+#if defined(TARGET_NUMAKER_PFM_NUC472) || defined(TARGET_NUMAKER_PFM_M453)
+// Overwrite _sbrk() to support two region model (heap and stack are two distinct regions).
+// __wrap__sbrk() is implemented in:
+// TARGET_NUMAKER_PFM_NUC472 hal/targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/TOOLCHAIN_GCC_ARM/retarget.c
+// TARGET_NUMAKER_PFM_M453 hal/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c
+extern "C" void *__wrap__sbrk(int incr);
+extern "C" caddr_t _sbrk(int incr) {
+ return (caddr_t) __wrap__sbrk(incr);
+}
+#else
+// Linker defined symbol used by _sbrk to indicate where heap should start.
+extern "C" uint32_t __end__;
+extern "C" caddr_t _sbrk(int incr) {
+ static unsigned char* heap = (unsigned char*)&__end__;
+ unsigned char* prev_heap = heap;
+ unsigned char* new_heap = heap + incr;
+
+#if defined(TARGET_CORTEX_A)
+ if (new_heap >= (unsigned char*)&__HeapLimit) { /* __HeapLimit is end of heap section */
+#else
+ if (new_heap >= (unsigned char*)__get_MSP()) {
+#endif
+ errno = ENOMEM;
+ return (caddr_t)-1;
+ }
+
+ // Additional heap checking if set
+ if (mbed_heap_size && (new_heap >= mbed_heap_start + mbed_heap_size)) {
+ errno = ENOMEM;
+ return (caddr_t)-1;
+ }
+
+ heap = new_heap;
+ return (caddr_t) prev_heap;
+}
+#endif
+#endif
+
+#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR)
+extern "C" void _exit(int return_code) {
+#else
+namespace std {
+extern "C" void exit(int return_code) {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+#if MBED_CONF_PLATFORM_STDIO_FLUSH_AT_EXIT
+ fflush(stdout);
+ fflush(stderr);
+#endif
+#endif
+
+#if DEVICE_SEMIHOST
+ if (mbed_interface_connected()) {
+ semihost_exit();
+ }
+#endif
+ if (return_code) {
+ mbed_die();
+ }
+
+ while (1);
+}
+
+#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CR)
+} //namespace std
+#endif
+
+#if defined(TOOLCHAIN_ARM) || defined(TOOLCHAIN_GCC)
+
+// This series of function disable the registration of global destructors
+// in a dynamic table which will be called when the application exit.
+// In mbed, program never exit properly, it dies.
+// More informations about this topic for ARMCC here:
+// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/6449.html
+extern "C" {
+int __aeabi_atexit(void *object, void (*dtor)(void* /*this*/), void *handle) {
+ return 1;
+}
+
+int __cxa_atexit(void (*dtor)(void* /*this*/), void *object, void *handle) {
+ return 1;
+}
+
+void __cxa_finalize(void *handle) {
+}
+
+} // end of extern "C"
+
+#endif
+
+
+#if defined(TOOLCHAIN_GCC)
+
+/*
+ * Depending on how newlib is configured, it is often not enough to define
+ * __aeabi_atexit, __cxa_atexit and __cxa_finalize in order to override the
+ * behavior regarding the registration of handlers with atexit.
+ *
+ * To overcome this limitation, exit and atexit are overriden here.
+ */
+extern "C"{
+
+/**
+ * @brief Retarget of exit for GCC.
+ * @details Unlike the standard version, this function doesn't call any function
+ * registered with atexit before calling _exit.
+ */
+void __wrap_exit(int return_code) {
+ _exit(return_code);
+}
+
+/**
+ * @brief Retarget atexit from GCC.
+ * @details This function will always fail and never register any handler to be
+ * called at exit.
+ */
+int __wrap_atexit(void (*func)()) {
+ return 1;
+}
+
+}
+
+#endif
+
+
+
+namespace mbed {
+
+void mbed_set_unbuffered_stream(std::FILE *_file) {
+#if defined (__ICCARM__)
+ char buf[2];
+ std::setvbuf(_file,buf,_IONBF,NULL);
+#else
+ setbuf(_file, NULL);
+#endif
+}
+
+/* Applications are expected to use fdopen()
+ * not this function directly. This code had to live here because FILE and FileHandle
+ * processes are all linked together here.
+ */
+std::FILE *mbed_fdopen(FileHandle *fh, const char *mode)
+{
+ char buf[12]; /* :0x12345678 + null byte */
+ std::sprintf(buf, ":%p", fh);
+ std::FILE *stream = std::fopen(buf, mode);
+ /* newlib-nano doesn't appear to ever call _isatty itself, so
+ * happily fully buffers an interactive stream. Deal with that here.
+ */
+ if (stream && fh->isatty()) {
+ mbed_set_unbuffered_stream(stream);
+ }
+ return stream;
+}
+
+int mbed_getc(std::FILE *_file){
+#if defined (__ICCARM__)
+ /*This is only valid for unbuffered streams*/
+ int res = std::fgetc(_file);
+ if (res>=0){
+ _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+ _file->_Rend = _file->_Wend;
+ _file->_Next = _file->_Wend;
+ }
+ return res;
+#else
+ return std::fgetc(_file);
+#endif
+}
+
+char* mbed_gets(char*s, int size, std::FILE *_file){
+#if defined (__ICCARM__)
+ /*This is only valid for unbuffered streams*/
+ char *str = fgets(s,size,_file);
+ if (str!=NULL){
+ _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+ _file->_Rend = _file->_Wend;
+ _file->_Next = _file->_Wend;
+ }
+ return str;
+#else
+ return std::fgets(s,size,_file);
+#endif
+}
+
+} // namespace mbed
+
+#if defined (__ICCARM__)
+// Stub out locks when an rtos is not present
+extern "C" WEAK void __iar_system_Mtxinit(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_system_Mtxdst(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_system_Mtxlock(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_system_Mtxunlock(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxinit(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxdst(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxlock(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxunlock(__iar_Rmtx *mutex) {}
+#elif defined(__CC_ARM)
+// Do nothing
+#elif defined (__GNUC__)
+struct _reent;
+// Stub out locks when an rtos is not present
+extern "C" WEAK void __rtos_malloc_lock( struct _reent *_r ) {}
+extern "C" WEAK void __rtos_malloc_unlock( struct _reent *_r ) {}
+extern "C" WEAK void __rtos_env_lock( struct _reent *_r ) {}
+extern "C" WEAK void __rtos_env_unlock( struct _reent *_r ) {}
+
+extern "C" void __malloc_lock( struct _reent *_r )
+{
+ __rtos_malloc_lock(_r);
+}
+
+extern "C" void __malloc_unlock( struct _reent *_r )
+{
+ __rtos_malloc_unlock(_r);
+}
+
+extern "C" void __env_lock( struct _reent *_r )
+{
+ __rtos_env_lock(_r);
+}
+
+extern "C" void __env_unlock( struct _reent *_r )
+{
+ __rtos_env_unlock(_r);
+}
+
+#define CXA_GUARD_INIT_DONE (1 << 0)
+#define CXA_GUARD_INIT_IN_PROGRESS (1 << 1)
+#define CXA_GUARD_MASK (CXA_GUARD_INIT_DONE | CXA_GUARD_INIT_IN_PROGRESS)
+
+extern "C" int __cxa_guard_acquire(int *guard_object_p)
+{
+ uint8_t *guard_object = (uint8_t *)guard_object_p;
+ if (CXA_GUARD_INIT_DONE == (*guard_object & CXA_GUARD_MASK)) {
+ return 0;
+ }
+ singleton_lock();
+ if (CXA_GUARD_INIT_DONE == (*guard_object & CXA_GUARD_MASK)) {
+ singleton_unlock();
+ return 0;
+ }
+ MBED_ASSERT(0 == (*guard_object & CXA_GUARD_MASK));
+ *guard_object = *guard_object | CXA_GUARD_INIT_IN_PROGRESS;
+ return 1;
+}
+
+extern "C" void __cxa_guard_release(int *guard_object_p)
+{
+ uint8_t *guard_object = (uint8_t *)guard_object_p;
+ MBED_ASSERT(CXA_GUARD_INIT_IN_PROGRESS == (*guard_object & CXA_GUARD_MASK));
+ *guard_object = (*guard_object & ~CXA_GUARD_MASK) | CXA_GUARD_INIT_DONE;
+ singleton_unlock();
+}
+
+extern "C" void __cxa_guard_abort(int *guard_object_p)
+{
+ uint8_t *guard_object = (uint8_t *)guard_object_p;
+ MBED_ASSERT(CXA_GUARD_INIT_IN_PROGRESS == (*guard_object & CXA_GUARD_MASK));
+ *guard_object = *guard_object & ~CXA_GUARD_INIT_IN_PROGRESS;
+ singleton_unlock();
+}
+
+#endif
+
+void *operator new(std::size_t count)
+{
+ void *buffer = malloc(count);
+ if (NULL == buffer) {
+ error("Operator new out of memory\r\n");
+ }
+ return buffer;
+}
+
+void *operator new[](std::size_t count)
+{
+ void *buffer = malloc(count);
+ if (NULL == buffer) {
+ error("Operator new[] out of memory\r\n");
+ }
+ return buffer;
+}
+
+void operator delete(void *ptr)
+{
+ if (ptr != NULL) {
+ free(ptr);
+ }
+}
+void operator delete[](void *ptr)
+{
+ if (ptr != NULL) {
+ free(ptr);
+ }
+}
+
+#if defined(MBED_CONF_RTOS_PRESENT) && defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED
+
+static const char* error_msg(int32_t status)
+{
+ switch (status) {
+ case osError:
+ return "Unspecified RTOS error";
+ case osErrorTimeout:
+ return "Operation not completed within the timeout period";
+ case osErrorResource:
+ return "Resource not available";
+ case osErrorParameter:
+ return "Parameter error";
+ case osErrorNoMemory:
+ return "System is out of memory";
+ case osErrorISR:
+ return "Not allowed in ISR context";
+ default:
+ return "Unknown";
+ }
+}
+
+extern "C" void EvrRtxKernelError (int32_t status)
+{
+ error("Kernel error %i: %s\r\n", status, error_msg(status));
+}
+
+extern "C" void EvrRtxThreadError (osThreadId_t thread_id, int32_t status)
+{
+ error("Thread %p error %i: %s\r\n", thread_id, status, error_msg(status));
+}
+
+extern "C" void EvrRtxTimerError (osTimerId_t timer_id, int32_t status)
+{
+ error("Timer %p error %i: %s\r\n", timer_id, status, error_msg(status));
+}
+
+extern "C" void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status)
+{
+ error("Event %p error %i: %s\r\n", ef_id, status, error_msg(status));
+}
+
+extern "C" void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status)
+{
+ error("Mutex %p error %i: %s\r\n", mutex_id, status, error_msg(status));
+}
+
+extern "C" void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status)
+{
+ error("Semaphore %p error %i\r\n", semaphore_id, status);
+}
+
+extern "C" void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status)
+{
+ error("Memory Pool %p error %i\r\n", mp_id, status);
+}
+
+extern "C" void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status)
+{
+ error("Message Queue %p error %i\r\n", mq_id, status);
+}
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_retarget.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,187 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef RETARGET_H
+#define RETARGET_H
+
+#if __cplusplus
+#include <cstdio>
+#endif //__cplusplus
+#include <stdint.h>
+#include <stddef.h>
+
+/* We can get the following standard types from sys/types for gcc, but we
+ * need to define the types ourselves for the other compilers that normally
+ * target embedded systems */
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+typedef int ssize_t; ///< Signed size type, usually encodes negative errors
+typedef long off_t; ///< Offset in a data stream
+typedef int mode_t; ///< Mode for opening files
+
+#define O_RDONLY 0
+#define O_WRONLY 1
+#define O_RDWR 2
+#define O_CREAT 0x0200
+#define O_TRUNC 0x0400
+#define O_APPEND 0x0008
+
+#define NAME_MAX 255 ///< Maximum size of a name in a file path
+
+#else
+#include <sys/fcntl.h>
+#include <sys/types.h>
+#include <sys/syslimits.h>
+#endif
+
+
+/* DIR declarations must also be here */
+#if __cplusplus
+namespace mbed {
+class FileHandle;
+class DirHandle;
+std::FILE *mbed_fdopen(FileHandle *fh, const char *mode);
+}
+typedef mbed::DirHandle DIR;
+#else
+typedef struct Dir DIR;
+#endif
+
+#if __cplusplus
+extern "C" {
+#endif
+ DIR *opendir(const char*);
+ struct dirent *readdir(DIR *);
+ int closedir(DIR*);
+ void rewinddir(DIR*);
+ long telldir(DIR*);
+ void seekdir(DIR*, long);
+ int mkdir(const char *name, mode_t n);
+#if __cplusplus
+};
+#endif
+
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+/* The intent of this section is to unify the errno error values to match
+ * the POSIX definitions for the GCC_ARM, ARMCC and IAR compilers. This is
+ * necessary because the ARMCC/IAR errno.h, or sys/stat.h are missing some
+ * symbol definitions used by the POSIX filesystem API to return errno codes.
+ * Note also that ARMCC errno.h defines some symbol values differently from
+ * the GCC_ARM/IAR/standard POSIX definitions. The definitions guard against
+ * this and future changes by changing the symbol definition as shown below. */
+#undef ENOENT
+#define ENOENT 2 /* No such file or directory. */
+
+#undef EIO
+#define EIO 5 /* I/O error */
+
+#undef ENXIO
+#define ENXIO 6 /* No such device or address */
+
+#undef ENOEXEC
+#define ENOEXEC 8 /* Exec format error */
+
+#undef EBADF
+#define EBADF 9 /* Bad file number */
+
+#undef EAGAIN
+#define EAGAIN 11 /* Resource unavailable, try again */
+
+#undef EWOULDBLOCK
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+
+#undef ENOMEM
+#define ENOMEM 12 /* Not enough space */
+
+#undef EACCES
+#define EACCES 13 /* Permission denied */
+
+#undef EFAULT
+#define EFAULT 14 /* Bad address */
+
+#undef EEXIST
+#define EEXIST 17 /* File exists */
+
+#undef EXDEV
+#define EXDEV 18 /* Cross-device link */
+
+#undef EINVAL
+#define EINVAL 22 /* Invalid argument */
+
+#undef ENFILE
+#define ENFILE 23 /* Too many open files in system */
+
+#undef EMFILE
+#define EMFILE 24 /* File descriptor value too large */
+
+#undef ESPIPE
+#define ESPIPE 29 /* Invalid seek */
+
+#undef ENOSYS
+#define ENOSYS 38 /* Function not implemented */
+
+#undef EOVERFLOW
+#define EOVERFLOW 75 /* Value too large to be stored in data type */
+
+/* Missing stat.h defines.
+ * The following are sys/stat.h definitions not currently present in the ARMCC
+ * errno.h. Note, ARMCC errno.h defines some symbol values differing from
+ * GCC_ARM/IAR/standard POSIX definitions. Guard against this and future
+ * changes by changing the symbol definition for filesystem use. */
+#define _IFDIR 0040000 /* directory */
+#define _IFREG 0100000 /* regular */
+
+#define S_IFDIR _IFDIR
+#define S_IFREG _IFREG
+
+#define S_IRWXU (S_IRUSR | S_IWUSR | S_IXUSR)
+#define S_IRUSR 0000400 /* read permission, owner */
+#define S_IWUSR 0000200 /* write permission, owner */
+#define S_IXUSR 0000100/* execute/search permission, owner */
+#define S_IRWXG (S_IRGRP | S_IWGRP | S_IXGRP)
+#define S_IRGRP 0000040 /* read permission, group */
+#define S_IWGRP 0000020 /* write permission, grougroup */
+#define S_IXGRP 0000010/* execute/search permission, group */
+#define S_IRWXO (S_IROTH | S_IWOTH | S_IXOTH)
+#define S_IROTH 0000004 /* read permission, other */
+#define S_IWOTH 0000002 /* write permission, other */
+#define S_IXOTH 0000001/* execute/search permission, other */
+
+#endif /* defined(__ARMCC_VERSION) || defined(__ICCARM__) */
+
+
+/* The following are dirent.h definitions are declared here to garuntee
+ * consistency where structure may be different with different toolchains */
+struct dirent {
+ char d_name[NAME_MAX+1];
+ uint8_t d_type;
+};
+
+enum {
+ DT_UNKNOWN, // The file type could not be determined.
+ DT_FIFO, // This is a named pipe (FIFO).
+ DT_CHR, // This is a character device.
+ DT_DIR, // This is a directory.
+ DT_BLK, // This is a block device.
+ DT_REG, // This is a regular file.
+ DT_LNK, // This is a symbolic link.
+ DT_SOCK, // This is a UNIX domain socket.
+};
+
+#endif /* RETARGET_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_rtc_time.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,101 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/rtc_api.h"
+
+#include <time.h>
+#include "platform/mbed_critical.h"
+#include "platform/mbed_rtc_time.h"
+#include "hal/us_ticker_api.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
+
+static SingletonPtr<PlatformMutex> _mutex;
+
+#if DEVICE_RTC
+static void (*_rtc_init)(void) = rtc_init;
+static int (*_rtc_isenabled)(void) = rtc_isenabled;
+static time_t (*_rtc_read)(void) = rtc_read;
+static void (*_rtc_write)(time_t t) = rtc_write;
+#else
+static void (*_rtc_init)(void) = NULL;
+static int (*_rtc_isenabled)(void) = NULL;
+static time_t (*_rtc_read)(void) = NULL;
+static void (*_rtc_write)(time_t t) = NULL;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if defined (__ICCARM__)
+time_t __time32(time_t *timer)
+#else
+time_t time(time_t *timer)
+#endif
+
+{
+ _mutex->lock();
+ if (_rtc_isenabled != NULL) {
+ if (!(_rtc_isenabled())) {
+ set_time(0);
+ }
+ }
+
+ time_t t = 0;
+ if (_rtc_read != NULL) {
+ t = _rtc_read();
+ }
+
+ if (timer != NULL) {
+ *timer = t;
+ }
+ _mutex->unlock();
+ return t;
+}
+
+void set_time(time_t t) {
+ _mutex->lock();
+ if (_rtc_init != NULL) {
+ _rtc_init();
+ }
+ if (_rtc_write != NULL) {
+ _rtc_write(t);
+ }
+ _mutex->unlock();
+}
+
+clock_t clock() {
+ _mutex->lock();
+ clock_t t = us_ticker_read();
+ t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
+ _mutex->unlock();
+ return t;
+}
+
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)) {
+ _mutex->lock();
+ _rtc_read = read_rtc;
+ _rtc_write = write_rtc;
+ _rtc_init = init_rtc;
+ _rtc_isenabled = isenabled_rtc;
+ _mutex->unlock();
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_rtc_time.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,93 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Implementation of the C time.h functions
+ *
+ * Provides mechanisms to set and read the current time, based
+ * on the microcontroller Real-Time Clock (RTC), plus some
+ * standard C manipulation and formating functions.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ * set_time(1256729737); // Set RTC time to Wed, 28 Oct 2009 11:35:37
+ *
+ * while(1) {
+ * time_t seconds = time(NULL);
+ *
+ * printf("Time as seconds since January 1, 1970 = %d\n", seconds);
+ *
+ * printf("Time as a basic string = %s", ctime(&seconds));
+ *
+ * char buffer[32];
+ * strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
+ * printf("Time as a custom formatted string = %s", buffer);
+ *
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ */
+
+/** Set the current time
+ *
+ * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
+ * to the time represented by the number of seconds since January 1, 1970
+ * (the UNIX timestamp).
+ *
+ * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ * set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
+ * }
+ * @endcode
+ */
+void set_time(time_t t);
+
+/** Attach an external RTC to be used for the C time functions
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * @param read_rtc pointer to function which returns current UNIX timestamp
+ * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
+ * @param init_rtc pointer to funtion which initializes RTC, can be NULL
+ * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL
+ */
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_semihost_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,164 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#include "platform/mbed_semihost_api.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#if DEVICE_SEMIHOST
+
+// ARM Semihosting Commands
+#define SYS_OPEN (0x1)
+#define SYS_CLOSE (0x2)
+#define SYS_WRITE (0x5)
+#define SYS_READ (0x6)
+#define SYS_ISTTY (0x9)
+#define SYS_SEEK (0xa)
+#define SYS_ENSURE (0xb)
+#define SYS_FLEN (0xc)
+#define SYS_REMOVE (0xe)
+#define SYS_RENAME (0xf)
+#define SYS_EXIT (0x18)
+
+// mbed Semihosting Commands
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) // 0x100 - 0x1ff
+#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
+#define USR_UID (RESERVED_FOR_USER_APPLICATIONS + 1)
+#define USR_RESET (RESERVED_FOR_USER_APPLICATIONS + 2)
+#define USR_VBUS (RESERVED_FOR_USER_APPLICATIONS + 3)
+#define USR_POWERDOWN (RESERVED_FOR_USER_APPLICATIONS + 4)
+#define USR_DISABLEDEBUG (RESERVED_FOR_USER_APPLICATIONS + 5)
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode) {
+ uint32_t args[3];
+ args[0] = (uint32_t)name;
+ args[1] = (uint32_t)openmode;
+ args[2] = (uint32_t)strlen(name);
+ return __semihost(SYS_OPEN, args);
+}
+
+int semihost_close(FILEHANDLE fh) {
+ return __semihost(SYS_CLOSE, &fh);
+}
+
+int semihost_write(FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode) {
+ if (length == 0) return 0;
+
+ uint32_t args[3];
+ args[0] = (uint32_t)fh;
+ args[1] = (uint32_t)buffer;
+ args[2] = (uint32_t)length;
+ return __semihost(SYS_WRITE, args);
+}
+
+int semihost_read(FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode) {
+ uint32_t args[3];
+ args[0] = (uint32_t)fh;
+ args[1] = (uint32_t)buffer;
+ args[2] = (uint32_t)length;
+ return __semihost(SYS_READ, args);
+}
+
+int semihost_istty(FILEHANDLE fh) {
+ return __semihost(SYS_ISTTY, &fh);
+}
+
+int semihost_seek(FILEHANDLE fh, long position) {
+ uint32_t args[2];
+ args[0] = (uint32_t)fh;
+ args[1] = (uint32_t)position;
+ return __semihost(SYS_SEEK, args);
+}
+
+int semihost_ensure(FILEHANDLE fh) {
+ return __semihost(SYS_ENSURE, &fh);
+}
+
+long semihost_flen(FILEHANDLE fh) {
+ return __semihost(SYS_FLEN, &fh);
+}
+
+int semihost_remove(const char *name) {
+ uint32_t args[2];
+ args[0] = (uint32_t)name;
+ args[1] = (uint32_t)strlen(name);
+ return __semihost(SYS_REMOVE, args);
+}
+
+int semihost_rename(const char *old_name, const char *new_name) {
+ uint32_t args[4];
+ args[0] = (uint32_t)old_name;
+ args[1] = (uint32_t)strlen(old_name);
+ args[0] = (uint32_t)new_name;
+ args[1] = (uint32_t)strlen(new_name);
+ return __semihost(SYS_RENAME, args);
+}
+#endif
+
+int semihost_exit(void) {
+ uint32_t args[4];
+ return __semihost(SYS_EXIT, args);
+}
+
+int semihost_uid(char *uid) {
+ uint32_t args[2];
+ args[0] = (uint32_t)uid;
+ args[1] = DEVICE_ID_LENGTH + 1;
+ return __semihost(USR_UID, &args);
+}
+
+int semihost_reset(void) {
+ // Does not normally return, however if used with older firmware versions
+ // that do not support this call it will return -1.
+ return __semihost(USR_RESET, NULL);
+}
+
+int semihost_vbus(void) {
+ return __semihost(USR_VBUS, NULL);
+}
+
+int semihost_powerdown(void) {
+ return __semihost(USR_POWERDOWN, NULL);
+}
+
+#if DEVICE_DEBUG_AWARENESS
+
+int semihost_connected(void) {
+ return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? 1 : 0;
+}
+
+#else
+// These processors cannot know if the interface is connect, assume so:
+static int is_debugger_attached = 1;
+
+int semihost_connected(void) {
+ return is_debugger_attached;
+}
+#endif
+
+int semihost_disabledebug(void) {
+ uint32_t args[1];
+#if !(DEVICE_DEBUG_AWARENESS)
+ is_debugger_attached = 0;
+#endif
+ return __semihost(USR_DISABLEDEBUG, &args);
+}
+
+#endif
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_semihost_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,99 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SEMIHOST_H
+#define MBED_SEMIHOST_H
+
+#include "device.h"
+#include "platform/mbed_toolchain.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+#ifndef __CC_ARM
+
+#if defined(__ICCARM__)
+static inline int __semihost(int reason, const void *arg) {
+ return __semihosting(reason, (void*)arg);
+}
+#else
+
+#ifdef __thumb__
+# define AngelSWI 0xAB
+# define AngelSWIInsn "bkpt"
+# define AngelSWIAsm bkpt
+#else
+# define AngelSWI 0x123456
+# define AngelSWIInsn "swi"
+# define AngelSWIAsm swi
+#endif
+
+static inline int __semihost(int reason, const void *arg) {
+ int value;
+
+ asm volatile (
+ "mov r0, %1" "\n\t"
+ "mov r1, %2" "\n\t"
+ AngelSWIInsn " %a3" "\n\t"
+ "mov %0, r0"
+ : "=r" (value) /* output operands */
+ : "r" (reason), "r" (arg), "i" (AngelSWI) /* input operands */
+ : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" /* list of clobbered registers */
+ );
+
+ return value;
+}
+#endif
+#endif
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode);
+int semihost_close (FILEHANDLE fh);
+int semihost_read (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);
+int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);
+int semihost_ensure(FILEHANDLE fh);
+long semihost_flen (FILEHANDLE fh);
+int semihost_seek (FILEHANDLE fh, long position);
+int semihost_istty (FILEHANDLE fh);
+
+int semihost_remove(const char *name);
+int semihost_rename(const char *old_name, const char *new_name);
+#endif
+
+int semihost_uid(char *uid);
+int semihost_reset(void);
+int semihost_vbus(void);
+int semihost_powerdown(void);
+int semihost_exit(void);
+
+int semihost_connected(void);
+int semihost_disabledebug(void);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_sleep.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,92 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SLEEP_H
+#define MBED_SLEEP_H
+
+#include "sleep_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Send the microcontroller to sleep
+ *
+ * @note This function can be a noop if not implemented by the platform.
+ * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined).
+ * @note This function will be a noop while uVisor is in use.
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+__INLINE static void sleep(void)
+{
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+#ifndef MBED_DEBUG
+#if DEVICE_SLEEP
+ hal_sleep();
+#endif /* DEVICE_SLEEP */
+#endif /* MBED_DEBUG */
+#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
+}
+
+/** Send the microcontroller to deep sleep
+ *
+ * @note This function can be a noop if not implemented by the platform.
+ * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined)
+ * @note This function will be a noop while uVisor is in use.
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+__INLINE static void deepsleep(void)
+{
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+#ifndef MBED_DEBUG
+#if DEVICE_SLEEP
+ hal_deepsleep();
+#endif /* DEVICE_SLEEP */
+#endif /* MBED_DEBUG */
+#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_stats.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,71 @@
+#include "mbed_stats.h"
+#include <string.h>
+#include <stdlib.h>
+#include "mbed_assert.h"
+
+#if MBED_CONF_RTOS_PRESENT
+#include "cmsis_os2.h"
+#endif
+
+// note: mbed_stats_heap_get defined in mbed_alloc_wrappers.cpp
+
+void mbed_stats_stack_get(mbed_stats_stack_t *stats)
+{
+ memset(stats, 0, sizeof(mbed_stats_stack_t));
+
+#if MBED_STACK_STATS_ENABLED && MBED_CONF_RTOS_PRESENT
+ uint32_t thread_n = osThreadGetCount();
+ unsigned i;
+ osThreadId_t *threads;
+
+ threads = malloc(sizeof(osThreadId_t) * thread_n);
+ MBED_ASSERT(threads != NULL);
+
+ osKernelLock();
+ thread_n = osThreadEnumerate(threads, thread_n);
+
+ for(i = 0; i < thread_n; i++) {
+ uint32_t stack_size = osThreadGetStackSize(threads[i]);
+ stats->max_size += stack_size - osThreadGetStackSpace(threads[i]);
+ stats->reserved_size += stack_size;
+ stats->stack_cnt++;
+ }
+ osKernelUnlock();
+
+ free(threads);
+#endif
+}
+
+size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count)
+{
+ memset(stats, 0, count*sizeof(mbed_stats_stack_t));
+ size_t i = 0;
+
+#if MBED_STACK_STATS_ENABLED && MBED_CONF_RTOS_PRESENT
+ osThreadId_t *threads;
+
+ threads = malloc(sizeof(osThreadId_t) * count);
+ MBED_ASSERT(threads != NULL);
+
+ osKernelLock();
+ count = osThreadEnumerate(threads, count);
+
+ for(i = 0; i < count; i++) {
+ uint32_t stack_size = osThreadGetStackSize(threads[i]);
+ stats[i].max_size = stack_size - osThreadGetStackSpace(threads[i]);
+ stats[i].reserved_size = stack_size;
+ stats[i].thread_id = (uint32_t)threads[i];
+ stats[i].stack_cnt = 1;
+ }
+ osKernelUnlock();
+
+ free(threads);
+#endif
+
+ return i;
+}
+
+#if MBED_STACK_STATS_ENABLED && !MBED_CONF_RTOS_PRESENT
+#warning Stack statistics are currently not supported without the rtos.
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_stats.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,76 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2016-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STATS_H
+#define MBED_STATS_H
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ uint32_t current_size; /**< Bytes allocated currently. */
+ uint32_t max_size; /**< Max bytes allocated at a given time. */
+ uint32_t total_size; /**< Cumulative sum of bytes ever allocated. */
+ uint32_t reserved_size; /**< Current number of bytes allocated for the heap. */
+ uint32_t alloc_cnt; /**< Current number of allocations. */
+ uint32_t alloc_fail_cnt; /**< Number of failed allocations. */
+} mbed_stats_heap_t;
+
+/**
+ * Fill the passed in heap stat structure with heap stats.
+ *
+ * @param stats A pointer to the mbed_stats_heap_t structure to fill
+ */
+void mbed_stats_heap_get(mbed_stats_heap_t *stats);
+
+typedef struct {
+ uint32_t thread_id; /**< Identifier for thread that owns the stack. */
+ uint32_t max_size; /**< Sum of the maximum number of bytes used in each stack. */
+ uint32_t reserved_size; /**< Current number of bytes allocated for all stacks. */
+ uint32_t stack_cnt; /**< Number of stacks currently allocated. */
+} mbed_stats_stack_t;
+
+/**
+ * Fill the passed in structure with stack stats.
+ *
+ * @param stats A pointer to the mbed_stats_stack_t structure to fill
+ */
+void mbed_stats_stack_get(mbed_stats_stack_t *stats);
+
+/**
+ * Fill the passed array of stat structures with the stack stats
+ * for each available stack.
+ *
+ * @param stats A pointer to an array of mbed_stats_stack_t structures to fill
+ * @param count The number of mbed_stats_stack_t structures in the provided array
+ * @return The number of mbed_stats_stack_t structures that have been filled,
+ * this is equal to the number of stacks on the system.
+ */
+size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_toolchain.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,338 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TOOLCHAIN_H
+#define MBED_TOOLCHAIN_H
+
+#include "mbed_preprocessor.h"
+
+
+// Warning for unsupported compilers
+#if !defined(__GNUC__) /* GCC */ \
+ && !defined(__CC_ARM) /* ARMCC */ \
+ && !defined(__clang__) /* LLVM/Clang */ \
+ && !defined(__ICCARM__) /* IAR */
+#warning "This compiler is not yet supported."
+#endif
+
+
+// Attributes
+
+/** MBED_PACKED
+ * Pack a structure, preventing any padding from being added between fields.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_PACKED(struct) foo {
+ * char x;
+ * int y;
+ * };
+ * @endcode
+ */
+#ifndef MBED_PACKED
+#if defined(__ICCARM__)
+#define MBED_PACKED(struct) __packed struct
+#else
+#define MBED_PACKED(struct) struct __attribute__((packed))
+#endif
+#endif
+
+/** MBED_ALIGN(N)
+ * Declare a variable to be aligned on an N-byte boundary.
+ *
+ * @note
+ * IAR does not support alignment greater than word size on the stack
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_ALIGN(16) char a;
+ * @endcode
+ */
+#ifndef MBED_ALIGN
+#if defined(__ICCARM__)
+#define MBED_ALIGN(N) _Pragma(MBED_STRINGIFY(data_alignment=N))
+#else
+#define MBED_ALIGN(N) __attribute__((aligned(N)))
+#endif
+#endif
+
+/** MBED_UNUSED
+ * Declare a function argument to be unused, suppressing compiler warnings
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * void foo(MBED_UNUSED int arg) {
+ *
+ * }
+ * @endcode
+ */
+#ifndef MBED_UNUSED
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_UNUSED __attribute__((__unused__))
+#else
+#define MBED_UNUSED
+#endif
+#endif
+
+/** MBED_WEAK
+ * Mark a function as being weak.
+ *
+ * @note
+ * weak functions are not friendly to making code re-usable, as they can only
+ * be overridden once (and if they are multiply overridden the linker will emit
+ * no warning). You should not normally use weak symbols as part of the API to
+ * re-usable modules.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_WEAK void foo() {
+ * // a weak implementation of foo that can be overriden by a definition
+ * // without __weak
+ * }
+ * @endcode
+ */
+#ifndef MBED_WEAK
+#if defined(__ICCARM__)
+#define MBED_WEAK __weak
+#else
+#define MBED_WEAK __attribute__((weak))
+#endif
+#endif
+
+/** MBED_PURE
+ * Hint to the compiler that a function depends only on parameters
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_PURE int foo(int arg){
+ * // no access to global variables
+ * }
+ * @endcode
+ */
+#ifndef MBED_PURE
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_PURE __attribute__((const))
+#else
+#define MBED_PURE
+#endif
+#endif
+
+/** MBED_FORCEINLINE
+ * Declare a function that must always be inlined. Failure to inline
+ * such a function will result in an error.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_FORCEINLINE void foo() {
+ *
+ * }
+ * @endcode
+ */
+#ifndef MBED_FORCEINLINE
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_FORCEINLINE static inline __attribute__((always_inline))
+#elif defined(__ICCARM__)
+#define MBED_FORCEINLINE _Pragma("inline=forced") static
+#else
+#define MBED_FORCEINLINE static inline
+#endif
+#endif
+
+/** MBED_NORETURN
+ * Declare a function that will never return.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_NORETURN void foo() {
+ * // must never return
+ * while (1) {}
+ * }
+ * @endcode
+ */
+#ifndef MBED_NORETURN
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_NORETURN __attribute__((noreturn))
+#elif defined(__ICCARM__)
+#define MBED_NORETURN __noreturn
+#else
+#define MBED_NORETURN
+#endif
+#endif
+
+/** MBED_UNREACHABLE
+ * An unreachable statement. If the statement is reached,
+ * behaviour is undefined. Useful in situations where the compiler
+ * cannot deduce the unreachability of code.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * void foo(int arg) {
+ * switch (arg) {
+ * case 1: return 1;
+ * case 2: return 2;
+ * ...
+ * }
+ * MBED_UNREACHABLE;
+ * }
+ * @endcode
+ */
+#ifndef MBED_UNREACHABLE
+#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM)
+#define MBED_UNREACHABLE __builtin_unreachable()
+#else
+#define MBED_UNREACHABLE while (1)
+#endif
+#endif
+
+/** MBED_DEPRECATED("message string")
+ * Mark a function declaration as deprecated, if it used then a warning will be
+ * issued by the compiler possibly including the provided message. Note that not
+ * all compilers are able to display the message.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_DEPRECATED("don't foo any more, bar instead")
+ * void foo(int arg);
+ * @endcode
+ */
+#ifndef MBED_DEPRECATED
+#if defined(__CC_ARM)
+#define MBED_DEPRECATED(M) __attribute__((deprecated))
+#elif defined(__GNUC__) || defined(__clang__)
+#define MBED_DEPRECATED(M) __attribute__((deprecated(M)))
+#else
+#define MBED_DEPRECATED(M)
+#endif
+#endif
+
+/** MBED_DEPRECATED_SINCE("version", "message string")
+ * Mark a function declaration as deprecated, noting that the declaration was
+ * deprecated on the specified version. If the function is used then a warning
+ * will be issued by the compiler possibly including the provided message.
+ * Note that not all compilers are able to display this message.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * MBED_DEPRECATED_SINCE("mbed-os-5.1", "don't foo any more, bar instead")
+ * void foo(int arg);
+ * @endcode
+ */
+#define MBED_DEPRECATED_SINCE(D, M) MBED_DEPRECATED(M " [since " D "]")
+
+/** MBED_CALLER_ADDR()
+ * Returns the caller of the current function.
+ *
+ * @note
+ * This macro is only implemented for GCC and ARMCC.
+ *
+ * @code
+ * #include "mbed_toolchain.h"
+ *
+ * printf("This function was called from %p", MBED_CALLER_ADDR());
+ * @endcode
+ *
+ * @return Address of the calling function
+ */
+#ifndef MBED_CALLER_ADDR
+#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM)
+#define MBED_CALLER_ADDR() __builtin_extract_return_addr(__builtin_return_address(0))
+#elif defined(__CC_ARM)
+#define MBED_CALLER_ADDR() __builtin_return_address(0)
+#else
+#define MBED_CALLER_ADDR() (NULL)
+#endif
+#endif
+
+#ifndef MBED_SECTION
+#if (defined(__GNUC__) || defined(__clang__)) || defined(__CC_ARM)
+#define MBED_SECTION(name) __attribute__ ((section (name)))
+#elif defined(__ICCARM__)
+#define MBED_SECTION(name) _Pragma(MBED_STRINGIFY(location=name))
+#else
+#error "Missing MBED_SECTION directive"
+#endif
+#endif
+
+#ifndef MBED_PRINTF
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_PRINTF(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx, first_param_idx)))
+#else
+#define MBED_PRINTF(format_idx, first_param_idx)
+#endif
+#endif
+
+#ifndef MBED_PRINTF_METHOD
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_PRINTF_METHOD(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx+1, first_param_idx+1)))
+#else
+#define MBED_PRINTF_METHOD(format_idx, first_param_idx)
+#endif
+#endif
+
+#ifndef MBED_SCANF
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_SCANF(format_idx, first_param_idx) __attribute__ ((__format__(__scanf__, format_idx, first_param_idx)))
+#else
+#define MBED_SCANF(format_idx, first_param_idx)
+#endif
+#endif
+
+#ifndef MBED_SCANF_METHOD
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MBED_SCANF_METHOD(format_idx, first_param_idx) __attribute__ ((__format__(__scanf__, format_idx+1, first_param_idx+1)))
+#else
+#define MBED_SCANF_METHOD(format_idx, first_param_idx)
+#endif
+#endif
+
+// FILEHANDLE declaration
+#if defined(TOOLCHAIN_ARM)
+#include <rt_sys.h>
+#endif
+
+#ifndef FILEHANDLE
+typedef int FILEHANDLE;
+#endif
+
+// Backwards compatibility
+#ifndef WEAK
+#define WEAK MBED_WEAK
+#endif
+
+#ifndef PACKED
+#define PACKED MBED_PACKED()
+#endif
+
+#ifndef EXTERN
+#define EXTERN extern
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_wait_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,73 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_WAIT_API_H
+#define MBED_WAIT_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Generic wait functions.
+ *
+ * These provide simple NOP type wait capabilities.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * DigitalOut heartbeat(LED1);
+ *
+ * int main() {
+ * while (1) {
+ * heartbeat = 1;
+ * wait(0.5);
+ * heartbeat = 0;
+ * wait(0.5);
+ * }
+ * }
+ * @endcode
+ */
+
+/** Waits for a number of seconds, with microsecond resolution (within
+ * the accuracy of single precision floating point).
+ *
+ * @param s number of seconds to wait
+ */
+void wait(float s);
+
+/** Waits a number of milliseconds.
+ *
+ * @param ms the whole number of milliseconds to wait
+ */
+void wait_ms(int ms);
+
+/** Waits a number of microseconds.
+ *
+ * @param us the whole number of microseconds to wait
+ */
+void wait_us(int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_wait_api_no_rtos.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// This implementation of the wait functions will be compiled only
+// if the RTOS is not present.
+#ifndef MBED_CONF_RTOS_PRESENT
+
+#include "platform/mbed_wait_api.h"
+#include "hal/us_ticker_api.h"
+
+void wait(float s) {
+ wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms) {
+ wait_us(ms * 1000);
+}
+
+void wait_us(int us) {
+ uint32_t start = us_ticker_read();
+ while ((us_ticker_read() - start) < (uint32_t)us);
+}
+
+#endif // #ifndef MBED_CONF_RTOS_PRESENT
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_wait_api_rtos.cpp Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// This implementation of the wait functions will be compiled only
+// if the RTOS is present.
+#ifdef MBED_CONF_RTOS_PRESENT
+
+#include "platform/mbed_wait_api.h"
+#include "hal/us_ticker_api.h"
+#include "rtos/rtos.h"
+#include "platform/mbed_critical.h"
+
+void wait(float s) {
+ wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms) {
+ wait_us(ms * 1000);
+}
+
+void wait_us(int us) {
+ uint32_t start = us_ticker_read();
+ // Use the RTOS to wait for millisecond delays if possible
+ int ms = us / 1000;
+ if ((ms > 0) && core_util_are_interrupts_enabled()) {
+ Thread::wait((uint32_t)ms);
+ }
+ // Use busy waiting for sub-millisecond delays, or for the whole
+ // interval if interrupts are not enabled
+ while ((us_ticker_read() - start) < (uint32_t)us);
+}
+
+#endif // #if MBED_CONF_RTOS_PRESENT
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/platform.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,36 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PLATFORM_H
+#define MBED_PLATFORM_H
+
+#include <cstddef>
+#include <cstdlib>
+#include <cstdio>
+#include <cstring>
+
+#include "platform/mbed_retarget.h"
+#include "platform/mbed_toolchain.h"
+#include "device.h"
+#include "PinNames.h"
+#include "PeripheralNames.h"
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/platform/rtc_time.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OLD_RTC_TIME_H +#define MBED_OLD_RTC_TIME_H + +#warning rtc_time.h has been replaced by mbed_rtc_time.h, please update to mbed_rtc_time.h [since mbed-os-5.3] +#include "platform/mbed_rtc_time.h" + +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/platform/semihost_api.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OLD_SEMIHOST_API_H +#define MBED_OLD_SEMIHOST_API_H + +#warning semihost_api.h has been replaced by mbed_semihost_api.h, please update to mbed_semihost_api.h [since mbed-os-5.3] +#include "platform/mbed_semihost_api.h" + +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/platform/sleep.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OLD_SLEEP_H +#define MBED_OLD_SLEEP_H + +#warning sleep.h has been replaced by mbed_sleep.h, please update to mbed_sleep.h [since mbed-os-5.3] +#include "platform/mbed_sleep.h" + +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/toolchain.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,29 @@
+
+/** \addtogroup platform */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OLD_TOOLCHAIN_H
+#define MBED_OLD_TOOLCHAIN_H
+
+#warning toolchain.h has been replaced by mbed_toolchain.h, please update to mbed_toolchain.h [since mbed-os-5.3]
+#include "platform/mbed_toolchain.h"
+
+#endif
+
+/** @}*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/platform/wait_api.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OLD_WAIT_API_H +#define MBED_OLD_WAIT_API_H + +#warning wait_api.h has been replaced by mbed_wait_api.h, please update to mbed_wait_api.h [since mbed-os-5.3] +#include "platform/mbed_wait_api.h" + +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,160 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART0,
+ UART1,
+ UART2,
+ UART3,
+ UART4,
+ UART5,
+ UART6,
+ UART7,
+} UARTName;
+
+// PWMType & 1 == 1 then have to use PWDTR[12] == 1
+typedef enum {
+ PWM1A = 0,
+ PWM1B,
+ PWM1C,
+ PWM1D,
+ PWM1E,
+ PWM1F,
+ PWM1G,
+ PWM1H,
+ PWM2A = 0x10,
+ PWM2B,
+ PWM2C,
+ PWM2D,
+ PWM2E,
+ PWM2F,
+ PWM2G,
+ PWM2H,
+} PWMType;
+
+typedef enum {
+ TIOC0A = 0,
+ TIOC0B,
+ TIOC0C,
+ TIOC0D,
+ TIOC1A = 0x10,
+ TIOC1B,
+ TIOC2A = 0x20,
+ TIOC2B,
+ TIOC3A = 0x30,
+ TIOC3B,
+ TIOC3C,
+ TIOC3D,
+ TIOC4A = 0x40,
+ TIOC4B,
+ TIOC4C,
+ TIOC4D,
+} MTU2_PWMType;
+
+typedef enum {
+ PWM0_PIN = 0,
+ PWM1_PIN,
+ PWM2_PIN,
+ PWM3_PIN,
+ PWM4_PIN,
+ PWM5_PIN,
+ PWM6_PIN,
+ PWM7_PIN,
+ PWM8_PIN,
+ PWM9_PIN,
+ PWM10_PIN,
+ PWM11_PIN,
+ PWM12_PIN,
+ PWM13_PIN,
+ MTU2_PWM0_PIN = 0x20,
+ MTU2_PWM1_PIN,
+ MTU2_PWM2_PIN,
+ MTU2_PWM3_PIN,
+ MTU2_PWM4_PIN,
+ MTU2_PWM5_PIN,
+ MTU2_PWM6_PIN,
+ MTU2_PWM7_PIN,
+ MTU2_PWM8_PIN,
+ MTU2_PWM9_PIN,
+ MTU2_PWM10_PIN,
+ MTU2_PWM11_PIN,
+ MTU2_PWM12_PIN,
+ MTU2_PWM13_PIN,
+ MTU2_PWM14_PIN,
+ MTU2_PWM15_PIN,
+ MTU2_PWM16_PIN,
+ MTU2_PWM17_PIN,
+ MTU2_PWM18_PIN,
+ MTU2_PWM19_PIN,
+ MTU2_PWM20_PIN,
+ MTU2_PWM21_PIN,
+} PWMName;
+
+typedef enum {
+ AN0= 0,
+ AN1= 1,
+ AN2= 2,
+ AN3= 3,
+ AN4= 4,
+ AN5= 5,
+ AN6= 6,
+ AN7= 7,
+} ADCName;
+
+typedef enum {
+ SPI_0 = 0,
+ SPI_1,
+ SPI_2,
+ SPI_3,
+} SPIName;
+
+typedef enum {
+ I2C_0 = 0,
+ I2C_1,
+ I2C_2,
+ I2C_3
+} I2CName;
+
+typedef enum {
+ CAN_0 = 0,
+ CAN_1,
+ CAN_2,
+ CAN_3,
+ CAN_4
+} CANName;
+
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART2
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 4
+
+typedef enum {
+ P0_0 = 0,
+ P0_1, P0_2, P0_3, P0_4, P0_5,_P0_6,_P0_7,_P0_8,_P0_9,_P0_10,_P0_11,_P0_12,_P0_13,_P0_14,_P0_15,
+ P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15,
+ P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15,
+ P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15,
+ P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15,
+ P5_0, P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, P5_8, P5_9, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15,
+ P6_0, P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7, P6_8, P6_9, P6_10, P6_11, P6_12, P6_13, P6_14, P6_15,
+ P7_0, P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7, P7_8, P7_9, P7_10, P7_11, P7_12, P7_13, P7_14, P7_15,
+ P8_0, P8_1, P8_2, P8_3, P8_4, P8_5, P8_6, P8_7, P8_8, P8_9, P8_10, P8_11, P8_12, P8_13, P8_14, P8_15,
+ P9_0, P9_1, P9_2, P9_3, P9_4, P9_5, P9_6, P9_7, P9_8, P9_9, P9_10, P9_11, P9_12, P9_13, P9_14, P9_15,
+ P10_0,P10_1,P10_2,P10_3,P10_4,P10_5,P10_6,P10_7,P10_8,P10_9,P10_10,P10_11,P10_12,P10_13,P10_14,P10_15,
+ P11_0,P11_1,P11_2,P11_3,P11_4,P11_5,P11_6,P11_7,P11_8,P11_9,P11_10,P11_11,P11_12,P11_13,P11_14,P11_15,
+
+ // mbed Pin Names
+ LED1 = P6_13,
+ LED2 = P6_14,
+ LED3 = P6_15,
+ LED4 = P6_12,
+
+ LED_RED = LED1,
+ LED_GREEN= LED2,
+ LED_BLUE = LED3,
+ LED_USER = LED4,
+
+ USBTX = P6_3,
+ USBRX = P6_2,
+
+ // Arduiono Pin Names
+ D0 = P2_15,
+ D1 = P2_14,
+ D2 = P4_7,
+ D3 = P4_6,
+ D4 = P4_5,
+ D5 = P4_4,
+ D6 = P8_13,
+ D7 = P8_11,
+ D8 = P8_15,
+ D9 = P8_14,
+ D10 = P10_13,
+ D11 = P10_14,
+ D12 = P10_15,
+ D13 = P10_12,
+ D14 = P1_3,
+ D15 = P1_2,
+
+ A0 = P1_8,
+ A1 = P1_9,
+ A2 = P1_10,
+ A3 = P1_11,
+ A4 = P1_13,
+ A5 = P1_15,
+
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+
+ USER_BUTTON0 = P6_0,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON0,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullUp = 0,
+ PullDown = 3,
+ PullNone = 2,
+ OpenDrain = 4,
+ PullDefault = PullDown
+} PinMode;
+
+#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0x0f)
+#define PINNO(pin) ((pin)&0x0f)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/PortNames.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1,
+ Port2 = 2,
+ Port3 = 3,
+ Port4 = 4
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,7 @@
+#ifndef RESERVED_PINS_H
+#define RESERVED_PINS_H
+
+#define TARGET_RESERVED_PINS {}
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,121 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+
+#include "adc_iodefine.h"
+#include "cpg_iodefine.h"
+
+#define ANALOGIN_MEDIAN_FILTER 0
+
+static const PinMap PinMap_ADC[] = {
+ {P1_8, AN0, 1},
+ {P1_9, AN1, 1},
+ {P1_10, AN2, 1},
+ {P1_11, AN3, 1},
+ {P1_12, AN4, 1},
+ {P1_13, AN5, 1},
+ {P1_14, AN6, 1},
+ {P1_15, AN7, 1},
+ {NC, NC, 0}
+};
+
+static volatile uint16_t *ADCDR[] = {
+ &ADCADDRA,
+ &ADCADDRB,
+ &ADCADDRC,
+ &ADCADDRD,
+ &ADCADDRE,
+ &ADCADDRF,
+ &ADCADDRG,
+ &ADCADDRH,
+};
+
+void analogin_init(analogin_t *obj, PinName pin) {
+ obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->adc != (ADCName)NC);
+
+ CPGSTBCR3 &= ~(1 << 1);
+ CPGSTBCR6 &= ~(1 << 7);
+
+ // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0
+ // [8:6] CKS 010 :: 340tclk
+ // [5:3] MDS 000 :: single mode
+ // [2:0] CH 000 :: AN0
+ ADCADCSR = 0x0080;
+
+ pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+ volatile uint16_t data;
+
+ // Select the appropriate channel and start conversion
+ ADCADCSR &= 0xfff8;
+ ADCADCSR |= (1 << 13 | (obj->adc & 0x7));
+
+ // Wait end of conversion
+ do {
+ data = ADCADCSR;
+ } while (((data & (1 << 15)) == 0) || ((data & (1 << 13)) != 0));
+
+ // clear flag
+ ADCADCSR &= ~(1 << 15);
+
+ return ((*(ADCDR[obj->adc])) >> 4) & 0x0FFF; // 12 bits range
+}
+
+#if ANALOGIN_MEDIAN_FILTER
+static inline void order(uint32_t *a, uint32_t *b) {
+ if (*a > *b) {
+ uint32_t t = *a;
+ *a = *b;
+ *b = t;
+ }
+}
+#endif
+
+static inline uint32_t adc_read_u32(analogin_t *obj) {
+ uint32_t value;
+#if ANALOGIN_MEDIAN_FILTER
+ uint32_t v1 = adc_read(obj);
+ uint32_t v2 = adc_read(obj);
+ uint32_t v3 = adc_read(obj);
+ order(&v1, &v2);
+ order(&v2, &v3);
+ order(&v1, &v2);
+ value = v2;
+#else
+ value = adc_read(obj);
+#endif
+ return value;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+ uint32_t value = adc_read_u32(obj);
+
+ return (value << 4) | ((value >> 8) & 0x000F); // 12-bit to 16-bit conversion
+}
+
+float analogin_read(analogin_t *obj) {
+ uint32_t value = adc_read_u32(obj);
+
+ return (float)value * (1.0f / (float)0x0FFF); // 12 bits range
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,1024 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+#include "mbed_assert.h"
+#include "can_api.h"
+#include "RZ_A1_Init.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "rscan0_iodefine.h"
+#include "r_typedefs.h"
+#include "MBRZA1H.h"
+
+#define CAN_NUM 5
+#define CAN_SND_RCV 2
+#define IRQ_NUM 8
+
+static void can_rec_irq(uint32_t ch);
+static void can_trx_irq(uint32_t ch);
+static void can_err_irq(uint32_t ch, CanIrqType type);
+static void can0_rec_irq(void);
+static void can1_rec_irq(void);
+static void can2_rec_irq(void);
+static void can3_rec_irq(void);
+static void can4_rec_irq(void);
+static void can0_trx_irq(void);
+static void can1_trx_irq(void);
+static void can2_trx_irq(void);
+static void can3_trx_irq(void);
+static void can4_trx_irq(void);
+static void can0_err_warning_irq(void);
+static void can1_err_warning_irq(void);
+static void can2_err_warning_irq(void);
+static void can3_err_warning_irq(void);
+static void can4_err_warning_irq(void);
+static void can0_overrun_irq(void);
+static void can1_overrun_irq(void);
+static void can2_overrun_irq(void);
+static void can3_overrun_irq(void);
+static void can4_overrun_irq(void);
+static void can0_passive_irq(void);
+static void can1_passive_irq(void);
+static void can2_passive_irq(void);
+static void can3_passive_irq(void);
+static void can4_passive_irq(void);
+static void can0_arb_lost_irq(void);
+static void can1_arb_lost_irq(void);
+static void can2_arb_lost_irq(void);
+static void can3_arb_lost_irq(void);
+static void can4_arb_lost_irq(void);
+static void can0_bus_err_irq(void);
+static void can1_bus_err_irq(void);
+static void can2_bus_err_irq(void);
+static void can3_bus_err_irq(void);
+static void can4_bus_err_irq(void);
+static void can_reset_reg(can_t *obj);
+static void can_reset_recv_rule(can_t *obj);
+static void can_reset_buffer(can_t *obj);
+static void can_reconfigure_channel(void);
+static void can_set_frequency(can_t *obj, int f);
+static void can_set_global_mode(int mode);
+static void can_set_channel_mode(uint32_t ch, int mode);
+
+typedef enum {
+ CAN_SEND = 0,
+ CAN_RECV
+} CANfunc;
+
+typedef enum {
+ GL_OPE = 0,
+ GL_RESET,
+ GL_TEST
+} Globalmode;
+
+typedef enum {
+ CH_COMM = 0,
+ CH_RESET,
+ CH_HOLD
+} Channelmode;
+
+typedef struct {
+ IRQn_Type int_num; /* Interrupt number */
+ IRQHandler handler; /* Interrupt handler */
+} can_info_int_t;
+
+static can_irq_handler irq_handler;
+static uint32_t can_irq_id[CAN_NUM];
+static int can_initialized[CAN_NUM] = {0};
+
+static const PinMap PinMap_CAN_RD[] = {
+ {P7_8 , CAN_0, 4},
+ {P9_1 , CAN_0, 3},
+ {P1_4 , CAN_1, 3},
+ {P5_9 , CAN_1, 5},
+ {P7_11 , CAN_1, 4},
+ {P11_12, CAN_1, 1},
+ {P4_9 , CAN_2, 6},
+ {P6_4 , CAN_2, 3},
+ {P7_2 , CAN_2, 5},
+ {P2_12 , CAN_3, 5},
+ {P4_2 , CAN_3, 4},
+ {P1_5 , CAN_4, 3},
+ {P2_14 , CAN_4, 5},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_CAN_TD[] = {
+ {P7_9 , CAN_0, 4},
+ {P9_0 , CAN_0, 3},
+ {P5_10 , CAN_1, 5},
+ {P7_10 , CAN_1, 4},
+ {P11_13, CAN_1, 1},
+ {P4_8 , CAN_2, 6},
+ {P6_5 , CAN_2, 3},
+ {P7_3 , CAN_2, 5},
+ {P2_13 , CAN_3, 5},
+ {P4_3 , CAN_3, 4},
+ {P4_11 , CAN_4, 6},
+ {P8_10 , CAN_4, 5},
+ {NC , NC , 0}
+};
+
+static __IO uint32_t *CTR_MATCH[] = {
+ &RSCAN0C0CTR,
+ &RSCAN0C1CTR,
+ &RSCAN0C2CTR,
+ &RSCAN0C3CTR,
+ &RSCAN0C4CTR,
+};
+
+static __IO uint32_t *CFG_MATCH[] = {
+ &RSCAN0C0CFG,
+ &RSCAN0C1CFG,
+ &RSCAN0C2CFG,
+ &RSCAN0C3CFG,
+ &RSCAN0C4CFG,
+};
+
+static __IO uint32_t *RFCC_MATCH[] = {
+ &RSCAN0RFCC0,
+ &RSCAN0RFCC1,
+ &RSCAN0RFCC2,
+ &RSCAN0RFCC3,
+ &RSCAN0RFCC4,
+ &RSCAN0RFCC5,
+ &RSCAN0RFCC6,
+ &RSCAN0RFCC7
+};
+
+static __IO uint32_t *TXQCC_MATCH[] = {
+ &RSCAN0TXQCC0,
+ &RSCAN0TXQCC1,
+ &RSCAN0TXQCC2,
+ &RSCAN0TXQCC3,
+ &RSCAN0TXQCC4,
+};
+
+static __IO uint32_t *THLCC_MATCH[] = {
+ &RSCAN0THLCC0,
+ &RSCAN0THLCC1,
+ &RSCAN0THLCC2,
+ &RSCAN0THLCC3,
+ &RSCAN0THLCC4,
+};
+
+static __IO uint32_t *STS_MATCH[] = {
+ &RSCAN0C0STS,
+ &RSCAN0C1STS,
+ &RSCAN0C2STS,
+ &RSCAN0C3STS,
+ &RSCAN0C4STS,
+};
+
+static __IO uint32_t *ERFL_MATCH[] = {
+ &RSCAN0C0ERFL,
+ &RSCAN0C1ERFL,
+ &RSCAN0C2ERFL,
+ &RSCAN0C3ERFL,
+ &RSCAN0C4ERFL,
+};
+
+static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = {
+ { &RSCAN0CFCC0 , &RSCAN0CFCC1 },
+ { &RSCAN0CFCC3 , &RSCAN0CFCC4 },
+ { &RSCAN0CFCC6 , &RSCAN0CFCC7 },
+ { &RSCAN0CFCC9 , &RSCAN0CFCC10 },
+ { &RSCAN0CFCC12, &RSCAN0CFCC13 }
+};
+
+static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = {
+ { &RSCAN0CFSTS0 , &RSCAN0CFSTS1 },
+ { &RSCAN0CFSTS3 , &RSCAN0CFSTS4 },
+ { &RSCAN0CFSTS6 , &RSCAN0CFSTS7 },
+ { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 },
+ { &RSCAN0CFSTS12, &RSCAN0CFSTS13 }
+};
+
+static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = {
+ { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1 },
+ { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4 },
+ { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7 },
+ { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 },
+ { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 }
+};
+
+static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = {
+ { &RSCAN0CFID0 , &RSCAN0CFID1 },
+ { &RSCAN0CFID3 , &RSCAN0CFID4 },
+ { &RSCAN0CFID6 , &RSCAN0CFID7 },
+ { &RSCAN0CFID9 , &RSCAN0CFID10 },
+ { &RSCAN0CFID12, &RSCAN0CFID13 }
+};
+
+static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = {
+ { &RSCAN0CFPTR0 , &RSCAN0CFPTR1 },
+ { &RSCAN0CFPTR3 , &RSCAN0CFPTR4 },
+ { &RSCAN0CFPTR6 , &RSCAN0CFPTR7 },
+ { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 },
+ { &RSCAN0CFPTR12, &RSCAN0CFPTR13 }
+};
+
+static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = {
+ { &RSCAN0CFDF00 , &RSCAN0CFDF01 },
+ { &RSCAN0CFDF03 , &RSCAN0CFDF04 },
+ { &RSCAN0CFDF06 , &RSCAN0CFDF07 },
+ { &RSCAN0CFDF09 , &RSCAN0CFDF010 },
+ { &RSCAN0CFDF012, &RSCAN0CFDF013 }
+};
+
+static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = {
+ { &RSCAN0CFDF10 , &RSCAN0CFDF11 },
+ { &RSCAN0CFDF13 , &RSCAN0CFDF14 },
+ { &RSCAN0CFDF16 , &RSCAN0CFDF17 },
+ { &RSCAN0CFDF19 , &RSCAN0CFDF110 },
+ { &RSCAN0CFDF112, &RSCAN0CFDF113 }
+};
+
+static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] =
+{
+ { /* ch0 */
+ { INTRCAN0REC_IRQn, can0_rec_irq }, /* RxIrq */
+ { INTRCAN0TRX_IRQn, can0_trx_irq }, /* TxIrq */
+ { INTRCAN0ERR_IRQn, can0_err_warning_irq }, /* EwIrq */
+ { INTRCAN0ERR_IRQn, can0_overrun_irq }, /* DoIrq */
+ { INTRCAN0ERR_IRQn, NULL }, /* WuIrq(not supported) */
+ { INTRCAN0ERR_IRQn, can0_passive_irq }, /* EpIrq */
+ { INTRCAN0ERR_IRQn, can0_arb_lost_irq }, /* AlIrq */
+ { INTRCAN0ERR_IRQn, can0_bus_err_irq } /* BeIrq */
+ },
+ { /* ch1 */
+ { INTRCAN1REC_IRQn, can1_rec_irq }, /* RxIrq */
+ { INTRCAN1TRX_IRQn, can1_trx_irq }, /* TxIrq */
+ { INTRCAN1ERR_IRQn, can1_err_warning_irq }, /* EwIrq */
+ { INTRCAN1ERR_IRQn, can1_overrun_irq }, /* DoIrq */
+ { INTRCAN1ERR_IRQn, NULL }, /* WuIrq(not supported) */
+ { INTRCAN1ERR_IRQn, can1_passive_irq }, /* EpIrq */
+ { INTRCAN1ERR_IRQn, can1_arb_lost_irq }, /* AlIrq */
+ { INTRCAN1ERR_IRQn, can1_bus_err_irq } /* BeIrq */
+ },
+ { /* ch2 */
+ { INTRCAN2REC_IRQn, can2_rec_irq }, /* RxIrq */
+ { INTRCAN2TRX_IRQn, can2_trx_irq }, /* TxIrq */
+ { INTRCAN2ERR_IRQn, can2_err_warning_irq }, /* EwIrq */
+ { INTRCAN2ERR_IRQn, can2_overrun_irq }, /* DoIrq */
+ { INTRCAN2ERR_IRQn, NULL }, /* WuIrq(not supported) */
+ { INTRCAN2ERR_IRQn, can2_passive_irq }, /* EpIrq */
+ { INTRCAN2ERR_IRQn, can2_arb_lost_irq }, /* AlIrq */
+ { INTRCAN2ERR_IRQn, can2_bus_err_irq } /* BeIrq */
+ },
+ { /* ch3 */
+ { INTRCAN3REC_IRQn, can3_rec_irq }, /* RxIrq */
+ { INTRCAN3TRX_IRQn, can3_trx_irq }, /* TxIrq */
+ { INTRCAN3ERR_IRQn, can3_err_warning_irq }, /* EwIrq */
+ { INTRCAN3ERR_IRQn, can3_overrun_irq }, /* DoIrq */
+ { INTRCAN3ERR_IRQn, NULL }, /* WuIrq(not supported) */
+ { INTRCAN3ERR_IRQn, can3_passive_irq }, /* EpIrq */
+ { INTRCAN3ERR_IRQn, can3_arb_lost_irq }, /* AlIrq */
+ { INTRCAN3ERR_IRQn, can3_bus_err_irq } /* BeIrq */
+ },
+ { /* ch4 */
+ { INTRCAN4REC_IRQn, can4_rec_irq }, /* RxIrq */
+ { INTRCAN4TRX_IRQn, can4_trx_irq }, /* TxIrq */
+ { INTRCAN4ERR_IRQn, can4_err_warning_irq }, /* EwIrq */
+ { INTRCAN4ERR_IRQn, can4_overrun_irq }, /* DoIrq */
+ { INTRCAN4ERR_IRQn, NULL }, /* WuIrq(not supported) */
+ { INTRCAN4ERR_IRQn, can4_passive_irq }, /* EpIrq */
+ { INTRCAN4ERR_IRQn, can4_arb_lost_irq }, /* AlIrq */
+ { INTRCAN4ERR_IRQn, can4_bus_err_irq } /* BeIrq */
+ }
+};
+
+static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0;
+static __IO uint32_t *dmy_gaflm = &RSCAN0GAFLM0;
+static __IO uint32_t *dmy_gaflp0 = &RSCAN0GAFLP00;
+static __IO uint32_t *dmy_gaflp1 = &RSCAN0GAFLP10;
+
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ can_irq_id[obj->ch] = id;
+}
+
+void can_irq_free(can_t *obj) {
+ can_irq_id[obj->ch] = 0;
+}
+
+void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
+ __IO uint32_t *dmy_ctr;
+
+ /* Wake-up Irq is not supported */
+ if (type != IRQ_WAKEUP) {
+ if (enable) {
+ dmy_ctr = CTR_MATCH[obj->ch];
+ if (type == IRQ_ERROR) {
+ /* EWIE interrupts is enable */
+ *dmy_ctr |= 0x00000200;
+ } else if (type == IRQ_OVERRUN) {
+ /* OLIE interrupts is enable */
+ *dmy_ctr |= 0x00002000;
+ } else if (type == IRQ_PASSIVE) {
+ /* EPIE interrupts is enable */
+ *dmy_ctr |= 0x00000400;
+ } else if (type == IRQ_ARB) {
+ /* ALIE interrupts is enable */
+ *dmy_ctr |= 0x00008000;
+ } else if (type == IRQ_BUS) {
+ /* BEIE interrupts is enable */
+ *dmy_ctr |= 0x00000100;
+ }
+ InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler);
+ GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5);
+ GIC_EnableIRQ(can_int_info[obj->ch][type].int_num);
+ } else {
+ GIC_DisableIRQ(can_int_info[obj->ch][type].int_num);
+ }
+ }
+}
+
+static void can_rec_irq(uint32_t ch) {
+ __IO uint32_t *dmy_cfsts;
+
+ dmy_cfsts = CFSTS_TBL[ch][CAN_RECV];
+ *dmy_cfsts &= 0xFFFFFFF7; // Clear CFRXIF
+
+ irq_handler(can_irq_id[ch], IRQ_RX);
+}
+
+static void can_trx_irq(uint32_t ch) {
+ __IO uint32_t *dmy_cfsts;
+
+ dmy_cfsts = CFSTS_TBL[ch][CAN_SEND];
+ *dmy_cfsts &= 0xFFFFFFEF; // Clear CFTXIF
+
+ irq_handler(can_irq_id[ch], IRQ_TX);
+}
+
+static void can_err_irq(uint32_t ch, CanIrqType type) {
+ __IO uint32_t *dmy_erfl;
+ int val = 1;
+
+ dmy_erfl = ERFL_MATCH[ch];
+ switch (type) {
+ case IRQ_ERROR:
+ *dmy_erfl &= 0xFFFFFFFD; // Clear EWF
+ break;
+ case IRQ_OVERRUN:
+ *dmy_erfl &= 0xFFFFFFDF; // Clear OVLF
+ break;
+ case IRQ_PASSIVE:
+ *dmy_erfl &= 0xFFFFFFFB; // Clear EPF
+ break;
+ case IRQ_ARB:
+ *dmy_erfl &= 0xFFFFFF7F; // Clear ALF
+ break;
+ case IRQ_BUS:
+ *dmy_erfl &= 0xFFFF00FF; // Clear ADERRAB0ERRAB1ERRACERRAAERRAFERRASERR
+ *dmy_erfl &= 0xFFFFFFFE; // Clear BEF
+ break;
+ case IRQ_WAKEUP:
+ /* not supported */
+ /* fall through */
+ default:
+ val = 0;
+ break;
+ }
+ if (val == 1) {
+ irq_handler(can_irq_id[ch], type);
+ }
+}
+
+static void can0_rec_irq(void) {
+ can_rec_irq(CAN_0);
+}
+
+static void can1_rec_irq(void) {
+ can_rec_irq(CAN_1);
+}
+
+static void can2_rec_irq(void) {
+ can_rec_irq(CAN_2);
+}
+
+static void can3_rec_irq(void) {
+ can_rec_irq(CAN_3);
+}
+
+static void can4_rec_irq(void) {
+ can_rec_irq(CAN_4);
+}
+
+static void can0_trx_irq(void) {
+ can_trx_irq(CAN_0);
+}
+
+static void can1_trx_irq(void) {
+ can_trx_irq(CAN_1);
+}
+
+static void can2_trx_irq(void) {
+ can_trx_irq(CAN_2);
+}
+
+static void can3_trx_irq(void) {
+ can_trx_irq(CAN_3);
+}
+
+static void can4_trx_irq(void) {
+ can_trx_irq(CAN_4);
+}
+
+static void can0_err_warning_irq(void) {
+ can_err_irq(CAN_0, IRQ_ERROR);
+}
+
+static void can1_err_warning_irq(void) {
+ can_err_irq(CAN_1, IRQ_ERROR);
+}
+
+static void can2_err_warning_irq(void) {
+ can_err_irq(CAN_2, IRQ_ERROR);
+}
+
+static void can3_err_warning_irq(void) {
+ can_err_irq(CAN_3, IRQ_ERROR);
+}
+
+static void can4_err_warning_irq(void) {
+ can_err_irq(CAN_4, IRQ_ERROR);
+}
+
+static void can0_overrun_irq(void) {
+ can_err_irq(CAN_0, IRQ_OVERRUN);
+}
+
+static void can1_overrun_irq(void) {
+ can_err_irq(CAN_1, IRQ_OVERRUN);
+}
+
+static void can2_overrun_irq(void) {
+ can_err_irq(CAN_2, IRQ_OVERRUN);
+}
+
+static void can3_overrun_irq(void) {
+ can_err_irq(CAN_3, IRQ_OVERRUN);
+}
+
+static void can4_overrun_irq(void) {
+ can_err_irq(CAN_4, IRQ_OVERRUN);
+}
+
+static void can0_passive_irq(void) {
+ can_err_irq(CAN_0, IRQ_PASSIVE);
+}
+
+static void can1_passive_irq(void) {
+ can_err_irq(CAN_1, IRQ_PASSIVE);
+}
+
+static void can2_passive_irq(void) {
+ can_err_irq(CAN_2, IRQ_PASSIVE);
+}
+
+static void can3_passive_irq(void) {
+ can_err_irq(CAN_3, IRQ_PASSIVE);
+}
+
+static void can4_passive_irq(void) {
+ can_err_irq(CAN_4, IRQ_PASSIVE);
+}
+
+static void can0_arb_lost_irq(void) {
+ can_err_irq(CAN_0, IRQ_ARB);
+}
+
+static void can1_arb_lost_irq(void) {
+ can_err_irq(CAN_1, IRQ_ARB);
+}
+
+static void can2_arb_lost_irq(void) {
+ can_err_irq(CAN_2, IRQ_ARB);
+}
+
+static void can3_arb_lost_irq(void) {
+ can_err_irq(CAN_3, IRQ_ARB);
+}
+
+static void can4_arb_lost_irq(void) {
+ can_err_irq(CAN_4, IRQ_ARB);
+}
+
+static void can0_bus_err_irq(void) {
+ can_err_irq(CAN_0, IRQ_BUS);
+}
+
+static void can1_bus_err_irq(void) {
+ can_err_irq(CAN_1, IRQ_BUS);
+}
+
+static void can2_bus_err_irq(void) {
+ can_err_irq(CAN_2, IRQ_BUS);
+}
+
+static void can3_bus_err_irq(void) {
+ can_err_irq(CAN_3, IRQ_BUS);
+}
+
+static void can4_bus_err_irq(void) {
+ can_err_irq(CAN_4, IRQ_BUS);
+}
+
+void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) {
+ __IO uint32_t *dmy_ctr;
+
+ /* determine the CAN to use */
+ uint32_t can_rx = pinmap_peripheral(rd, PinMap_CAN_RD);
+ uint32_t can_tx = pinmap_peripheral(td, PinMap_CAN_TD);
+ obj->ch = pinmap_merge(can_tx, can_rx);
+ MBED_ASSERT((int)obj->ch != NC);
+
+ /* enable CAN clock */
+ CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP32);
+ /* Has CAN RAM initialisation completed ? */
+ while ((RSCAN0GSTS & 0x08) == 0x08) {
+ __NOP();
+ }
+ /* clear Global Stop mode bit */
+ RSCAN0GCTR &= 0xFFFFFFFB;
+ /* clear Channel Stop mode bit */
+ dmy_ctr = CTR_MATCH[obj->ch];
+ *dmy_ctr &= 0xFFFFFFFB;
+ /* Enter global reset mode */
+ can_set_global_mode(GL_RESET);
+ /* Enter channel reset mode */
+ can_set_channel_mode(obj->ch, CH_RESET);
+ /* reset register */
+ can_reset_reg(obj);
+
+ can_initialized[obj->ch] = 1;
+ /* reconfigure channel which is already initialized */
+ can_reconfigure_channel();
+
+ /* pin out the can pins */
+ pinmap_pinout(rd, PinMap_CAN_RD);
+ pinmap_pinout(td, PinMap_CAN_TD);
+
+ /* set can frequency */
+ can_frequency(obj, hz);
+}
+
+void can_init(can_t *obj, PinName rd, PinName td) {
+ can_init_freq(obj, rd, td, 100000);
+}
+
+void can_free(can_t *obj) {
+ /* disable CAN clock */
+ CPGSTBCR3 |= CPG_STBCR3_BIT_MSTP32;
+}
+
+int can_frequency(can_t *obj, int f) {
+ __IO uint32_t *dmy_cfcc;
+ int retval = 0;
+
+ if (f <= 1000000) {
+ /* less than 1Mhz */
+ /* set Channel Reset mode */
+ can_set_channel_mode(obj->ch, CH_RESET);
+ can_set_frequency(obj, f);
+ /* set Channel Communication mode */
+ can_set_channel_mode(obj->ch, CH_COMM);
+ /* restore CFE bit since it is cleared */
+ /* Use send/receive FIFO buffer */
+ dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
+ *dmy_cfcc |= 0x01;
+ dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
+ *dmy_cfcc |= 0x01;
+ retval = 1;
+ }
+
+ return retval;
+}
+
+void can_reset(can_t *obj) {
+ /* Enter global reset mode */
+ can_set_global_mode(GL_RESET);
+ /* Enter channel reset mode */
+ can_set_channel_mode(obj->ch, CH_RESET);
+ /* reset register */
+ can_reset_reg(obj);
+ /* reconfigure channel which is already initialized */
+ can_reconfigure_channel();
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc) {
+ __IO uint32_t *dmy_sts;
+ __IO uint32_t *dmy_cfsts;
+ __IO uint32_t *dmy_cfid;
+ __IO uint32_t *dmy_cfptr;
+ __IO uint32_t *dmy_cfdf0;
+ __IO uint32_t *dmy_cfdf1;
+ __IO uint32_t *dmy_cfpctr;
+ int retval = 0;
+
+ /* Wait to become channel communication mode */
+ dmy_sts = STS_MATCH[obj->ch];
+ while ((*dmy_sts & 0x07) != 0) {
+ __NOP();
+ }
+
+ if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x03FFFF))) {
+ /* send/receive FIFO buffer isn't full */
+ dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND];
+ if ((*dmy_cfsts & 0x02) != 0x02) {
+ /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
+ dmy_cfid = CFID_TBL[obj->ch][CAN_SEND];
+ *dmy_cfid = ((msg.format << 31) | (msg.type << 30));
+ if (msg.format == CANStandard) {
+ *dmy_cfid |= (msg.id & 0x07FF);
+ } else {
+ *dmy_cfid |= ((msg.id & 0x03FFFF) << 11);
+ }
+ /* set length */
+ dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND];
+ *dmy_cfptr = msg.len << 28;
+ /* set data */
+ dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_SEND];
+ memcpy((void *)dmy_cfdf0, &msg.data[0], 4);
+ dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_SEND];
+ memcpy((void *)dmy_cfdf1, &msg.data[4], 4);
+ /* send request */
+ dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_SEND];
+ *dmy_cfpctr = 0xFF;
+ retval = 1;
+ }
+ }
+
+ return retval;
+}
+
+int can_read(can_t *obj, CAN_Message *msg, int handle) {
+ __IO uint32_t *dmy_sts;
+ __IO uint32_t *dmy_cfsts;
+ __IO uint32_t *dmy_cfid;
+ __IO uint32_t *dmy_cfptr;
+ __IO uint32_t *dmy_cfdf0;
+ __IO uint32_t *dmy_cfdf1;
+ __IO uint32_t *dmy_cfpctr;
+ int retval = 0;
+
+ /* Wait to become channel communication mode */
+ dmy_sts = STS_MATCH[obj->ch];
+ while ((*dmy_sts & 0x07) != 0) {
+ __NOP();
+ }
+
+ /* send/receive FIFO buffer isn't empty */
+ dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV];
+ while ((*dmy_cfsts & 0x01) != 0x01) {
+ /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
+ dmy_cfid = CFID_TBL[obj->ch][CAN_RECV];
+ msg->format = (CANFormat)(*dmy_cfid >> 31);
+ msg->type = (CANType)(*dmy_cfid >> 30);
+ if (msg->format == CANStandard) {
+ msg->id = (*dmy_cfid & 0x07FF);
+ } else {
+ msg->id = ((*dmy_cfid >> 11) & 0x03FFFF);
+ }
+ /* get length */
+ dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV];
+ msg->len = (unsigned char)(*dmy_cfptr >> 28);
+ /* get data */
+ dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_RECV];
+ memcpy(&msg->data[0], (void *)dmy_cfdf0, 4);
+ dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_RECV];
+ memcpy(&msg->data[4], (void *)dmy_cfdf1, 4);
+ /* receive(next data) request */
+ dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_RECV];
+ *dmy_cfpctr = 0xFF;
+ retval = 1;
+ }
+
+ return retval;
+}
+
+unsigned char can_rderror(can_t *obj) {
+ __IO uint32_t *dmy_sts;
+
+ dmy_sts = STS_MATCH[obj->ch];
+ return (unsigned char)((*dmy_sts >> 16) & 0xFF);
+}
+
+unsigned char can_tderror(can_t *obj) {
+ __IO uint32_t *dmy_sts;
+
+ dmy_sts = STS_MATCH[obj->ch];
+ return (unsigned char)((*dmy_sts >> 24) & 0xFF);
+}
+
+int can_mode(can_t *obj, CanMode mode) {
+ __IO uint32_t *dmy_ctr;
+ __IO uint32_t *dmy_sts;
+ __IO uint32_t *dmy_cfcc;
+ int ch_cnt;
+ can_t *tmp_obj;
+ tmp_obj = obj;
+ int retval = 1;
+
+ switch (mode) {
+ case MODE_RESET:
+ can_set_global_mode(GL_RESET);
+ can_set_channel_mode(obj->ch, CH_RESET);
+ for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
+ can_initialized[ch_cnt] = 0;
+ }
+ break;
+ case MODE_NORMAL:
+ can_set_global_mode(GL_OPE);
+ can_set_channel_mode(obj->ch, CH_COMM);
+ break;
+ case MODE_SILENT:
+ can_set_channel_mode(obj->ch, CH_HOLD);
+ /* set listen only mode, enable communication test mode */
+ dmy_ctr = CTR_MATCH[obj->ch];
+ *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
+ can_set_channel_mode(obj->ch, CH_COMM);
+ break;
+ case MODE_TEST_LOCAL:
+ can_set_channel_mode(obj->ch, CH_HOLD);
+ /* set self test mode 0, enable communication test mode */
+ dmy_ctr = CTR_MATCH[obj->ch];
+ *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x05000000);
+ can_set_channel_mode(obj->ch, CH_COMM);
+ break;
+ case MODE_TEST_GLOBAL:
+ /* set the channel between the communication test on channel 1 and channel 2 */
+ /* set Channel Hold mode */
+ for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) {
+ dmy_sts = STS_MATCH[tmp_obj->ch];
+ if ((*dmy_sts & 0x04) == 0x04) {
+ /* Channel Stop mode */
+ /* clear Channel Stop mode bit */
+ dmy_ctr = CTR_MATCH[tmp_obj->ch];
+ *dmy_ctr &= 0xFFFFFFFB;
+ can_set_channel_mode(tmp_obj->ch, CH_RESET);
+ }
+ can_set_channel_mode(tmp_obj->ch, CH_HOLD);
+ }
+ can_set_global_mode(GL_TEST);
+ /* enable communication test between channel1 and channel2 */
+ RSCAN0GTSTCFG = 0x06;
+ RSCAN0GTSTCTR = 0x01;
+ /* send and receive setting of channel1 and channel2 */
+ for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) {
+ can_reset_buffer(tmp_obj);
+ /* set global interrrupt */
+ /* THLEIE, MEIE and DEIE interrupts are disable */
+ RSCAN0GCTR &= 0xFFFFF8FF;
+ /* BLIE, OLIE, BORIE and BOEIE interrupts are disable */
+ /* TAIE, ALIE, EPIE, EWIE and BEIE interrupts are enable */
+ dmy_ctr = CTR_MATCH[tmp_obj->ch];
+ *dmy_ctr &= 0x00018700;
+ can_set_global_mode(GL_OPE);
+ can_set_channel_mode(tmp_obj->ch, CH_COMM);
+ /* Use send/receive FIFO buffer */
+ dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_SEND];
+ *dmy_cfcc |= 0x01;
+ dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_RECV];
+ *dmy_cfcc |= 0x01;
+ }
+ break;
+ case MODE_TEST_SILENT:
+ /* not supported */
+ /* fall through */
+ default:
+ retval = 0;
+ break;
+ }
+
+ return retval;
+}
+
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
+ int retval = 0;
+
+ if ((format == CANStandard) || (format == CANExtended)) {
+ if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x03FFFF))) {
+ /* set Global Reset mode and Channel Reset mode */
+ can_set_global_mode(GL_RESET);
+ can_set_channel_mode(obj->ch, CH_RESET);
+ /* enable receive rule table writing */
+ RSCAN0GAFLECTR = 0x00000100;
+ /* set the page number of receive rule table(page number = 0) */
+ RSCAN0GAFLECTR |= (obj->ch * 4);
+ /* set IDE format */
+ *dmy_gaflid = (format << 31);
+ if (format == CANExtended) {
+ /* set receive rule ID for bit28-11 */
+ *dmy_gaflid |= (id << 11);
+ } else {
+ /* set receive rule ID for bit10-0 */
+ *dmy_gaflid |= id;
+ }
+ /* set ID mask bit */
+ *dmy_gaflm = (0xC0000000 | mask);
+ /* disable receive rule table writing */
+ RSCAN0GAFLECTR &= 0xFFFFFEFF;
+ /* reconfigure channel which is already initialized */
+ can_reconfigure_channel();
+ retval = 1;
+ }
+ }
+
+ return retval;
+}
+
+void can_monitor(can_t *obj, int silent) {
+ __IO uint32_t *dmy_ctr;
+
+ /* set Channel Hold mode */
+ can_set_channel_mode(obj->ch, CH_HOLD);
+ if (silent) {
+ /* set listen only mode, enable communication test mode */
+ dmy_ctr = CTR_MATCH[obj->ch];
+ *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
+ can_set_channel_mode(obj->ch, CH_COMM);
+ } else {
+ /* set normal test mode, disable communication test mode */
+ dmy_ctr = CTR_MATCH[obj->ch];
+ *dmy_ctr &= 0x00FFFFFF;
+ /* reset register */
+ can_reset_reg(obj);
+ /* reconfigure channel which is already initialized */
+ can_reconfigure_channel();
+ }
+}
+
+static void can_reset_reg(can_t *obj) {
+ __IO uint32_t *dmy_ctr;
+
+ /* time stamp source uses peripheral clock (pclk(P1_phi)/2), CAN clock uses clkc(P1_phi/2), */
+ /* mirror off, DLC not transfer, DLC check permit, transmit buffer priority, clock source not divided */
+ RSCAN0GCFG = 0x00000003;
+ /* set default frequency at 100k */
+ can_set_frequency(obj, 100000);
+ /* set receive rule */
+ can_reset_recv_rule(obj);
+ /* set buffer */
+ can_reset_buffer(obj);
+ /* set global interrrupt */
+ /* THLEIE, MEIE and DEIE interrupts are disable */
+ RSCAN0GCTR &= 0xFFFFF8FF;
+ /* ALIE, BLIE, OLIE, BORIE, BOEIE, EPIE, EWIE and BEIE interrupts are disable */
+ dmy_ctr = CTR_MATCH[obj->ch];
+ *dmy_ctr &= 0xFFFF00FF;
+}
+
+static void can_reset_recv_rule(can_t *obj) {
+ /* number of receive rules of each chanel = 64 */
+ RSCAN0GAFLCFG0 = 0x40404040;
+ RSCAN0GAFLCFG1 = 0x40000000;
+ /* enable receive rule table writing */
+ RSCAN0GAFLECTR = 0x00000100;
+ /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */
+ RSCAN0GAFLECTR |= (obj->ch * 4);
+ /* set standard ID, data frame and receive rule ID */
+ *dmy_gaflid = 0x07FF;
+ /* IDE bit, RTR bit and ID bit(28-0) are not compared */
+ *dmy_gaflm = 0;
+ /* DLC check is 1 bytes, not use a receive buffer */
+ *dmy_gaflp0 = 0x10000000;
+ /* use a send/receive FIFO buffer(ex: if ch = 1, FIFO buffer number = 4 and bit = 12) */
+ *dmy_gaflp1 = (1 << ((obj->ch + 3) * 3));
+ /* disable receive rule table writing */
+ RSCAN0GAFLECTR &= 0xFFFFFEFF;
+}
+
+static void can_reset_buffer(can_t *obj) {
+ __IO uint32_t *dmy_rfcc;
+ __IO uint32_t *dmy_cfcc;
+ __IO uint32_t *dmy_txqcc;
+ __IO uint32_t *dmy_thlcc;
+ int cnt;
+
+ /* set linked send buffer number(ex: if ch = 1 and mode = send, buffer number = 16), interval timer is pclk/2 */
+ /* number of rows of send/receive FIFO buffer = 4 */
+ dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
+ *dmy_cfcc = 0x00011100; /* send/receive FIFO mode is send */
+ dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
+ *dmy_cfcc = 0x00001100; /* send/receive FIFO mode is receive */
+ /* receive buffer is not used */
+ RSCAN0RMNB = 0;
+ /* receive FIFO buffer is not used */
+ for (cnt = 0; cnt < 8; cnt++) {
+ dmy_rfcc = RFCC_MATCH[cnt];
+ *dmy_rfcc = 0;
+ }
+ /* send queue is not used */
+ dmy_txqcc = TXQCC_MATCH[obj->ch];
+ *dmy_txqcc = 0;
+ /* send history is not used */
+ dmy_thlcc = THLCC_MATCH[obj->ch];
+ *dmy_thlcc = 0;
+
+ /* CFTXIE and CFRXIE interrupts are enable */
+ dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
+ *dmy_cfcc |= 0x04;
+ dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
+ *dmy_cfcc |= 0x02;
+ /* TMIEp interrupt is disable */
+ RSCAN0TMIEC0 = 0x00000000;
+ RSCAN0TMIEC1 = 0x00000000;
+ RSCAN0TMIEC2 = 0x00000000;
+}
+
+static void can_reconfigure_channel(void) {
+ __IO uint32_t *dmy_cfcc;
+ int ch_cnt;
+
+ for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
+ if (can_initialized[ch_cnt] == 1) {
+ /* set Global Operation mode and Channel Communication mode */
+ can_set_global_mode(GL_OPE);
+ can_set_channel_mode(ch_cnt, CH_COMM);
+ /* Use send/receive FIFO buffer */
+ dmy_cfcc = CFCC_TBL[ch_cnt][CAN_SEND];
+ *dmy_cfcc |= 0x01;
+ dmy_cfcc = CFCC_TBL[ch_cnt][CAN_RECV];
+ *dmy_cfcc |= 0x01;
+ }
+ }
+}
+
+static void can_set_frequency(can_t *obj, int f) {
+ __IO uint32_t *dmy_cfg;
+ int oldfreq = 0;
+ int newfreq = 0;
+ uint32_t clkc_val;
+ uint8_t tmp_tq;
+ uint8_t tq = 0;
+ uint8_t tmp_brp;
+ uint8_t brp = 0;
+ uint8_t tseg1 = 0;
+ uint8_t tseg2 = 0;
+
+ /* set clkc */
+ if (RZ_A1_IsClockMode0() == false) {
+ clkc_val = CM1_RENESAS_RZ_A1_P1_CLK / 2;
+ } else {
+ clkc_val = CM0_RENESAS_RZ_A1_P1_CLK / 2;
+ }
+ /* calculate BRP bit and Choose max value of calculated frequency */
+ for (tmp_tq = 8; tmp_tq <= 25; tmp_tq++) {
+ /* f = fCAN / ((BRP+1) * Tq) */
+ /* BRP = (fCAN / (f * Tq)) - 1 */
+ tmp_brp = ((clkc_val / (f * tmp_tq)) - 1) + 1; // carry(decimal point is carry)
+ newfreq = clkc_val / ((tmp_brp + 1) * tmp_tq);
+ if (newfreq >= oldfreq) {
+ oldfreq = newfreq;
+ tq = tmp_tq;
+ brp = tmp_brp;
+ }
+ }
+ /* calculate TSEG1 bit and TSEG2 bit */
+ tseg1 = (tq - 1) * 0.666666667;
+ tseg2 = (tq - 1) - tseg1;
+ /* set RSCAN0CmCFG register */
+ dmy_cfg = CFG_MATCH[obj->ch];
+ *dmy_cfg = ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
+}
+
+static void can_set_global_mode(int mode) {
+ /* set Global mode */
+ RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | mode);
+ /* Wait to cahnge into Global XXXX mode */
+ while ((RSCAN0GSTS & 0x07) != mode) {
+ __NOP();
+ }
+}
+
+static void can_set_channel_mode(uint32_t ch, int mode) {
+ __IO uint32_t *dmy_ctr;
+ __IO uint32_t *dmy_sts;
+
+ /* set Channel mode */
+ dmy_ctr = CTR_MATCH[ch];
+ *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | mode);
+ /* Wait to cahnge into Channel XXXX mode */
+ dmy_sts = STS_MATCH[ch];
+ while ((*dmy_sts & 0x07) != mode) {
+ __NOP();
+ }
+}
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,51 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +/* ->Take measures about optimization problems of web compiler */ + /* Web compiler has problem that inlining code may not be generated correctly */ + /* when "-O3 -Otime" was specified. */ +#if defined(__CC_ARM) && (__ARMCC_VERSION <= 5040027) +#pragma Ospace +#endif +/* <-Take measures about optimization problems of web compiler */ + + + + + + +#define TRANSACTION_QUEUE_SIZE_SPI 16 + + + + + +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + + + + + +#include "objects.h" +#include "dma_api.h" + +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,1060 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+ * @file MBRZA1H.h
+ * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for
+ * Renesas MBRZA1H Device Series
+ * @version
+ * @date 19 Sept 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+
+#ifndef __MBRZA1H_H__
+#define __MBRZA1H_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/****** SGI Interrupts Numbers ****************************************/
+ SGI0_IRQn = 0,
+ SGI1_IRQn = 1,
+ SGI2_IRQn = 2,
+ SGI3_IRQn = 3,
+ SGI4_IRQn = 4,
+ SGI5_IRQn = 5,
+ SGI6_IRQn = 6,
+ SGI7_IRQn = 7,
+ SGI8_IRQn = 8,
+ SGI9_IRQn = 9,
+ SGI10_IRQn = 10,
+ SGI11_IRQn = 11,
+ SGI12_IRQn = 12,
+ SGI13_IRQn = 13,
+ SGI14_IRQn = 14,
+ SGI15_IRQn = 15,
+
+/****** Cortex-A9 Processor Exceptions Numbers ****************************************/
+ /* 16 - 578 */
+ PMUIRQ0_IRQn = 16,
+ COMMRX0_IRQn = 17,
+ COMMTX0_IRQn = 18,
+ CTIIRQ0_IRQn = 19,
+
+ IRQ0_IRQn = 32,
+ IRQ1_IRQn = 33,
+ IRQ2_IRQn = 34,
+ IRQ3_IRQn = 35,
+ IRQ4_IRQn = 36,
+ IRQ5_IRQn = 37,
+ IRQ6_IRQn = 38,
+ IRQ7_IRQn = 39,
+
+ PL310ERR_IRQn = 40,
+
+ DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
+ DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
+ DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
+ DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
+ DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
+ DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
+ DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
+ DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
+ DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
+ DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
+ DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
+ DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
+ DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
+ DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
+ DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
+ DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
+ DMAERR_IRQn = 57, /*!< DMAC Interrupt */
+
+ /* 58-72 Reserved */
+
+ USBI0_IRQn = 73,
+ USBI1_IRQn = 74,
+
+ S0_VI_VSYNC0_IRQn = 75,
+ S0_LO_VSYNC0_IRQn = 76,
+ S0_VSYNCERR0_IRQn = 77,
+ GR3_VLINE0_IRQn = 78,
+ S0_VFIELD0_IRQn = 79,
+ IV1_VBUFERR0_IRQn = 80,
+ IV3_VBUFERR0_IRQn = 81,
+ IV5_VBUFERR0_IRQn = 82,
+ IV6_VBUFERR0_IRQn = 83,
+ S0_WLINE0_IRQn = 84,
+ S1_VI_VSYNC0_IRQn = 85,
+ S1_LO_VSYNC0_IRQn = 86,
+ S1_VSYNCERR0_IRQn = 87,
+ S1_VFIELD0_IRQn = 88,
+ IV2_VBUFERR0_IRQn = 89,
+ IV4_VBUFERR0_IRQn = 90,
+ S1_WLINE0_IRQn = 91,
+ OIR_VI_VSYNC0_IRQn = 92,
+ OIR_LO_VSYNC0_IRQn = 93,
+ OIR_VSYNCERR0_IRQn = 94,
+ OIR_VFIELD0_IRQn = 95,
+ IV7_VBUFERR0_IRQn = 96,
+ IV8_VBUFERR0_IRQn = 97,
+ /* 98 Reserved */
+ S0_VI_VSYNC1_IRQn = 99,
+ S0_LO_VSYNC1_IRQn = 100,
+ S0_VSYNCERR1_IRQn = 101,
+ GR3_VLINE1_IRQn = 102,
+ S0_VFIELD1_IRQn = 103,
+ IV1_VBUFERR1_IRQn = 104,
+ IV3_VBUFERR1_IRQn = 105,
+ IV5_VBUFERR1_IRQn = 106,
+ IV6_VBUFERR1_IRQn = 107,
+ S0_WLINE1_IRQn = 108,
+ S1_VI_VSYNC1_IRQn = 109,
+ S1_LO_VSYNC1_IRQn = 110,
+ S1_VSYNCERR1_IRQn = 111,
+ S1_VFIELD1_IRQn = 112,
+ IV2_VBUFERR1_IRQn = 113,
+ IV4_VBUFERR1_IRQn = 114,
+ S1_WLINE1_IRQn = 115,
+ OIR_VI_VSYNC1_IRQn = 116,
+ OIR_LO_VSYNC1_IRQn = 117,
+ OIR_VSYNCERR1_IRQn = 118,
+ OIR_VFIELD1_IRQn = 119,
+ IV7_VBUFERR1_IRQn = 120,
+ IV8_VBUFERR1_IRQn = 121,
+ /* Reserved = 122 */
+
+ IMRDI_IRQn = 123,
+ IMR2I0_IRQn = 124,
+ IMR2I1_IRQn = 125,
+
+ JEDI_IRQn = 126,
+ JDTI_IRQn = 127,
+
+ CMP0_IRQn = 128,
+ CMP1_IRQn = 129,
+
+ INT0_IRQn = 130,
+ INT1_IRQn = 131,
+ INT2_IRQn = 132,
+ INT3_IRQn = 133,
+
+ OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
+ OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
+
+ CMI_IRQn = 136,
+ WTOUT_IRQn = 137,
+
+ ITI_IRQn = 138,
+
+ TGI0A_IRQn = 139,
+ TGI0B_IRQn = 140,
+ TGI0C_IRQn = 141,
+ TGI0D_IRQn = 142,
+ TGI0V_IRQn = 143,
+ TGI0E_IRQn = 144,
+ TGI0F_IRQn = 145,
+ TGI1A_IRQn = 146,
+ TGI1B_IRQn = 147,
+ TGI1V_IRQn = 148,
+ TGI1U_IRQn = 149,
+ TGI2A_IRQn = 150,
+ TGI2B_IRQn = 151,
+ TGI2V_IRQn = 152,
+ TGI2U_IRQn = 153,
+ TGI3A_IRQn = 154,
+ TGI3B_IRQn = 155,
+ TGI3C_IRQn = 156,
+ TGI3D_IRQn = 157,
+ TGI3V_IRQn = 158,
+ TGI4A_IRQn = 159,
+ TGI4B_IRQn = 160,
+ TGI4C_IRQn = 161,
+ TGI4D_IRQn = 162,
+ TGI4V_IRQn = 163,
+
+ CMI1_IRQn = 164,
+ CMI2_IRQn = 165,
+
+ SGDEI0_IRQn = 166,
+ SGDEI1_IRQn = 167,
+ SGDEI2_IRQn = 168,
+ SGDEI3_IRQn = 169,
+
+ ADI_IRQn = 170,
+ LMTI_IRQn = 171,
+
+ SSII0_IRQn = 172, /*!< SSIF Interrupt */
+ SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
+ SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
+ SSII1_IRQn = 175, /*!< SSIF Interrupt */
+ SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
+ SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
+ SSII2_IRQn = 178, /*!< SSIF Interrupt */
+ SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
+ SSII3_IRQn = 180, /*!< SSIF Interrupt */
+ SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
+ SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
+ SSII4_IRQn = 183, /*!< SSIF Interrupt */
+ SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
+ SSII5_IRQn = 185, /*!< SSIF Interrupt */
+ SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
+ SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
+
+ SPDIFI_IRQn = 188,
+
+ INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
+ INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
+ INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
+ INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
+ INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
+ INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
+ INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
+ INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
+ INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
+ INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
+ INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
+ INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
+ INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
+ INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
+ INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
+ INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
+ INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
+ INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
+ INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
+ INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
+ INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
+ INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
+ INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
+ INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
+ INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
+ INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
+ INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
+ INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
+ INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
+ INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
+ INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
+ INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
+
+ SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
+ SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
+ SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
+ SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
+ SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
+ SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
+ SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
+ SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
+ SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
+ SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
+ SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
+ SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
+ SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
+ SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
+ SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
+ SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
+ SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
+ SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
+ SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
+ SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
+ SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
+ SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
+ SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
+ SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
+ SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
+ SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
+ SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
+ SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
+ SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
+ SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
+ SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
+ SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
+
+ INTRCANGERR_IRQn = 253,
+ INTRCANGRECC_IRQn = 254,
+ INTRCAN0REC_IRQn = 255,
+ INTRCAN0ERR_IRQn = 256,
+ INTRCAN0TRX_IRQn = 257,
+ INTRCAN1REC_IRQn = 258,
+ INTRCAN1ERR_IRQn = 259,
+ INTRCAN1TRX_IRQn = 260,
+ INTRCAN2REC_IRQn = 261,
+ INTRCAN2ERR_IRQn = 262,
+ INTRCAN2TRX_IRQn = 263,
+ INTRCAN3REC_IRQn = 264,
+ INTRCAN3ERR_IRQn = 265,
+ INTRCAN3TRX_IRQn = 266,
+ INTRCAN4REC_IRQn = 267,
+ INTRCAN4ERR_IRQn = 268,
+ INTRCAN4TRX_IRQn = 269,
+
+ RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
+ RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
+ RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
+ RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
+ RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
+ RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
+ RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
+ RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
+ RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
+ RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
+ RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
+ RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
+ RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
+ RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
+ RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
+
+ IEBBTD_IRQn = 285,
+ IEBBTERR_IRQn = 286,
+ IEBBTSTA_IRQn = 287,
+ IEBBTV_IRQn = 288,
+
+ ISY_IRQn = 289,
+ IERR_IRQn = 290,
+ ITARG_IRQn = 291,
+ ISEC_IRQn = 292,
+ IBUF_IRQn = 293,
+ IREADY_IRQn = 294,
+
+ STERB_IRQn = 295,
+ FLTENDI_IRQn = 296,
+ FLTREQ0I_IRQn = 297,
+ FLTREQ1I_IRQn = 298,
+
+ MMC0_IRQn = 299,
+ MMC1_IRQn = 300,
+ MMC2_IRQn = 301,
+
+ SCHI0_3_IRQn = 302,
+ SDHI0_0_IRQn = 303,
+ SDHI0_1_IRQn = 304,
+ SCHI1_3_IRQn = 305,
+ SDHI1_0_IRQn = 306,
+ SDHI1_1_IRQn = 307,
+
+ ARM_IRQn = 308,
+ PRD_IRQn = 309,
+ CUP_IRQn = 310,
+
+ SCUAI0_IRQn = 311,
+ SCUAI1_IRQn = 312,
+ SCUFDI0_IRQn = 313,
+ SCUFDI1_IRQn = 314,
+ SCUFDI2_IRQn = 315,
+ SCUFDI3_IRQn = 316,
+ SCUFUI0_IRQn = 317,
+ SCUFUI1_IRQn = 318,
+ SCUFUI2_IRQn = 319,
+ SCUFUI3_IRQn = 320,
+ SCUDVI0_IRQn = 321,
+ SCUDVI1_IRQn = 322,
+ SCUDVI2_IRQn = 323,
+ SCUDVI3_IRQn = 324,
+
+ MLB_CINT_IRQn = 325,
+ MLB_SINT_IRQn = 326,
+
+ DRC10_IRQn = 327,
+ DRC11_IRQn = 328,
+
+ /* 329-330 Reserved */
+
+ LINI0_INT_T_IRQn = 331,
+ LINI0_INT_R_IRQn = 332,
+ LINI0_INT_S_IRQn = 333,
+ LINI0_INT_M_IRQn = 334,
+ LINI1_INT_T_IRQn = 335,
+ LINI1_INT_R_IRQn = 336,
+ LINI1_INT_S_IRQn = 337,
+ LINI1_INT_M_IRQn = 338,
+
+ /* 339-346 Reserved */
+
+ SCIERI0_IRQn = 347,
+ SCIRXI0_IRQn = 348,
+ SCITXI0_IRQn = 349,
+ SCITEI0_IRQn = 350,
+ SCIERI1_IRQn = 351,
+ SCIRXI1_IRQn = 352,
+ SCITXI1_IRQn = 353,
+ SCITEI1_IRQn = 354,
+
+ AVBI_DATA = 355,
+ AVBI_ERROR = 356,
+ AVBI_MANAGE = 357,
+ AVBI_MAC = 358,
+
+ ETHERI_IRQn = 359,
+
+ /* 360-363 Reserved */
+
+ CEUI_IRQn = 364,
+
+ /* 365-380 Reserved */
+
+
+ H2XMLB_ERRINT_IRQn = 381,
+ H2XIC1_ERRINT_IRQn = 382,
+ X2HPERI1_ERRINT_IRQn = 383,
+ X2HPERR2_ERRINT_IRQn = 384,
+ X2HPERR34_ERRINT_IRQn= 385,
+ X2HPERR5_ERRINT_IRQn = 386,
+ X2HPERR67_ERRINT_IRQn= 387,
+ X2HDBGR_ERRINT_IRQn = 388,
+ X2HBSC_ERRINT_IRQn = 389,
+ X2HSPI1_ERRINT_IRQn = 390,
+ X2HSPI2_ERRINT_IRQn = 391,
+ PRRI_IRQn = 392,
+
+ IFEI0_IRQn = 393,
+ OFFI0_IRQn = 394,
+ PFVEI0_IRQn = 395,
+ IFEI1_IRQn = 396,
+ OFFI1_IRQn = 397,
+ PFVEI1_IRQn = 398,
+
+ /* 399-415 Reserved */
+ TINT0_IRQn = 416,
+ TINT1_IRQn = 417,
+ TINT2_IRQn = 418,
+ TINT3_IRQn = 419,
+ TINT4_IRQn = 420,
+ TINT5_IRQn = 421,
+ TINT6_IRQn = 422,
+ TINT7_IRQn = 423,
+ TINT8_IRQn = 424,
+ TINT9_IRQn = 425,
+ TINT10_IRQn = 426,
+ TINT11_IRQn = 427,
+ TINT12_IRQn = 428,
+ TINT13_IRQn = 429,
+ TINT14_IRQn = 430,
+ TINT15_IRQn = 431,
+ TINT16_IRQn = 432,
+ TINT17_IRQn = 433,
+ TINT18_IRQn = 434,
+ TINT19_IRQn = 435,
+ TINT20_IRQn = 436,
+ TINT21_IRQn = 437,
+ TINT22_IRQn = 438,
+ TINT23_IRQn = 439,
+ TINT24_IRQn = 440,
+ TINT25_IRQn = 441,
+ TINT26_IRQn = 442,
+ TINT27_IRQn = 443,
+ TINT28_IRQn = 444,
+ TINT29_IRQn = 445,
+ TINT30_IRQn = 446,
+ TINT31_IRQn = 447,
+ TINT32_IRQn = 448,
+ TINT33_IRQn = 449,
+ TINT34_IRQn = 450,
+ TINT35_IRQn = 451,
+ TINT36_IRQn = 452,
+ TINT37_IRQn = 453,
+ TINT38_IRQn = 454,
+ TINT39_IRQn = 455,
+ TINT40_IRQn = 456,
+ TINT41_IRQn = 457,
+ TINT42_IRQn = 458,
+ TINT43_IRQn = 459,
+ TINT44_IRQn = 460,
+ TINT45_IRQn = 461,
+ TINT46_IRQn = 462,
+ TINT47_IRQn = 463,
+ TINT48_IRQn = 464,
+ TINT49_IRQn = 465,
+ TINT50_IRQn = 466,
+ TINT51_IRQn = 467,
+ TINT52_IRQn = 468,
+ TINT53_IRQn = 469,
+ TINT54_IRQn = 470,
+ TINT55_IRQn = 471,
+ TINT56_IRQn = 472,
+ TINT57_IRQn = 473,
+ TINT58_IRQn = 474,
+ TINT59_IRQn = 475,
+ TINT60_IRQn = 476,
+ TINT61_IRQn = 477,
+ TINT62_IRQn = 478,
+ TINT63_IRQn = 479,
+ TINT64_IRQn = 480,
+ TINT65_IRQn = 481,
+ TINT66_IRQn = 482,
+ TINT67_IRQn = 483,
+ TINT68_IRQn = 484,
+ TINT69_IRQn = 485,
+ TINT70_IRQn = 486,
+ TINT71_IRQn = 487,
+ TINT72_IRQn = 488,
+ TINT73_IRQn = 489,
+ TINT74_IRQn = 490,
+ TINT75_IRQn = 491,
+ TINT76_IRQn = 492,
+ TINT77_IRQn = 493,
+ TINT78_IRQn = 494,
+ TINT79_IRQn = 495,
+ TINT80_IRQn = 496,
+ TINT81_IRQn = 497,
+ TINT82_IRQn = 498,
+ TINT83_IRQn = 499,
+ TINT84_IRQn = 500,
+ TINT85_IRQn = 501,
+ TINT86_IRQn = 502,
+ TINT87_IRQn = 503,
+ TINT88_IRQn = 504,
+ TINT89_IRQn = 505,
+ TINT90_IRQn = 506,
+ TINT91_IRQn = 507,
+ TINT92_IRQn = 508,
+ TINT93_IRQn = 509,
+ TINT94_IRQn = 510,
+ TINT95_IRQn = 511,
+ TINT96_IRQn = 512,
+ TINT97_IRQn = 513,
+ TINT98_IRQn = 514,
+ TINT99_IRQn = 515,
+ TINT100_IRQn = 516,
+ TINT101_IRQn = 517,
+ TINT102_IRQn = 518,
+ TINT103_IRQn = 519,
+ TINT104_IRQn = 520,
+ TINT105_IRQn = 521,
+ TINT106_IRQn = 522,
+ TINT107_IRQn = 523,
+ TINT108_IRQn = 524,
+ TINT109_IRQn = 525,
+ TINT110_IRQn = 526,
+ TINT111_IRQn = 527,
+ TINT112_IRQn = 528,
+ TINT113_IRQn = 529,
+ TINT114_IRQn = 530,
+ TINT115_IRQn = 531,
+ TINT116_IRQn = 532,
+ TINT117_IRQn = 533,
+ TINT118_IRQn = 534,
+ TINT119_IRQn = 535,
+ TINT120_IRQn = 536,
+ TINT121_IRQn = 537,
+ TINT122_IRQn = 538,
+ TINT123_IRQn = 539,
+ TINT124_IRQn = 540,
+ TINT125_IRQn = 541,
+ TINT126_IRQn = 542,
+ TINT127_IRQn = 543,
+ TINT128_IRQn = 544,
+ TINT129_IRQn = 545,
+ TINT130_IRQn = 546,
+ TINT131_IRQn = 547,
+ TINT132_IRQn = 548,
+ TINT133_IRQn = 549,
+ TINT134_IRQn = 550,
+ TINT135_IRQn = 551,
+ TINT136_IRQn = 552,
+ TINT137_IRQn = 553,
+ TINT138_IRQn = 554,
+ TINT139_IRQn = 555,
+ TINT140_IRQn = 556,
+ TINT141_IRQn = 557,
+ TINT142_IRQn = 558,
+ TINT143_IRQn = 559,
+ TINT144_IRQn = 560,
+ TINT145_IRQn = 561,
+ TINT146_IRQn = 562,
+ TINT147_IRQn = 563,
+ TINT148_IRQn = 564,
+ TINT149_IRQn = 565,
+ TINT150_IRQn = 566,
+ TINT151_IRQn = 567,
+ TINT152_IRQn = 568,
+ TINT153_IRQn = 569,
+ TINT154_IRQn = 570,
+ TINT155_IRQn = 571,
+ TINT156_IRQn = 572,
+ TINT157_IRQn = 573,
+ TINT158_IRQn = 574,
+ TINT159_IRQn = 575,
+ TINT160_IRQn = 576,
+ TINT161_IRQn = 577,
+ TINT162_IRQn = 578,
+ TINT163_IRQn = 579,
+ TINT164_IRQn = 580,
+ TINT165_IRQn = 581,
+ TINT166_IRQn = 582,
+ TINT167_IRQn = 583,
+ TINT168_IRQn = 584,
+ TINT169_IRQn = 585,
+ TINT170_IRQn = 586
+
+} IRQn_Type;
+
+#define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn
+
+/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
+#define __CA9_REV 0x0000 /*!< Core revision r0 */
+
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+#include <core_ca9.h>
+#include "system_MBRZA1H.h"
+
+
+/******************************************************************************/
+/* Device Specific Peripheral Section */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals
+ Renesas_RZ_A1 Device Specific Peripheral registers structures
+ @{
+*/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+#include "pl310.h"
+#include "gic.h"
+#include "nvic_wrapper.h"
+#include "cmsis_nvic.h"
+
+#include "ostm_iodefine.h"
+#include "gpio_iodefine.h"
+#include "cpg_iodefine.h"
+#include "l2c_iodefine.h"
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/*@}*/ /* end of group Renesas_RZ_A1_Peripherals */
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping
+ @{
+*/
+
+/* R7S72100 CPU board */
+#define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
+#define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
+#define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
+#define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
+#define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
+#define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
+#define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
+#define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
+#define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
+#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
+#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
+#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
+#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
+#define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
+#define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
+#define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
+#define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
+
+//Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map
+//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0.
+#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = NON_SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = NORMAL; \
+ region.sec_t = SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0.
+#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = NON_SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = READ; \
+ region.user_t = READ; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Normal_RO. Sect_Normal_Cod, but not executable
+#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = NON_SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = READ; \
+ region.user_t = READ; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
+#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = WB_WA; \
+ region.outer_norm_t = WB_WA; \
+ region.mem_t = NORMAL; \
+ region.sec_t = NON_SECURE; \
+ region.xn_t = EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = STRONGLY_ORDERED; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
+#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = STRONGLY_ORDERED; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = READ; \
+ region.user_t = READ; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Device_RW. Sect_Device_RO, but writeable
+#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = STRONGLY_ORDERED; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_section_descriptor(&descriptor_l1, region);
+//Page_4k_Device_RW. Shared device, not executable, rw, domain 0
+#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = SHARED_DEVICE; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
+
+//Page_64k_Device_RW. Shared device, not executable, rw, domain 0
+#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
+ region.domain = 0x0; \
+ region.e_t = ECC_DISABLED; \
+ region.g_t = GLOBAL; \
+ region.inner_norm_t = NON_CACHEABLE; \
+ region.outer_norm_t = NON_CACHEABLE; \
+ region.mem_t = SHARED_DEVICE; \
+ region.sec_t = SECURE; \
+ region.xn_t = NON_EXECUTE; \
+ region.priv_t = RW; \
+ region.user_t = RW; \
+ region.sh_t = NON_SHARED; \
+ __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
+
+
+/*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
+
+/******************************************************************************/
+/* Clock Settings */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions
+ @{
+*/
+
+/*
+ * Clock Mode 0 settings
+ * SW1-4(MD_CLK):ON
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1035
+ * CLKEN2 = 0b - unstable
+ * CLKEN[1:0]=01b - Output, Low, Low
+ * IFC[1:0] =00b - CPU clock is 1/1 PLL clock
+ * FRQCR2=0x0001
+ * GFC[1:0] =01b - Graphic clock is 2/3 bus clock
+ */
+#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
+#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
+#define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
+#define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
+#define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
+#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
+#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
+
+/*
+ * Clock Mode 1 settings
+ * SW1-4(MD_CLK):OFF
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1335
+ * CLKEN2 = 0b - unstable
+ * CLKEN[1:0]=01b - Output, Low, Low
+ * IFC[1:0] =11b - CPU clock is 1/3 PLL clock
+ * FRQCR2=0x0003
+ * GFC[1:0] =11b - graphic clock is 1/3 bus clock
+ */
+#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
+#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
+#define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
+#define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
+#define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
+#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
+#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
+
+/*@}*/ /* end of group Renesas_RZ_A1_Clocks */
+
+/******************************************************************************/
+/* CPG Settings */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions
+ @{
+*/
+
+#define CPG_FRQCR_SHIFT_CKOEN2 (14)
+#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
+#define CPG_FRQCR_SHIFT_CKOEN0 (12)
+#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
+#define CPG_FRQCR_SHIFT_IFC (8)
+#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
+
+#define CPG_FRQCR2_SHIFT_GFC (0)
+#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
+
+
+#define CPG_STBCR1_BIT_STBY (0x80u)
+#define CPG_STBCR1_BIT_DEEP (0x40u)
+#define CPG_STBCR2_BIT_HIZ (0x80u)
+#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
+#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
+#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
+#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
+#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
+#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
+#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
+#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
+#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
+#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
+#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
+#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
+#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
+#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
+#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
+#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
+#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
+#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
+#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
+#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
+#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
+#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
+#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
+#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
+#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */
+#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
+#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
+#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
+#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */
+#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */
+#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
+#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
+#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
+#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
+#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */
+#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
+#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
+#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
+#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
+#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
+#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
+#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
+#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
+#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
+#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
+#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
+#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
+#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
+#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
+#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
+#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
+#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
+#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
+#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
+#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
+#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
+#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
+#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
+#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
+#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
+#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
+#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
+#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
+#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
+#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
+#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
+#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
+#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
+#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
+#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
+#define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */
+#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
+#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
+#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
+#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
+#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
+#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
+#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
+#define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */
+#define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */
+#define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */
+#define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */
+#define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */
+#define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */
+#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
+#define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */
+#define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */
+#define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */
+#define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */
+#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
+#define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */
+#define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */
+#define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */
+#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
+#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
+#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
+#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
+#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
+#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
+#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
+#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
+#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
+#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
+#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
+#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
+#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
+#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
+
+/*@}*/ /* end of group Renesas_RZ_A1_CPG */
+
+/******************************************************************************/
+/* GPIO Settings */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions
+ @{
+*/
+
+#define GPIO_BIT_N0 (1u << 0)
+#define GPIO_BIT_N1 (1u << 1)
+#define GPIO_BIT_N2 (1u << 2)
+#define GPIO_BIT_N3 (1u << 3)
+#define GPIO_BIT_N4 (1u << 4)
+#define GPIO_BIT_N5 (1u << 5)
+#define GPIO_BIT_N6 (1u << 6)
+#define GPIO_BIT_N7 (1u << 7)
+#define GPIO_BIT_N8 (1u << 8)
+#define GPIO_BIT_N9 (1u << 9)
+#define GPIO_BIT_N10 (1u << 10)
+#define GPIO_BIT_N11 (1u << 11)
+#define GPIO_BIT_N12 (1u << 12)
+#define GPIO_BIT_N13 (1u << 13)
+#define GPIO_BIT_N14 (1u << 14)
+#define GPIO_BIT_N15 (1u << 15)
+
+
+#define MD_BOOT10_MASK (0x3)
+
+#define MD_BOOT10_BM0 (0x0)
+#define MD_BOOT10_BM1 (0x2)
+#define MD_BOOT10_BM3 (0x1)
+#define MD_BOOT10_BM4_5 (0x3)
+
+#define MD_CLK (1u << 2)
+#define MD_CLKS (1u << 3)
+
+/*@}*/ /* end of group Renesas_RZ_A1_GPIO */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __MBRZA1H_H__
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/RZ_A1_Init.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,136 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file RZ_A1_Init.c
+* $Rev: 624 $
+* $Date:: 2013-04-24 13:37:48 +0900#$
+* @brief RZ_A1 Initialize
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "MBRZA1H.h"
+#include "RZ_A1_Init.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
+#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
+
+#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: RZ_A1_SetSramWriteEnable
+* @brief Initialize Board settings
+*
+* Description:<br>
+* Set SRAM write enable
+* @param none
+* @retval none
+******************************************************************************/
+void RZ_A1_SetSramWriteEnable(void)
+{
+ /* Enable SRAM write access */
+ CPG.SYSCR3 = 0x0F;
+
+ return;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_InitClock
+* @brief Initialize Board settings
+*
+* Description:<br>
+* Initialize Clock
+* @param none
+* @retval none
+******************************************************************************/
+void RZ_A1_InitClock(void)
+{
+ /* Cancel L2C standby status before clock change */
+ L2CREG15_POWER_CTRL = 0x00000001;
+
+ /* Clock settings */
+ /* ClockMode0 */
+ CPG.FRQCR = 0x1035; /* CPU Clock =399.99MHz */
+ CPG.FRQCR2 = 0x0001; /* G Clock =266.66MHz */
+
+ return;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_IsClockMode0
+* @brief Query Clock Mode
+*
+* Description:<br>
+* Answer ClockMode0 or not
+* @param none
+* @retval true : clock mode 0
+* @retval false : clock mode 1
+******************************************************************************/
+int RZ_A1_IsClockMode0(void)
+{
+ /* ClockMode0 */
+ return true;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_InitBus
+* @brief Initialize Bus
+*
+* Description:<br>
+* Initialize Pin Setting
+* @param none
+* @retval none
+******************************************************************************/
+void RZ_A1_InitBus(void)
+{
+ /*************************************************************************/
+ /* If need Pin Setting before run program, the setting will be wrote here*/
+ /*************************************************************************/
+
+ return;
+}
+
+/******************************************************************************
+End of file
+******************************************************************************/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/RZ_A1_Init.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file RZ_A1_Init.h
+* $Rev: 531 $
+* $Date:: 2013-04-16 13:07:35 +0900#$
+* @brief RZ_A1 Initialize
+******************************************************************************/
+
+#ifndef RZ_A1_INIT_H
+#define RZ_A1_INIT_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stdio.h>
+#include <stdbool.h>
+#include "iodefine.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+void RZ_A1_SetSramWriteEnable(void);
+void RZ_A1_InitClock(void);
+int RZ_A1_IsClockMode0(void);
+void RZ_A1_InitBus(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RZ_A1_INIT_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,44 @@
+
+
+LOAD_TTB 0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
+{
+ TTB +0 EMPTY 0x4000
+ { } ; Level-1 Translation Table for MMU
+}
+
+SFLASH 0x18000000 (0x08000000)
+{
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ; S-Flash ROM : Executable cached region
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+ BOOT_LOADER_BEGIN 0x18000000 FIXED
+ {
+ * ( BOOT_LOADER )
+ }
+
+ VECTORS 0x18004000 FIXED
+ {
+ * (RESET, +FIRST) ; Vector table and other (assembler) startup code
+ * (InRoot$$Sections) ; All (library) code that must be in a root region
+ * (+RO-CODE) ; Application RO code (.text)
+ }
+
+ RO_DATA +0
+ { * (+RO-DATA) } ; Application RO data (.constdata)
+
+ RW_DATA 0x20020000
+ { * (+RW) } ; Application RW data (.data)
+
+ ZI_DATA +0 ALIGN 0x400
+ { * (+ZI) } ; Application ZI data (.bss)
+
+ RW_DATA_NC 0x60900000 0x00100000
+ { * (NC_DATA) } ; Application RW data Non cached area
+
+ ZI_DATA_NC +0
+ { * (NC_BSS) } ; Application ZI data Non cached area
+}
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,228 @@
+/* Linker script for mbed RZ_A1H */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000000
+ BOOT_LOADER (rx) : ORIGIN = 0x18000000, LENGTH = 0x00004000
+ SFLASH (rx) : ORIGIN = 0x18004000, LENGTH = 0x07FFC000
+ L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+ RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00700000
+ RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .boot :
+ {
+ KEEP(*(.boot_loader))
+ } > BOOT_LOADER
+
+ .text :
+ {
+
+ Image$$VECTORS$$Base = .;
+ * (RESET)
+ Image$$VECTORS$$Limit = .;
+ . += 0x00000400;
+
+ KEEP(*(.isr_vector))
+ *(SVC_TABLE)
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ Image$$RO_DATA$$Base = .;
+ *(.rodata*)
+ Image$$RO_DATA$$Limit = .;
+
+ KEEP(*(.eh_frame*))
+ } > SFLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > SFLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > SFLASH
+ __exidx_end = .;
+
+
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__nc_data_start)
+ LONG (__nc_data_end - __nc_data_start)
+ __copy_table_end__ = .;
+ } > SFLASH
+
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__nc_bss_start)
+ LONG (__nc_bss_end - __nc_bss_start)
+ __zero_table_end__ = .;
+ } > SFLASH
+
+ __etext = .;
+
+ .ttb :
+ {
+ Image$$TTB$$ZI$$Base = .;
+ . += 0x00004000;
+ Image$$TTB$$ZI$$Limit = .;
+ } > L_TTB
+
+ .data : AT (__etext)
+ {
+ Image$$RW_DATA$$Base = .;
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+ Image$$RW_DATA$$Limit = .;
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+
+ .bss ALIGN(0x400):
+ {
+ Image$$ZI_DATA$$Base = .;
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ Image$$ZI_DATA$$Limit = .;
+ } > RAM
+
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ __etext2 = __etext + SIZEOF(.data);
+ .nc_data : AT (__etext2)
+ {
+ Image$$RW_DATA_NC$$Base = .;
+ __nc_data_start = .;
+ *(NC_DATA)
+
+ . = ALIGN(4);
+ __nc_data_end = .;
+ Image$$RW_DATA_NC$$Limit = .;
+ } > RAM_NC
+
+ .nc_bss (NOLOAD) :
+ {
+ Image$$ZI_DATA_NC$$Base = .;
+ __nc_bss_start = .;
+ *(NC_BSS)
+
+ . = ALIGN(4);
+ __nc_bss_end = .;
+ Image$$ZI_DATA_NC$$Limit = .;
+ } > RAM_NC
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,533 @@
+/* File: startup_ARMCM3.s
+ * Purpose: startup file for Cortex-M3/M4 devices. Should use with
+ * GNU Tools for ARM Embedded Processors
+ * Version: V1.1
+ * Date: 17 June 2011
+ *
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ */
+ .syntax unified
+ .extern _start
+
+@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
+ .equ USR_MODE , 0x10
+ .equ FIQ_MODE , 0x11
+ .equ IRQ_MODE , 0x12
+ .equ SVC_MODE , 0x13
+ .equ ABT_MODE , 0x17
+ .equ UND_MODE , 0x1b
+ .equ SYS_MODE , 0x1f
+ .equ Thum_bit , 0x20 @ CPSR/SPSR Thumb bit
+
+ .equ GICI_BASE , 0xe8202000
+ .equ ICCIAR_OFFSET , 0x0000000C
+ .equ ICCEOIR_OFFSET , 0x00000010
+ .equ ICCHPIR_OFFSET , 0x00000018
+ .equ GICD_BASE , 0xe8201000
+ .equ ICDISER0_OFFSET , 0x00000100
+ .equ ICDICER0_OFFSET , 0x00000180
+ .equ ICDISPR0_OFFSET , 0x00000200
+ .equ ICDABR0_OFFSET , 0x00000300
+ .equ ICDIPR0_OFFSET , 0x00000400
+
+ .equ Mode_USR , 0x10
+ .equ Mode_FIQ , 0x11
+ .equ Mode_IRQ , 0x12
+ .equ Mode_SVC , 0x13
+ .equ Mode_ABT , 0x17
+ .equ Mode_UND , 0x1B
+ .equ Mode_SYS , 0x1F
+
+ .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled
+ .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled
+ .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state
+
+ .equ GIC_ERRATA_CHECK_1, 0x000003FE
+ .equ GIC_ERRATA_CHECK_2, 0x000003FF
+
+ .equ Sect_Normal , 0x00005c06 @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+ .equ Sect_Normal_Cod , 0x0000dc06 @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+ .equ Sect_Normal_RO , 0x0000dc16 @ as Sect_Normal_Cod, but not executable
+ .equ Sect_Normal_RW , 0x00005c16 @ as Sect_Normal_Cod, but writeable and not executable
+ .equ Sect_SO , 0x00000c12 @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+ .equ Sect_Device_RO , 0x00008c12 @ device, non-shareable, non-executable, ro, domain 0, base addr 0
+ .equ Sect_Device_RW , 0x00000c12 @ as Sect_Device_RO, but writeable
+ .equ Sect_Fault , 0x00000000 @ this translation will fault (the bottom 2 bits are important, the rest are ignored)
+
+ .equ RAM_BASE , 0x80000000
+ .equ VRAM_BASE , 0x18000000
+ .equ SRAM_BASE , 0x2e000000
+ .equ ETHERNET , 0x1a000000
+ .equ CS3_PERIPHERAL_BASE, 0x1c000000
+
+
+@ Stack Configuration
+
+ .EQU UND_Stack_Size , 0x00000100
+ .EQU SVC_Stack_Size , 0x00008000
+ .EQU ABT_Stack_Size , 0x00000100
+ .EQU FIQ_Stack_Size , 0x00000100
+ .EQU IRQ_Stack_Size , 0x00008000
+ .EQU USR_Stack_Size , 0x00004000
+
+ .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
+
+ .section .stack
+ .align 3
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space ISR_Stack_Size
+__initial_sp:
+ .space USR_Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+
+@ Heap Configuration
+
+ .EQU Heap_Size , 0x00080000
+
+ .section .heap
+ .align 3
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long 0xe59ff018 /* 0x00 */
+ .long 0xe59ff018 /* 0x04 */
+ .long 0xe59ff018 /* 0x08 */
+ .long 0xe59ff018 /* 0x0c */
+ .long 0xe59ff018 /* 0x10 */
+ .long 0xe59ff018 /* 0x14 */
+ .long 0xe59ff018 /* 0x18 */
+ .long 0xe59ff018 /* 0x1c */
+
+ .long Reset_Handler /* 0x20 */
+ .long Undef_Handler /* 0x24 */
+ .long SVC_Handler /* 0x28 */
+ .long PAbt_Handler /* 0x2c */
+ .long DAbt_Handler /* 0x30 */
+ .long 0 /* Reserved */
+ .long IRQ_Handler /* IRQ */
+ .long FIQ_Handler /* FIQ */
+
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ @ Put any cores other than 0 to sleep
+ mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
+ ands r0, r0, #3
+
+goToSleep:
+ wfine
+ bne goToSleep
+
+@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
+@ Enables Full Access i.e. in both privileged and non privileged modes
+ mrc p15, 0, r0, c1, c0, 2 @ Read Coprocessor Access Control Register (CPACR)
+ orr r0, r0, #(0xF << 20) @ Enable access to CP 10 & 11
+ mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register (CPACR)
+ isb
+
+@ Switch on the VFP and NEON hardware
+ mov r0, #0x40000000
+ vmsr fpexc, r0 @ Write FPEXC register, EN bit set
+
+ mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register
+ bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache
+ bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache
+ bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU
+ bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction
+ bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs
+ mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register
+ isb
+
+@ Set Vector Base Address Register (VBAR) to point to this application's vector table
+ ldr r0, =__isr_vector
+ mcr p15, 0, r0, c12, c0, 0
+
+@ Setup Stack for each exceptional mode
+/* ldr r0, =__StackTop */
+ ldr r0, =(__StackTop - USR_Stack_Size)
+
+@ Enter Undefined Instruction Mode and set its Stack Pointer
+ msr cpsr_c, #(Mode_UND | I_Bit | F_Bit)
+ mov sp, r0
+ sub r0, r0, #UND_Stack_Size
+
+@ Enter Abort Mode and set its Stack Pointer
+ msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit)
+ mov sp, r0
+ sub r0, r0, #ABT_Stack_Size
+
+@ Enter FIQ Mode and set its Stack Pointer
+ msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit)
+ mov sp, r0
+ sub r0, r0, #FIQ_Stack_Size
+
+@ Enter IRQ Mode and set its Stack Pointer
+ msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit)
+ mov sp, r0
+ sub r0, r0, #IRQ_Stack_Size
+
+@ Enter Supervisor Mode and set its Stack Pointer
+ msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit)
+ mov sp, r0
+
+@ Enter System Mode to complete initialization and enter kernel
+ msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
+ mov sp, r0
+
+ isb
+ ldr r0, =RZ_A1_SetSramWriteEnable
+ blx r0
+
+ .extern create_translation_table
+ bl create_translation_table
+
+@ USR/SYS stack pointer will be set during kernel init
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =InitMemorySubsystem
+ blx r0
+
+@ fp_init
+ mov r0, #0x3000000
+ vmsr fpscr, r0
+
+
+@ data sections copy
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+
+@ bss sections clear
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+
+
+ ldr r0, =_start
+ bx r0
+
+ ldr r0, sf_boot @ dummy to keep boot loader area
+loop_here:
+ b loop_here
+
+sf_boot:
+ .word boot_loader
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .text
+
+Undef_Handler:
+ .global Undef_Handler
+ .func Undef_Handler
+ .extern CUndefHandler
+ SRSDB SP!, #Mode_UND
+ PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */
+
+ MRS R0, SPSR
+ TST R0, #T_Bit /* Check mode */
+ MOVEQ R1, #4 /* R1 = 4 ARM mode */
+ MOVNE R1, #2 /* R1 = 2 Thumb mode */
+ SUB R0, LR, R1
+ LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */
+ BEQ undef_cont
+
+ /* Thumb instruction */
+ /* Determine if it is a 32-bit Thumb instruction */
+ LDRH R0, [R0]
+ MOV R2, #0x1c
+ CMP R2, R0, LSR #11
+ BHS undef_cont /* 16-bit Thumb instruction */
+
+ /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
+ LDRH R2, [LR]
+ ORR R0, R2, R0, LSL #16
+undef_cont:
+ MOV R2, LR /* Set LR to third argument */
+
+/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
+ MOV R3, SP /* Ensure stack is 8-byte aligned */
+ AND R12, R3, #4
+ SUB SP, SP, R12 /* Adjust stack */
+ PUSH {R12, LR} /* Store stack adjustment and dummy LR */
+
+ /* R0 Offending instruction */
+ /* R1 =2 (Thumb) or =4 (ARM) */
+ BL CUndefHandler
+
+ POP {R12, LR} /* Get stack adjustment & discard dummy LR */
+ ADD SP, SP, R12 /* Unadjust stack */
+
+ LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */
+ SUB LR, LR, R0
+ LDR R0, [SP, #28] /* Restore stacked SPSR */
+ MSR SPSR_cxsf, R0
+ POP {R0-R4, R12} /* Restore stacked APCS registers */
+ ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */
+ MOVS PC, LR
+ .endfunc
+
+PAbt_Handler:
+ .global PAbt_Handler
+ .func PAbt_Handler
+ .extern CPAbtHandler
+ SUB LR, LR, #4 /* Pre-adjust LR */
+ SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
+ PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
+ MRC p15, 0, R0, c5, c0, 1 /* IFSR */
+ MRC p15, 0, R1, c6, c0, 2 /* IFAR */
+
+ MOV R2, LR /* Set LR to third argument */
+
+/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
+ MOV R3, SP /* Ensure stack is 8-byte aligned */
+ AND R12, R3, #4
+ SUB SP, SP, R12 /* Adjust stack */
+ PUSH {R12, LR} /* Store stack adjustment and dummy LR */
+
+ BL CPAbtHandler
+
+ POP {R12, LR} /* Get stack adjustment & discard dummy LR */
+ ADD SP, SP, R12 /* Unadjust stack */
+
+ POP {R0-R4, R12} /* Restore stack APCS registers */
+ RFEFD SP! /* Return from exception */
+ .endfunc
+
+DAbt_Handler:
+ .global DAbt_Handler
+ .func DAbt_Handler
+ .extern CDAbtHandler
+ SUB LR, LR, #8 /* Pre-adjust LR */
+ SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
+ PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
+ CLREX /* State of exclusive monitors unknown after taken data abort */
+ MRC p15, 0, R0, c5, c0, 0 /* DFSR */
+ MRC p15, 0, R1, c6, c0, 0 /* DFAR */
+
+ MOV R2, LR /* Set LR to third argument */
+
+/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
+ MOV R3, SP /* Ensure stack is 8-byte aligned */
+ AND R12, R3, #4
+ SUB SP, SP, R12 /* Adjust stack */
+ PUSH {R12, LR} /* Store stack adjustment and dummy LR */
+
+ BL CDAbtHandler
+
+ POP {R12, LR} /* Get stack adjustment & discard dummy LR */
+ ADD SP, SP, R12 /* Unadjust stack */
+
+ POP {R0-R4, R12} /* Restore stacked APCS registers */
+ RFEFD SP! /* Return from exception */
+ .endfunc
+
+FIQ_Handler:
+ .global FIQ_Handler
+ .func FIQ_Handler
+ /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
+ * so if a real FIQ Handler is implemented, this will be needed before returning:
+ */
+ /* LDR R1, =GICI_BASE
+ LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
+ */
+ B .
+ .endfunc
+
+ .extern SVC_Handler /* refer RTX function */
+
+IRQ_Handler:
+ .global IRQ_Handler
+ .func IRQ_Handler
+ .extern IRQCount
+ .extern IRQTable
+ .extern IRQNestLevel
+
+ /* prologue */
+ SUB LR, LR, #4 /* Pre-adjust LR */
+ SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
+ CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
+ PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */
+
+/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */
+ MOV R3, SP /* Ensure stack is 8-byte aligned */
+ AND R1, R3, #4
+ SUB SP, SP, R1 /* Adjust stack */
+ PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */
+
+ LDR R0, =IRQNestLevel /* Get address of nesting counter */
+ LDR R1, [R0]
+ ADD R1, R1, #1 /* Increment nesting counter */
+ STR R1, [R0]
+
+ /* identify and acknowledge interrupt */
+ LDR R1, =GICI_BASE
+ LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
+ LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */
+ DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
+
+ /* Workaround GIC 390 errata 733075
+ * If the ID is not 0, then service the interrupt as normal.
+ * If the ID is 0 and active, then service interrupt ID 0 as normal.
+ * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
+ * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
+ */
+ LDR R2, =GICD_BASE
+ LDR R3, =GIC_ERRATA_CHECK_1
+ CMP R0, R3
+ BEQ unlock_cpu
+ LDR R3, =GIC_ERRATA_CHECK_2
+ CMP R0, R3
+ BEQ unlock_cpu
+ CMP R0, #0
+ BNE int_active /* If the ID is not 0, then service the interrupt */
+ LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */
+ TST R3, #1
+ BNE int_active /* If active, then service the interrupt */
+unlock_cpu:
+ LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */
+ STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */
+ DSB /* Ensure the write completes before continuing */
+ B ret_irq /* Do not service the spurious interrupt */
+ /* End workaround */
+
+int_active:
+ LDR R2, =IRQCount /* Read number of IRQs */
+ LDR R2, [R2]
+ CMP R0, R2 /* Clean up and return if no handler */
+ BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
+ LDR R2, =IRQTable /* Get address of handler */
+ LDR R2, [R2, R0, LSL #2]
+ CMP R2, #0 /* Clean up and return if handler address is 0 */
+ BEQ ret_irq
+ PUSH {R0,R1}
+
+ CPSIE i /* Now safe to re-enable interrupts */
+ BLX R2 /* Call handler. R0 will be IRQ number */
+ CPSID i /* Disable interrupts again */
+
+ /* write EOIR (GIC CPU Interface register) */
+ POP {R0,R1}
+ DSB /* Ensure that interrupt source is cleared before we write the EOIR */
+ret_irq:
+ /* epilogue */
+ STR R0, [R1, #ICCEOIR_OFFSET]
+
+ LDR R0, =IRQNestLevel /* Get address of nesting counter */
+ LDR R1, [R0]
+ SUB R1, R1, #1 /* Decrement nesting counter */
+ STR R1, [R0]
+
+ POP {R1, LR} /* Get stack adjustment and restore LR_SVC */
+ ADD SP, SP, R1 /* Unadjust stack */
+
+ POP {R0-R3,R12} /* Restore stacked APCS registers */
+ RFEFD SP! /* Return from exception */
+ .endfunc
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler SVC_Handler
+
+
+/* User Initial Stack & Heap */
+
+ .ifdef __MICROLIB
+
+ .global __initial_sp
+ .global __heap_base
+ .global __heap_limit
+
+ .else
+
+ .extern __use_two_region_memory
+ .global __user_initial_stackheap
+__user_initial_stackheap:
+
+ LDR R0, = __HeapBase
+ LDR R1, =(__StackTop)
+ LDR R2, = (__HeapBase + Heap_Size)
+ LDR R3, = (__StackTop - USR_Stack_Size)
+ BX LR
+
+ .endif
+
+
+ .END
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/MBRZA1H.icf Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,64 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x18004000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x18000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x187FFFFF;
+define symbol __ICFEDIT_region_TTB_start__ = 0x20000000;
+define symbol __ICFEDIT_region_TTB_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x00004000;
+define symbol __ICFEDIT_size_svcstack__ = 0x00008000;
+define symbol __ICFEDIT_size_irqstack__ = 0x00008000;
+define symbol __ICFEDIT_size_fiqstack__ = 0x00000100;
+define symbol __ICFEDIT_size_undstack__ = 0x00000100;
+define symbol __ICFEDIT_size_abtstack__ = 0x00000100;
+define symbol __ICFEDIT_size_heap__ = 0x00080000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;
+
+define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60900000;
+define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;
+
+define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;
+define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;
+
+define memory mem with size = 4G;
+
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];
+define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];
+define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
+
+define block ROM_FIXED_ORDER with fixed order { ro code, ro data };
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+do not initialize { section .retram };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly, block ROM_FIXED_ORDER };
+place in RAM_region { readwrite,
+ block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+ block UND_STACK, block ABT_STACK, block HEAP };
+
+place in RetRAM_region { section .retram };
+place in MirrorRAM_region { section .mirrorram };
+place in MirrorRetRAM_region { section .mirrorretram };
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.s Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,506 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Part one of the system initialization code,
+;; contains low-level
+;; initialization.
+;;
+;; Copyright 2007 IAR Systems. All rights reserved.
+;;
+;; $Revision: 49919 $
+;;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION SVC_STACK:DATA:NOROOT(3)
+ SECTION IRQ_STACK:DATA:NOROOT(3)
+ SECTION ABT_STACK:DATA:NOROOT(3)
+ SECTION FIQ_STACK:DATA:NOROOT(3)
+ SECTION UND_STACK:DATA:NOROOT(3)
+ SECTION CSTACK:DATA:NOROOT(3)
+
+;
+; The module in this file are included in the libraries, and may be
+; replaced by any user-defined modules that define the PUBLIC symbol
+; __iar_program_start or a user defined start symbol.
+;
+; To override the cstartup defined in the library, simply add your
+; modified version to the workbench project.
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ PUBLIC __vector_core_a9
+ PUBLIC __RST_Handler
+ PUBLIC Undefined_Handler
+ EXTERN SWI_Handler
+ PUBLIC Prefetch_Handler
+ PUBLIC Abort_Handler
+ PUBLIC IRQ_Handler
+ PUBLIC FIQ_Handler
+ EXTERN VbarInit
+ EXTERN SetLowVectors
+ EXTERN init_TTB
+ EXTERN enable_mmu
+ EXTERN Peripheral_BasicInit
+ EXTERN initsct
+ EXTERN PowerON_Reset
+ PUBLIC FPUEnable
+
+
+ DATA
+
+__iar_init$$done: ; The vector table is not needed
+ ; until after copy initialization is done
+
+__vector_core_a9: ; Make this a DATA label, so that stack usage
+ ; analysis doesn't consider it an uncalled fun
+
+ ARM
+
+ ; All default exception handlers (except reset) are
+ ; defined as weak symbol definitions.
+ ; If a handler is defined by the application it will take precedence.
+ LDR PC,Reset_Addr ; Reset
+ LDR PC,Undefined_Addr ; Undefined instructions
+ LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
+ LDR PC,Prefetch_Addr ; Prefetch abort
+ LDR PC,Abort_Addr ; Data abort
+ DCD 0 ; RESERVED
+ LDR PC,IRQ_Addr ; IRQ
+ LDR PC,FIQ_Addr ; FIQ
+
+ DATA
+
+Reset_Addr: DCD __RST_Handler
+Undefined_Addr: DCD Undefined_Handler
+SWI_Addr: DCD SWI_Handler
+Prefetch_Addr: DCD Prefetch_Handler
+Abort_Addr: DCD Abort_Handler
+IRQ_Addr: DCD IRQ_Handler
+FIQ_Addr: DCD FIQ_Handler
+
+
+; --------------------------------------------------
+; ?cstartup -- low-level system initialization code.
+;
+; After a reset execution starts here, the mode is ARM, supervisor
+; with interrupts disabled.
+;
+
+
+
+ SECTION .text:CODE:NOROOT(2)
+ EXTERN RZ_A1_SetSramWriteEnable
+ EXTERN create_translation_table
+ EXTERN SystemInit
+ EXTERN InitMemorySubsystem
+ EXTERN __iar_program_start
+ REQUIRE __vector_core_a9
+ EXTWEAK __iar_init_core
+ EXTWEAK __iar_init_vfp
+
+
+ ARM
+
+__RST_Handler:
+?cstartup:
+
+
+;;; @ Put any cores other than 0 to sleep
+ mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR
+ ands r0, r0, #3
+
+goToSleep:
+ wfine
+ bne goToSleep
+
+
+//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
+//@ Enables Full Access i.e. in both privileged and non privileged modes
+ mrc p15, 0, r0, c1, c0, 2 ;@ Read Coprocessor Access Control Register (CPACR)
+ orr r0, r0, #(0xF << 20) ;@ Enable access to CP 10 & 11
+ mcr p15, 0, r0, c1, c0, 2 ;@ Write Coprocessor Access Control Register (CPACR)
+ isb
+
+
+;; Switch on the VFP and NEON hardware
+ mov r0, #0x40000000
+ vmsr fpexc, r0 ;@ Write FPEXC register, EN bit set
+
+ mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register
+ bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache
+ bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache
+ bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU
+ bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction
+ bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs
+ mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register
+ isb
+
+
+;; Set Vector Base Address Register (VBAR) to point to this application's vector table
+ ldr r0, =__vector_core_a9
+ mcr p15, 0, r0, c12, c0, 0
+
+
+;
+; Add initialization needed before setup of stackpointers here.
+;
+
+;
+; Initialize the stack pointers.
+; The pattern below can be used for any of the exception stacks:
+; FIQ, IRQ, SVC, ABT, UND, SYS.
+; The USR mode uses the same stack as SYS.
+; The stack segments must be defined in the linker command file,
+; and be declared above.
+;
+
+
+; --------------------
+; Mode, correspords to bits 0-5 in CPSR
+
+#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR
+
+#define USR_MODE 0x10 ; User mode
+#define FIQ_MODE 0x11 ; Fast Interrupt Request mode
+#define IRQ_MODE 0x12 ; Interrupt Request mode
+#define SVC_MODE 0x13 ; Supervisor mode
+#define ABT_MODE 0x17 ; Abort mode
+#define UND_MODE 0x1B ; Undefined Instruction mode
+#define SYS_MODE 0x1F ; System mode
+
+#define Mode_SVC 0x13
+#define Mode_ABT 0x17
+#define Mode_UND 0x1B
+#define GICI_BASE 0xe8202000
+#define ICCIAR_OFFSET 0x0000000C
+#define ICCEOIR_OFFSET 0x00000010
+#define ICCHPIR_OFFSET 0x00000018
+#define GICD_BASE 0xe8201000
+#define GIC_ERRATA_CHECK_1 0x000003FE
+#define GIC_ERRATA_CHECK_2 0x000003FF
+#define ICDABR0_OFFSET 0x00000300
+#define ICDIPR0_OFFSET 0x00000400
+#define T_Bit 0x20 ; when T bit is set, core is in Thumb state
+
+ MRS r0, cpsr ; Original PSR value
+
+ ;; Set up the SVC stack pointer.
+ BIC r0, r0, #MODE_MSK ; Clear the mode bits
+ ORR r0, r0, #SVC_MODE ; Set SVC mode bits
+ MSR cpsr_c, r0 ; Change the mode
+ LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
+
+ ;; Set up the interrupt stack pointer.
+
+ BIC r0, r0, #MODE_MSK ; Clear the mode bits
+ ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
+ MSR cpsr_c, r0 ; Change the mode
+ LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
+
+ ;; Set up the fast interrupt stack pointer.
+
+ BIC r0, r0, #MODE_MSK ; Clear the mode bits
+ ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
+ MSR cpsr_c, r0 ; Change the mode
+ LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
+
+
+ ;; Set up the ABT stack pointer.
+
+ BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
+ ORR r0 ,r0, #ABT_MODE ; Set System mode bits
+ MSR cpsr_c, r0 ; Change the mode
+ LDR sp, =SFE(ABT_STACK) ; End of CSTACK
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
+
+
+ ;; Set up the UDF stack pointer.
+
+ BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
+ ORR r0 ,r0, #UND_MODE ; Set System mode bits
+ MSR cpsr_c, r0 ; Change the mode
+ LDR sp, =SFE(UND_STACK) ; End of CSTACK
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
+
+ ;; Set up the normal stack pointer.
+
+ BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
+ ORR r0 ,r0, #SYS_MODE ; Set System mode bits
+ MSR cpsr_c, r0 ; Change the mode
+ LDR sp, =SFE(CSTACK) ; End of CSTACK
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
+
+;;;
+
+ isb
+ ldr r0, =RZ_A1_SetSramWriteEnable
+ blx r0
+
+ bl create_translation_table
+
+; USR/SYS stack pointer will be set during kernel init
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =InitMemorySubsystem
+ blx r0
+
+; fp_init
+ mov r0, #0x3000000
+ vmsr fpscr, r0
+
+
+
+;;; Continue to __cmain for C-level initialization.
+
+ FUNCALL __RST_Handler, __iar_program_start
+ B __iar_program_start
+
+
+ ldr r0, sf_boot ;@ dummy to keep boot loader area
+loop_here:
+ b loop_here
+
+sf_boot:
+ DC32 0x00000001
+
+Undefined_Handler:
+ EXTERN CUndefHandler
+ SRSDB SP!, #Mode_UND
+ PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */
+
+ MRS R0, SPSR
+ TST R0, #T_Bit /* Check mode */
+ MOVEQ R1, #4 /* R1 = 4 ARM mode */
+ MOVNE R1, #2 /* R1 = 2 Thumb mode */
+ SUB R0, LR, R1
+ LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */
+ BEQ undef_cont
+
+ /* Thumb instruction */
+ /* Determine if it is a 32-bit Thumb instruction */
+ LDRH R0, [R0]
+ MOV R2, #0x1c
+ CMP R2, R0, LSR #11
+ BHS undef_cont /* 16-bit Thumb instruction */
+
+ /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
+ LDRH R2, [LR]
+ ORR R0, R2, R0, LSL #16
+undef_cont:
+ MOV R2, LR /* Set LR to third argument */
+
+/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
+ MOV R3, SP /* Ensure stack is 8-byte aligned */
+ AND R12, R3, #4
+ SUB SP, SP, R12 /* Adjust stack */
+ PUSH {R12, LR} /* Store stack adjustment and dummy LR */
+
+ /* R0 Offending instruction */
+ /* R1 =2 (Thumb) or =4 (ARM) */
+ BL CUndefHandler
+
+ POP {R12, LR} /* Get stack adjustment & discard dummy LR */
+ ADD SP, SP, R12 /* Unadjust stack */
+
+ LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */
+ SUB LR, LR, R0
+ LDR R0, [SP, #28] /* Restore stacked SPSR */
+ MSR SPSR_cxsf, R0
+ POP {R0-R4, R12} /* Restore stacked APCS registers */
+ ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */
+ MOVS PC, LR
+
+Prefetch_Handler:
+ EXTERN CPAbtHandler
+ SUB LR, LR, #4 /* Pre-adjust LR */
+ SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
+ PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
+ MRC p15, 0, R0, c5, c0, 1 /* IFSR */
+ MRC p15, 0, R1, c6, c0, 2 /* IFAR */
+
+ MOV R2, LR /* Set LR to third argument */
+
+/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
+ MOV R3, SP /* Ensure stack is 8-byte aligned */
+ AND R12, R3, #4
+ SUB SP, SP, R12 /* Adjust stack */
+ PUSH {R12, LR} /* Store stack adjustment and dummy LR */
+
+ BL CPAbtHandler
+
+ POP {R12, LR} /* Get stack adjustment & discard dummy LR */
+ ADD SP, SP, R12 /* Unadjust stack */
+
+ POP {R0-R4, R12} /* Restore stack APCS registers */
+ RFEFD SP! /* Return from exception */
+
+Abort_Handler:
+ EXTERN CDAbtHandler
+ SUB LR, LR, #8 /* Pre-adjust LR */
+ SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
+ PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
+ CLREX /* State of exclusive monitors unknown after taken data abort */
+ MRC p15, 0, R0, c5, c0, 0 /* DFSR */
+ MRC p15, 0, R1, c6, c0, 0 /* DFAR */
+
+ MOV R2, LR /* Set LR to third argument */
+
+/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
+ MOV R3, SP /* Ensure stack is 8-byte aligned */
+ AND R12, R3, #4
+ SUB SP, SP, R12 /* Adjust stack */
+ PUSH {R12, LR} /* Store stack adjustment and dummy LR */
+
+ BL CDAbtHandler
+
+ POP {R12, LR} /* Get stack adjustment & discard dummy LR */
+ ADD SP, SP, R12 /* Unadjust stack */
+
+ POP {R0-R4, R12} /* Restore stacked APCS registers */
+ RFEFD SP! /* Return from exception */
+
+FIQ_Handler:
+ /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
+ * so if a real FIQ Handler is implemented, this will be needed before returning:
+ */
+ /* LDR R1, =GICI_BASE
+ LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
+ */
+ B .
+
+ EXTERN SVC_Handler /* refer RTX function */
+
+IRQ_Handler:
+ EXTERN IRQCount
+ EXTERN IRQTable
+ EXTERN IRQNestLevel
+
+ /* prologue */
+ SUB LR, LR, #4 /* Pre-adjust LR */
+ SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
+ CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
+ PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */
+
+/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */
+ MOV R3, SP /* Ensure stack is 8-byte aligned */
+ AND R1, R3, #4
+ SUB SP, SP, R1 /* Adjust stack */
+ PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */
+
+ LDR R0, =IRQNestLevel /* Get address of nesting counter */
+ LDR R1, [R0]
+ ADD R1, R1, #1 /* Increment nesting counter */
+ STR R1, [R0]
+
+ /* identify and acknowledge interrupt */
+ LDR R1, =GICI_BASE
+ LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
+ LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */
+ DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
+
+ /* Workaround GIC 390 errata 733075
+ * If the ID is not 0, then service the interrupt as normal.
+ * If the ID is 0 and active, then service interrupt ID 0 as normal.
+ * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
+ * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
+ */
+ LDR R2, =GICD_BASE
+ LDR R3, =GIC_ERRATA_CHECK_1
+ CMP R0, R3
+ BEQ unlock_cpu
+ LDR R3, =GIC_ERRATA_CHECK_2
+ CMP R0, R3
+ BEQ unlock_cpu
+ CMP R0, #0
+ BNE int_active /* If the ID is not 0, then service the interrupt */
+ LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */
+ TST R3, #1
+ BNE int_active /* If active, then service the interrupt */
+unlock_cpu:
+ LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */
+ STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */
+ DSB /* Ensure the write completes before continuing */
+ B ret_irq /* Do not service the spurious interrupt */
+ /* End workaround */
+
+int_active:
+ LDR R2, =IRQCount /* Read number of IRQs */
+ LDR R2, [R2]
+ CMP R0, R2 /* Clean up and return if no handler */
+ BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
+ LDR R2, =IRQTable /* Get address of handler */
+ LDR R2, [R2, R0, LSL #2]
+ CMP R2, #0 /* Clean up and return if handler address is 0 */
+ BEQ ret_irq
+ PUSH {R0,R1}
+
+ CPSIE i /* Now safe to re-enable interrupts */
+ BLX R2 /* Call handler. R0 will be IRQ number */
+ CPSID i /* Disable interrupts again */
+
+ /* write EOIR (GIC CPU Interface register) */
+ POP {R0,R1}
+ DSB /* Ensure that interrupt source is cleared before we write the EOIR */
+ret_irq:
+ /* epilogue */
+ STR R0, [R1, #ICCEOIR_OFFSET]
+
+ LDR R0, =IRQNestLevel /* Get address of nesting counter */
+ LDR R1, [R0]
+ SUB R1, R1, #1 /* Decrement nesting counter */
+ STR R1, [R0]
+
+ POP {R1, LR} /* Get stack adjustment and restore LR_SVC */
+ ADD SP, SP, R1 /* Unadjust stack */
+
+ POP {R0-R3,R12} /* Restore stacked APCS registers */
+ RFEFD SP! /* Return from exception */
+;;;
+;;; Add more initialization here
+;;;
+FPUEnable:
+ ARM
+
+ //Permit access to VFP registers by modifying CPACR
+ MRC p15,0,R1,c1,c0,2
+ ORR R1,R1,#0x00F00000
+ MCR p15,0,R1,c1,c0,2
+
+ //Enable VFP
+ VMRS R1,FPEXC
+ ORR R1,R1,#0x40000000
+ VMSR FPEXC,R1
+
+ //Initialise VFP registers to 0
+ MOV R2,#0
+ VMOV D0, R2,R2
+ VMOV D1, R2,R2
+ VMOV D2, R2,R2
+ VMOV D3, R2,R2
+ VMOV D4, R2,R2
+ VMOV D5, R2,R2
+ VMOV D6, R2,R2
+ VMOV D7, R2,R2
+ VMOV D8, R2,R2
+ VMOV D9, R2,R2
+ VMOV D10,R2,R2
+ VMOV D11,R2,R2
+ VMOV D12,R2,R2
+ VMOV D13,R2,R2
+ VMOV D14,R2,R2
+ VMOV D15,R2,R2
+
+ //Initialise FPSCR to a known state
+ VMRS R2,FPSCR
+ LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ AND R2,R2,R3
+ VMSR FPSCR,R2
+
+ BX LR
+
+ END
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC1768 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "MBRZA1H.h" + +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "MBRZA1H.h"
+
+extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ InterruptHandlerRegister(IRQn, (IRQHandler)vector);
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t vectors = (uint32_t)IRQTable[IRQn];
+ return vectors;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/dev_drv.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,86 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : dev_drv.h
+* $Rev: 809 $
+* $Date:: 2014-04-09 15:06:36 +0900#$
+* Description : Device driver header
+******************************************************************************/
+#ifndef DEV_DRV_H
+#define DEV_DRV_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* ==== Arguments, Return values ==== */
+#define DEVDRV_SUCCESS (0) /* Success */
+#define DEVDRV_ERROR (-1) /* Failure */
+
+/* ==== Flags ==== */
+#define DEVDRV_FLAG_OFF (0) /* Flag OFF */
+#define DEVDRV_FLAG_ON (1) /* Flag ON */
+
+/* ==== Channels ==== */
+typedef enum devdrv_ch
+{
+ DEVDRV_CH_0, /* Channel 0 */
+ DEVDRV_CH_1, /* Channel 1 */
+ DEVDRV_CH_2, /* Channel 2 */
+ DEVDRV_CH_3, /* Channel 3 */
+ DEVDRV_CH_4, /* Channel 4 */
+ DEVDRV_CH_5, /* Channel 5 */
+ DEVDRV_CH_6, /* Channel 6 */
+ DEVDRV_CH_7, /* Channel 7 */
+ DEVDRV_CH_8, /* Channel 8 */
+ DEVDRV_CH_9, /* Channel 9 */
+ DEVDRV_CH_10, /* Channel 10 */
+ DEVDRV_CH_11, /* Channel 11 */
+ DEVDRV_CH_12, /* Channel 12 */
+ DEVDRV_CH_13, /* Channel 13 */
+ DEVDRV_CH_14, /* Channel 14 */
+ DEVDRV_CH_15 /* Channel 15 */
+} devdrv_ch_t;
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#endif /* DEV_DRV_H */
+
+/* End of File */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/gic.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,306 @@
+/**************************************************************************//**
+ * @file gic.c
+ * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version
+ * @date 19 Sept 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+#include "MBRZA1H.h"
+
+#define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
+#define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */
+
+/* Globals for use of post-scatterloading code that must access GIC */
+const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE;
+const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE;
+
+void GIC_EnableDistributor(void)
+{
+ GICDistributor->ICDDCR |= 1; //enable distributor
+}
+
+void GIC_DisableDistributor(void)
+{
+ GICDistributor->ICDDCR &=~1; //disable distributor
+}
+
+uint32_t GIC_DistributorInfo(void)
+{
+ return (uint32_t)(GICDistributor->ICDICTR);
+}
+
+uint32_t GIC_DistributorImplementer(void)
+{
+ return (uint32_t)(GICDistributor->ICDIIDR);
+}
+
+void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
+{
+ volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
+ field += IRQn % 4;
+ *field = (uint8_t)cpu_target & 0xf;
+}
+
+void GIC_SetICDICFR (const uint32_t *ICDICFRn)
+{
+ uint32_t i, num_irq;
+
+ //Get the maximum number of interrupts that the GIC supports
+ num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
+
+ for (i = 0; i < (num_irq/16); i++)
+ {
+ GICDistributor->ICDISPR[i] = *ICDICFRn++;
+ }
+}
+
+uint32_t GIC_GetTarget(IRQn_Type IRQn)
+{
+ volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
+ field += IRQn % 4;
+ return ((uint32_t)*field & 0xf);
+}
+
+void GIC_EnableInterface(void)
+{
+ GICInterface->ICCICR |= 1; //enable interface
+}
+
+void GIC_DisableInterface(void)
+{
+ GICInterface->ICCICR &=~1; //disable distributor
+}
+
+IRQn_Type GIC_AcknowledgePending(void)
+{
+ return (IRQn_Type)(GICInterface->ICCIAR);
+}
+
+void GIC_EndInterrupt(IRQn_Type IRQn)
+{
+ GICInterface->ICCEOIR = IRQn;
+}
+
+void GIC_EnableIRQ(IRQn_Type IRQn)
+{
+ GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_DisableIRQ(IRQn_Type IRQn)
+{
+ GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
+{
+ volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]);
+ int bit_shift = (IRQn % 16)<<1;
+ uint8_t save_byte;
+
+ field += (bit_shift / 8);
+ bit_shift %= 8;
+
+ save_byte = *field;
+ save_byte &= ((uint8_t)~(3u << bit_shift));
+
+ *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift);
+}
+
+void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
+ field += (IRQn % 4);
+ *field = (uint8_t)priority;
+}
+
+uint32_t GIC_GetPriority(IRQn_Type IRQn)
+{
+ volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
+ field += (IRQn % 4);
+ return (uint32_t)*field;
+}
+
+void GIC_InterfacePriorityMask(uint32_t priority)
+{
+ GICInterface->ICCPMR = priority & 0xff; //set priority mask
+}
+
+void GIC_SetBinaryPoint(uint32_t binary_point)
+{
+ GICInterface->ICCBPR = binary_point & 0x07; //set binary point
+}
+
+uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
+{
+ return (uint32_t)GICInterface->ICCBPR;
+}
+
+uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
+{
+ uint32_t pending, active;
+
+ active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
+ pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
+
+ return ((active<<1) | pending);
+}
+
+void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
+{
+ GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
+}
+
+void GIC_DistInit(void)
+{
+ //IRQn_Type i;
+ uint32_t i;
+ uint32_t num_irq = 0;
+ uint32_t priority_field;
+
+ //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
+ //configuring all of the interrupts as Secure.
+
+ //Disable interrupt forwarding
+ GIC_DisableDistributor();
+ //Get the maximum number of interrupts that the GIC supports
+ num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
+
+ /* Priority level is implementation defined.
+ To determine the number of priority bits implemented write 0xFF to an ICDIPR
+ priority field and read back the value stored.*/
+ GIC_SetPriority((IRQn_Type)0, 0xff);
+ priority_field = GIC_GetPriority((IRQn_Type)0);
+
+ for (i = 32; i < num_irq; i++)
+ {
+ //Disable all SPI the interrupts
+ GIC_DisableIRQ((IRQn_Type)i);
+ //Set level-sensitive and N-N model
+ //GIC_SetLevelModel(i, 0, 0);
+ //Set priority
+ GIC_SetPriority((IRQn_Type)i, priority_field/2);
+ //Set target list to "all cpus"
+ GIC_SetTarget((IRQn_Type)i, 0xff);
+ }
+ /* Set level-edge and 1-N model */
+ /* GICDistributor->ICDICFR[ 0] is read only */
+ GICDistributor->ICDICFR[ 1] = 0x00000055;
+ GICDistributor->ICDICFR[ 2] = 0xFFFD5555;
+ GICDistributor->ICDICFR[ 3] = 0x555FFFFF;
+ GICDistributor->ICDICFR[ 4] = 0x55555555;
+ GICDistributor->ICDICFR[ 5] = 0x55555555;
+ GICDistributor->ICDICFR[ 6] = 0x55555555;
+ GICDistributor->ICDICFR[ 7] = 0x55555555;
+ GICDistributor->ICDICFR[ 8] = 0x5555F555;
+ GICDistributor->ICDICFR[ 9] = 0x55555555;
+ GICDistributor->ICDICFR[10] = 0x55555555;
+ GICDistributor->ICDICFR[11] = 0xF5555555;
+ GICDistributor->ICDICFR[12] = 0xF555F555;
+ GICDistributor->ICDICFR[13] = 0x5555F555;
+ GICDistributor->ICDICFR[14] = 0x55555555;
+ GICDistributor->ICDICFR[15] = 0x55555555;
+ GICDistributor->ICDICFR[16] = 0x55555555;
+ GICDistributor->ICDICFR[17] = 0xFD555555;
+ GICDistributor->ICDICFR[18] = 0x55555557;
+ GICDistributor->ICDICFR[19] = 0x55555555;
+ GICDistributor->ICDICFR[20] = 0xFFD55555;
+ GICDistributor->ICDICFR[21] = 0x5F55557F;
+ GICDistributor->ICDICFR[22] = 0xFD55555F;
+ GICDistributor->ICDICFR[23] = 0x55555557;
+ GICDistributor->ICDICFR[24] = 0x55555555;
+ GICDistributor->ICDICFR[25] = 0x55555555;
+ GICDistributor->ICDICFR[26] = 0x55555555;
+ GICDistributor->ICDICFR[27] = 0x55555555;
+ GICDistributor->ICDICFR[28] = 0x55555555;
+ GICDistributor->ICDICFR[29] = 0x55555555;
+ GICDistributor->ICDICFR[30] = 0x55555555;
+ GICDistributor->ICDICFR[31] = 0x55555555;
+ GICDistributor->ICDICFR[32] = 0x55555555;
+ GICDistributor->ICDICFR[33] = 0x55555555;
+
+ //Enable distributor
+ GIC_EnableDistributor();
+}
+
+void GIC_CPUInterfaceInit(void)
+{
+ IRQn_Type i;
+ uint32_t priority_field;
+
+ //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
+ //configuring all of the interrupts as Secure.
+
+ //Disable interrupt forwarding
+ GIC_DisableInterface();
+
+ /* Priority level is implementation defined.
+ To determine the number of priority bits implemented write 0xFF to an ICDIPR
+ priority field and read back the value stored.*/
+ GIC_SetPriority((IRQn_Type)0, 0xff);
+ priority_field = GIC_GetPriority((IRQn_Type)0);
+
+ //SGI and PPI
+ for (i = (IRQn_Type)0; i < 32; i++)
+ {
+ //Set level-sensitive and N-N model for PPI
+ //if(i > 15)
+ //GIC_SetLevelModel(i, 0, 0);
+ //Disable SGI and PPI interrupts
+ GIC_DisableIRQ(i);
+ //Set priority
+ GIC_SetPriority(i, priority_field/2);
+ }
+ //Enable interface
+ GIC_EnableInterface();
+ //Set binary point to 0
+ GIC_SetBinaryPoint(0);
+ //Set priority mask
+ GIC_InterfacePriorityMask(0xff);
+}
+
+void GIC_Enable(void)
+{
+ GIC_DistInit();
+ GIC_CPUInterfaceInit(); //per CPU
+}
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/gic.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,317 @@
+/**************************************************************************//**
+ * @file gic.h
+ * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version
+ * @date 29 August 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+#ifndef GIC_H_
+#define GIC_H_
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
+ */
+typedef struct
+{
+ __IO uint32_t ICDDCR;
+ __I uint32_t ICDICTR;
+ __I uint32_t ICDIIDR;
+ uint32_t RESERVED0[29];
+ __IO uint32_t ICDISR[32];
+ __IO uint32_t ICDISER[32];
+ __IO uint32_t ICDICER[32];
+ __IO uint32_t ICDISPR[32];
+ __IO uint32_t ICDICPR[32];
+ __I uint32_t ICDABR[32];
+ uint32_t RESERVED1[32];
+ __IO uint32_t ICDIPR[256];
+ __IO uint32_t ICDIPTR[256];
+ __IO uint32_t ICDICFR[64];
+ uint32_t RESERVED2[128];
+ __IO uint32_t ICDSGIR;
+} GICDistributor_Type;
+
+/** \brief Structure type to access the Controller Interface (GICC)
+ */
+typedef struct
+{
+ __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register
+ __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register
+ __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register
+ __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register
+ __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register
+ __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register
+ __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register
+ __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register
+
+ uint32_t RESERVED[55];
+
+ __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register
+} GICInterface_Type;
+
+/*@} end of GICD */
+
+/* ########################## GIC functions #################################### */
+/** \brief Functions that manage interrupts via the GIC.
+ @{
+ */
+
+/** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface
+
+ Enables the forwarding of pending interrupts to the CPU interfaces.
+
+ */
+void GIC_EnableDistributor(void);
+
+/** \brief Disable Distributor
+
+ Disables the forwarding of pending interrupts to the CPU interfaces.
+
+ */
+void GIC_DisableDistributor(void);
+
+/** \brief Provides information about the configuration of the GIC.
+ Provides information about the configuration of the GIC.
+ - whether the GIC implements the Security Extensions
+ - the maximum number of interrupt IDs that the GIC supports
+ - the number of CPU interfaces implemented
+ - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
+
+ \return Distributor Information.
+ */
+uint32_t GIC_DistributorInfo(void);
+
+/** \brief Distributor Implementer Identification Register.
+
+ Distributor Implementer Identification Register
+
+ \return Implementer Information.
+ */
+uint32_t GIC_DistributorImplementer(void);
+
+/** \brief Set list of processors that the interrupt is sent to if it is asserted.
+
+ The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
+ This field stores the list of processors that the interrupt is sent to if it is asserted.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] target CPU target
+ */
+void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
+
+/** \brief Get list of processors that the interrupt is sent to if it is asserted.
+
+ The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
+ This field stores the list of processors that the interrupt is sent to if it is asserted.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] target CPU target
+*/
+uint32_t GIC_GetTarget(IRQn_Type IRQn);
+
+/** \brief Enable Interface
+
+ Enables the signalling of interrupts to the target processors.
+
+ */
+void GIC_EnableInterface(void);
+
+/** \brief Disable Interface
+
+ Disables the signalling of interrupts to the target processors.
+
+ */
+void GIC_DisableInterface(void);
+
+/** \brief Acknowledge Interrupt
+
+ The function acknowledges the highest priority pending interrupt and returns its IRQ number.
+
+ \return Interrupt number
+ */
+IRQn_Type GIC_AcknowledgePending(void);
+
+/** \brief End Interrupt
+
+ The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
+
+ \param [in] IRQn Interrupt number.
+ */
+void GIC_EndInterrupt(IRQn_Type IRQn);
+
+
+/** \brief Enable Interrupt
+
+ Set-enable bit for each interrupt supported by the GIC.
+
+ \param [in] IRQn External interrupt number.
+ */
+void GIC_EnableIRQ(IRQn_Type IRQn);
+
+/** \brief Disable Interrupt
+
+ Clear-enable bit for each interrupt supported by the GIC.
+
+ \param [in] IRQn Number of the external interrupt to disable
+ */
+void GIC_DisableIRQ(IRQn_Type IRQn);
+
+/** \brief Set Pending Interrupt
+
+ Set-pending bit for each interrupt supported by the GIC.
+
+ \param [in] IRQn Interrupt number.
+ */
+void GIC_SetPendingIRQ(IRQn_Type IRQn);
+
+/** \brief Clear Pending Interrupt
+
+ Clear-pending bit for each interrupt supported by the GIC
+
+ \param [in] IRQn Number of the interrupt for clear pending
+ */
+void GIC_ClearPendingIRQ(IRQn_Type IRQn);
+
+/** \brief Int_config field for each interrupt supported by the GIC.
+
+ This field identifies whether the corresponding interrupt is:
+ (1) edge-triggered or (0) level-sensitive
+ (1) 1-N model or (0) N-N model
+
+ \param [in] IRQn Interrupt number.
+ \param [in] edge_level (1) edge-triggered or (0) level-sensitive
+ \param [in] model (1) 1-N model or (0) N-N model
+ */
+void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ */
+uint32_t GIC_GetPriority(IRQn_Type IRQn);
+
+/** \brief CPU Interface Priority Mask Register
+
+ The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
+ value indicated by this field, the interface signals the interrupt to the processor.
+
+ \param [in] Mask.
+ */
+void GIC_InterfacePriorityMask(uint32_t priority);
+
+/** \brief Set the binary point.
+
+ Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
+
+ \param [in] Mask.
+ */
+void GIC_SetBinaryPoint(uint32_t binary_point);
+
+/** \brief Get the binary point.
+
+ Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
+
+ \return Binary point.
+ */
+uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
+
+/** \brief Get Interrupt state.
+
+ Get the interrupt state, whether pending and/or active
+
+ \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active
+ */
+uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
+
+/** \brief Send Software Generated interrupt
+
+ Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
+GIC_InterfacePriorityMask
+ \param [in] IRQn The Interrupt ID of the SGI.
+ \param [in] target_list CPUTargetList
+ \param [in] filter_list TargetListFilter
+ */
+void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
+
+/** \brief API call to initialise the interrupt distributor
+
+ API call to initialise the interrupt distributor
+
+ */
+void GIC_DistInit(void);
+
+/** \brief API call to initialise the CPU interface
+
+ API call to initialise the CPU interface
+
+ */
+void GIC_CPUInterfaceInit(void);
+
+/** \brief API call to set the Interrupt Configuration Registers
+
+ API call to initialise the Interrupt Configuration Registers
+
+ */
+void GIC_SetICDICFR (const uint32_t *ICDICFRn);
+
+/** \brief API call to Enable the GIC
+
+ API call to Enable the GIC
+
+ */
+void GIC_Enable(void);
+
+#endif /* GIC_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,358 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : bsc_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : BSC register define header +*******************************************************************************/ +#ifndef BSC_IOBITMASK_H +#define BSC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define BSC_CMNCR_HIZCNT (0x00000001uL) +#define BSC_CMNCR_HIZMEM (0x00000002uL) +#define BSC_CMNCR_DPRTY (0x00000600uL) +#define BSC_CMNCR_AL0 (0x01000000uL) +#define BSC_CMNCR_TL0 (0x10000000uL) + +#define BSC_CS0BCR_BSZ (0x00000600uL) +#define BSC_CS0BCR_TYPE (0x00007000uL) +#define BSC_CS0BCR_IWRRS (0x00070000uL) +#define BSC_CS0BCR_IWRRD (0x00380000uL) +#define BSC_CS0BCR_IWRWS (0x01C00000uL) +#define BSC_CS0BCR_IWRWD (0x0E000000uL) +#define BSC_CS0BCR_IWW (0x70000000uL) + +#define BSC_CS1BCR_BSZ (0x00000600uL) +#define BSC_CS1BCR_TYPE (0x00007000uL) +#define BSC_CS1BCR_IWRRS (0x00070000uL) +#define BSC_CS1BCR_IWRRD (0x00380000uL) +#define BSC_CS1BCR_IWRWS (0x01C00000uL) +#define BSC_CS1BCR_IWRWD (0x0E000000uL) +#define BSC_CS1BCR_IWW (0x70000000uL) + +#define BSC_CS2BCR_BSZ (0x00000600uL) +#define BSC_CS2BCR_TYPE (0x00007000uL) +#define BSC_CS2BCR_IWRRS (0x00070000uL) +#define BSC_CS2BCR_IWRRD (0x00380000uL) +#define BSC_CS2BCR_IWRWS (0x01C00000uL) +#define BSC_CS2BCR_IWRWD (0x0E000000uL) +#define BSC_CS2BCR_IWW (0x70000000uL) + +#define BSC_CS3BCR_BSZ (0x00000600uL) +#define BSC_CS3BCR_TYPE (0x00007000uL) +#define BSC_CS3BCR_IWRRS (0x00070000uL) +#define BSC_CS3BCR_IWRRD (0x00380000uL) +#define BSC_CS3BCR_IWRWS (0x01C00000uL) +#define BSC_CS3BCR_IWRWD (0x0E000000uL) +#define BSC_CS3BCR_IWW (0x70000000uL) + +#define BSC_CS4BCR_BSZ (0x00000600uL) +#define BSC_CS4BCR_TYPE (0x00007000uL) +#define BSC_CS4BCR_IWRRS (0x00070000uL) +#define BSC_CS4BCR_IWRRD (0x00380000uL) +#define BSC_CS4BCR_IWRWS (0x01C00000uL) +#define BSC_CS4BCR_IWRWD (0x0E000000uL) +#define BSC_CS4BCR_IWW (0x70000000uL) + +#define BSC_CS5BCR_BSZ (0x00000600uL) +#define BSC_CS5BCR_TYPE (0x00007000uL) +#define BSC_CS5BCR_IWRRS (0x00070000uL) +#define BSC_CS5BCR_IWRRD (0x00380000uL) +#define BSC_CS5BCR_IWRWS (0x01C00000uL) +#define BSC_CS5BCR_IWRWD (0x0E000000uL) +#define BSC_CS5BCR_IWW (0x70000000uL) + +#define BSC_CS0WCR_NORMAL_HW (0x00000003uL) +#define BSC_CS0WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS0WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS0WCR_NORMAL_SW (0x00001800uL) +#define BSC_CS0WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS1WCR_NORMAL_HW (0x00000003uL) +#define BSC_CS1WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS1WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS1WCR_NORMAL_SW (0x00001800uL) +#define BSC_CS1WCR_NORMAL_WW (0x00070000uL) +#define BSC_CS1WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS2WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS2WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS2WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS3WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS3WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS3WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS4WCR_NORMAL_HW (0x00000003uL) +#define BSC_CS4WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS4WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS4WCR_NORMAL_SW (0x00001800uL) +#define BSC_CS4WCR_NORMAL_WW (0x00070000uL) +#define BSC_CS4WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS5WCR_NORMAL_HW (0x00000003uL) +#define BSC_CS5WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS5WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS5WCR_NORMAL_SW (0x00001800uL) +#define BSC_CS5WCR_NORMAL_WW (0x00070000uL) +#define BSC_CS5WCR_NORMAL_MPXWBAS (0x00100000uL) +#define BSC_CS5WCR_NORMAL_SZSEL (0x00200000uL) + +#define BSC_CS0WCR_BROM_ASY_WM (0x00000040uL) +#define BSC_CS0WCR_BROM_ASY_W (0x00000780uL) +#define BSC_CS0WCR_BROM_ASY_BW (0x00030000uL) +#define BSC_CS0WCR_BROM_ASY_BST (0x00300000uL) + +#define BSC_CS4WCR_BROM_ASY_HW (0x00000003uL) +#define BSC_CS4WCR_BROM_ASY_WM (0x00000040uL) +#define BSC_CS4WCR_BROM_ASY_W (0x00000780uL) +#define BSC_CS4WCR_BROM_ASY_SW (0x00001800uL) +#define BSC_CS4WCR_BROM_ASY_BW (0x00030000uL) +#define BSC_CS4WCR_BROM_ASY_BST (0x00300000uL) + +#define BSC_CS2WCR_SDRAM_A2CL (0x00000180uL) + +#define BSC_CS3WCR_SDRAM_WTRC (0x00000003uL) +#define BSC_CS3WCR_SDRAM_TRWL (0x00000018uL) +#define BSC_CS3WCR_SDRAM_A3CL (0x00000180uL) +#define BSC_CS3WCR_SDRAM_WTRCD (0x00000C00uL) +#define BSC_CS3WCR_SDRAM_WTRP (0x00006000uL) + +#define BSC_CS0WCR_BROM_SY_WM (0x00000040uL) +#define BSC_CS0WCR_BROM_SY_W (0x00000780uL) +#define BSC_CS0WCR_BROM_SY_BW (0x00030000uL) + +#define BSC_SDCR_A3COL (0x00000003uL) +#define BSC_SDCR_A3ROW (0x00000018uL) +#define BSC_SDCR_BACTV (0x00000100uL) +#define BSC_SDCR_PDOWN (0x00000200uL) +#define BSC_SDCR_RMODE (0x00000400uL) +#define BSC_SDCR_RFSH (0x00000800uL) +#define BSC_SDCR_DEEP (0x00002000uL) +#define BSC_SDCR_A2COL (0x00030000uL) +#define BSC_SDCR_A2ROW (0x00180000uL) + +#define BSC_RTCSR_RRC (0x00000007uL) +#define BSC_RTCSR_CKS (0x00000038uL) +#define BSC_RTCSR_CMIE (0x00000040uL) +#define BSC_RTCSR_CMF (0x00000080uL) + +#define BSC_RTCNT_D (0xFFFFFFFFuL) + +#define BSC_RTCOR_D (0xFFFFFFFFuL) + +#define BSC_TOSCOR0_D (0x0000FFFFuL) + +#define BSC_TOSCOR1_D (0x0000FFFFuL) + +#define BSC_TOSCOR2_D (0x0000FFFFuL) + +#define BSC_TOSCOR3_D (0x0000FFFFuL) + +#define BSC_TOSCOR4_D (0x0000FFFFuL) + +#define BSC_TOSCOR5_D (0x0000FFFFuL) + +#define BSC_TOSTR_CS0TOSTF (0x00000001uL) +#define BSC_TOSTR_CS1TOSTF (0x00000002uL) +#define BSC_TOSTR_CS2TOSTF (0x00000004uL) +#define BSC_TOSTR_CS3TOSTF (0x00000008uL) +#define BSC_TOSTR_CS4TOSTF (0x00000010uL) +#define BSC_TOSTR_CS5TOSTF (0x00000020uL) + +#define BSC_TOENR_CS0TOEN (0x00000001uL) +#define BSC_TOENR_CS1TOEN (0x00000002uL) +#define BSC_TOENR_CS2TOEN (0x00000004uL) +#define BSC_TOENR_CS3TOEN (0x00000008uL) +#define BSC_TOENR_CS4TOEN (0x00000010uL) +#define BSC_TOENR_CS5TOEN (0x00000020uL) + + +/* ==== Shift values for IO registers ==== */ +#define BSC_CMNCR_HIZCNT_SHIFT (0u) +#define BSC_CMNCR_HIZMEM_SHIFT (1u) +#define BSC_CMNCR_DPRTY_SHIFT (9u) +#define BSC_CMNCR_AL0_SHIFT (24u) +#define BSC_CMNCR_TL0_SHIFT (28u) + +#define BSC_CS0BCR_BSZ_SHIFT (9u) +#define BSC_CS0BCR_TYPE_SHIFT (12u) +#define BSC_CS0BCR_IWRRS_SHIFT (16u) +#define BSC_CS0BCR_IWRRD_SHIFT (19u) +#define BSC_CS0BCR_IWRWS_SHIFT (22u) +#define BSC_CS0BCR_IWRWD_SHIFT (25u) +#define BSC_CS0BCR_IWW_SHIFT (28u) + +#define BSC_CS1BCR_BSZ_SHIFT (9u) +#define BSC_CS1BCR_TYPE_SHIFT (12u) +#define BSC_CS1BCR_IWRRS_SHIFT (16u) +#define BSC_CS1BCR_IWRRD_SHIFT (19u) +#define BSC_CS1BCR_IWRWS_SHIFT (22u) +#define BSC_CS1BCR_IWRWD_SHIFT (25u) +#define BSC_CS1BCR_IWW_SHIFT (28u) + +#define BSC_CS2BCR_BSZ_SHIFT (9u) +#define BSC_CS2BCR_TYPE_SHIFT (12u) +#define BSC_CS2BCR_IWRRS_SHIFT (16u) +#define BSC_CS2BCR_IWRRD_SHIFT (19u) +#define BSC_CS2BCR_IWRWS_SHIFT (22u) +#define BSC_CS2BCR_IWRWD_SHIFT (25u) +#define BSC_CS2BCR_IWW_SHIFT (28u) + +#define BSC_CS3BCR_BSZ_SHIFT (9u) +#define BSC_CS3BCR_TYPE_SHIFT (12u) +#define BSC_CS3BCR_IWRRS_SHIFT (16u) +#define BSC_CS3BCR_IWRRD_SHIFT (19u) +#define BSC_CS3BCR_IWRWS_SHIFT (22u) +#define BSC_CS3BCR_IWRWD_SHIFT (25u) +#define BSC_CS3BCR_IWW_SHIFT (28u) + +#define BSC_CS4BCR_BSZ_SHIFT (9u) +#define BSC_CS4BCR_TYPE_SHIFT (12u) +#define BSC_CS4BCR_IWRRS_SHIFT (16u) +#define BSC_CS4BCR_IWRRD_SHIFT (19u) +#define BSC_CS4BCR_IWRWS_SHIFT (22u) +#define BSC_CS4BCR_IWRWD_SHIFT (25u) +#define BSC_CS4BCR_IWW_SHIFT (28u) + +#define BSC_CS5BCR_BSZ_SHIFT (9u) +#define BSC_CS5BCR_TYPE_SHIFT (12u) +#define BSC_CS5BCR_IWRRS_SHIFT (16u) +#define BSC_CS5BCR_IWRRD_SHIFT (19u) +#define BSC_CS5BCR_IWRWS_SHIFT (22u) +#define BSC_CS5BCR_IWRWD_SHIFT (25u) +#define BSC_CS5BCR_IWW_SHIFT (28u) + +#define BSC_CS0WCR_NORMAL_HW_SHIFT (0u) +#define BSC_CS0WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS0WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS0WCR_NORMAL_SW_SHIFT (11u) +#define BSC_CS0WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS1WCR_NORMAL_HW_SHIFT (0u) +#define BSC_CS1WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS1WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS1WCR_NORMAL_SW_SHIFT (11u) +#define BSC_CS1WCR_NORMAL_WW_SHIFT (16u) +#define BSC_CS1WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS2WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS2WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS2WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS3WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS3WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS3WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS4WCR_NORMAL_HW_SHIFT (0u) +#define BSC_CS4WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS4WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS4WCR_NORMAL_SW_SHIFT (11u) +#define BSC_CS4WCR_NORMAL_WW_SHIFT (16u) +#define BSC_CS4WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS5WCR_NORMAL_HW_SHIFT (0u) +#define BSC_CS5WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS5WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS5WCR_NORMAL_SW_SHIFT (11u) +#define BSC_CS5WCR_NORMAL_WW_SHIFT (16u) +#define BSC_CS5WCR_NORMAL_MPXWBAS_SHIFT (20u) +#define BSC_CS5WCR_NORMAL_SZSEL_SHIFT (21u) + +#define BSC_CS0WCR_BROM_ASY_WM_SHIFT (6u) +#define BSC_CS0WCR_BROM_ASY_W_SHIFT (7u) +#define BSC_CS0WCR_BROM_ASY_BW_SHIFT (16u) +#define BSC_CS0WCR_BROM_ASY_BST_SHIFT (20u) + +#define BSC_CS4WCR_BROM_ASY_HW_SHIFT (0u) +#define BSC_CS4WCR_BROM_ASY_WM_SHIFT (6u) +#define BSC_CS4WCR_BROM_ASY_W_SHIFT (7u) +#define BSC_CS4WCR_BROM_ASY_SW_SHIFT (11u) +#define BSC_CS4WCR_BROM_ASY_BW_SHIFT (16u) +#define BSC_CS4WCR_BROM_ASY_BST_SHIFT (20u) + +#define BSC_CS2WCR_SDRAM_A2CL_SHIFT (7u) + +#define BSC_CS3WCR_SDRAM_WTRC_SHIFT (0u) +#define BSC_CS3WCR_SDRAM_TRWL_SHIFT (3u) +#define BSC_CS3WCR_SDRAM_A3CL_SHIFT (7u) +#define BSC_CS3WCR_SDRAM_WTRCD_SHIFT (10u) +#define BSC_CS3WCR_SDRAM_WTRP_SHIFT (13u) + +#define BSC_CS0WCR_BROM_SY_WM_SHIFT (6u) +#define BSC_CS0WCR_BROM_SY_W_SHIFT (7u) +#define BSC_CS0WCR_BROM_SY_BW_SHIFT (16u) + +#define BSC_SDCR_A3COL_SHIFT (0u) +#define BSC_SDCR_A3ROW_SHIFT (3u) +#define BSC_SDCR_BACTV_SHIFT (8u) +#define BSC_SDCR_PDOWN_SHIFT (9u) +#define BSC_SDCR_RMODE_SHIFT (10u) +#define BSC_SDCR_RFSH_SHIFT (11u) +#define BSC_SDCR_DEEP_SHIFT (13u) +#define BSC_SDCR_A2COL_SHIFT (16u) +#define BSC_SDCR_A2ROW_SHIFT (19u) + +#define BSC_RTCSR_RRC_SHIFT (0u) +#define BSC_RTCSR_CKS_SHIFT (3u) +#define BSC_RTCSR_CMIE_SHIFT (6u) +#define BSC_RTCSR_CMF_SHIFT (7u) + +#define BSC_RTCNT_D_SHIFT (0u) + +#define BSC_RTCOR_D_SHIFT (0u) + +#define BSC_TOSCOR0_D_SHIFT (0u) + +#define BSC_TOSCOR1_D_SHIFT (0u) + +#define BSC_TOSCOR2_D_SHIFT (0u) + +#define BSC_TOSCOR3_D_SHIFT (0u) + +#define BSC_TOSCOR4_D_SHIFT (0u) + +#define BSC_TOSCOR5_D_SHIFT (0u) + +#define BSC_TOSTR_CS0TOSTF_SHIFT (0u) +#define BSC_TOSTR_CS1TOSTF_SHIFT (1u) +#define BSC_TOSTR_CS2TOSTF_SHIFT (2u) +#define BSC_TOSTR_CS3TOSTF_SHIFT (3u) +#define BSC_TOSTR_CS4TOSTF_SHIFT (4u) +#define BSC_TOSTR_CS5TOSTF_SHIFT (5u) + +#define BSC_TOENR_CS0TOEN_SHIFT (0u) +#define BSC_TOENR_CS1TOEN_SHIFT (1u) +#define BSC_TOENR_CS2TOEN_SHIFT (2u) +#define BSC_TOENR_CS3TOEN_SHIFT (3u) +#define BSC_TOENR_CS4TOEN_SHIFT (4u) +#define BSC_TOENR_CS5TOEN_SHIFT (5u) + + +#endif /* BSC_IOBITMASK_H */ + +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,462 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : cpg_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : CPG register define header +*******************************************************************************/ +#ifndef CPG_IOBITMASK_H +#define CPG_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define CPG_FRQCR_IFC (0x0300u) +#define CPG_FRQCR_CKOEN (0x3000u) +#define CPG_FRQCR_CKOEN2 (0x4000u) + +#define CPG_FRQCR2_GFC (0x0003u) + +#define CPG_CPUSTS_ISBUSY (0x10u) + +#define CPG_STBCR1_DEEP (0x40u) +#define CPG_STBCR1_STBY (0x80u) + +#define CPG_STBCR2_MSTP20 (0x01u) +#define CPG_STBCR2_HIZ (0x80u) + +#define CPG_STBREQ1_STBRQ10 (0x01u) +#define CPG_STBREQ1_STBRQ12 (0x04u) +#define CPG_STBREQ1_STBRQ13 (0x08u) +#define CPG_STBREQ1_STBRQ15 (0x20u) + +#define CPG_STBREQ2_STBRQ20 (0x01u) +#define CPG_STBREQ2_STBRQ21 (0x02u) +#define CPG_STBREQ2_STBRQ22 (0x04u) +#define CPG_STBREQ2_STBRQ23 (0x08u) +#define CPG_STBREQ2_STBRQ24 (0x10u) +#define CPG_STBREQ2_STBRQ25 (0x20u) +#define CPG_STBREQ2_STBRQ26 (0x40u) +#define CPG_STBREQ2_STBRQ27 (0x80u) + +#define CPG_STBACK1_STBAK10 (0x01u) +#define CPG_STBACK1_STBAK12 (0x04u) +#define CPG_STBACK1_STBAK13 (0x08u) +#define CPG_STBACK1_STBAK15 (0x20u) + +#define CPG_STBACK2_STBAK20 (0x01u) +#define CPG_STBACK2_STBAK21 (0x02u) +#define CPG_STBACK2_STBAK22 (0x04u) +#define CPG_STBACK2_STBAK23 (0x08u) +#define CPG_STBACK2_STBAK24 (0x10u) +#define CPG_STBACK2_STBAK25 (0x20u) +#define CPG_STBACK2_STBAK26 (0x40u) +#define CPG_STBACK2_STBAK27 (0x80u) + +#define CPG_SYSCR1_VRAME0 (0x01u) +#define CPG_SYSCR1_VRAME1 (0x02u) +#define CPG_SYSCR1_VRAME2 (0x04u) +#define CPG_SYSCR1_VRAME3 (0x08u) +#define CPG_SYSCR1_VRAME4 (0x10u) + +#define CPG_SYSCR2_VRAMWE0 (0x01u) +#define CPG_SYSCR2_VRAMWE1 (0x02u) +#define CPG_SYSCR2_VRAMWE2 (0x04u) +#define CPG_SYSCR2_VRAMWE3 (0x08u) +#define CPG_SYSCR2_VRAMWE4 (0x10u) + +#define CPG_SYSCR3_RRAMWE0 (0x01u) +#define CPG_SYSCR3_RRAMWE1 (0x02u) +#define CPG_SYSCR3_RRAMWE2 (0x04u) +#define CPG_SYSCR3_RRAMWE3 (0x08u) + +#define CPG_STBCR3_MSTP30 (0x01u) +#define CPG_STBCR3_MSTP31 (0x02u) +#define CPG_STBCR3_MSTP32 (0x04u) +#define CPG_STBCR3_MSTP33 (0x08u) +#define CPG_STBCR3_MSTP34 (0x10u) +#define CPG_STBCR3_MSTP35 (0x20u) +#define CPG_STBCR3_MSTP36 (0x40u) +#define CPG_STBCR3_MSTP37 (0x80u) + +#define CPG_STBCR4_MSTP40 (0x01u) +#define CPG_STBCR4_MSTP41 (0x02u) +#define CPG_STBCR4_MSTP42 (0x04u) +#define CPG_STBCR4_MSTP43 (0x08u) +#define CPG_STBCR4_MSTP44 (0x10u) +#define CPG_STBCR4_MSTP45 (0x20u) +#define CPG_STBCR4_MSTP46 (0x40u) +#define CPG_STBCR4_MSTP47 (0x80u) + +#define CPG_STBCR5_MSTP50 (0x01u) +#define CPG_STBCR5_MSTP51 (0x02u) +#define CPG_STBCR5_MSTP52 (0x04u) +#define CPG_STBCR5_MSTP53 (0x08u) +#define CPG_STBCR5_MSTP54 (0x10u) +#define CPG_STBCR5_MSTP55 (0x20u) +#define CPG_STBCR5_MSTP56 (0x40u) +#define CPG_STBCR5_MSTP57 (0x80u) + +#define CPG_STBCR6_MSTP60 (0x01u) +#define CPG_STBCR6_MSTP61 (0x02u) +#define CPG_STBCR6_MSTP62 (0x04u) +#define CPG_STBCR6_MSTP63 (0x08u) +#define CPG_STBCR6_MSTP64 (0x10u) +#define CPG_STBCR6_MSTP65 (0x20u) +#define CPG_STBCR6_MSTP66 (0x40u) +#define CPG_STBCR6_MSTP67 (0x80u) + +#define CPG_STBCR7_MSTP70 (0x01u) +#define CPG_STBCR7_MSTP71 (0x02u) +#define CPG_STBCR7_MSTP73 (0x08u) +#define CPG_STBCR7_MSTP74 (0x10u) +#define CPG_STBCR7_MSTP76 (0x40u) +#define CPG_STBCR7_MSTP77 (0x80u) + +#define CPG_STBCR8_MSTP81 (0x02u) +#define CPG_STBCR8_MSTP82 (0x04u) +#define CPG_STBCR8_MSTP83 (0x08u) +#define CPG_STBCR8_MSTP84 (0x10u) +#define CPG_STBCR8_MSTP85 (0x20u) +#define CPG_STBCR8_MSTP86 (0x40u) +#define CPG_STBCR8_MSTP87 (0x80u) + +#define CPG_STBCR9_MSTP90 (0x01u) +#define CPG_STBCR9_MSTP91 (0x02u) +#define CPG_STBCR9_MSTP92 (0x04u) +#define CPG_STBCR9_MSTP93 (0x08u) +#define CPG_STBCR9_MSTP94 (0x10u) +#define CPG_STBCR9_MSTP95 (0x20u) +#define CPG_STBCR9_MSTP96 (0x40u) +#define CPG_STBCR9_MSTP97 (0x80u) + +#define CPG_STBCR10_MSTP100 (0x01u) +#define CPG_STBCR10_MSTP101 (0x02u) +#define CPG_STBCR10_MSTP102 (0x04u) +#define CPG_STBCR10_MSTP103 (0x08u) +#define CPG_STBCR10_MSTP104 (0x10u) +#define CPG_STBCR10_MSTP105 (0x20u) +#define CPG_STBCR10_MSTP106 (0x40u) +#define CPG_STBCR10_MSTP107 (0x80u) + +#define CPG_STBCR11_MSTP110 (0x01u) +#define CPG_STBCR11_MSTP111 (0x02u) +#define CPG_STBCR11_MSTP112 (0x04u) +#define CPG_STBCR11_MSTP113 (0x08u) +#define CPG_STBCR11_MSTP114 (0x10u) +#define CPG_STBCR11_MSTP115 (0x20u) + +#define CPG_STBCR12_MSTP120 (0x01u) +#define CPG_STBCR12_MSTP121 (0x02u) +#define CPG_STBCR12_MSTP122 (0x04u) +#define CPG_STBCR12_MSTP123 (0x08u) + +#define CPG_STBCR13_MSTP131 (0x02u) +#define CPG_STBCR13_MSTP132 (0x04u) + +#define CPG_SWRSTCR1_SRST11 (0x02u) +#define CPG_SWRSTCR1_SRST12 (0x04u) +#define CPG_SWRSTCR1_SRST13 (0x08u) +#define CPG_SWRSTCR1_SRST14 (0x10u) +#define CPG_SWRSTCR1_SRST15 (0x20u) +#define CPG_SWRSTCR1_SRST16 (0x40u) +#define CPG_SWRSTCR1_AXTALE (0x80u) + +#define CPG_SWRSTCR2_SRST21 (0x02u) + +#define CPG_SWRSTCR3_SRST32 (0x04u) + +#define CPG_RRAMKP_RRAMKP0 (0x01u) +#define CPG_RRAMKP_RRAMKP1 (0x02u) +#define CPG_RRAMKP_RRAMKP2 (0x04u) +#define CPG_RRAMKP_RRAMKP3 (0x08u) + +#define CPG_DSCTR_RAMBOOT (0x40u) +#define CPG_DSCTR_EBUSKEEPE (0x80u) + +#define CPG_DSSSR_P8_2 (0x0001u) +#define CPG_DSSSR_P9_1 (0x0002u) +#define CPG_DSSSR_P2_15 (0x0004u) +#define CPG_DSSSR_P7_8 (0x0008u) +#define CPG_DSSSR_P5_9 (0x0010u) +#define CPG_DSSSR_P6_4 (0x0020u) +#define CPG_DSSSR_RTCAR (0x0040u) +#define CPG_DSSSR_NMI (0x0100u) +#define CPG_DSSSR_P3_3 (0x0200u) +#define CPG_DSSSR_P8_7 (0x0400u) +#define CPG_DSSSR_P2_12 (0x0800u) +#define CPG_DSSSR_P3_1 (0x1000u) +#define CPG_DSSSR_P3_9 (0x2000u) +#define CPG_DSSSR_P6_2 (0x4000u) + +#define CPG_DSESR_P8_2E (0x0001u) +#define CPG_DSESR_P9_1E (0x0002u) +#define CPG_DSESR_P2_15E (0x0004u) +#define CPG_DSESR_P7_8E (0x0008u) +#define CPG_DSESR_P5_9E (0x0010u) +#define CPG_DSESR_P6_4E (0x0020u) +#define CPG_DSESR_NMIE (0x0100u) +#define CPG_DSESR_P3_3E (0x0200u) +#define CPG_DSESR_P8_7E (0x0400u) +#define CPG_DSESR_P2_12E (0x0800u) +#define CPG_DSESR_P3_1E (0x1000u) +#define CPG_DSESR_P3_9E (0x2000u) +#define CPG_DSESR_P6_2E (0x4000u) + +#define CPG_DSFR_P8_2F (0x0001u) +#define CPG_DSFR_P9_1F (0x0002u) +#define CPG_DSFR_P2_15F (0x0004u) +#define CPG_DSFR_P7_8F (0x0008u) +#define CPG_DSFR_P5_9F (0x0010u) +#define CPG_DSFR_P6_4F (0x0020u) +#define CPG_DSFR_RTCARF (0x0040u) +#define CPG_DSFR_NMIF (0x0100u) +#define CPG_DSFR_P3_3F (0x0200u) +#define CPG_DSFR_P8_7F (0x0400u) +#define CPG_DSFR_P2_12F (0x0800u) +#define CPG_DSFR_P3_1F (0x1000u) +#define CPG_DSFR_P3_9F (0x2000u) +#define CPG_DSFR_P6_2F (0x4000u) +#define CPG_DSFR_IOKEEP (0x8000u) + +#define CPG_XTALCTR_GAIN0 (0x01u) +#define CPG_XTALCTR_GAIN1 (0x02u) + + +/* ==== Shift values for IO registers ==== */ +#define CPG_FRQCR_IFC_SHIFT (8u) +#define CPG_FRQCR_CKOEN_SHIFT (12u) +#define CPG_FRQCR_CKOEN2_SHIFT (14u) + +#define CPG_FRQCR2_GFC_SHIFT (0u) + +#define CPG_CPUSTS_ISBUSY_SHIFT (4u) + +#define CPG_STBCR1_DEEP_SHIFT (6u) +#define CPG_STBCR1_STBY_SHIFT (7u) + +#define CPG_STBCR2_MSTP20_SHIFT (0u) +#define CPG_STBCR2_HIZ_SHIFT (7u) + +#define CPG_STBREQ1_STBRQ10_SHIFT (0u) +#define CPG_STBREQ1_STBRQ12_SHIFT (2u) +#define CPG_STBREQ1_STBRQ13_SHIFT (3u) +#define CPG_STBREQ1_STBRQ15_SHIFT (5u) + +#define CPG_STBREQ2_STBRQ20_SHIFT (0u) +#define CPG_STBREQ2_STBRQ21_SHIFT (1u) +#define CPG_STBREQ2_STBRQ22_SHIFT (2u) +#define CPG_STBREQ2_STBRQ23_SHIFT (3u) +#define CPG_STBREQ2_STBRQ24_SHIFT (4u) +#define CPG_STBREQ2_STBRQ25_SHIFT (5u) +#define CPG_STBREQ2_STBRQ26_SHIFT (6u) +#define CPG_STBREQ2_STBRQ27_SHIFT (7u) + +#define CPG_STBACK1_STBAK10_SHIFT (0u) +#define CPG_STBACK1_STBAK12_SHIFT (2u) +#define CPG_STBACK1_STBAK13_SHIFT (3u) +#define CPG_STBACK1_STBAK15_SHIFT (5u) + +#define CPG_STBACK2_STBAK20_SHIFT (0u) +#define CPG_STBACK2_STBAK21_SHIFT (1u) +#define CPG_STBACK2_STBAK22_SHIFT (2u) +#define CPG_STBACK2_STBAK23_SHIFT (3u) +#define CPG_STBACK2_STBAK24_SHIFT (4u) +#define CPG_STBACK2_STBAK25_SHIFT (5u) +#define CPG_STBACK2_STBAK26_SHIFT (6u) +#define CPG_STBACK2_STBAK27_SHIFT (7u) + +#define CPG_SYSCR1_VRAME0_SHIFT (0u) +#define CPG_SYSCR1_VRAME1_SHIFT (1u) +#define CPG_SYSCR1_VRAME2_SHIFT (2u) +#define CPG_SYSCR1_VRAME3_SHIFT (3u) +#define CPG_SYSCR1_VRAME4_SHIFT (4u) + +#define CPG_SYSCR2_VRAMWE0_SHIFT (0u) +#define CPG_SYSCR2_VRAMWE1_SHIFT (1u) +#define CPG_SYSCR2_VRAMWE2_SHIFT (2u) +#define CPG_SYSCR2_VRAMWE3_SHIFT (3u) +#define CPG_SYSCR2_VRAMWE4_SHIFT (4u) + +#define CPG_SYSCR3_RRAMWE0_SHIFT (0u) +#define CPG_SYSCR3_RRAMWE1_SHIFT (1u) +#define CPG_SYSCR3_RRAMWE2_SHIFT (2u) +#define CPG_SYSCR3_RRAMWE3_SHIFT (3u) + +#define CPG_STBCR3_MSTP30_SHIFT (0u) +#define CPG_STBCR3_MSTP31_SHIFT (1u) +#define CPG_STBCR3_MSTP32_SHIFT (2u) +#define CPG_STBCR3_MSTP33_SHIFT (3u) +#define CPG_STBCR3_MSTP34_SHIFT (4u) +#define CPG_STBCR3_MSTP35_SHIFT (5u) +#define CPG_STBCR3_MSTP36_SHIFT (6u) +#define CPG_STBCR3_MSTP37_SHIFT (7u) + +#define CPG_STBCR4_MSTP40_SHIFT (0u) +#define CPG_STBCR4_MSTP41_SHIFT (1u) +#define CPG_STBCR4_MSTP42_SHIFT (2u) +#define CPG_STBCR4_MSTP43_SHIFT (3u) +#define CPG_STBCR4_MSTP44_SHIFT (4u) +#define CPG_STBCR4_MSTP45_SHIFT (5u) +#define CPG_STBCR4_MSTP46_SHIFT (6u) +#define CPG_STBCR4_MSTP47_SHIFT (7u) + +#define CPG_STBCR5_MSTP50_SHIFT (0u) +#define CPG_STBCR5_MSTP51_SHIFT (1u) +#define CPG_STBCR5_MSTP52_SHIFT (2u) +#define CPG_STBCR5_MSTP53_SHIFT (3u) +#define CPG_STBCR5_MSTP54_SHIFT (4u) +#define CPG_STBCR5_MSTP55_SHIFT (5u) +#define CPG_STBCR5_MSTP56_SHIFT (6u) +#define CPG_STBCR5_MSTP57_SHIFT (7u) + +#define CPG_STBCR6_MSTP60_SHIFT (0u) +#define CPG_STBCR6_MSTP61_SHIFT (1u) +#define CPG_STBCR6_MSTP62_SHIFT (2u) +#define CPG_STBCR6_MSTP63_SHIFT (3u) +#define CPG_STBCR6_MSTP64_SHIFT (4u) +#define CPG_STBCR6_MSTP65_SHIFT (5u) +#define CPG_STBCR6_MSTP66_SHIFT (6u) +#define CPG_STBCR6_MSTP67_SHIFT (7u) + +#define CPG_STBCR7_MSTP70_SHIFT (0u) +#define CPG_STBCR7_MSTP71_SHIFT (1u) +#define CPG_STBCR7_MSTP73_SHIFT (3u) +#define CPG_STBCR7_MSTP74_SHIFT (4u) +#define CPG_STBCR7_MSTP76_SHIFT (6u) +#define CPG_STBCR7_MSTP77_SHIFT (7u) + +#define CPG_STBCR8_MSTP81_SHIFT (1u) +#define CPG_STBCR8_MSTP82_SHIFT (2u) +#define CPG_STBCR8_MSTP83_SHIFT (3u) +#define CPG_STBCR8_MSTP84_SHIFT (4u) +#define CPG_STBCR8_MSTP85_SHIFT (5u) +#define CPG_STBCR8_MSTP86_SHIFT (6u) +#define CPG_STBCR8_MSTP87_SHIFT (7u) + +#define CPG_STBCR9_MSTP90_SHIFT (0u) +#define CPG_STBCR9_MSTP91_SHIFT (1u) +#define CPG_STBCR9_MSTP92_SHIFT (2u) +#define CPG_STBCR9_MSTP93_SHIFT (3u) +#define CPG_STBCR9_MSTP94_SHIFT (4u) +#define CPG_STBCR9_MSTP95_SHIFT (5u) +#define CPG_STBCR9_MSTP96_SHIFT (6u) +#define CPG_STBCR9_MSTP97_SHIFT (7u) + +#define CPG_STBCR10_MSTP100_SHIFT (0u) +#define CPG_STBCR10_MSTP101_SHIFT (1u) +#define CPG_STBCR10_MSTP102_SHIFT (2u) +#define CPG_STBCR10_MSTP103_SHIFT (3u) +#define CPG_STBCR10_MSTP104_SHIFT (4u) +#define CPG_STBCR10_MSTP105_SHIFT (5u) +#define CPG_STBCR10_MSTP106_SHIFT (6u) +#define CPG_STBCR10_MSTP107_SHIFT (7u) + +#define CPG_STBCR11_MSTP110_SHIFT (0u) +#define CPG_STBCR11_MSTP111_SHIFT (1u) +#define CPG_STBCR11_MSTP112_SHIFT (2u) +#define CPG_STBCR11_MSTP113_SHIFT (3u) +#define CPG_STBCR11_MSTP114_SHIFT (4u) +#define CPG_STBCR11_MSTP115_SHIFT (5u) + +#define CPG_STBCR12_MSTP120_SHIFT (0u) +#define CPG_STBCR12_MSTP121_SHIFT (1u) +#define CPG_STBCR12_MSTP122_SHIFT (2u) +#define CPG_STBCR12_MSTP123_SHIFT (3u) + +#define CPG_STBCR13_MSTP131_SHIFT (1u) +#define CPG_STBCR13_MSTP132_SHIFT (2u) + +#define CPG_SWRSTCR1_SRST11_SHIFT (1u) +#define CPG_SWRSTCR1_SRST12_SHIFT (2u) +#define CPG_SWRSTCR1_SRST13_SHIFT (3u) +#define CPG_SWRSTCR1_SRST14_SHIFT (4u) +#define CPG_SWRSTCR1_SRST15_SHIFT (5u) +#define CPG_SWRSTCR1_SRST16_SHIFT (6u) +#define CPG_SWRSTCR1_AXTALE_SHIFT (7u) + +#define CPG_SWRSTCR2_SRST21_SHIFT (1u) + +#define CPG_SWRSTCR3_SRST32_SHIFT (2u) + +#define CPG_RRAMKP_RRAMKP0_SHIFT (0u) +#define CPG_RRAMKP_RRAMKP1_SHIFT (1u) +#define CPG_RRAMKP_RRAMKP2_SHIFT (2u) +#define CPG_RRAMKP_RRAMKP3_SHIFT (3u) + +#define CPG_DSCTR_RAMBOOT_SHIFT (6u) +#define CPG_DSCTR_EBUSKEEPE_SHIFT (7u) + +#define CPG_DSSSR_P8_2_SHIFT (0u) +#define CPG_DSSSR_P9_1_SHIFT (1u) +#define CPG_DSSSR_P2_15_SHIFT (2u) +#define CPG_DSSSR_P7_8_SHIFT (3u) +#define CPG_DSSSR_P5_9_SHIFT (4u) +#define CPG_DSSSR_P6_4_SHIFT (5u) +#define CPG_DSSSR_RTCAR_SHIFT (6u) +#define CPG_DSSSR_NMI_SHIFT (8u) +#define CPG_DSSSR_P3_3_SHIFT (9u) +#define CPG_DSSSR_P8_7_SHIFT (10u) +#define CPG_DSSSR_P2_12_SHIFT (11u) +#define CPG_DSSSR_P3_1_SHIFT (12u) +#define CPG_DSSSR_P3_9_SHIFT (13u) +#define CPG_DSSSR_P6_2_SHIFT (14u) + +#define CPG_DSESR_P8_2E_SHIFT (0u) +#define CPG_DSESR_P9_1E_SHIFT (1u) +#define CPG_DSESR_P2_15E_SHIFT (2u) +#define CPG_DSESR_P7_8E_SHIFT (3u) +#define CPG_DSESR_P5_9E_SHIFT (4u) +#define CPG_DSESR_P6_4E_SHIFT (5u) +#define CPG_DSESR_NMIE_SHIFT (8u) +#define CPG_DSESR_P3_3E_SHIFT (9u) +#define CPG_DSESR_P8_7E_SHIFT (10u) +#define CPG_DSESR_P2_12E_SHIFT (11u) +#define CPG_DSESR_P3_1E_SHIFT (12u) +#define CPG_DSESR_P3_9E_SHIFT (13u) +#define CPG_DSESR_P6_2E_SHIFT (14u) + +#define CPG_DSFR_P8_2F_SHIFT (0u) +#define CPG_DSFR_P9_1F_SHIFT (1u) +#define CPG_DSFR_P2_15F_SHIFT (2u) +#define CPG_DSFR_P7_8F_SHIFT (3u) +#define CPG_DSFR_P5_9F_SHIFT (4u) +#define CPG_DSFR_P6_4F_SHIFT (5u) +#define CPG_DSFR_RTCARF_SHIFT (6u) +#define CPG_DSFR_NMIF_SHIFT (8u) +#define CPG_DSFR_P3_3F_SHIFT (9u) +#define CPG_DSFR_P8_7F_SHIFT (10u) +#define CPG_DSFR_P2_12F_SHIFT (11u) +#define CPG_DSFR_P3_1F_SHIFT (12u) +#define CPG_DSFR_P3_9F_SHIFT (13u) +#define CPG_DSFR_P6_2F_SHIFT (14u) +#define CPG_DSFR_IOKEEP_SHIFT (15u) + +#define CPG_XTALCTR_GAIN0_SHIFT (0u) +#define CPG_XTALCTR_GAIN1_SHIFT (1u) + + +#endif /* CPG_IOBITMASK_H */ + +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,2676 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : dmac_iobitmask.h +* $Rev: 1114 $ +* $Date:: 2014-07-09 14:56:39 +0900#$ +* Description : DMAC register define header +*******************************************************************************/ +#ifndef DMAC_IOBITMASK_H +#define DMAC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +/* ---- DMAC0 ---- */ +#define DMAC0_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC0_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC0_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC0_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC0_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC0_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC0_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC0_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC0_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC0_CHSTAT_n_EN (0x00000001uL) +#define DMAC0_CHSTAT_n_RQST (0x00000002uL) +#define DMAC0_CHSTAT_n_TACT (0x00000004uL) +#define DMAC0_CHSTAT_n_SUS (0x00000008uL) +#define DMAC0_CHSTAT_n_ER (0x00000010uL) +#define DMAC0_CHSTAT_n_END (0x00000020uL) +#define DMAC0_CHSTAT_n_TC (0x00000040uL) +#define DMAC0_CHSTAT_n_SR (0x00000080uL) +#define DMAC0_CHSTAT_n_DL (0x00000100uL) +#define DMAC0_CHSTAT_n_DW (0x00000200uL) +#define DMAC0_CHSTAT_n_DER (0x00000400uL) +#define DMAC0_CHSTAT_n_MODE (0x00000800uL) +#define DMAC0_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC0_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC0_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC0_CHCTRL_n_STG (0x00000004uL) +#define DMAC0_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC0_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC0_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC0_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC0_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC0_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC0_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC0_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC0_CHCFG_n_SEL (0x00000007uL) +#define DMAC0_CHCFG_n_REQD (0x00000008uL) +#define DMAC0_CHCFG_n_LOEN (0x00000010uL) +#define DMAC0_CHCFG_n_HIEN (0x00000020uL) +#define DMAC0_CHCFG_n_LVL (0x00000040uL) +#define DMAC0_CHCFG_n_AM (0x00000700uL) +#define DMAC0_CHCFG_n_SDS (0x0000F000uL) +#define DMAC0_CHCFG_n_DDS (0x000F0000uL) +#define DMAC0_CHCFG_n_SAD (0x00100000uL) +#define DMAC0_CHCFG_n_DAD (0x00200000uL) +#define DMAC0_CHCFG_n_TM (0x00400000uL) +#define DMAC0_CHCFG_n_DEM (0x01000000uL) +#define DMAC0_CHCFG_n_TCM (0x02000000uL) +#define DMAC0_CHCFG_n_SBE (0x08000000uL) +#define DMAC0_CHCFG_n_RSEL (0x10000000uL) +#define DMAC0_CHCFG_n_RSW (0x20000000uL) +#define DMAC0_CHCFG_n_REN (0x40000000uL) +#define DMAC0_CHCFG_n_DMS (0x80000000uL) + +#define DMAC0_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC0_CHEXT_n_SCA (0x000000F0uL) +#define DMAC0_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC0_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC0_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC1 ---- */ +#define DMAC1_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC1_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC1_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC1_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC1_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC1_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC1_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC1_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC1_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC1_CHSTAT_n_EN (0x00000001uL) +#define DMAC1_CHSTAT_n_RQST (0x00000002uL) +#define DMAC1_CHSTAT_n_TACT (0x00000004uL) +#define DMAC1_CHSTAT_n_SUS (0x00000008uL) +#define DMAC1_CHSTAT_n_ER (0x00000010uL) +#define DMAC1_CHSTAT_n_END (0x00000020uL) +#define DMAC1_CHSTAT_n_TC (0x00000040uL) +#define DMAC1_CHSTAT_n_SR (0x00000080uL) +#define DMAC1_CHSTAT_n_DL (0x00000100uL) +#define DMAC1_CHSTAT_n_DW (0x00000200uL) +#define DMAC1_CHSTAT_n_DER (0x00000400uL) +#define DMAC1_CHSTAT_n_MODE (0x00000800uL) +#define DMAC1_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC1_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC1_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC1_CHCTRL_n_STG (0x00000004uL) +#define DMAC1_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC1_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC1_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC1_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC1_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC1_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC1_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC1_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC1_CHCFG_n_SEL (0x00000007uL) +#define DMAC1_CHCFG_n_REQD (0x00000008uL) +#define DMAC1_CHCFG_n_LOEN (0x00000010uL) +#define DMAC1_CHCFG_n_HIEN (0x00000020uL) +#define DMAC1_CHCFG_n_LVL (0x00000040uL) +#define DMAC1_CHCFG_n_AM (0x00000700uL) +#define DMAC1_CHCFG_n_SDS (0x0000F000uL) +#define DMAC1_CHCFG_n_DDS (0x000F0000uL) +#define DMAC1_CHCFG_n_SAD (0x00100000uL) +#define DMAC1_CHCFG_n_DAD (0x00200000uL) +#define DMAC1_CHCFG_n_TM (0x00400000uL) +#define DMAC1_CHCFG_n_DEM (0x01000000uL) +#define DMAC1_CHCFG_n_TCM (0x02000000uL) +#define DMAC1_CHCFG_n_SBE (0x08000000uL) +#define DMAC1_CHCFG_n_RSEL (0x10000000uL) +#define DMAC1_CHCFG_n_RSW (0x20000000uL) +#define DMAC1_CHCFG_n_REN (0x40000000uL) +#define DMAC1_CHCFG_n_DMS (0x80000000uL) + +#define DMAC1_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC1_CHEXT_n_SCA (0x000000F0uL) +#define DMAC1_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC1_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC1_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC2 ---- */ +#define DMAC2_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC2_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC2_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC2_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC2_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC2_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC2_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC2_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC2_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC2_CHSTAT_n_EN (0x00000001uL) +#define DMAC2_CHSTAT_n_RQST (0x00000002uL) +#define DMAC2_CHSTAT_n_TACT (0x00000004uL) +#define DMAC2_CHSTAT_n_SUS (0x00000008uL) +#define DMAC2_CHSTAT_n_ER (0x00000010uL) +#define DMAC2_CHSTAT_n_END (0x00000020uL) +#define DMAC2_CHSTAT_n_TC (0x00000040uL) +#define DMAC2_CHSTAT_n_SR (0x00000080uL) +#define DMAC2_CHSTAT_n_DL (0x00000100uL) +#define DMAC2_CHSTAT_n_DW (0x00000200uL) +#define DMAC2_CHSTAT_n_DER (0x00000400uL) +#define DMAC2_CHSTAT_n_MODE (0x00000800uL) +#define DMAC2_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC2_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC2_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC2_CHCTRL_n_STG (0x00000004uL) +#define DMAC2_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC2_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC2_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC2_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC2_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC2_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC2_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC2_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC2_CHCFG_n_SEL (0x00000007uL) +#define DMAC2_CHCFG_n_REQD (0x00000008uL) +#define DMAC2_CHCFG_n_LOEN (0x00000010uL) +#define DMAC2_CHCFG_n_HIEN (0x00000020uL) +#define DMAC2_CHCFG_n_LVL (0x00000040uL) +#define DMAC2_CHCFG_n_AM (0x00000700uL) +#define DMAC2_CHCFG_n_SDS (0x0000F000uL) +#define DMAC2_CHCFG_n_DDS (0x000F0000uL) +#define DMAC2_CHCFG_n_SAD (0x00100000uL) +#define DMAC2_CHCFG_n_DAD (0x00200000uL) +#define DMAC2_CHCFG_n_TM (0x00400000uL) +#define DMAC2_CHCFG_n_DEM (0x01000000uL) +#define DMAC2_CHCFG_n_TCM (0x02000000uL) +#define DMAC2_CHCFG_n_SBE (0x08000000uL) +#define DMAC2_CHCFG_n_RSEL (0x10000000uL) +#define DMAC2_CHCFG_n_RSW (0x20000000uL) +#define DMAC2_CHCFG_n_REN (0x40000000uL) +#define DMAC2_CHCFG_n_DMS (0x80000000uL) + +#define DMAC2_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC2_CHEXT_n_SCA (0x000000F0uL) +#define DMAC2_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC2_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC2_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC3 ---- */ +#define DMAC3_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC3_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC3_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC3_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC3_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC3_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC3_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC3_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC3_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC3_CHSTAT_n_EN (0x00000001uL) +#define DMAC3_CHSTAT_n_RQST (0x00000002uL) +#define DMAC3_CHSTAT_n_TACT (0x00000004uL) +#define DMAC3_CHSTAT_n_SUS (0x00000008uL) +#define DMAC3_CHSTAT_n_ER (0x00000010uL) +#define DMAC3_CHSTAT_n_END (0x00000020uL) +#define DMAC3_CHSTAT_n_TC (0x00000040uL) +#define DMAC3_CHSTAT_n_SR (0x00000080uL) +#define DMAC3_CHSTAT_n_DL (0x00000100uL) +#define DMAC3_CHSTAT_n_DW (0x00000200uL) +#define DMAC3_CHSTAT_n_DER (0x00000400uL) +#define DMAC3_CHSTAT_n_MODE (0x00000800uL) +#define DMAC3_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC3_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC3_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC3_CHCTRL_n_STG (0x00000004uL) +#define DMAC3_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC3_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC3_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC3_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC3_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC3_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC3_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC3_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC3_CHCFG_n_SEL (0x00000007uL) +#define DMAC3_CHCFG_n_REQD (0x00000008uL) +#define DMAC3_CHCFG_n_LOEN (0x00000010uL) +#define DMAC3_CHCFG_n_HIEN (0x00000020uL) +#define DMAC3_CHCFG_n_LVL (0x00000040uL) +#define DMAC3_CHCFG_n_AM (0x00000700uL) +#define DMAC3_CHCFG_n_SDS (0x0000F000uL) +#define DMAC3_CHCFG_n_DDS (0x000F0000uL) +#define DMAC3_CHCFG_n_SAD (0x00100000uL) +#define DMAC3_CHCFG_n_DAD (0x00200000uL) +#define DMAC3_CHCFG_n_TM (0x00400000uL) +#define DMAC3_CHCFG_n_DEM (0x01000000uL) +#define DMAC3_CHCFG_n_TCM (0x02000000uL) +#define DMAC3_CHCFG_n_SBE (0x08000000uL) +#define DMAC3_CHCFG_n_RSEL (0x10000000uL) +#define DMAC3_CHCFG_n_RSW (0x20000000uL) +#define DMAC3_CHCFG_n_REN (0x40000000uL) +#define DMAC3_CHCFG_n_DMS (0x80000000uL) + +#define DMAC3_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC3_CHEXT_n_SCA (0x000000F0uL) +#define DMAC3_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC3_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC3_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC4 ---- */ +#define DMAC4_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC4_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC4_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC4_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC4_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC4_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC4_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC4_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC4_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC4_CHSTAT_n_EN (0x00000001uL) +#define DMAC4_CHSTAT_n_RQST (0x00000002uL) +#define DMAC4_CHSTAT_n_TACT (0x00000004uL) +#define DMAC4_CHSTAT_n_SUS (0x00000008uL) +#define DMAC4_CHSTAT_n_ER (0x00000010uL) +#define DMAC4_CHSTAT_n_END (0x00000020uL) +#define DMAC4_CHSTAT_n_TC (0x00000040uL) +#define DMAC4_CHSTAT_n_SR (0x00000080uL) +#define DMAC4_CHSTAT_n_DL (0x00000100uL) +#define DMAC4_CHSTAT_n_DW (0x00000200uL) +#define DMAC4_CHSTAT_n_DER (0x00000400uL) +#define DMAC4_CHSTAT_n_MODE (0x00000800uL) +#define DMAC4_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC4_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC4_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC4_CHCTRL_n_STG (0x00000004uL) +#define DMAC4_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC4_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC4_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC4_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC4_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC4_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC4_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC4_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC4_CHCFG_n_SEL (0x00000007uL) +#define DMAC4_CHCFG_n_REQD (0x00000008uL) +#define DMAC4_CHCFG_n_LOEN (0x00000010uL) +#define DMAC4_CHCFG_n_HIEN (0x00000020uL) +#define DMAC4_CHCFG_n_LVL (0x00000040uL) +#define DMAC4_CHCFG_n_AM (0x00000700uL) +#define DMAC4_CHCFG_n_SDS (0x0000F000uL) +#define DMAC4_CHCFG_n_DDS (0x000F0000uL) +#define DMAC4_CHCFG_n_SAD (0x00100000uL) +#define DMAC4_CHCFG_n_DAD (0x00200000uL) +#define DMAC4_CHCFG_n_TM (0x00400000uL) +#define DMAC4_CHCFG_n_DEM (0x01000000uL) +#define DMAC4_CHCFG_n_TCM (0x02000000uL) +#define DMAC4_CHCFG_n_SBE (0x08000000uL) +#define DMAC4_CHCFG_n_RSEL (0x10000000uL) +#define DMAC4_CHCFG_n_RSW (0x20000000uL) +#define DMAC4_CHCFG_n_REN (0x40000000uL) +#define DMAC4_CHCFG_n_DMS (0x80000000uL) + +#define DMAC4_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC4_CHEXT_n_SCA (0x000000F0uL) +#define DMAC4_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC4_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC4_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC5 ---- */ +#define DMAC5_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC5_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC5_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC5_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC5_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC5_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC5_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC5_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC5_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC5_CHSTAT_n_EN (0x00000001uL) +#define DMAC5_CHSTAT_n_RQST (0x00000002uL) +#define DMAC5_CHSTAT_n_TACT (0x00000004uL) +#define DMAC5_CHSTAT_n_SUS (0x00000008uL) +#define DMAC5_CHSTAT_n_ER (0x00000010uL) +#define DMAC5_CHSTAT_n_END (0x00000020uL) +#define DMAC5_CHSTAT_n_TC (0x00000040uL) +#define DMAC5_CHSTAT_n_SR (0x00000080uL) +#define DMAC5_CHSTAT_n_DL (0x00000100uL) +#define DMAC5_CHSTAT_n_DW (0x00000200uL) +#define DMAC5_CHSTAT_n_DER (0x00000400uL) +#define DMAC5_CHSTAT_n_MODE (0x00000800uL) +#define DMAC5_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC5_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC5_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC5_CHCTRL_n_STG (0x00000004uL) +#define DMAC5_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC5_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC5_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC5_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC5_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC5_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC5_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC5_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC5_CHCFG_n_SEL (0x00000007uL) +#define DMAC5_CHCFG_n_REQD (0x00000008uL) +#define DMAC5_CHCFG_n_LOEN (0x00000010uL) +#define DMAC5_CHCFG_n_HIEN (0x00000020uL) +#define DMAC5_CHCFG_n_LVL (0x00000040uL) +#define DMAC5_CHCFG_n_AM (0x00000700uL) +#define DMAC5_CHCFG_n_SDS (0x0000F000uL) +#define DMAC5_CHCFG_n_DDS (0x000F0000uL) +#define DMAC5_CHCFG_n_SAD (0x00100000uL) +#define DMAC5_CHCFG_n_DAD (0x00200000uL) +#define DMAC5_CHCFG_n_TM (0x00400000uL) +#define DMAC5_CHCFG_n_DEM (0x01000000uL) +#define DMAC5_CHCFG_n_TCM (0x02000000uL) +#define DMAC5_CHCFG_n_SBE (0x08000000uL) +#define DMAC5_CHCFG_n_RSEL (0x10000000uL) +#define DMAC5_CHCFG_n_RSW (0x20000000uL) +#define DMAC5_CHCFG_n_REN (0x40000000uL) +#define DMAC5_CHCFG_n_DMS (0x80000000uL) + +#define DMAC5_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC5_CHEXT_n_SCA (0x000000F0uL) +#define DMAC5_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC5_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC5_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC6 ---- */ +#define DMAC6_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC6_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC6_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC6_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC6_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC6_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC6_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC6_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC6_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC6_CHSTAT_n_EN (0x00000001uL) +#define DMAC6_CHSTAT_n_RQST (0x00000002uL) +#define DMAC6_CHSTAT_n_TACT (0x00000004uL) +#define DMAC6_CHSTAT_n_SUS (0x00000008uL) +#define DMAC6_CHSTAT_n_ER (0x00000010uL) +#define DMAC6_CHSTAT_n_END (0x00000020uL) +#define DMAC6_CHSTAT_n_TC (0x00000040uL) +#define DMAC6_CHSTAT_n_SR (0x00000080uL) +#define DMAC6_CHSTAT_n_DL (0x00000100uL) +#define DMAC6_CHSTAT_n_DW (0x00000200uL) +#define DMAC6_CHSTAT_n_DER (0x00000400uL) +#define DMAC6_CHSTAT_n_MODE (0x00000800uL) +#define DMAC6_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC6_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC6_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC6_CHCTRL_n_STG (0x00000004uL) +#define DMAC6_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC6_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC6_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC6_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC6_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC6_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC6_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC6_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC6_CHCFG_n_SEL (0x00000007uL) +#define DMAC6_CHCFG_n_REQD (0x00000008uL) +#define DMAC6_CHCFG_n_LOEN (0x00000010uL) +#define DMAC6_CHCFG_n_HIEN (0x00000020uL) +#define DMAC6_CHCFG_n_LVL (0x00000040uL) +#define DMAC6_CHCFG_n_AM (0x00000700uL) +#define DMAC6_CHCFG_n_SDS (0x0000F000uL) +#define DMAC6_CHCFG_n_DDS (0x000F0000uL) +#define DMAC6_CHCFG_n_SAD (0x00100000uL) +#define DMAC6_CHCFG_n_DAD (0x00200000uL) +#define DMAC6_CHCFG_n_TM (0x00400000uL) +#define DMAC6_CHCFG_n_DEM (0x01000000uL) +#define DMAC6_CHCFG_n_TCM (0x02000000uL) +#define DMAC6_CHCFG_n_SBE (0x08000000uL) +#define DMAC6_CHCFG_n_RSEL (0x10000000uL) +#define DMAC6_CHCFG_n_RSW (0x20000000uL) +#define DMAC6_CHCFG_n_REN (0x40000000uL) +#define DMAC6_CHCFG_n_DMS (0x80000000uL) + +#define DMAC6_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC6_CHEXT_n_SCA (0x000000F0uL) +#define DMAC6_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC6_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC6_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC7 ---- */ +#define DMAC7_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC7_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC7_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC7_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC7_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC7_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC7_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC7_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC7_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC7_CHSTAT_n_EN (0x00000001uL) +#define DMAC7_CHSTAT_n_RQST (0x00000002uL) +#define DMAC7_CHSTAT_n_TACT (0x00000004uL) +#define DMAC7_CHSTAT_n_SUS (0x00000008uL) +#define DMAC7_CHSTAT_n_ER (0x00000010uL) +#define DMAC7_CHSTAT_n_END (0x00000020uL) +#define DMAC7_CHSTAT_n_TC (0x00000040uL) +#define DMAC7_CHSTAT_n_SR (0x00000080uL) +#define DMAC7_CHSTAT_n_DL (0x00000100uL) +#define DMAC7_CHSTAT_n_DW (0x00000200uL) +#define DMAC7_CHSTAT_n_DER (0x00000400uL) +#define DMAC7_CHSTAT_n_MODE (0x00000800uL) +#define DMAC7_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC7_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC7_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC7_CHCTRL_n_STG (0x00000004uL) +#define DMAC7_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC7_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC7_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC7_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC7_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC7_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC7_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC7_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC7_CHCFG_n_SEL (0x00000007uL) +#define DMAC7_CHCFG_n_REQD (0x00000008uL) +#define DMAC7_CHCFG_n_LOEN (0x00000010uL) +#define DMAC7_CHCFG_n_HIEN (0x00000020uL) +#define DMAC7_CHCFG_n_LVL (0x00000040uL) +#define DMAC7_CHCFG_n_AM (0x00000700uL) +#define DMAC7_CHCFG_n_SDS (0x0000F000uL) +#define DMAC7_CHCFG_n_DDS (0x000F0000uL) +#define DMAC7_CHCFG_n_SAD (0x00100000uL) +#define DMAC7_CHCFG_n_DAD (0x00200000uL) +#define DMAC7_CHCFG_n_TM (0x00400000uL) +#define DMAC7_CHCFG_n_DEM (0x01000000uL) +#define DMAC7_CHCFG_n_TCM (0x02000000uL) +#define DMAC7_CHCFG_n_SBE (0x08000000uL) +#define DMAC7_CHCFG_n_RSEL (0x10000000uL) +#define DMAC7_CHCFG_n_RSW (0x20000000uL) +#define DMAC7_CHCFG_n_REN (0x40000000uL) +#define DMAC7_CHCFG_n_DMS (0x80000000uL) + +#define DMAC7_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC7_CHEXT_n_SCA (0x000000F0uL) +#define DMAC7_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC7_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC7_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC0-7 ---- */ +#define DMAC07_DCTRL_0_7_PR (0x00000001uL) +#define DMAC07_DCTRL_0_7_LVINT (0x00000002uL) +#define DMAC07_DCTRL_0_7_LDCA (0x0000003CuL) +#define DMAC07_DCTRL_0_7_LWCA (0x000003C0uL) + +#define DMAC07_DSTAT_EN_0_7_EN0 (0x00000001uL) +#define DMAC07_DSTAT_EN_0_7_EN1 (0x00000002uL) +#define DMAC07_DSTAT_EN_0_7_EN2 (0x00000004uL) +#define DMAC07_DSTAT_EN_0_7_EN3 (0x00000008uL) +#define DMAC07_DSTAT_EN_0_7_EN4 (0x00000010uL) +#define DMAC07_DSTAT_EN_0_7_EN5 (0x00000020uL) +#define DMAC07_DSTAT_EN_0_7_EN6 (0x00000040uL) +#define DMAC07_DSTAT_EN_0_7_EN7 (0x00000080uL) + +#define DMAC07_DSTAT_ER_0_7_ER0 (0x00000001uL) +#define DMAC07_DSTAT_ER_0_7_ER1 (0x00000002uL) +#define DMAC07_DSTAT_ER_0_7_ER2 (0x00000004uL) +#define DMAC07_DSTAT_ER_0_7_ER3 (0x00000008uL) +#define DMAC07_DSTAT_ER_0_7_ER4 (0x00000010uL) +#define DMAC07_DSTAT_ER_0_7_ER5 (0x00000020uL) +#define DMAC07_DSTAT_ER_0_7_ER6 (0x00000040uL) +#define DMAC07_DSTAT_ER_0_7_ER7 (0x00000080uL) + +#define DMAC07_DSTAT_END_0_7_END0 (0x00000001uL) +#define DMAC07_DSTAT_END_0_7_END1 (0x00000002uL) +#define DMAC07_DSTAT_END_0_7_END2 (0x00000004uL) +#define DMAC07_DSTAT_END_0_7_END3 (0x00000008uL) +#define DMAC07_DSTAT_END_0_7_END4 (0x00000010uL) +#define DMAC07_DSTAT_END_0_7_END5 (0x00000020uL) +#define DMAC07_DSTAT_END_0_7_END6 (0x00000040uL) +#define DMAC07_DSTAT_END_0_7_END7 (0x00000080uL) + +#define DMAC07_DSTAT_TC_0_7_TC0 (0x00000001uL) +#define DMAC07_DSTAT_TC_0_7_TC1 (0x00000002uL) +#define DMAC07_DSTAT_TC_0_7_TC2 (0x00000004uL) +#define DMAC07_DSTAT_TC_0_7_TC3 (0x00000008uL) +#define DMAC07_DSTAT_TC_0_7_TC4 (0x00000010uL) +#define DMAC07_DSTAT_TC_0_7_TC5 (0x00000020uL) +#define DMAC07_DSTAT_TC_0_7_TC6 (0x00000040uL) +#define DMAC07_DSTAT_TC_0_7_TC7 (0x00000080uL) + +#define DMAC07_DSTAT_SUS_0_7_SUS0 (0x00000001uL) +#define DMAC07_DSTAT_SUS_0_7_SUS1 (0x00000002uL) +#define DMAC07_DSTAT_SUS_0_7_SUS2 (0x00000004uL) +#define DMAC07_DSTAT_SUS_0_7_SUS3 (0x00000008uL) +#define DMAC07_DSTAT_SUS_0_7_SUS4 (0x00000010uL) +#define DMAC07_DSTAT_SUS_0_7_SUS5 (0x00000020uL) +#define DMAC07_DSTAT_SUS_0_7_SUS6 (0x00000040uL) +#define DMAC07_DSTAT_SUS_0_7_SUS7 (0x00000080uL) + +/* ---- DMAC8 ---- */ +#define DMAC8_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC8_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC8_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC8_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC8_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC8_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC8_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC8_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC8_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC8_CHSTAT_n_EN (0x00000001uL) +#define DMAC8_CHSTAT_n_RQST (0x00000002uL) +#define DMAC8_CHSTAT_n_TACT (0x00000004uL) +#define DMAC8_CHSTAT_n_SUS (0x00000008uL) +#define DMAC8_CHSTAT_n_ER (0x00000010uL) +#define DMAC8_CHSTAT_n_END (0x00000020uL) +#define DMAC8_CHSTAT_n_TC (0x00000040uL) +#define DMAC8_CHSTAT_n_SR (0x00000080uL) +#define DMAC8_CHSTAT_n_DL (0x00000100uL) +#define DMAC8_CHSTAT_n_DW (0x00000200uL) +#define DMAC8_CHSTAT_n_DER (0x00000400uL) +#define DMAC8_CHSTAT_n_MODE (0x00000800uL) +#define DMAC8_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC8_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC8_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC8_CHCTRL_n_STG (0x00000004uL) +#define DMAC8_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC8_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC8_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC8_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC8_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC8_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC8_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC8_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC8_CHCFG_n_SEL (0x00000007uL) +#define DMAC8_CHCFG_n_REQD (0x00000008uL) +#define DMAC8_CHCFG_n_LOEN (0x00000010uL) +#define DMAC8_CHCFG_n_HIEN (0x00000020uL) +#define DMAC8_CHCFG_n_LVL (0x00000040uL) +#define DMAC8_CHCFG_n_AM (0x00000700uL) +#define DMAC8_CHCFG_n_SDS (0x0000F000uL) +#define DMAC8_CHCFG_n_DDS (0x000F0000uL) +#define DMAC8_CHCFG_n_SAD (0x00100000uL) +#define DMAC8_CHCFG_n_DAD (0x00200000uL) +#define DMAC8_CHCFG_n_TM (0x00400000uL) +#define DMAC8_CHCFG_n_DEM (0x01000000uL) +#define DMAC8_CHCFG_n_TCM (0x02000000uL) +#define DMAC8_CHCFG_n_SBE (0x08000000uL) +#define DMAC8_CHCFG_n_RSEL (0x10000000uL) +#define DMAC8_CHCFG_n_RSW (0x20000000uL) +#define DMAC8_CHCFG_n_REN (0x40000000uL) +#define DMAC8_CHCFG_n_DMS (0x80000000uL) + +#define DMAC8_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC8_CHEXT_n_SCA (0x000000F0uL) +#define DMAC8_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC8_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC8_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC9 ---- */ +#define DMAC9_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC9_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC9_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC9_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC9_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC9_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC9_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC9_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC9_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC9_CHSTAT_n_EN (0x00000001uL) +#define DMAC9_CHSTAT_n_RQST (0x00000002uL) +#define DMAC9_CHSTAT_n_TACT (0x00000004uL) +#define DMAC9_CHSTAT_n_SUS (0x00000008uL) +#define DMAC9_CHSTAT_n_ER (0x00000010uL) +#define DMAC9_CHSTAT_n_END (0x00000020uL) +#define DMAC9_CHSTAT_n_TC (0x00000040uL) +#define DMAC9_CHSTAT_n_SR (0x00000080uL) +#define DMAC9_CHSTAT_n_DL (0x00000100uL) +#define DMAC9_CHSTAT_n_DW (0x00000200uL) +#define DMAC9_CHSTAT_n_DER (0x00000400uL) +#define DMAC9_CHSTAT_n_MODE (0x00000800uL) +#define DMAC9_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC9_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC9_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC9_CHCTRL_n_STG (0x00000004uL) +#define DMAC9_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC9_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC9_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC9_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC9_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC9_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC9_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC9_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC9_CHCFG_n_SEL (0x00000007uL) +#define DMAC9_CHCFG_n_REQD (0x00000008uL) +#define DMAC9_CHCFG_n_LOEN (0x00000010uL) +#define DMAC9_CHCFG_n_HIEN (0x00000020uL) +#define DMAC9_CHCFG_n_LVL (0x00000040uL) +#define DMAC9_CHCFG_n_AM (0x00000700uL) +#define DMAC9_CHCFG_n_SDS (0x0000F000uL) +#define DMAC9_CHCFG_n_DDS (0x000F0000uL) +#define DMAC9_CHCFG_n_SAD (0x00100000uL) +#define DMAC9_CHCFG_n_DAD (0x00200000uL) +#define DMAC9_CHCFG_n_TM (0x00400000uL) +#define DMAC9_CHCFG_n_DEM (0x01000000uL) +#define DMAC9_CHCFG_n_TCM (0x02000000uL) +#define DMAC9_CHCFG_n_SBE (0x08000000uL) +#define DMAC9_CHCFG_n_RSEL (0x10000000uL) +#define DMAC9_CHCFG_n_RSW (0x20000000uL) +#define DMAC9_CHCFG_n_REN (0x40000000uL) +#define DMAC9_CHCFG_n_DMS (0x80000000uL) + +#define DMAC9_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC9_CHEXT_n_SCA (0x000000F0uL) +#define DMAC9_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC9_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC9_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC10 ---- */ +#define DMAC10_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC10_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC10_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC10_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC10_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC10_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC10_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC10_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC10_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC10_CHSTAT_n_EN (0x00000001uL) +#define DMAC10_CHSTAT_n_RQST (0x00000002uL) +#define DMAC10_CHSTAT_n_TACT (0x00000004uL) +#define DMAC10_CHSTAT_n_SUS (0x00000008uL) +#define DMAC10_CHSTAT_n_ER (0x00000010uL) +#define DMAC10_CHSTAT_n_END (0x00000020uL) +#define DMAC10_CHSTAT_n_TC (0x00000040uL) +#define DMAC10_CHSTAT_n_SR (0x00000080uL) +#define DMAC10_CHSTAT_n_DL (0x00000100uL) +#define DMAC10_CHSTAT_n_DW (0x00000200uL) +#define DMAC10_CHSTAT_n_DER (0x00000400uL) +#define DMAC10_CHSTAT_n_MODE (0x00000800uL) +#define DMAC10_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC10_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC10_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC10_CHCTRL_n_STG (0x00000004uL) +#define DMAC10_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC10_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC10_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC10_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC10_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC10_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC10_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC10_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC10_CHCFG_n_SEL (0x00000007uL) +#define DMAC10_CHCFG_n_REQD (0x00000008uL) +#define DMAC10_CHCFG_n_LOEN (0x00000010uL) +#define DMAC10_CHCFG_n_HIEN (0x00000020uL) +#define DMAC10_CHCFG_n_LVL (0x00000040uL) +#define DMAC10_CHCFG_n_AM (0x00000700uL) +#define DMAC10_CHCFG_n_SDS (0x0000F000uL) +#define DMAC10_CHCFG_n_DDS (0x000F0000uL) +#define DMAC10_CHCFG_n_SAD (0x00100000uL) +#define DMAC10_CHCFG_n_DAD (0x00200000uL) +#define DMAC10_CHCFG_n_TM (0x00400000uL) +#define DMAC10_CHCFG_n_DEM (0x01000000uL) +#define DMAC10_CHCFG_n_TCM (0x02000000uL) +#define DMAC10_CHCFG_n_SBE (0x08000000uL) +#define DMAC10_CHCFG_n_RSEL (0x10000000uL) +#define DMAC10_CHCFG_n_RSW (0x20000000uL) +#define DMAC10_CHCFG_n_REN (0x40000000uL) +#define DMAC10_CHCFG_n_DMS (0x80000000uL) + +#define DMAC10_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC10_CHEXT_n_SCA (0x000000F0uL) +#define DMAC10_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC10_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC10_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC11 ---- */ +#define DMAC11_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC11_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC11_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC11_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC11_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC11_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC11_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC11_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC11_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC11_CHSTAT_n_EN (0x00000001uL) +#define DMAC11_CHSTAT_n_RQST (0x00000002uL) +#define DMAC11_CHSTAT_n_TACT (0x00000004uL) +#define DMAC11_CHSTAT_n_SUS (0x00000008uL) +#define DMAC11_CHSTAT_n_ER (0x00000010uL) +#define DMAC11_CHSTAT_n_END (0x00000020uL) +#define DMAC11_CHSTAT_n_TC (0x00000040uL) +#define DMAC11_CHSTAT_n_SR (0x00000080uL) +#define DMAC11_CHSTAT_n_DL (0x00000100uL) +#define DMAC11_CHSTAT_n_DW (0x00000200uL) +#define DMAC11_CHSTAT_n_DER (0x00000400uL) +#define DMAC11_CHSTAT_n_MODE (0x00000800uL) +#define DMAC11_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC11_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC11_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC11_CHCTRL_n_STG (0x00000004uL) +#define DMAC11_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC11_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC11_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC11_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC11_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC11_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC11_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC11_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC11_CHCFG_n_SEL (0x00000007uL) +#define DMAC11_CHCFG_n_REQD (0x00000008uL) +#define DMAC11_CHCFG_n_LOEN (0x00000010uL) +#define DMAC11_CHCFG_n_HIEN (0x00000020uL) +#define DMAC11_CHCFG_n_LVL (0x00000040uL) +#define DMAC11_CHCFG_n_AM (0x00000700uL) +#define DMAC11_CHCFG_n_SDS (0x0000F000uL) +#define DMAC11_CHCFG_n_DDS (0x000F0000uL) +#define DMAC11_CHCFG_n_SAD (0x00100000uL) +#define DMAC11_CHCFG_n_DAD (0x00200000uL) +#define DMAC11_CHCFG_n_TM (0x00400000uL) +#define DMAC11_CHCFG_n_DEM (0x01000000uL) +#define DMAC11_CHCFG_n_TCM (0x02000000uL) +#define DMAC11_CHCFG_n_SBE (0x08000000uL) +#define DMAC11_CHCFG_n_RSEL (0x10000000uL) +#define DMAC11_CHCFG_n_RSW (0x20000000uL) +#define DMAC11_CHCFG_n_REN (0x40000000uL) +#define DMAC11_CHCFG_n_DMS (0x80000000uL) + +#define DMAC11_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC11_CHEXT_n_SCA (0x000000F0uL) +#define DMAC11_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC11_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC11_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC12 ---- */ +#define DMAC12_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC12_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC12_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC12_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC12_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC12_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC12_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC12_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC12_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC12_CHSTAT_n_EN (0x00000001uL) +#define DMAC12_CHSTAT_n_RQST (0x00000002uL) +#define DMAC12_CHSTAT_n_TACT (0x00000004uL) +#define DMAC12_CHSTAT_n_SUS (0x00000008uL) +#define DMAC12_CHSTAT_n_ER (0x00000010uL) +#define DMAC12_CHSTAT_n_END (0x00000020uL) +#define DMAC12_CHSTAT_n_TC (0x00000040uL) +#define DMAC12_CHSTAT_n_SR (0x00000080uL) +#define DMAC12_CHSTAT_n_DL (0x00000100uL) +#define DMAC12_CHSTAT_n_DW (0x00000200uL) +#define DMAC12_CHSTAT_n_DER (0x00000400uL) +#define DMAC12_CHSTAT_n_MODE (0x00000800uL) +#define DMAC12_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC12_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC12_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC12_CHCTRL_n_STG (0x00000004uL) +#define DMAC12_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC12_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC12_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC12_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC12_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC12_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC12_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC12_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC12_CHCFG_n_SEL (0x00000007uL) +#define DMAC12_CHCFG_n_REQD (0x00000008uL) +#define DMAC12_CHCFG_n_LOEN (0x00000010uL) +#define DMAC12_CHCFG_n_HIEN (0x00000020uL) +#define DMAC12_CHCFG_n_LVL (0x00000040uL) +#define DMAC12_CHCFG_n_AM (0x00000700uL) +#define DMAC12_CHCFG_n_SDS (0x0000F000uL) +#define DMAC12_CHCFG_n_DDS (0x000F0000uL) +#define DMAC12_CHCFG_n_SAD (0x00100000uL) +#define DMAC12_CHCFG_n_DAD (0x00200000uL) +#define DMAC12_CHCFG_n_TM (0x00400000uL) +#define DMAC12_CHCFG_n_DEM (0x01000000uL) +#define DMAC12_CHCFG_n_TCM (0x02000000uL) +#define DMAC12_CHCFG_n_SBE (0x08000000uL) +#define DMAC12_CHCFG_n_RSEL (0x10000000uL) +#define DMAC12_CHCFG_n_RSW (0x20000000uL) +#define DMAC12_CHCFG_n_REN (0x40000000uL) +#define DMAC12_CHCFG_n_DMS (0x80000000uL) + +#define DMAC12_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC12_CHEXT_n_SCA (0x000000F0uL) +#define DMAC12_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC12_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC12_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC13 ---- */ +#define DMAC13_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC13_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC13_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC13_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC13_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC13_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC13_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC13_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC13_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC13_CHSTAT_n_EN (0x00000001uL) +#define DMAC13_CHSTAT_n_RQST (0x00000002uL) +#define DMAC13_CHSTAT_n_TACT (0x00000004uL) +#define DMAC13_CHSTAT_n_SUS (0x00000008uL) +#define DMAC13_CHSTAT_n_ER (0x00000010uL) +#define DMAC13_CHSTAT_n_END (0x00000020uL) +#define DMAC13_CHSTAT_n_TC (0x00000040uL) +#define DMAC13_CHSTAT_n_SR (0x00000080uL) +#define DMAC13_CHSTAT_n_DL (0x00000100uL) +#define DMAC13_CHSTAT_n_DW (0x00000200uL) +#define DMAC13_CHSTAT_n_DER (0x00000400uL) +#define DMAC13_CHSTAT_n_MODE (0x00000800uL) +#define DMAC13_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC13_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC13_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC13_CHCTRL_n_STG (0x00000004uL) +#define DMAC13_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC13_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC13_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC13_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC13_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC13_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC13_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC13_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC13_CHCFG_n_SEL (0x00000007uL) +#define DMAC13_CHCFG_n_REQD (0x00000008uL) +#define DMAC13_CHCFG_n_LOEN (0x00000010uL) +#define DMAC13_CHCFG_n_HIEN (0x00000020uL) +#define DMAC13_CHCFG_n_LVL (0x00000040uL) +#define DMAC13_CHCFG_n_AM (0x00000700uL) +#define DMAC13_CHCFG_n_SDS (0x0000F000uL) +#define DMAC13_CHCFG_n_DDS (0x000F0000uL) +#define DMAC13_CHCFG_n_SAD (0x00100000uL) +#define DMAC13_CHCFG_n_DAD (0x00200000uL) +#define DMAC13_CHCFG_n_TM (0x00400000uL) +#define DMAC13_CHCFG_n_DEM (0x01000000uL) +#define DMAC13_CHCFG_n_TCM (0x02000000uL) +#define DMAC13_CHCFG_n_SBE (0x08000000uL) +#define DMAC13_CHCFG_n_RSEL (0x10000000uL) +#define DMAC13_CHCFG_n_RSW (0x20000000uL) +#define DMAC13_CHCFG_n_REN (0x40000000uL) +#define DMAC13_CHCFG_n_DMS (0x80000000uL) + +#define DMAC13_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC13_CHEXT_n_SCA (0x000000F0uL) +#define DMAC13_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC13_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC13_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC14 ---- */ +#define DMAC14_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC14_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC14_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC14_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC14_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC14_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC14_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC14_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC14_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC14_CHSTAT_n_EN (0x00000001uL) +#define DMAC14_CHSTAT_n_RQST (0x00000002uL) +#define DMAC14_CHSTAT_n_TACT (0x00000004uL) +#define DMAC14_CHSTAT_n_SUS (0x00000008uL) +#define DMAC14_CHSTAT_n_ER (0x00000010uL) +#define DMAC14_CHSTAT_n_END (0x00000020uL) +#define DMAC14_CHSTAT_n_TC (0x00000040uL) +#define DMAC14_CHSTAT_n_SR (0x00000080uL) +#define DMAC14_CHSTAT_n_DL (0x00000100uL) +#define DMAC14_CHSTAT_n_DW (0x00000200uL) +#define DMAC14_CHSTAT_n_DER (0x00000400uL) +#define DMAC14_CHSTAT_n_MODE (0x00000800uL) +#define DMAC14_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC14_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC14_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC14_CHCTRL_n_STG (0x00000004uL) +#define DMAC14_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC14_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC14_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC14_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC14_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC14_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC14_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC14_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC14_CHCFG_n_SEL (0x00000007uL) +#define DMAC14_CHCFG_n_REQD (0x00000008uL) +#define DMAC14_CHCFG_n_LOEN (0x00000010uL) +#define DMAC14_CHCFG_n_HIEN (0x00000020uL) +#define DMAC14_CHCFG_n_LVL (0x00000040uL) +#define DMAC14_CHCFG_n_AM (0x00000700uL) +#define DMAC14_CHCFG_n_SDS (0x0000F000uL) +#define DMAC14_CHCFG_n_DDS (0x000F0000uL) +#define DMAC14_CHCFG_n_SAD (0x00100000uL) +#define DMAC14_CHCFG_n_DAD (0x00200000uL) +#define DMAC14_CHCFG_n_TM (0x00400000uL) +#define DMAC14_CHCFG_n_DEM (0x01000000uL) +#define DMAC14_CHCFG_n_TCM (0x02000000uL) +#define DMAC14_CHCFG_n_SBE (0x08000000uL) +#define DMAC14_CHCFG_n_RSEL (0x10000000uL) +#define DMAC14_CHCFG_n_RSW (0x20000000uL) +#define DMAC14_CHCFG_n_REN (0x40000000uL) +#define DMAC14_CHCFG_n_DMS (0x80000000uL) + +#define DMAC14_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC14_CHEXT_n_SCA (0x000000F0uL) +#define DMAC14_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC14_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC14_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC15 ---- */ +#define DMAC15_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC15_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC15_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC15_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC15_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC15_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC15_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC15_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC15_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC15_CHSTAT_n_EN (0x00000001uL) +#define DMAC15_CHSTAT_n_RQST (0x00000002uL) +#define DMAC15_CHSTAT_n_TACT (0x00000004uL) +#define DMAC15_CHSTAT_n_SUS (0x00000008uL) +#define DMAC15_CHSTAT_n_ER (0x00000010uL) +#define DMAC15_CHSTAT_n_END (0x00000020uL) +#define DMAC15_CHSTAT_n_TC (0x00000040uL) +#define DMAC15_CHSTAT_n_SR (0x00000080uL) +#define DMAC15_CHSTAT_n_DL (0x00000100uL) +#define DMAC15_CHSTAT_n_DW (0x00000200uL) +#define DMAC15_CHSTAT_n_DER (0x00000400uL) +#define DMAC15_CHSTAT_n_MODE (0x00000800uL) +#define DMAC15_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC15_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC15_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC15_CHCTRL_n_STG (0x00000004uL) +#define DMAC15_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC15_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC15_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC15_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC15_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC15_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC15_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC15_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC15_CHCFG_n_SEL (0x00000007uL) +#define DMAC15_CHCFG_n_REQD (0x00000008uL) +#define DMAC15_CHCFG_n_LOEN (0x00000010uL) +#define DMAC15_CHCFG_n_HIEN (0x00000020uL) +#define DMAC15_CHCFG_n_LVL (0x00000040uL) +#define DMAC15_CHCFG_n_AM (0x00000700uL) +#define DMAC15_CHCFG_n_SDS (0x0000F000uL) +#define DMAC15_CHCFG_n_DDS (0x000F0000uL) +#define DMAC15_CHCFG_n_SAD (0x00100000uL) +#define DMAC15_CHCFG_n_DAD (0x00200000uL) +#define DMAC15_CHCFG_n_TM (0x00400000uL) +#define DMAC15_CHCFG_n_DEM (0x01000000uL) +#define DMAC15_CHCFG_n_TCM (0x02000000uL) +#define DMAC15_CHCFG_n_SBE (0x08000000uL) +#define DMAC15_CHCFG_n_RSEL (0x10000000uL) +#define DMAC15_CHCFG_n_RSW (0x20000000uL) +#define DMAC15_CHCFG_n_REN (0x40000000uL) +#define DMAC15_CHCFG_n_DMS (0x80000000uL) + +#define DMAC15_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC15_CHEXT_n_SCA (0x000000F0uL) +#define DMAC15_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC15_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC15_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC8-15 ---- */ +#define DMAC815_DCTRL_8_15_PR (0x00000001uL) +#define DMAC815_DCTRL_8_15_LVINT (0x00000002uL) +#define DMAC815_DCTRL_8_15_LDCA (0x0000003CuL) +#define DMAC815_DCTRL_8_15_LWCA (0x00003C00uL) + +#define DMAC815_DSTAT_EN_8_15_EN8 (0x00000001uL) +#define DMAC815_DSTAT_EN_8_15_EN9 (0x00000002uL) +#define DMAC815_DSTAT_EN_8_15_EN10 (0x00000004uL) +#define DMAC815_DSTAT_EN_8_15_EN11 (0x00000008uL) +#define DMAC815_DSTAT_EN_8_15_EN12 (0x00000010uL) +#define DMAC815_DSTAT_EN_8_15_EN13 (0x00000020uL) +#define DMAC815_DSTAT_EN_8_15_EN14 (0x00000040uL) +#define DMAC815_DSTAT_EN_8_15_EN15 (0x00000080uL) + +#define DMAC815_DSTAT_ER_8_15_ER8 (0x00000001uL) +#define DMAC815_DSTAT_ER_8_15_ER9 (0x00000002uL) +#define DMAC815_DSTAT_ER_8_15_ER10 (0x00000004uL) +#define DMAC815_DSTAT_ER_8_15_ER11 (0x00000008uL) +#define DMAC815_DSTAT_ER_8_15_ER12 (0x00000010uL) +#define DMAC815_DSTAT_ER_8_15_ER13 (0x00000020uL) +#define DMAC815_DSTAT_ER_8_15_ER14 (0x00000040uL) +#define DMAC815_DSTAT_ER_8_15_ER15 (0x00000080uL) + +#define DMAC815_DSTAT_END_8_15_END8 (0x00000001uL) +#define DMAC815_DSTAT_END_8_15_END9 (0x00000002uL) +#define DMAC815_DSTAT_END_8_15_END10 (0x00000004uL) +#define DMAC815_DSTAT_END_8_15_END11 (0x00000008uL) +#define DMAC815_DSTAT_END_8_15_END12 (0x00000010uL) +#define DMAC815_DSTAT_END_8_15_END13 (0x00000020uL) +#define DMAC815_DSTAT_END_8_15_END14 (0x00000040uL) +#define DMAC815_DSTAT_END_8_15_END15 (0x00000080uL) + +#define DMAC815_DSTAT_TC_8_15_TC8 (0x00000001uL) +#define DMAC815_DSTAT_TC_8_15_TC9 (0x00000002uL) +#define DMAC815_DSTAT_TC_8_15_TC10 (0x00000004uL) +#define DMAC815_DSTAT_TC_8_15_TC11 (0x00000008uL) +#define DMAC815_DSTAT_TC_8_15_TC12 (0x00000010uL) +#define DMAC815_DSTAT_TC_8_15_TC13 (0x00000020uL) +#define DMAC815_DSTAT_TC_8_15_TC14 (0x00000040uL) +#define DMAC815_DSTAT_TC_8_15_TC15 (0x00000080uL) + +#define DMAC815_DSTAT_SUS_8_15_SUS8 (0x00000001uL) +#define DMAC815_DSTAT_SUS_8_15_SUS9 (0x00000002uL) +#define DMAC815_DSTAT_SUS_8_15_SUS10 (0x00000004uL) +#define DMAC815_DSTAT_SUS_8_15_SUS11 (0x00000008uL) +#define DMAC815_DSTAT_SUS_8_15_SUS12 (0x00000010uL) +#define DMAC815_DSTAT_SUS_8_15_SUS13 (0x00000020uL) +#define DMAC815_DSTAT_SUS_8_15_SUS14 (0x00000040uL) +#define DMAC815_DSTAT_SUS_8_15_SUS15 (0x00000080uL) + +/* ---- DMAC0-1 ---- */ +#define DMAC01_DMARS_CH0_RID (0x00000003uL) +#define DMAC01_DMARS_CH0_MID (0x000001FCuL) +#define DMAC01_DMARS_CH1_RID (0x00030000uL) +#define DMAC01_DMARS_CH1_MID (0x01FC0000uL) + +/* ---- DMAC2-3 ---- */ +#define DMAC23_DMARS_CH2_RID (0x00000003uL) +#define DMAC23_DMARS_CH2_MID (0x000001FCuL) +#define DMAC23_DMARS_CH3_RID (0x00030000uL) +#define DMAC23_DMARS_CH3_MID (0x01FC0000uL) + +/* ---- DMAC4-5 ---- */ +#define DMAC45_DMARS_CH4_RID (0x00000003uL) +#define DMAC45_DMARS_CH4_MID (0x000001FCuL) +#define DMAC45_DMARS_CH5_RID (0x00030000uL) +#define DMAC45_DMARS_CH5_MID (0x01FC0000uL) + +/* ---- DMAC6-7 ---- */ +#define DMAC67_DMARS_CH6_RID (0x00000003uL) +#define DMAC67_DMARS_CH6_MID (0x000001FCuL) +#define DMAC67_DMARS_CH7_RID (0x00030000uL) +#define DMAC67_DMARS_CH7_MID (0x01FC0000uL) + +/* ---- DMAC8-9 ---- */ +#define DMAC89_DMARS_CH8_RID (0x00000003uL) +#define DMAC89_DMARS_CH8_MID (0x000001FCuL) +#define DMAC89_DMARS_CH9_RID (0x00030000uL) +#define DMAC89_DMARS_CH9_MID (0x01FC0000uL) + +/* ---- DMAC10-11 ---- */ +#define DMAC1011_DMARS_CH10_RID (0x00000003uL) +#define DMAC1011_DMARS_CH10_MID (0x000001FCuL) +#define DMAC1011_DMARS_CH11_RID (0x00030000uL) +#define DMAC1011_DMARS_CH11_MID (0x01FC0000uL) + +/* ---- DMAC12-13 ---- */ +#define DMAC1213_DMARS_CH12_RID (0x00000003uL) +#define DMAC1213_DMARS_CH12_MID (0x000001FCuL) +#define DMAC1213_DMARS_CH13_RID (0x00030000uL) +#define DMAC1213_DMARS_CH13_MID (0x01FC0000uL) + +/* ---- DMAC14-15 ---- */ +#define DMAC1415_DMARS_CH14_RID (0x00000003uL) +#define DMAC1415_DMARS_CH14_MID (0x000001FCuL) +#define DMAC1415_DMARS_CH15_RID (0x00030000uL) +#define DMAC1415_DMARS_CH15_MID (0x01FC0000uL) + + +/* ==== Shift values for IO registers ==== */ +/* ---- DMAC0 ---- */ +#define DMAC0_N0SA_n_SA_SHIFT (0u) + +#define DMAC0_N0DA_n_DA_SHIFT (0u) + +#define DMAC0_N0TB_n_TB_SHIFT (0u) + +#define DMAC0_N1SA_n_SA_SHIFT (0u) + +#define DMAC0_N1DA_n_DA_SHIFT (0u) + +#define DMAC0_N1TB_n_TB_SHIFT (0u) + +#define DMAC0_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC0_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC0_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC0_CHSTAT_n_EN_SHIFT (0u) +#define DMAC0_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC0_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC0_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC0_CHSTAT_n_ER_SHIFT (4u) +#define DMAC0_CHSTAT_n_END_SHIFT (5u) +#define DMAC0_CHSTAT_n_TC_SHIFT (6u) +#define DMAC0_CHSTAT_n_SR_SHIFT (7u) +#define DMAC0_CHSTAT_n_DL_SHIFT (8u) +#define DMAC0_CHSTAT_n_DW_SHIFT (9u) +#define DMAC0_CHSTAT_n_DER_SHIFT (10u) +#define DMAC0_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC0_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC0_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC0_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC0_CHCTRL_n_STG_SHIFT (2u) +#define DMAC0_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC0_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC0_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC0_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC0_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC0_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC0_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC0_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC0_CHCFG_n_SEL_SHIFT (0u) +#define DMAC0_CHCFG_n_REQD_SHIFT (3u) +#define DMAC0_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC0_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC0_CHCFG_n_LVL_SHIFT (6u) +#define DMAC0_CHCFG_n_AM_SHIFT (8u) +#define DMAC0_CHCFG_n_SDS_SHIFT (12u) +#define DMAC0_CHCFG_n_DDS_SHIFT (16u) +#define DMAC0_CHCFG_n_SAD_SHIFT (20u) +#define DMAC0_CHCFG_n_DAD_SHIFT (21u) +#define DMAC0_CHCFG_n_TM_SHIFT (22u) +#define DMAC0_CHCFG_n_DEM_SHIFT (24u) +#define DMAC0_CHCFG_n_TCM_SHIFT (25u) +#define DMAC0_CHCFG_n_SBE_SHIFT (27u) +#define DMAC0_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC0_CHCFG_n_RSW_SHIFT (29u) +#define DMAC0_CHCFG_n_REN_SHIFT (30u) +#define DMAC0_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC0_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC0_CHEXT_n_SCA_SHIFT (4u) +#define DMAC0_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC0_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC0_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC1 ---- */ +#define DMAC1_N0SA_n_SA_SHIFT (0u) + +#define DMAC1_N0DA_n_DA_SHIFT (0u) + +#define DMAC1_N0TB_n_TB_SHIFT (0u) + +#define DMAC1_N1SA_n_SA_SHIFT (0u) + +#define DMAC1_N1DA_n_DA_SHIFT (0u) + +#define DMAC1_N1TB_n_TB_SHIFT (0u) + +#define DMAC1_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC1_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC1_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC1_CHSTAT_n_EN_SHIFT (0u) +#define DMAC1_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC1_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC1_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC1_CHSTAT_n_ER_SHIFT (4u) +#define DMAC1_CHSTAT_n_END_SHIFT (5u) +#define DMAC1_CHSTAT_n_TC_SHIFT (6u) +#define DMAC1_CHSTAT_n_SR_SHIFT (7u) +#define DMAC1_CHSTAT_n_DL_SHIFT (8u) +#define DMAC1_CHSTAT_n_DW_SHIFT (9u) +#define DMAC1_CHSTAT_n_DER_SHIFT (10u) +#define DMAC1_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC1_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC1_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC1_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC1_CHCTRL_n_STG_SHIFT (2u) +#define DMAC1_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC1_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC1_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC1_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC1_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC1_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC1_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC1_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC1_CHCFG_n_SEL_SHIFT (0u) +#define DMAC1_CHCFG_n_REQD_SHIFT (3u) +#define DMAC1_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC1_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC1_CHCFG_n_LVL_SHIFT (6u) +#define DMAC1_CHCFG_n_AM_SHIFT (8u) +#define DMAC1_CHCFG_n_SDS_SHIFT (12u) +#define DMAC1_CHCFG_n_DDS_SHIFT (16u) +#define DMAC1_CHCFG_n_SAD_SHIFT (20u) +#define DMAC1_CHCFG_n_DAD_SHIFT (21u) +#define DMAC1_CHCFG_n_TM_SHIFT (22u) +#define DMAC1_CHCFG_n_DEM_SHIFT (24u) +#define DMAC1_CHCFG_n_TCM_SHIFT (25u) +#define DMAC1_CHCFG_n_SBE_SHIFT (27u) +#define DMAC1_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC1_CHCFG_n_RSW_SHIFT (29u) +#define DMAC1_CHCFG_n_REN_SHIFT (30u) +#define DMAC1_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC1_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC1_CHEXT_n_SCA_SHIFT (4u) +#define DMAC1_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC1_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC1_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC2 ---- */ +#define DMAC2_N0SA_n_SA_SHIFT (0u) + +#define DMAC2_N0DA_n_DA_SHIFT (0u) + +#define DMAC2_N0TB_n_TB_SHIFT (0u) + +#define DMAC2_N1SA_n_SA_SHIFT (0u) + +#define DMAC2_N1DA_n_DA_SHIFT (0u) + +#define DMAC2_N1TB_n_TB_SHIFT (0u) + +#define DMAC2_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC2_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC2_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC2_CHSTAT_n_EN_SHIFT (0u) +#define DMAC2_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC2_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC2_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC2_CHSTAT_n_ER_SHIFT (4u) +#define DMAC2_CHSTAT_n_END_SHIFT (5u) +#define DMAC2_CHSTAT_n_TC_SHIFT (6u) +#define DMAC2_CHSTAT_n_SR_SHIFT (7u) +#define DMAC2_CHSTAT_n_DL_SHIFT (8u) +#define DMAC2_CHSTAT_n_DW_SHIFT (9u) +#define DMAC2_CHSTAT_n_DER_SHIFT (10u) +#define DMAC2_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC2_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC2_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC2_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC2_CHCTRL_n_STG_SHIFT (2u) +#define DMAC2_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC2_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC2_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC2_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC2_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC2_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC2_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC2_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC2_CHCFG_n_SEL_SHIFT (0u) +#define DMAC2_CHCFG_n_REQD_SHIFT (3u) +#define DMAC2_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC2_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC2_CHCFG_n_LVL_SHIFT (6u) +#define DMAC2_CHCFG_n_AM_SHIFT (8u) +#define DMAC2_CHCFG_n_SDS_SHIFT (12u) +#define DMAC2_CHCFG_n_DDS_SHIFT (16u) +#define DMAC2_CHCFG_n_SAD_SHIFT (20u) +#define DMAC2_CHCFG_n_DAD_SHIFT (21u) +#define DMAC2_CHCFG_n_TM_SHIFT (22u) +#define DMAC2_CHCFG_n_DEM_SHIFT (24u) +#define DMAC2_CHCFG_n_TCM_SHIFT (25u) +#define DMAC2_CHCFG_n_SBE_SHIFT (27u) +#define DMAC2_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC2_CHCFG_n_RSW_SHIFT (29u) +#define DMAC2_CHCFG_n_REN_SHIFT (30u) +#define DMAC2_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC2_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC2_CHEXT_n_SCA_SHIFT (4u) +#define DMAC2_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC2_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC2_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC3 ---- */ +#define DMAC3_N0SA_n_SA_SHIFT (0u) + +#define DMAC3_N0DA_n_DA_SHIFT (0u) + +#define DMAC3_N0TB_n_TB_SHIFT (0u) + +#define DMAC3_N1SA_n_SA_SHIFT (0u) + +#define DMAC3_N1DA_n_DA_SHIFT (0u) + +#define DMAC3_N1TB_n_TB_SHIFT (0u) + +#define DMAC3_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC3_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC3_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC3_CHSTAT_n_EN_SHIFT (0u) +#define DMAC3_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC3_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC3_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC3_CHSTAT_n_ER_SHIFT (4u) +#define DMAC3_CHSTAT_n_END_SHIFT (5u) +#define DMAC3_CHSTAT_n_TC_SHIFT (6u) +#define DMAC3_CHSTAT_n_SR_SHIFT (7u) +#define DMAC3_CHSTAT_n_DL_SHIFT (8u) +#define DMAC3_CHSTAT_n_DW_SHIFT (9u) +#define DMAC3_CHSTAT_n_DER_SHIFT (10u) +#define DMAC3_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC3_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC3_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC3_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC3_CHCTRL_n_STG_SHIFT (2u) +#define DMAC3_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC3_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC3_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC3_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC3_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC3_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC3_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC3_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC3_CHCFG_n_SEL_SHIFT (0u) +#define DMAC3_CHCFG_n_REQD_SHIFT (3u) +#define DMAC3_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC3_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC3_CHCFG_n_LVL_SHIFT (6u) +#define DMAC3_CHCFG_n_AM_SHIFT (8u) +#define DMAC3_CHCFG_n_SDS_SHIFT (12u) +#define DMAC3_CHCFG_n_DDS_SHIFT (16u) +#define DMAC3_CHCFG_n_SAD_SHIFT (20u) +#define DMAC3_CHCFG_n_DAD_SHIFT (21u) +#define DMAC3_CHCFG_n_TM_SHIFT (22u) +#define DMAC3_CHCFG_n_DEM_SHIFT (24u) +#define DMAC3_CHCFG_n_TCM_SHIFT (25u) +#define DMAC3_CHCFG_n_SBE_SHIFT (27u) +#define DMAC3_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC3_CHCFG_n_RSW_SHIFT (29u) +#define DMAC3_CHCFG_n_REN_SHIFT (30u) +#define DMAC3_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC3_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC3_CHEXT_n_SCA_SHIFT (4u) +#define DMAC3_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC3_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC3_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC4 ---- */ +#define DMAC4_N0SA_n_SA_SHIFT (0u) + +#define DMAC4_N0DA_n_DA_SHIFT (0u) + +#define DMAC4_N0TB_n_TB_SHIFT (0u) + +#define DMAC4_N1SA_n_SA_SHIFT (0u) + +#define DMAC4_N1DA_n_DA_SHIFT (0u) + +#define DMAC4_N1TB_n_TB_SHIFT (0u) + +#define DMAC4_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC4_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC4_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC4_CHSTAT_n_EN_SHIFT (0u) +#define DMAC4_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC4_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC4_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC4_CHSTAT_n_ER_SHIFT (4u) +#define DMAC4_CHSTAT_n_END_SHIFT (5u) +#define DMAC4_CHSTAT_n_TC_SHIFT (6u) +#define DMAC4_CHSTAT_n_SR_SHIFT (7u) +#define DMAC4_CHSTAT_n_DL_SHIFT (8u) +#define DMAC4_CHSTAT_n_DW_SHIFT (9u) +#define DMAC4_CHSTAT_n_DER_SHIFT (10u) +#define DMAC4_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC4_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC4_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC4_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC4_CHCTRL_n_STG_SHIFT (2u) +#define DMAC4_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC4_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC4_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC4_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC4_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC4_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC4_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC4_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC4_CHCFG_n_SEL_SHIFT (0u) +#define DMAC4_CHCFG_n_REQD_SHIFT (3u) +#define DMAC4_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC4_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC4_CHCFG_n_LVL_SHIFT (6u) +#define DMAC4_CHCFG_n_AM_SHIFT (8u) +#define DMAC4_CHCFG_n_SDS_SHIFT (12u) +#define DMAC4_CHCFG_n_DDS_SHIFT (16u) +#define DMAC4_CHCFG_n_SAD_SHIFT (20u) +#define DMAC4_CHCFG_n_DAD_SHIFT (21u) +#define DMAC4_CHCFG_n_TM_SHIFT (22u) +#define DMAC4_CHCFG_n_DEM_SHIFT (24u) +#define DMAC4_CHCFG_n_TCM_SHIFT (25u) +#define DMAC4_CHCFG_n_SBE_SHIFT (27u) +#define DMAC4_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC4_CHCFG_n_RSW_SHIFT (29u) +#define DMAC4_CHCFG_n_REN_SHIFT (30u) +#define DMAC4_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC4_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC4_CHEXT_n_SCA_SHIFT (4u) +#define DMAC4_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC4_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC4_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC5 ---- */ +#define DMAC5_N0SA_n_SA_SHIFT (0u) + +#define DMAC5_N0DA_n_DA_SHIFT (0u) + +#define DMAC5_N0TB_n_TB_SHIFT (0u) + +#define DMAC5_N1SA_n_SA_SHIFT (0u) + +#define DMAC5_N1DA_n_DA_SHIFT (0u) + +#define DMAC5_N1TB_n_TB_SHIFT (0u) + +#define DMAC5_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC5_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC5_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC5_CHSTAT_n_EN_SHIFT (0u) +#define DMAC5_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC5_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC5_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC5_CHSTAT_n_ER_SHIFT (4u) +#define DMAC5_CHSTAT_n_END_SHIFT (5u) +#define DMAC5_CHSTAT_n_TC_SHIFT (6u) +#define DMAC5_CHSTAT_n_SR_SHIFT (7u) +#define DMAC5_CHSTAT_n_DL_SHIFT (8u) +#define DMAC5_CHSTAT_n_DW_SHIFT (9u) +#define DMAC5_CHSTAT_n_DER_SHIFT (10u) +#define DMAC5_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC5_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC5_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC5_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC5_CHCTRL_n_STG_SHIFT (2u) +#define DMAC5_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC5_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC5_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC5_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC5_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC5_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC5_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC5_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC5_CHCFG_n_SEL_SHIFT (0u) +#define DMAC5_CHCFG_n_REQD_SHIFT (3u) +#define DMAC5_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC5_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC5_CHCFG_n_LVL_SHIFT (6u) +#define DMAC5_CHCFG_n_AM_SHIFT (8u) +#define DMAC5_CHCFG_n_SDS_SHIFT (12u) +#define DMAC5_CHCFG_n_DDS_SHIFT (16u) +#define DMAC5_CHCFG_n_SAD_SHIFT (20u) +#define DMAC5_CHCFG_n_DAD_SHIFT (21u) +#define DMAC5_CHCFG_n_TM_SHIFT (22u) +#define DMAC5_CHCFG_n_DEM_SHIFT (24u) +#define DMAC5_CHCFG_n_TCM_SHIFT (25u) +#define DMAC5_CHCFG_n_SBE_SHIFT (27u) +#define DMAC5_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC5_CHCFG_n_RSW_SHIFT (29u) +#define DMAC5_CHCFG_n_REN_SHIFT (30u) +#define DMAC5_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC5_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC5_CHEXT_n_SCA_SHIFT (4u) +#define DMAC5_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC5_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC5_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC6 ---- */ +#define DMAC6_N0SA_n_SA_SHIFT (0u) + +#define DMAC6_N0DA_n_DA_SHIFT (0u) + +#define DMAC6_N0TB_n_TB_SHIFT (0u) + +#define DMAC6_N1SA_n_SA_SHIFT (0u) + +#define DMAC6_N1DA_n_DA_SHIFT (0u) + +#define DMAC6_N1TB_n_TB_SHIFT (0u) + +#define DMAC6_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC6_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC6_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC6_CHSTAT_n_EN_SHIFT (0u) +#define DMAC6_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC6_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC6_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC6_CHSTAT_n_ER_SHIFT (4u) +#define DMAC6_CHSTAT_n_END_SHIFT (5u) +#define DMAC6_CHSTAT_n_TC_SHIFT (6u) +#define DMAC6_CHSTAT_n_SR_SHIFT (7u) +#define DMAC6_CHSTAT_n_DL_SHIFT (8u) +#define DMAC6_CHSTAT_n_DW_SHIFT (9u) +#define DMAC6_CHSTAT_n_DER_SHIFT (10u) +#define DMAC6_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC6_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC6_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC6_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC6_CHCTRL_n_STG_SHIFT (2u) +#define DMAC6_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC6_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC6_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC6_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC6_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC6_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC6_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC6_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC6_CHCFG_n_SEL_SHIFT (0u) +#define DMAC6_CHCFG_n_REQD_SHIFT (3u) +#define DMAC6_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC6_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC6_CHCFG_n_LVL_SHIFT (6u) +#define DMAC6_CHCFG_n_AM_SHIFT (8u) +#define DMAC6_CHCFG_n_SDS_SHIFT (12u) +#define DMAC6_CHCFG_n_DDS_SHIFT (16u) +#define DMAC6_CHCFG_n_SAD_SHIFT (20u) +#define DMAC6_CHCFG_n_DAD_SHIFT (21u) +#define DMAC6_CHCFG_n_TM_SHIFT (22u) +#define DMAC6_CHCFG_n_DEM_SHIFT (24u) +#define DMAC6_CHCFG_n_TCM_SHIFT (25u) +#define DMAC6_CHCFG_n_SBE_SHIFT (27u) +#define DMAC6_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC6_CHCFG_n_RSW_SHIFT (29u) +#define DMAC6_CHCFG_n_REN_SHIFT (30u) +#define DMAC6_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC6_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC6_CHEXT_n_SCA_SHIFT (4u) +#define DMAC6_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC6_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC6_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC7 ---- */ +#define DMAC7_N0SA_n_SA_SHIFT (0u) + +#define DMAC7_N0DA_n_DA_SHIFT (0u) + +#define DMAC7_N0TB_n_TB_SHIFT (0u) + +#define DMAC7_N1SA_n_SA_SHIFT (0u) + +#define DMAC7_N1DA_n_DA_SHIFT (0u) + +#define DMAC7_N1TB_n_TB_SHIFT (0u) + +#define DMAC7_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC7_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC7_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC7_CHSTAT_n_EN_SHIFT (0u) +#define DMAC7_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC7_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC7_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC7_CHSTAT_n_ER_SHIFT (4u) +#define DMAC7_CHSTAT_n_END_SHIFT (5u) +#define DMAC7_CHSTAT_n_TC_SHIFT (6u) +#define DMAC7_CHSTAT_n_SR_SHIFT (7u) +#define DMAC7_CHSTAT_n_DL_SHIFT (8u) +#define DMAC7_CHSTAT_n_DW_SHIFT (9u) +#define DMAC7_CHSTAT_n_DER_SHIFT (10u) +#define DMAC7_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC7_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC7_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC7_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC7_CHCTRL_n_STG_SHIFT (2u) +#define DMAC7_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC7_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC7_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC7_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC7_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC7_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC7_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC7_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC7_CHCFG_n_SEL_SHIFT (0u) +#define DMAC7_CHCFG_n_REQD_SHIFT (3u) +#define DMAC7_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC7_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC7_CHCFG_n_LVL_SHIFT (6u) +#define DMAC7_CHCFG_n_AM_SHIFT (8u) +#define DMAC7_CHCFG_n_SDS_SHIFT (12u) +#define DMAC7_CHCFG_n_DDS_SHIFT (16u) +#define DMAC7_CHCFG_n_SAD_SHIFT (20u) +#define DMAC7_CHCFG_n_DAD_SHIFT (21u) +#define DMAC7_CHCFG_n_TM_SHIFT (22u) +#define DMAC7_CHCFG_n_DEM_SHIFT (24u) +#define DMAC7_CHCFG_n_TCM_SHIFT (25u) +#define DMAC7_CHCFG_n_SBE_SHIFT (27u) +#define DMAC7_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC7_CHCFG_n_RSW_SHIFT (29u) +#define DMAC7_CHCFG_n_REN_SHIFT (30u) +#define DMAC7_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC7_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC7_CHEXT_n_SCA_SHIFT (4u) +#define DMAC7_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC7_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC7_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC0-7 ---- */ +#define DMAC07_DCTRL_0_7_PR_SHIFT (0u) +#define DMAC07_DCTRL_0_7_LVINT_SHIFT (1u) +#define DMAC07_DCTRL_0_7_LDCA_SHIFT (2u) +#define DMAC07_DCTRL_0_7_LWCA_SHIFT (6u) + +#define DMAC07_DSTAT_EN_0_7_EN0_SHIFT (0u) +#define DMAC07_DSTAT_EN_0_7_EN1_SHIFT (1u) +#define DMAC07_DSTAT_EN_0_7_EN2_SHIFT (2u) +#define DMAC07_DSTAT_EN_0_7_EN3_SHIFT (3u) +#define DMAC07_DSTAT_EN_0_7_EN4_SHIFT (4u) +#define DMAC07_DSTAT_EN_0_7_EN5_SHIFT (5u) +#define DMAC07_DSTAT_EN_0_7_EN6_SHIFT (6u) +#define DMAC07_DSTAT_EN_0_7_EN7_SHIFT (7u) + +#define DMAC07_DSTAT_ER_0_7_ER0_SHIFT (0u) +#define DMAC07_DSTAT_ER_0_7_ER1_SHIFT (1u) +#define DMAC07_DSTAT_ER_0_7_ER2_SHIFT (2u) +#define DMAC07_DSTAT_ER_0_7_ER3_SHIFT (3u) +#define DMAC07_DSTAT_ER_0_7_ER4_SHIFT (4u) +#define DMAC07_DSTAT_ER_0_7_ER5_SHIFT (5u) +#define DMAC07_DSTAT_ER_0_7_ER6_SHIFT (6u) +#define DMAC07_DSTAT_ER_0_7_ER7_SHIFT (7u) + +#define DMAC07_DSTAT_END_0_7_END0_SHIFT (0u) +#define DMAC07_DSTAT_END_0_7_END1_SHIFT (1u) +#define DMAC07_DSTAT_END_0_7_END2_SHIFT (2u) +#define DMAC07_DSTAT_END_0_7_END3_SHIFT (3u) +#define DMAC07_DSTAT_END_0_7_END4_SHIFT (4u) +#define DMAC07_DSTAT_END_0_7_END5_SHIFT (5u) +#define DMAC07_DSTAT_END_0_7_END6_SHIFT (6u) +#define DMAC07_DSTAT_END_0_7_END7_SHIFT (7u) + +#define DMAC07_DSTAT_TC_0_7_TC0_SHIFT (0u) +#define DMAC07_DSTAT_TC_0_7_TC1_SHIFT (1u) +#define DMAC07_DSTAT_TC_0_7_TC2_SHIFT (2u) +#define DMAC07_DSTAT_TC_0_7_TC3_SHIFT (3u) +#define DMAC07_DSTAT_TC_0_7_TC4_SHIFT (4u) +#define DMAC07_DSTAT_TC_0_7_TC5_SHIFT (5u) +#define DMAC07_DSTAT_TC_0_7_TC6_SHIFT (6u) +#define DMAC07_DSTAT_TC_0_7_TC7_SHIFT (7u) + +#define DMAC07_DSTAT_SUS_0_7_SUS0_SHIFT (0u) +#define DMAC07_DSTAT_SUS_0_7_SUS1_SHIFT (1u) +#define DMAC07_DSTAT_SUS_0_7_SUS2_SHIFT (2u) +#define DMAC07_DSTAT_SUS_0_7_SUS3_SHIFT (3u) +#define DMAC07_DSTAT_SUS_0_7_SUS4_SHIFT (4u) +#define DMAC07_DSTAT_SUS_0_7_SUS5_SHIFT (5u) +#define DMAC07_DSTAT_SUS_0_7_SUS6_SHIFT (6u) +#define DMAC07_DSTAT_SUS_0_7_SUS7_SHIFT (7u) + +/* ---- DMAC8 ---- */ +#define DMAC8_N0SA_n_SA_SHIFT (0u) + +#define DMAC8_N0DA_n_DA_SHIFT (0u) + +#define DMAC8_N0TB_n_TB_SHIFT (0u) + +#define DMAC8_N1SA_n_SA_SHIFT (0u) + +#define DMAC8_N1DA_n_DA_SHIFT (0u) + +#define DMAC8_N1TB_n_TB_SHIFT (0u) + +#define DMAC8_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC8_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC8_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC8_CHSTAT_n_EN_SHIFT (0u) +#define DMAC8_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC8_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC8_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC8_CHSTAT_n_ER_SHIFT (4u) +#define DMAC8_CHSTAT_n_END_SHIFT (5u) +#define DMAC8_CHSTAT_n_TC_SHIFT (6u) +#define DMAC8_CHSTAT_n_SR_SHIFT (7u) +#define DMAC8_CHSTAT_n_DL_SHIFT (8u) +#define DMAC8_CHSTAT_n_DW_SHIFT (9u) +#define DMAC8_CHSTAT_n_DER_SHIFT (10u) +#define DMAC8_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC8_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC8_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC8_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC8_CHCTRL_n_STG_SHIFT (2u) +#define DMAC8_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC8_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC8_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC8_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC8_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC8_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC8_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC8_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC8_CHCFG_n_SEL_SHIFT (0u) +#define DMAC8_CHCFG_n_REQD_SHIFT (3u) +#define DMAC8_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC8_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC8_CHCFG_n_LVL_SHIFT (6u) +#define DMAC8_CHCFG_n_AM_SHIFT (8u) +#define DMAC8_CHCFG_n_SDS_SHIFT (12u) +#define DMAC8_CHCFG_n_DDS_SHIFT (16u) +#define DMAC8_CHCFG_n_SAD_SHIFT (20u) +#define DMAC8_CHCFG_n_DAD_SHIFT (21u) +#define DMAC8_CHCFG_n_TM_SHIFT (22u) +#define DMAC8_CHCFG_n_DEM_SHIFT (24u) +#define DMAC8_CHCFG_n_TCM_SHIFT (25u) +#define DMAC8_CHCFG_n_SBE_SHIFT (27u) +#define DMAC8_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC8_CHCFG_n_RSW_SHIFT (29u) +#define DMAC8_CHCFG_n_REN_SHIFT (30u) +#define DMAC8_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC8_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC8_CHEXT_n_SCA_SHIFT (4u) +#define DMAC8_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC8_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC8_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC9 ---- */ +#define DMAC9_N0SA_n_SA_SHIFT (0u) + +#define DMAC9_N0DA_n_DA_SHIFT (0u) + +#define DMAC9_N0TB_n_TB_SHIFT (0u) + +#define DMAC9_N1SA_n_SA_SHIFT (0u) + +#define DMAC9_N1DA_n_DA_SHIFT (0u) + +#define DMAC9_N1TB_n_TB_SHIFT (0u) + +#define DMAC9_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC9_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC9_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC9_CHSTAT_n_EN_SHIFT (0u) +#define DMAC9_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC9_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC9_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC9_CHSTAT_n_ER_SHIFT (4u) +#define DMAC9_CHSTAT_n_END_SHIFT (5u) +#define DMAC9_CHSTAT_n_TC_SHIFT (6u) +#define DMAC9_CHSTAT_n_SR_SHIFT (7u) +#define DMAC9_CHSTAT_n_DL_SHIFT (8u) +#define DMAC9_CHSTAT_n_DW_SHIFT (9u) +#define DMAC9_CHSTAT_n_DER_SHIFT (10u) +#define DMAC9_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC9_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC9_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC9_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC9_CHCTRL_n_STG_SHIFT (2u) +#define DMAC9_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC9_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC9_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC9_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC9_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC9_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC9_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC9_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC9_CHCFG_n_SEL_SHIFT (0u) +#define DMAC9_CHCFG_n_REQD_SHIFT (3u) +#define DMAC9_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC9_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC9_CHCFG_n_LVL_SHIFT (6u) +#define DMAC9_CHCFG_n_AM_SHIFT (8u) +#define DMAC9_CHCFG_n_SDS_SHIFT (12u) +#define DMAC9_CHCFG_n_DDS_SHIFT (16u) +#define DMAC9_CHCFG_n_SAD_SHIFT (20u) +#define DMAC9_CHCFG_n_DAD_SHIFT (21u) +#define DMAC9_CHCFG_n_TM_SHIFT (22u) +#define DMAC9_CHCFG_n_DEM_SHIFT (24u) +#define DMAC9_CHCFG_n_TCM_SHIFT (25u) +#define DMAC9_CHCFG_n_SBE_SHIFT (27u) +#define DMAC9_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC9_CHCFG_n_RSW_SHIFT (29u) +#define DMAC9_CHCFG_n_REN_SHIFT (30u) +#define DMAC9_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC9_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC9_CHEXT_n_SCA_SHIFT (4u) +#define DMAC9_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC9_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC9_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC10 ---- */ +#define DMAC10_N0SA_n_SA_SHIFT (0u) + +#define DMAC10_N0DA_n_DA_SHIFT (0u) + +#define DMAC10_N0TB_n_TB_SHIFT (0u) + +#define DMAC10_N1SA_n_SA_SHIFT (0u) + +#define DMAC10_N1DA_n_DA_SHIFT (0u) + +#define DMAC10_N1TB_n_TB_SHIFT (0u) + +#define DMAC10_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC10_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC10_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC10_CHSTAT_n_EN_SHIFT (0u) +#define DMAC10_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC10_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC10_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC10_CHSTAT_n_ER_SHIFT (4u) +#define DMAC10_CHSTAT_n_END_SHIFT (5u) +#define DMAC10_CHSTAT_n_TC_SHIFT (6u) +#define DMAC10_CHSTAT_n_SR_SHIFT (7u) +#define DMAC10_CHSTAT_n_DL_SHIFT (8u) +#define DMAC10_CHSTAT_n_DW_SHIFT (9u) +#define DMAC10_CHSTAT_n_DER_SHIFT (10u) +#define DMAC10_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC10_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC10_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC10_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC10_CHCTRL_n_STG_SHIFT (2u) +#define DMAC10_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC10_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC10_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC10_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC10_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC10_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC10_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC10_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC10_CHCFG_n_SEL_SHIFT (0u) +#define DMAC10_CHCFG_n_REQD_SHIFT (3u) +#define DMAC10_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC10_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC10_CHCFG_n_LVL_SHIFT (6u) +#define DMAC10_CHCFG_n_AM_SHIFT (8u) +#define DMAC10_CHCFG_n_SDS_SHIFT (12u) +#define DMAC10_CHCFG_n_DDS_SHIFT (16u) +#define DMAC10_CHCFG_n_SAD_SHIFT (20u) +#define DMAC10_CHCFG_n_DAD_SHIFT (21u) +#define DMAC10_CHCFG_n_TM_SHIFT (22u) +#define DMAC10_CHCFG_n_DEM_SHIFT (24u) +#define DMAC10_CHCFG_n_TCM_SHIFT (25u) +#define DMAC10_CHCFG_n_SBE_SHIFT (27u) +#define DMAC10_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC10_CHCFG_n_RSW_SHIFT (29u) +#define DMAC10_CHCFG_n_REN_SHIFT (30u) +#define DMAC10_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC10_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC10_CHEXT_n_SCA_SHIFT (4u) +#define DMAC10_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC10_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC10_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC11 ---- */ +#define DMAC11_N0SA_n_SA_SHIFT (0u) + +#define DMAC11_N0DA_n_DA_SHIFT (0u) + +#define DMAC11_N0TB_n_TB_SHIFT (0u) + +#define DMAC11_N1SA_n_SA_SHIFT (0u) + +#define DMAC11_N1DA_n_DA_SHIFT (0u) + +#define DMAC11_N1TB_n_TB_SHIFT (0u) + +#define DMAC11_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC11_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC11_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC11_CHSTAT_n_EN_SHIFT (0u) +#define DMAC11_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC11_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC11_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC11_CHSTAT_n_ER_SHIFT (4u) +#define DMAC11_CHSTAT_n_END_SHIFT (5u) +#define DMAC11_CHSTAT_n_TC_SHIFT (6u) +#define DMAC11_CHSTAT_n_SR_SHIFT (7u) +#define DMAC11_CHSTAT_n_DL_SHIFT (8u) +#define DMAC11_CHSTAT_n_DW_SHIFT (9u) +#define DMAC11_CHSTAT_n_DER_SHIFT (10u) +#define DMAC11_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC11_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC11_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC11_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC11_CHCTRL_n_STG_SHIFT (2u) +#define DMAC11_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC11_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC11_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC11_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC11_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC11_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC11_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC11_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC11_CHCFG_n_SEL_SHIFT (0u) +#define DMAC11_CHCFG_n_REQD_SHIFT (3u) +#define DMAC11_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC11_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC11_CHCFG_n_LVL_SHIFT (6u) +#define DMAC11_CHCFG_n_AM_SHIFT (8u) +#define DMAC11_CHCFG_n_SDS_SHIFT (12u) +#define DMAC11_CHCFG_n_DDS_SHIFT (16u) +#define DMAC11_CHCFG_n_SAD_SHIFT (20u) +#define DMAC11_CHCFG_n_DAD_SHIFT (21u) +#define DMAC11_CHCFG_n_TM_SHIFT (22u) +#define DMAC11_CHCFG_n_DEM_SHIFT (24u) +#define DMAC11_CHCFG_n_TCM_SHIFT (25u) +#define DMAC11_CHCFG_n_SBE_SHIFT (27u) +#define DMAC11_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC11_CHCFG_n_RSW_SHIFT (29u) +#define DMAC11_CHCFG_n_REN_SHIFT (30u) +#define DMAC11_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC11_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC11_CHEXT_n_SCA_SHIFT (4u) +#define DMAC11_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC11_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC11_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC12 ---- */ +#define DMAC12_N0SA_n_SA_SHIFT (0u) + +#define DMAC12_N0DA_n_DA_SHIFT (0u) + +#define DMAC12_N0TB_n_TB_SHIFT (0u) + +#define DMAC12_N1SA_n_SA_SHIFT (0u) + +#define DMAC12_N1DA_n_DA_SHIFT (0u) + +#define DMAC12_N1TB_n_TB_SHIFT (0u) + +#define DMAC12_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC12_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC12_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC12_CHSTAT_n_EN_SHIFT (0u) +#define DMAC12_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC12_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC12_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC12_CHSTAT_n_ER_SHIFT (4u) +#define DMAC12_CHSTAT_n_END_SHIFT (5u) +#define DMAC12_CHSTAT_n_TC_SHIFT (6u) +#define DMAC12_CHSTAT_n_SR_SHIFT (7u) +#define DMAC12_CHSTAT_n_DL_SHIFT (8u) +#define DMAC12_CHSTAT_n_DW_SHIFT (9u) +#define DMAC12_CHSTAT_n_DER_SHIFT (10u) +#define DMAC12_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC12_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC12_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC12_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC12_CHCTRL_n_STG_SHIFT (2u) +#define DMAC12_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC12_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC12_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC12_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC12_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC12_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC12_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC12_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC12_CHCFG_n_SEL_SHIFT (0u) +#define DMAC12_CHCFG_n_REQD_SHIFT (3u) +#define DMAC12_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC12_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC12_CHCFG_n_LVL_SHIFT (6u) +#define DMAC12_CHCFG_n_AM_SHIFT (8u) +#define DMAC12_CHCFG_n_SDS_SHIFT (12u) +#define DMAC12_CHCFG_n_DDS_SHIFT (16u) +#define DMAC12_CHCFG_n_SAD_SHIFT (20u) +#define DMAC12_CHCFG_n_DAD_SHIFT (21u) +#define DMAC12_CHCFG_n_TM_SHIFT (22u) +#define DMAC12_CHCFG_n_DEM_SHIFT (24u) +#define DMAC12_CHCFG_n_TCM_SHIFT (25u) +#define DMAC12_CHCFG_n_SBE_SHIFT (27u) +#define DMAC12_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC12_CHCFG_n_RSW_SHIFT (29u) +#define DMAC12_CHCFG_n_REN_SHIFT (30u) +#define DMAC12_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC12_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC12_CHEXT_n_SCA_SHIFT (4u) +#define DMAC12_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC12_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC12_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC13 ---- */ +#define DMAC13_N0SA_n_SA_SHIFT (0u) + +#define DMAC13_N0DA_n_DA_SHIFT (0u) + +#define DMAC13_N0TB_n_TB_SHIFT (0u) + +#define DMAC13_N1SA_n_SA_SHIFT (0u) + +#define DMAC13_N1DA_n_DA_SHIFT (0u) + +#define DMAC13_N1TB_n_TB_SHIFT (0u) + +#define DMAC13_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC13_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC13_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC13_CHSTAT_n_EN_SHIFT (0u) +#define DMAC13_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC13_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC13_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC13_CHSTAT_n_ER_SHIFT (4u) +#define DMAC13_CHSTAT_n_END_SHIFT (5u) +#define DMAC13_CHSTAT_n_TC_SHIFT (6u) +#define DMAC13_CHSTAT_n_SR_SHIFT (7u) +#define DMAC13_CHSTAT_n_DL_SHIFT (8u) +#define DMAC13_CHSTAT_n_DW_SHIFT (9u) +#define DMAC13_CHSTAT_n_DER_SHIFT (10u) +#define DMAC13_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC13_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC13_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC13_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC13_CHCTRL_n_STG_SHIFT (2u) +#define DMAC13_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC13_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC13_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC13_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC13_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC13_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC13_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC13_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC13_CHCFG_n_SEL_SHIFT (0u) +#define DMAC13_CHCFG_n_REQD_SHIFT (3u) +#define DMAC13_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC13_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC13_CHCFG_n_LVL_SHIFT (6u) +#define DMAC13_CHCFG_n_AM_SHIFT (8u) +#define DMAC13_CHCFG_n_SDS_SHIFT (12u) +#define DMAC13_CHCFG_n_DDS_SHIFT (16u) +#define DMAC13_CHCFG_n_SAD_SHIFT (20u) +#define DMAC13_CHCFG_n_DAD_SHIFT (21u) +#define DMAC13_CHCFG_n_TM_SHIFT (22u) +#define DMAC13_CHCFG_n_DEM_SHIFT (24u) +#define DMAC13_CHCFG_n_TCM_SHIFT (25u) +#define DMAC13_CHCFG_n_SBE_SHIFT (27u) +#define DMAC13_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC13_CHCFG_n_RSW_SHIFT (29u) +#define DMAC13_CHCFG_n_REN_SHIFT (30u) +#define DMAC13_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC13_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC13_CHEXT_n_SCA_SHIFT (4u) +#define DMAC13_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC13_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC13_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC14 ---- */ +#define DMAC14_N0SA_n_SA_SHIFT (0u) + +#define DMAC14_N0DA_n_DA_SHIFT (0u) + +#define DMAC14_N0TB_n_TB_SHIFT (0u) + +#define DMAC14_N1SA_n_SA_SHIFT (0u) + +#define DMAC14_N1DA_n_DA_SHIFT (0u) + +#define DMAC14_N1TB_n_TB_SHIFT (0u) + +#define DMAC14_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC14_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC14_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC14_CHSTAT_n_EN_SHIFT (0u) +#define DMAC14_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC14_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC14_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC14_CHSTAT_n_ER_SHIFT (4u) +#define DMAC14_CHSTAT_n_END_SHIFT (5u) +#define DMAC14_CHSTAT_n_TC_SHIFT (6u) +#define DMAC14_CHSTAT_n_SR_SHIFT (7u) +#define DMAC14_CHSTAT_n_DL_SHIFT (8u) +#define DMAC14_CHSTAT_n_DW_SHIFT (9u) +#define DMAC14_CHSTAT_n_DER_SHIFT (10u) +#define DMAC14_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC14_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC14_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC14_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC14_CHCTRL_n_STG_SHIFT (2u) +#define DMAC14_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC14_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC14_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC14_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC14_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC14_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC14_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC14_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC14_CHCFG_n_SEL_SHIFT (0u) +#define DMAC14_CHCFG_n_REQD_SHIFT (3u) +#define DMAC14_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC14_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC14_CHCFG_n_LVL_SHIFT (6u) +#define DMAC14_CHCFG_n_AM_SHIFT (8u) +#define DMAC14_CHCFG_n_SDS_SHIFT (12u) +#define DMAC14_CHCFG_n_DDS_SHIFT (16u) +#define DMAC14_CHCFG_n_SAD_SHIFT (20u) +#define DMAC14_CHCFG_n_DAD_SHIFT (21u) +#define DMAC14_CHCFG_n_TM_SHIFT (22u) +#define DMAC14_CHCFG_n_DEM_SHIFT (24u) +#define DMAC14_CHCFG_n_TCM_SHIFT (25u) +#define DMAC14_CHCFG_n_SBE_SHIFT (27u) +#define DMAC14_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC14_CHCFG_n_RSW_SHIFT (29u) +#define DMAC14_CHCFG_n_REN_SHIFT (30u) +#define DMAC14_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC14_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC14_CHEXT_n_SCA_SHIFT (4u) +#define DMAC14_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC14_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC14_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC15 ---- */ +#define DMAC15_N0SA_n_SA_SHIFT (0u) + +#define DMAC15_N0DA_n_DA_SHIFT (0u) + +#define DMAC15_N0TB_n_TB_SHIFT (0u) + +#define DMAC15_N1SA_n_SA_SHIFT (0u) + +#define DMAC15_N1DA_n_DA_SHIFT (0u) + +#define DMAC15_N1TB_n_TB_SHIFT (0u) + +#define DMAC15_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC15_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC15_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC15_CHSTAT_n_EN_SHIFT (0u) +#define DMAC15_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC15_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC15_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC15_CHSTAT_n_ER_SHIFT (4u) +#define DMAC15_CHSTAT_n_END_SHIFT (5u) +#define DMAC15_CHSTAT_n_TC_SHIFT (6u) +#define DMAC15_CHSTAT_n_SR_SHIFT (7u) +#define DMAC15_CHSTAT_n_DL_SHIFT (8u) +#define DMAC15_CHSTAT_n_DW_SHIFT (9u) +#define DMAC15_CHSTAT_n_DER_SHIFT (10u) +#define DMAC15_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC15_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC15_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC15_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC15_CHCTRL_n_STG_SHIFT (2u) +#define DMAC15_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC15_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC15_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC15_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC15_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC15_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC15_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC15_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC15_CHCFG_n_SEL_SHIFT (0u) +#define DMAC15_CHCFG_n_REQD_SHIFT (3u) +#define DMAC15_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC15_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC15_CHCFG_n_LVL_SHIFT (6u) +#define DMAC15_CHCFG_n_AM_SHIFT (8u) +#define DMAC15_CHCFG_n_SDS_SHIFT (12u) +#define DMAC15_CHCFG_n_DDS_SHIFT (16u) +#define DMAC15_CHCFG_n_SAD_SHIFT (20u) +#define DMAC15_CHCFG_n_DAD_SHIFT (21u) +#define DMAC15_CHCFG_n_TM_SHIFT (22u) +#define DMAC15_CHCFG_n_DEM_SHIFT (24u) +#define DMAC15_CHCFG_n_TCM_SHIFT (25u) +#define DMAC15_CHCFG_n_SBE_SHIFT (27u) +#define DMAC15_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC15_CHCFG_n_RSW_SHIFT (29u) +#define DMAC15_CHCFG_n_REN_SHIFT (30u) +#define DMAC15_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC15_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC15_CHEXT_n_SCA_SHIFT (4u) +#define DMAC15_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC15_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC15_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC8-15 ---- */ +#define DMAC815_DCTRL_8_15_PR_SHIFT (0u) +#define DMAC815_DCTRL_8_15_LVINT_SHIFT (1u) +#define DMAC815_DCTRL_8_15_LDCA_SHIFT (2u) +#define DMAC815_DCTRL_8_15_LWCA_SHIFT (10u) + +#define DMAC815_DSTAT_EN_8_15_EN8_SHIFT (0u) +#define DMAC815_DSTAT_EN_8_15_EN9_SHIFT (1u) +#define DMAC815_DSTAT_EN_8_15_EN10_SHIFT (2u) +#define DMAC815_DSTAT_EN_8_15_EN11_SHIFT (3u) +#define DMAC815_DSTAT_EN_8_15_EN12_SHIFT (4u) +#define DMAC815_DSTAT_EN_8_15_EN13_SHIFT (5u) +#define DMAC815_DSTAT_EN_8_15_EN14_SHIFT (6u) +#define DMAC815_DSTAT_EN_8_15_EN15_SHIFT (7u) + +#define DMAC815_DSTAT_ER_8_15_ER8_SHIFT (0u) +#define DMAC815_DSTAT_ER_8_15_ER9_SHIFT (1u) +#define DMAC815_DSTAT_ER_8_15_ER10_SHIFT (2u) +#define DMAC815_DSTAT_ER_8_15_ER11_SHIFT (3u) +#define DMAC815_DSTAT_ER_8_15_ER12_SHIFT (4u) +#define DMAC815_DSTAT_ER_8_15_ER13_SHIFT (5u) +#define DMAC815_DSTAT_ER_8_15_ER14_SHIFT (6u) +#define DMAC815_DSTAT_ER_8_15_ER15_SHIFT (7u) + +#define DMAC815_DSTAT_END_8_15_END8_SHIFT (0u) +#define DMAC815_DSTAT_END_8_15_END9_SHIFT (1u) +#define DMAC815_DSTAT_END_8_15_END10_SHIFT (2u) +#define DMAC815_DSTAT_END_8_15_END11_SHIFT (3u) +#define DMAC815_DSTAT_END_8_15_END12_SHIFT (4u) +#define DMAC815_DSTAT_END_8_15_END13_SHIFT (5u) +#define DMAC815_DSTAT_END_8_15_END14_SHIFT (6u) +#define DMAC815_DSTAT_END_8_15_END15_SHIFT (7u) + +#define DMAC815_DSTAT_TC_8_15_TC8_SHIFT (0u) +#define DMAC815_DSTAT_TC_8_15_TC9_SHIFT (1u) +#define DMAC815_DSTAT_TC_8_15_TC10_SHIFT (2u) +#define DMAC815_DSTAT_TC_8_15_TC11_SHIFT (3u) +#define DMAC815_DSTAT_TC_8_15_TC12_SHIFT (4u) +#define DMAC815_DSTAT_TC_8_15_TC13_SHIFT (5u) +#define DMAC815_DSTAT_TC_8_15_TC14_SHIFT (6u) +#define DMAC815_DSTAT_TC_8_15_TC15_SHIFT (7u) + +#define DMAC815_DSTAT_SUS_8_15_SUS8_SHIFT (0u) +#define DMAC815_DSTAT_SUS_8_15_SUS9_SHIFT (1u) +#define DMAC815_DSTAT_SUS_8_15_SUS10_SHIFT (2u) +#define DMAC815_DSTAT_SUS_8_15_SUS11_SHIFT (3u) +#define DMAC815_DSTAT_SUS_8_15_SUS12_SHIFT (4u) +#define DMAC815_DSTAT_SUS_8_15_SUS13_SHIFT (5u) +#define DMAC815_DSTAT_SUS_8_15_SUS14_SHIFT (6u) +#define DMAC815_DSTAT_SUS_8_15_SUS15_SHIFT (7u) + +/* ---- DMAC0-1 ---- */ +#define DMAC01_DMARS_CH0_RID_SHIFT (0u) +#define DMAC01_DMARS_CH0_MID_SHIFT (2u) +#define DMAC01_DMARS_CH1_RID_SHIFT (16u) +#define DMAC01_DMARS_CH1_MID_SHIFT (18u) + +/* ---- DMAC2-3 ---- */ +#define DMAC23_DMARS_CH2_RID_SHIFT (0u) +#define DMAC23_DMARS_CH2_MID_SHIFT (2u) +#define DMAC23_DMARS_CH3_RID_SHIFT (16u) +#define DMAC23_DMARS_CH3_MID_SHIFT (18u) + +/* ---- DMAC4-5 ---- */ +#define DMAC45_DMARS_CH4_RID_SHIFT (0u) +#define DMAC45_DMARS_CH4_MID_SHIFT (2u) +#define DMAC45_DMARS_CH5_RID_SHIFT (16u) +#define DMAC45_DMARS_CH5_MID_SHIFT (18u) + +/* ---- DMAC6-7 ---- */ +#define DMAC67_DMARS_CH6_RID_SHIFT (0u) +#define DMAC67_DMARS_CH6_MID_SHIFT (2u) +#define DMAC67_DMARS_CH7_RID_SHIFT (16u) +#define DMAC67_DMARS_CH7_MID_SHIFT (18u) + +/* ---- DMAC8-9 ---- */ +#define DMAC89_DMARS_CH8_RID_SHIFT (0u) +#define DMAC89_DMARS_CH8_MID_SHIFT (2u) +#define DMAC89_DMARS_CH9_RID_SHIFT (16u) +#define DMAC89_DMARS_CH9_MID_SHIFT (18u) + +/* ---- DMAC10-11 ---- */ +#define DMAC1011_DMARS_CH10_RID_SHIFT (0u) +#define DMAC1011_DMARS_CH10_MID_SHIFT (2u) +#define DMAC1011_DMARS_CH11_RID_SHIFT (16u) +#define DMAC1011_DMARS_CH11_MID_SHIFT (18u) + +/* ---- DMAC12-13 ---- */ +#define DMAC1213_DMARS_CH12_RID_SHIFT (0u) +#define DMAC1213_DMARS_CH12_MID_SHIFT (2u) +#define DMAC1213_DMARS_CH13_RID_SHIFT (16u) +#define DMAC1213_DMARS_CH13_MID_SHIFT (18u) + +/* ---- DMAC14-15 ---- */ +#define DMAC1415_DMARS_CH14_RID_SHIFT (0u) +#define DMAC1415_DMARS_CH14_MID_SHIFT (2u) +#define DMAC1415_DMARS_CH15_RID_SHIFT (16u) +#define DMAC1415_DMARS_CH15_MID_SHIFT (18u) + + +#endif /* DMAC_IOBITMASK_H */ + +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,5794 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : gpio_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : General purpose I/O ports register define header +*******************************************************************************/ +#ifndef GPIO_IOBITMASK_H +#define GPIO_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +/* ---- P0 ---- */ +#define GPIO_PPR0_PPR00 (0x0001u) +#define GPIO_PPR0_PPR01 (0x0002u) +#define GPIO_PPR0_PPR02 (0x0004u) +#define GPIO_PPR0_PPR03 (0x0008u) +#define GPIO_PPR0_PPR04 (0x0010u) +#define GPIO_PPR0_PPR05 (0x0020u) + +#define GPIO_PMC0_PMC04 (0x0010u) +#define GPIO_PMC0_PMC05 (0x0020u) + +#define GPIO_PMCSR0_PMCSR04 (0x00000010uL) +#define GPIO_PMCSR0_PMCSR05 (0x00000020uL) + +#define GPIO_PIBC0_PIBC00 (0x0001u) +#define GPIO_PIBC0_PIBC01 (0x0002u) +#define GPIO_PIBC0_PIBC02 (0x0004u) +#define GPIO_PIBC0_PIBC03 (0x0008u) +#define GPIO_PIBC0_PIBC04 (0x0010u) +#define GPIO_PIBC0_PIBC05 (0x0020u) + +/* ---- P1 ---- */ +#define GPIO_P1_P10 (0x0001u) +#define GPIO_P1_P11 (0x0002u) +#define GPIO_P1_P12 (0x0004u) +#define GPIO_P1_P13 (0x0008u) +#define GPIO_P1_P14 (0x0010u) +#define GPIO_P1_P15 (0x0020u) +#define GPIO_P1_P16 (0x0040u) +#define GPIO_P1_P17 (0x0080u) + +#define GPIO_PSR1_PSR10 (0x00000001uL) +#define GPIO_PSR1_PSR11 (0x00000002uL) +#define GPIO_PSR1_PSR12 (0x00000004uL) +#define GPIO_PSR1_PSR13 (0x00000008uL) +#define GPIO_PSR1_PSR14 (0x00000010uL) +#define GPIO_PSR1_PSR15 (0x00000020uL) +#define GPIO_PSR1_PSR16 (0x00000040uL) +#define GPIO_PSR1_PSR17 (0x00000080uL) +#define GPIO_PSR1_PSR116 (0x00010000uL) +#define GPIO_PSR1_PSR117 (0x00020000uL) +#define GPIO_PSR1_PSR118 (0x00040000uL) +#define GPIO_PSR1_PSR119 (0x00080000uL) +#define GPIO_PSR1_PSR120 (0x00100000uL) +#define GPIO_PSR1_PSR121 (0x00200000uL) +#define GPIO_PSR1_PSR122 (0x00400000uL) +#define GPIO_PSR1_PSR123 (0x00800000uL) + +#define GPIO_PPR1_PPR10 (0x0001u) +#define GPIO_PPR1_PPR11 (0x0002u) +#define GPIO_PPR1_PPR12 (0x0004u) +#define GPIO_PPR1_PPR13 (0x0008u) +#define GPIO_PPR1_PPR14 (0x0010u) +#define GPIO_PPR1_PPR15 (0x0020u) +#define GPIO_PPR1_PPR16 (0x0040u) +#define GPIO_PPR1_PPR17 (0x0080u) +#define GPIO_PPR1_PPR18 (0x0100u) +#define GPIO_PPR1_PPR19 (0x0200u) +#define GPIO_PPR1_PPR110 (0x0400u) +#define GPIO_PPR1_PPR111 (0x0800u) +#define GPIO_PPR1_PPR112 (0x1000u) +#define GPIO_PPR1_PPR113 (0x2000u) +#define GPIO_PPR1_PPR114 (0x4000u) +#define GPIO_PPR1_PPR115 (0x8000u) + +#define GPIO_PM1_PM10 (0x0001u) +#define GPIO_PM1_PM11 (0x0002u) +#define GPIO_PM1_PM12 (0x0004u) +#define GPIO_PM1_PM13 (0x0008u) +#define GPIO_PM1_PM14 (0x0010u) +#define GPIO_PM1_PM15 (0x0020u) +#define GPIO_PM1_PM16 (0x0040u) +#define GPIO_PM1_PM17 (0x0080u) + +#define GPIO_PMC1_PMC10 (0x0001u) +#define GPIO_PMC1_PMC11 (0x0002u) +#define GPIO_PMC1_PMC12 (0x0004u) +#define GPIO_PMC1_PMC13 (0x0008u) +#define GPIO_PMC1_PMC14 (0x0010u) +#define GPIO_PMC1_PMC15 (0x0020u) +#define GPIO_PMC1_PMC16 (0x0040u) +#define GPIO_PMC1_PMC17 (0x0080u) +#define GPIO_PMC1_PMC18 (0x0100u) +#define GPIO_PMC1_PMC19 (0x0200u) +#define GPIO_PMC1_PMC110 (0x0400u) +#define GPIO_PMC1_PMC111 (0x0800u) +#define GPIO_PMC1_PMC112 (0x1000u) +#define GPIO_PMC1_PMC113 (0x2000u) +#define GPIO_PMC1_PMC114 (0x4000u) +#define GPIO_PMC1_PMC115 (0x8000u) + +#define GPIO_PFC1_PFC10 (0x0001u) +#define GPIO_PFC1_PFC11 (0x0002u) +#define GPIO_PFC1_PFC12 (0x0004u) +#define GPIO_PFC1_PFC13 (0x0008u) +#define GPIO_PFC1_PFC14 (0x0010u) +#define GPIO_PFC1_PFC15 (0x0020u) +#define GPIO_PFC1_PFC16 (0x0040u) +#define GPIO_PFC1_PFC17 (0x0080u) +#define GPIO_PFC1_PFC18 (0x0100u) +#define GPIO_PFC1_PFC19 (0x0200u) +#define GPIO_PFC1_PFC110 (0x0400u) +#define GPIO_PFC1_PFC111 (0x0800u) +#define GPIO_PFC1_PFC112 (0x1000u) +#define GPIO_PFC1_PFC113 (0x2000u) +#define GPIO_PFC1_PFC114 (0x4000u) +#define GPIO_PFC1_PFC115 (0x8000u) + +#define GPIO_PFCE1_PFCE10 (0x0001u) +#define GPIO_PFCE1_PFCE11 (0x0002u) +#define GPIO_PFCE1_PFCE12 (0x0004u) +#define GPIO_PFCE1_PFCE13 (0x0008u) +#define GPIO_PFCE1_PFCE14 (0x0010u) +#define GPIO_PFCE1_PFCE15 (0x0020u) +#define GPIO_PFCE1_PFCE16 (0x0040u) +#define GPIO_PFCE1_PFCE17 (0x0080u) +#define GPIO_PFCE1_PFCE18 (0x0100u) +#define GPIO_PFCE1_PFCE19 (0x0200u) +#define GPIO_PFCE1_PFCE110 (0x0400u) +#define GPIO_PFCE1_PFCE111 (0x0800u) +#define GPIO_PFCE1_PFCE112 (0x1000u) +#define GPIO_PFCE1_PFCE113 (0x2000u) +#define GPIO_PFCE1_PFCE114 (0x4000u) +#define GPIO_PFCE1_PFCE115 (0x8000u) + +#define GPIO_PNOT1_PNOT10 (0x0001u) +#define GPIO_PNOT1_PNOT11 (0x0002u) +#define GPIO_PNOT1_PNOT12 (0x0004u) +#define GPIO_PNOT1_PNOT13 (0x0008u) +#define GPIO_PNOT1_PNOT14 (0x0010u) +#define GPIO_PNOT1_PNOT15 (0x0020u) +#define GPIO_PNOT1_PNOT16 (0x0040u) +#define GPIO_PNOT1_PNOT17 (0x0080u) + +#define GPIO_PMSR1_PMSR10 (0x00000001uL) +#define GPIO_PMSR1_PMSR11 (0x00000002uL) +#define GPIO_PMSR1_PMSR12 (0x00000004uL) +#define GPIO_PMSR1_PMSR13 (0x00000008uL) +#define GPIO_PMSR1_PMSR14 (0x00000010uL) +#define GPIO_PMSR1_PMSR15 (0x00000020uL) +#define GPIO_PMSR1_PMSR16 (0x00000040uL) +#define GPIO_PMSR1_PMSR17 (0x00000080uL) +#define GPIO_PMSR1_PMSR116 (0x00010000uL) +#define GPIO_PMSR1_PMSR117 (0x00020000uL) +#define GPIO_PMSR1_PMSR118 (0x00040000uL) +#define GPIO_PMSR1_PMSR119 (0x00080000uL) +#define GPIO_PMSR1_PMSR120 (0x00100000uL) +#define GPIO_PMSR1_PMSR121 (0x00200000uL) +#define GPIO_PMSR1_PMSR122 (0x00400000uL) +#define GPIO_PMSR1_PMSR123 (0x00800000uL) + +#define GPIO_PMCSR1_PMCSR10 (0x00000001uL) +#define GPIO_PMCSR1_PMCSR11 (0x00000002uL) +#define GPIO_PMCSR1_PMCSR12 (0x00000004uL) +#define GPIO_PMCSR1_PMCSR13 (0x00000008uL) +#define GPIO_PMCSR1_PMCSR14 (0x00000010uL) +#define GPIO_PMCSR1_PMCSR15 (0x00000020uL) +#define GPIO_PMCSR1_PMCSR16 (0x00000040uL) +#define GPIO_PMCSR1_PMCSR17 (0x00000080uL) +#define GPIO_PMCSR1_PMCSR116 (0x00010000uL) +#define GPIO_PMCSR1_PMCSR117 (0x00020000uL) +#define GPIO_PMCSR1_PMCSR118 (0x00040000uL) +#define GPIO_PMCSR1_PMCSR119 (0x00080000uL) +#define GPIO_PMCSR1_PMCSR120 (0x00100000uL) +#define GPIO_PMCSR1_PMCSR121 (0x00200000uL) +#define GPIO_PMCSR1_PMCSR122 (0x00400000uL) +#define GPIO_PMCSR1_PMCSR123 (0x00800000uL) + +#define GPIO_PFCAE1_PFCAE10 (0x0001u) +#define GPIO_PFCAE1_PFCAE11 (0x0002u) +#define GPIO_PFCAE1_PFCAE12 (0x0004u) +#define GPIO_PFCAE1_PFCAE13 (0x0008u) +#define GPIO_PFCAE1_PFCAE14 (0x0010u) +#define GPIO_PFCAE1_PFCAE15 (0x0020u) +#define GPIO_PFCAE1_PFCAE16 (0x0040u) +#define GPIO_PFCAE1_PFCAE17 (0x0080u) +#define GPIO_PFCAE1_PFCAE18 (0x0100u) +#define GPIO_PFCAE1_PFCAE19 (0x0200u) +#define GPIO_PFCAE1_PFCAE110 (0x0400u) +#define GPIO_PFCAE1_PFCAE111 (0x0800u) +#define GPIO_PFCAE1_PFCAE112 (0x1000u) +#define GPIO_PFCAE1_PFCAE113 (0x2000u) +#define GPIO_PFCAE1_PFCAE114 (0x4000u) +#define GPIO_PFCAE1_PFCAE115 (0x8000u) + +#define GPIO_PIBC1_PIBC10 (0x0001u) +#define GPIO_PIBC1_PIBC11 (0x0002u) +#define GPIO_PIBC1_PIBC12 (0x0004u) +#define GPIO_PIBC1_PIBC13 (0x0008u) +#define GPIO_PIBC1_PIBC14 (0x0010u) +#define GPIO_PIBC1_PIBC15 (0x0020u) +#define GPIO_PIBC1_PIBC16 (0x0040u) +#define GPIO_PIBC1_PIBC17 (0x0080u) +#define GPIO_PIBC1_PIBC18 (0x0100u) +#define GPIO_PIBC1_PIBC19 (0x0200u) +#define GPIO_PIBC1_PIBC110 (0x0400u) +#define GPIO_PIBC1_PIBC111 (0x0800u) +#define GPIO_PIBC1_PIBC112 (0x1000u) +#define GPIO_PIBC1_PIBC113 (0x2000u) +#define GPIO_PIBC1_PIBC114 (0x4000u) +#define GPIO_PIBC1_PIBC115 (0x8000u) + +#define GPIO_PBDC1_PBDC10 (0x0001u) +#define GPIO_PBDC1_PBDC11 (0x0002u) +#define GPIO_PBDC1_PBDC12 (0x0004u) +#define GPIO_PBDC1_PBDC13 (0x0008u) +#define GPIO_PBDC1_PBDC14 (0x0010u) +#define GPIO_PBDC1_PBDC15 (0x0020u) +#define GPIO_PBDC1_PBDC16 (0x0040u) +#define GPIO_PBDC1_PBDC17 (0x0080u) +#define GPIO_PBDC1_PBDC18 (0x0100u) +#define GPIO_PBDC1_PBDC19 (0x0200u) +#define GPIO_PBDC1_PBDC110 (0x0400u) +#define GPIO_PBDC1_PBDC111 (0x0800u) +#define GPIO_PBDC1_PBDC112 (0x1000u) +#define GPIO_PBDC1_PBDC113 (0x2000u) +#define GPIO_PBDC1_PBDC114 (0x4000u) +#define GPIO_PBDC1_PBDC115 (0x8000u) + +#define GPIO_PIPC1_PIPC10 (0x0001u) +#define GPIO_PIPC1_PIPC11 (0x0002u) +#define GPIO_PIPC1_PIPC12 (0x0004u) +#define GPIO_PIPC1_PIPC13 (0x0008u) +#define GPIO_PIPC1_PIPC14 (0x0010u) +#define GPIO_PIPC1_PIPC15 (0x0020u) +#define GPIO_PIPC1_PIPC16 (0x0040u) +#define GPIO_PIPC1_PIPC17 (0x0080u) + +/* ---- P2 ---- */ +#define GPIO_P2_P20 (0x0001u) +#define GPIO_P2_P21 (0x0002u) +#define GPIO_P2_P22 (0x0004u) +#define GPIO_P2_P23 (0x0008u) +#define GPIO_P2_P24 (0x0010u) +#define GPIO_P2_P25 (0x0020u) +#define GPIO_P2_P26 (0x0040u) +#define GPIO_P2_P27 (0x0080u) +#define GPIO_P2_P28 (0x0100u) +#define GPIO_P2_P29 (0x0200u) +#define GPIO_P2_P210 (0x0400u) +#define GPIO_P2_P211 (0x0800u) +#define GPIO_P2_P212 (0x1000u) +#define GPIO_P2_P213 (0x2000u) +#define GPIO_P2_P214 (0x4000u) +#define GPIO_P2_P215 (0x8000u) + +#define GPIO_PSR2_PSR20 (0x00000001uL) +#define GPIO_PSR2_PSR21 (0x00000002uL) +#define GPIO_PSR2_PSR22 (0x00000004uL) +#define GPIO_PSR2_PSR23 (0x00000008uL) +#define GPIO_PSR2_PSR24 (0x00000010uL) +#define GPIO_PSR2_PSR25 (0x00000020uL) +#define GPIO_PSR2_PSR26 (0x00000040uL) +#define GPIO_PSR2_PSR27 (0x00000080uL) +#define GPIO_PSR2_PSR28 (0x00000100uL) +#define GPIO_PSR2_PSR29 (0x00000200uL) +#define GPIO_PSR2_PSR210 (0x00000400uL) +#define GPIO_PSR2_PSR211 (0x00000800uL) +#define GPIO_PSR2_PSR212 (0x00001000uL) +#define GPIO_PSR2_PSR213 (0x00002000uL) +#define GPIO_PSR2_PSR214 (0x00004000uL) +#define GPIO_PSR2_PSR215 (0x00008000uL) +#define GPIO_PSR2_PSR216 (0x00010000uL) +#define GPIO_PSR2_PSR217 (0x00020000uL) +#define GPIO_PSR2_PSR218 (0x00040000uL) +#define GPIO_PSR2_PSR219 (0x00080000uL) +#define GPIO_PSR2_PSR220 (0x00100000uL) +#define GPIO_PSR2_PSR221 (0x00200000uL) +#define GPIO_PSR2_PSR222 (0x00400000uL) +#define GPIO_PSR2_PSR223 (0x00800000uL) +#define GPIO_PSR2_PSR224 (0x01000000uL) +#define GPIO_PSR2_PSR225 (0x02000000uL) +#define GPIO_PSR2_PSR226 (0x04000000uL) +#define GPIO_PSR2_PSR227 (0x08000000uL) +#define GPIO_PSR2_PSR228 (0x10000000uL) +#define GPIO_PSR2_PSR229 (0x20000000uL) +#define GPIO_PSR2_PSR230 (0x40000000uL) +#define GPIO_PSR2_PSR231 (0x80000000uL) + +#define GPIO_PPR2_PPR20 (0x0001u) +#define GPIO_PPR2_PPR21 (0x0002u) +#define GPIO_PPR2_PPR22 (0x0004u) +#define GPIO_PPR2_PPR23 (0x0008u) +#define GPIO_PPR2_PPR24 (0x0010u) +#define GPIO_PPR2_PPR25 (0x0020u) +#define GPIO_PPR2_PPR26 (0x0040u) +#define GPIO_PPR2_PPR27 (0x0080u) +#define GPIO_PPR2_PPR28 (0x0100u) +#define GPIO_PPR2_PPR29 (0x0200u) +#define GPIO_PPR2_PPR210 (0x0400u) +#define GPIO_PPR2_PPR211 (0x0800u) +#define GPIO_PPR2_PPR212 (0x1000u) +#define GPIO_PPR2_PPR213 (0x2000u) +#define GPIO_PPR2_PPR214 (0x4000u) +#define GPIO_PPR2_PPR215 (0x8000u) + +#define GPIO_PM2_PM20 (0x0001u) +#define GPIO_PM2_PM21 (0x0002u) +#define GPIO_PM2_PM22 (0x0004u) +#define GPIO_PM2_PM23 (0x0008u) +#define GPIO_PM2_PM24 (0x0010u) +#define GPIO_PM2_PM25 (0x0020u) +#define GPIO_PM2_PM26 (0x0040u) +#define GPIO_PM2_PM27 (0x0080u) +#define GPIO_PM2_PM28 (0x0100u) +#define GPIO_PM2_PM29 (0x0200u) +#define GPIO_PM2_PM210 (0x0400u) +#define GPIO_PM2_PM211 (0x0800u) +#define GPIO_PM2_PM212 (0x1000u) +#define GPIO_PM2_PM213 (0x2000u) +#define GPIO_PM2_PM214 (0x4000u) +#define GPIO_PM2_PM215 (0x8000u) + +#define GPIO_PMC2_PMC20 (0x0001u) +#define GPIO_PMC2_PMC21 (0x0002u) +#define GPIO_PMC2_PMC22 (0x0004u) +#define GPIO_PMC2_PMC23 (0x0008u) +#define GPIO_PMC2_PMC24 (0x0010u) +#define GPIO_PMC2_PMC25 (0x0020u) +#define GPIO_PMC2_PMC26 (0x0040u) +#define GPIO_PMC2_PMC27 (0x0080u) +#define GPIO_PMC2_PMC28 (0x0100u) +#define GPIO_PMC2_PMC29 (0x0200u) +#define GPIO_PMC2_PMC210 (0x0400u) +#define GPIO_PMC2_PMC211 (0x0800u) +#define GPIO_PMC2_PMC212 (0x1000u) +#define GPIO_PMC2_PMC213 (0x2000u) +#define GPIO_PMC2_PMC214 (0x4000u) +#define GPIO_PMC2_PMC215 (0x8000u) + +#define GPIO_PFC2_PFC20 (0x0001u) +#define GPIO_PFC2_PFC21 (0x0002u) +#define GPIO_PFC2_PFC22 (0x0004u) +#define GPIO_PFC2_PFC23 (0x0008u) +#define GPIO_PFC2_PFC24 (0x0010u) +#define GPIO_PFC2_PFC25 (0x0020u) +#define GPIO_PFC2_PFC26 (0x0040u) +#define GPIO_PFC2_PFC27 (0x0080u) +#define GPIO_PFC2_PFC28 (0x0100u) +#define GPIO_PFC2_PFC29 (0x0200u) +#define GPIO_PFC2_PFC210 (0x0400u) +#define GPIO_PFC2_PFC211 (0x0800u) +#define GPIO_PFC2_PFC212 (0x1000u) +#define GPIO_PFC2_PFC213 (0x2000u) +#define GPIO_PFC2_PFC214 (0x4000u) +#define GPIO_PFC2_PFC215 (0x8000u) + +#define GPIO_PFCE2_PFCE20 (0x0001u) +#define GPIO_PFCE2_PFCE21 (0x0002u) +#define GPIO_PFCE2_PFCE22 (0x0004u) +#define GPIO_PFCE2_PFCE23 (0x0008u) +#define GPIO_PFCE2_PFCE24 (0x0010u) +#define GPIO_PFCE2_PFCE25 (0x0020u) +#define GPIO_PFCE2_PFCE26 (0x0040u) +#define GPIO_PFCE2_PFCE27 (0x0080u) +#define GPIO_PFCE2_PFCE28 (0x0100u) +#define GPIO_PFCE2_PFCE29 (0x0200u) +#define GPIO_PFCE2_PFCE210 (0x0400u) +#define GPIO_PFCE2_PFCE211 (0x0800u) +#define GPIO_PFCE2_PFCE212 (0x1000u) +#define GPIO_PFCE2_PFCE213 (0x2000u) +#define GPIO_PFCE2_PFCE214 (0x4000u) +#define GPIO_PFCE2_PFCE215 (0x8000u) + +#define GPIO_PNOT2_PNOT20 (0x0001u) +#define GPIO_PNOT2_PNOT21 (0x0002u) +#define GPIO_PNOT2_PNOT22 (0x0004u) +#define GPIO_PNOT2_PNOT23 (0x0008u) +#define GPIO_PNOT2_PNOT24 (0x0010u) +#define GPIO_PNOT2_PNOT25 (0x0020u) +#define GPIO_PNOT2_PNOT26 (0x0040u) +#define GPIO_PNOT2_PNOT27 (0x0080u) +#define GPIO_PNOT2_PNOT28 (0x0100u) +#define GPIO_PNOT2_PNOT29 (0x0200u) +#define GPIO_PNOT2_PNOT210 (0x0400u) +#define GPIO_PNOT2_PNOT211 (0x0800u) +#define GPIO_PNOT2_PNOT212 (0x1000u) +#define GPIO_PNOT2_PNOT213 (0x2000u) +#define GPIO_PNOT2_PNOT214 (0x4000u) +#define GPIO_PNOT2_PNOT215 (0x8000u) + +#define GPIO_PMSR2_PMSR20 (0x00000001uL) +#define GPIO_PMSR2_PMSR21 (0x00000002uL) +#define GPIO_PMSR2_PMSR22 (0x00000004uL) +#define GPIO_PMSR2_PMSR23 (0x00000008uL) +#define GPIO_PMSR2_PMSR24 (0x00000010uL) +#define GPIO_PMSR2_PMSR25 (0x00000020uL) +#define GPIO_PMSR2_PMSR26 (0x00000040uL) +#define GPIO_PMSR2_PMSR27 (0x00000080uL) +#define GPIO_PMSR2_PMSR28 (0x00000100uL) +#define GPIO_PMSR2_PMSR29 (0x00000200uL) +#define GPIO_PMSR2_PMSR210 (0x00000400uL) +#define GPIO_PMSR2_PMSR211 (0x00000800uL) +#define GPIO_PMSR2_PMSR212 (0x00001000uL) +#define GPIO_PMSR2_PMSR213 (0x00002000uL) +#define GPIO_PMSR2_PMSR214 (0x00004000uL) +#define GPIO_PMSR2_PMSR215 (0x00008000uL) +#define GPIO_PMSR2_PMSR216 (0x00010000uL) +#define GPIO_PMSR2_PMSR217 (0x00020000uL) +#define GPIO_PMSR2_PMSR218 (0x00040000uL) +#define GPIO_PMSR2_PMSR219 (0x00080000uL) +#define GPIO_PMSR2_PMSR220 (0x00100000uL) +#define GPIO_PMSR2_PMSR221 (0x00200000uL) +#define GPIO_PMSR2_PMSR222 (0x00400000uL) +#define GPIO_PMSR2_PMSR223 (0x00800000uL) +#define GPIO_PMSR2_PMSR224 (0x01000000uL) +#define GPIO_PMSR2_PMSR225 (0x02000000uL) +#define GPIO_PMSR2_PMSR226 (0x04000000uL) +#define GPIO_PMSR2_PMSR227 (0x08000000uL) +#define GPIO_PMSR2_PMSR228 (0x10000000uL) +#define GPIO_PMSR2_PMSR229 (0x20000000uL) +#define GPIO_PMSR2_PMSR230 (0x40000000uL) +#define GPIO_PMSR2_PMSR231 (0x80000000uL) + +#define GPIO_PMCSR2_PMCSR20 (0x00000001uL) +#define GPIO_PMCSR2_PMCSR21 (0x00000002uL) +#define GPIO_PMCSR2_PMCSR22 (0x00000004uL) +#define GPIO_PMCSR2_PMCSR23 (0x00000008uL) +#define GPIO_PMCSR2_PMCSR24 (0x00000010uL) +#define GPIO_PMCSR2_PMCSR25 (0x00000020uL) +#define GPIO_PMCSR2_PMCSR26 (0x00000040uL) +#define GPIO_PMCSR2_PMCSR27 (0x00000080uL) +#define GPIO_PMCSR2_PMCSR28 (0x00000100uL) +#define GPIO_PMCSR2_PMCSR29 (0x00000200uL) +#define GPIO_PMCSR2_PMCSR210 (0x00000400uL) +#define GPIO_PMCSR2_PMCSR211 (0x00000800uL) +#define GPIO_PMCSR2_PMCSR212 (0x00001000uL) +#define GPIO_PMCSR2_PMCSR213 (0x00002000uL) +#define GPIO_PMCSR2_PMCSR214 (0x00004000uL) +#define GPIO_PMCSR2_PMCSR215 (0x00008000uL) +#define GPIO_PMCSR2_PMCSR216 (0x00010000uL) +#define GPIO_PMCSR2_PMCSR217 (0x00020000uL) +#define GPIO_PMCSR2_PMCSR218 (0x00040000uL) +#define GPIO_PMCSR2_PMCSR219 (0x00080000uL) +#define GPIO_PMCSR2_PMCSR220 (0x00100000uL) +#define GPIO_PMCSR2_PMCSR221 (0x00200000uL) +#define GPIO_PMCSR2_PMCSR222 (0x00400000uL) +#define GPIO_PMCSR2_PMCSR223 (0x00800000uL) +#define GPIO_PMCSR2_PMCSR224 (0x01000000uL) +#define GPIO_PMCSR2_PMCSR225 (0x02000000uL) +#define GPIO_PMCSR2_PMCSR226 (0x04000000uL) +#define GPIO_PMCSR2_PMCSR227 (0x08000000uL) +#define GPIO_PMCSR2_PMCSR228 (0x10000000uL) +#define GPIO_PMCSR2_PMCSR229 (0x20000000uL) +#define GPIO_PMCSR2_PMCSR230 (0x40000000uL) +#define GPIO_PMCSR2_PMCSR231 (0x80000000uL) + +#define GPIO_PFCAE2_PFCAE20 (0x0001u) +#define GPIO_PFCAE2_PFCAE21 (0x0002u) +#define GPIO_PFCAE2_PFCAE22 (0x0004u) +#define GPIO_PFCAE2_PFCAE23 (0x0008u) +#define GPIO_PFCAE2_PFCAE24 (0x0010u) +#define GPIO_PFCAE2_PFCAE25 (0x0020u) +#define GPIO_PFCAE2_PFCAE26 (0x0040u) +#define GPIO_PFCAE2_PFCAE27 (0x0080u) +#define GPIO_PFCAE2_PFCAE28 (0x0100u) +#define GPIO_PFCAE2_PFCAE29 (0x0200u) +#define GPIO_PFCAE2_PFCAE210 (0x0400u) +#define GPIO_PFCAE2_PFCAE211 (0x0800u) +#define GPIO_PFCAE2_PFCAE212 (0x1000u) +#define GPIO_PFCAE2_PFCAE213 (0x2000u) +#define GPIO_PFCAE2_PFCAE214 (0x4000u) +#define GPIO_PFCAE2_PFCAE215 (0x8000u) + +#define GPIO_PIBC2_PIBC20 (0x0001u) +#define GPIO_PIBC2_PIBC21 (0x0002u) +#define GPIO_PIBC2_PIBC22 (0x0004u) +#define GPIO_PIBC2_PIBC23 (0x0008u) +#define GPIO_PIBC2_PIBC24 (0x0010u) +#define GPIO_PIBC2_PIBC25 (0x0020u) +#define GPIO_PIBC2_PIBC26 (0x0040u) +#define GPIO_PIBC2_PIBC27 (0x0080u) +#define GPIO_PIBC2_PIBC28 (0x0100u) +#define GPIO_PIBC2_PIBC29 (0x0200u) +#define GPIO_PIBC2_PIBC210 (0x0400u) +#define GPIO_PIBC2_PIBC211 (0x0800u) +#define GPIO_PIBC2_PIBC212 (0x1000u) +#define GPIO_PIBC2_PIBC213 (0x2000u) +#define GPIO_PIBC2_PIBC214 (0x4000u) +#define GPIO_PIBC2_PIBC215 (0x8000u) + +#define GPIO_PBDC2_PBDC20 (0x0001u) +#define GPIO_PBDC2_PBDC21 (0x0002u) +#define GPIO_PBDC2_PBDC22 (0x0004u) +#define GPIO_PBDC2_PBDC23 (0x0008u) +#define GPIO_PBDC2_PBDC24 (0x0010u) +#define GPIO_PBDC2_PBDC25 (0x0020u) +#define GPIO_PBDC2_PBDC26 (0x0040u) +#define GPIO_PBDC2_PBDC27 (0x0080u) +#define GPIO_PBDC2_PBDC28 (0x0100u) +#define GPIO_PBDC2_PBDC29 (0x0200u) +#define GPIO_PBDC2_PBDC210 (0x0400u) +#define GPIO_PBDC2_PBDC211 (0x0800u) +#define GPIO_PBDC2_PBDC212 (0x1000u) +#define GPIO_PBDC2_PBDC213 (0x2000u) +#define GPIO_PBDC2_PBDC214 (0x4000u) +#define GPIO_PBDC2_PBDC215 (0x8000u) + +#define GPIO_PIPC2_PIPC20 (0x0001u) +#define GPIO_PIPC2_PIPC21 (0x0002u) +#define GPIO_PIPC2_PIPC22 (0x0004u) +#define GPIO_PIPC2_PIPC23 (0x0008u) +#define GPIO_PIPC2_PIPC24 (0x0010u) +#define GPIO_PIPC2_PIPC25 (0x0020u) +#define GPIO_PIPC2_PIPC26 (0x0040u) +#define GPIO_PIPC2_PIPC27 (0x0080u) +#define GPIO_PIPC2_PIPC28 (0x0100u) +#define GPIO_PIPC2_PIPC29 (0x0200u) +#define GPIO_PIPC2_PIPC210 (0x0400u) +#define GPIO_PIPC2_PIPC211 (0x0800u) +#define GPIO_PIPC2_PIPC212 (0x1000u) +#define GPIO_PIPC2_PIPC213 (0x2000u) +#define GPIO_PIPC2_PIPC214 (0x4000u) +#define GPIO_PIPC2_PIPC215 (0x8000u) + +/* ---- P3 ---- */ +#define GPIO_P3_P30 (0x0001u) +#define GPIO_P3_P31 (0x0002u) +#define GPIO_P3_P32 (0x0004u) +#define GPIO_P3_P33 (0x0008u) +#define GPIO_P3_P34 (0x0010u) +#define GPIO_P3_P35 (0x0020u) +#define GPIO_P3_P36 (0x0040u) +#define GPIO_P3_P37 (0x0080u) +#define GPIO_P3_P38 (0x0100u) +#define GPIO_P3_P39 (0x0200u) +#define GPIO_P3_P310 (0x0400u) +#define GPIO_P3_P311 (0x0800u) +#define GPIO_P3_P312 (0x1000u) +#define GPIO_P3_P313 (0x2000u) +#define GPIO_P3_P314 (0x4000u) +#define GPIO_P3_P315 (0x8000u) + +#define GPIO_PSR3_PSR30 (0x00000001uL) +#define GPIO_PSR3_PSR31 (0x00000002uL) +#define GPIO_PSR3_PSR32 (0x00000004uL) +#define GPIO_PSR3_PSR33 (0x00000008uL) +#define GPIO_PSR3_PSR34 (0x00000010uL) +#define GPIO_PSR3_PSR35 (0x00000020uL) +#define GPIO_PSR3_PSR36 (0x00000040uL) +#define GPIO_PSR3_PSR37 (0x00000080uL) +#define GPIO_PSR3_PSR38 (0x00000100uL) +#define GPIO_PSR3_PSR39 (0x00000200uL) +#define GPIO_PSR3_PSR310 (0x00000400uL) +#define GPIO_PSR3_PSR311 (0x00000800uL) +#define GPIO_PSR3_PSR312 (0x00001000uL) +#define GPIO_PSR3_PSR313 (0x00002000uL) +#define GPIO_PSR3_PSR314 (0x00004000uL) +#define GPIO_PSR3_PSR315 (0x00008000uL) +#define GPIO_PSR3_PSR316 (0x00010000uL) +#define GPIO_PSR3_PSR317 (0x00020000uL) +#define GPIO_PSR3_PSR318 (0x00040000uL) +#define GPIO_PSR3_PSR319 (0x00080000uL) +#define GPIO_PSR3_PSR320 (0x00100000uL) +#define GPIO_PSR3_PSR321 (0x00200000uL) +#define GPIO_PSR3_PSR322 (0x00400000uL) +#define GPIO_PSR3_PSR323 (0x00800000uL) +#define GPIO_PSR3_PSR324 (0x01000000uL) +#define GPIO_PSR3_PSR325 (0x02000000uL) +#define GPIO_PSR3_PSR326 (0x04000000uL) +#define GPIO_PSR3_PSR327 (0x08000000uL) +#define GPIO_PSR3_PSR328 (0x10000000uL) +#define GPIO_PSR3_PSR329 (0x20000000uL) +#define GPIO_PSR3_PSR330 (0x40000000uL) +#define GPIO_PSR3_PSR331 (0x80000000uL) + +#define GPIO_PPR3_PPR30 (0x0001u) +#define GPIO_PPR3_PPR31 (0x0002u) +#define GPIO_PPR3_PPR32 (0x0004u) +#define GPIO_PPR3_PPR33 (0x0008u) +#define GPIO_PPR3_PPR34 (0x0010u) +#define GPIO_PPR3_PPR35 (0x0020u) +#define GPIO_PPR3_PPR36 (0x0040u) +#define GPIO_PPR3_PPR37 (0x0080u) +#define GPIO_PPR3_PPR38 (0x0100u) +#define GPIO_PPR3_PPR39 (0x0200u) +#define GPIO_PPR3_PPR310 (0x0400u) +#define GPIO_PPR3_PPR311 (0x0800u) +#define GPIO_PPR3_PPR312 (0x1000u) +#define GPIO_PPR3_PPR313 (0x2000u) +#define GPIO_PPR3_PPR314 (0x4000u) +#define GPIO_PPR3_PPR315 (0x8000u) + +#define GPIO_PM3_PM30 (0x0001u) +#define GPIO_PM3_PM31 (0x0002u) +#define GPIO_PM3_PM32 (0x0004u) +#define GPIO_PM3_PM33 (0x0008u) +#define GPIO_PM3_PM34 (0x0010u) +#define GPIO_PM3_PM35 (0x0020u) +#define GPIO_PM3_PM36 (0x0040u) +#define GPIO_PM3_PM37 (0x0080u) +#define GPIO_PM3_PM38 (0x0100u) +#define GPIO_PM3_PM39 (0x0200u) +#define GPIO_PM3_PM310 (0x0400u) +#define GPIO_PM3_PM311 (0x0800u) +#define GPIO_PM3_PM312 (0x1000u) +#define GPIO_PM3_PM313 (0x2000u) +#define GPIO_PM3_PM314 (0x4000u) +#define GPIO_PM3_PM315 (0x8000u) + +#define GPIO_PMC3_PMC30 (0x0001u) +#define GPIO_PMC3_PMC31 (0x0002u) +#define GPIO_PMC3_PMC32 (0x0004u) +#define GPIO_PMC3_PMC33 (0x0008u) +#define GPIO_PMC3_PMC34 (0x0010u) +#define GPIO_PMC3_PMC35 (0x0020u) +#define GPIO_PMC3_PMC36 (0x0040u) +#define GPIO_PMC3_PMC37 (0x0080u) +#define GPIO_PMC3_PMC38 (0x0100u) +#define GPIO_PMC3_PMC39 (0x0200u) +#define GPIO_PMC3_PMC310 (0x0400u) +#define GPIO_PMC3_PMC311 (0x0800u) +#define GPIO_PMC3_PMC312 (0x1000u) +#define GPIO_PMC3_PMC313 (0x2000u) +#define GPIO_PMC3_PMC314 (0x4000u) +#define GPIO_PMC3_PMC315 (0x8000u) + +#define GPIO_PFC3_PFC30 (0x0001u) +#define GPIO_PFC3_PFC31 (0x0002u) +#define GPIO_PFC3_PFC32 (0x0004u) +#define GPIO_PFC3_PFC33 (0x0008u) +#define GPIO_PFC3_PFC34 (0x0010u) +#define GPIO_PFC3_PFC35 (0x0020u) +#define GPIO_PFC3_PFC36 (0x0040u) +#define GPIO_PFC3_PFC37 (0x0080u) +#define GPIO_PFC3_PFC38 (0x0100u) +#define GPIO_PFC3_PFC39 (0x0200u) +#define GPIO_PFC3_PFC310 (0x0400u) +#define GPIO_PFC3_PFC311 (0x0800u) +#define GPIO_PFC3_PFC312 (0x1000u) +#define GPIO_PFC3_PFC313 (0x2000u) +#define GPIO_PFC3_PFC314 (0x4000u) +#define GPIO_PFC3_PFC315 (0x8000u) + +#define GPIO_PFCE3_PFCE30 (0x0001u) +#define GPIO_PFCE3_PFCE31 (0x0002u) +#define GPIO_PFCE3_PFCE32 (0x0004u) +#define GPIO_PFCE3_PFCE33 (0x0008u) +#define GPIO_PFCE3_PFCE34 (0x0010u) +#define GPIO_PFCE3_PFCE35 (0x0020u) +#define GPIO_PFCE3_PFCE36 (0x0040u) +#define GPIO_PFCE3_PFCE37 (0x0080u) +#define GPIO_PFCE3_PFCE38 (0x0100u) +#define GPIO_PFCE3_PFCE39 (0x0200u) +#define GPIO_PFCE3_PFCE310 (0x0400u) +#define GPIO_PFCE3_PFCE311 (0x0800u) +#define GPIO_PFCE3_PFCE312 (0x1000u) +#define GPIO_PFCE3_PFCE313 (0x2000u) +#define GPIO_PFCE3_PFCE314 (0x4000u) +#define GPIO_PFCE3_PFCE315 (0x8000u) + +#define GPIO_PNOT3_PNOT30 (0x0001u) +#define GPIO_PNOT3_PNOT31 (0x0002u) +#define GPIO_PNOT3_PNOT32 (0x0004u) +#define GPIO_PNOT3_PNOT33 (0x0008u) +#define GPIO_PNOT3_PNOT34 (0x0010u) +#define GPIO_PNOT3_PNOT35 (0x0020u) +#define GPIO_PNOT3_PNOT36 (0x0040u) +#define GPIO_PNOT3_PNOT37 (0x0080u) +#define GPIO_PNOT3_PNOT38 (0x0100u) +#define GPIO_PNOT3_PNOT39 (0x0200u) +#define GPIO_PNOT3_PNOT310 (0x0400u) +#define GPIO_PNOT3_PNOT311 (0x0800u) +#define GPIO_PNOT3_PNOT312 (0x1000u) +#define GPIO_PNOT3_PNOT313 (0x2000u) +#define GPIO_PNOT3_PNOT314 (0x4000u) +#define GPIO_PNOT3_PNOT315 (0x8000u) + +#define GPIO_PMSR3_PMSR30 (0x00000001uL) +#define GPIO_PMSR3_PMSR31 (0x00000002uL) +#define GPIO_PMSR3_PMSR32 (0x00000004uL) +#define GPIO_PMSR3_PMSR33 (0x00000008uL) +#define GPIO_PMSR3_PMSR34 (0x00000010uL) +#define GPIO_PMSR3_PMSR35 (0x00000020uL) +#define GPIO_PMSR3_PMSR36 (0x00000040uL) +#define GPIO_PMSR3_PMSR37 (0x00000080uL) +#define GPIO_PMSR3_PMSR38 (0x00000100uL) +#define GPIO_PMSR3_PMSR39 (0x00000200uL) +#define GPIO_PMSR3_PMSR310 (0x00000400uL) +#define GPIO_PMSR3_PMSR311 (0x00000800uL) +#define GPIO_PMSR3_PMSR312 (0x00001000uL) +#define GPIO_PMSR3_PMSR313 (0x00002000uL) +#define GPIO_PMSR3_PMSR314 (0x00004000uL) +#define GPIO_PMSR3_PMSR315 (0x00008000uL) +#define GPIO_PMSR3_PMSR316 (0x00010000uL) +#define GPIO_PMSR3_PMSR317 (0x00020000uL) +#define GPIO_PMSR3_PMSR318 (0x00040000uL) +#define GPIO_PMSR3_PMSR319 (0x00080000uL) +#define GPIO_PMSR3_PMSR320 (0x00100000uL) +#define GPIO_PMSR3_PMSR321 (0x00200000uL) +#define GPIO_PMSR3_PMSR322 (0x00400000uL) +#define GPIO_PMSR3_PMSR323 (0x00800000uL) +#define GPIO_PMSR3_PMSR324 (0x01000000uL) +#define GPIO_PMSR3_PMSR325 (0x02000000uL) +#define GPIO_PMSR3_PMSR326 (0x04000000uL) +#define GPIO_PMSR3_PMSR327 (0x08000000uL) +#define GPIO_PMSR3_PMSR328 (0x10000000uL) +#define GPIO_PMSR3_PMSR329 (0x20000000uL) +#define GPIO_PMSR3_PMSR330 (0x40000000uL) +#define GPIO_PMSR3_PMSR331 (0x80000000uL) + +#define GPIO_PMCSR3_PMCSR30 (0x00000001uL) +#define GPIO_PMCSR3_PMCSR31 (0x00000002uL) +#define GPIO_PMCSR3_PMCSR32 (0x00000004uL) +#define GPIO_PMCSR3_PMCSR33 (0x00000008uL) +#define GPIO_PMCSR3_PMCSR34 (0x00000010uL) +#define GPIO_PMCSR3_PMCSR35 (0x00000020uL) +#define GPIO_PMCSR3_PMCSR36 (0x00000040uL) +#define GPIO_PMCSR3_PMCSR37 (0x00000080uL) +#define GPIO_PMCSR3_PMCSR38 (0x00000100uL) +#define GPIO_PMCSR3_PMCSR39 (0x00000200uL) +#define GPIO_PMCSR3_PMCSR310 (0x00000400uL) +#define GPIO_PMCSR3_PMCSR311 (0x00000800uL) +#define GPIO_PMCSR3_PMCSR312 (0x00001000uL) +#define GPIO_PMCSR3_PMCSR313 (0x00002000uL) +#define GPIO_PMCSR3_PMCSR314 (0x00004000uL) +#define GPIO_PMCSR3_PMCSR315 (0x00008000uL) +#define GPIO_PMCSR3_PMCSR316 (0x00010000uL) +#define GPIO_PMCSR3_PMCSR317 (0x00020000uL) +#define GPIO_PMCSR3_PMCSR318 (0x00040000uL) +#define GPIO_PMCSR3_PMCSR319 (0x00080000uL) +#define GPIO_PMCSR3_PMCSR320 (0x00100000uL) +#define GPIO_PMCSR3_PMCSR321 (0x00200000uL) +#define GPIO_PMCSR3_PMCSR322 (0x00400000uL) +#define GPIO_PMCSR3_PMCSR323 (0x00800000uL) +#define GPIO_PMCSR3_PMCSR324 (0x01000000uL) +#define GPIO_PMCSR3_PMCSR325 (0x02000000uL) +#define GPIO_PMCSR3_PMCSR326 (0x04000000uL) +#define GPIO_PMCSR3_PMCSR327 (0x08000000uL) +#define GPIO_PMCSR3_PMCSR328 (0x10000000uL) +#define GPIO_PMCSR3_PMCSR329 (0x20000000uL) +#define GPIO_PMCSR3_PMCSR330 (0x40000000uL) +#define GPIO_PMCSR3_PMCSR331 (0x80000000uL) + +#define GPIO_PFCAE3_PFCAE30 (0x0001u) +#define GPIO_PFCAE3_PFCAE31 (0x0002u) +#define GPIO_PFCAE3_PFCAE32 (0x0004u) +#define GPIO_PFCAE3_PFCAE33 (0x0008u) +#define GPIO_PFCAE3_PFCAE34 (0x0010u) +#define GPIO_PFCAE3_PFCAE35 (0x0020u) +#define GPIO_PFCAE3_PFCAE36 (0x0040u) +#define GPIO_PFCAE3_PFCAE37 (0x0080u) +#define GPIO_PFCAE3_PFCAE38 (0x0100u) +#define GPIO_PFCAE3_PFCAE39 (0x0200u) +#define GPIO_PFCAE3_PFCAE310 (0x0400u) +#define GPIO_PFCAE3_PFCAE311 (0x0800u) +#define GPIO_PFCAE3_PFCAE312 (0x1000u) +#define GPIO_PFCAE3_PFCAE313 (0x2000u) +#define GPIO_PFCAE3_PFCAE314 (0x4000u) +#define GPIO_PFCAE3_PFCAE315 (0x8000u) + +#define GPIO_PIBC3_PIBC30 (0x0001u) +#define GPIO_PIBC3_PIBC31 (0x0002u) +#define GPIO_PIBC3_PIBC32 (0x0004u) +#define GPIO_PIBC3_PIBC33 (0x0008u) +#define GPIO_PIBC3_PIBC34 (0x0010u) +#define GPIO_PIBC3_PIBC35 (0x0020u) +#define GPIO_PIBC3_PIBC36 (0x0040u) +#define GPIO_PIBC3_PIBC37 (0x0080u) +#define GPIO_PIBC3_PIBC38 (0x0100u) +#define GPIO_PIBC3_PIBC39 (0x0200u) +#define GPIO_PIBC3_PIBC310 (0x0400u) +#define GPIO_PIBC3_PIBC311 (0x0800u) +#define GPIO_PIBC3_PIBC312 (0x1000u) +#define GPIO_PIBC3_PIBC313 (0x2000u) +#define GPIO_PIBC3_PIBC314 (0x4000u) +#define GPIO_PIBC3_PIBC315 (0x8000u) + +#define GPIO_PBDC3_PBDC30 (0x0001u) +#define GPIO_PBDC3_PBDC31 (0x0002u) +#define GPIO_PBDC3_PBDC32 (0x0004u) +#define GPIO_PBDC3_PBDC33 (0x0008u) +#define GPIO_PBDC3_PBDC34 (0x0010u) +#define GPIO_PBDC3_PBDC35 (0x0020u) +#define GPIO_PBDC3_PBDC36 (0x0040u) +#define GPIO_PBDC3_PBDC37 (0x0080u) +#define GPIO_PBDC3_PBDC38 (0x0100u) +#define GPIO_PBDC3_PBDC39 (0x0200u) +#define GPIO_PBDC3_PBDC310 (0x0400u) +#define GPIO_PBDC3_PBDC311 (0x0800u) +#define GPIO_PBDC3_PBDC312 (0x1000u) +#define GPIO_PBDC3_PBDC313 (0x2000u) +#define GPIO_PBDC3_PBDC314 (0x4000u) +#define GPIO_PBDC3_PBDC315 (0x8000u) + +#define GPIO_PIPC3_PIPC30 (0x0001u) +#define GPIO_PIPC3_PIPC31 (0x0002u) +#define GPIO_PIPC3_PIPC32 (0x0004u) +#define GPIO_PIPC3_PIPC33 (0x0008u) +#define GPIO_PIPC3_PIPC34 (0x0010u) +#define GPIO_PIPC3_PIPC35 (0x0020u) +#define GPIO_PIPC3_PIPC36 (0x0040u) +#define GPIO_PIPC3_PIPC37 (0x0080u) +#define GPIO_PIPC3_PIPC38 (0x0100u) +#define GPIO_PIPC3_PIPC39 (0x0200u) +#define GPIO_PIPC3_PIPC310 (0x0400u) +#define GPIO_PIPC3_PIPC311 (0x0800u) +#define GPIO_PIPC3_PIPC312 (0x1000u) +#define GPIO_PIPC3_PIPC313 (0x2000u) +#define GPIO_PIPC3_PIPC314 (0x4000u) +#define GPIO_PIPC3_PIPC315 (0x8000u) + +/* ---- P4 ---- */ +#define GPIO_P4_P40 (0x0001u) +#define GPIO_P4_P41 (0x0002u) +#define GPIO_P4_P42 (0x0004u) +#define GPIO_P4_P43 (0x0008u) +#define GPIO_P4_P44 (0x0010u) +#define GPIO_P4_P45 (0x0020u) +#define GPIO_P4_P46 (0x0040u) +#define GPIO_P4_P47 (0x0080u) +#define GPIO_P4_P48 (0x0100u) +#define GPIO_P4_P49 (0x0200u) +#define GPIO_P4_P410 (0x0400u) +#define GPIO_P4_P411 (0x0800u) +#define GPIO_P4_P412 (0x1000u) +#define GPIO_P4_P413 (0x2000u) +#define GPIO_P4_P414 (0x4000u) +#define GPIO_P4_P415 (0x8000u) + +#define GPIO_PSR4_PSR40 (0x00000001uL) +#define GPIO_PSR4_PSR41 (0x00000002uL) +#define GPIO_PSR4_PSR42 (0x00000004uL) +#define GPIO_PSR4_PSR43 (0x00000008uL) +#define GPIO_PSR4_PSR44 (0x00000010uL) +#define GPIO_PSR4_PSR45 (0x00000020uL) +#define GPIO_PSR4_PSR46 (0x00000040uL) +#define GPIO_PSR4_PSR47 (0x00000080uL) +#define GPIO_PSR4_PSR48 (0x00000100uL) +#define GPIO_PSR4_PSR49 (0x00000200uL) +#define GPIO_PSR4_PSR410 (0x00000400uL) +#define GPIO_PSR4_PSR411 (0x00000800uL) +#define GPIO_PSR4_PSR412 (0x00001000uL) +#define GPIO_PSR4_PSR413 (0x00002000uL) +#define GPIO_PSR4_PSR414 (0x00004000uL) +#define GPIO_PSR4_PSR415 (0x00008000uL) +#define GPIO_PSR4_PSR416 (0x00010000uL) +#define GPIO_PSR4_PSR417 (0x00020000uL) +#define GPIO_PSR4_PSR418 (0x00040000uL) +#define GPIO_PSR4_PSR419 (0x00080000uL) +#define GPIO_PSR4_PSR420 (0x00100000uL) +#define GPIO_PSR4_PSR421 (0x00200000uL) +#define GPIO_PSR4_PSR422 (0x00400000uL) +#define GPIO_PSR4_PSR423 (0x00800000uL) +#define GPIO_PSR4_PSR424 (0x01000000uL) +#define GPIO_PSR4_PSR425 (0x02000000uL) +#define GPIO_PSR4_PSR426 (0x04000000uL) +#define GPIO_PSR4_PSR427 (0x08000000uL) +#define GPIO_PSR4_PSR428 (0x10000000uL) +#define GPIO_PSR4_PSR429 (0x20000000uL) +#define GPIO_PSR4_PSR430 (0x40000000uL) +#define GPIO_PSR4_PSR431 (0x80000000uL) + +#define GPIO_PPR4_PPR40 (0x0001u) +#define GPIO_PPR4_PPR41 (0x0002u) +#define GPIO_PPR4_PPR42 (0x0004u) +#define GPIO_PPR4_PPR43 (0x0008u) +#define GPIO_PPR4_PPR44 (0x0010u) +#define GPIO_PPR4_PPR45 (0x0020u) +#define GPIO_PPR4_PPR46 (0x0040u) +#define GPIO_PPR4_PPR47 (0x0080u) +#define GPIO_PPR4_PPR48 (0x0100u) +#define GPIO_PPR4_PPR49 (0x0200u) +#define GPIO_PPR4_PPR410 (0x0400u) +#define GPIO_PPR4_PPR411 (0x0800u) +#define GPIO_PPR4_PPR412 (0x1000u) +#define GPIO_PPR4_PPR413 (0x2000u) +#define GPIO_PPR4_PPR414 (0x4000u) +#define GPIO_PPR4_PPR415 (0x8000u) + +#define GPIO_PM4_PM40 (0x0001u) +#define GPIO_PM4_PM41 (0x0002u) +#define GPIO_PM4_PM42 (0x0004u) +#define GPIO_PM4_PM43 (0x0008u) +#define GPIO_PM4_PM44 (0x0010u) +#define GPIO_PM4_PM45 (0x0020u) +#define GPIO_PM4_PM46 (0x0040u) +#define GPIO_PM4_PM47 (0x0080u) +#define GPIO_PM4_PM48 (0x0100u) +#define GPIO_PM4_PM49 (0x0200u) +#define GPIO_PM4_PM410 (0x0400u) +#define GPIO_PM4_PM411 (0x0800u) +#define GPIO_PM4_PM412 (0x1000u) +#define GPIO_PM4_PM413 (0x2000u) +#define GPIO_PM4_PM414 (0x4000u) +#define GPIO_PM4_PM415 (0x8000u) + +#define GPIO_PMC4_PMC40 (0x0001u) +#define GPIO_PMC4_PMC41 (0x0002u) +#define GPIO_PMC4_PMC42 (0x0004u) +#define GPIO_PMC4_PMC43 (0x0008u) +#define GPIO_PMC4_PMC44 (0x0010u) +#define GPIO_PMC4_PMC45 (0x0020u) +#define GPIO_PMC4_PMC46 (0x0040u) +#define GPIO_PMC4_PMC47 (0x0080u) +#define GPIO_PMC4_PMC48 (0x0100u) +#define GPIO_PMC4_PMC49 (0x0200u) +#define GPIO_PMC4_PMC410 (0x0400u) +#define GPIO_PMC4_PMC411 (0x0800u) +#define GPIO_PMC4_PMC412 (0x1000u) +#define GPIO_PMC4_PMC413 (0x2000u) +#define GPIO_PMC4_PMC414 (0x4000u) +#define GPIO_PMC4_PMC415 (0x8000u) + +#define GPIO_PFC4_PFC40 (0x0001u) +#define GPIO_PFC4_PFC41 (0x0002u) +#define GPIO_PFC4_PFC42 (0x0004u) +#define GPIO_PFC4_PFC43 (0x0008u) +#define GPIO_PFC4_PFC44 (0x0010u) +#define GPIO_PFC4_PFC45 (0x0020u) +#define GPIO_PFC4_PFC46 (0x0040u) +#define GPIO_PFC4_PFC47 (0x0080u) +#define GPIO_PFC4_PFC48 (0x0100u) +#define GPIO_PFC4_PFC49 (0x0200u) +#define GPIO_PFC4_PFC410 (0x0400u) +#define GPIO_PFC4_PFC411 (0x0800u) +#define GPIO_PFC4_PFC412 (0x1000u) +#define GPIO_PFC4_PFC413 (0x2000u) +#define GPIO_PFC4_PFC414 (0x4000u) +#define GPIO_PFC4_PFC415 (0x8000u) + +#define GPIO_PFCE4_PFCE40 (0x0001u) +#define GPIO_PFCE4_PFCE41 (0x0002u) +#define GPIO_PFCE4_PFCE42 (0x0004u) +#define GPIO_PFCE4_PFCE43 (0x0008u) +#define GPIO_PFCE4_PFCE44 (0x0010u) +#define GPIO_PFCE4_PFCE45 (0x0020u) +#define GPIO_PFCE4_PFCE46 (0x0040u) +#define GPIO_PFCE4_PFCE47 (0x0080u) +#define GPIO_PFCE4_PFCE48 (0x0100u) +#define GPIO_PFCE4_PFCE49 (0x0200u) +#define GPIO_PFCE4_PFCE410 (0x0400u) +#define GPIO_PFCE4_PFCE411 (0x0800u) +#define GPIO_PFCE4_PFCE412 (0x1000u) +#define GPIO_PFCE4_PFCE413 (0x2000u) +#define GPIO_PFCE4_PFCE414 (0x4000u) +#define GPIO_PFCE4_PFCE415 (0x8000u) + +#define GPIO_PNOT4_PNOT40 (0x0001u) +#define GPIO_PNOT4_PNOT41 (0x0002u) +#define GPIO_PNOT4_PNOT42 (0x0004u) +#define GPIO_PNOT4_PNOT43 (0x0008u) +#define GPIO_PNOT4_PNOT44 (0x0010u) +#define GPIO_PNOT4_PNOT45 (0x0020u) +#define GPIO_PNOT4_PNOT46 (0x0040u) +#define GPIO_PNOT4_PNOT47 (0x0080u) +#define GPIO_PNOT4_PNOT48 (0x0100u) +#define GPIO_PNOT4_PNOT49 (0x0200u) +#define GPIO_PNOT4_PNOT410 (0x0400u) +#define GPIO_PNOT4_PNOT411 (0x0800u) +#define GPIO_PNOT4_PNOT412 (0x1000u) +#define GPIO_PNOT4_PNOT413 (0x2000u) +#define GPIO_PNOT4_PNOT414 (0x4000u) +#define GPIO_PNOT4_PNOT415 (0x8000u) + +#define GPIO_PMSR4_PMSR40 (0x00000001uL) +#define GPIO_PMSR4_PMSR41 (0x00000002uL) +#define GPIO_PMSR4_PMSR42 (0x00000004uL) +#define GPIO_PMSR4_PMSR43 (0x00000008uL) +#define GPIO_PMSR4_PMSR44 (0x00000010uL) +#define GPIO_PMSR4_PMSR45 (0x00000020uL) +#define GPIO_PMSR4_PMSR46 (0x00000040uL) +#define GPIO_PMSR4_PMSR47 (0x00000080uL) +#define GPIO_PMSR4_PMSR48 (0x00000100uL) +#define GPIO_PMSR4_PMSR49 (0x00000200uL) +#define GPIO_PMSR4_PMSR410 (0x00000400uL) +#define GPIO_PMSR4_PMSR411 (0x00000800uL) +#define GPIO_PMSR4_PMSR412 (0x00001000uL) +#define GPIO_PMSR4_PMSR413 (0x00002000uL) +#define GPIO_PMSR4_PMSR414 (0x00004000uL) +#define GPIO_PMSR4_PMSR415 (0x00008000uL) +#define GPIO_PMSR4_PMSR416 (0x00010000uL) +#define GPIO_PMSR4_PMSR417 (0x00020000uL) +#define GPIO_PMSR4_PMSR418 (0x00040000uL) +#define GPIO_PMSR4_PMSR419 (0x00080000uL) +#define GPIO_PMSR4_PMSR420 (0x00100000uL) +#define GPIO_PMSR4_PMSR421 (0x00200000uL) +#define GPIO_PMSR4_PMSR422 (0x00400000uL) +#define GPIO_PMSR4_PMSR423 (0x00800000uL) +#define GPIO_PMSR4_PMSR424 (0x01000000uL) +#define GPIO_PMSR4_PMSR425 (0x02000000uL) +#define GPIO_PMSR4_PMSR426 (0x04000000uL) +#define GPIO_PMSR4_PMSR427 (0x08000000uL) +#define GPIO_PMSR4_PMSR428 (0x10000000uL) +#define GPIO_PMSR4_PMSR429 (0x20000000uL) +#define GPIO_PMSR4_PMSR430 (0x40000000uL) +#define GPIO_PMSR4_PMSR431 (0x80000000uL) + +#define GPIO_PMCSR4_PMCSR40 (0x00000001uL) +#define GPIO_PMCSR4_PMCSR41 (0x00000002uL) +#define GPIO_PMCSR4_PMCSR42 (0x00000004uL) +#define GPIO_PMCSR4_PMCSR43 (0x00000008uL) +#define GPIO_PMCSR4_PMCSR44 (0x00000010uL) +#define GPIO_PMCSR4_PMCSR45 (0x00000020uL) +#define GPIO_PMCSR4_PMCSR46 (0x00000040uL) +#define GPIO_PMCSR4_PMCSR47 (0x00000080uL) +#define GPIO_PMCSR4_PMCSR48 (0x00000100uL) +#define GPIO_PMCSR4_PMCSR49 (0x00000200uL) +#define GPIO_PMCSR4_PMCSR410 (0x00000400uL) +#define GPIO_PMCSR4_PMCSR411 (0x00000800uL) +#define GPIO_PMCSR4_PMCSR412 (0x00001000uL) +#define GPIO_PMCSR4_PMCSR413 (0x00002000uL) +#define GPIO_PMCSR4_PMCSR414 (0x00004000uL) +#define GPIO_PMCSR4_PMCSR415 (0x00008000uL) +#define GPIO_PMCSR4_PMCSR416 (0x00010000uL) +#define GPIO_PMCSR4_PMCSR417 (0x00020000uL) +#define GPIO_PMCSR4_PMCSR418 (0x00040000uL) +#define GPIO_PMCSR4_PMCSR419 (0x00080000uL) +#define GPIO_PMCSR4_PMCSR420 (0x00100000uL) +#define GPIO_PMCSR4_PMCSR421 (0x00200000uL) +#define GPIO_PMCSR4_PMCSR422 (0x00400000uL) +#define GPIO_PMCSR4_PMCSR423 (0x00800000uL) +#define GPIO_PMCSR4_PMCSR424 (0x01000000uL) +#define GPIO_PMCSR4_PMCSR425 (0x02000000uL) +#define GPIO_PMCSR4_PMCSR426 (0x04000000uL) +#define GPIO_PMCSR4_PMCSR427 (0x08000000uL) +#define GPIO_PMCSR4_PMCSR428 (0x10000000uL) +#define GPIO_PMCSR4_PMCSR429 (0x20000000uL) +#define GPIO_PMCSR4_PMCSR430 (0x40000000uL) +#define GPIO_PMCSR4_PMCSR431 (0x80000000uL) + +#define GPIO_PFCAE4_PFCAE40 (0x0001u) +#define GPIO_PFCAE4_PFCAE41 (0x0002u) +#define GPIO_PFCAE4_PFCAE42 (0x0004u) +#define GPIO_PFCAE4_PFCAE43 (0x0008u) +#define GPIO_PFCAE4_PFCAE44 (0x0010u) +#define GPIO_PFCAE4_PFCAE45 (0x0020u) +#define GPIO_PFCAE4_PFCAE46 (0x0040u) +#define GPIO_PFCAE4_PFCAE47 (0x0080u) +#define GPIO_PFCAE4_PFCAE48 (0x0100u) +#define GPIO_PFCAE4_PFCAE49 (0x0200u) +#define GPIO_PFCAE4_PFCAE410 (0x0400u) +#define GPIO_PFCAE4_PFCAE411 (0x0800u) +#define GPIO_PFCAE4_PFCAE412 (0x1000u) +#define GPIO_PFCAE4_PFCAE413 (0x2000u) +#define GPIO_PFCAE4_PFCAE414 (0x4000u) +#define GPIO_PFCAE4_PFCAE415 (0x8000u) + +#define GPIO_PIBC4_PIBC40 (0x0001u) +#define GPIO_PIBC4_PIBC41 (0x0002u) +#define GPIO_PIBC4_PIBC42 (0x0004u) +#define GPIO_PIBC4_PIBC43 (0x0008u) +#define GPIO_PIBC4_PIBC44 (0x0010u) +#define GPIO_PIBC4_PIBC45 (0x0020u) +#define GPIO_PIBC4_PIBC46 (0x0040u) +#define GPIO_PIBC4_PIBC47 (0x0080u) +#define GPIO_PIBC4_PIBC48 (0x0100u) +#define GPIO_PIBC4_PIBC49 (0x0200u) +#define GPIO_PIBC4_PIBC410 (0x0400u) +#define GPIO_PIBC4_PIBC411 (0x0800u) +#define GPIO_PIBC4_PIBC412 (0x1000u) +#define GPIO_PIBC4_PIBC413 (0x2000u) +#define GPIO_PIBC4_PIBC414 (0x4000u) +#define GPIO_PIBC4_PIBC415 (0x8000u) + +#define GPIO_PBDC4_PBDC40 (0x0001u) +#define GPIO_PBDC4_PBDC41 (0x0002u) +#define GPIO_PBDC4_PBDC42 (0x0004u) +#define GPIO_PBDC4_PBDC43 (0x0008u) +#define GPIO_PBDC4_PBDC44 (0x0010u) +#define GPIO_PBDC4_PBDC45 (0x0020u) +#define GPIO_PBDC4_PBDC46 (0x0040u) +#define GPIO_PBDC4_PBDC47 (0x0080u) +#define GPIO_PBDC4_PBDC48 (0x0100u) +#define GPIO_PBDC4_PBDC49 (0x0200u) +#define GPIO_PBDC4_PBDC410 (0x0400u) +#define GPIO_PBDC4_PBDC411 (0x0800u) +#define GPIO_PBDC4_PBDC412 (0x1000u) +#define GPIO_PBDC4_PBDC413 (0x2000u) +#define GPIO_PBDC4_PBDC414 (0x4000u) +#define GPIO_PBDC4_PBDC415 (0x8000u) + +#define GPIO_PIPC4_PIPC40 (0x0001u) +#define GPIO_PIPC4_PIPC41 (0x0002u) +#define GPIO_PIPC4_PIPC42 (0x0004u) +#define GPIO_PIPC4_PIPC43 (0x0008u) +#define GPIO_PIPC4_PIPC44 (0x0010u) +#define GPIO_PIPC4_PIPC45 (0x0020u) +#define GPIO_PIPC4_PIPC46 (0x0040u) +#define GPIO_PIPC4_PIPC47 (0x0080u) +#define GPIO_PIPC4_PIPC48 (0x0100u) +#define GPIO_PIPC4_PIPC49 (0x0200u) +#define GPIO_PIPC4_PIPC410 (0x0400u) +#define GPIO_PIPC4_PIPC411 (0x0800u) +#define GPIO_PIPC4_PIPC412 (0x1000u) +#define GPIO_PIPC4_PIPC413 (0x2000u) +#define GPIO_PIPC4_PIPC414 (0x4000u) +#define GPIO_PIPC4_PIPC415 (0x8000u) + +/* ---- P5 ---- */ +#define GPIO_P5_P50 (0x0001u) +#define GPIO_P5_P51 (0x0002u) +#define GPIO_P5_P52 (0x0004u) +#define GPIO_P5_P53 (0x0008u) +#define GPIO_P5_P54 (0x0010u) +#define GPIO_P5_P55 (0x0020u) +#define GPIO_P5_P56 (0x0040u) +#define GPIO_P5_P57 (0x0080u) +#define GPIO_P5_P58 (0x0100u) +#define GPIO_P5_P59 (0x0200u) +#define GPIO_P5_P510 (0x0400u) + +#define GPIO_PSR5_PSR50 (0x00000001uL) +#define GPIO_PSR5_PSR51 (0x00000002uL) +#define GPIO_PSR5_PSR52 (0x00000004uL) +#define GPIO_PSR5_PSR53 (0x00000008uL) +#define GPIO_PSR5_PSR54 (0x00000010uL) +#define GPIO_PSR5_PSR55 (0x00000020uL) +#define GPIO_PSR5_PSR56 (0x00000040uL) +#define GPIO_PSR5_PSR57 (0x00000080uL) +#define GPIO_PSR5_PSR58 (0x00000100uL) +#define GPIO_PSR5_PSR59 (0x00000200uL) +#define GPIO_PSR5_PSR510 (0x00000400uL) +#define GPIO_PSR5_PSR516 (0x00010000uL) +#define GPIO_PSR5_PSR517 (0x00020000uL) +#define GPIO_PSR5_PSR518 (0x00040000uL) +#define GPIO_PSR5_PSR519 (0x00080000uL) +#define GPIO_PSR5_PSR520 (0x00100000uL) +#define GPIO_PSR5_PSR521 (0x00200000uL) +#define GPIO_PSR5_PSR522 (0x00400000uL) +#define GPIO_PSR5_PSR523 (0x00800000uL) +#define GPIO_PSR5_PSR524 (0x01000000uL) +#define GPIO_PSR5_PSR525 (0x02000000uL) +#define GPIO_PSR5_PSR526 (0x04000000uL) + +#define GPIO_PPR5_PPR50 (0x0001u) +#define GPIO_PPR5_PPR51 (0x0002u) +#define GPIO_PPR5_PPR52 (0x0004u) +#define GPIO_PPR5_PPR53 (0x0008u) +#define GPIO_PPR5_PPR54 (0x0010u) +#define GPIO_PPR5_PPR55 (0x0020u) +#define GPIO_PPR5_PPR56 (0x0040u) +#define GPIO_PPR5_PPR57 (0x0080u) +#define GPIO_PPR5_PPR58 (0x0100u) +#define GPIO_PPR5_PPR59 (0x0200u) +#define GPIO_PPR5_PPR510 (0x0400u) + +#define GPIO_PM5_PM50 (0x0001u) +#define GPIO_PM5_PM51 (0x0002u) +#define GPIO_PM5_PM52 (0x0004u) +#define GPIO_PM5_PM53 (0x0008u) +#define GPIO_PM5_PM54 (0x0010u) +#define GPIO_PM5_PM55 (0x0020u) +#define GPIO_PM5_PM56 (0x0040u) +#define GPIO_PM5_PM57 (0x0080u) +#define GPIO_PM5_PM58 (0x0100u) +#define GPIO_PM5_PM59 (0x0200u) +#define GPIO_PM5_PM510 (0x0400u) + +#define GPIO_PMC5_PMC50 (0x0001u) +#define GPIO_PMC5_PMC51 (0x0002u) +#define GPIO_PMC5_PMC52 (0x0004u) +#define GPIO_PMC5_PMC53 (0x0008u) +#define GPIO_PMC5_PMC54 (0x0010u) +#define GPIO_PMC5_PMC55 (0x0020u) +#define GPIO_PMC5_PMC56 (0x0040u) +#define GPIO_PMC5_PMC57 (0x0080u) +#define GPIO_PMC5_PMC58 (0x0100u) +#define GPIO_PMC5_PMC59 (0x0200u) +#define GPIO_PMC5_PMC510 (0x0400u) + +#define GPIO_PFC5_PFC50 (0x0001u) +#define GPIO_PFC5_PFC51 (0x0002u) +#define GPIO_PFC5_PFC52 (0x0004u) +#define GPIO_PFC5_PFC53 (0x0008u) +#define GPIO_PFC5_PFC54 (0x0010u) +#define GPIO_PFC5_PFC55 (0x0020u) +#define GPIO_PFC5_PFC56 (0x0040u) +#define GPIO_PFC5_PFC57 (0x0080u) +#define GPIO_PFC5_PFC58 (0x0100u) +#define GPIO_PFC5_PFC59 (0x0200u) +#define GPIO_PFC5_PFC510 (0x0400u) + +#define GPIO_PFCE5_PFCE50 (0x0001u) +#define GPIO_PFCE5_PFCE51 (0x0002u) +#define GPIO_PFCE5_PFCE52 (0x0004u) +#define GPIO_PFCE5_PFCE53 (0x0008u) +#define GPIO_PFCE5_PFCE54 (0x0010u) +#define GPIO_PFCE5_PFCE55 (0x0020u) +#define GPIO_PFCE5_PFCE56 (0x0040u) +#define GPIO_PFCE5_PFCE57 (0x0080u) +#define GPIO_PFCE5_PFCE58 (0x0100u) +#define GPIO_PFCE5_PFCE59 (0x0200u) +#define GPIO_PFCE5_PFCE510 (0x0400u) + +#define GPIO_PNOT5_PNOT50 (0x0001u) +#define GPIO_PNOT5_PNOT51 (0x0002u) +#define GPIO_PNOT5_PNOT52 (0x0004u) +#define GPIO_PNOT5_PNOT53 (0x0008u) +#define GPIO_PNOT5_PNOT54 (0x0010u) +#define GPIO_PNOT5_PNOT55 (0x0020u) +#define GPIO_PNOT5_PNOT56 (0x0040u) +#define GPIO_PNOT5_PNOT57 (0x0080u) +#define GPIO_PNOT5_PNOT58 (0x0100u) +#define GPIO_PNOT5_PNOT59 (0x0200u) +#define GPIO_PNOT5_PNOT510 (0x0400u) + +#define GPIO_PMSR5_PMSR50 (0x00000001uL) +#define GPIO_PMSR5_PMSR51 (0x00000002uL) +#define GPIO_PMSR5_PMSR52 (0x00000004uL) +#define GPIO_PMSR5_PMSR53 (0x00000008uL) +#define GPIO_PMSR5_PMSR54 (0x00000010uL) +#define GPIO_PMSR5_PMSR55 (0x00000020uL) +#define GPIO_PMSR5_PMSR56 (0x00000040uL) +#define GPIO_PMSR5_PMSR57 (0x00000080uL) +#define GPIO_PMSR5_PMSR58 (0x00000100uL) +#define GPIO_PMSR5_PMSR59 (0x00000200uL) +#define GPIO_PMSR5_PMSR510 (0x00000400uL) +#define GPIO_PMSR5_PMSR516 (0x00010000uL) +#define GPIO_PMSR5_PMSR517 (0x00020000uL) +#define GPIO_PMSR5_PMSR518 (0x00040000uL) +#define GPIO_PMSR5_PMSR519 (0x00080000uL) +#define GPIO_PMSR5_PMSR520 (0x00100000uL) +#define GPIO_PMSR5_PMSR521 (0x00200000uL) +#define GPIO_PMSR5_PMSR522 (0x00400000uL) +#define GPIO_PMSR5_PMSR523 (0x00800000uL) +#define GPIO_PMSR5_PMSR524 (0x01000000uL) +#define GPIO_PMSR5_PMSR525 (0x02000000uL) +#define GPIO_PMSR5_PMSR526 (0x04000000uL) + +#define GPIO_PMCSR5_PMCSR50 (0x00000001uL) +#define GPIO_PMCSR5_PMCSR51 (0x00000002uL) +#define GPIO_PMCSR5_PMCSR52 (0x00000004uL) +#define GPIO_PMCSR5_PMCSR53 (0x00000008uL) +#define GPIO_PMCSR5_PMCSR54 (0x00000010uL) +#define GPIO_PMCSR5_PMCSR55 (0x00000020uL) +#define GPIO_PMCSR5_PMCSR56 (0x00000040uL) +#define GPIO_PMCSR5_PMCSR57 (0x00000080uL) +#define GPIO_PMCSR5_PMCSR58 (0x00000100uL) +#define GPIO_PMCSR5_PMCSR59 (0x00000200uL) +#define GPIO_PMCSR5_PMCSR510 (0x00000400uL) +#define GPIO_PMCSR5_PMCSR516 (0x00010000uL) +#define GPIO_PMCSR5_PMCSR517 (0x00020000uL) +#define GPIO_PMCSR5_PMCSR518 (0x00040000uL) +#define GPIO_PMCSR5_PMCSR519 (0x00080000uL) +#define GPIO_PMCSR5_PMCSR520 (0x00100000uL) +#define GPIO_PMCSR5_PMCSR521 (0x00200000uL) +#define GPIO_PMCSR5_PMCSR522 (0x00400000uL) +#define GPIO_PMCSR5_PMCSR523 (0x00800000uL) +#define GPIO_PMCSR5_PMCSR524 (0x01000000uL) +#define GPIO_PMCSR5_PMCSR525 (0x02000000uL) +#define GPIO_PMCSR5_PMCSR526 (0x04000000uL) + +#define GPIO_PFCAE5_PFCAE50 (0x0001u) +#define GPIO_PFCAE5_PFCAE51 (0x0002u) +#define GPIO_PFCAE5_PFCAE52 (0x0004u) +#define GPIO_PFCAE5_PFCAE53 (0x0008u) +#define GPIO_PFCAE5_PFCAE54 (0x0010u) +#define GPIO_PFCAE5_PFCAE55 (0x0020u) +#define GPIO_PFCAE5_PFCAE56 (0x0040u) +#define GPIO_PFCAE5_PFCAE57 (0x0080u) +#define GPIO_PFCAE5_PFCAE58 (0x0100u) +#define GPIO_PFCAE5_PFCAE59 (0x0200u) +#define GPIO_PFCAE5_PFCAE510 (0x0400u) + +#define GPIO_PIBC5_PIBC50 (0x0001u) +#define GPIO_PIBC5_PIBC51 (0x0002u) +#define GPIO_PIBC5_PIBC52 (0x0004u) +#define GPIO_PIBC5_PIBC53 (0x0008u) +#define GPIO_PIBC5_PIBC54 (0x0010u) +#define GPIO_PIBC5_PIBC55 (0x0020u) +#define GPIO_PIBC5_PIBC56 (0x0040u) +#define GPIO_PIBC5_PIBC57 (0x0080u) +#define GPIO_PIBC5_PIBC58 (0x0100u) +#define GPIO_PIBC5_PIBC59 (0x0200u) +#define GPIO_PIBC5_PIBC510 (0x0400u) + +#define GPIO_PBDC5_PBDC50 (0x0001u) +#define GPIO_PBDC5_PBDC51 (0x0002u) +#define GPIO_PBDC5_PBDC52 (0x0004u) +#define GPIO_PBDC5_PBDC53 (0x0008u) +#define GPIO_PBDC5_PBDC54 (0x0010u) +#define GPIO_PBDC5_PBDC55 (0x0020u) +#define GPIO_PBDC5_PBDC56 (0x0040u) +#define GPIO_PBDC5_PBDC57 (0x0080u) +#define GPIO_PBDC5_PBDC58 (0x0100u) +#define GPIO_PBDC5_PBDC59 (0x0200u) +#define GPIO_PBDC5_PBDC510 (0x0400u) + +#define GPIO_PIPC5_PIPC50 (0x0001u) +#define GPIO_PIPC5_PIPC51 (0x0002u) +#define GPIO_PIPC5_PIPC52 (0x0004u) +#define GPIO_PIPC5_PIPC53 (0x0008u) +#define GPIO_PIPC5_PIPC54 (0x0010u) +#define GPIO_PIPC5_PIPC55 (0x0020u) +#define GPIO_PIPC5_PIPC56 (0x0040u) +#define GPIO_PIPC5_PIPC57 (0x0080u) +#define GPIO_PIPC5_PIPC58 (0x0100u) +#define GPIO_PIPC5_PIPC59 (0x0200u) +#define GPIO_PIPC5_PIPC510 (0x0400u) + +/* ---- P6 ---- */ +#define GPIO_P6_P60 (0x0001u) +#define GPIO_P6_P61 (0x0002u) +#define GPIO_P6_P62 (0x0004u) +#define GPIO_P6_P63 (0x0008u) +#define GPIO_P6_P64 (0x0010u) +#define GPIO_P6_P65 (0x0020u) +#define GPIO_P6_P66 (0x0040u) +#define GPIO_P6_P67 (0x0080u) +#define GPIO_P6_P68 (0x0100u) +#define GPIO_P6_P69 (0x0200u) +#define GPIO_P6_P610 (0x0400u) +#define GPIO_P6_P611 (0x0800u) +#define GPIO_P6_P612 (0x1000u) +#define GPIO_P6_P613 (0x2000u) +#define GPIO_P6_P614 (0x4000u) +#define GPIO_P6_P615 (0x8000u) + +#define GPIO_PSR6_PSR60 (0x00000001uL) +#define GPIO_PSR6_PSR61 (0x00000002uL) +#define GPIO_PSR6_PSR62 (0x00000004uL) +#define GPIO_PSR6_PSR63 (0x00000008uL) +#define GPIO_PSR6_PSR64 (0x00000010uL) +#define GPIO_PSR6_PSR65 (0x00000020uL) +#define GPIO_PSR6_PSR66 (0x00000040uL) +#define GPIO_PSR6_PSR67 (0x00000080uL) +#define GPIO_PSR6_PSR68 (0x00000100uL) +#define GPIO_PSR6_PSR69 (0x00000200uL) +#define GPIO_PSR6_PSR610 (0x00000400uL) +#define GPIO_PSR6_PSR611 (0x00000800uL) +#define GPIO_PSR6_PSR612 (0x00001000uL) +#define GPIO_PSR6_PSR613 (0x00002000uL) +#define GPIO_PSR6_PSR614 (0x00004000uL) +#define GPIO_PSR6_PSR615 (0x00008000uL) +#define GPIO_PSR6_PSR616 (0x00010000uL) +#define GPIO_PSR6_PSR617 (0x00020000uL) +#define GPIO_PSR6_PSR618 (0x00040000uL) +#define GPIO_PSR6_PSR619 (0x00080000uL) +#define GPIO_PSR6_PSR620 (0x00100000uL) +#define GPIO_PSR6_PSR621 (0x00200000uL) +#define GPIO_PSR6_PSR622 (0x00400000uL) +#define GPIO_PSR6_PSR623 (0x00800000uL) +#define GPIO_PSR6_PSR624 (0x01000000uL) +#define GPIO_PSR6_PSR625 (0x02000000uL) +#define GPIO_PSR6_PSR626 (0x04000000uL) +#define GPIO_PSR6_PSR627 (0x08000000uL) +#define GPIO_PSR6_PSR628 (0x10000000uL) +#define GPIO_PSR6_PSR629 (0x20000000uL) +#define GPIO_PSR6_PSR630 (0x40000000uL) +#define GPIO_PSR6_PSR631 (0x80000000uL) + +#define GPIO_PPR6_PPR60 (0x0001u) +#define GPIO_PPR6_PPR61 (0x0002u) +#define GPIO_PPR6_PPR62 (0x0004u) +#define GPIO_PPR6_PPR63 (0x0008u) +#define GPIO_PPR6_PPR64 (0x0010u) +#define GPIO_PPR6_PPR65 (0x0020u) +#define GPIO_PPR6_PPR66 (0x0040u) +#define GPIO_PPR6_PPR67 (0x0080u) +#define GPIO_PPR6_PPR68 (0x0100u) +#define GPIO_PPR6_PPR69 (0x0200u) +#define GPIO_PPR6_PPR610 (0x0400u) +#define GPIO_PPR6_PPR611 (0x0800u) +#define GPIO_PPR6_PPR612 (0x1000u) +#define GPIO_PPR6_PPR613 (0x2000u) +#define GPIO_PPR6_PPR614 (0x4000u) +#define GPIO_PPR6_PPR615 (0x8000u) + +#define GPIO_PM6_PM60 (0x0001u) +#define GPIO_PM6_PM61 (0x0002u) +#define GPIO_PM6_PM62 (0x0004u) +#define GPIO_PM6_PM63 (0x0008u) +#define GPIO_PM6_PM64 (0x0010u) +#define GPIO_PM6_PM65 (0x0020u) +#define GPIO_PM6_PM66 (0x0040u) +#define GPIO_PM6_PM67 (0x0080u) +#define GPIO_PM6_PM68 (0x0100u) +#define GPIO_PM6_PM69 (0x0200u) +#define GPIO_PM6_PM610 (0x0400u) +#define GPIO_PM6_PM611 (0x0800u) +#define GPIO_PM6_PM612 (0x1000u) +#define GPIO_PM6_PM613 (0x2000u) +#define GPIO_PM6_PM614 (0x4000u) +#define GPIO_PM6_PM615 (0x8000u) + +#define GPIO_PMC6_PMC60 (0x0001u) +#define GPIO_PMC6_PMC61 (0x0002u) +#define GPIO_PMC6_PMC62 (0x0004u) +#define GPIO_PMC6_PMC63 (0x0008u) +#define GPIO_PMC6_PMC64 (0x0010u) +#define GPIO_PMC6_PMC65 (0x0020u) +#define GPIO_PMC6_PMC66 (0x0040u) +#define GPIO_PMC6_PMC67 (0x0080u) +#define GPIO_PMC6_PMC68 (0x0100u) +#define GPIO_PMC6_PMC69 (0x0200u) +#define GPIO_PMC6_PMC610 (0x0400u) +#define GPIO_PMC6_PMC611 (0x0800u) +#define GPIO_PMC6_PMC612 (0x1000u) +#define GPIO_PMC6_PMC613 (0x2000u) +#define GPIO_PMC6_PMC614 (0x4000u) +#define GPIO_PMC6_PMC615 (0x8000u) + +#define GPIO_PFC6_PFC60 (0x0001u) +#define GPIO_PFC6_PFC61 (0x0002u) +#define GPIO_PFC6_PFC62 (0x0004u) +#define GPIO_PFC6_PFC63 (0x0008u) +#define GPIO_PFC6_PFC64 (0x0010u) +#define GPIO_PFC6_PFC65 (0x0020u) +#define GPIO_PFC6_PFC66 (0x0040u) +#define GPIO_PFC6_PFC67 (0x0080u) +#define GPIO_PFC6_PFC68 (0x0100u) +#define GPIO_PFC6_PFC69 (0x0200u) +#define GPIO_PFC6_PFC610 (0x0400u) +#define GPIO_PFC6_PFC611 (0x0800u) +#define GPIO_PFC6_PFC612 (0x1000u) +#define GPIO_PFC6_PFC613 (0x2000u) +#define GPIO_PFC6_PFC614 (0x4000u) +#define GPIO_PFC6_PFC615 (0x8000u) + +#define GPIO_PFCE6_PFCE60 (0x0001u) +#define GPIO_PFCE6_PFCE61 (0x0002u) +#define GPIO_PFCE6_PFCE62 (0x0004u) +#define GPIO_PFCE6_PFCE63 (0x0008u) +#define GPIO_PFCE6_PFCE64 (0x0010u) +#define GPIO_PFCE6_PFCE65 (0x0020u) +#define GPIO_PFCE6_PFCE66 (0x0040u) +#define GPIO_PFCE6_PFCE67 (0x0080u) +#define GPIO_PFCE6_PFCE68 (0x0100u) +#define GPIO_PFCE6_PFCE69 (0x0200u) +#define GPIO_PFCE6_PFCE610 (0x0400u) +#define GPIO_PFCE6_PFCE611 (0x0800u) +#define GPIO_PFCE6_PFCE612 (0x1000u) +#define GPIO_PFCE6_PFCE613 (0x2000u) +#define GPIO_PFCE6_PFCE614 (0x4000u) +#define GPIO_PFCE6_PFCE615 (0x8000u) + +#define GPIO_PNOT6_PNOT60 (0x0001u) +#define GPIO_PNOT6_PNOT61 (0x0002u) +#define GPIO_PNOT6_PNOT62 (0x0004u) +#define GPIO_PNOT6_PNOT63 (0x0008u) +#define GPIO_PNOT6_PNOT64 (0x0010u) +#define GPIO_PNOT6_PNOT65 (0x0020u) +#define GPIO_PNOT6_PNOT66 (0x0040u) +#define GPIO_PNOT6_PNOT67 (0x0080u) +#define GPIO_PNOT6_PNOT68 (0x0100u) +#define GPIO_PNOT6_PNOT69 (0x0200u) +#define GPIO_PNOT6_PNOT610 (0x0400u) +#define GPIO_PNOT6_PNOT611 (0x0800u) +#define GPIO_PNOT6_PNOT612 (0x1000u) +#define GPIO_PNOT6_PNOT613 (0x2000u) +#define GPIO_PNOT6_PNOT614 (0x4000u) +#define GPIO_PNOT6_PNOT615 (0x8000u) + +#define GPIO_PMSR6_PMSR60 (0x00000001uL) +#define GPIO_PMSR6_PMSR61 (0x00000002uL) +#define GPIO_PMSR6_PMSR62 (0x00000004uL) +#define GPIO_PMSR6_PMSR63 (0x00000008uL) +#define GPIO_PMSR6_PMSR64 (0x00000010uL) +#define GPIO_PMSR6_PMSR65 (0x00000020uL) +#define GPIO_PMSR6_PMSR66 (0x00000040uL) +#define GPIO_PMSR6_PMSR67 (0x00000080uL) +#define GPIO_PMSR6_PMSR68 (0x00000100uL) +#define GPIO_PMSR6_PMSR69 (0x00000200uL) +#define GPIO_PMSR6_PMSR610 (0x00000400uL) +#define GPIO_PMSR6_PMSR611 (0x00000800uL) +#define GPIO_PMSR6_PMSR612 (0x00001000uL) +#define GPIO_PMSR6_PMSR613 (0x00002000uL) +#define GPIO_PMSR6_PMSR614 (0x00004000uL) +#define GPIO_PMSR6_PMSR615 (0x00008000uL) +#define GPIO_PMSR6_PMSR616 (0x00010000uL) +#define GPIO_PMSR6_PMSR617 (0x00020000uL) +#define GPIO_PMSR6_PMSR618 (0x00040000uL) +#define GPIO_PMSR6_PMSR619 (0x00080000uL) +#define GPIO_PMSR6_PMSR620 (0x00100000uL) +#define GPIO_PMSR6_PMSR621 (0x00200000uL) +#define GPIO_PMSR6_PMSR622 (0x00400000uL) +#define GPIO_PMSR6_PMSR623 (0x00800000uL) +#define GPIO_PMSR6_PMSR624 (0x01000000uL) +#define GPIO_PMSR6_PMSR625 (0x02000000uL) +#define GPIO_PMSR6_PMSR626 (0x04000000uL) +#define GPIO_PMSR6_PMSR627 (0x08000000uL) +#define GPIO_PMSR6_PMSR628 (0x10000000uL) +#define GPIO_PMSR6_PMSR629 (0x20000000uL) +#define GPIO_PMSR6_PMSR630 (0x40000000uL) +#define GPIO_PMSR6_PMSR631 (0x80000000uL) + +#define GPIO_PMCSR6_PMCSR60 (0x00000001uL) +#define GPIO_PMCSR6_PMCSR61 (0x00000002uL) +#define GPIO_PMCSR6_PMCSR62 (0x00000004uL) +#define GPIO_PMCSR6_PMCSR63 (0x00000008uL) +#define GPIO_PMCSR6_PMCSR64 (0x00000010uL) +#define GPIO_PMCSR6_PMCSR65 (0x00000020uL) +#define GPIO_PMCSR6_PMCSR66 (0x00000040uL) +#define GPIO_PMCSR6_PMCSR67 (0x00000080uL) +#define GPIO_PMCSR6_PMCSR68 (0x00000100uL) +#define GPIO_PMCSR6_PMCSR69 (0x00000200uL) +#define GPIO_PMCSR6_PMCSR610 (0x00000400uL) +#define GPIO_PMCSR6_PMCSR611 (0x00000800uL) +#define GPIO_PMCSR6_PMCSR612 (0x00001000uL) +#define GPIO_PMCSR6_PMCSR613 (0x00002000uL) +#define GPIO_PMCSR6_PMCSR614 (0x00004000uL) +#define GPIO_PMCSR6_PMCSR615 (0x00008000uL) +#define GPIO_PMCSR6_PMCSR616 (0x00010000uL) +#define GPIO_PMCSR6_PMCSR617 (0x00020000uL) +#define GPIO_PMCSR6_PMCSR618 (0x00040000uL) +#define GPIO_PMCSR6_PMCSR619 (0x00080000uL) +#define GPIO_PMCSR6_PMCSR620 (0x00100000uL) +#define GPIO_PMCSR6_PMCSR621 (0x00200000uL) +#define GPIO_PMCSR6_PMCSR622 (0x00400000uL) +#define GPIO_PMCSR6_PMCSR623 (0x00800000uL) +#define GPIO_PMCSR6_PMCSR624 (0x01000000uL) +#define GPIO_PMCSR6_PMCSR625 (0x02000000uL) +#define GPIO_PMCSR6_PMCSR626 (0x04000000uL) +#define GPIO_PMCSR6_PMCSR627 (0x08000000uL) +#define GPIO_PMCSR6_PMCSR628 (0x10000000uL) +#define GPIO_PMCSR6_PMCSR629 (0x20000000uL) +#define GPIO_PMCSR6_PMCSR630 (0x40000000uL) +#define GPIO_PMCSR6_PMCSR631 (0x80000000uL) + +#define GPIO_PFCAE6_PFCAE60 (0x0001u) +#define GPIO_PFCAE6_PFCAE61 (0x0002u) +#define GPIO_PFCAE6_PFCAE62 (0x0004u) +#define GPIO_PFCAE6_PFCAE63 (0x0008u) +#define GPIO_PFCAE6_PFCAE64 (0x0010u) +#define GPIO_PFCAE6_PFCAE65 (0x0020u) +#define GPIO_PFCAE6_PFCAE66 (0x0040u) +#define GPIO_PFCAE6_PFCAE67 (0x0080u) +#define GPIO_PFCAE6_PFCAE68 (0x0100u) +#define GPIO_PFCAE6_PFCAE69 (0x0200u) +#define GPIO_PFCAE6_PFCAE610 (0x0400u) +#define GPIO_PFCAE6_PFCAE611 (0x0800u) +#define GPIO_PFCAE6_PFCAE612 (0x1000u) +#define GPIO_PFCAE6_PFCAE613 (0x2000u) +#define GPIO_PFCAE6_PFCAE614 (0x4000u) +#define GPIO_PFCAE6_PFCAE615 (0x8000u) + +#define GPIO_PIBC6_PIBC60 (0x0001u) +#define GPIO_PIBC6_PIBC61 (0x0002u) +#define GPIO_PIBC6_PIBC62 (0x0004u) +#define GPIO_PIBC6_PIBC63 (0x0008u) +#define GPIO_PIBC6_PIBC64 (0x0010u) +#define GPIO_PIBC6_PIBC65 (0x0020u) +#define GPIO_PIBC6_PIBC66 (0x0040u) +#define GPIO_PIBC6_PIBC67 (0x0080u) +#define GPIO_PIBC6_PIBC68 (0x0100u) +#define GPIO_PIBC6_PIBC69 (0x0200u) +#define GPIO_PIBC6_PIBC610 (0x0400u) +#define GPIO_PIBC6_PIBC611 (0x0800u) +#define GPIO_PIBC6_PIBC612 (0x1000u) +#define GPIO_PIBC6_PIBC613 (0x2000u) +#define GPIO_PIBC6_PIBC614 (0x4000u) +#define GPIO_PIBC6_PIBC615 (0x8000u) + +#define GPIO_PBDC6_PBDC60 (0x0001u) +#define GPIO_PBDC6_PBDC61 (0x0002u) +#define GPIO_PBDC6_PBDC62 (0x0004u) +#define GPIO_PBDC6_PBDC63 (0x0008u) +#define GPIO_PBDC6_PBDC64 (0x0010u) +#define GPIO_PBDC6_PBDC65 (0x0020u) +#define GPIO_PBDC6_PBDC66 (0x0040u) +#define GPIO_PBDC6_PBDC67 (0x0080u) +#define GPIO_PBDC6_PBDC68 (0x0100u) +#define GPIO_PBDC6_PBDC69 (0x0200u) +#define GPIO_PBDC6_PBDC610 (0x0400u) +#define GPIO_PBDC6_PBDC611 (0x0800u) +#define GPIO_PBDC6_PBDC612 (0x1000u) +#define GPIO_PBDC6_PBDC613 (0x2000u) +#define GPIO_PBDC6_PBDC614 (0x4000u) +#define GPIO_PBDC6_PBDC615 (0x8000u) + +#define GPIO_PIPC6_PIPC60 (0x0001u) +#define GPIO_PIPC6_PIPC61 (0x0002u) +#define GPIO_PIPC6_PIPC62 (0x0004u) +#define GPIO_PIPC6_PIPC63 (0x0008u) +#define GPIO_PIPC6_PIPC64 (0x0010u) +#define GPIO_PIPC6_PIPC65 (0x0020u) +#define GPIO_PIPC6_PIPC66 (0x0040u) +#define GPIO_PIPC6_PIPC67 (0x0080u) +#define GPIO_PIPC6_PIPC68 (0x0100u) +#define GPIO_PIPC6_PIPC69 (0x0200u) +#define GPIO_PIPC6_PIPC610 (0x0400u) +#define GPIO_PIPC6_PIPC611 (0x0800u) +#define GPIO_PIPC6_PIPC612 (0x1000u) +#define GPIO_PIPC6_PIPC613 (0x2000u) +#define GPIO_PIPC6_PIPC614 (0x4000u) +#define GPIO_PIPC6_PIPC615 (0x8000u) + +/* ---- P7 ---- */ +#define GPIO_P7_P70 (0x0001u) +#define GPIO_P7_P71 (0x0002u) +#define GPIO_P7_P72 (0x0004u) +#define GPIO_P7_P73 (0x0008u) +#define GPIO_P7_P74 (0x0010u) +#define GPIO_P7_P75 (0x0020u) +#define GPIO_P7_P76 (0x0040u) +#define GPIO_P7_P77 (0x0080u) +#define GPIO_P7_P78 (0x0100u) +#define GPIO_P7_P79 (0x0200u) +#define GPIO_P7_P710 (0x0400u) +#define GPIO_P7_P711 (0x0800u) +#define GPIO_P7_P712 (0x1000u) +#define GPIO_P7_P713 (0x2000u) +#define GPIO_P7_P714 (0x4000u) +#define GPIO_P7_P715 (0x8000u) + +#define GPIO_PSR7_PSR70 (0x00000001uL) +#define GPIO_PSR7_PSR71 (0x00000002uL) +#define GPIO_PSR7_PSR72 (0x00000004uL) +#define GPIO_PSR7_PSR73 (0x00000008uL) +#define GPIO_PSR7_PSR74 (0x00000010uL) +#define GPIO_PSR7_PSR75 (0x00000020uL) +#define GPIO_PSR7_PSR76 (0x00000040uL) +#define GPIO_PSR7_PSR77 (0x00000080uL) +#define GPIO_PSR7_PSR78 (0x00000100uL) +#define GPIO_PSR7_PSR79 (0x00000200uL) +#define GPIO_PSR7_PSR710 (0x00000400uL) +#define GPIO_PSR7_PSR711 (0x00000800uL) +#define GPIO_PSR7_PSR712 (0x00001000uL) +#define GPIO_PSR7_PSR713 (0x00002000uL) +#define GPIO_PSR7_PSR714 (0x00004000uL) +#define GPIO_PSR7_PSR715 (0x00008000uL) +#define GPIO_PSR7_PSR716 (0x00010000uL) +#define GPIO_PSR7_PSR717 (0x00020000uL) +#define GPIO_PSR7_PSR718 (0x00040000uL) +#define GPIO_PSR7_PSR719 (0x00080000uL) +#define GPIO_PSR7_PSR720 (0x00100000uL) +#define GPIO_PSR7_PSR721 (0x00200000uL) +#define GPIO_PSR7_PSR722 (0x00400000uL) +#define GPIO_PSR7_PSR723 (0x00800000uL) +#define GPIO_PSR7_PSR724 (0x01000000uL) +#define GPIO_PSR7_PSR725 (0x02000000uL) +#define GPIO_PSR7_PSR726 (0x04000000uL) +#define GPIO_PSR7_PSR727 (0x08000000uL) +#define GPIO_PSR7_PSR728 (0x10000000uL) +#define GPIO_PSR7_PSR729 (0x20000000uL) +#define GPIO_PSR7_PSR730 (0x40000000uL) +#define GPIO_PSR7_PSR731 (0x80000000uL) + +#define GPIO_PPR7_PPR70 (0x0001u) +#define GPIO_PPR7_PPR71 (0x0002u) +#define GPIO_PPR7_PPR72 (0x0004u) +#define GPIO_PPR7_PPR73 (0x0008u) +#define GPIO_PPR7_PPR74 (0x0010u) +#define GPIO_PPR7_PPR75 (0x0020u) +#define GPIO_PPR7_PPR76 (0x0040u) +#define GPIO_PPR7_PPR77 (0x0080u) +#define GPIO_PPR7_PPR78 (0x0100u) +#define GPIO_PPR7_PPR79 (0x0200u) +#define GPIO_PPR7_PPR710 (0x0400u) +#define GPIO_PPR7_PPR711 (0x0800u) +#define GPIO_PPR7_PPR712 (0x1000u) +#define GPIO_PPR7_PPR713 (0x2000u) +#define GPIO_PPR7_PPR714 (0x4000u) +#define GPIO_PPR7_PPR715 (0x8000u) + +#define GPIO_PM7_PM70 (0x0001u) +#define GPIO_PM7_PM71 (0x0002u) +#define GPIO_PM7_PM72 (0x0004u) +#define GPIO_PM7_PM73 (0x0008u) +#define GPIO_PM7_PM74 (0x0010u) +#define GPIO_PM7_PM75 (0x0020u) +#define GPIO_PM7_PM76 (0x0040u) +#define GPIO_PM7_PM77 (0x0080u) +#define GPIO_PM7_PM78 (0x0100u) +#define GPIO_PM7_PM79 (0x0200u) +#define GPIO_PM7_PM710 (0x0400u) +#define GPIO_PM7_PM711 (0x0800u) +#define GPIO_PM7_PM712 (0x1000u) +#define GPIO_PM7_PM713 (0x2000u) +#define GPIO_PM7_PM714 (0x4000u) +#define GPIO_PM7_PM715 (0x8000u) + +#define GPIO_PMC7_PMC70 (0x0001u) +#define GPIO_PMC7_PMC71 (0x0002u) +#define GPIO_PMC7_PMC72 (0x0004u) +#define GPIO_PMC7_PMC73 (0x0008u) +#define GPIO_PMC7_PMC74 (0x0010u) +#define GPIO_PMC7_PMC75 (0x0020u) +#define GPIO_PMC7_PMC76 (0x0040u) +#define GPIO_PMC7_PMC77 (0x0080u) +#define GPIO_PMC7_PMC78 (0x0100u) +#define GPIO_PMC7_PMC79 (0x0200u) +#define GPIO_PMC7_PMC710 (0x0400u) +#define GPIO_PMC7_PMC711 (0x0800u) +#define GPIO_PMC7_PMC712 (0x1000u) +#define GPIO_PMC7_PMC713 (0x2000u) +#define GPIO_PMC7_PMC714 (0x4000u) +#define GPIO_PMC7_PMC715 (0x8000u) + +#define GPIO_PFC7_PFC70 (0x0001u) +#define GPIO_PFC7_PFC71 (0x0002u) +#define GPIO_PFC7_PFC72 (0x0004u) +#define GPIO_PFC7_PFC73 (0x0008u) +#define GPIO_PFC7_PFC74 (0x0010u) +#define GPIO_PFC7_PFC75 (0x0020u) +#define GPIO_PFC7_PFC76 (0x0040u) +#define GPIO_PFC7_PFC77 (0x0080u) +#define GPIO_PFC7_PFC78 (0x0100u) +#define GPIO_PFC7_PFC79 (0x0200u) +#define GPIO_PFC7_PFC710 (0x0400u) +#define GPIO_PFC7_PFC711 (0x0800u) +#define GPIO_PFC7_PFC712 (0x1000u) +#define GPIO_PFC7_PFC713 (0x2000u) +#define GPIO_PFC7_PFC714 (0x4000u) +#define GPIO_PFC7_PFC715 (0x8000u) + +#define GPIO_PFCE7_PFCE70 (0x0001u) +#define GPIO_PFCE7_PFCE71 (0x0002u) +#define GPIO_PFCE7_PFCE72 (0x0004u) +#define GPIO_PFCE7_PFCE73 (0x0008u) +#define GPIO_PFCE7_PFCE74 (0x0010u) +#define GPIO_PFCE7_PFCE75 (0x0020u) +#define GPIO_PFCE7_PFCE76 (0x0040u) +#define GPIO_PFCE7_PFCE77 (0x0080u) +#define GPIO_PFCE7_PFCE78 (0x0100u) +#define GPIO_PFCE7_PFCE79 (0x0200u) +#define GPIO_PFCE7_PFCE710 (0x0400u) +#define GPIO_PFCE7_PFCE711 (0x0800u) +#define GPIO_PFCE7_PFCE712 (0x1000u) +#define GPIO_PFCE7_PFCE713 (0x2000u) +#define GPIO_PFCE7_PFCE714 (0x4000u) +#define GPIO_PFCE7_PFCE715 (0x8000u) + +#define GPIO_PNOT7_PNOT70 (0x0001u) +#define GPIO_PNOT7_PNOT71 (0x0002u) +#define GPIO_PNOT7_PNOT72 (0x0004u) +#define GPIO_PNOT7_PNOT73 (0x0008u) +#define GPIO_PNOT7_PNOT74 (0x0010u) +#define GPIO_PNOT7_PNOT75 (0x0020u) +#define GPIO_PNOT7_PNOT76 (0x0040u) +#define GPIO_PNOT7_PNOT77 (0x0080u) +#define GPIO_PNOT7_PNOT78 (0x0100u) +#define GPIO_PNOT7_PNOT79 (0x0200u) +#define GPIO_PNOT7_PNOT710 (0x0400u) +#define GPIO_PNOT7_PNOT711 (0x0800u) +#define GPIO_PNOT7_PNOT712 (0x1000u) +#define GPIO_PNOT7_PNOT713 (0x2000u) +#define GPIO_PNOT7_PNOT714 (0x4000u) +#define GPIO_PNOT7_PNOT715 (0x8000u) + +#define GPIO_PMSR7_PMSR70 (0x00000001uL) +#define GPIO_PMSR7_PMSR71 (0x00000002uL) +#define GPIO_PMSR7_PMSR72 (0x00000004uL) +#define GPIO_PMSR7_PMSR73 (0x00000008uL) +#define GPIO_PMSR7_PMSR74 (0x00000010uL) +#define GPIO_PMSR7_PMSR75 (0x00000020uL) +#define GPIO_PMSR7_PMSR76 (0x00000040uL) +#define GPIO_PMSR7_PMSR77 (0x00000080uL) +#define GPIO_PMSR7_PMSR78 (0x00000100uL) +#define GPIO_PMSR7_PMSR79 (0x00000200uL) +#define GPIO_PMSR7_PMSR710 (0x00000400uL) +#define GPIO_PMSR7_PMSR711 (0x00000800uL) +#define GPIO_PMSR7_PMSR712 (0x00001000uL) +#define GPIO_PMSR7_PMSR713 (0x00002000uL) +#define GPIO_PMSR7_PMSR714 (0x00004000uL) +#define GPIO_PMSR7_PMSR715 (0x00008000uL) +#define GPIO_PMSR7_PMSR716 (0x00010000uL) +#define GPIO_PMSR7_PMSR717 (0x00020000uL) +#define GPIO_PMSR7_PMSR718 (0x00040000uL) +#define GPIO_PMSR7_PMSR719 (0x00080000uL) +#define GPIO_PMSR7_PMSR720 (0x00100000uL) +#define GPIO_PMSR7_PMSR721 (0x00200000uL) +#define GPIO_PMSR7_PMSR722 (0x00400000uL) +#define GPIO_PMSR7_PMSR723 (0x00800000uL) +#define GPIO_PMSR7_PMSR724 (0x01000000uL) +#define GPIO_PMSR7_PMSR725 (0x02000000uL) +#define GPIO_PMSR7_PMSR726 (0x04000000uL) +#define GPIO_PMSR7_PMSR727 (0x08000000uL) +#define GPIO_PMSR7_PMSR728 (0x10000000uL) +#define GPIO_PMSR7_PMSR729 (0x20000000uL) +#define GPIO_PMSR7_PMSR730 (0x40000000uL) +#define GPIO_PMSR7_PMSR731 (0x80000000uL) + +#define GPIO_PMCSR7_PMCSR70 (0x00000001uL) +#define GPIO_PMCSR7_PMCSR71 (0x00000002uL) +#define GPIO_PMCSR7_PMCSR72 (0x00000004uL) +#define GPIO_PMCSR7_PMCSR73 (0x00000008uL) +#define GPIO_PMCSR7_PMCSR74 (0x00000010uL) +#define GPIO_PMCSR7_PMCSR75 (0x00000020uL) +#define GPIO_PMCSR7_PMCSR76 (0x00000040uL) +#define GPIO_PMCSR7_PMCSR77 (0x00000080uL) +#define GPIO_PMCSR7_PMCSR78 (0x00000100uL) +#define GPIO_PMCSR7_PMCSR79 (0x00000200uL) +#define GPIO_PMCSR7_PMCSR710 (0x00000400uL) +#define GPIO_PMCSR7_PMCSR711 (0x00000800uL) +#define GPIO_PMCSR7_PMCSR712 (0x00001000uL) +#define GPIO_PMCSR7_PMCSR713 (0x00002000uL) +#define GPIO_PMCSR7_PMCSR714 (0x00004000uL) +#define GPIO_PMCSR7_PMCSR715 (0x00008000uL) +#define GPIO_PMCSR7_PMCSR716 (0x00010000uL) +#define GPIO_PMCSR7_PMCSR717 (0x00020000uL) +#define GPIO_PMCSR7_PMCSR718 (0x00040000uL) +#define GPIO_PMCSR7_PMCSR719 (0x00080000uL) +#define GPIO_PMCSR7_PMCSR720 (0x00100000uL) +#define GPIO_PMCSR7_PMCSR721 (0x00200000uL) +#define GPIO_PMCSR7_PMCSR722 (0x00400000uL) +#define GPIO_PMCSR7_PMCSR723 (0x00800000uL) +#define GPIO_PMCSR7_PMCSR724 (0x01000000uL) +#define GPIO_PMCSR7_PMCSR725 (0x02000000uL) +#define GPIO_PMCSR7_PMCSR726 (0x04000000uL) +#define GPIO_PMCSR7_PMCSR727 (0x08000000uL) +#define GPIO_PMCSR7_PMCSR728 (0x10000000uL) +#define GPIO_PMCSR7_PMCSR729 (0x20000000uL) +#define GPIO_PMCSR7_PMCSR730 (0x40000000uL) +#define GPIO_PMCSR7_PMCSR731 (0x80000000uL) + +#define GPIO_PFCAE7_PFCAE70 (0x0001u) +#define GPIO_PFCAE7_PFCAE71 (0x0002u) +#define GPIO_PFCAE7_PFCAE72 (0x0004u) +#define GPIO_PFCAE7_PFCAE73 (0x0008u) +#define GPIO_PFCAE7_PFCAE74 (0x0010u) +#define GPIO_PFCAE7_PFCAE75 (0x0020u) +#define GPIO_PFCAE7_PFCAE76 (0x0040u) +#define GPIO_PFCAE7_PFCAE77 (0x0080u) +#define GPIO_PFCAE7_PFCAE78 (0x0100u) +#define GPIO_PFCAE7_PFCAE79 (0x0200u) +#define GPIO_PFCAE7_PFCAE710 (0x0400u) +#define GPIO_PFCAE7_PFCAE711 (0x0800u) +#define GPIO_PFCAE7_PFCAE712 (0x1000u) +#define GPIO_PFCAE7_PFCAE713 (0x2000u) +#define GPIO_PFCAE7_PFCAE714 (0x4000u) +#define GPIO_PFCAE7_PFCAE715 (0x8000u) + +#define GPIO_PIBC7_PIBC70 (0x0001u) +#define GPIO_PIBC7_PIBC71 (0x0002u) +#define GPIO_PIBC7_PIBC72 (0x0004u) +#define GPIO_PIBC7_PIBC73 (0x0008u) +#define GPIO_PIBC7_PIBC74 (0x0010u) +#define GPIO_PIBC7_PIBC75 (0x0020u) +#define GPIO_PIBC7_PIBC76 (0x0040u) +#define GPIO_PIBC7_PIBC77 (0x0080u) +#define GPIO_PIBC7_PIBC78 (0x0100u) +#define GPIO_PIBC7_PIBC79 (0x0200u) +#define GPIO_PIBC7_PIBC710 (0x0400u) +#define GPIO_PIBC7_PIBC711 (0x0800u) +#define GPIO_PIBC7_PIBC712 (0x1000u) +#define GPIO_PIBC7_PIBC713 (0x2000u) +#define GPIO_PIBC7_PIBC714 (0x4000u) +#define GPIO_PIBC7_PIBC715 (0x8000u) + +#define GPIO_PBDC7_PBDC70 (0x0001u) +#define GPIO_PBDC7_PBDC71 (0x0002u) +#define GPIO_PBDC7_PBDC72 (0x0004u) +#define GPIO_PBDC7_PBDC73 (0x0008u) +#define GPIO_PBDC7_PBDC74 (0x0010u) +#define GPIO_PBDC7_PBDC75 (0x0020u) +#define GPIO_PBDC7_PBDC76 (0x0040u) +#define GPIO_PBDC7_PBDC77 (0x0080u) +#define GPIO_PBDC7_PBDC78 (0x0100u) +#define GPIO_PBDC7_PBDC79 (0x0200u) +#define GPIO_PBDC7_PBDC710 (0x0400u) +#define GPIO_PBDC7_PBDC711 (0x0800u) +#define GPIO_PBDC7_PBDC712 (0x1000u) +#define GPIO_PBDC7_PBDC713 (0x2000u) +#define GPIO_PBDC7_PBDC714 (0x4000u) +#define GPIO_PBDC7_PBDC715 (0x8000u) + +#define GPIO_PIPC7_PIPC70 (0x0001u) +#define GPIO_PIPC7_PIPC71 (0x0002u) +#define GPIO_PIPC7_PIPC72 (0x0004u) +#define GPIO_PIPC7_PIPC73 (0x0008u) +#define GPIO_PIPC7_PIPC74 (0x0010u) +#define GPIO_PIPC7_PIPC75 (0x0020u) +#define GPIO_PIPC7_PIPC76 (0x0040u) +#define GPIO_PIPC7_PIPC77 (0x0080u) +#define GPIO_PIPC7_PIPC78 (0x0100u) +#define GPIO_PIPC7_PIPC79 (0x0200u) +#define GPIO_PIPC7_PIPC710 (0x0400u) +#define GPIO_PIPC7_PIPC711 (0x0800u) +#define GPIO_PIPC7_PIPC712 (0x1000u) +#define GPIO_PIPC7_PIPC713 (0x2000u) +#define GPIO_PIPC7_PIPC714 (0x4000u) +#define GPIO_PIPC7_PIPC715 (0x8000u) + +/* ---- P8 ---- */ +#define GPIO_P8_P80 (0x0001u) +#define GPIO_P8_P81 (0x0002u) +#define GPIO_P8_P82 (0x0004u) +#define GPIO_P8_P83 (0x0008u) +#define GPIO_P8_P84 (0x0010u) +#define GPIO_P8_P85 (0x0020u) +#define GPIO_P8_P86 (0x0040u) +#define GPIO_P8_P87 (0x0080u) +#define GPIO_P8_P88 (0x0100u) +#define GPIO_P8_P89 (0x0200u) +#define GPIO_P8_P810 (0x0400u) +#define GPIO_P8_P811 (0x0800u) +#define GPIO_P8_P812 (0x1000u) +#define GPIO_P8_P813 (0x2000u) +#define GPIO_P8_P814 (0x4000u) +#define GPIO_P8_P815 (0x8000u) + +#define GPIO_PSR8_PSR80 (0x00000001uL) +#define GPIO_PSR8_PSR81 (0x00000002uL) +#define GPIO_PSR8_PSR82 (0x00000004uL) +#define GPIO_PSR8_PSR83 (0x00000008uL) +#define GPIO_PSR8_PSR84 (0x00000010uL) +#define GPIO_PSR8_PSR85 (0x00000020uL) +#define GPIO_PSR8_PSR86 (0x00000040uL) +#define GPIO_PSR8_PSR87 (0x00000080uL) +#define GPIO_PSR8_PSR88 (0x00000100uL) +#define GPIO_PSR8_PSR89 (0x00000200uL) +#define GPIO_PSR8_PSR810 (0x00000400uL) +#define GPIO_PSR8_PSR811 (0x00000800uL) +#define GPIO_PSR8_PSR812 (0x00001000uL) +#define GPIO_PSR8_PSR813 (0x00002000uL) +#define GPIO_PSR8_PSR814 (0x00004000uL) +#define GPIO_PSR8_PSR815 (0x00008000uL) +#define GPIO_PSR8_PSR816 (0x00010000uL) +#define GPIO_PSR8_PSR817 (0x00020000uL) +#define GPIO_PSR8_PSR818 (0x00040000uL) +#define GPIO_PSR8_PSR819 (0x00080000uL) +#define GPIO_PSR8_PSR820 (0x00100000uL) +#define GPIO_PSR8_PSR821 (0x00200000uL) +#define GPIO_PSR8_PSR822 (0x00400000uL) +#define GPIO_PSR8_PSR823 (0x00800000uL) +#define GPIO_PSR8_PSR824 (0x01000000uL) +#define GPIO_PSR8_PSR825 (0x02000000uL) +#define GPIO_PSR8_PSR826 (0x04000000uL) +#define GPIO_PSR8_PSR827 (0x08000000uL) +#define GPIO_PSR8_PSR828 (0x10000000uL) +#define GPIO_PSR8_PSR829 (0x20000000uL) +#define GPIO_PSR8_PSR830 (0x40000000uL) +#define GPIO_PSR8_PSR831 (0x80000000uL) + +#define GPIO_PPR8_PPR80 (0x0001u) +#define GPIO_PPR8_PPR81 (0x0002u) +#define GPIO_PPR8_PPR82 (0x0004u) +#define GPIO_PPR8_PPR83 (0x0008u) +#define GPIO_PPR8_PPR84 (0x0010u) +#define GPIO_PPR8_PPR85 (0x0020u) +#define GPIO_PPR8_PPR86 (0x0040u) +#define GPIO_PPR8_PPR87 (0x0080u) +#define GPIO_PPR8_PPR88 (0x0100u) +#define GPIO_PPR8_PPR89 (0x0200u) +#define GPIO_PPR8_PPR810 (0x0400u) +#define GPIO_PPR8_PPR811 (0x0800u) +#define GPIO_PPR8_PPR812 (0x1000u) +#define GPIO_PPR8_PPR813 (0x2000u) +#define GPIO_PPR8_PPR814 (0x4000u) +#define GPIO_PPR8_PPR815 (0x8000u) + +#define GPIO_PM8_PM80 (0x0001u) +#define GPIO_PM8_PM81 (0x0002u) +#define GPIO_PM8_PM82 (0x0004u) +#define GPIO_PM8_PM83 (0x0008u) +#define GPIO_PM8_PM84 (0x0010u) +#define GPIO_PM8_PM85 (0x0020u) +#define GPIO_PM8_PM86 (0x0040u) +#define GPIO_PM8_PM87 (0x0080u) +#define GPIO_PM8_PM88 (0x0100u) +#define GPIO_PM8_PM89 (0x0200u) +#define GPIO_PM8_PM810 (0x0400u) +#define GPIO_PM8_PM811 (0x0800u) +#define GPIO_PM8_PM812 (0x1000u) +#define GPIO_PM8_PM813 (0x2000u) +#define GPIO_PM8_PM814 (0x4000u) +#define GPIO_PM8_PM815 (0x8000u) + +#define GPIO_PMC8_PMC80 (0x0001u) +#define GPIO_PMC8_PMC81 (0x0002u) +#define GPIO_PMC8_PMC82 (0x0004u) +#define GPIO_PMC8_PMC83 (0x0008u) +#define GPIO_PMC8_PMC84 (0x0010u) +#define GPIO_PMC8_PMC85 (0x0020u) +#define GPIO_PMC8_PMC86 (0x0040u) +#define GPIO_PMC8_PMC87 (0x0080u) +#define GPIO_PMC8_PMC88 (0x0100u) +#define GPIO_PMC8_PMC89 (0x0200u) +#define GPIO_PMC8_PMC810 (0x0400u) +#define GPIO_PMC8_PMC811 (0x0800u) +#define GPIO_PMC8_PMC812 (0x1000u) +#define GPIO_PMC8_PMC813 (0x2000u) +#define GPIO_PMC8_PMC814 (0x4000u) +#define GPIO_PMC8_PMC815 (0x8000u) + +#define GPIO_PFC8_PFC80 (0x0001u) +#define GPIO_PFC8_PFC81 (0x0002u) +#define GPIO_PFC8_PFC82 (0x0004u) +#define GPIO_PFC8_PFC83 (0x0008u) +#define GPIO_PFC8_PFC84 (0x0010u) +#define GPIO_PFC8_PFC85 (0x0020u) +#define GPIO_PFC8_PFC86 (0x0040u) +#define GPIO_PFC8_PFC87 (0x0080u) +#define GPIO_PFC8_PFC88 (0x0100u) +#define GPIO_PFC8_PFC89 (0x0200u) +#define GPIO_PFC8_PFC810 (0x0400u) +#define GPIO_PFC8_PFC811 (0x0800u) +#define GPIO_PFC8_PFC812 (0x1000u) +#define GPIO_PFC8_PFC813 (0x2000u) +#define GPIO_PFC8_PFC814 (0x4000u) +#define GPIO_PFC8_PFC815 (0x8000u) + +#define GPIO_PFCE8_PFCE80 (0x0001u) +#define GPIO_PFCE8_PFCE81 (0x0002u) +#define GPIO_PFCE8_PFCE82 (0x0004u) +#define GPIO_PFCE8_PFCE83 (0x0008u) +#define GPIO_PFCE8_PFCE84 (0x0010u) +#define GPIO_PFCE8_PFCE85 (0x0020u) +#define GPIO_PFCE8_PFCE86 (0x0040u) +#define GPIO_PFCE8_PFCE87 (0x0080u) +#define GPIO_PFCE8_PFCE88 (0x0100u) +#define GPIO_PFCE8_PFCE89 (0x0200u) +#define GPIO_PFCE8_PFCE810 (0x0400u) +#define GPIO_PFCE8_PFCE811 (0x0800u) +#define GPIO_PFCE8_PFCE812 (0x1000u) +#define GPIO_PFCE8_PFCE813 (0x2000u) +#define GPIO_PFCE8_PFCE814 (0x4000u) +#define GPIO_PFCE8_PFCE815 (0x8000u) + +#define GPIO_PNOT8_PNOT80 (0x0001u) +#define GPIO_PNOT8_PNOT81 (0x0002u) +#define GPIO_PNOT8_PNOT82 (0x0004u) +#define GPIO_PNOT8_PNOT83 (0x0008u) +#define GPIO_PNOT8_PNOT84 (0x0010u) +#define GPIO_PNOT8_PNOT85 (0x0020u) +#define GPIO_PNOT8_PNOT86 (0x0040u) +#define GPIO_PNOT8_PNOT87 (0x0080u) +#define GPIO_PNOT8_PNOT88 (0x0100u) +#define GPIO_PNOT8_PNOT89 (0x0200u) +#define GPIO_PNOT8_PNOT810 (0x0400u) +#define GPIO_PNOT8_PNOT811 (0x0800u) +#define GPIO_PNOT8_PNOT812 (0x1000u) +#define GPIO_PNOT8_PNOT813 (0x2000u) +#define GPIO_PNOT8_PNOT814 (0x4000u) +#define GPIO_PNOT8_PNOT815 (0x8000u) + +#define GPIO_PMSR8_PMSR80 (0x00000001uL) +#define GPIO_PMSR8_PMSR81 (0x00000002uL) +#define GPIO_PMSR8_PMSR82 (0x00000004uL) +#define GPIO_PMSR8_PMSR83 (0x00000008uL) +#define GPIO_PMSR8_PMSR84 (0x00000010uL) +#define GPIO_PMSR8_PMSR85 (0x00000020uL) +#define GPIO_PMSR8_PMSR86 (0x00000040uL) +#define GPIO_PMSR8_PMSR87 (0x00000080uL) +#define GPIO_PMSR8_PMSR88 (0x00000100uL) +#define GPIO_PMSR8_PMSR89 (0x00000200uL) +#define GPIO_PMSR8_PMSR810 (0x00000400uL) +#define GPIO_PMSR8_PMSR811 (0x00000800uL) +#define GPIO_PMSR8_PMSR812 (0x00001000uL) +#define GPIO_PMSR8_PMSR813 (0x00002000uL) +#define GPIO_PMSR8_PMSR814 (0x00004000uL) +#define GPIO_PMSR8_PMSR815 (0x00008000uL) +#define GPIO_PMSR8_PMSR816 (0x00010000uL) +#define GPIO_PMSR8_PMSR817 (0x00020000uL) +#define GPIO_PMSR8_PMSR818 (0x00040000uL) +#define GPIO_PMSR8_PMSR819 (0x00080000uL) +#define GPIO_PMSR8_PMSR820 (0x00100000uL) +#define GPIO_PMSR8_PMSR821 (0x00200000uL) +#define GPIO_PMSR8_PMSR822 (0x00400000uL) +#define GPIO_PMSR8_PMSR823 (0x00800000uL) +#define GPIO_PMSR8_PMSR824 (0x01000000uL) +#define GPIO_PMSR8_PMSR825 (0x02000000uL) +#define GPIO_PMSR8_PMSR826 (0x04000000uL) +#define GPIO_PMSR8_PMSR827 (0x08000000uL) +#define GPIO_PMSR8_PMSR828 (0x10000000uL) +#define GPIO_PMSR8_PMSR829 (0x20000000uL) +#define GPIO_PMSR8_PMSR830 (0x40000000uL) +#define GPIO_PMSR8_PMSR831 (0x80000000uL) + +#define GPIO_PMCSR8_PMCSR80 (0x00000001uL) +#define GPIO_PMCSR8_PMCSR81 (0x00000002uL) +#define GPIO_PMCSR8_PMCSR82 (0x00000004uL) +#define GPIO_PMCSR8_PMCSR83 (0x00000008uL) +#define GPIO_PMCSR8_PMCSR84 (0x00000010uL) +#define GPIO_PMCSR8_PMCSR85 (0x00000020uL) +#define GPIO_PMCSR8_PMCSR86 (0x00000040uL) +#define GPIO_PMCSR8_PMCSR87 (0x00000080uL) +#define GPIO_PMCSR8_PMCSR88 (0x00000100uL) +#define GPIO_PMCSR8_PMCSR89 (0x00000200uL) +#define GPIO_PMCSR8_PMCSR810 (0x00000400uL) +#define GPIO_PMCSR8_PMCSR811 (0x00000800uL) +#define GPIO_PMCSR8_PMCSR812 (0x00001000uL) +#define GPIO_PMCSR8_PMCSR813 (0x00002000uL) +#define GPIO_PMCSR8_PMCSR814 (0x00004000uL) +#define GPIO_PMCSR8_PMCSR815 (0x00008000uL) +#define GPIO_PMCSR8_PMCSR816 (0x00010000uL) +#define GPIO_PMCSR8_PMCSR817 (0x00020000uL) +#define GPIO_PMCSR8_PMCSR818 (0x00040000uL) +#define GPIO_PMCSR8_PMCSR819 (0x00080000uL) +#define GPIO_PMCSR8_PMCSR820 (0x00100000uL) +#define GPIO_PMCSR8_PMCSR821 (0x00200000uL) +#define GPIO_PMCSR8_PMCSR822 (0x00400000uL) +#define GPIO_PMCSR8_PMCSR823 (0x00800000uL) +#define GPIO_PMCSR8_PMCSR824 (0x01000000uL) +#define GPIO_PMCSR8_PMCSR825 (0x02000000uL) +#define GPIO_PMCSR8_PMCSR826 (0x04000000uL) +#define GPIO_PMCSR8_PMCSR827 (0x08000000uL) +#define GPIO_PMCSR8_PMCSR828 (0x10000000uL) +#define GPIO_PMCSR8_PMCSR829 (0x20000000uL) +#define GPIO_PMCSR8_PMCSR830 (0x40000000uL) +#define GPIO_PMCSR8_PMCSR831 (0x80000000uL) + +#define GPIO_PFCAE8_PFCAE80 (0x0001u) +#define GPIO_PFCAE8_PFCAE81 (0x0002u) +#define GPIO_PFCAE8_PFCAE82 (0x0004u) +#define GPIO_PFCAE8_PFCAE83 (0x0008u) +#define GPIO_PFCAE8_PFCAE84 (0x0010u) +#define GPIO_PFCAE8_PFCAE85 (0x0020u) +#define GPIO_PFCAE8_PFCAE86 (0x0040u) +#define GPIO_PFCAE8_PFCAE87 (0x0080u) +#define GPIO_PFCAE8_PFCAE88 (0x0100u) +#define GPIO_PFCAE8_PFCAE89 (0x0200u) +#define GPIO_PFCAE8_PFCAE810 (0x0400u) +#define GPIO_PFCAE8_PFCAE811 (0x0800u) +#define GPIO_PFCAE8_PFCAE812 (0x1000u) +#define GPIO_PFCAE8_PFCAE813 (0x2000u) +#define GPIO_PFCAE8_PFCAE814 (0x4000u) +#define GPIO_PFCAE8_PFCAE815 (0x8000u) + +#define GPIO_PIBC8_PIBC80 (0x0001u) +#define GPIO_PIBC8_PIBC81 (0x0002u) +#define GPIO_PIBC8_PIBC82 (0x0004u) +#define GPIO_PIBC8_PIBC83 (0x0008u) +#define GPIO_PIBC8_PIBC84 (0x0010u) +#define GPIO_PIBC8_PIBC85 (0x0020u) +#define GPIO_PIBC8_PIBC86 (0x0040u) +#define GPIO_PIBC8_PIBC87 (0x0080u) +#define GPIO_PIBC8_PIBC88 (0x0100u) +#define GPIO_PIBC8_PIBC89 (0x0200u) +#define GPIO_PIBC8_PIBC810 (0x0400u) +#define GPIO_PIBC8_PIBC811 (0x0800u) +#define GPIO_PIBC8_PIBC812 (0x1000u) +#define GPIO_PIBC8_PIBC813 (0x2000u) +#define GPIO_PIBC8_PIBC814 (0x4000u) +#define GPIO_PIBC8_PIBC815 (0x8000u) + +#define GPIO_PBDC8_PBDC80 (0x0001u) +#define GPIO_PBDC8_PBDC81 (0x0002u) +#define GPIO_PBDC8_PBDC82 (0x0004u) +#define GPIO_PBDC8_PBDC83 (0x0008u) +#define GPIO_PBDC8_PBDC84 (0x0010u) +#define GPIO_PBDC8_PBDC85 (0x0020u) +#define GPIO_PBDC8_PBDC86 (0x0040u) +#define GPIO_PBDC8_PBDC87 (0x0080u) +#define GPIO_PBDC8_PBDC88 (0x0100u) +#define GPIO_PBDC8_PBDC89 (0x0200u) +#define GPIO_PBDC8_PBDC810 (0x0400u) +#define GPIO_PBDC8_PBDC811 (0x0800u) +#define GPIO_PBDC8_PBDC812 (0x1000u) +#define GPIO_PBDC8_PBDC813 (0x2000u) +#define GPIO_PBDC8_PBDC814 (0x4000u) +#define GPIO_PBDC8_PBDC815 (0x8000u) + +#define GPIO_PIPC8_PIPC80 (0x0001u) +#define GPIO_PIPC8_PIPC81 (0x0002u) +#define GPIO_PIPC8_PIPC82 (0x0004u) +#define GPIO_PIPC8_PIPC83 (0x0008u) +#define GPIO_PIPC8_PIPC84 (0x0010u) +#define GPIO_PIPC8_PIPC85 (0x0020u) +#define GPIO_PIPC8_PIPC86 (0x0040u) +#define GPIO_PIPC8_PIPC87 (0x0080u) +#define GPIO_PIPC8_PIPC88 (0x0100u) +#define GPIO_PIPC8_PIPC89 (0x0200u) +#define GPIO_PIPC8_PIPC810 (0x0400u) +#define GPIO_PIPC8_PIPC811 (0x0800u) +#define GPIO_PIPC8_PIPC812 (0x1000u) +#define GPIO_PIPC8_PIPC813 (0x2000u) +#define GPIO_PIPC8_PIPC814 (0x4000u) +#define GPIO_PIPC8_PIPC815 (0x8000u) + +/* ---- P9 ---- */ +#define GPIO_P9_P90 (0x0001u) +#define GPIO_P9_P91 (0x0002u) +#define GPIO_P9_P92 (0x0004u) +#define GPIO_P9_P93 (0x0008u) +#define GPIO_P9_P94 (0x0010u) +#define GPIO_P9_P95 (0x0020u) +#define GPIO_P9_P96 (0x0040u) +#define GPIO_P9_P97 (0x0080u) + +#define GPIO_PSR9_PSR90 (0x00000001uL) +#define GPIO_PSR9_PSR91 (0x00000002uL) +#define GPIO_PSR9_PSR92 (0x00000004uL) +#define GPIO_PSR9_PSR93 (0x00000008uL) +#define GPIO_PSR9_PSR94 (0x00000010uL) +#define GPIO_PSR9_PSR95 (0x00000020uL) +#define GPIO_PSR9_PSR96 (0x00000040uL) +#define GPIO_PSR9_PSR97 (0x00000080uL) +#define GPIO_PSR9_PSR916 (0x00010000uL) +#define GPIO_PSR9_PSR917 (0x00020000uL) +#define GPIO_PSR9_PSR918 (0x00040000uL) +#define GPIO_PSR9_PSR919 (0x00080000uL) +#define GPIO_PSR9_PSR920 (0x00100000uL) +#define GPIO_PSR9_PSR921 (0x00200000uL) +#define GPIO_PSR9_PSR922 (0x00400000uL) +#define GPIO_PSR9_PSR923 (0x00800000uL) + +#define GPIO_PPR9_PPR90 (0x0001u) +#define GPIO_PPR9_PPR91 (0x0002u) +#define GPIO_PPR9_PPR92 (0x0004u) +#define GPIO_PPR9_PPR93 (0x0008u) +#define GPIO_PPR9_PPR94 (0x0010u) +#define GPIO_PPR9_PPR95 (0x0020u) +#define GPIO_PPR9_PPR96 (0x0040u) +#define GPIO_PPR9_PPR97 (0x0080u) + +#define GPIO_PM9_PM90 (0x0001u) +#define GPIO_PM9_PM91 (0x0002u) +#define GPIO_PM9_PM92 (0x0004u) +#define GPIO_PM9_PM93 (0x0008u) +#define GPIO_PM9_PM94 (0x0010u) +#define GPIO_PM9_PM95 (0x0020u) +#define GPIO_PM9_PM96 (0x0040u) +#define GPIO_PM9_PM97 (0x0080u) + +#define GPIO_PMC9_PMC90 (0x0001u) +#define GPIO_PMC9_PMC91 (0x0002u) +#define GPIO_PMC9_PMC92 (0x0004u) +#define GPIO_PMC9_PMC93 (0x0008u) +#define GPIO_PMC9_PMC94 (0x0010u) +#define GPIO_PMC9_PMC95 (0x0020u) +#define GPIO_PMC9_PMC96 (0x0040u) +#define GPIO_PMC9_PMC97 (0x0080u) + +#define GPIO_PFC9_PFC90 (0x0001u) +#define GPIO_PFC9_PFC91 (0x0002u) +#define GPIO_PFC9_PFC92 (0x0004u) +#define GPIO_PFC9_PFC93 (0x0008u) +#define GPIO_PFC9_PFC94 (0x0010u) +#define GPIO_PFC9_PFC95 (0x0020u) +#define GPIO_PFC9_PFC96 (0x0040u) +#define GPIO_PFC9_PFC97 (0x0080u) + +#define GPIO_PFCE9_PFCE90 (0x0001u) +#define GPIO_PFCE9_PFCE91 (0x0002u) +#define GPIO_PFCE9_PFCE92 (0x0004u) +#define GPIO_PFCE9_PFCE93 (0x0008u) +#define GPIO_PFCE9_PFCE94 (0x0010u) +#define GPIO_PFCE9_PFCE95 (0x0020u) +#define GPIO_PFCE9_PFCE96 (0x0040u) +#define GPIO_PFCE9_PFCE97 (0x0080u) + +#define GPIO_PNOT9_PNOT90 (0x0001u) +#define GPIO_PNOT9_PNOT91 (0x0002u) +#define GPIO_PNOT9_PNOT92 (0x0004u) +#define GPIO_PNOT9_PNOT93 (0x0008u) +#define GPIO_PNOT9_PNOT94 (0x0010u) +#define GPIO_PNOT9_PNOT95 (0x0020u) +#define GPIO_PNOT9_PNOT96 (0x0040u) +#define GPIO_PNOT9_PNOT97 (0x0080u) + +#define GPIO_PMSR9_PMSR90 (0x00000001uL) +#define GPIO_PMSR9_PMSR91 (0x00000002uL) +#define GPIO_PMSR9_PMSR92 (0x00000004uL) +#define GPIO_PMSR9_PMSR93 (0x00000008uL) +#define GPIO_PMSR9_PMSR94 (0x00000010uL) +#define GPIO_PMSR9_PMSR95 (0x00000020uL) +#define GPIO_PMSR9_PMSR96 (0x00000040uL) +#define GPIO_PMSR9_PMSR97 (0x00000080uL) +#define GPIO_PMSR9_PMSR916 (0x00010000uL) +#define GPIO_PMSR9_PMSR917 (0x00020000uL) +#define GPIO_PMSR9_PMSR918 (0x00040000uL) +#define GPIO_PMSR9_PMSR919 (0x00080000uL) +#define GPIO_PMSR9_PMSR920 (0x00100000uL) +#define GPIO_PMSR9_PMSR921 (0x00200000uL) +#define GPIO_PMSR9_PMSR922 (0x00400000uL) +#define GPIO_PMSR9_PMSR923 (0x00800000uL) + +#define GPIO_PMCSR9_PMCSR90 (0x00000001uL) +#define GPIO_PMCSR9_PMCSR91 (0x00000002uL) +#define GPIO_PMCSR9_PMCSR92 (0x00000004uL) +#define GPIO_PMCSR9_PMCSR93 (0x00000008uL) +#define GPIO_PMCSR9_PMCSR94 (0x00000010uL) +#define GPIO_PMCSR9_PMCSR95 (0x00000020uL) +#define GPIO_PMCSR9_PMCSR96 (0x00000040uL) +#define GPIO_PMCSR9_PMCSR97 (0x00000080uL) +#define GPIO_PMCSR9_PMCSR916 (0x00010000uL) +#define GPIO_PMCSR9_PMCSR917 (0x00020000uL) +#define GPIO_PMCSR9_PMCSR918 (0x00040000uL) +#define GPIO_PMCSR9_PMCSR919 (0x00080000uL) +#define GPIO_PMCSR9_PMCSR920 (0x00100000uL) +#define GPIO_PMCSR9_PMCSR921 (0x00200000uL) +#define GPIO_PMCSR9_PMCSR922 (0x00400000uL) +#define GPIO_PMCSR9_PMCSR923 (0x00800000uL) + +#define GPIO_PFCAE9_PFCAE90 (0x0001u) +#define GPIO_PFCAE9_PFCAE91 (0x0002u) +#define GPIO_PFCAE9_PFCAE92 (0x0004u) +#define GPIO_PFCAE9_PFCAE93 (0x0008u) +#define GPIO_PFCAE9_PFCAE94 (0x0010u) +#define GPIO_PFCAE9_PFCAE95 (0x0020u) +#define GPIO_PFCAE9_PFCAE96 (0x0040u) +#define GPIO_PFCAE9_PFCAE97 (0x0080u) + +#define GPIO_PIBC9_PIBC90 (0x0001u) +#define GPIO_PIBC9_PIBC91 (0x0002u) +#define GPIO_PIBC9_PIBC92 (0x0004u) +#define GPIO_PIBC9_PIBC93 (0x0008u) +#define GPIO_PIBC9_PIBC94 (0x0010u) +#define GPIO_PIBC9_PIBC95 (0x0020u) +#define GPIO_PIBC9_PIBC96 (0x0040u) +#define GPIO_PIBC9_PIBC97 (0x0080u) + +#define GPIO_PBDC9_PBDC90 (0x0001u) +#define GPIO_PBDC9_PBDC91 (0x0002u) +#define GPIO_PBDC9_PBDC92 (0x0004u) +#define GPIO_PBDC9_PBDC93 (0x0008u) +#define GPIO_PBDC9_PBDC94 (0x0010u) +#define GPIO_PBDC9_PBDC95 (0x0020u) +#define GPIO_PBDC9_PBDC96 (0x0040u) +#define GPIO_PBDC9_PBDC97 (0x0080u) + +#define GPIO_PIPC9_PIPC90 (0x0001u) +#define GPIO_PIPC9_PIPC91 (0x0002u) +#define GPIO_PIPC9_PIPC92 (0x0004u) +#define GPIO_PIPC9_PIPC93 (0x0008u) +#define GPIO_PIPC9_PIPC94 (0x0010u) +#define GPIO_PIPC9_PIPC95 (0x0020u) +#define GPIO_PIPC9_PIPC96 (0x0040u) +#define GPIO_PIPC9_PIPC97 (0x0080u) + +/* ---- P10 ---- */ +#define GPIO_P10_P100 (0x0001u) +#define GPIO_P10_P101 (0x0002u) +#define GPIO_P10_P102 (0x0004u) +#define GPIO_P10_P103 (0x0008u) +#define GPIO_P10_P104 (0x0010u) +#define GPIO_P10_P105 (0x0020u) +#define GPIO_P10_P106 (0x0040u) +#define GPIO_P10_P107 (0x0080u) +#define GPIO_P10_P108 (0x0100u) +#define GPIO_P10_P109 (0x0200u) +#define GPIO_P10_P1010 (0x0400u) +#define GPIO_P10_P1011 (0x0800u) +#define GPIO_P10_P1012 (0x1000u) +#define GPIO_P10_P1013 (0x2000u) +#define GPIO_P10_P1014 (0x4000u) +#define GPIO_P10_P1015 (0x8000u) + +#define GPIO_PSR10_PSR100 (0x00000001uL) +#define GPIO_PSR10_PSR101 (0x00000002uL) +#define GPIO_PSR10_PSR102 (0x00000004uL) +#define GPIO_PSR10_PSR103 (0x00000008uL) +#define GPIO_PSR10_PSR104 (0x00000010uL) +#define GPIO_PSR10_PSR105 (0x00000020uL) +#define GPIO_PSR10_PSR106 (0x00000040uL) +#define GPIO_PSR10_PSR107 (0x00000080uL) +#define GPIO_PSR10_PSR108 (0x00000100uL) +#define GPIO_PSR10_PSR109 (0x00000200uL) +#define GPIO_PSR10_PSR1010 (0x00000400uL) +#define GPIO_PSR10_PSR1011 (0x00000800uL) +#define GPIO_PSR10_PSR1012 (0x00001000uL) +#define GPIO_PSR10_PSR1013 (0x00002000uL) +#define GPIO_PSR10_PSR1014 (0x00004000uL) +#define GPIO_PSR10_PSR1015 (0x00008000uL) +#define GPIO_PSR10_PSR1016 (0x00010000uL) +#define GPIO_PSR10_PSR1017 (0x00020000uL) +#define GPIO_PSR10_PSR1018 (0x00040000uL) +#define GPIO_PSR10_PSR1019 (0x00080000uL) +#define GPIO_PSR10_PSR1020 (0x00100000uL) +#define GPIO_PSR10_PSR1021 (0x00200000uL) +#define GPIO_PSR10_PSR1022 (0x00400000uL) +#define GPIO_PSR10_PSR1023 (0x00800000uL) +#define GPIO_PSR10_PSR1024 (0x01000000uL) +#define GPIO_PSR10_PSR1025 (0x02000000uL) +#define GPIO_PSR10_PSR1026 (0x04000000uL) +#define GPIO_PSR10_PSR1027 (0x08000000uL) +#define GPIO_PSR10_PSR1028 (0x10000000uL) +#define GPIO_PSR10_PSR1029 (0x20000000uL) +#define GPIO_PSR10_PSR1030 (0x40000000uL) +#define GPIO_PSR10_PSR1031 (0x80000000uL) + +#define GPIO_PPR10_PPR100 (0x0001u) +#define GPIO_PPR10_PPR101 (0x0002u) +#define GPIO_PPR10_PPR102 (0x0004u) +#define GPIO_PPR10_PPR103 (0x0008u) +#define GPIO_PPR10_PPR104 (0x0010u) +#define GPIO_PPR10_PPR105 (0x0020u) +#define GPIO_PPR10_PPR106 (0x0040u) +#define GPIO_PPR10_PPR107 (0x0080u) +#define GPIO_PPR10_PPR108 (0x0100u) +#define GPIO_PPR10_PPR109 (0x0200u) +#define GPIO_PPR10_PPR1010 (0x0400u) +#define GPIO_PPR10_PPR1011 (0x0800u) +#define GPIO_PPR10_PPR1012 (0x1000u) +#define GPIO_PPR10_PPR1013 (0x2000u) +#define GPIO_PPR10_PPR1014 (0x4000u) +#define GPIO_PPR10_PPR1015 (0x8000u) + +#define GPIO_PM10_PM100 (0x0001u) +#define GPIO_PM10_PM101 (0x0002u) +#define GPIO_PM10_PM102 (0x0004u) +#define GPIO_PM10_PM103 (0x0008u) +#define GPIO_PM10_PM104 (0x0010u) +#define GPIO_PM10_PM105 (0x0020u) +#define GPIO_PM10_PM106 (0x0040u) +#define GPIO_PM10_PM107 (0x0080u) +#define GPIO_PM10_PM108 (0x0100u) +#define GPIO_PM10_PM109 (0x0200u) +#define GPIO_PM10_PM1010 (0x0400u) +#define GPIO_PM10_PM1011 (0x0800u) +#define GPIO_PM10_PM1012 (0x1000u) +#define GPIO_PM10_PM1013 (0x2000u) +#define GPIO_PM10_PM1014 (0x4000u) +#define GPIO_PM10_PM1015 (0x8000u) + +#define GPIO_PMC10_PMC100 (0x0001u) +#define GPIO_PMC10_PMC101 (0x0002u) +#define GPIO_PMC10_PMC102 (0x0004u) +#define GPIO_PMC10_PMC103 (0x0008u) +#define GPIO_PMC10_PMC104 (0x0010u) +#define GPIO_PMC10_PMC105 (0x0020u) +#define GPIO_PMC10_PMC106 (0x0040u) +#define GPIO_PMC10_PMC107 (0x0080u) +#define GPIO_PMC10_PMC108 (0x0100u) +#define GPIO_PMC10_PMC109 (0x0200u) +#define GPIO_PMC10_PMC1010 (0x0400u) +#define GPIO_PMC10_PMC1011 (0x0800u) +#define GPIO_PMC10_PMC1012 (0x1000u) +#define GPIO_PMC10_PMC1013 (0x2000u) +#define GPIO_PMC10_PMC1014 (0x4000u) +#define GPIO_PMC10_PMC1015 (0x8000u) + +#define GPIO_PFC10_PFC100 (0x0001u) +#define GPIO_PFC10_PFC101 (0x0002u) +#define GPIO_PFC10_PFC102 (0x0004u) +#define GPIO_PFC10_PFC103 (0x0008u) +#define GPIO_PFC10_PFC104 (0x0010u) +#define GPIO_PFC10_PFC105 (0x0020u) +#define GPIO_PFC10_PFC106 (0x0040u) +#define GPIO_PFC10_PFC107 (0x0080u) +#define GPIO_PFC10_PFC108 (0x0100u) +#define GPIO_PFC10_PFC109 (0x0200u) +#define GPIO_PFC10_PFC1010 (0x0400u) +#define GPIO_PFC10_PFC1011 (0x0800u) +#define GPIO_PFC10_PFC1012 (0x1000u) +#define GPIO_PFC10_PFC1013 (0x2000u) +#define GPIO_PFC10_PFC1014 (0x4000u) +#define GPIO_PFC10_PFC1015 (0x8000u) + +#define GPIO_PFCE10_PFCE100 (0x0001u) +#define GPIO_PFCE10_PFCE101 (0x0002u) +#define GPIO_PFCE10_PFCE102 (0x0004u) +#define GPIO_PFCE10_PFCE103 (0x0008u) +#define GPIO_PFCE10_PFCE104 (0x0010u) +#define GPIO_PFCE10_PFCE105 (0x0020u) +#define GPIO_PFCE10_PFCE106 (0x0040u) +#define GPIO_PFCE10_PFCE107 (0x0080u) +#define GPIO_PFCE10_PFCE108 (0x0100u) +#define GPIO_PFCE10_PFCE109 (0x0200u) +#define GPIO_PFCE10_PFCE1010 (0x0400u) +#define GPIO_PFCE10_PFCE1011 (0x0800u) +#define GPIO_PFCE10_PFCE1012 (0x1000u) +#define GPIO_PFCE10_PFCE1013 (0x2000u) +#define GPIO_PFCE10_PFCE1014 (0x4000u) +#define GPIO_PFCE10_PFCE1015 (0x8000u) + +#define GPIO_PNOT10_PNOT100 (0x0001u) +#define GPIO_PNOT10_PNOT101 (0x0002u) +#define GPIO_PNOT10_PNOT102 (0x0004u) +#define GPIO_PNOT10_PNOT103 (0x0008u) +#define GPIO_PNOT10_PNOT104 (0x0010u) +#define GPIO_PNOT10_PNOT105 (0x0020u) +#define GPIO_PNOT10_PNOT106 (0x0040u) +#define GPIO_PNOT10_PNOT107 (0x0080u) +#define GPIO_PNOT10_PNOT108 (0x0100u) +#define GPIO_PNOT10_PNOT109 (0x0200u) +#define GPIO_PNOT10_PNOT1010 (0x0400u) +#define GPIO_PNOT10_PNOT1011 (0x0800u) +#define GPIO_PNOT10_PNOT1012 (0x1000u) +#define GPIO_PNOT10_PNOT1013 (0x2000u) +#define GPIO_PNOT10_PNOT1014 (0x4000u) +#define GPIO_PNOT10_PNOT1015 (0x8000u) + +#define GPIO_PMSR10_PMSR100 (0x00000001uL) +#define GPIO_PMSR10_PMSR101 (0x00000002uL) +#define GPIO_PMSR10_PMSR102 (0x00000004uL) +#define GPIO_PMSR10_PMSR103 (0x00000008uL) +#define GPIO_PMSR10_PMSR104 (0x00000010uL) +#define GPIO_PMSR10_PMSR105 (0x00000020uL) +#define GPIO_PMSR10_PMSR106 (0x00000040uL) +#define GPIO_PMSR10_PMSR107 (0x00000080uL) +#define GPIO_PMSR10_PMSR108 (0x00000100uL) +#define GPIO_PMSR10_PMSR109 (0x00000200uL) +#define GPIO_PMSR10_PMSR1010 (0x00000400uL) +#define GPIO_PMSR10_PMSR1011 (0x00000800uL) +#define GPIO_PMSR10_PMSR1012 (0x00001000uL) +#define GPIO_PMSR10_PMSR1013 (0x00002000uL) +#define GPIO_PMSR10_PMSR1014 (0x00004000uL) +#define GPIO_PMSR10_PMSR1015 (0x00008000uL) +#define GPIO_PMSR10_PMSR1016 (0x00010000uL) +#define GPIO_PMSR10_PMSR1017 (0x00020000uL) +#define GPIO_PMSR10_PMSR1018 (0x00040000uL) +#define GPIO_PMSR10_PMSR1019 (0x00080000uL) +#define GPIO_PMSR10_PMSR1020 (0x00100000uL) +#define GPIO_PMSR10_PMSR1021 (0x00200000uL) +#define GPIO_PMSR10_PMSR1022 (0x00400000uL) +#define GPIO_PMSR10_PMSR1023 (0x00800000uL) +#define GPIO_PMSR10_PMSR1024 (0x01000000uL) +#define GPIO_PMSR10_PMSR1025 (0x02000000uL) +#define GPIO_PMSR10_PMSR1026 (0x04000000uL) +#define GPIO_PMSR10_PMSR1027 (0x08000000uL) +#define GPIO_PMSR10_PMSR1028 (0x10000000uL) +#define GPIO_PMSR10_PMSR1029 (0x20000000uL) +#define GPIO_PMSR10_PMSR1030 (0x40000000uL) +#define GPIO_PMSR10_PMSR1031 (0x80000000uL) + +#define GPIO_PMCSR10_PMCSR100 (0x00000001uL) +#define GPIO_PMCSR10_PMCSR101 (0x00000002uL) +#define GPIO_PMCSR10_PMCSR102 (0x00000004uL) +#define GPIO_PMCSR10_PMCSR103 (0x00000008uL) +#define GPIO_PMCSR10_PMCSR104 (0x00000010uL) +#define GPIO_PMCSR10_PMCSR105 (0x00000020uL) +#define GPIO_PMCSR10_PMCSR106 (0x00000040uL) +#define GPIO_PMCSR10_PMCSR107 (0x00000080uL) +#define GPIO_PMCSR10_PMCSR108 (0x00000100uL) +#define GPIO_PMCSR10_PMCSR109 (0x00000200uL) +#define GPIO_PMCSR10_PMCSR1010 (0x00000400uL) +#define GPIO_PMCSR10_PMCSR1011 (0x00000800uL) +#define GPIO_PMCSR10_PMCSR1012 (0x00001000uL) +#define GPIO_PMCSR10_PMCSR1013 (0x00002000uL) +#define GPIO_PMCSR10_PMCSR1014 (0x00004000uL) +#define GPIO_PMCSR10_PMCSR1015 (0x00008000uL) +#define GPIO_PMCSR10_PMCSR1016 (0x00010000uL) +#define GPIO_PMCSR10_PMCSR1017 (0x00020000uL) +#define GPIO_PMCSR10_PMCSR1018 (0x00040000uL) +#define GPIO_PMCSR10_PMCSR1019 (0x00080000uL) +#define GPIO_PMCSR10_PMCSR1020 (0x00100000uL) +#define GPIO_PMCSR10_PMCSR1021 (0x00200000uL) +#define GPIO_PMCSR10_PMCSR1022 (0x00400000uL) +#define GPIO_PMCSR10_PMCSR1023 (0x00800000uL) +#define GPIO_PMCSR10_PMCSR1024 (0x01000000uL) +#define GPIO_PMCSR10_PMCSR1025 (0x02000000uL) +#define GPIO_PMCSR10_PMCSR1026 (0x04000000uL) +#define GPIO_PMCSR10_PMCSR1027 (0x08000000uL) +#define GPIO_PMCSR10_PMCSR1028 (0x10000000uL) +#define GPIO_PMCSR10_PMCSR1029 (0x20000000uL) +#define GPIO_PMCSR10_PMCSR1030 (0x40000000uL) +#define GPIO_PMCSR10_PMCSR1031 (0x80000000uL) + +#define GPIO_PFCAE10_PFCAE100 (0x0001u) +#define GPIO_PFCAE10_PFCAE101 (0x0002u) +#define GPIO_PFCAE10_PFCAE102 (0x0004u) +#define GPIO_PFCAE10_PFCAE103 (0x0008u) +#define GPIO_PFCAE10_PFCAE104 (0x0010u) +#define GPIO_PFCAE10_PFCAE105 (0x0020u) +#define GPIO_PFCAE10_PFCAE106 (0x0040u) +#define GPIO_PFCAE10_PFCAE107 (0x0080u) +#define GPIO_PFCAE10_PFCAE108 (0x0100u) +#define GPIO_PFCAE10_PFCAE109 (0x0200u) +#define GPIO_PFCAE10_PFCAE1010 (0x0400u) +#define GPIO_PFCAE10_PFCAE1011 (0x0800u) +#define GPIO_PFCAE10_PFCAE1012 (0x1000u) +#define GPIO_PFCAE10_PFCAE1013 (0x2000u) +#define GPIO_PFCAE10_PFCAE1014 (0x4000u) +#define GPIO_PFCAE10_PFCAE1015 (0x8000u) + +#define GPIO_PIBC10_PIBC100 (0x0001u) +#define GPIO_PIBC10_PIBC101 (0x0002u) +#define GPIO_PIBC10_PIBC102 (0x0004u) +#define GPIO_PIBC10_PIBC103 (0x0008u) +#define GPIO_PIBC10_PIBC104 (0x0010u) +#define GPIO_PIBC10_PIBC105 (0x0020u) +#define GPIO_PIBC10_PIBC106 (0x0040u) +#define GPIO_PIBC10_PIBC107 (0x0080u) +#define GPIO_PIBC10_PIBC108 (0x0100u) +#define GPIO_PIBC10_PIBC109 (0x0200u) +#define GPIO_PIBC10_PIBC1010 (0x0400u) +#define GPIO_PIBC10_PIBC1011 (0x0800u) +#define GPIO_PIBC10_PIBC1012 (0x1000u) +#define GPIO_PIBC10_PIBC1013 (0x2000u) +#define GPIO_PIBC10_PIBC1014 (0x4000u) +#define GPIO_PIBC10_PIBC1015 (0x8000u) + +#define GPIO_PBDC10_PBDC100 (0x0001u) +#define GPIO_PBDC10_PBDC101 (0x0002u) +#define GPIO_PBDC10_PBDC102 (0x0004u) +#define GPIO_PBDC10_PBDC103 (0x0008u) +#define GPIO_PBDC10_PBDC104 (0x0010u) +#define GPIO_PBDC10_PBDC105 (0x0020u) +#define GPIO_PBDC10_PBDC106 (0x0040u) +#define GPIO_PBDC10_PBDC107 (0x0080u) +#define GPIO_PBDC10_PBDC108 (0x0100u) +#define GPIO_PBDC10_PBDC109 (0x0200u) +#define GPIO_PBDC10_PBDC1010 (0x0400u) +#define GPIO_PBDC10_PBDC1011 (0x0800u) +#define GPIO_PBDC10_PBDC1012 (0x1000u) +#define GPIO_PBDC10_PBDC1013 (0x2000u) +#define GPIO_PBDC10_PBDC1014 (0x4000u) +#define GPIO_PBDC10_PBDC1015 (0x8000u) + +#define GPIO_PIPC10_PIPC100 (0x0001u) +#define GPIO_PIPC10_PIPC101 (0x0002u) +#define GPIO_PIPC10_PIPC102 (0x0004u) +#define GPIO_PIPC10_PIPC103 (0x0008u) +#define GPIO_PIPC10_PIPC104 (0x0010u) +#define GPIO_PIPC10_PIPC105 (0x0020u) +#define GPIO_PIPC10_PIPC106 (0x0040u) +#define GPIO_PIPC10_PIPC107 (0x0080u) +#define GPIO_PIPC10_PIPC108 (0x0100u) +#define GPIO_PIPC10_PIPC109 (0x0200u) +#define GPIO_PIPC10_PIPC1010 (0x0400u) +#define GPIO_PIPC10_PIPC1011 (0x0800u) +#define GPIO_PIPC10_PIPC1012 (0x1000u) +#define GPIO_PIPC10_PIPC1013 (0x2000u) +#define GPIO_PIPC10_PIPC1014 (0x4000u) +#define GPIO_PIPC10_PIPC1015 (0x8000u) + +/* ---- P11 ---- */ +#define GPIO_P11_P110 (0x0001u) +#define GPIO_P11_P111 (0x0002u) +#define GPIO_P11_P112 (0x0004u) +#define GPIO_P11_P113 (0x0008u) +#define GPIO_P11_P114 (0x0010u) +#define GPIO_P11_P115 (0x0020u) +#define GPIO_P11_P116 (0x0040u) +#define GPIO_P11_P117 (0x0080u) +#define GPIO_P11_P118 (0x0100u) +#define GPIO_P11_P119 (0x0200u) +#define GPIO_P11_P1110 (0x0400u) +#define GPIO_P11_P1111 (0x0800u) +#define GPIO_P11_P1112 (0x1000u) +#define GPIO_P11_P1113 (0x2000u) +#define GPIO_P11_P1114 (0x4000u) +#define GPIO_P11_P1115 (0x8000u) + +#define GPIO_PSR11_PSR110 (0x00000001uL) +#define GPIO_PSR11_PSR111 (0x00000002uL) +#define GPIO_PSR11_PSR112 (0x00000004uL) +#define GPIO_PSR11_PSR113 (0x00000008uL) +#define GPIO_PSR11_PSR114 (0x00000010uL) +#define GPIO_PSR11_PSR115 (0x00000020uL) +#define GPIO_PSR11_PSR116 (0x00000040uL) +#define GPIO_PSR11_PSR117 (0x00000080uL) +#define GPIO_PSR11_PSR118 (0x00000100uL) +#define GPIO_PSR11_PSR119 (0x00000200uL) +#define GPIO_PSR11_PSR1110 (0x00000400uL) +#define GPIO_PSR11_PSR1111 (0x00000800uL) +#define GPIO_PSR11_PSR1112 (0x00001000uL) +#define GPIO_PSR11_PSR1113 (0x00002000uL) +#define GPIO_PSR11_PSR1114 (0x00004000uL) +#define GPIO_PSR11_PSR1115 (0x00008000uL) +#define GPIO_PSR11_PSR1116 (0x00010000uL) +#define GPIO_PSR11_PSR1117 (0x00020000uL) +#define GPIO_PSR11_PSR1118 (0x00040000uL) +#define GPIO_PSR11_PSR1119 (0x00080000uL) +#define GPIO_PSR11_PSR1120 (0x00100000uL) +#define GPIO_PSR11_PSR1121 (0x00200000uL) +#define GPIO_PSR11_PSR1122 (0x00400000uL) +#define GPIO_PSR11_PSR1123 (0x00800000uL) +#define GPIO_PSR11_PSR1124 (0x01000000uL) +#define GPIO_PSR11_PSR1125 (0x02000000uL) +#define GPIO_PSR11_PSR1126 (0x04000000uL) +#define GPIO_PSR11_PSR1127 (0x08000000uL) +#define GPIO_PSR11_PSR1128 (0x10000000uL) +#define GPIO_PSR11_PSR1129 (0x20000000uL) +#define GPIO_PSR11_PSR1130 (0x40000000uL) +#define GPIO_PSR11_PSR1131 (0x80000000uL) + +#define GPIO_PPR11_PPR110 (0x0001u) +#define GPIO_PPR11_PPR111 (0x0002u) +#define GPIO_PPR11_PPR112 (0x0004u) +#define GPIO_PPR11_PPR113 (0x0008u) +#define GPIO_PPR11_PPR114 (0x0010u) +#define GPIO_PPR11_PPR115 (0x0020u) +#define GPIO_PPR11_PPR116 (0x0040u) +#define GPIO_PPR11_PPR117 (0x0080u) +#define GPIO_PPR11_PPR118 (0x0100u) +#define GPIO_PPR11_PPR119 (0x0200u) +#define GPIO_PPR11_PPR1110 (0x0400u) +#define GPIO_PPR11_PPR1111 (0x0800u) +#define GPIO_PPR11_PPR1112 (0x1000u) +#define GPIO_PPR11_PPR1113 (0x2000u) +#define GPIO_PPR11_PPR1114 (0x4000u) +#define GPIO_PPR11_PPR1115 (0x8000u) + +#define GPIO_PM11_PM110 (0x0001u) +#define GPIO_PM11_PM111 (0x0002u) +#define GPIO_PM11_PM112 (0x0004u) +#define GPIO_PM11_PM113 (0x0008u) +#define GPIO_PM11_PM114 (0x0010u) +#define GPIO_PM11_PM115 (0x0020u) +#define GPIO_PM11_PM116 (0x0040u) +#define GPIO_PM11_PM117 (0x0080u) +#define GPIO_PM11_PM118 (0x0100u) +#define GPIO_PM11_PM119 (0x0200u) +#define GPIO_PM11_PM1110 (0x0400u) +#define GPIO_PM11_PM1111 (0x0800u) +#define GPIO_PM11_PM1112 (0x1000u) +#define GPIO_PM11_PM1113 (0x2000u) +#define GPIO_PM11_PM1114 (0x4000u) +#define GPIO_PM11_PM1115 (0x8000u) + +#define GPIO_PMC11_PMC110 (0x0001u) +#define GPIO_PMC11_PMC111 (0x0002u) +#define GPIO_PMC11_PMC112 (0x0004u) +#define GPIO_PMC11_PMC113 (0x0008u) +#define GPIO_PMC11_PMC114 (0x0010u) +#define GPIO_PMC11_PMC115 (0x0020u) +#define GPIO_PMC11_PMC116 (0x0040u) +#define GPIO_PMC11_PMC117 (0x0080u) +#define GPIO_PMC11_PMC118 (0x0100u) +#define GPIO_PMC11_PMC119 (0x0200u) +#define GPIO_PMC11_PMC1110 (0x0400u) +#define GPIO_PMC11_PMC1111 (0x0800u) +#define GPIO_PMC11_PMC1112 (0x1000u) +#define GPIO_PMC11_PMC1113 (0x2000u) +#define GPIO_PMC11_PMC1114 (0x4000u) +#define GPIO_PMC11_PMC1115 (0x8000u) + +#define GPIO_PFC11_PFC110 (0x0001u) +#define GPIO_PFC11_PFC111 (0x0002u) +#define GPIO_PFC11_PFC112 (0x0004u) +#define GPIO_PFC11_PFC113 (0x0008u) +#define GPIO_PFC11_PFC114 (0x0010u) +#define GPIO_PFC11_PFC115 (0x0020u) +#define GPIO_PFC11_PFC116 (0x0040u) +#define GPIO_PFC11_PFC117 (0x0080u) +#define GPIO_PFC11_PFC118 (0x0100u) +#define GPIO_PFC11_PFC119 (0x0200u) +#define GPIO_PFC11_PFC1110 (0x0400u) +#define GPIO_PFC11_PFC1111 (0x0800u) +#define GPIO_PFC11_PFC1112 (0x1000u) +#define GPIO_PFC11_PFC1113 (0x2000u) +#define GPIO_PFC11_PFC1114 (0x4000u) +#define GPIO_PFC11_PFC1115 (0x8000u) + +#define GPIO_PFCE11_PFCE110 (0x0001u) +#define GPIO_PFCE11_PFCE111 (0x0002u) +#define GPIO_PFCE11_PFCE112 (0x0004u) +#define GPIO_PFCE11_PFCE113 (0x0008u) +#define GPIO_PFCE11_PFCE114 (0x0010u) +#define GPIO_PFCE11_PFCE115 (0x0020u) +#define GPIO_PFCE11_PFCE116 (0x0040u) +#define GPIO_PFCE11_PFCE117 (0x0080u) +#define GPIO_PFCE11_PFCE118 (0x0100u) +#define GPIO_PFCE11_PFCE119 (0x0200u) +#define GPIO_PFCE11_PFCE1110 (0x0400u) +#define GPIO_PFCE11_PFCE1111 (0x0800u) +#define GPIO_PFCE11_PFCE1112 (0x1000u) +#define GPIO_PFCE11_PFCE1113 (0x2000u) +#define GPIO_PFCE11_PFCE1114 (0x4000u) +#define GPIO_PFCE11_PFCE1115 (0x8000u) + +#define GPIO_PNOT11_PNOT110 (0x0001u) +#define GPIO_PNOT11_PNOT111 (0x0002u) +#define GPIO_PNOT11_PNOT112 (0x0004u) +#define GPIO_PNOT11_PNOT113 (0x0008u) +#define GPIO_PNOT11_PNOT114 (0x0010u) +#define GPIO_PNOT11_PNOT115 (0x0020u) +#define GPIO_PNOT11_PNOT116 (0x0040u) +#define GPIO_PNOT11_PNOT117 (0x0080u) +#define GPIO_PNOT11_PNOT118 (0x0100u) +#define GPIO_PNOT11_PNOT119 (0x0200u) +#define GPIO_PNOT11_PNOT1110 (0x0400u) +#define GPIO_PNOT11_PNOT1111 (0x0800u) +#define GPIO_PNOT11_PNOT1112 (0x1000u) +#define GPIO_PNOT11_PNOT1113 (0x2000u) +#define GPIO_PNOT11_PNOT1114 (0x4000u) +#define GPIO_PNOT11_PNOT1115 (0x8000u) + +#define GPIO_PMSR11_PMSR110 (0x00000001uL) +#define GPIO_PMSR11_PMSR111 (0x00000002uL) +#define GPIO_PMSR11_PMSR112 (0x00000004uL) +#define GPIO_PMSR11_PMSR113 (0x00000008uL) +#define GPIO_PMSR11_PMSR114 (0x00000010uL) +#define GPIO_PMSR11_PMSR115 (0x00000020uL) +#define GPIO_PMSR11_PMSR116 (0x00000040uL) +#define GPIO_PMSR11_PMSR117 (0x00000080uL) +#define GPIO_PMSR11_PMSR118 (0x00000100uL) +#define GPIO_PMSR11_PMSR119 (0x00000200uL) +#define GPIO_PMSR11_PMSR1110 (0x00000400uL) +#define GPIO_PMSR11_PMSR1111 (0x00000800uL) +#define GPIO_PMSR11_PMSR1112 (0x00001000uL) +#define GPIO_PMSR11_PMSR1113 (0x00002000uL) +#define GPIO_PMSR11_PMSR1114 (0x00004000uL) +#define GPIO_PMSR11_PMSR1115 (0x00008000uL) +#define GPIO_PMSR11_PMSR1116 (0x00010000uL) +#define GPIO_PMSR11_PMSR1117 (0x00020000uL) +#define GPIO_PMSR11_PMSR1118 (0x00040000uL) +#define GPIO_PMSR11_PMSR1119 (0x00080000uL) +#define GPIO_PMSR11_PMSR1120 (0x00100000uL) +#define GPIO_PMSR11_PMSR1121 (0x00200000uL) +#define GPIO_PMSR11_PMSR1122 (0x00400000uL) +#define GPIO_PMSR11_PMSR1123 (0x00800000uL) +#define GPIO_PMSR11_PMSR1124 (0x01000000uL) +#define GPIO_PMSR11_PMSR1125 (0x02000000uL) +#define GPIO_PMSR11_PMSR1126 (0x04000000uL) +#define GPIO_PMSR11_PMSR1127 (0x08000000uL) +#define GPIO_PMSR11_PMSR1128 (0x10000000uL) +#define GPIO_PMSR11_PMSR1129 (0x20000000uL) +#define GPIO_PMSR11_PMSR1130 (0x40000000uL) +#define GPIO_PMSR11_PMSR1131 (0x80000000uL) + +#define GPIO_PMCSR11_PMCSR110 (0x00000001uL) +#define GPIO_PMCSR11_PMCSR111 (0x00000002uL) +#define GPIO_PMCSR11_PMCSR112 (0x00000004uL) +#define GPIO_PMCSR11_PMCSR113 (0x00000008uL) +#define GPIO_PMCSR11_PMCSR114 (0x00000010uL) +#define GPIO_PMCSR11_PMCSR115 (0x00000020uL) +#define GPIO_PMCSR11_PMCSR116 (0x00000040uL) +#define GPIO_PMCSR11_PMCSR117 (0x00000080uL) +#define GPIO_PMCSR11_PMCSR118 (0x00000100uL) +#define GPIO_PMCSR11_PMCSR119 (0x00000200uL) +#define GPIO_PMCSR11_PMCSR1110 (0x00000400uL) +#define GPIO_PMCSR11_PMCSR1111 (0x00000800uL) +#define GPIO_PMCSR11_PMCSR1112 (0x00001000uL) +#define GPIO_PMCSR11_PMCSR1113 (0x00002000uL) +#define GPIO_PMCSR11_PMCSR1114 (0x00004000uL) +#define GPIO_PMCSR11_PMCSR1115 (0x00008000uL) +#define GPIO_PMCSR11_PMCSR1116 (0x00010000uL) +#define GPIO_PMCSR11_PMCSR1117 (0x00020000uL) +#define GPIO_PMCSR11_PMCSR1118 (0x00040000uL) +#define GPIO_PMCSR11_PMCSR1119 (0x00080000uL) +#define GPIO_PMCSR11_PMCSR1120 (0x00100000uL) +#define GPIO_PMCSR11_PMCSR1121 (0x00200000uL) +#define GPIO_PMCSR11_PMCSR1122 (0x00400000uL) +#define GPIO_PMCSR11_PMCSR1123 (0x00800000uL) +#define GPIO_PMCSR11_PMCSR1124 (0x01000000uL) +#define GPIO_PMCSR11_PMCSR1125 (0x02000000uL) +#define GPIO_PMCSR11_PMCSR1126 (0x04000000uL) +#define GPIO_PMCSR11_PMCSR1127 (0x08000000uL) +#define GPIO_PMCSR11_PMCSR1128 (0x10000000uL) +#define GPIO_PMCSR11_PMCSR1129 (0x20000000uL) +#define GPIO_PMCSR11_PMCSR1130 (0x40000000uL) +#define GPIO_PMCSR11_PMCSR1131 (0x80000000uL) + +#define GPIO_PFCAE11_PFCAE110 (0x0001u) +#define GPIO_PFCAE11_PFCAE111 (0x0002u) +#define GPIO_PFCAE11_PFCAE112 (0x0004u) +#define GPIO_PFCAE11_PFCAE113 (0x0008u) +#define GPIO_PFCAE11_PFCAE114 (0x0010u) +#define GPIO_PFCAE11_PFCAE115 (0x0020u) +#define GPIO_PFCAE11_PFCAE116 (0x0040u) +#define GPIO_PFCAE11_PFCAE117 (0x0080u) +#define GPIO_PFCAE11_PFCAE118 (0x0100u) +#define GPIO_PFCAE11_PFCAE119 (0x0200u) +#define GPIO_PFCAE11_PFCAE1110 (0x0400u) +#define GPIO_PFCAE11_PFCAE1111 (0x0800u) +#define GPIO_PFCAE11_PFCAE1112 (0x1000u) +#define GPIO_PFCAE11_PFCAE1113 (0x2000u) +#define GPIO_PFCAE11_PFCAE1114 (0x4000u) +#define GPIO_PFCAE11_PFCAE1115 (0x8000u) + +#define GPIO_PIBC11_PIBC110 (0x0001u) +#define GPIO_PIBC11_PIBC111 (0x0002u) +#define GPIO_PIBC11_PIBC112 (0x0004u) +#define GPIO_PIBC11_PIBC113 (0x0008u) +#define GPIO_PIBC11_PIBC114 (0x0010u) +#define GPIO_PIBC11_PIBC115 (0x0020u) +#define GPIO_PIBC11_PIBC116 (0x0040u) +#define GPIO_PIBC11_PIBC117 (0x0080u) +#define GPIO_PIBC11_PIBC118 (0x0100u) +#define GPIO_PIBC11_PIBC119 (0x0200u) +#define GPIO_PIBC11_PIBC1110 (0x0400u) +#define GPIO_PIBC11_PIBC1111 (0x0800u) +#define GPIO_PIBC11_PIBC1112 (0x1000u) +#define GPIO_PIBC11_PIBC1113 (0x2000u) +#define GPIO_PIBC11_PIBC1114 (0x4000u) +#define GPIO_PIBC11_PIBC1115 (0x8000u) + +#define GPIO_PBDC11_PBDC110 (0x0001u) +#define GPIO_PBDC11_PBDC111 (0x0002u) +#define GPIO_PBDC11_PBDC112 (0x0004u) +#define GPIO_PBDC11_PBDC113 (0x0008u) +#define GPIO_PBDC11_PBDC114 (0x0010u) +#define GPIO_PBDC11_PBDC115 (0x0020u) +#define GPIO_PBDC11_PBDC116 (0x0040u) +#define GPIO_PBDC11_PBDC117 (0x0080u) +#define GPIO_PBDC11_PBDC118 (0x0100u) +#define GPIO_PBDC11_PBDC119 (0x0200u) +#define GPIO_PBDC11_PBDC1110 (0x0400u) +#define GPIO_PBDC11_PBDC1111 (0x0800u) +#define GPIO_PBDC11_PBDC1112 (0x1000u) +#define GPIO_PBDC11_PBDC1113 (0x2000u) +#define GPIO_PBDC11_PBDC1114 (0x4000u) +#define GPIO_PBDC11_PBDC1115 (0x8000u) + +#define GPIO_PIPC11_PIPC110 (0x0001u) +#define GPIO_PIPC11_PIPC111 (0x0002u) +#define GPIO_PIPC11_PIPC112 (0x0004u) +#define GPIO_PIPC11_PIPC113 (0x0008u) +#define GPIO_PIPC11_PIPC114 (0x0010u) +#define GPIO_PIPC11_PIPC115 (0x0020u) +#define GPIO_PIPC11_PIPC116 (0x0040u) +#define GPIO_PIPC11_PIPC117 (0x0080u) +#define GPIO_PIPC11_PIPC118 (0x0100u) +#define GPIO_PIPC11_PIPC119 (0x0200u) +#define GPIO_PIPC11_PIPC1110 (0x0400u) +#define GPIO_PIPC11_PIPC1111 (0x0800u) +#define GPIO_PIPC11_PIPC1112 (0x1000u) +#define GPIO_PIPC11_PIPC1113 (0x2000u) +#define GPIO_PIPC11_PIPC1114 (0x4000u) +#define GPIO_PIPC11_PIPC1115 (0x8000u) + + +/* ==== Shift values for IO registers ==== */ +/* ---- P0 ---- */ +#define GPIO_PPR0_PPR00_SHIFT (0u) +#define GPIO_PPR0_PPR01_SHIFT (1u) +#define GPIO_PPR0_PPR02_SHIFT (2u) +#define GPIO_PPR0_PPR03_SHIFT (3u) +#define GPIO_PPR0_PPR04_SHIFT (4u) +#define GPIO_PPR0_PPR05_SHIFT (5u) + +#define GPIO_PMC0_PMC04_SHIFT (4u) +#define GPIO_PMC0_PMC05_SHIFT (5u) + +#define GPIO_PMCSR0_PMCSR04_SHIFT (4u) +#define GPIO_PMCSR0_PMCSR05_SHIFT (5u) + +#define GPIO_PIBC0_PIBC00_SHIFT (0u) +#define GPIO_PIBC0_PIBC01_SHIFT (1u) +#define GPIO_PIBC0_PIBC02_SHIFT (2u) +#define GPIO_PIBC0_PIBC03_SHIFT (3u) +#define GPIO_PIBC0_PIBC04_SHIFT (4u) +#define GPIO_PIBC0_PIBC05_SHIFT (5u) + +/* ---- P1 ---- */ +#define GPIO_P1_P10_SHIFT (0u) +#define GPIO_P1_P11_SHIFT (1u) +#define GPIO_P1_P12_SHIFT (2u) +#define GPIO_P1_P13_SHIFT (3u) +#define GPIO_P1_P14_SHIFT (4u) +#define GPIO_P1_P15_SHIFT (5u) +#define GPIO_P1_P16_SHIFT (6u) +#define GPIO_P1_P17_SHIFT (7u) + +#define GPIO_PSR1_PSR10_SHIFT (0u) +#define GPIO_PSR1_PSR11_SHIFT (1u) +#define GPIO_PSR1_PSR12_SHIFT (2u) +#define GPIO_PSR1_PSR13_SHIFT (3u) +#define GPIO_PSR1_PSR14_SHIFT (4u) +#define GPIO_PSR1_PSR15_SHIFT (5u) +#define GPIO_PSR1_PSR16_SHIFT (6u) +#define GPIO_PSR1_PSR17_SHIFT (7u) +#define GPIO_PSR1_PSR116_SHIFT (16u) +#define GPIO_PSR1_PSR117_SHIFT (17u) +#define GPIO_PSR1_PSR118_SHIFT (18u) +#define GPIO_PSR1_PSR119_SHIFT (19u) +#define GPIO_PSR1_PSR120_SHIFT (20u) +#define GPIO_PSR1_PSR121_SHIFT (21u) +#define GPIO_PSR1_PSR122_SHIFT (22u) +#define GPIO_PSR1_PSR123_SHIFT (23u) + +#define GPIO_PPR1_PPR10_SHIFT (0u) +#define GPIO_PPR1_PPR11_SHIFT (1u) +#define GPIO_PPR1_PPR12_SHIFT (2u) +#define GPIO_PPR1_PPR13_SHIFT (3u) +#define GPIO_PPR1_PPR14_SHIFT (4u) +#define GPIO_PPR1_PPR15_SHIFT (5u) +#define GPIO_PPR1_PPR16_SHIFT (6u) +#define GPIO_PPR1_PPR17_SHIFT (7u) +#define GPIO_PPR1_PPR18_SHIFT (8u) +#define GPIO_PPR1_PPR19_SHIFT (9u) +#define GPIO_PPR1_PPR110_SHIFT (10u) +#define GPIO_PPR1_PPR111_SHIFT (11u) +#define GPIO_PPR1_PPR112_SHIFT (12u) +#define GPIO_PPR1_PPR113_SHIFT (13u) +#define GPIO_PPR1_PPR114_SHIFT (14u) +#define GPIO_PPR1_PPR115_SHIFT (15u) + +#define GPIO_PM1_PM10_SHIFT (0u) +#define GPIO_PM1_PM11_SHIFT (1u) +#define GPIO_PM1_PM12_SHIFT (2u) +#define GPIO_PM1_PM13_SHIFT (3u) +#define GPIO_PM1_PM14_SHIFT (4u) +#define GPIO_PM1_PM15_SHIFT (5u) +#define GPIO_PM1_PM16_SHIFT (6u) +#define GPIO_PM1_PM17_SHIFT (7u) + +#define GPIO_PMC1_PMC10_SHIFT (0u) +#define GPIO_PMC1_PMC11_SHIFT (1u) +#define GPIO_PMC1_PMC12_SHIFT (2u) +#define GPIO_PMC1_PMC13_SHIFT (3u) +#define GPIO_PMC1_PMC14_SHIFT (4u) +#define GPIO_PMC1_PMC15_SHIFT (5u) +#define GPIO_PMC1_PMC16_SHIFT (6u) +#define GPIO_PMC1_PMC17_SHIFT (7u) +#define GPIO_PMC1_PMC18_SHIFT (8u) +#define GPIO_PMC1_PMC19_SHIFT (9u) +#define GPIO_PMC1_PMC110_SHIFT (10u) +#define GPIO_PMC1_PMC111_SHIFT (11u) +#define GPIO_PMC1_PMC112_SHIFT (12u) +#define GPIO_PMC1_PMC113_SHIFT (13u) +#define GPIO_PMC1_PMC114_SHIFT (14u) +#define GPIO_PMC1_PMC115_SHIFT (15u) + +#define GPIO_PFC1_PFC10_SHIFT (0u) +#define GPIO_PFC1_PFC11_SHIFT (1u) +#define GPIO_PFC1_PFC12_SHIFT (2u) +#define GPIO_PFC1_PFC13_SHIFT (3u) +#define GPIO_PFC1_PFC14_SHIFT (4u) +#define GPIO_PFC1_PFC15_SHIFT (5u) +#define GPIO_PFC1_PFC16_SHIFT (6u) +#define GPIO_PFC1_PFC17_SHIFT (7u) +#define GPIO_PFC1_PFC18_SHIFT (8u) +#define GPIO_PFC1_PFC19_SHIFT (9u) +#define GPIO_PFC1_PFC110_SHIFT (10u) +#define GPIO_PFC1_PFC111_SHIFT (11u) +#define GPIO_PFC1_PFC112_SHIFT (12u) +#define GPIO_PFC1_PFC113_SHIFT (13u) +#define GPIO_PFC1_PFC114_SHIFT (14u) +#define GPIO_PFC1_PFC115_SHIFT (15u) + +#define GPIO_PFCE1_PFCE10_SHIFT (0u) +#define GPIO_PFCE1_PFCE11_SHIFT (1u) +#define GPIO_PFCE1_PFCE12_SHIFT (2u) +#define GPIO_PFCE1_PFCE13_SHIFT (3u) +#define GPIO_PFCE1_PFCE14_SHIFT (4u) +#define GPIO_PFCE1_PFCE15_SHIFT (5u) +#define GPIO_PFCE1_PFCE16_SHIFT (6u) +#define GPIO_PFCE1_PFCE17_SHIFT (7u) +#define GPIO_PFCE1_PFCE18_SHIFT (8u) +#define GPIO_PFCE1_PFCE19_SHIFT (9u) +#define GPIO_PFCE1_PFCE110_SHIFT (10u) +#define GPIO_PFCE1_PFCE111_SHIFT (11u) +#define GPIO_PFCE1_PFCE112_SHIFT (12u) +#define GPIO_PFCE1_PFCE113_SHIFT (13u) +#define GPIO_PFCE1_PFCE114_SHIFT (14u) +#define GPIO_PFCE1_PFCE115_SHIFT (15u) + +#define GPIO_PNOT1_PNOT10_SHIFT (0u) +#define GPIO_PNOT1_PNOT11_SHIFT (1u) +#define GPIO_PNOT1_PNOT12_SHIFT (2u) +#define GPIO_PNOT1_PNOT13_SHIFT (3u) +#define GPIO_PNOT1_PNOT14_SHIFT (4u) +#define GPIO_PNOT1_PNOT15_SHIFT (5u) +#define GPIO_PNOT1_PNOT16_SHIFT (6u) +#define GPIO_PNOT1_PNOT17_SHIFT (7u) + +#define GPIO_PMSR1_PMSR10_SHIFT (0u) +#define GPIO_PMSR1_PMSR11_SHIFT (1u) +#define GPIO_PMSR1_PMSR12_SHIFT (2u) +#define GPIO_PMSR1_PMSR13_SHIFT (3u) +#define GPIO_PMSR1_PMSR14_SHIFT (4u) +#define GPIO_PMSR1_PMSR15_SHIFT (5u) +#define GPIO_PMSR1_PMSR16_SHIFT (6u) +#define GPIO_PMSR1_PMSR17_SHIFT (7u) +#define GPIO_PMSR1_PMSR116_SHIFT (16u) +#define GPIO_PMSR1_PMSR117_SHIFT (17u) +#define GPIO_PMSR1_PMSR118_SHIFT (18u) +#define GPIO_PMSR1_PMSR119_SHIFT (19u) +#define GPIO_PMSR1_PMSR120_SHIFT (20u) +#define GPIO_PMSR1_PMSR121_SHIFT (21u) +#define GPIO_PMSR1_PMSR122_SHIFT (22u) +#define GPIO_PMSR1_PMSR123_SHIFT (23u) + +#define GPIO_PMCSR1_PMCSR10_SHIFT (0u) +#define GPIO_PMCSR1_PMCSR11_SHIFT (1u) +#define GPIO_PMCSR1_PMCSR12_SHIFT (2u) +#define GPIO_PMCSR1_PMCSR13_SHIFT (3u) +#define GPIO_PMCSR1_PMCSR14_SHIFT (4u) +#define GPIO_PMCSR1_PMCSR15_SHIFT (5u) +#define GPIO_PMCSR1_PMCSR16_SHIFT (6u) +#define GPIO_PMCSR1_PMCSR17_SHIFT (7u) +#define GPIO_PMCSR1_PMCSR116_SHIFT (16u) +#define GPIO_PMCSR1_PMCSR117_SHIFT (17u) +#define GPIO_PMCSR1_PMCSR118_SHIFT (18u) +#define GPIO_PMCSR1_PMCSR119_SHIFT (19u) +#define GPIO_PMCSR1_PMCSR120_SHIFT (20u) +#define GPIO_PMCSR1_PMCSR121_SHIFT (21u) +#define GPIO_PMCSR1_PMCSR122_SHIFT (22u) +#define GPIO_PMCSR1_PMCSR123_SHIFT (23u) + +#define GPIO_PFCAE1_PFCAE10_SHIFT (0u) +#define GPIO_PFCAE1_PFCAE11_SHIFT (1u) +#define GPIO_PFCAE1_PFCAE12_SHIFT (2u) +#define GPIO_PFCAE1_PFCAE13_SHIFT (3u) +#define GPIO_PFCAE1_PFCAE14_SHIFT (4u) +#define GPIO_PFCAE1_PFCAE15_SHIFT (5u) +#define GPIO_PFCAE1_PFCAE16_SHIFT (6u) +#define GPIO_PFCAE1_PFCAE17_SHIFT (7u) +#define GPIO_PFCAE1_PFCAE18_SHIFT (8u) +#define GPIO_PFCAE1_PFCAE19_SHIFT (9u) +#define GPIO_PFCAE1_PFCAE110_SHIFT (10u) +#define GPIO_PFCAE1_PFCAE111_SHIFT (11u) +#define GPIO_PFCAE1_PFCAE112_SHIFT (12u) +#define GPIO_PFCAE1_PFCAE113_SHIFT (13u) +#define GPIO_PFCAE1_PFCAE114_SHIFT (14u) +#define GPIO_PFCAE1_PFCAE115_SHIFT (15u) + +#define GPIO_PIBC1_PIBC10_SHIFT (0u) +#define GPIO_PIBC1_PIBC11_SHIFT (1u) +#define GPIO_PIBC1_PIBC12_SHIFT (2u) +#define GPIO_PIBC1_PIBC13_SHIFT (3u) +#define GPIO_PIBC1_PIBC14_SHIFT (4u) +#define GPIO_PIBC1_PIBC15_SHIFT (5u) +#define GPIO_PIBC1_PIBC16_SHIFT (6u) +#define GPIO_PIBC1_PIBC17_SHIFT (7u) +#define GPIO_PIBC1_PIBC18_SHIFT (8u) +#define GPIO_PIBC1_PIBC19_SHIFT (9u) +#define GPIO_PIBC1_PIBC110_SHIFT (10u) +#define GPIO_PIBC1_PIBC111_SHIFT (11u) +#define GPIO_PIBC1_PIBC112_SHIFT (12u) +#define GPIO_PIBC1_PIBC113_SHIFT (13u) +#define GPIO_PIBC1_PIBC114_SHIFT (14u) +#define GPIO_PIBC1_PIBC115_SHIFT (15u) + +#define GPIO_PBDC1_PBDC10_SHIFT (0u) +#define GPIO_PBDC1_PBDC11_SHIFT (1u) +#define GPIO_PBDC1_PBDC12_SHIFT (2u) +#define GPIO_PBDC1_PBDC13_SHIFT (3u) +#define GPIO_PBDC1_PBDC14_SHIFT (4u) +#define GPIO_PBDC1_PBDC15_SHIFT (5u) +#define GPIO_PBDC1_PBDC16_SHIFT (6u) +#define GPIO_PBDC1_PBDC17_SHIFT (7u) +#define GPIO_PBDC1_PBDC18_SHIFT (8u) +#define GPIO_PBDC1_PBDC19_SHIFT (9u) +#define GPIO_PBDC1_PBDC110_SHIFT (10u) +#define GPIO_PBDC1_PBDC111_SHIFT (11u) +#define GPIO_PBDC1_PBDC112_SHIFT (12u) +#define GPIO_PBDC1_PBDC113_SHIFT (13u) +#define GPIO_PBDC1_PBDC114_SHIFT (14u) +#define GPIO_PBDC1_PBDC115_SHIFT (15u) + +#define GPIO_PIPC1_PIPC10_SHIFT (0u) +#define GPIO_PIPC1_PIPC11_SHIFT (1u) +#define GPIO_PIPC1_PIPC12_SHIFT (2u) +#define GPIO_PIPC1_PIPC13_SHIFT (3u) +#define GPIO_PIPC1_PIPC14_SHIFT (4u) +#define GPIO_PIPC1_PIPC15_SHIFT (5u) +#define GPIO_PIPC1_PIPC16_SHIFT (6u) +#define GPIO_PIPC1_PIPC17_SHIFT (7u) + +/* ---- P2 ---- */ +#define GPIO_P2_P20_SHIFT (0u) +#define GPIO_P2_P21_SHIFT (1u) +#define GPIO_P2_P22_SHIFT (2u) +#define GPIO_P2_P23_SHIFT (3u) +#define GPIO_P2_P24_SHIFT (4u) +#define GPIO_P2_P25_SHIFT (5u) +#define GPIO_P2_P26_SHIFT (6u) +#define GPIO_P2_P27_SHIFT (7u) +#define GPIO_P2_P28_SHIFT (8u) +#define GPIO_P2_P29_SHIFT (9u) +#define GPIO_P2_P210_SHIFT (10u) +#define GPIO_P2_P211_SHIFT (11u) +#define GPIO_P2_P212_SHIFT (12u) +#define GPIO_P2_P213_SHIFT (13u) +#define GPIO_P2_P214_SHIFT (14u) +#define GPIO_P2_P215_SHIFT (15u) + +#define GPIO_PSR2_PSR20_SHIFT (0u) +#define GPIO_PSR2_PSR21_SHIFT (1u) +#define GPIO_PSR2_PSR22_SHIFT (2u) +#define GPIO_PSR2_PSR23_SHIFT (3u) +#define GPIO_PSR2_PSR24_SHIFT (4u) +#define GPIO_PSR2_PSR25_SHIFT (5u) +#define GPIO_PSR2_PSR26_SHIFT (6u) +#define GPIO_PSR2_PSR27_SHIFT (7u) +#define GPIO_PSR2_PSR28_SHIFT (8u) +#define GPIO_PSR2_PSR29_SHIFT (9u) +#define GPIO_PSR2_PSR210_SHIFT (10u) +#define GPIO_PSR2_PSR211_SHIFT (11u) +#define GPIO_PSR2_PSR212_SHIFT (12u) +#define GPIO_PSR2_PSR213_SHIFT (13u) +#define GPIO_PSR2_PSR214_SHIFT (14u) +#define GPIO_PSR2_PSR215_SHIFT (15u) +#define GPIO_PSR2_PSR216_SHIFT (16u) +#define GPIO_PSR2_PSR217_SHIFT (17u) +#define GPIO_PSR2_PSR218_SHIFT (18u) +#define GPIO_PSR2_PSR219_SHIFT (19u) +#define GPIO_PSR2_PSR220_SHIFT (20u) +#define GPIO_PSR2_PSR221_SHIFT (21u) +#define GPIO_PSR2_PSR222_SHIFT (22u) +#define GPIO_PSR2_PSR223_SHIFT (23u) +#define GPIO_PSR2_PSR224_SHIFT (24u) +#define GPIO_PSR2_PSR225_SHIFT (25u) +#define GPIO_PSR2_PSR226_SHIFT (26u) +#define GPIO_PSR2_PSR227_SHIFT (27u) +#define GPIO_PSR2_PSR228_SHIFT (28u) +#define GPIO_PSR2_PSR229_SHIFT (29u) +#define GPIO_PSR2_PSR230_SHIFT (30u) +#define GPIO_PSR2_PSR231_SHIFT (31u) + +#define GPIO_PPR2_PPR20_SHIFT (0u) +#define GPIO_PPR2_PPR21_SHIFT (1u) +#define GPIO_PPR2_PPR22_SHIFT (2u) +#define GPIO_PPR2_PPR23_SHIFT (3u) +#define GPIO_PPR2_PPR24_SHIFT (4u) +#define GPIO_PPR2_PPR25_SHIFT (5u) +#define GPIO_PPR2_PPR26_SHIFT (6u) +#define GPIO_PPR2_PPR27_SHIFT (7u) +#define GPIO_PPR2_PPR28_SHIFT (8u) +#define GPIO_PPR2_PPR29_SHIFT (9u) +#define GPIO_PPR2_PPR210_SHIFT (10u) +#define GPIO_PPR2_PPR211_SHIFT (11u) +#define GPIO_PPR2_PPR212_SHIFT (12u) +#define GPIO_PPR2_PPR213_SHIFT (13u) +#define GPIO_PPR2_PPR214_SHIFT (14u) +#define GPIO_PPR2_PPR215_SHIFT (15u) + +#define GPIO_PM2_PM20_SHIFT (0u) +#define GPIO_PM2_PM21_SHIFT (1u) +#define GPIO_PM2_PM22_SHIFT (2u) +#define GPIO_PM2_PM23_SHIFT (3u) +#define GPIO_PM2_PM24_SHIFT (4u) +#define GPIO_PM2_PM25_SHIFT (5u) +#define GPIO_PM2_PM26_SHIFT (6u) +#define GPIO_PM2_PM27_SHIFT (7u) +#define GPIO_PM2_PM28_SHIFT (8u) +#define GPIO_PM2_PM29_SHIFT (9u) +#define GPIO_PM2_PM210_SHIFT (10u) +#define GPIO_PM2_PM211_SHIFT (11u) +#define GPIO_PM2_PM212_SHIFT (12u) +#define GPIO_PM2_PM213_SHIFT (13u) +#define GPIO_PM2_PM214_SHIFT (14u) +#define GPIO_PM2_PM215_SHIFT (15u) + +#define GPIO_PMC2_PMC20_SHIFT (0u) +#define GPIO_PMC2_PMC21_SHIFT (1u) +#define GPIO_PMC2_PMC22_SHIFT (2u) +#define GPIO_PMC2_PMC23_SHIFT (3u) +#define GPIO_PMC2_PMC24_SHIFT (4u) +#define GPIO_PMC2_PMC25_SHIFT (5u) +#define GPIO_PMC2_PMC26_SHIFT (6u) +#define GPIO_PMC2_PMC27_SHIFT (7u) +#define GPIO_PMC2_PMC28_SHIFT (8u) +#define GPIO_PMC2_PMC29_SHIFT (9u) +#define GPIO_PMC2_PMC210_SHIFT (10u) +#define GPIO_PMC2_PMC211_SHIFT (11u) +#define GPIO_PMC2_PMC212_SHIFT (12u) +#define GPIO_PMC2_PMC213_SHIFT (13u) +#define GPIO_PMC2_PMC214_SHIFT (14u) +#define GPIO_PMC2_PMC215_SHIFT (15u) + +#define GPIO_PFC2_PFC20_SHIFT (0u) +#define GPIO_PFC2_PFC21_SHIFT (1u) +#define GPIO_PFC2_PFC22_SHIFT (2u) +#define GPIO_PFC2_PFC23_SHIFT (3u) +#define GPIO_PFC2_PFC24_SHIFT (4u) +#define GPIO_PFC2_PFC25_SHIFT (5u) +#define GPIO_PFC2_PFC26_SHIFT (6u) +#define GPIO_PFC2_PFC27_SHIFT (7u) +#define GPIO_PFC2_PFC28_SHIFT (8u) +#define GPIO_PFC2_PFC29_SHIFT (9u) +#define GPIO_PFC2_PFC210_SHIFT (10u) +#define GPIO_PFC2_PFC211_SHIFT (11u) +#define GPIO_PFC2_PFC212_SHIFT (12u) +#define GPIO_PFC2_PFC213_SHIFT (13u) +#define GPIO_PFC2_PFC214_SHIFT (14u) +#define GPIO_PFC2_PFC215_SHIFT (15u) + +#define GPIO_PFCE2_PFCE20_SHIFT (0u) +#define GPIO_PFCE2_PFCE21_SHIFT (1u) +#define GPIO_PFCE2_PFCE22_SHIFT (2u) +#define GPIO_PFCE2_PFCE23_SHIFT (3u) +#define GPIO_PFCE2_PFCE24_SHIFT (4u) +#define GPIO_PFCE2_PFCE25_SHIFT (5u) +#define GPIO_PFCE2_PFCE26_SHIFT (6u) +#define GPIO_PFCE2_PFCE27_SHIFT (7u) +#define GPIO_PFCE2_PFCE28_SHIFT (8u) +#define GPIO_PFCE2_PFCE29_SHIFT (9u) +#define GPIO_PFCE2_PFCE210_SHIFT (10u) +#define GPIO_PFCE2_PFCE211_SHIFT (11u) +#define GPIO_PFCE2_PFCE212_SHIFT (12u) +#define GPIO_PFCE2_PFCE213_SHIFT (13u) +#define GPIO_PFCE2_PFCE214_SHIFT (14u) +#define GPIO_PFCE2_PFCE215_SHIFT (15u) + +#define GPIO_PNOT2_PNOT20_SHIFT (0u) +#define GPIO_PNOT2_PNOT21_SHIFT (1u) +#define GPIO_PNOT2_PNOT22_SHIFT (2u) +#define GPIO_PNOT2_PNOT23_SHIFT (3u) +#define GPIO_PNOT2_PNOT24_SHIFT (4u) +#define GPIO_PNOT2_PNOT25_SHIFT (5u) +#define GPIO_PNOT2_PNOT26_SHIFT (6u) +#define GPIO_PNOT2_PNOT27_SHIFT (7u) +#define GPIO_PNOT2_PNOT28_SHIFT (8u) +#define GPIO_PNOT2_PNOT29_SHIFT (9u) +#define GPIO_PNOT2_PNOT210_SHIFT (10u) +#define GPIO_PNOT2_PNOT211_SHIFT (11u) +#define GPIO_PNOT2_PNOT212_SHIFT (12u) +#define GPIO_PNOT2_PNOT213_SHIFT (13u) +#define GPIO_PNOT2_PNOT214_SHIFT (14u) +#define GPIO_PNOT2_PNOT215_SHIFT (15u) + +#define GPIO_PMSR2_PMSR20_SHIFT (0u) +#define GPIO_PMSR2_PMSR21_SHIFT (1u) +#define GPIO_PMSR2_PMSR22_SHIFT (2u) +#define GPIO_PMSR2_PMSR23_SHIFT (3u) +#define GPIO_PMSR2_PMSR24_SHIFT (4u) +#define GPIO_PMSR2_PMSR25_SHIFT (5u) +#define GPIO_PMSR2_PMSR26_SHIFT (6u) +#define GPIO_PMSR2_PMSR27_SHIFT (7u) +#define GPIO_PMSR2_PMSR28_SHIFT (8u) +#define GPIO_PMSR2_PMSR29_SHIFT (9u) +#define GPIO_PMSR2_PMSR210_SHIFT (10u) +#define GPIO_PMSR2_PMSR211_SHIFT (11u) +#define GPIO_PMSR2_PMSR212_SHIFT (12u) +#define GPIO_PMSR2_PMSR213_SHIFT (13u) +#define GPIO_PMSR2_PMSR214_SHIFT (14u) +#define GPIO_PMSR2_PMSR215_SHIFT (15u) +#define GPIO_PMSR2_PMSR216_SHIFT (16u) +#define GPIO_PMSR2_PMSR217_SHIFT (17u) +#define GPIO_PMSR2_PMSR218_SHIFT (18u) +#define GPIO_PMSR2_PMSR219_SHIFT (19u) +#define GPIO_PMSR2_PMSR220_SHIFT (20u) +#define GPIO_PMSR2_PMSR221_SHIFT (21u) +#define GPIO_PMSR2_PMSR222_SHIFT (22u) +#define GPIO_PMSR2_PMSR223_SHIFT (23u) +#define GPIO_PMSR2_PMSR224_SHIFT (24u) +#define GPIO_PMSR2_PMSR225_SHIFT (25u) +#define GPIO_PMSR2_PMSR226_SHIFT (26u) +#define GPIO_PMSR2_PMSR227_SHIFT (27u) +#define GPIO_PMSR2_PMSR228_SHIFT (28u) +#define GPIO_PMSR2_PMSR229_SHIFT (29u) +#define GPIO_PMSR2_PMSR230_SHIFT (30u) +#define GPIO_PMSR2_PMSR231_SHIFT (31u) + +#define GPIO_PMCSR2_PMCSR20_SHIFT (0u) +#define GPIO_PMCSR2_PMCSR21_SHIFT (1u) +#define GPIO_PMCSR2_PMCSR22_SHIFT (2u) +#define GPIO_PMCSR2_PMCSR23_SHIFT (3u) +#define GPIO_PMCSR2_PMCSR24_SHIFT (4u) +#define GPIO_PMCSR2_PMCSR25_SHIFT (5u) +#define GPIO_PMCSR2_PMCSR26_SHIFT (6u) +#define GPIO_PMCSR2_PMCSR27_SHIFT (7u) +#define GPIO_PMCSR2_PMCSR28_SHIFT (8u) +#define GPIO_PMCSR2_PMCSR29_SHIFT (9u) +#define GPIO_PMCSR2_PMCSR210_SHIFT (10u) +#define GPIO_PMCSR2_PMCSR211_SHIFT (11u) +#define GPIO_PMCSR2_PMCSR212_SHIFT (12u) +#define GPIO_PMCSR2_PMCSR213_SHIFT (13u) +#define GPIO_PMCSR2_PMCSR214_SHIFT (14u) +#define GPIO_PMCSR2_PMCSR215_SHIFT (15u) +#define GPIO_PMCSR2_PMCSR216_SHIFT (16u) +#define GPIO_PMCSR2_PMCSR217_SHIFT (17u) +#define GPIO_PMCSR2_PMCSR218_SHIFT (18u) +#define GPIO_PMCSR2_PMCSR219_SHIFT (19u) +#define GPIO_PMCSR2_PMCSR220_SHIFT (20u) +#define GPIO_PMCSR2_PMCSR221_SHIFT (21u) +#define GPIO_PMCSR2_PMCSR222_SHIFT (22u) +#define GPIO_PMCSR2_PMCSR223_SHIFT (23u) +#define GPIO_PMCSR2_PMCSR224_SHIFT (24u) +#define GPIO_PMCSR2_PMCSR225_SHIFT (25u) +#define GPIO_PMCSR2_PMCSR226_SHIFT (26u) +#define GPIO_PMCSR2_PMCSR227_SHIFT (27u) +#define GPIO_PMCSR2_PMCSR228_SHIFT (28u) +#define GPIO_PMCSR2_PMCSR229_SHIFT (29u) +#define GPIO_PMCSR2_PMCSR230_SHIFT (30u) +#define GPIO_PMCSR2_PMCSR231_SHIFT (31u) + +#define GPIO_PFCAE2_PFCAE20_SHIFT (0u) +#define GPIO_PFCAE2_PFCAE21_SHIFT (1u) +#define GPIO_PFCAE2_PFCAE22_SHIFT (2u) +#define GPIO_PFCAE2_PFCAE23_SHIFT (3u) +#define GPIO_PFCAE2_PFCAE24_SHIFT (4u) +#define GPIO_PFCAE2_PFCAE25_SHIFT (5u) +#define GPIO_PFCAE2_PFCAE26_SHIFT (6u) +#define GPIO_PFCAE2_PFCAE27_SHIFT (7u) +#define GPIO_PFCAE2_PFCAE28_SHIFT (8u) +#define GPIO_PFCAE2_PFCAE29_SHIFT (9u) +#define GPIO_PFCAE2_PFCAE210_SHIFT (10u) +#define GPIO_PFCAE2_PFCAE211_SHIFT (11u) +#define GPIO_PFCAE2_PFCAE212_SHIFT (12u) +#define GPIO_PFCAE2_PFCAE213_SHIFT (13u) +#define GPIO_PFCAE2_PFCAE214_SHIFT (14u) +#define GPIO_PFCAE2_PFCAE215_SHIFT (15u) + +#define GPIO_PIBC2_PIBC20_SHIFT (0u) +#define GPIO_PIBC2_PIBC21_SHIFT (1u) +#define GPIO_PIBC2_PIBC22_SHIFT (2u) +#define GPIO_PIBC2_PIBC23_SHIFT (3u) +#define GPIO_PIBC2_PIBC24_SHIFT (4u) +#define GPIO_PIBC2_PIBC25_SHIFT (5u) +#define GPIO_PIBC2_PIBC26_SHIFT (6u) +#define GPIO_PIBC2_PIBC27_SHIFT (7u) +#define GPIO_PIBC2_PIBC28_SHIFT (8u) +#define GPIO_PIBC2_PIBC29_SHIFT (9u) +#define GPIO_PIBC2_PIBC210_SHIFT (10u) +#define GPIO_PIBC2_PIBC211_SHIFT (11u) +#define GPIO_PIBC2_PIBC212_SHIFT (12u) +#define GPIO_PIBC2_PIBC213_SHIFT (13u) +#define GPIO_PIBC2_PIBC214_SHIFT (14u) +#define GPIO_PIBC2_PIBC215_SHIFT (15u) + +#define GPIO_PBDC2_PBDC20_SHIFT (0u) +#define GPIO_PBDC2_PBDC21_SHIFT (1u) +#define GPIO_PBDC2_PBDC22_SHIFT (2u) +#define GPIO_PBDC2_PBDC23_SHIFT (3u) +#define GPIO_PBDC2_PBDC24_SHIFT (4u) +#define GPIO_PBDC2_PBDC25_SHIFT (5u) +#define GPIO_PBDC2_PBDC26_SHIFT (6u) +#define GPIO_PBDC2_PBDC27_SHIFT (7u) +#define GPIO_PBDC2_PBDC28_SHIFT (8u) +#define GPIO_PBDC2_PBDC29_SHIFT (9u) +#define GPIO_PBDC2_PBDC210_SHIFT (10u) +#define GPIO_PBDC2_PBDC211_SHIFT (11u) +#define GPIO_PBDC2_PBDC212_SHIFT (12u) +#define GPIO_PBDC2_PBDC213_SHIFT (13u) +#define GPIO_PBDC2_PBDC214_SHIFT (14u) +#define GPIO_PBDC2_PBDC215_SHIFT (15u) + +#define GPIO_PIPC2_PIPC20_SHIFT (0u) +#define GPIO_PIPC2_PIPC21_SHIFT (1u) +#define GPIO_PIPC2_PIPC22_SHIFT (2u) +#define GPIO_PIPC2_PIPC23_SHIFT (3u) +#define GPIO_PIPC2_PIPC24_SHIFT (4u) +#define GPIO_PIPC2_PIPC25_SHIFT (5u) +#define GPIO_PIPC2_PIPC26_SHIFT (6u) +#define GPIO_PIPC2_PIPC27_SHIFT (7u) +#define GPIO_PIPC2_PIPC28_SHIFT (8u) +#define GPIO_PIPC2_PIPC29_SHIFT (9u) +#define GPIO_PIPC2_PIPC210_SHIFT (10u) +#define GPIO_PIPC2_PIPC211_SHIFT (11u) +#define GPIO_PIPC2_PIPC212_SHIFT (12u) +#define GPIO_PIPC2_PIPC213_SHIFT (13u) +#define GPIO_PIPC2_PIPC214_SHIFT (14u) +#define GPIO_PIPC2_PIPC215_SHIFT (15u) + +/* ---- P3 ---- */ +#define GPIO_P3_P30_SHIFT (0u) +#define GPIO_P3_P31_SHIFT (1u) +#define GPIO_P3_P32_SHIFT (2u) +#define GPIO_P3_P33_SHIFT (3u) +#define GPIO_P3_P34_SHIFT (4u) +#define GPIO_P3_P35_SHIFT (5u) +#define GPIO_P3_P36_SHIFT (6u) +#define GPIO_P3_P37_SHIFT (7u) +#define GPIO_P3_P38_SHIFT (8u) +#define GPIO_P3_P39_SHIFT (9u) +#define GPIO_P3_P310_SHIFT (10u) +#define GPIO_P3_P311_SHIFT (11u) +#define GPIO_P3_P312_SHIFT (12u) +#define GPIO_P3_P313_SHIFT (13u) +#define GPIO_P3_P314_SHIFT (14u) +#define GPIO_P3_P315_SHIFT (15u) + +#define GPIO_PSR3_PSR30_SHIFT (0u) +#define GPIO_PSR3_PSR31_SHIFT (1u) +#define GPIO_PSR3_PSR32_SHIFT (2u) +#define GPIO_PSR3_PSR33_SHIFT (3u) +#define GPIO_PSR3_PSR34_SHIFT (4u) +#define GPIO_PSR3_PSR35_SHIFT (5u) +#define GPIO_PSR3_PSR36_SHIFT (6u) +#define GPIO_PSR3_PSR37_SHIFT (7u) +#define GPIO_PSR3_PSR38_SHIFT (8u) +#define GPIO_PSR3_PSR39_SHIFT (9u) +#define GPIO_PSR3_PSR310_SHIFT (10u) +#define GPIO_PSR3_PSR311_SHIFT (11u) +#define GPIO_PSR3_PSR312_SHIFT (12u) +#define GPIO_PSR3_PSR313_SHIFT (13u) +#define GPIO_PSR3_PSR314_SHIFT (14u) +#define GPIO_PSR3_PSR315_SHIFT (15u) +#define GPIO_PSR3_PSR316_SHIFT (16u) +#define GPIO_PSR3_PSR317_SHIFT (17u) +#define GPIO_PSR3_PSR318_SHIFT (18u) +#define GPIO_PSR3_PSR319_SHIFT (19u) +#define GPIO_PSR3_PSR320_SHIFT (20u) +#define GPIO_PSR3_PSR321_SHIFT (21u) +#define GPIO_PSR3_PSR322_SHIFT (22u) +#define GPIO_PSR3_PSR323_SHIFT (23u) +#define GPIO_PSR3_PSR324_SHIFT (24u) +#define GPIO_PSR3_PSR325_SHIFT (25u) +#define GPIO_PSR3_PSR326_SHIFT (26u) +#define GPIO_PSR3_PSR327_SHIFT (27u) +#define GPIO_PSR3_PSR328_SHIFT (28u) +#define GPIO_PSR3_PSR329_SHIFT (29u) +#define GPIO_PSR3_PSR330_SHIFT (30u) +#define GPIO_PSR3_PSR331_SHIFT (31u) + +#define GPIO_PPR3_PPR30_SHIFT (0u) +#define GPIO_PPR3_PPR31_SHIFT (1u) +#define GPIO_PPR3_PPR32_SHIFT (2u) +#define GPIO_PPR3_PPR33_SHIFT (3u) +#define GPIO_PPR3_PPR34_SHIFT (4u) +#define GPIO_PPR3_PPR35_SHIFT (5u) +#define GPIO_PPR3_PPR36_SHIFT (6u) +#define GPIO_PPR3_PPR37_SHIFT (7u) +#define GPIO_PPR3_PPR38_SHIFT (8u) +#define GPIO_PPR3_PPR39_SHIFT (9u) +#define GPIO_PPR3_PPR310_SHIFT (10u) +#define GPIO_PPR3_PPR311_SHIFT (11u) +#define GPIO_PPR3_PPR312_SHIFT (12u) +#define GPIO_PPR3_PPR313_SHIFT (13u) +#define GPIO_PPR3_PPR314_SHIFT (14u) +#define GPIO_PPR3_PPR315_SHIFT (15u) + +#define GPIO_PM3_PM30_SHIFT (0u) +#define GPIO_PM3_PM31_SHIFT (1u) +#define GPIO_PM3_PM32_SHIFT (2u) +#define GPIO_PM3_PM33_SHIFT (3u) +#define GPIO_PM3_PM34_SHIFT (4u) +#define GPIO_PM3_PM35_SHIFT (5u) +#define GPIO_PM3_PM36_SHIFT (6u) +#define GPIO_PM3_PM37_SHIFT (7u) +#define GPIO_PM3_PM38_SHIFT (8u) +#define GPIO_PM3_PM39_SHIFT (9u) +#define GPIO_PM3_PM310_SHIFT (10u) +#define GPIO_PM3_PM311_SHIFT (11u) +#define GPIO_PM3_PM312_SHIFT (12u) +#define GPIO_PM3_PM313_SHIFT (13u) +#define GPIO_PM3_PM314_SHIFT (14u) +#define GPIO_PM3_PM315_SHIFT (15u) + +#define GPIO_PMC3_PMC30_SHIFT (0u) +#define GPIO_PMC3_PMC31_SHIFT (1u) +#define GPIO_PMC3_PMC32_SHIFT (2u) +#define GPIO_PMC3_PMC33_SHIFT (3u) +#define GPIO_PMC3_PMC34_SHIFT (4u) +#define GPIO_PMC3_PMC35_SHIFT (5u) +#define GPIO_PMC3_PMC36_SHIFT (6u) +#define GPIO_PMC3_PMC37_SHIFT (7u) +#define GPIO_PMC3_PMC38_SHIFT (8u) +#define GPIO_PMC3_PMC39_SHIFT (9u) +#define GPIO_PMC3_PMC310_SHIFT (10u) +#define GPIO_PMC3_PMC311_SHIFT (11u) +#define GPIO_PMC3_PMC312_SHIFT (12u) +#define GPIO_PMC3_PMC313_SHIFT (13u) +#define GPIO_PMC3_PMC314_SHIFT (14u) +#define GPIO_PMC3_PMC315_SHIFT (15u) + +#define GPIO_PFC3_PFC30_SHIFT (0u) +#define GPIO_PFC3_PFC31_SHIFT (1u) +#define GPIO_PFC3_PFC32_SHIFT (2u) +#define GPIO_PFC3_PFC33_SHIFT (3u) +#define GPIO_PFC3_PFC34_SHIFT (4u) +#define GPIO_PFC3_PFC35_SHIFT (5u) +#define GPIO_PFC3_PFC36_SHIFT (6u) +#define GPIO_PFC3_PFC37_SHIFT (7u) +#define GPIO_PFC3_PFC38_SHIFT (8u) +#define GPIO_PFC3_PFC39_SHIFT (9u) +#define GPIO_PFC3_PFC310_SHIFT (10u) +#define GPIO_PFC3_PFC311_SHIFT (11u) +#define GPIO_PFC3_PFC312_SHIFT (12u) +#define GPIO_PFC3_PFC313_SHIFT (13u) +#define GPIO_PFC3_PFC314_SHIFT (14u) +#define GPIO_PFC3_PFC315_SHIFT (15u) + +#define GPIO_PFCE3_PFCE30_SHIFT (0u) +#define GPIO_PFCE3_PFCE31_SHIFT (1u) +#define GPIO_PFCE3_PFCE32_SHIFT (2u) +#define GPIO_PFCE3_PFCE33_SHIFT (3u) +#define GPIO_PFCE3_PFCE34_SHIFT (4u) +#define GPIO_PFCE3_PFCE35_SHIFT (5u) +#define GPIO_PFCE3_PFCE36_SHIFT (6u) +#define GPIO_PFCE3_PFCE37_SHIFT (7u) +#define GPIO_PFCE3_PFCE38_SHIFT (8u) +#define GPIO_PFCE3_PFCE39_SHIFT (9u) +#define GPIO_PFCE3_PFCE310_SHIFT (10u) +#define GPIO_PFCE3_PFCE311_SHIFT (11u) +#define GPIO_PFCE3_PFCE312_SHIFT (12u) +#define GPIO_PFCE3_PFCE313_SHIFT (13u) +#define GPIO_PFCE3_PFCE314_SHIFT (14u) +#define GPIO_PFCE3_PFCE315_SHIFT (15u) + +#define GPIO_PNOT3_PNOT30_SHIFT (0u) +#define GPIO_PNOT3_PNOT31_SHIFT (1u) +#define GPIO_PNOT3_PNOT32_SHIFT (2u) +#define GPIO_PNOT3_PNOT33_SHIFT (3u) +#define GPIO_PNOT3_PNOT34_SHIFT (4u) +#define GPIO_PNOT3_PNOT35_SHIFT (5u) +#define GPIO_PNOT3_PNOT36_SHIFT (6u) +#define GPIO_PNOT3_PNOT37_SHIFT (7u) +#define GPIO_PNOT3_PNOT38_SHIFT (8u) +#define GPIO_PNOT3_PNOT39_SHIFT (9u) +#define GPIO_PNOT3_PNOT310_SHIFT (10u) +#define GPIO_PNOT3_PNOT311_SHIFT (11u) +#define GPIO_PNOT3_PNOT312_SHIFT (12u) +#define GPIO_PNOT3_PNOT313_SHIFT (13u) +#define GPIO_PNOT3_PNOT314_SHIFT (14u) +#define GPIO_PNOT3_PNOT315_SHIFT (15u) + +#define GPIO_PMSR3_PMSR30_SHIFT (0u) +#define GPIO_PMSR3_PMSR31_SHIFT (1u) +#define GPIO_PMSR3_PMSR32_SHIFT (2u) +#define GPIO_PMSR3_PMSR33_SHIFT (3u) +#define GPIO_PMSR3_PMSR34_SHIFT (4u) +#define GPIO_PMSR3_PMSR35_SHIFT (5u) +#define GPIO_PMSR3_PMSR36_SHIFT (6u) +#define GPIO_PMSR3_PMSR37_SHIFT (7u) +#define GPIO_PMSR3_PMSR38_SHIFT (8u) +#define GPIO_PMSR3_PMSR39_SHIFT (9u) +#define GPIO_PMSR3_PMSR310_SHIFT (10u) +#define GPIO_PMSR3_PMSR311_SHIFT (11u) +#define GPIO_PMSR3_PMSR312_SHIFT (12u) +#define GPIO_PMSR3_PMSR313_SHIFT (13u) +#define GPIO_PMSR3_PMSR314_SHIFT (14u) +#define GPIO_PMSR3_PMSR315_SHIFT (15u) +#define GPIO_PMSR3_PMSR316_SHIFT (16u) +#define GPIO_PMSR3_PMSR317_SHIFT (17u) +#define GPIO_PMSR3_PMSR318_SHIFT (18u) +#define GPIO_PMSR3_PMSR319_SHIFT (19u) +#define GPIO_PMSR3_PMSR320_SHIFT (20u) +#define GPIO_PMSR3_PMSR321_SHIFT (21u) +#define GPIO_PMSR3_PMSR322_SHIFT (22u) +#define GPIO_PMSR3_PMSR323_SHIFT (23u) +#define GPIO_PMSR3_PMSR324_SHIFT (24u) +#define GPIO_PMSR3_PMSR325_SHIFT (25u) +#define GPIO_PMSR3_PMSR326_SHIFT (26u) +#define GPIO_PMSR3_PMSR327_SHIFT (27u) +#define GPIO_PMSR3_PMSR328_SHIFT (28u) +#define GPIO_PMSR3_PMSR329_SHIFT (29u) +#define GPIO_PMSR3_PMSR330_SHIFT (30u) +#define GPIO_PMSR3_PMSR331_SHIFT (31u) + +#define GPIO_PMCSR3_PMCSR30_SHIFT (0u) +#define GPIO_PMCSR3_PMCSR31_SHIFT (1u) +#define GPIO_PMCSR3_PMCSR32_SHIFT (2u) +#define GPIO_PMCSR3_PMCSR33_SHIFT (3u) +#define GPIO_PMCSR3_PMCSR34_SHIFT (4u) +#define GPIO_PMCSR3_PMCSR35_SHIFT (5u) +#define GPIO_PMCSR3_PMCSR36_SHIFT (6u) +#define GPIO_PMCSR3_PMCSR37_SHIFT (7u) +#define GPIO_PMCSR3_PMCSR38_SHIFT (8u) +#define GPIO_PMCSR3_PMCSR39_SHIFT (9u) +#define GPIO_PMCSR3_PMCSR310_SHIFT (10u) +#define GPIO_PMCSR3_PMCSR311_SHIFT (11u) +#define GPIO_PMCSR3_PMCSR312_SHIFT (12u) +#define GPIO_PMCSR3_PMCSR313_SHIFT (13u) +#define GPIO_PMCSR3_PMCSR314_SHIFT (14u) +#define GPIO_PMCSR3_PMCSR315_SHIFT (15u) +#define GPIO_PMCSR3_PMCSR316_SHIFT (16u) +#define GPIO_PMCSR3_PMCSR317_SHIFT (17u) +#define GPIO_PMCSR3_PMCSR318_SHIFT (18u) +#define GPIO_PMCSR3_PMCSR319_SHIFT (19u) +#define GPIO_PMCSR3_PMCSR320_SHIFT (20u) +#define GPIO_PMCSR3_PMCSR321_SHIFT (21u) +#define GPIO_PMCSR3_PMCSR322_SHIFT (22u) +#define GPIO_PMCSR3_PMCSR323_SHIFT (23u) +#define GPIO_PMCSR3_PMCSR324_SHIFT (24u) +#define GPIO_PMCSR3_PMCSR325_SHIFT (25u) +#define GPIO_PMCSR3_PMCSR326_SHIFT (26u) +#define GPIO_PMCSR3_PMCSR327_SHIFT (27u) +#define GPIO_PMCSR3_PMCSR328_SHIFT (28u) +#define GPIO_PMCSR3_PMCSR329_SHIFT (29u) +#define GPIO_PMCSR3_PMCSR330_SHIFT (30u) +#define GPIO_PMCSR3_PMCSR331_SHIFT (31u) + +#define GPIO_PFCAE3_PFCAE30_SHIFT (0u) +#define GPIO_PFCAE3_PFCAE31_SHIFT (1u) +#define GPIO_PFCAE3_PFCAE32_SHIFT (2u) +#define GPIO_PFCAE3_PFCAE33_SHIFT (3u) +#define GPIO_PFCAE3_PFCAE34_SHIFT (4u) +#define GPIO_PFCAE3_PFCAE35_SHIFT (5u) +#define GPIO_PFCAE3_PFCAE36_SHIFT (6u) +#define GPIO_PFCAE3_PFCAE37_SHIFT (7u) +#define GPIO_PFCAE3_PFCAE38_SHIFT (8u) +#define GPIO_PFCAE3_PFCAE39_SHIFT (9u) +#define GPIO_PFCAE3_PFCAE310_SHIFT (10u) +#define GPIO_PFCAE3_PFCAE311_SHIFT (11u) +#define GPIO_PFCAE3_PFCAE312_SHIFT (12u) +#define GPIO_PFCAE3_PFCAE313_SHIFT (13u) +#define GPIO_PFCAE3_PFCAE314_SHIFT (14u) +#define GPIO_PFCAE3_PFCAE315_SHIFT (15u) + +#define GPIO_PIBC3_PIBC30_SHIFT (0u) +#define GPIO_PIBC3_PIBC31_SHIFT (1u) +#define GPIO_PIBC3_PIBC32_SHIFT (2u) +#define GPIO_PIBC3_PIBC33_SHIFT (3u) +#define GPIO_PIBC3_PIBC34_SHIFT (4u) +#define GPIO_PIBC3_PIBC35_SHIFT (5u) +#define GPIO_PIBC3_PIBC36_SHIFT (6u) +#define GPIO_PIBC3_PIBC37_SHIFT (7u) +#define GPIO_PIBC3_PIBC38_SHIFT (8u) +#define GPIO_PIBC3_PIBC39_SHIFT (9u) +#define GPIO_PIBC3_PIBC310_SHIFT (10u) +#define GPIO_PIBC3_PIBC311_SHIFT (11u) +#define GPIO_PIBC3_PIBC312_SHIFT (12u) +#define GPIO_PIBC3_PIBC313_SHIFT (13u) +#define GPIO_PIBC3_PIBC314_SHIFT (14u) +#define GPIO_PIBC3_PIBC315_SHIFT (15u) + +#define GPIO_PBDC3_PBDC30_SHIFT (0u) +#define GPIO_PBDC3_PBDC31_SHIFT (1u) +#define GPIO_PBDC3_PBDC32_SHIFT (2u) +#define GPIO_PBDC3_PBDC33_SHIFT (3u) +#define GPIO_PBDC3_PBDC34_SHIFT (4u) +#define GPIO_PBDC3_PBDC35_SHIFT (5u) +#define GPIO_PBDC3_PBDC36_SHIFT (6u) +#define GPIO_PBDC3_PBDC37_SHIFT (7u) +#define GPIO_PBDC3_PBDC38_SHIFT (8u) +#define GPIO_PBDC3_PBDC39_SHIFT (9u) +#define GPIO_PBDC3_PBDC310_SHIFT (10u) +#define GPIO_PBDC3_PBDC311_SHIFT (11u) +#define GPIO_PBDC3_PBDC312_SHIFT (12u) +#define GPIO_PBDC3_PBDC313_SHIFT (13u) +#define GPIO_PBDC3_PBDC314_SHIFT (14u) +#define GPIO_PBDC3_PBDC315_SHIFT (15u) + +#define GPIO_PIPC3_PIPC30_SHIFT (0u) +#define GPIO_PIPC3_PIPC31_SHIFT (1u) +#define GPIO_PIPC3_PIPC32_SHIFT (2u) +#define GPIO_PIPC3_PIPC33_SHIFT (3u) +#define GPIO_PIPC3_PIPC34_SHIFT (4u) +#define GPIO_PIPC3_PIPC35_SHIFT (5u) +#define GPIO_PIPC3_PIPC36_SHIFT (6u) +#define GPIO_PIPC3_PIPC37_SHIFT (7u) +#define GPIO_PIPC3_PIPC38_SHIFT (8u) +#define GPIO_PIPC3_PIPC39_SHIFT (9u) +#define GPIO_PIPC3_PIPC310_SHIFT (10u) +#define GPIO_PIPC3_PIPC311_SHIFT (11u) +#define GPIO_PIPC3_PIPC312_SHIFT (12u) +#define GPIO_PIPC3_PIPC313_SHIFT (13u) +#define GPIO_PIPC3_PIPC314_SHIFT (14u) +#define GPIO_PIPC3_PIPC315_SHIFT (15u) + +/* ---- P4 ---- */ +#define GPIO_P4_P40_SHIFT (0u) +#define GPIO_P4_P41_SHIFT (1u) +#define GPIO_P4_P42_SHIFT (2u) +#define GPIO_P4_P43_SHIFT (3u) +#define GPIO_P4_P44_SHIFT (4u) +#define GPIO_P4_P45_SHIFT (5u) +#define GPIO_P4_P46_SHIFT (6u) +#define GPIO_P4_P47_SHIFT (7u) +#define GPIO_P4_P48_SHIFT (8u) +#define GPIO_P4_P49_SHIFT (9u) +#define GPIO_P4_P410_SHIFT (10u) +#define GPIO_P4_P411_SHIFT (11u) +#define GPIO_P4_P412_SHIFT (12u) +#define GPIO_P4_P413_SHIFT (13u) +#define GPIO_P4_P414_SHIFT (14u) +#define GPIO_P4_P415_SHIFT (15u) + +#define GPIO_PSR4_PSR40_SHIFT (0u) +#define GPIO_PSR4_PSR41_SHIFT (1u) +#define GPIO_PSR4_PSR42_SHIFT (2u) +#define GPIO_PSR4_PSR43_SHIFT (3u) +#define GPIO_PSR4_PSR44_SHIFT (4u) +#define GPIO_PSR4_PSR45_SHIFT (5u) +#define GPIO_PSR4_PSR46_SHIFT (6u) +#define GPIO_PSR4_PSR47_SHIFT (7u) +#define GPIO_PSR4_PSR48_SHIFT (8u) +#define GPIO_PSR4_PSR49_SHIFT (9u) +#define GPIO_PSR4_PSR410_SHIFT (10u) +#define GPIO_PSR4_PSR411_SHIFT (11u) +#define GPIO_PSR4_PSR412_SHIFT (12u) +#define GPIO_PSR4_PSR413_SHIFT (13u) +#define GPIO_PSR4_PSR414_SHIFT (14u) +#define GPIO_PSR4_PSR415_SHIFT (15u) +#define GPIO_PSR4_PSR416_SHIFT (16u) +#define GPIO_PSR4_PSR417_SHIFT (17u) +#define GPIO_PSR4_PSR418_SHIFT (18u) +#define GPIO_PSR4_PSR419_SHIFT (19u) +#define GPIO_PSR4_PSR420_SHIFT (20u) +#define GPIO_PSR4_PSR421_SHIFT (21u) +#define GPIO_PSR4_PSR422_SHIFT (22u) +#define GPIO_PSR4_PSR423_SHIFT (23u) +#define GPIO_PSR4_PSR424_SHIFT (24u) +#define GPIO_PSR4_PSR425_SHIFT (25u) +#define GPIO_PSR4_PSR426_SHIFT (26u) +#define GPIO_PSR4_PSR427_SHIFT (27u) +#define GPIO_PSR4_PSR428_SHIFT (28u) +#define GPIO_PSR4_PSR429_SHIFT (29u) +#define GPIO_PSR4_PSR430_SHIFT (30u) +#define GPIO_PSR4_PSR431_SHIFT (31u) + +#define GPIO_PPR4_PPR40_SHIFT (0u) +#define GPIO_PPR4_PPR41_SHIFT (1u) +#define GPIO_PPR4_PPR42_SHIFT (2u) +#define GPIO_PPR4_PPR43_SHIFT (3u) +#define GPIO_PPR4_PPR44_SHIFT (4u) +#define GPIO_PPR4_PPR45_SHIFT (5u) +#define GPIO_PPR4_PPR46_SHIFT (6u) +#define GPIO_PPR4_PPR47_SHIFT (7u) +#define GPIO_PPR4_PPR48_SHIFT (8u) +#define GPIO_PPR4_PPR49_SHIFT (9u) +#define GPIO_PPR4_PPR410_SHIFT (10u) +#define GPIO_PPR4_PPR411_SHIFT (11u) +#define GPIO_PPR4_PPR412_SHIFT (12u) +#define GPIO_PPR4_PPR413_SHIFT (13u) +#define GPIO_PPR4_PPR414_SHIFT (14u) +#define GPIO_PPR4_PPR415_SHIFT (15u) + +#define GPIO_PM4_PM40_SHIFT (0u) +#define GPIO_PM4_PM41_SHIFT (1u) +#define GPIO_PM4_PM42_SHIFT (2u) +#define GPIO_PM4_PM43_SHIFT (3u) +#define GPIO_PM4_PM44_SHIFT (4u) +#define GPIO_PM4_PM45_SHIFT (5u) +#define GPIO_PM4_PM46_SHIFT (6u) +#define GPIO_PM4_PM47_SHIFT (7u) +#define GPIO_PM4_PM48_SHIFT (8u) +#define GPIO_PM4_PM49_SHIFT (9u) +#define GPIO_PM4_PM410_SHIFT (10u) +#define GPIO_PM4_PM411_SHIFT (11u) +#define GPIO_PM4_PM412_SHIFT (12u) +#define GPIO_PM4_PM413_SHIFT (13u) +#define GPIO_PM4_PM414_SHIFT (14u) +#define GPIO_PM4_PM415_SHIFT (15u) + +#define GPIO_PMC4_PMC40_SHIFT (0u) +#define GPIO_PMC4_PMC41_SHIFT (1u) +#define GPIO_PMC4_PMC42_SHIFT (2u) +#define GPIO_PMC4_PMC43_SHIFT (3u) +#define GPIO_PMC4_PMC44_SHIFT (4u) +#define GPIO_PMC4_PMC45_SHIFT (5u) +#define GPIO_PMC4_PMC46_SHIFT (6u) +#define GPIO_PMC4_PMC47_SHIFT (7u) +#define GPIO_PMC4_PMC48_SHIFT (8u) +#define GPIO_PMC4_PMC49_SHIFT (9u) +#define GPIO_PMC4_PMC410_SHIFT (10u) +#define GPIO_PMC4_PMC411_SHIFT (11u) +#define GPIO_PMC4_PMC412_SHIFT (12u) +#define GPIO_PMC4_PMC413_SHIFT (13u) +#define GPIO_PMC4_PMC414_SHIFT (14u) +#define GPIO_PMC4_PMC415_SHIFT (15u) + +#define GPIO_PFC4_PFC40_SHIFT (0u) +#define GPIO_PFC4_PFC41_SHIFT (1u) +#define GPIO_PFC4_PFC42_SHIFT (2u) +#define GPIO_PFC4_PFC43_SHIFT (3u) +#define GPIO_PFC4_PFC44_SHIFT (4u) +#define GPIO_PFC4_PFC45_SHIFT (5u) +#define GPIO_PFC4_PFC46_SHIFT (6u) +#define GPIO_PFC4_PFC47_SHIFT (7u) +#define GPIO_PFC4_PFC48_SHIFT (8u) +#define GPIO_PFC4_PFC49_SHIFT (9u) +#define GPIO_PFC4_PFC410_SHIFT (10u) +#define GPIO_PFC4_PFC411_SHIFT (11u) +#define GPIO_PFC4_PFC412_SHIFT (12u) +#define GPIO_PFC4_PFC413_SHIFT (13u) +#define GPIO_PFC4_PFC414_SHIFT (14u) +#define GPIO_PFC4_PFC415_SHIFT (15u) + +#define GPIO_PFCE4_PFCE40_SHIFT (0u) +#define GPIO_PFCE4_PFCE41_SHIFT (1u) +#define GPIO_PFCE4_PFCE42_SHIFT (2u) +#define GPIO_PFCE4_PFCE43_SHIFT (3u) +#define GPIO_PFCE4_PFCE44_SHIFT (4u) +#define GPIO_PFCE4_PFCE45_SHIFT (5u) +#define GPIO_PFCE4_PFCE46_SHIFT (6u) +#define GPIO_PFCE4_PFCE47_SHIFT (7u) +#define GPIO_PFCE4_PFCE48_SHIFT (8u) +#define GPIO_PFCE4_PFCE49_SHIFT (9u) +#define GPIO_PFCE4_PFCE410_SHIFT (10u) +#define GPIO_PFCE4_PFCE411_SHIFT (11u) +#define GPIO_PFCE4_PFCE412_SHIFT (12u) +#define GPIO_PFCE4_PFCE413_SHIFT (13u) +#define GPIO_PFCE4_PFCE414_SHIFT (14u) +#define GPIO_PFCE4_PFCE415_SHIFT (15u) + +#define GPIO_PNOT4_PNOT40_SHIFT (0u) +#define GPIO_PNOT4_PNOT41_SHIFT (1u) +#define GPIO_PNOT4_PNOT42_SHIFT (2u) +#define GPIO_PNOT4_PNOT43_SHIFT (3u) +#define GPIO_PNOT4_PNOT44_SHIFT (4u) +#define GPIO_PNOT4_PNOT45_SHIFT (5u) +#define GPIO_PNOT4_PNOT46_SHIFT (6u) +#define GPIO_PNOT4_PNOT47_SHIFT (7u) +#define GPIO_PNOT4_PNOT48_SHIFT (8u) +#define GPIO_PNOT4_PNOT49_SHIFT (9u) +#define GPIO_PNOT4_PNOT410_SHIFT (10u) +#define GPIO_PNOT4_PNOT411_SHIFT (11u) +#define GPIO_PNOT4_PNOT412_SHIFT (12u) +#define GPIO_PNOT4_PNOT413_SHIFT (13u) +#define GPIO_PNOT4_PNOT414_SHIFT (14u) +#define GPIO_PNOT4_PNOT415_SHIFT (15u) + +#define GPIO_PMSR4_PMSR40_SHIFT (0u) +#define GPIO_PMSR4_PMSR41_SHIFT (1u) +#define GPIO_PMSR4_PMSR42_SHIFT (2u) +#define GPIO_PMSR4_PMSR43_SHIFT (3u) +#define GPIO_PMSR4_PMSR44_SHIFT (4u) +#define GPIO_PMSR4_PMSR45_SHIFT (5u) +#define GPIO_PMSR4_PMSR46_SHIFT (6u) +#define GPIO_PMSR4_PMSR47_SHIFT (7u) +#define GPIO_PMSR4_PMSR48_SHIFT (8u) +#define GPIO_PMSR4_PMSR49_SHIFT (9u) +#define GPIO_PMSR4_PMSR410_SHIFT (10u) +#define GPIO_PMSR4_PMSR411_SHIFT (11u) +#define GPIO_PMSR4_PMSR412_SHIFT (12u) +#define GPIO_PMSR4_PMSR413_SHIFT (13u) +#define GPIO_PMSR4_PMSR414_SHIFT (14u) +#define GPIO_PMSR4_PMSR415_SHIFT (15u) +#define GPIO_PMSR4_PMSR416_SHIFT (16u) +#define GPIO_PMSR4_PMSR417_SHIFT (17u) +#define GPIO_PMSR4_PMSR418_SHIFT (18u) +#define GPIO_PMSR4_PMSR419_SHIFT (19u) +#define GPIO_PMSR4_PMSR420_SHIFT (20u) +#define GPIO_PMSR4_PMSR421_SHIFT (21u) +#define GPIO_PMSR4_PMSR422_SHIFT (22u) +#define GPIO_PMSR4_PMSR423_SHIFT (23u) +#define GPIO_PMSR4_PMSR424_SHIFT (24u) +#define GPIO_PMSR4_PMSR425_SHIFT (25u) +#define GPIO_PMSR4_PMSR426_SHIFT (26u) +#define GPIO_PMSR4_PMSR427_SHIFT (27u) +#define GPIO_PMSR4_PMSR428_SHIFT (28u) +#define GPIO_PMSR4_PMSR429_SHIFT (29u) +#define GPIO_PMSR4_PMSR430_SHIFT (30u) +#define GPIO_PMSR4_PMSR431_SHIFT (31u) + +#define GPIO_PMCSR4_PMCSR40_SHIFT (0u) +#define GPIO_PMCSR4_PMCSR41_SHIFT (1u) +#define GPIO_PMCSR4_PMCSR42_SHIFT (2u) +#define GPIO_PMCSR4_PMCSR43_SHIFT (3u) +#define GPIO_PMCSR4_PMCSR44_SHIFT (4u) +#define GPIO_PMCSR4_PMCSR45_SHIFT (5u) +#define GPIO_PMCSR4_PMCSR46_SHIFT (6u) +#define GPIO_PMCSR4_PMCSR47_SHIFT (7u) +#define GPIO_PMCSR4_PMCSR48_SHIFT (8u) +#define GPIO_PMCSR4_PMCSR49_SHIFT (9u) +#define GPIO_PMCSR4_PMCSR410_SHIFT (10u) +#define GPIO_PMCSR4_PMCSR411_SHIFT (11u) +#define GPIO_PMCSR4_PMCSR412_SHIFT (12u) +#define GPIO_PMCSR4_PMCSR413_SHIFT (13u) +#define GPIO_PMCSR4_PMCSR414_SHIFT (14u) +#define GPIO_PMCSR4_PMCSR415_SHIFT (15u) +#define GPIO_PMCSR4_PMCSR416_SHIFT (16u) +#define GPIO_PMCSR4_PMCSR417_SHIFT (17u) +#define GPIO_PMCSR4_PMCSR418_SHIFT (18u) +#define GPIO_PMCSR4_PMCSR419_SHIFT (19u) +#define GPIO_PMCSR4_PMCSR420_SHIFT (20u) +#define GPIO_PMCSR4_PMCSR421_SHIFT (21u) +#define GPIO_PMCSR4_PMCSR422_SHIFT (22u) +#define GPIO_PMCSR4_PMCSR423_SHIFT (23u) +#define GPIO_PMCSR4_PMCSR424_SHIFT (24u) +#define GPIO_PMCSR4_PMCSR425_SHIFT (25u) +#define GPIO_PMCSR4_PMCSR426_SHIFT (26u) +#define GPIO_PMCSR4_PMCSR427_SHIFT (27u) +#define GPIO_PMCSR4_PMCSR428_SHIFT (28u) +#define GPIO_PMCSR4_PMCSR429_SHIFT (29u) +#define GPIO_PMCSR4_PMCSR430_SHIFT (30u) +#define GPIO_PMCSR4_PMCSR431_SHIFT (31u) + +#define GPIO_PFCAE4_PFCAE40_SHIFT (0u) +#define GPIO_PFCAE4_PFCAE41_SHIFT (1u) +#define GPIO_PFCAE4_PFCAE42_SHIFT (2u) +#define GPIO_PFCAE4_PFCAE43_SHIFT (3u) +#define GPIO_PFCAE4_PFCAE44_SHIFT (4u) +#define GPIO_PFCAE4_PFCAE45_SHIFT (5u) +#define GPIO_PFCAE4_PFCAE46_SHIFT (6u) +#define GPIO_PFCAE4_PFCAE47_SHIFT (7u) +#define GPIO_PFCAE4_PFCAE48_SHIFT (8u) +#define GPIO_PFCAE4_PFCAE49_SHIFT (9u) +#define GPIO_PFCAE4_PFCAE410_SHIFT (10u) +#define GPIO_PFCAE4_PFCAE411_SHIFT (11u) +#define GPIO_PFCAE4_PFCAE412_SHIFT (12u) +#define GPIO_PFCAE4_PFCAE413_SHIFT (13u) +#define GPIO_PFCAE4_PFCAE414_SHIFT (14u) +#define GPIO_PFCAE4_PFCAE415_SHIFT (15u) + +#define GPIO_PIBC4_PIBC40_SHIFT (0u) +#define GPIO_PIBC4_PIBC41_SHIFT (1u) +#define GPIO_PIBC4_PIBC42_SHIFT (2u) +#define GPIO_PIBC4_PIBC43_SHIFT (3u) +#define GPIO_PIBC4_PIBC44_SHIFT (4u) +#define GPIO_PIBC4_PIBC45_SHIFT (5u) +#define GPIO_PIBC4_PIBC46_SHIFT (6u) +#define GPIO_PIBC4_PIBC47_SHIFT (7u) +#define GPIO_PIBC4_PIBC48_SHIFT (8u) +#define GPIO_PIBC4_PIBC49_SHIFT (9u) +#define GPIO_PIBC4_PIBC410_SHIFT (10u) +#define GPIO_PIBC4_PIBC411_SHIFT (11u) +#define GPIO_PIBC4_PIBC412_SHIFT (12u) +#define GPIO_PIBC4_PIBC413_SHIFT (13u) +#define GPIO_PIBC4_PIBC414_SHIFT (14u) +#define GPIO_PIBC4_PIBC415_SHIFT (15u) + +#define GPIO_PBDC4_PBDC40_SHIFT (0u) +#define GPIO_PBDC4_PBDC41_SHIFT (1u) +#define GPIO_PBDC4_PBDC42_SHIFT (2u) +#define GPIO_PBDC4_PBDC43_SHIFT (3u) +#define GPIO_PBDC4_PBDC44_SHIFT (4u) +#define GPIO_PBDC4_PBDC45_SHIFT (5u) +#define GPIO_PBDC4_PBDC46_SHIFT (6u) +#define GPIO_PBDC4_PBDC47_SHIFT (7u) +#define GPIO_PBDC4_PBDC48_SHIFT (8u) +#define GPIO_PBDC4_PBDC49_SHIFT (9u) +#define GPIO_PBDC4_PBDC410_SHIFT (10u) +#define GPIO_PBDC4_PBDC411_SHIFT (11u) +#define GPIO_PBDC4_PBDC412_SHIFT (12u) +#define GPIO_PBDC4_PBDC413_SHIFT (13u) +#define GPIO_PBDC4_PBDC414_SHIFT (14u) +#define GPIO_PBDC4_PBDC415_SHIFT (15u) + +#define GPIO_PIPC4_PIPC40_SHIFT (0u) +#define GPIO_PIPC4_PIPC41_SHIFT (1u) +#define GPIO_PIPC4_PIPC42_SHIFT (2u) +#define GPIO_PIPC4_PIPC43_SHIFT (3u) +#define GPIO_PIPC4_PIPC44_SHIFT (4u) +#define GPIO_PIPC4_PIPC45_SHIFT (5u) +#define GPIO_PIPC4_PIPC46_SHIFT (6u) +#define GPIO_PIPC4_PIPC47_SHIFT (7u) +#define GPIO_PIPC4_PIPC48_SHIFT (8u) +#define GPIO_PIPC4_PIPC49_SHIFT (9u) +#define GPIO_PIPC4_PIPC410_SHIFT (10u) +#define GPIO_PIPC4_PIPC411_SHIFT (11u) +#define GPIO_PIPC4_PIPC412_SHIFT (12u) +#define GPIO_PIPC4_PIPC413_SHIFT (13u) +#define GPIO_PIPC4_PIPC414_SHIFT (14u) +#define GPIO_PIPC4_PIPC415_SHIFT (15u) + +/* ---- P5 ---- */ +#define GPIO_P5_P50_SHIFT (0u) +#define GPIO_P5_P51_SHIFT (1u) +#define GPIO_P5_P52_SHIFT (2u) +#define GPIO_P5_P53_SHIFT (3u) +#define GPIO_P5_P54_SHIFT (4u) +#define GPIO_P5_P55_SHIFT (5u) +#define GPIO_P5_P56_SHIFT (6u) +#define GPIO_P5_P57_SHIFT (7u) +#define GPIO_P5_P58_SHIFT (8u) +#define GPIO_P5_P59_SHIFT (9u) +#define GPIO_P5_P510_SHIFT (10u) + +#define GPIO_PSR5_PSR50_SHIFT (0u) +#define GPIO_PSR5_PSR51_SHIFT (1u) +#define GPIO_PSR5_PSR52_SHIFT (2u) +#define GPIO_PSR5_PSR53_SHIFT (3u) +#define GPIO_PSR5_PSR54_SHIFT (4u) +#define GPIO_PSR5_PSR55_SHIFT (5u) +#define GPIO_PSR5_PSR56_SHIFT (6u) +#define GPIO_PSR5_PSR57_SHIFT (7u) +#define GPIO_PSR5_PSR58_SHIFT (8u) +#define GPIO_PSR5_PSR59_SHIFT (9u) +#define GPIO_PSR5_PSR510_SHIFT (10u) +#define GPIO_PSR5_PSR516_SHIFT (16u) +#define GPIO_PSR5_PSR517_SHIFT (17u) +#define GPIO_PSR5_PSR518_SHIFT (18u) +#define GPIO_PSR5_PSR519_SHIFT (19u) +#define GPIO_PSR5_PSR520_SHIFT (20u) +#define GPIO_PSR5_PSR521_SHIFT (21u) +#define GPIO_PSR5_PSR522_SHIFT (22u) +#define GPIO_PSR5_PSR523_SHIFT (23u) +#define GPIO_PSR5_PSR524_SHIFT (24u) +#define GPIO_PSR5_PSR525_SHIFT (25u) +#define GPIO_PSR5_PSR526_SHIFT (26u) + +#define GPIO_PPR5_PPR50_SHIFT (0u) +#define GPIO_PPR5_PPR51_SHIFT (1u) +#define GPIO_PPR5_PPR52_SHIFT (2u) +#define GPIO_PPR5_PPR53_SHIFT (3u) +#define GPIO_PPR5_PPR54_SHIFT (4u) +#define GPIO_PPR5_PPR55_SHIFT (5u) +#define GPIO_PPR5_PPR56_SHIFT (6u) +#define GPIO_PPR5_PPR57_SHIFT (7u) +#define GPIO_PPR5_PPR58_SHIFT (8u) +#define GPIO_PPR5_PPR59_SHIFT (9u) +#define GPIO_PPR5_PPR510_SHIFT (10u) + +#define GPIO_PM5_PM50_SHIFT (0u) +#define GPIO_PM5_PM51_SHIFT (1u) +#define GPIO_PM5_PM52_SHIFT (2u) +#define GPIO_PM5_PM53_SHIFT (3u) +#define GPIO_PM5_PM54_SHIFT (4u) +#define GPIO_PM5_PM55_SHIFT (5u) +#define GPIO_PM5_PM56_SHIFT (6u) +#define GPIO_PM5_PM57_SHIFT (7u) +#define GPIO_PM5_PM58_SHIFT (8u) +#define GPIO_PM5_PM59_SHIFT (9u) +#define GPIO_PM5_PM510_SHIFT (10u) + +#define GPIO_PMC5_PMC50_SHIFT (0u) +#define GPIO_PMC5_PMC51_SHIFT (1u) +#define GPIO_PMC5_PMC52_SHIFT (2u) +#define GPIO_PMC5_PMC53_SHIFT (3u) +#define GPIO_PMC5_PMC54_SHIFT (4u) +#define GPIO_PMC5_PMC55_SHIFT (5u) +#define GPIO_PMC5_PMC56_SHIFT (6u) +#define GPIO_PMC5_PMC57_SHIFT (7u) +#define GPIO_PMC5_PMC58_SHIFT (8u) +#define GPIO_PMC5_PMC59_SHIFT (9u) +#define GPIO_PMC5_PMC510_SHIFT (10u) + +#define GPIO_PFC5_PFC50_SHIFT (0u) +#define GPIO_PFC5_PFC51_SHIFT (1u) +#define GPIO_PFC5_PFC52_SHIFT (2u) +#define GPIO_PFC5_PFC53_SHIFT (3u) +#define GPIO_PFC5_PFC54_SHIFT (4u) +#define GPIO_PFC5_PFC55_SHIFT (5u) +#define GPIO_PFC5_PFC56_SHIFT (6u) +#define GPIO_PFC5_PFC57_SHIFT (7u) +#define GPIO_PFC5_PFC58_SHIFT (8u) +#define GPIO_PFC5_PFC59_SHIFT (9u) +#define GPIO_PFC5_PFC510_SHIFT (10u) + +#define GPIO_PFCE5_PFCE50_SHIFT (0u) +#define GPIO_PFCE5_PFCE51_SHIFT (1u) +#define GPIO_PFCE5_PFCE52_SHIFT (2u) +#define GPIO_PFCE5_PFCE53_SHIFT (3u) +#define GPIO_PFCE5_PFCE54_SHIFT (4u) +#define GPIO_PFCE5_PFCE55_SHIFT (5u) +#define GPIO_PFCE5_PFCE56_SHIFT (6u) +#define GPIO_PFCE5_PFCE57_SHIFT (7u) +#define GPIO_PFCE5_PFCE58_SHIFT (8u) +#define GPIO_PFCE5_PFCE59_SHIFT (9u) +#define GPIO_PFCE5_PFCE510_SHIFT (10u) + +#define GPIO_PNOT5_PNOT50_SHIFT (0u) +#define GPIO_PNOT5_PNOT51_SHIFT (1u) +#define GPIO_PNOT5_PNOT52_SHIFT (2u) +#define GPIO_PNOT5_PNOT53_SHIFT (3u) +#define GPIO_PNOT5_PNOT54_SHIFT (4u) +#define GPIO_PNOT5_PNOT55_SHIFT (5u) +#define GPIO_PNOT5_PNOT56_SHIFT (6u) +#define GPIO_PNOT5_PNOT57_SHIFT (7u) +#define GPIO_PNOT5_PNOT58_SHIFT (8u) +#define GPIO_PNOT5_PNOT59_SHIFT (9u) +#define GPIO_PNOT5_PNOT510_SHIFT (10u) + +#define GPIO_PMSR5_PMSR50_SHIFT (0u) +#define GPIO_PMSR5_PMSR51_SHIFT (1u) +#define GPIO_PMSR5_PMSR52_SHIFT (2u) +#define GPIO_PMSR5_PMSR53_SHIFT (3u) +#define GPIO_PMSR5_PMSR54_SHIFT (4u) +#define GPIO_PMSR5_PMSR55_SHIFT (5u) +#define GPIO_PMSR5_PMSR56_SHIFT (6u) +#define GPIO_PMSR5_PMSR57_SHIFT (7u) +#define GPIO_PMSR5_PMSR58_SHIFT (8u) +#define GPIO_PMSR5_PMSR59_SHIFT (9u) +#define GPIO_PMSR5_PMSR510_SHIFT (10u) +#define GPIO_PMSR5_PMSR516_SHIFT (16u) +#define GPIO_PMSR5_PMSR517_SHIFT (17u) +#define GPIO_PMSR5_PMSR518_SHIFT (18u) +#define GPIO_PMSR5_PMSR519_SHIFT (19u) +#define GPIO_PMSR5_PMSR520_SHIFT (20u) +#define GPIO_PMSR5_PMSR521_SHIFT (21u) +#define GPIO_PMSR5_PMSR522_SHIFT (22u) +#define GPIO_PMSR5_PMSR523_SHIFT (23u) +#define GPIO_PMSR5_PMSR524_SHIFT (24u) +#define GPIO_PMSR5_PMSR525_SHIFT (25u) +#define GPIO_PMSR5_PMSR526_SHIFT (26u) + +#define GPIO_PMCSR5_PMCSR50_SHIFT (0u) +#define GPIO_PMCSR5_PMCSR51_SHIFT (1u) +#define GPIO_PMCSR5_PMCSR52_SHIFT (2u) +#define GPIO_PMCSR5_PMCSR53_SHIFT (3u) +#define GPIO_PMCSR5_PMCSR54_SHIFT (4u) +#define GPIO_PMCSR5_PMCSR55_SHIFT (5u) +#define GPIO_PMCSR5_PMCSR56_SHIFT (6u) +#define GPIO_PMCSR5_PMCSR57_SHIFT (7u) +#define GPIO_PMCSR5_PMCSR58_SHIFT (8u) +#define GPIO_PMCSR5_PMCSR59_SHIFT (9u) +#define GPIO_PMCSR5_PMCSR510_SHIFT (10u) +#define GPIO_PMCSR5_PMCSR516_SHIFT (16u) +#define GPIO_PMCSR5_PMCSR517_SHIFT (17u) +#define GPIO_PMCSR5_PMCSR518_SHIFT (18u) +#define GPIO_PMCSR5_PMCSR519_SHIFT (19u) +#define GPIO_PMCSR5_PMCSR520_SHIFT (20u) +#define GPIO_PMCSR5_PMCSR521_SHIFT (21u) +#define GPIO_PMCSR5_PMCSR522_SHIFT (22u) +#define GPIO_PMCSR5_PMCSR523_SHIFT (23u) +#define GPIO_PMCSR5_PMCSR524_SHIFT (24u) +#define GPIO_PMCSR5_PMCSR525_SHIFT (25u) +#define GPIO_PMCSR5_PMCSR526_SHIFT (26u) + +#define GPIO_PFCAE5_PFCAE50_SHIFT (0u) +#define GPIO_PFCAE5_PFCAE51_SHIFT (1u) +#define GPIO_PFCAE5_PFCAE52_SHIFT (2u) +#define GPIO_PFCAE5_PFCAE53_SHIFT (3u) +#define GPIO_PFCAE5_PFCAE54_SHIFT (4u) +#define GPIO_PFCAE5_PFCAE55_SHIFT (5u) +#define GPIO_PFCAE5_PFCAE56_SHIFT (6u) +#define GPIO_PFCAE5_PFCAE57_SHIFT (7u) +#define GPIO_PFCAE5_PFCAE58_SHIFT (8u) +#define GPIO_PFCAE5_PFCAE59_SHIFT (9u) +#define GPIO_PFCAE5_PFCAE510_SHIFT (10u) + +#define GPIO_PIBC5_PIBC50_SHIFT (0u) +#define GPIO_PIBC5_PIBC51_SHIFT (1u) +#define GPIO_PIBC5_PIBC52_SHIFT (2u) +#define GPIO_PIBC5_PIBC53_SHIFT (3u) +#define GPIO_PIBC5_PIBC54_SHIFT (4u) +#define GPIO_PIBC5_PIBC55_SHIFT (5u) +#define GPIO_PIBC5_PIBC56_SHIFT (6u) +#define GPIO_PIBC5_PIBC57_SHIFT (7u) +#define GPIO_PIBC5_PIBC58_SHIFT (8u) +#define GPIO_PIBC5_PIBC59_SHIFT (9u) +#define GPIO_PIBC5_PIBC510_SHIFT (10u) + +#define GPIO_PBDC5_PBDC50_SHIFT (0u) +#define GPIO_PBDC5_PBDC51_SHIFT (1u) +#define GPIO_PBDC5_PBDC52_SHIFT (2u) +#define GPIO_PBDC5_PBDC53_SHIFT (3u) +#define GPIO_PBDC5_PBDC54_SHIFT (4u) +#define GPIO_PBDC5_PBDC55_SHIFT (5u) +#define GPIO_PBDC5_PBDC56_SHIFT (6u) +#define GPIO_PBDC5_PBDC57_SHIFT (7u) +#define GPIO_PBDC5_PBDC58_SHIFT (8u) +#define GPIO_PBDC5_PBDC59_SHIFT (9u) +#define GPIO_PBDC5_PBDC510_SHIFT (10u) + +#define GPIO_PIPC5_PIPC50_SHIFT (0u) +#define GPIO_PIPC5_PIPC51_SHIFT (1u) +#define GPIO_PIPC5_PIPC52_SHIFT (2u) +#define GPIO_PIPC5_PIPC53_SHIFT (3u) +#define GPIO_PIPC5_PIPC54_SHIFT (4u) +#define GPIO_PIPC5_PIPC55_SHIFT (5u) +#define GPIO_PIPC5_PIPC56_SHIFT (6u) +#define GPIO_PIPC5_PIPC57_SHIFT (7u) +#define GPIO_PIPC5_PIPC58_SHIFT (8u) +#define GPIO_PIPC5_PIPC59_SHIFT (9u) +#define GPIO_PIPC5_PIPC510_SHIFT (10u) + +/* ---- P6 ---- */ +#define GPIO_P6_P60_SHIFT (0u) +#define GPIO_P6_P61_SHIFT (1u) +#define GPIO_P6_P62_SHIFT (2u) +#define GPIO_P6_P63_SHIFT (3u) +#define GPIO_P6_P64_SHIFT (4u) +#define GPIO_P6_P65_SHIFT (5u) +#define GPIO_P6_P66_SHIFT (6u) +#define GPIO_P6_P67_SHIFT (7u) +#define GPIO_P6_P68_SHIFT (8u) +#define GPIO_P6_P69_SHIFT (9u) +#define GPIO_P6_P610_SHIFT (10u) +#define GPIO_P6_P611_SHIFT (11u) +#define GPIO_P6_P612_SHIFT (12u) +#define GPIO_P6_P613_SHIFT (13u) +#define GPIO_P6_P614_SHIFT (14u) +#define GPIO_P6_P615_SHIFT (15u) + +#define GPIO_PSR6_PSR60_SHIFT (0u) +#define GPIO_PSR6_PSR61_SHIFT (1u) +#define GPIO_PSR6_PSR62_SHIFT (2u) +#define GPIO_PSR6_PSR63_SHIFT (3u) +#define GPIO_PSR6_PSR64_SHIFT (4u) +#define GPIO_PSR6_PSR65_SHIFT (5u) +#define GPIO_PSR6_PSR66_SHIFT (6u) +#define GPIO_PSR6_PSR67_SHIFT (7u) +#define GPIO_PSR6_PSR68_SHIFT (8u) +#define GPIO_PSR6_PSR69_SHIFT (9u) +#define GPIO_PSR6_PSR610_SHIFT (10u) +#define GPIO_PSR6_PSR611_SHIFT (11u) +#define GPIO_PSR6_PSR612_SHIFT (12u) +#define GPIO_PSR6_PSR613_SHIFT (13u) +#define GPIO_PSR6_PSR614_SHIFT (14u) +#define GPIO_PSR6_PSR615_SHIFT (15u) +#define GPIO_PSR6_PSR616_SHIFT (16u) +#define GPIO_PSR6_PSR617_SHIFT (17u) +#define GPIO_PSR6_PSR618_SHIFT (18u) +#define GPIO_PSR6_PSR619_SHIFT (19u) +#define GPIO_PSR6_PSR620_SHIFT (20u) +#define GPIO_PSR6_PSR621_SHIFT (21u) +#define GPIO_PSR6_PSR622_SHIFT (22u) +#define GPIO_PSR6_PSR623_SHIFT (23u) +#define GPIO_PSR6_PSR624_SHIFT (24u) +#define GPIO_PSR6_PSR625_SHIFT (25u) +#define GPIO_PSR6_PSR626_SHIFT (26u) +#define GPIO_PSR6_PSR627_SHIFT (27u) +#define GPIO_PSR6_PSR628_SHIFT (28u) +#define GPIO_PSR6_PSR629_SHIFT (29u) +#define GPIO_PSR6_PSR630_SHIFT (30u) +#define GPIO_PSR6_PSR631_SHIFT (31u) + +#define GPIO_PPR6_PPR60_SHIFT (0u) +#define GPIO_PPR6_PPR61_SHIFT (1u) +#define GPIO_PPR6_PPR62_SHIFT (2u) +#define GPIO_PPR6_PPR63_SHIFT (3u) +#define GPIO_PPR6_PPR64_SHIFT (4u) +#define GPIO_PPR6_PPR65_SHIFT (5u) +#define GPIO_PPR6_PPR66_SHIFT (6u) +#define GPIO_PPR6_PPR67_SHIFT (7u) +#define GPIO_PPR6_PPR68_SHIFT (8u) +#define GPIO_PPR6_PPR69_SHIFT (9u) +#define GPIO_PPR6_PPR610_SHIFT (10u) +#define GPIO_PPR6_PPR611_SHIFT (11u) +#define GPIO_PPR6_PPR612_SHIFT (12u) +#define GPIO_PPR6_PPR613_SHIFT (13u) +#define GPIO_PPR6_PPR614_SHIFT (14u) +#define GPIO_PPR6_PPR615_SHIFT (15u) + +#define GPIO_PM6_PM60_SHIFT (0u) +#define GPIO_PM6_PM61_SHIFT (1u) +#define GPIO_PM6_PM62_SHIFT (2u) +#define GPIO_PM6_PM63_SHIFT (3u) +#define GPIO_PM6_PM64_SHIFT (4u) +#define GPIO_PM6_PM65_SHIFT (5u) +#define GPIO_PM6_PM66_SHIFT (6u) +#define GPIO_PM6_PM67_SHIFT (7u) +#define GPIO_PM6_PM68_SHIFT (8u) +#define GPIO_PM6_PM69_SHIFT (9u) +#define GPIO_PM6_PM610_SHIFT (10u) +#define GPIO_PM6_PM611_SHIFT (11u) +#define GPIO_PM6_PM612_SHIFT (12u) +#define GPIO_PM6_PM613_SHIFT (13u) +#define GPIO_PM6_PM614_SHIFT (14u) +#define GPIO_PM6_PM615_SHIFT (15u) + +#define GPIO_PMC6_PMC60_SHIFT (0u) +#define GPIO_PMC6_PMC61_SHIFT (1u) +#define GPIO_PMC6_PMC62_SHIFT (2u) +#define GPIO_PMC6_PMC63_SHIFT (3u) +#define GPIO_PMC6_PMC64_SHIFT (4u) +#define GPIO_PMC6_PMC65_SHIFT (5u) +#define GPIO_PMC6_PMC66_SHIFT (6u) +#define GPIO_PMC6_PMC67_SHIFT (7u) +#define GPIO_PMC6_PMC68_SHIFT (8u) +#define GPIO_PMC6_PMC69_SHIFT (9u) +#define GPIO_PMC6_PMC610_SHIFT (10u) +#define GPIO_PMC6_PMC611_SHIFT (11u) +#define GPIO_PMC6_PMC612_SHIFT (12u) +#define GPIO_PMC6_PMC613_SHIFT (13u) +#define GPIO_PMC6_PMC614_SHIFT (14u) +#define GPIO_PMC6_PMC615_SHIFT (15u) + +#define GPIO_PFC6_PFC60_SHIFT (0u) +#define GPIO_PFC6_PFC61_SHIFT (1u) +#define GPIO_PFC6_PFC62_SHIFT (2u) +#define GPIO_PFC6_PFC63_SHIFT (3u) +#define GPIO_PFC6_PFC64_SHIFT (4u) +#define GPIO_PFC6_PFC65_SHIFT (5u) +#define GPIO_PFC6_PFC66_SHIFT (6u) +#define GPIO_PFC6_PFC67_SHIFT (7u) +#define GPIO_PFC6_PFC68_SHIFT (8u) +#define GPIO_PFC6_PFC69_SHIFT (9u) +#define GPIO_PFC6_PFC610_SHIFT (10u) +#define GPIO_PFC6_PFC611_SHIFT (11u) +#define GPIO_PFC6_PFC612_SHIFT (12u) +#define GPIO_PFC6_PFC613_SHIFT (13u) +#define GPIO_PFC6_PFC614_SHIFT (14u) +#define GPIO_PFC6_PFC615_SHIFT (15u) + +#define GPIO_PFCE6_PFCE60_SHIFT (0u) +#define GPIO_PFCE6_PFCE61_SHIFT (1u) +#define GPIO_PFCE6_PFCE62_SHIFT (2u) +#define GPIO_PFCE6_PFCE63_SHIFT (3u) +#define GPIO_PFCE6_PFCE64_SHIFT (4u) +#define GPIO_PFCE6_PFCE65_SHIFT (5u) +#define GPIO_PFCE6_PFCE66_SHIFT (6u) +#define GPIO_PFCE6_PFCE67_SHIFT (7u) +#define GPIO_PFCE6_PFCE68_SHIFT (8u) +#define GPIO_PFCE6_PFCE69_SHIFT (9u) +#define GPIO_PFCE6_PFCE610_SHIFT (10u) +#define GPIO_PFCE6_PFCE611_SHIFT (11u) +#define GPIO_PFCE6_PFCE612_SHIFT (12u) +#define GPIO_PFCE6_PFCE613_SHIFT (13u) +#define GPIO_PFCE6_PFCE614_SHIFT (14u) +#define GPIO_PFCE6_PFCE615_SHIFT (15u) + +#define GPIO_PNOT6_PNOT60_SHIFT (0u) +#define GPIO_PNOT6_PNOT61_SHIFT (1u) +#define GPIO_PNOT6_PNOT62_SHIFT (2u) +#define GPIO_PNOT6_PNOT63_SHIFT (3u) +#define GPIO_PNOT6_PNOT64_SHIFT (4u) +#define GPIO_PNOT6_PNOT65_SHIFT (5u) +#define GPIO_PNOT6_PNOT66_SHIFT (6u) +#define GPIO_PNOT6_PNOT67_SHIFT (7u) +#define GPIO_PNOT6_PNOT68_SHIFT (8u) +#define GPIO_PNOT6_PNOT69_SHIFT (9u) +#define GPIO_PNOT6_PNOT610_SHIFT (10u) +#define GPIO_PNOT6_PNOT611_SHIFT (11u) +#define GPIO_PNOT6_PNOT612_SHIFT (12u) +#define GPIO_PNOT6_PNOT613_SHIFT (13u) +#define GPIO_PNOT6_PNOT614_SHIFT (14u) +#define GPIO_PNOT6_PNOT615_SHIFT (15u) + +#define GPIO_PMSR6_PMSR60_SHIFT (0u) +#define GPIO_PMSR6_PMSR61_SHIFT (1u) +#define GPIO_PMSR6_PMSR62_SHIFT (2u) +#define GPIO_PMSR6_PMSR63_SHIFT (3u) +#define GPIO_PMSR6_PMSR64_SHIFT (4u) +#define GPIO_PMSR6_PMSR65_SHIFT (5u) +#define GPIO_PMSR6_PMSR66_SHIFT (6u) +#define GPIO_PMSR6_PMSR67_SHIFT (7u) +#define GPIO_PMSR6_PMSR68_SHIFT (8u) +#define GPIO_PMSR6_PMSR69_SHIFT (9u) +#define GPIO_PMSR6_PMSR610_SHIFT (10u) +#define GPIO_PMSR6_PMSR611_SHIFT (11u) +#define GPIO_PMSR6_PMSR612_SHIFT (12u) +#define GPIO_PMSR6_PMSR613_SHIFT (13u) +#define GPIO_PMSR6_PMSR614_SHIFT (14u) +#define GPIO_PMSR6_PMSR615_SHIFT (15u) +#define GPIO_PMSR6_PMSR616_SHIFT (16u) +#define GPIO_PMSR6_PMSR617_SHIFT (17u) +#define GPIO_PMSR6_PMSR618_SHIFT (18u) +#define GPIO_PMSR6_PMSR619_SHIFT (19u) +#define GPIO_PMSR6_PMSR620_SHIFT (20u) +#define GPIO_PMSR6_PMSR621_SHIFT (21u) +#define GPIO_PMSR6_PMSR622_SHIFT (22u) +#define GPIO_PMSR6_PMSR623_SHIFT (23u) +#define GPIO_PMSR6_PMSR624_SHIFT (24u) +#define GPIO_PMSR6_PMSR625_SHIFT (25u) +#define GPIO_PMSR6_PMSR626_SHIFT (26u) +#define GPIO_PMSR6_PMSR627_SHIFT (27u) +#define GPIO_PMSR6_PMSR628_SHIFT (28u) +#define GPIO_PMSR6_PMSR629_SHIFT (29u) +#define GPIO_PMSR6_PMSR630_SHIFT (30u) +#define GPIO_PMSR6_PMSR631_SHIFT (31u) + +#define GPIO_PMCSR6_PMCSR60_SHIFT (0u) +#define GPIO_PMCSR6_PMCSR61_SHIFT (1u) +#define GPIO_PMCSR6_PMCSR62_SHIFT (2u) +#define GPIO_PMCSR6_PMCSR63_SHIFT (3u) +#define GPIO_PMCSR6_PMCSR64_SHIFT (4u) +#define GPIO_PMCSR6_PMCSR65_SHIFT (5u) +#define GPIO_PMCSR6_PMCSR66_SHIFT (6u) +#define GPIO_PMCSR6_PMCSR67_SHIFT (7u) +#define GPIO_PMCSR6_PMCSR68_SHIFT (8u) +#define GPIO_PMCSR6_PMCSR69_SHIFT (9u) +#define GPIO_PMCSR6_PMCSR610_SHIFT (10u) +#define GPIO_PMCSR6_PMCSR611_SHIFT (11u) +#define GPIO_PMCSR6_PMCSR612_SHIFT (12u) +#define GPIO_PMCSR6_PMCSR613_SHIFT (13u) +#define GPIO_PMCSR6_PMCSR614_SHIFT (14u) +#define GPIO_PMCSR6_PMCSR615_SHIFT (15u) +#define GPIO_PMCSR6_PMCSR616_SHIFT (16u) +#define GPIO_PMCSR6_PMCSR617_SHIFT (17u) +#define GPIO_PMCSR6_PMCSR618_SHIFT (18u) +#define GPIO_PMCSR6_PMCSR619_SHIFT (19u) +#define GPIO_PMCSR6_PMCSR620_SHIFT (20u) +#define GPIO_PMCSR6_PMCSR621_SHIFT (21u) +#define GPIO_PMCSR6_PMCSR622_SHIFT (22u) +#define GPIO_PMCSR6_PMCSR623_SHIFT (23u) +#define GPIO_PMCSR6_PMCSR624_SHIFT (24u) +#define GPIO_PMCSR6_PMCSR625_SHIFT (25u) +#define GPIO_PMCSR6_PMCSR626_SHIFT (26u) +#define GPIO_PMCSR6_PMCSR627_SHIFT (27u) +#define GPIO_PMCSR6_PMCSR628_SHIFT (28u) +#define GPIO_PMCSR6_PMCSR629_SHIFT (29u) +#define GPIO_PMCSR6_PMCSR630_SHIFT (30u) +#define GPIO_PMCSR6_PMCSR631_SHIFT (31u) + +#define GPIO_PFCAE6_PFCAE60_SHIFT (0u) +#define GPIO_PFCAE6_PFCAE61_SHIFT (1u) +#define GPIO_PFCAE6_PFCAE62_SHIFT (2u) +#define GPIO_PFCAE6_PFCAE63_SHIFT (3u) +#define GPIO_PFCAE6_PFCAE64_SHIFT (4u) +#define GPIO_PFCAE6_PFCAE65_SHIFT (5u) +#define GPIO_PFCAE6_PFCAE66_SHIFT (6u) +#define GPIO_PFCAE6_PFCAE67_SHIFT (7u) +#define GPIO_PFCAE6_PFCAE68_SHIFT (8u) +#define GPIO_PFCAE6_PFCAE69_SHIFT (9u) +#define GPIO_PFCAE6_PFCAE610_SHIFT (10u) +#define GPIO_PFCAE6_PFCAE611_SHIFT (11u) +#define GPIO_PFCAE6_PFCAE612_SHIFT (12u) +#define GPIO_PFCAE6_PFCAE613_SHIFT (13u) +#define GPIO_PFCAE6_PFCAE614_SHIFT (14u) +#define GPIO_PFCAE6_PFCAE615_SHIFT (15u) + +#define GPIO_PIBC6_PIBC60_SHIFT (0u) +#define GPIO_PIBC6_PIBC61_SHIFT (1u) +#define GPIO_PIBC6_PIBC62_SHIFT (2u) +#define GPIO_PIBC6_PIBC63_SHIFT (3u) +#define GPIO_PIBC6_PIBC64_SHIFT (4u) +#define GPIO_PIBC6_PIBC65_SHIFT (5u) +#define GPIO_PIBC6_PIBC66_SHIFT (6u) +#define GPIO_PIBC6_PIBC67_SHIFT (7u) +#define GPIO_PIBC6_PIBC68_SHIFT (8u) +#define GPIO_PIBC6_PIBC69_SHIFT (9u) +#define GPIO_PIBC6_PIBC610_SHIFT (10u) +#define GPIO_PIBC6_PIBC611_SHIFT (11u) +#define GPIO_PIBC6_PIBC612_SHIFT (12u) +#define GPIO_PIBC6_PIBC613_SHIFT (13u) +#define GPIO_PIBC6_PIBC614_SHIFT (14u) +#define GPIO_PIBC6_PIBC615_SHIFT (15u) + +#define GPIO_PBDC6_PBDC60_SHIFT (0u) +#define GPIO_PBDC6_PBDC61_SHIFT (1u) +#define GPIO_PBDC6_PBDC62_SHIFT (2u) +#define GPIO_PBDC6_PBDC63_SHIFT (3u) +#define GPIO_PBDC6_PBDC64_SHIFT (4u) +#define GPIO_PBDC6_PBDC65_SHIFT (5u) +#define GPIO_PBDC6_PBDC66_SHIFT (6u) +#define GPIO_PBDC6_PBDC67_SHIFT (7u) +#define GPIO_PBDC6_PBDC68_SHIFT (8u) +#define GPIO_PBDC6_PBDC69_SHIFT (9u) +#define GPIO_PBDC6_PBDC610_SHIFT (10u) +#define GPIO_PBDC6_PBDC611_SHIFT (11u) +#define GPIO_PBDC6_PBDC612_SHIFT (12u) +#define GPIO_PBDC6_PBDC613_SHIFT (13u) +#define GPIO_PBDC6_PBDC614_SHIFT (14u) +#define GPIO_PBDC6_PBDC615_SHIFT (15u) + +#define GPIO_PIPC6_PIPC60_SHIFT (0u) +#define GPIO_PIPC6_PIPC61_SHIFT (1u) +#define GPIO_PIPC6_PIPC62_SHIFT (2u) +#define GPIO_PIPC6_PIPC63_SHIFT (3u) +#define GPIO_PIPC6_PIPC64_SHIFT (4u) +#define GPIO_PIPC6_PIPC65_SHIFT (5u) +#define GPIO_PIPC6_PIPC66_SHIFT (6u) +#define GPIO_PIPC6_PIPC67_SHIFT (7u) +#define GPIO_PIPC6_PIPC68_SHIFT (8u) +#define GPIO_PIPC6_PIPC69_SHIFT (9u) +#define GPIO_PIPC6_PIPC610_SHIFT (10u) +#define GPIO_PIPC6_PIPC611_SHIFT (11u) +#define GPIO_PIPC6_PIPC612_SHIFT (12u) +#define GPIO_PIPC6_PIPC613_SHIFT (13u) +#define GPIO_PIPC6_PIPC614_SHIFT (14u) +#define GPIO_PIPC6_PIPC615_SHIFT (15u) + +/* ---- P7 ---- */ +#define GPIO_P7_P70_SHIFT (0u) +#define GPIO_P7_P71_SHIFT (1u) +#define GPIO_P7_P72_SHIFT (2u) +#define GPIO_P7_P73_SHIFT (3u) +#define GPIO_P7_P74_SHIFT (4u) +#define GPIO_P7_P75_SHIFT (5u) +#define GPIO_P7_P76_SHIFT (6u) +#define GPIO_P7_P77_SHIFT (7u) +#define GPIO_P7_P78_SHIFT (8u) +#define GPIO_P7_P79_SHIFT (9u) +#define GPIO_P7_P710_SHIFT (10u) +#define GPIO_P7_P711_SHIFT (11u) +#define GPIO_P7_P712_SHIFT (12u) +#define GPIO_P7_P713_SHIFT (13u) +#define GPIO_P7_P714_SHIFT (14u) +#define GPIO_P7_P715_SHIFT (15u) + +#define GPIO_PSR7_PSR70_SHIFT (0u) +#define GPIO_PSR7_PSR71_SHIFT (1u) +#define GPIO_PSR7_PSR72_SHIFT (2u) +#define GPIO_PSR7_PSR73_SHIFT (3u) +#define GPIO_PSR7_PSR74_SHIFT (4u) +#define GPIO_PSR7_PSR75_SHIFT (5u) +#define GPIO_PSR7_PSR76_SHIFT (6u) +#define GPIO_PSR7_PSR77_SHIFT (7u) +#define GPIO_PSR7_PSR78_SHIFT (8u) +#define GPIO_PSR7_PSR79_SHIFT (9u) +#define GPIO_PSR7_PSR710_SHIFT (10u) +#define GPIO_PSR7_PSR711_SHIFT (11u) +#define GPIO_PSR7_PSR712_SHIFT (12u) +#define GPIO_PSR7_PSR713_SHIFT (13u) +#define GPIO_PSR7_PSR714_SHIFT (14u) +#define GPIO_PSR7_PSR715_SHIFT (15u) +#define GPIO_PSR7_PSR716_SHIFT (16u) +#define GPIO_PSR7_PSR717_SHIFT (17u) +#define GPIO_PSR7_PSR718_SHIFT (18u) +#define GPIO_PSR7_PSR719_SHIFT (19u) +#define GPIO_PSR7_PSR720_SHIFT (20u) +#define GPIO_PSR7_PSR721_SHIFT (21u) +#define GPIO_PSR7_PSR722_SHIFT (22u) +#define GPIO_PSR7_PSR723_SHIFT (23u) +#define GPIO_PSR7_PSR724_SHIFT (24u) +#define GPIO_PSR7_PSR725_SHIFT (25u) +#define GPIO_PSR7_PSR726_SHIFT (26u) +#define GPIO_PSR7_PSR727_SHIFT (27u) +#define GPIO_PSR7_PSR728_SHIFT (28u) +#define GPIO_PSR7_PSR729_SHIFT (29u) +#define GPIO_PSR7_PSR730_SHIFT (30u) +#define GPIO_PSR7_PSR731_SHIFT (31u) + +#define GPIO_PPR7_PPR70_SHIFT (0u) +#define GPIO_PPR7_PPR71_SHIFT (1u) +#define GPIO_PPR7_PPR72_SHIFT (2u) +#define GPIO_PPR7_PPR73_SHIFT (3u) +#define GPIO_PPR7_PPR74_SHIFT (4u) +#define GPIO_PPR7_PPR75_SHIFT (5u) +#define GPIO_PPR7_PPR76_SHIFT (6u) +#define GPIO_PPR7_PPR77_SHIFT (7u) +#define GPIO_PPR7_PPR78_SHIFT (8u) +#define GPIO_PPR7_PPR79_SHIFT (9u) +#define GPIO_PPR7_PPR710_SHIFT (10u) +#define GPIO_PPR7_PPR711_SHIFT (11u) +#define GPIO_PPR7_PPR712_SHIFT (12u) +#define GPIO_PPR7_PPR713_SHIFT (13u) +#define GPIO_PPR7_PPR714_SHIFT (14u) +#define GPIO_PPR7_PPR715_SHIFT (15u) + +#define GPIO_PM7_PM70_SHIFT (0u) +#define GPIO_PM7_PM71_SHIFT (1u) +#define GPIO_PM7_PM72_SHIFT (2u) +#define GPIO_PM7_PM73_SHIFT (3u) +#define GPIO_PM7_PM74_SHIFT (4u) +#define GPIO_PM7_PM75_SHIFT (5u) +#define GPIO_PM7_PM76_SHIFT (6u) +#define GPIO_PM7_PM77_SHIFT (7u) +#define GPIO_PM7_PM78_SHIFT (8u) +#define GPIO_PM7_PM79_SHIFT (9u) +#define GPIO_PM7_PM710_SHIFT (10u) +#define GPIO_PM7_PM711_SHIFT (11u) +#define GPIO_PM7_PM712_SHIFT (12u) +#define GPIO_PM7_PM713_SHIFT (13u) +#define GPIO_PM7_PM714_SHIFT (14u) +#define GPIO_PM7_PM715_SHIFT (15u) + +#define GPIO_PMC7_PMC70_SHIFT (0u) +#define GPIO_PMC7_PMC71_SHIFT (1u) +#define GPIO_PMC7_PMC72_SHIFT (2u) +#define GPIO_PMC7_PMC73_SHIFT (3u) +#define GPIO_PMC7_PMC74_SHIFT (4u) +#define GPIO_PMC7_PMC75_SHIFT (5u) +#define GPIO_PMC7_PMC76_SHIFT (6u) +#define GPIO_PMC7_PMC77_SHIFT (7u) +#define GPIO_PMC7_PMC78_SHIFT (8u) +#define GPIO_PMC7_PMC79_SHIFT (9u) +#define GPIO_PMC7_PMC710_SHIFT (10u) +#define GPIO_PMC7_PMC711_SHIFT (11u) +#define GPIO_PMC7_PMC712_SHIFT (12u) +#define GPIO_PMC7_PMC713_SHIFT (13u) +#define GPIO_PMC7_PMC714_SHIFT (14u) +#define GPIO_PMC7_PMC715_SHIFT (15u) + +#define GPIO_PFC7_PFC70_SHIFT (0u) +#define GPIO_PFC7_PFC71_SHIFT (1u) +#define GPIO_PFC7_PFC72_SHIFT (2u) +#define GPIO_PFC7_PFC73_SHIFT (3u) +#define GPIO_PFC7_PFC74_SHIFT (4u) +#define GPIO_PFC7_PFC75_SHIFT (5u) +#define GPIO_PFC7_PFC76_SHIFT (6u) +#define GPIO_PFC7_PFC77_SHIFT (7u) +#define GPIO_PFC7_PFC78_SHIFT (8u) +#define GPIO_PFC7_PFC79_SHIFT (9u) +#define GPIO_PFC7_PFC710_SHIFT (10u) +#define GPIO_PFC7_PFC711_SHIFT (11u) +#define GPIO_PFC7_PFC712_SHIFT (12u) +#define GPIO_PFC7_PFC713_SHIFT (13u) +#define GPIO_PFC7_PFC714_SHIFT (14u) +#define GPIO_PFC7_PFC715_SHIFT (15u) + +#define GPIO_PFCE7_PFCE70_SHIFT (0u) +#define GPIO_PFCE7_PFCE71_SHIFT (1u) +#define GPIO_PFCE7_PFCE72_SHIFT (2u) +#define GPIO_PFCE7_PFCE73_SHIFT (3u) +#define GPIO_PFCE7_PFCE74_SHIFT (4u) +#define GPIO_PFCE7_PFCE75_SHIFT (5u) +#define GPIO_PFCE7_PFCE76_SHIFT (6u) +#define GPIO_PFCE7_PFCE77_SHIFT (7u) +#define GPIO_PFCE7_PFCE78_SHIFT (8u) +#define GPIO_PFCE7_PFCE79_SHIFT (9u) +#define GPIO_PFCE7_PFCE710_SHIFT (10u) +#define GPIO_PFCE7_PFCE711_SHIFT (11u) +#define GPIO_PFCE7_PFCE712_SHIFT (12u) +#define GPIO_PFCE7_PFCE713_SHIFT (13u) +#define GPIO_PFCE7_PFCE714_SHIFT (14u) +#define GPIO_PFCE7_PFCE715_SHIFT (15u) + +#define GPIO_PNOT7_PNOT70_SHIFT (0u) +#define GPIO_PNOT7_PNOT71_SHIFT (1u) +#define GPIO_PNOT7_PNOT72_SHIFT (2u) +#define GPIO_PNOT7_PNOT73_SHIFT (3u) +#define GPIO_PNOT7_PNOT74_SHIFT (4u) +#define GPIO_PNOT7_PNOT75_SHIFT (5u) +#define GPIO_PNOT7_PNOT76_SHIFT (6u) +#define GPIO_PNOT7_PNOT77_SHIFT (7u) +#define GPIO_PNOT7_PNOT78_SHIFT (8u) +#define GPIO_PNOT7_PNOT79_SHIFT (9u) +#define GPIO_PNOT7_PNOT710_SHIFT (10u) +#define GPIO_PNOT7_PNOT711_SHIFT (11u) +#define GPIO_PNOT7_PNOT712_SHIFT (12u) +#define GPIO_PNOT7_PNOT713_SHIFT (13u) +#define GPIO_PNOT7_PNOT714_SHIFT (14u) +#define GPIO_PNOT7_PNOT715_SHIFT (15u) + +#define GPIO_PMSR7_PMSR70_SHIFT (0u) +#define GPIO_PMSR7_PMSR71_SHIFT (1u) +#define GPIO_PMSR7_PMSR72_SHIFT (2u) +#define GPIO_PMSR7_PMSR73_SHIFT (3u) +#define GPIO_PMSR7_PMSR74_SHIFT (4u) +#define GPIO_PMSR7_PMSR75_SHIFT (5u) +#define GPIO_PMSR7_PMSR76_SHIFT (6u) +#define GPIO_PMSR7_PMSR77_SHIFT (7u) +#define GPIO_PMSR7_PMSR78_SHIFT (8u) +#define GPIO_PMSR7_PMSR79_SHIFT (9u) +#define GPIO_PMSR7_PMSR710_SHIFT (10u) +#define GPIO_PMSR7_PMSR711_SHIFT (11u) +#define GPIO_PMSR7_PMSR712_SHIFT (12u) +#define GPIO_PMSR7_PMSR713_SHIFT (13u) +#define GPIO_PMSR7_PMSR714_SHIFT (14u) +#define GPIO_PMSR7_PMSR715_SHIFT (15u) +#define GPIO_PMSR7_PMSR716_SHIFT (16u) +#define GPIO_PMSR7_PMSR717_SHIFT (17u) +#define GPIO_PMSR7_PMSR718_SHIFT (18u) +#define GPIO_PMSR7_PMSR719_SHIFT (19u) +#define GPIO_PMSR7_PMSR720_SHIFT (20u) +#define GPIO_PMSR7_PMSR721_SHIFT (21u) +#define GPIO_PMSR7_PMSR722_SHIFT (22u) +#define GPIO_PMSR7_PMSR723_SHIFT (23u) +#define GPIO_PMSR7_PMSR724_SHIFT (24u) +#define GPIO_PMSR7_PMSR725_SHIFT (25u) +#define GPIO_PMSR7_PMSR726_SHIFT (26u) +#define GPIO_PMSR7_PMSR727_SHIFT (27u) +#define GPIO_PMSR7_PMSR728_SHIFT (28u) +#define GPIO_PMSR7_PMSR729_SHIFT (29u) +#define GPIO_PMSR7_PMSR730_SHIFT (30u) +#define GPIO_PMSR7_PMSR731_SHIFT (31u) + +#define GPIO_PMCSR7_PMCSR70_SHIFT (0u) +#define GPIO_PMCSR7_PMCSR71_SHIFT (1u) +#define GPIO_PMCSR7_PMCSR72_SHIFT (2u) +#define GPIO_PMCSR7_PMCSR73_SHIFT (3u) +#define GPIO_PMCSR7_PMCSR74_SHIFT (4u) +#define GPIO_PMCSR7_PMCSR75_SHIFT (5u) +#define GPIO_PMCSR7_PMCSR76_SHIFT (6u) +#define GPIO_PMCSR7_PMCSR77_SHIFT (7u) +#define GPIO_PMCSR7_PMCSR78_SHIFT (8u) +#define GPIO_PMCSR7_PMCSR79_SHIFT (9u) +#define GPIO_PMCSR7_PMCSR710_SHIFT (10u) +#define GPIO_PMCSR7_PMCSR711_SHIFT (11u) +#define GPIO_PMCSR7_PMCSR712_SHIFT (12u) +#define GPIO_PMCSR7_PMCSR713_SHIFT (13u) +#define GPIO_PMCSR7_PMCSR714_SHIFT (14u) +#define GPIO_PMCSR7_PMCSR715_SHIFT (15u) +#define GPIO_PMCSR7_PMCSR716_SHIFT (16u) +#define GPIO_PMCSR7_PMCSR717_SHIFT (17u) +#define GPIO_PMCSR7_PMCSR718_SHIFT (18u) +#define GPIO_PMCSR7_PMCSR719_SHIFT (19u) +#define GPIO_PMCSR7_PMCSR720_SHIFT (20u) +#define GPIO_PMCSR7_PMCSR721_SHIFT (21u) +#define GPIO_PMCSR7_PMCSR722_SHIFT (22u) +#define GPIO_PMCSR7_PMCSR723_SHIFT (23u) +#define GPIO_PMCSR7_PMCSR724_SHIFT (24u) +#define GPIO_PMCSR7_PMCSR725_SHIFT (25u) +#define GPIO_PMCSR7_PMCSR726_SHIFT (26u) +#define GPIO_PMCSR7_PMCSR727_SHIFT (27u) +#define GPIO_PMCSR7_PMCSR728_SHIFT (28u) +#define GPIO_PMCSR7_PMCSR729_SHIFT (29u) +#define GPIO_PMCSR7_PMCSR730_SHIFT (30u) +#define GPIO_PMCSR7_PMCSR731_SHIFT (31u) + +#define GPIO_PFCAE7_PFCAE70_SHIFT (0u) +#define GPIO_PFCAE7_PFCAE71_SHIFT (1u) +#define GPIO_PFCAE7_PFCAE72_SHIFT (2u) +#define GPIO_PFCAE7_PFCAE73_SHIFT (3u) +#define GPIO_PFCAE7_PFCAE74_SHIFT (4u) +#define GPIO_PFCAE7_PFCAE75_SHIFT (5u) +#define GPIO_PFCAE7_PFCAE76_SHIFT (6u) +#define GPIO_PFCAE7_PFCAE77_SHIFT (7u) +#define GPIO_PFCAE7_PFCAE78_SHIFT (8u) +#define GPIO_PFCAE7_PFCAE79_SHIFT (9u) +#define GPIO_PFCAE7_PFCAE710_SHIFT (10u) +#define GPIO_PFCAE7_PFCAE711_SHIFT (11u) +#define GPIO_PFCAE7_PFCAE712_SHIFT (12u) +#define GPIO_PFCAE7_PFCAE713_SHIFT (13u) +#define GPIO_PFCAE7_PFCAE714_SHIFT (14u) +#define GPIO_PFCAE7_PFCAE715_SHIFT (15u) + +#define GPIO_PIBC7_PIBC70_SHIFT (0u) +#define GPIO_PIBC7_PIBC71_SHIFT (1u) +#define GPIO_PIBC7_PIBC72_SHIFT (2u) +#define GPIO_PIBC7_PIBC73_SHIFT (3u) +#define GPIO_PIBC7_PIBC74_SHIFT (4u) +#define GPIO_PIBC7_PIBC75_SHIFT (5u) +#define GPIO_PIBC7_PIBC76_SHIFT (6u) +#define GPIO_PIBC7_PIBC77_SHIFT (7u) +#define GPIO_PIBC7_PIBC78_SHIFT (8u) +#define GPIO_PIBC7_PIBC79_SHIFT (9u) +#define GPIO_PIBC7_PIBC710_SHIFT (10u) +#define GPIO_PIBC7_PIBC711_SHIFT (11u) +#define GPIO_PIBC7_PIBC712_SHIFT (12u) +#define GPIO_PIBC7_PIBC713_SHIFT (13u) +#define GPIO_PIBC7_PIBC714_SHIFT (14u) +#define GPIO_PIBC7_PIBC715_SHIFT (15u) + +#define GPIO_PBDC7_PBDC70_SHIFT (0u) +#define GPIO_PBDC7_PBDC71_SHIFT (1u) +#define GPIO_PBDC7_PBDC72_SHIFT (2u) +#define GPIO_PBDC7_PBDC73_SHIFT (3u) +#define GPIO_PBDC7_PBDC74_SHIFT (4u) +#define GPIO_PBDC7_PBDC75_SHIFT (5u) +#define GPIO_PBDC7_PBDC76_SHIFT (6u) +#define GPIO_PBDC7_PBDC77_SHIFT (7u) +#define GPIO_PBDC7_PBDC78_SHIFT (8u) +#define GPIO_PBDC7_PBDC79_SHIFT (9u) +#define GPIO_PBDC7_PBDC710_SHIFT (10u) +#define GPIO_PBDC7_PBDC711_SHIFT (11u) +#define GPIO_PBDC7_PBDC712_SHIFT (12u) +#define GPIO_PBDC7_PBDC713_SHIFT (13u) +#define GPIO_PBDC7_PBDC714_SHIFT (14u) +#define GPIO_PBDC7_PBDC715_SHIFT (15u) + +#define GPIO_PIPC7_PIPC70_SHIFT (0u) +#define GPIO_PIPC7_PIPC71_SHIFT (1u) +#define GPIO_PIPC7_PIPC72_SHIFT (2u) +#define GPIO_PIPC7_PIPC73_SHIFT (3u) +#define GPIO_PIPC7_PIPC74_SHIFT (4u) +#define GPIO_PIPC7_PIPC75_SHIFT (5u) +#define GPIO_PIPC7_PIPC76_SHIFT (6u) +#define GPIO_PIPC7_PIPC77_SHIFT (7u) +#define GPIO_PIPC7_PIPC78_SHIFT (8u) +#define GPIO_PIPC7_PIPC79_SHIFT (9u) +#define GPIO_PIPC7_PIPC710_SHIFT (10u) +#define GPIO_PIPC7_PIPC711_SHIFT (11u) +#define GPIO_PIPC7_PIPC712_SHIFT (12u) +#define GPIO_PIPC7_PIPC713_SHIFT (13u) +#define GPIO_PIPC7_PIPC714_SHIFT (14u) +#define GPIO_PIPC7_PIPC715_SHIFT (15u) + +/* ---- P8 ---- */ +#define GPIO_P8_P80_SHIFT (0u) +#define GPIO_P8_P81_SHIFT (1u) +#define GPIO_P8_P82_SHIFT (2u) +#define GPIO_P8_P83_SHIFT (3u) +#define GPIO_P8_P84_SHIFT (4u) +#define GPIO_P8_P85_SHIFT (5u) +#define GPIO_P8_P86_SHIFT (6u) +#define GPIO_P8_P87_SHIFT (7u) +#define GPIO_P8_P88_SHIFT (8u) +#define GPIO_P8_P89_SHIFT (9u) +#define GPIO_P8_P810_SHIFT (10u) +#define GPIO_P8_P811_SHIFT (11u) +#define GPIO_P8_P812_SHIFT (12u) +#define GPIO_P8_P813_SHIFT (13u) +#define GPIO_P8_P814_SHIFT (14u) +#define GPIO_P8_P815_SHIFT (15u) + +#define GPIO_PSR8_PSR80_SHIFT (0u) +#define GPIO_PSR8_PSR81_SHIFT (1u) +#define GPIO_PSR8_PSR82_SHIFT (2u) +#define GPIO_PSR8_PSR83_SHIFT (3u) +#define GPIO_PSR8_PSR84_SHIFT (4u) +#define GPIO_PSR8_PSR85_SHIFT (5u) +#define GPIO_PSR8_PSR86_SHIFT (6u) +#define GPIO_PSR8_PSR87_SHIFT (7u) +#define GPIO_PSR8_PSR88_SHIFT (8u) +#define GPIO_PSR8_PSR89_SHIFT (9u) +#define GPIO_PSR8_PSR810_SHIFT (10u) +#define GPIO_PSR8_PSR811_SHIFT (11u) +#define GPIO_PSR8_PSR812_SHIFT (12u) +#define GPIO_PSR8_PSR813_SHIFT (13u) +#define GPIO_PSR8_PSR814_SHIFT (14u) +#define GPIO_PSR8_PSR815_SHIFT (15u) +#define GPIO_PSR8_PSR816_SHIFT (16u) +#define GPIO_PSR8_PSR817_SHIFT (17u) +#define GPIO_PSR8_PSR818_SHIFT (18u) +#define GPIO_PSR8_PSR819_SHIFT (19u) +#define GPIO_PSR8_PSR820_SHIFT (20u) +#define GPIO_PSR8_PSR821_SHIFT (21u) +#define GPIO_PSR8_PSR822_SHIFT (22u) +#define GPIO_PSR8_PSR823_SHIFT (23u) +#define GPIO_PSR8_PSR824_SHIFT (24u) +#define GPIO_PSR8_PSR825_SHIFT (25u) +#define GPIO_PSR8_PSR826_SHIFT (26u) +#define GPIO_PSR8_PSR827_SHIFT (27u) +#define GPIO_PSR8_PSR828_SHIFT (28u) +#define GPIO_PSR8_PSR829_SHIFT (29u) +#define GPIO_PSR8_PSR830_SHIFT (30u) +#define GPIO_PSR8_PSR831_SHIFT (31u) + +#define GPIO_PPR8_PPR80_SHIFT (0u) +#define GPIO_PPR8_PPR81_SHIFT (1u) +#define GPIO_PPR8_PPR82_SHIFT (2u) +#define GPIO_PPR8_PPR83_SHIFT (3u) +#define GPIO_PPR8_PPR84_SHIFT (4u) +#define GPIO_PPR8_PPR85_SHIFT (5u) +#define GPIO_PPR8_PPR86_SHIFT (6u) +#define GPIO_PPR8_PPR87_SHIFT (7u) +#define GPIO_PPR8_PPR88_SHIFT (8u) +#define GPIO_PPR8_PPR89_SHIFT (9u) +#define GPIO_PPR8_PPR810_SHIFT (10u) +#define GPIO_PPR8_PPR811_SHIFT (11u) +#define GPIO_PPR8_PPR812_SHIFT (12u) +#define GPIO_PPR8_PPR813_SHIFT (13u) +#define GPIO_PPR8_PPR814_SHIFT (14u) +#define GPIO_PPR8_PPR815_SHIFT (15u) + +#define GPIO_PM8_PM80_SHIFT (0u) +#define GPIO_PM8_PM81_SHIFT (1u) +#define GPIO_PM8_PM82_SHIFT (2u) +#define GPIO_PM8_PM83_SHIFT (3u) +#define GPIO_PM8_PM84_SHIFT (4u) +#define GPIO_PM8_PM85_SHIFT (5u) +#define GPIO_PM8_PM86_SHIFT (6u) +#define GPIO_PM8_PM87_SHIFT (7u) +#define GPIO_PM8_PM88_SHIFT (8u) +#define GPIO_PM8_PM89_SHIFT (9u) +#define GPIO_PM8_PM810_SHIFT (10u) +#define GPIO_PM8_PM811_SHIFT (11u) +#define GPIO_PM8_PM812_SHIFT (12u) +#define GPIO_PM8_PM813_SHIFT (13u) +#define GPIO_PM8_PM814_SHIFT (14u) +#define GPIO_PM8_PM815_SHIFT (15u) + +#define GPIO_PMC8_PMC80_SHIFT (0u) +#define GPIO_PMC8_PMC81_SHIFT (1u) +#define GPIO_PMC8_PMC82_SHIFT (2u) +#define GPIO_PMC8_PMC83_SHIFT (3u) +#define GPIO_PMC8_PMC84_SHIFT (4u) +#define GPIO_PMC8_PMC85_SHIFT (5u) +#define GPIO_PMC8_PMC86_SHIFT (6u) +#define GPIO_PMC8_PMC87_SHIFT (7u) +#define GPIO_PMC8_PMC88_SHIFT (8u) +#define GPIO_PMC8_PMC89_SHIFT (9u) +#define GPIO_PMC8_PMC810_SHIFT (10u) +#define GPIO_PMC8_PMC811_SHIFT (11u) +#define GPIO_PMC8_PMC812_SHIFT (12u) +#define GPIO_PMC8_PMC813_SHIFT (13u) +#define GPIO_PMC8_PMC814_SHIFT (14u) +#define GPIO_PMC8_PMC815_SHIFT (15u) + +#define GPIO_PFC8_PFC80_SHIFT (0u) +#define GPIO_PFC8_PFC81_SHIFT (1u) +#define GPIO_PFC8_PFC82_SHIFT (2u) +#define GPIO_PFC8_PFC83_SHIFT (3u) +#define GPIO_PFC8_PFC84_SHIFT (4u) +#define GPIO_PFC8_PFC85_SHIFT (5u) +#define GPIO_PFC8_PFC86_SHIFT (6u) +#define GPIO_PFC8_PFC87_SHIFT (7u) +#define GPIO_PFC8_PFC88_SHIFT (8u) +#define GPIO_PFC8_PFC89_SHIFT (9u) +#define GPIO_PFC8_PFC810_SHIFT (10u) +#define GPIO_PFC8_PFC811_SHIFT (11u) +#define GPIO_PFC8_PFC812_SHIFT (12u) +#define GPIO_PFC8_PFC813_SHIFT (13u) +#define GPIO_PFC8_PFC814_SHIFT (14u) +#define GPIO_PFC8_PFC815_SHIFT (15u) + +#define GPIO_PFCE8_PFCE80_SHIFT (0u) +#define GPIO_PFCE8_PFCE81_SHIFT (1u) +#define GPIO_PFCE8_PFCE82_SHIFT (2u) +#define GPIO_PFCE8_PFCE83_SHIFT (3u) +#define GPIO_PFCE8_PFCE84_SHIFT (4u) +#define GPIO_PFCE8_PFCE85_SHIFT (5u) +#define GPIO_PFCE8_PFCE86_SHIFT (6u) +#define GPIO_PFCE8_PFCE87_SHIFT (7u) +#define GPIO_PFCE8_PFCE88_SHIFT (8u) +#define GPIO_PFCE8_PFCE89_SHIFT (9u) +#define GPIO_PFCE8_PFCE810_SHIFT (10u) +#define GPIO_PFCE8_PFCE811_SHIFT (11u) +#define GPIO_PFCE8_PFCE812_SHIFT (12u) +#define GPIO_PFCE8_PFCE813_SHIFT (13u) +#define GPIO_PFCE8_PFCE814_SHIFT (14u) +#define GPIO_PFCE8_PFCE815_SHIFT (15u) + +#define GPIO_PNOT8_PNOT80_SHIFT (0u) +#define GPIO_PNOT8_PNOT81_SHIFT (1u) +#define GPIO_PNOT8_PNOT82_SHIFT (2u) +#define GPIO_PNOT8_PNOT83_SHIFT (3u) +#define GPIO_PNOT8_PNOT84_SHIFT (4u) +#define GPIO_PNOT8_PNOT85_SHIFT (5u) +#define GPIO_PNOT8_PNOT86_SHIFT (6u) +#define GPIO_PNOT8_PNOT87_SHIFT (7u) +#define GPIO_PNOT8_PNOT88_SHIFT (8u) +#define GPIO_PNOT8_PNOT89_SHIFT (9u) +#define GPIO_PNOT8_PNOT810_SHIFT (10u) +#define GPIO_PNOT8_PNOT811_SHIFT (11u) +#define GPIO_PNOT8_PNOT812_SHIFT (12u) +#define GPIO_PNOT8_PNOT813_SHIFT (13u) +#define GPIO_PNOT8_PNOT814_SHIFT (14u) +#define GPIO_PNOT8_PNOT815_SHIFT (15u) + +#define GPIO_PMSR8_PMSR80_SHIFT (0u) +#define GPIO_PMSR8_PMSR81_SHIFT (1u) +#define GPIO_PMSR8_PMSR82_SHIFT (2u) +#define GPIO_PMSR8_PMSR83_SHIFT (3u) +#define GPIO_PMSR8_PMSR84_SHIFT (4u) +#define GPIO_PMSR8_PMSR85_SHIFT (5u) +#define GPIO_PMSR8_PMSR86_SHIFT (6u) +#define GPIO_PMSR8_PMSR87_SHIFT (7u) +#define GPIO_PMSR8_PMSR88_SHIFT (8u) +#define GPIO_PMSR8_PMSR89_SHIFT (9u) +#define GPIO_PMSR8_PMSR810_SHIFT (10u) +#define GPIO_PMSR8_PMSR811_SHIFT (11u) +#define GPIO_PMSR8_PMSR812_SHIFT (12u) +#define GPIO_PMSR8_PMSR813_SHIFT (13u) +#define GPIO_PMSR8_PMSR814_SHIFT (14u) +#define GPIO_PMSR8_PMSR815_SHIFT (15u) +#define GPIO_PMSR8_PMSR816_SHIFT (16u) +#define GPIO_PMSR8_PMSR817_SHIFT (17u) +#define GPIO_PMSR8_PMSR818_SHIFT (18u) +#define GPIO_PMSR8_PMSR819_SHIFT (19u) +#define GPIO_PMSR8_PMSR820_SHIFT (20u) +#define GPIO_PMSR8_PMSR821_SHIFT (21u) +#define GPIO_PMSR8_PMSR822_SHIFT (22u) +#define GPIO_PMSR8_PMSR823_SHIFT (23u) +#define GPIO_PMSR8_PMSR824_SHIFT (24u) +#define GPIO_PMSR8_PMSR825_SHIFT (25u) +#define GPIO_PMSR8_PMSR826_SHIFT (26u) +#define GPIO_PMSR8_PMSR827_SHIFT (27u) +#define GPIO_PMSR8_PMSR828_SHIFT (28u) +#define GPIO_PMSR8_PMSR829_SHIFT (29u) +#define GPIO_PMSR8_PMSR830_SHIFT (30u) +#define GPIO_PMSR8_PMSR831_SHIFT (31u) + +#define GPIO_PMCSR8_PMCSR80_SHIFT (0u) +#define GPIO_PMCSR8_PMCSR81_SHIFT (1u) +#define GPIO_PMCSR8_PMCSR82_SHIFT (2u) +#define GPIO_PMCSR8_PMCSR83_SHIFT (3u) +#define GPIO_PMCSR8_PMCSR84_SHIFT (4u) +#define GPIO_PMCSR8_PMCSR85_SHIFT (5u) +#define GPIO_PMCSR8_PMCSR86_SHIFT (6u) +#define GPIO_PMCSR8_PMCSR87_SHIFT (7u) +#define GPIO_PMCSR8_PMCSR88_SHIFT (8u) +#define GPIO_PMCSR8_PMCSR89_SHIFT (9u) +#define GPIO_PMCSR8_PMCSR810_SHIFT (10u) +#define GPIO_PMCSR8_PMCSR811_SHIFT (11u) +#define GPIO_PMCSR8_PMCSR812_SHIFT (12u) +#define GPIO_PMCSR8_PMCSR813_SHIFT (13u) +#define GPIO_PMCSR8_PMCSR814_SHIFT (14u) +#define GPIO_PMCSR8_PMCSR815_SHIFT (15u) +#define GPIO_PMCSR8_PMCSR816_SHIFT (16u) +#define GPIO_PMCSR8_PMCSR817_SHIFT (17u) +#define GPIO_PMCSR8_PMCSR818_SHIFT (18u) +#define GPIO_PMCSR8_PMCSR819_SHIFT (19u) +#define GPIO_PMCSR8_PMCSR820_SHIFT (20u) +#define GPIO_PMCSR8_PMCSR821_SHIFT (21u) +#define GPIO_PMCSR8_PMCSR822_SHIFT (22u) +#define GPIO_PMCSR8_PMCSR823_SHIFT (23u) +#define GPIO_PMCSR8_PMCSR824_SHIFT (24u) +#define GPIO_PMCSR8_PMCSR825_SHIFT (25u) +#define GPIO_PMCSR8_PMCSR826_SHIFT (26u) +#define GPIO_PMCSR8_PMCSR827_SHIFT (27u) +#define GPIO_PMCSR8_PMCSR828_SHIFT (28u) +#define GPIO_PMCSR8_PMCSR829_SHIFT (29u) +#define GPIO_PMCSR8_PMCSR830_SHIFT (30u) +#define GPIO_PMCSR8_PMCSR831_SHIFT (31u) + +#define GPIO_PFCAE8_PFCAE80_SHIFT (0u) +#define GPIO_PFCAE8_PFCAE81_SHIFT (1u) +#define GPIO_PFCAE8_PFCAE82_SHIFT (2u) +#define GPIO_PFCAE8_PFCAE83_SHIFT (3u) +#define GPIO_PFCAE8_PFCAE84_SHIFT (4u) +#define GPIO_PFCAE8_PFCAE85_SHIFT (5u) +#define GPIO_PFCAE8_PFCAE86_SHIFT (6u) +#define GPIO_PFCAE8_PFCAE87_SHIFT (7u) +#define GPIO_PFCAE8_PFCAE88_SHIFT (8u) +#define GPIO_PFCAE8_PFCAE89_SHIFT (9u) +#define GPIO_PFCAE8_PFCAE810_SHIFT (10u) +#define GPIO_PFCAE8_PFCAE811_SHIFT (11u) +#define GPIO_PFCAE8_PFCAE812_SHIFT (12u) +#define GPIO_PFCAE8_PFCAE813_SHIFT (13u) +#define GPIO_PFCAE8_PFCAE814_SHIFT (14u) +#define GPIO_PFCAE8_PFCAE815_SHIFT (15u) + +#define GPIO_PIBC8_PIBC80_SHIFT (0u) +#define GPIO_PIBC8_PIBC81_SHIFT (1u) +#define GPIO_PIBC8_PIBC82_SHIFT (2u) +#define GPIO_PIBC8_PIBC83_SHIFT (3u) +#define GPIO_PIBC8_PIBC84_SHIFT (4u) +#define GPIO_PIBC8_PIBC85_SHIFT (5u) +#define GPIO_PIBC8_PIBC86_SHIFT (6u) +#define GPIO_PIBC8_PIBC87_SHIFT (7u) +#define GPIO_PIBC8_PIBC88_SHIFT (8u) +#define GPIO_PIBC8_PIBC89_SHIFT (9u) +#define GPIO_PIBC8_PIBC810_SHIFT (10u) +#define GPIO_PIBC8_PIBC811_SHIFT (11u) +#define GPIO_PIBC8_PIBC812_SHIFT (12u) +#define GPIO_PIBC8_PIBC813_SHIFT (13u) +#define GPIO_PIBC8_PIBC814_SHIFT (14u) +#define GPIO_PIBC8_PIBC815_SHIFT (15u) + +#define GPIO_PBDC8_PBDC80_SHIFT (0u) +#define GPIO_PBDC8_PBDC81_SHIFT (1u) +#define GPIO_PBDC8_PBDC82_SHIFT (2u) +#define GPIO_PBDC8_PBDC83_SHIFT (3u) +#define GPIO_PBDC8_PBDC84_SHIFT (4u) +#define GPIO_PBDC8_PBDC85_SHIFT (5u) +#define GPIO_PBDC8_PBDC86_SHIFT (6u) +#define GPIO_PBDC8_PBDC87_SHIFT (7u) +#define GPIO_PBDC8_PBDC88_SHIFT (8u) +#define GPIO_PBDC8_PBDC89_SHIFT (9u) +#define GPIO_PBDC8_PBDC810_SHIFT (10u) +#define GPIO_PBDC8_PBDC811_SHIFT (11u) +#define GPIO_PBDC8_PBDC812_SHIFT (12u) +#define GPIO_PBDC8_PBDC813_SHIFT (13u) +#define GPIO_PBDC8_PBDC814_SHIFT (14u) +#define GPIO_PBDC8_PBDC815_SHIFT (15u) + +#define GPIO_PIPC8_PIPC80_SHIFT (0u) +#define GPIO_PIPC8_PIPC81_SHIFT (1u) +#define GPIO_PIPC8_PIPC82_SHIFT (2u) +#define GPIO_PIPC8_PIPC83_SHIFT (3u) +#define GPIO_PIPC8_PIPC84_SHIFT (4u) +#define GPIO_PIPC8_PIPC85_SHIFT (5u) +#define GPIO_PIPC8_PIPC86_SHIFT (6u) +#define GPIO_PIPC8_PIPC87_SHIFT (7u) +#define GPIO_PIPC8_PIPC88_SHIFT (8u) +#define GPIO_PIPC8_PIPC89_SHIFT (9u) +#define GPIO_PIPC8_PIPC810_SHIFT (10u) +#define GPIO_PIPC8_PIPC811_SHIFT (11u) +#define GPIO_PIPC8_PIPC812_SHIFT (12u) +#define GPIO_PIPC8_PIPC813_SHIFT (13u) +#define GPIO_PIPC8_PIPC814_SHIFT (14u) +#define GPIO_PIPC8_PIPC815_SHIFT (15u) + +/* ---- P9 ---- */ +#define GPIO_P9_P90_SHIFT (0u) +#define GPIO_P9_P91_SHIFT (1u) +#define GPIO_P9_P92_SHIFT (2u) +#define GPIO_P9_P93_SHIFT (3u) +#define GPIO_P9_P94_SHIFT (4u) +#define GPIO_P9_P95_SHIFT (5u) +#define GPIO_P9_P96_SHIFT (6u) +#define GPIO_P9_P97_SHIFT (7u) + +#define GPIO_PSR9_PSR90_SHIFT (0u) +#define GPIO_PSR9_PSR91_SHIFT (1u) +#define GPIO_PSR9_PSR92_SHIFT (2u) +#define GPIO_PSR9_PSR93_SHIFT (3u) +#define GPIO_PSR9_PSR94_SHIFT (4u) +#define GPIO_PSR9_PSR95_SHIFT (5u) +#define GPIO_PSR9_PSR96_SHIFT (6u) +#define GPIO_PSR9_PSR97_SHIFT (7u) +#define GPIO_PSR9_PSR916_SHIFT (16u) +#define GPIO_PSR9_PSR917_SHIFT (17u) +#define GPIO_PSR9_PSR918_SHIFT (18u) +#define GPIO_PSR9_PSR919_SHIFT (19u) +#define GPIO_PSR9_PSR920_SHIFT (20u) +#define GPIO_PSR9_PSR921_SHIFT (21u) +#define GPIO_PSR9_PSR922_SHIFT (22u) +#define GPIO_PSR9_PSR923_SHIFT (23u) + +#define GPIO_PPR9_PPR90_SHIFT (0u) +#define GPIO_PPR9_PPR91_SHIFT (1u) +#define GPIO_PPR9_PPR92_SHIFT (2u) +#define GPIO_PPR9_PPR93_SHIFT (3u) +#define GPIO_PPR9_PPR94_SHIFT (4u) +#define GPIO_PPR9_PPR95_SHIFT (5u) +#define GPIO_PPR9_PPR96_SHIFT (6u) +#define GPIO_PPR9_PPR97_SHIFT (7u) + +#define GPIO_PM9_PM90_SHIFT (0u) +#define GPIO_PM9_PM91_SHIFT (1u) +#define GPIO_PM9_PM92_SHIFT (2u) +#define GPIO_PM9_PM93_SHIFT (3u) +#define GPIO_PM9_PM94_SHIFT (4u) +#define GPIO_PM9_PM95_SHIFT (5u) +#define GPIO_PM9_PM96_SHIFT (6u) +#define GPIO_PM9_PM97_SHIFT (7u) + +#define GPIO_PMC9_PMC90_SHIFT (0u) +#define GPIO_PMC9_PMC91_SHIFT (1u) +#define GPIO_PMC9_PMC92_SHIFT (2u) +#define GPIO_PMC9_PMC93_SHIFT (3u) +#define GPIO_PMC9_PMC94_SHIFT (4u) +#define GPIO_PMC9_PMC95_SHIFT (5u) +#define GPIO_PMC9_PMC96_SHIFT (6u) +#define GPIO_PMC9_PMC97_SHIFT (7u) + +#define GPIO_PFC9_PFC90_SHIFT (0u) +#define GPIO_PFC9_PFC91_SHIFT (1u) +#define GPIO_PFC9_PFC92_SHIFT (2u) +#define GPIO_PFC9_PFC93_SHIFT (3u) +#define GPIO_PFC9_PFC94_SHIFT (4u) +#define GPIO_PFC9_PFC95_SHIFT (5u) +#define GPIO_PFC9_PFC96_SHIFT (6u) +#define GPIO_PFC9_PFC97_SHIFT (7u) + +#define GPIO_PFCE9_PFCE90_SHIFT (0u) +#define GPIO_PFCE9_PFCE91_SHIFT (1u) +#define GPIO_PFCE9_PFCE92_SHIFT (2u) +#define GPIO_PFCE9_PFCE93_SHIFT (3u) +#define GPIO_PFCE9_PFCE94_SHIFT (4u) +#define GPIO_PFCE9_PFCE95_SHIFT (5u) +#define GPIO_PFCE9_PFCE96_SHIFT (6u) +#define GPIO_PFCE9_PFCE97_SHIFT (7u) + +#define GPIO_PNOT9_PNOT90_SHIFT (0u) +#define GPIO_PNOT9_PNOT91_SHIFT (1u) +#define GPIO_PNOT9_PNOT92_SHIFT (2u) +#define GPIO_PNOT9_PNOT93_SHIFT (3u) +#define GPIO_PNOT9_PNOT94_SHIFT (4u) +#define GPIO_PNOT9_PNOT95_SHIFT (5u) +#define GPIO_PNOT9_PNOT96_SHIFT (6u) +#define GPIO_PNOT9_PNOT97_SHIFT (7u) + +#define GPIO_PMSR9_PMSR90_SHIFT (0u) +#define GPIO_PMSR9_PMSR91_SHIFT (1u) +#define GPIO_PMSR9_PMSR92_SHIFT (2u) +#define GPIO_PMSR9_PMSR93_SHIFT (3u) +#define GPIO_PMSR9_PMSR94_SHIFT (4u) +#define GPIO_PMSR9_PMSR95_SHIFT (5u) +#define GPIO_PMSR9_PMSR96_SHIFT (6u) +#define GPIO_PMSR9_PMSR97_SHIFT (7u) +#define GPIO_PMSR9_PMSR916_SHIFT (16u) +#define GPIO_PMSR9_PMSR917_SHIFT (17u) +#define GPIO_PMSR9_PMSR918_SHIFT (18u) +#define GPIO_PMSR9_PMSR919_SHIFT (19u) +#define GPIO_PMSR9_PMSR920_SHIFT (20u) +#define GPIO_PMSR9_PMSR921_SHIFT (21u) +#define GPIO_PMSR9_PMSR922_SHIFT (22u) +#define GPIO_PMSR9_PMSR923_SHIFT (23u) + +#define GPIO_PMCSR9_PMCSR90_SHIFT (0u) +#define GPIO_PMCSR9_PMCSR91_SHIFT (1u) +#define GPIO_PMCSR9_PMCSR92_SHIFT (2u) +#define GPIO_PMCSR9_PMCSR93_SHIFT (3u) +#define GPIO_PMCSR9_PMCSR94_SHIFT (4u) +#define GPIO_PMCSR9_PMCSR95_SHIFT (5u) +#define GPIO_PMCSR9_PMCSR96_SHIFT (6u) +#define GPIO_PMCSR9_PMCSR97_SHIFT (7u) +#define GPIO_PMCSR9_PMCSR916_SHIFT (16u) +#define GPIO_PMCSR9_PMCSR917_SHIFT (17u) +#define GPIO_PMCSR9_PMCSR918_SHIFT (18u) +#define GPIO_PMCSR9_PMCSR919_SHIFT (19u) +#define GPIO_PMCSR9_PMCSR920_SHIFT (20u) +#define GPIO_PMCSR9_PMCSR921_SHIFT (21u) +#define GPIO_PMCSR9_PMCSR922_SHIFT (22u) +#define GPIO_PMCSR9_PMCSR923_SHIFT (23u) + +#define GPIO_PFCAE9_PFCAE90_SHIFT (0u) +#define GPIO_PFCAE9_PFCAE91_SHIFT (1u) +#define GPIO_PFCAE9_PFCAE92_SHIFT (2u) +#define GPIO_PFCAE9_PFCAE93_SHIFT (3u) +#define GPIO_PFCAE9_PFCAE94_SHIFT (4u) +#define GPIO_PFCAE9_PFCAE95_SHIFT (5u) +#define GPIO_PFCAE9_PFCAE96_SHIFT (6u) +#define GPIO_PFCAE9_PFCAE97_SHIFT (7u) + +#define GPIO_PIBC9_PIBC90_SHIFT (0u) +#define GPIO_PIBC9_PIBC91_SHIFT (1u) +#define GPIO_PIBC9_PIBC92_SHIFT (2u) +#define GPIO_PIBC9_PIBC93_SHIFT (3u) +#define GPIO_PIBC9_PIBC94_SHIFT (4u) +#define GPIO_PIBC9_PIBC95_SHIFT (5u) +#define GPIO_PIBC9_PIBC96_SHIFT (6u) +#define GPIO_PIBC9_PIBC97_SHIFT (7u) + +#define GPIO_PBDC9_PBDC90_SHIFT (0u) +#define GPIO_PBDC9_PBDC91_SHIFT (1u) +#define GPIO_PBDC9_PBDC92_SHIFT (2u) +#define GPIO_PBDC9_PBDC93_SHIFT (3u) +#define GPIO_PBDC9_PBDC94_SHIFT (4u) +#define GPIO_PBDC9_PBDC95_SHIFT (5u) +#define GPIO_PBDC9_PBDC96_SHIFT (6u) +#define GPIO_PBDC9_PBDC97_SHIFT (7u) + +#define GPIO_PIPC9_PIPC90_SHIFT (0u) +#define GPIO_PIPC9_PIPC91_SHIFT (1u) +#define GPIO_PIPC9_PIPC92_SHIFT (2u) +#define GPIO_PIPC9_PIPC93_SHIFT (3u) +#define GPIO_PIPC9_PIPC94_SHIFT (4u) +#define GPIO_PIPC9_PIPC95_SHIFT (5u) +#define GPIO_PIPC9_PIPC96_SHIFT (6u) +#define GPIO_PIPC9_PIPC97_SHIFT (7u) + +/* ---- P10 ---- */ +#define GPIO_P10_P100_SHIFT (0u) +#define GPIO_P10_P101_SHIFT (1u) +#define GPIO_P10_P102_SHIFT (2u) +#define GPIO_P10_P103_SHIFT (3u) +#define GPIO_P10_P104_SHIFT (4u) +#define GPIO_P10_P105_SHIFT (5u) +#define GPIO_P10_P106_SHIFT (6u) +#define GPIO_P10_P107_SHIFT (7u) +#define GPIO_P10_P108_SHIFT (8u) +#define GPIO_P10_P109_SHIFT (9u) +#define GPIO_P10_P1010_SHIFT (10u) +#define GPIO_P10_P1011_SHIFT (11u) +#define GPIO_P10_P1012_SHIFT (12u) +#define GPIO_P10_P1013_SHIFT (13u) +#define GPIO_P10_P1014_SHIFT (14u) +#define GPIO_P10_P1015_SHIFT (15u) + +#define GPIO_PSR10_PSR100_SHIFT (0u) +#define GPIO_PSR10_PSR101_SHIFT (1u) +#define GPIO_PSR10_PSR102_SHIFT (2u) +#define GPIO_PSR10_PSR103_SHIFT (3u) +#define GPIO_PSR10_PSR104_SHIFT (4u) +#define GPIO_PSR10_PSR105_SHIFT (5u) +#define GPIO_PSR10_PSR106_SHIFT (6u) +#define GPIO_PSR10_PSR107_SHIFT (7u) +#define GPIO_PSR10_PSR108_SHIFT (8u) +#define GPIO_PSR10_PSR109_SHIFT (9u) +#define GPIO_PSR10_PSR1010_SHIFT (10u) +#define GPIO_PSR10_PSR1011_SHIFT (11u) +#define GPIO_PSR10_PSR1012_SHIFT (12u) +#define GPIO_PSR10_PSR1013_SHIFT (13u) +#define GPIO_PSR10_PSR1014_SHIFT (14u) +#define GPIO_PSR10_PSR1015_SHIFT (15u) +#define GPIO_PSR10_PSR1016_SHIFT (16u) +#define GPIO_PSR10_PSR1017_SHIFT (17u) +#define GPIO_PSR10_PSR1018_SHIFT (18u) +#define GPIO_PSR10_PSR1019_SHIFT (19u) +#define GPIO_PSR10_PSR1020_SHIFT (20u) +#define GPIO_PSR10_PSR1021_SHIFT (21u) +#define GPIO_PSR10_PSR1022_SHIFT (22u) +#define GPIO_PSR10_PSR1023_SHIFT (23u) +#define GPIO_PSR10_PSR1024_SHIFT (24u) +#define GPIO_PSR10_PSR1025_SHIFT (25u) +#define GPIO_PSR10_PSR1026_SHIFT (26u) +#define GPIO_PSR10_PSR1027_SHIFT (27u) +#define GPIO_PSR10_PSR1028_SHIFT (28u) +#define GPIO_PSR10_PSR1029_SHIFT (29u) +#define GPIO_PSR10_PSR1030_SHIFT (30u) +#define GPIO_PSR10_PSR1031_SHIFT (31u) + +#define GPIO_PPR10_PPR100_SHIFT (0u) +#define GPIO_PPR10_PPR101_SHIFT (1u) +#define GPIO_PPR10_PPR102_SHIFT (2u) +#define GPIO_PPR10_PPR103_SHIFT (3u) +#define GPIO_PPR10_PPR104_SHIFT (4u) +#define GPIO_PPR10_PPR105_SHIFT (5u) +#define GPIO_PPR10_PPR106_SHIFT (6u) +#define GPIO_PPR10_PPR107_SHIFT (7u) +#define GPIO_PPR10_PPR108_SHIFT (8u) +#define GPIO_PPR10_PPR109_SHIFT (9u) +#define GPIO_PPR10_PPR1010_SHIFT (10u) +#define GPIO_PPR10_PPR1011_SHIFT (11u) +#define GPIO_PPR10_PPR1012_SHIFT (12u) +#define GPIO_PPR10_PPR1013_SHIFT (13u) +#define GPIO_PPR10_PPR1014_SHIFT (14u) +#define GPIO_PPR10_PPR1015_SHIFT (15u) + +#define GPIO_PM10_PM100_SHIFT (0u) +#define GPIO_PM10_PM101_SHIFT (1u) +#define GPIO_PM10_PM102_SHIFT (2u) +#define GPIO_PM10_PM103_SHIFT (3u) +#define GPIO_PM10_PM104_SHIFT (4u) +#define GPIO_PM10_PM105_SHIFT (5u) +#define GPIO_PM10_PM106_SHIFT (6u) +#define GPIO_PM10_PM107_SHIFT (7u) +#define GPIO_PM10_PM108_SHIFT (8u) +#define GPIO_PM10_PM109_SHIFT (9u) +#define GPIO_PM10_PM1010_SHIFT (10u) +#define GPIO_PM10_PM1011_SHIFT (11u) +#define GPIO_PM10_PM1012_SHIFT (12u) +#define GPIO_PM10_PM1013_SHIFT (13u) +#define GPIO_PM10_PM1014_SHIFT (14u) +#define GPIO_PM10_PM1015_SHIFT (15u) + +#define GPIO_PMC10_PMC100_SHIFT (0u) +#define GPIO_PMC10_PMC101_SHIFT (1u) +#define GPIO_PMC10_PMC102_SHIFT (2u) +#define GPIO_PMC10_PMC103_SHIFT (3u) +#define GPIO_PMC10_PMC104_SHIFT (4u) +#define GPIO_PMC10_PMC105_SHIFT (5u) +#define GPIO_PMC10_PMC106_SHIFT (6u) +#define GPIO_PMC10_PMC107_SHIFT (7u) +#define GPIO_PMC10_PMC108_SHIFT (8u) +#define GPIO_PMC10_PMC109_SHIFT (9u) +#define GPIO_PMC10_PMC1010_SHIFT (10u) +#define GPIO_PMC10_PMC1011_SHIFT (11u) +#define GPIO_PMC10_PMC1012_SHIFT (12u) +#define GPIO_PMC10_PMC1013_SHIFT (13u) +#define GPIO_PMC10_PMC1014_SHIFT (14u) +#define GPIO_PMC10_PMC1015_SHIFT (15u) + +#define GPIO_PFC10_PFC100_SHIFT (0u) +#define GPIO_PFC10_PFC101_SHIFT (1u) +#define GPIO_PFC10_PFC102_SHIFT (2u) +#define GPIO_PFC10_PFC103_SHIFT (3u) +#define GPIO_PFC10_PFC104_SHIFT (4u) +#define GPIO_PFC10_PFC105_SHIFT (5u) +#define GPIO_PFC10_PFC106_SHIFT (6u) +#define GPIO_PFC10_PFC107_SHIFT (7u) +#define GPIO_PFC10_PFC108_SHIFT (8u) +#define GPIO_PFC10_PFC109_SHIFT (9u) +#define GPIO_PFC10_PFC1010_SHIFT (10u) +#define GPIO_PFC10_PFC1011_SHIFT (11u) +#define GPIO_PFC10_PFC1012_SHIFT (12u) +#define GPIO_PFC10_PFC1013_SHIFT (13u) +#define GPIO_PFC10_PFC1014_SHIFT (14u) +#define GPIO_PFC10_PFC1015_SHIFT (15u) + +#define GPIO_PFCE10_PFCE100_SHIFT (0u) +#define GPIO_PFCE10_PFCE101_SHIFT (1u) +#define GPIO_PFCE10_PFCE102_SHIFT (2u) +#define GPIO_PFCE10_PFCE103_SHIFT (3u) +#define GPIO_PFCE10_PFCE104_SHIFT (4u) +#define GPIO_PFCE10_PFCE105_SHIFT (5u) +#define GPIO_PFCE10_PFCE106_SHIFT (6u) +#define GPIO_PFCE10_PFCE107_SHIFT (7u) +#define GPIO_PFCE10_PFCE108_SHIFT (8u) +#define GPIO_PFCE10_PFCE109_SHIFT (9u) +#define GPIO_PFCE10_PFCE1010_SHIFT (10u) +#define GPIO_PFCE10_PFCE1011_SHIFT (11u) +#define GPIO_PFCE10_PFCE1012_SHIFT (12u) +#define GPIO_PFCE10_PFCE1013_SHIFT (13u) +#define GPIO_PFCE10_PFCE1014_SHIFT (14u) +#define GPIO_PFCE10_PFCE1015_SHIFT (15u) + +#define GPIO_PNOT10_PNOT100_SHIFT (0u) +#define GPIO_PNOT10_PNOT101_SHIFT (1u) +#define GPIO_PNOT10_PNOT102_SHIFT (2u) +#define GPIO_PNOT10_PNOT103_SHIFT (3u) +#define GPIO_PNOT10_PNOT104_SHIFT (4u) +#define GPIO_PNOT10_PNOT105_SHIFT (5u) +#define GPIO_PNOT10_PNOT106_SHIFT (6u) +#define GPIO_PNOT10_PNOT107_SHIFT (7u) +#define GPIO_PNOT10_PNOT108_SHIFT (8u) +#define GPIO_PNOT10_PNOT109_SHIFT (9u) +#define GPIO_PNOT10_PNOT1010_SHIFT (10u) +#define GPIO_PNOT10_PNOT1011_SHIFT (11u) +#define GPIO_PNOT10_PNOT1012_SHIFT (12u) +#define GPIO_PNOT10_PNOT1013_SHIFT (13u) +#define GPIO_PNOT10_PNOT1014_SHIFT (14u) +#define GPIO_PNOT10_PNOT1015_SHIFT (15u) + +#define GPIO_PMSR10_PMSR100_SHIFT (0u) +#define GPIO_PMSR10_PMSR101_SHIFT (1u) +#define GPIO_PMSR10_PMSR102_SHIFT (2u) +#define GPIO_PMSR10_PMSR103_SHIFT (3u) +#define GPIO_PMSR10_PMSR104_SHIFT (4u) +#define GPIO_PMSR10_PMSR105_SHIFT (5u) +#define GPIO_PMSR10_PMSR106_SHIFT (6u) +#define GPIO_PMSR10_PMSR107_SHIFT (7u) +#define GPIO_PMSR10_PMSR108_SHIFT (8u) +#define GPIO_PMSR10_PMSR109_SHIFT (9u) +#define GPIO_PMSR10_PMSR1010_SHIFT (10u) +#define GPIO_PMSR10_PMSR1011_SHIFT (11u) +#define GPIO_PMSR10_PMSR1012_SHIFT (12u) +#define GPIO_PMSR10_PMSR1013_SHIFT (13u) +#define GPIO_PMSR10_PMSR1014_SHIFT (14u) +#define GPIO_PMSR10_PMSR1015_SHIFT (15u) +#define GPIO_PMSR10_PMSR1016_SHIFT (16u) +#define GPIO_PMSR10_PMSR1017_SHIFT (17u) +#define GPIO_PMSR10_PMSR1018_SHIFT (18u) +#define GPIO_PMSR10_PMSR1019_SHIFT (19u) +#define GPIO_PMSR10_PMSR1020_SHIFT (20u) +#define GPIO_PMSR10_PMSR1021_SHIFT (21u) +#define GPIO_PMSR10_PMSR1022_SHIFT (22u) +#define GPIO_PMSR10_PMSR1023_SHIFT (23u) +#define GPIO_PMSR10_PMSR1024_SHIFT (24u) +#define GPIO_PMSR10_PMSR1025_SHIFT (25u) +#define GPIO_PMSR10_PMSR1026_SHIFT (26u) +#define GPIO_PMSR10_PMSR1027_SHIFT (27u) +#define GPIO_PMSR10_PMSR1028_SHIFT (28u) +#define GPIO_PMSR10_PMSR1029_SHIFT (29u) +#define GPIO_PMSR10_PMSR1030_SHIFT (30u) +#define GPIO_PMSR10_PMSR1031_SHIFT (31u) + +#define GPIO_PMCSR10_PMCSR100_SHIFT (0u) +#define GPIO_PMCSR10_PMCSR101_SHIFT (1u) +#define GPIO_PMCSR10_PMCSR102_SHIFT (2u) +#define GPIO_PMCSR10_PMCSR103_SHIFT (3u) +#define GPIO_PMCSR10_PMCSR104_SHIFT (4u) +#define GPIO_PMCSR10_PMCSR105_SHIFT (5u) +#define GPIO_PMCSR10_PMCSR106_SHIFT (6u) +#define GPIO_PMCSR10_PMCSR107_SHIFT (7u) +#define GPIO_PMCSR10_PMCSR108_SHIFT (8u) +#define GPIO_PMCSR10_PMCSR109_SHIFT (9u) +#define GPIO_PMCSR10_PMCSR1010_SHIFT (10u) +#define GPIO_PMCSR10_PMCSR1011_SHIFT (11u) +#define GPIO_PMCSR10_PMCSR1012_SHIFT (12u) +#define GPIO_PMCSR10_PMCSR1013_SHIFT (13u) +#define GPIO_PMCSR10_PMCSR1014_SHIFT (14u) +#define GPIO_PMCSR10_PMCSR1015_SHIFT (15u) +#define GPIO_PMCSR10_PMCSR1016_SHIFT (16u) +#define GPIO_PMCSR10_PMCSR1017_SHIFT (17u) +#define GPIO_PMCSR10_PMCSR1018_SHIFT (18u) +#define GPIO_PMCSR10_PMCSR1019_SHIFT (19u) +#define GPIO_PMCSR10_PMCSR1020_SHIFT (20u) +#define GPIO_PMCSR10_PMCSR1021_SHIFT (21u) +#define GPIO_PMCSR10_PMCSR1022_SHIFT (22u) +#define GPIO_PMCSR10_PMCSR1023_SHIFT (23u) +#define GPIO_PMCSR10_PMCSR1024_SHIFT (24u) +#define GPIO_PMCSR10_PMCSR1025_SHIFT (25u) +#define GPIO_PMCSR10_PMCSR1026_SHIFT (26u) +#define GPIO_PMCSR10_PMCSR1027_SHIFT (27u) +#define GPIO_PMCSR10_PMCSR1028_SHIFT (28u) +#define GPIO_PMCSR10_PMCSR1029_SHIFT (29u) +#define GPIO_PMCSR10_PMCSR1030_SHIFT (30u) +#define GPIO_PMCSR10_PMCSR1031_SHIFT (31u) + +#define GPIO_PFCAE10_PFCAE100_SHIFT (0u) +#define GPIO_PFCAE10_PFCAE101_SHIFT (1u) +#define GPIO_PFCAE10_PFCAE102_SHIFT (2u) +#define GPIO_PFCAE10_PFCAE103_SHIFT (3u) +#define GPIO_PFCAE10_PFCAE104_SHIFT (4u) +#define GPIO_PFCAE10_PFCAE105_SHIFT (5u) +#define GPIO_PFCAE10_PFCAE106_SHIFT (6u) +#define GPIO_PFCAE10_PFCAE107_SHIFT (7u) +#define GPIO_PFCAE10_PFCAE108_SHIFT (8u) +#define GPIO_PFCAE10_PFCAE109_SHIFT (9u) +#define GPIO_PFCAE10_PFCAE1010_SHIFT (10u) +#define GPIO_PFCAE10_PFCAE1011_SHIFT (11u) +#define GPIO_PFCAE10_PFCAE1012_SHIFT (12u) +#define GPIO_PFCAE10_PFCAE1013_SHIFT (13u) +#define GPIO_PFCAE10_PFCAE1014_SHIFT (14u) +#define GPIO_PFCAE10_PFCAE1015_SHIFT (15u) + +#define GPIO_PIBC10_PIBC100_SHIFT (0u) +#define GPIO_PIBC10_PIBC101_SHIFT (1u) +#define GPIO_PIBC10_PIBC102_SHIFT (2u) +#define GPIO_PIBC10_PIBC103_SHIFT (3u) +#define GPIO_PIBC10_PIBC104_SHIFT (4u) +#define GPIO_PIBC10_PIBC105_SHIFT (5u) +#define GPIO_PIBC10_PIBC106_SHIFT (6u) +#define GPIO_PIBC10_PIBC107_SHIFT (7u) +#define GPIO_PIBC10_PIBC108_SHIFT (8u) +#define GPIO_PIBC10_PIBC109_SHIFT (9u) +#define GPIO_PIBC10_PIBC1010_SHIFT (10u) +#define GPIO_PIBC10_PIBC1011_SHIFT (11u) +#define GPIO_PIBC10_PIBC1012_SHIFT (12u) +#define GPIO_PIBC10_PIBC1013_SHIFT (13u) +#define GPIO_PIBC10_PIBC1014_SHIFT (14u) +#define GPIO_PIBC10_PIBC1015_SHIFT (15u) + +#define GPIO_PBDC10_PBDC100_SHIFT (0u) +#define GPIO_PBDC10_PBDC101_SHIFT (1u) +#define GPIO_PBDC10_PBDC102_SHIFT (2u) +#define GPIO_PBDC10_PBDC103_SHIFT (3u) +#define GPIO_PBDC10_PBDC104_SHIFT (4u) +#define GPIO_PBDC10_PBDC105_SHIFT (5u) +#define GPIO_PBDC10_PBDC106_SHIFT (6u) +#define GPIO_PBDC10_PBDC107_SHIFT (7u) +#define GPIO_PBDC10_PBDC108_SHIFT (8u) +#define GPIO_PBDC10_PBDC109_SHIFT (9u) +#define GPIO_PBDC10_PBDC1010_SHIFT (10u) +#define GPIO_PBDC10_PBDC1011_SHIFT (11u) +#define GPIO_PBDC10_PBDC1012_SHIFT (12u) +#define GPIO_PBDC10_PBDC1013_SHIFT (13u) +#define GPIO_PBDC10_PBDC1014_SHIFT (14u) +#define GPIO_PBDC10_PBDC1015_SHIFT (15u) + +#define GPIO_PIPC10_PIPC100_SHIFT (0u) +#define GPIO_PIPC10_PIPC101_SHIFT (1u) +#define GPIO_PIPC10_PIPC102_SHIFT (2u) +#define GPIO_PIPC10_PIPC103_SHIFT (3u) +#define GPIO_PIPC10_PIPC104_SHIFT (4u) +#define GPIO_PIPC10_PIPC105_SHIFT (5u) +#define GPIO_PIPC10_PIPC106_SHIFT (6u) +#define GPIO_PIPC10_PIPC107_SHIFT (7u) +#define GPIO_PIPC10_PIPC108_SHIFT (8u) +#define GPIO_PIPC10_PIPC109_SHIFT (9u) +#define GPIO_PIPC10_PIPC1010_SHIFT (10u) +#define GPIO_PIPC10_PIPC1011_SHIFT (11u) +#define GPIO_PIPC10_PIPC1012_SHIFT (12u) +#define GPIO_PIPC10_PIPC1013_SHIFT (13u) +#define GPIO_PIPC10_PIPC1014_SHIFT (14u) +#define GPIO_PIPC10_PIPC1015_SHIFT (15u) + +/* ---- P11 ---- */ +#define GPIO_P11_P110_SHIFT (0u) +#define GPIO_P11_P111_SHIFT (1u) +#define GPIO_P11_P112_SHIFT (2u) +#define GPIO_P11_P113_SHIFT (3u) +#define GPIO_P11_P114_SHIFT (4u) +#define GPIO_P11_P115_SHIFT (5u) +#define GPIO_P11_P116_SHIFT (6u) +#define GPIO_P11_P117_SHIFT (7u) +#define GPIO_P11_P118_SHIFT (8u) +#define GPIO_P11_P119_SHIFT (9u) +#define GPIO_P11_P1110_SHIFT (10u) +#define GPIO_P11_P1111_SHIFT (11u) +#define GPIO_P11_P1112_SHIFT (12u) +#define GPIO_P11_P1113_SHIFT (13u) +#define GPIO_P11_P1114_SHIFT (14u) +#define GPIO_P11_P1115_SHIFT (15u) + +#define GPIO_PSR11_PSR110_SHIFT (0u) +#define GPIO_PSR11_PSR111_SHIFT (1u) +#define GPIO_PSR11_PSR112_SHIFT (2u) +#define GPIO_PSR11_PSR113_SHIFT (3u) +#define GPIO_PSR11_PSR114_SHIFT (4u) +#define GPIO_PSR11_PSR115_SHIFT (5u) +#define GPIO_PSR11_PSR116_SHIFT (6u) +#define GPIO_PSR11_PSR117_SHIFT (7u) +#define GPIO_PSR11_PSR118_SHIFT (8u) +#define GPIO_PSR11_PSR119_SHIFT (9u) +#define GPIO_PSR11_PSR1110_SHIFT (10u) +#define GPIO_PSR11_PSR1111_SHIFT (11u) +#define GPIO_PSR11_PSR1112_SHIFT (12u) +#define GPIO_PSR11_PSR1113_SHIFT (13u) +#define GPIO_PSR11_PSR1114_SHIFT (14u) +#define GPIO_PSR11_PSR1115_SHIFT (15u) +#define GPIO_PSR11_PSR1116_SHIFT (16u) +#define GPIO_PSR11_PSR1117_SHIFT (17u) +#define GPIO_PSR11_PSR1118_SHIFT (18u) +#define GPIO_PSR11_PSR1119_SHIFT (19u) +#define GPIO_PSR11_PSR1120_SHIFT (20u) +#define GPIO_PSR11_PSR1121_SHIFT (21u) +#define GPIO_PSR11_PSR1122_SHIFT (22u) +#define GPIO_PSR11_PSR1123_SHIFT (23u) +#define GPIO_PSR11_PSR1124_SHIFT (24u) +#define GPIO_PSR11_PSR1125_SHIFT (25u) +#define GPIO_PSR11_PSR1126_SHIFT (26u) +#define GPIO_PSR11_PSR1127_SHIFT (27u) +#define GPIO_PSR11_PSR1128_SHIFT (28u) +#define GPIO_PSR11_PSR1129_SHIFT (29u) +#define GPIO_PSR11_PSR1130_SHIFT (30u) +#define GPIO_PSR11_PSR1131_SHIFT (31u) + +#define GPIO_PPR11_PPR110_SHIFT (0u) +#define GPIO_PPR11_PPR111_SHIFT (1u) +#define GPIO_PPR11_PPR112_SHIFT (2u) +#define GPIO_PPR11_PPR113_SHIFT (3u) +#define GPIO_PPR11_PPR114_SHIFT (4u) +#define GPIO_PPR11_PPR115_SHIFT (5u) +#define GPIO_PPR11_PPR116_SHIFT (6u) +#define GPIO_PPR11_PPR117_SHIFT (7u) +#define GPIO_PPR11_PPR118_SHIFT (8u) +#define GPIO_PPR11_PPR119_SHIFT (9u) +#define GPIO_PPR11_PPR1110_SHIFT (10u) +#define GPIO_PPR11_PPR1111_SHIFT (11u) +#define GPIO_PPR11_PPR1112_SHIFT (12u) +#define GPIO_PPR11_PPR1113_SHIFT (13u) +#define GPIO_PPR11_PPR1114_SHIFT (14u) +#define GPIO_PPR11_PPR1115_SHIFT (15u) + +#define GPIO_PM11_PM110_SHIFT (0u) +#define GPIO_PM11_PM111_SHIFT (1u) +#define GPIO_PM11_PM112_SHIFT (2u) +#define GPIO_PM11_PM113_SHIFT (3u) +#define GPIO_PM11_PM114_SHIFT (4u) +#define GPIO_PM11_PM115_SHIFT (5u) +#define GPIO_PM11_PM116_SHIFT (6u) +#define GPIO_PM11_PM117_SHIFT (7u) +#define GPIO_PM11_PM118_SHIFT (8u) +#define GPIO_PM11_PM119_SHIFT (9u) +#define GPIO_PM11_PM1110_SHIFT (10u) +#define GPIO_PM11_PM1111_SHIFT (11u) +#define GPIO_PM11_PM1112_SHIFT (12u) +#define GPIO_PM11_PM1113_SHIFT (13u) +#define GPIO_PM11_PM1114_SHIFT (14u) +#define GPIO_PM11_PM1115_SHIFT (15u) + +#define GPIO_PMC11_PMC110_SHIFT (0u) +#define GPIO_PMC11_PMC111_SHIFT (1u) +#define GPIO_PMC11_PMC112_SHIFT (2u) +#define GPIO_PMC11_PMC113_SHIFT (3u) +#define GPIO_PMC11_PMC114_SHIFT (4u) +#define GPIO_PMC11_PMC115_SHIFT (5u) +#define GPIO_PMC11_PMC116_SHIFT (6u) +#define GPIO_PMC11_PMC117_SHIFT (7u) +#define GPIO_PMC11_PMC118_SHIFT (8u) +#define GPIO_PMC11_PMC119_SHIFT (9u) +#define GPIO_PMC11_PMC1110_SHIFT (10u) +#define GPIO_PMC11_PMC1111_SHIFT (11u) +#define GPIO_PMC11_PMC1112_SHIFT (12u) +#define GPIO_PMC11_PMC1113_SHIFT (13u) +#define GPIO_PMC11_PMC1114_SHIFT (14u) +#define GPIO_PMC11_PMC1115_SHIFT (15u) + +#define GPIO_PFC11_PFC110_SHIFT (0u) +#define GPIO_PFC11_PFC111_SHIFT (1u) +#define GPIO_PFC11_PFC112_SHIFT (2u) +#define GPIO_PFC11_PFC113_SHIFT (3u) +#define GPIO_PFC11_PFC114_SHIFT (4u) +#define GPIO_PFC11_PFC115_SHIFT (5u) +#define GPIO_PFC11_PFC116_SHIFT (6u) +#define GPIO_PFC11_PFC117_SHIFT (7u) +#define GPIO_PFC11_PFC118_SHIFT (8u) +#define GPIO_PFC11_PFC119_SHIFT (9u) +#define GPIO_PFC11_PFC1110_SHIFT (10u) +#define GPIO_PFC11_PFC1111_SHIFT (11u) +#define GPIO_PFC11_PFC1112_SHIFT (12u) +#define GPIO_PFC11_PFC1113_SHIFT (13u) +#define GPIO_PFC11_PFC1114_SHIFT (14u) +#define GPIO_PFC11_PFC1115_SHIFT (15u) + +#define GPIO_PFCE11_PFCE110_SHIFT (0u) +#define GPIO_PFCE11_PFCE111_SHIFT (1u) +#define GPIO_PFCE11_PFCE112_SHIFT (2u) +#define GPIO_PFCE11_PFCE113_SHIFT (3u) +#define GPIO_PFCE11_PFCE114_SHIFT (4u) +#define GPIO_PFCE11_PFCE115_SHIFT (5u) +#define GPIO_PFCE11_PFCE116_SHIFT (6u) +#define GPIO_PFCE11_PFCE117_SHIFT (7u) +#define GPIO_PFCE11_PFCE118_SHIFT (8u) +#define GPIO_PFCE11_PFCE119_SHIFT (9u) +#define GPIO_PFCE11_PFCE1110_SHIFT (10u) +#define GPIO_PFCE11_PFCE1111_SHIFT (11u) +#define GPIO_PFCE11_PFCE1112_SHIFT (12u) +#define GPIO_PFCE11_PFCE1113_SHIFT (13u) +#define GPIO_PFCE11_PFCE1114_SHIFT (14u) +#define GPIO_PFCE11_PFCE1115_SHIFT (15u) + +#define GPIO_PNOT11_PNOT110_SHIFT (0u) +#define GPIO_PNOT11_PNOT111_SHIFT (1u) +#define GPIO_PNOT11_PNOT112_SHIFT (2u) +#define GPIO_PNOT11_PNOT113_SHIFT (3u) +#define GPIO_PNOT11_PNOT114_SHIFT (4u) +#define GPIO_PNOT11_PNOT115_SHIFT (5u) +#define GPIO_PNOT11_PNOT116_SHIFT (6u) +#define GPIO_PNOT11_PNOT117_SHIFT (7u) +#define GPIO_PNOT11_PNOT118_SHIFT (8u) +#define GPIO_PNOT11_PNOT119_SHIFT (9u) +#define GPIO_PNOT11_PNOT1110_SHIFT (10u) +#define GPIO_PNOT11_PNOT1111_SHIFT (11u) +#define GPIO_PNOT11_PNOT1112_SHIFT (12u) +#define GPIO_PNOT11_PNOT1113_SHIFT (13u) +#define GPIO_PNOT11_PNOT1114_SHIFT (14u) +#define GPIO_PNOT11_PNOT1115_SHIFT (15u) + +#define GPIO_PMSR11_PMSR110_SHIFT (0u) +#define GPIO_PMSR11_PMSR111_SHIFT (1u) +#define GPIO_PMSR11_PMSR112_SHIFT (2u) +#define GPIO_PMSR11_PMSR113_SHIFT (3u) +#define GPIO_PMSR11_PMSR114_SHIFT (4u) +#define GPIO_PMSR11_PMSR115_SHIFT (5u) +#define GPIO_PMSR11_PMSR116_SHIFT (6u) +#define GPIO_PMSR11_PMSR117_SHIFT (7u) +#define GPIO_PMSR11_PMSR118_SHIFT (8u) +#define GPIO_PMSR11_PMSR119_SHIFT (9u) +#define GPIO_PMSR11_PMSR1110_SHIFT (10u) +#define GPIO_PMSR11_PMSR1111_SHIFT (11u) +#define GPIO_PMSR11_PMSR1112_SHIFT (12u) +#define GPIO_PMSR11_PMSR1113_SHIFT (13u) +#define GPIO_PMSR11_PMSR1114_SHIFT (14u) +#define GPIO_PMSR11_PMSR1115_SHIFT (15u) +#define GPIO_PMSR11_PMSR1116_SHIFT (16u) +#define GPIO_PMSR11_PMSR1117_SHIFT (17u) +#define GPIO_PMSR11_PMSR1118_SHIFT (18u) +#define GPIO_PMSR11_PMSR1119_SHIFT (19u) +#define GPIO_PMSR11_PMSR1120_SHIFT (20u) +#define GPIO_PMSR11_PMSR1121_SHIFT (21u) +#define GPIO_PMSR11_PMSR1122_SHIFT (22u) +#define GPIO_PMSR11_PMSR1123_SHIFT (23u) +#define GPIO_PMSR11_PMSR1124_SHIFT (24u) +#define GPIO_PMSR11_PMSR1125_SHIFT (25u) +#define GPIO_PMSR11_PMSR1126_SHIFT (26u) +#define GPIO_PMSR11_PMSR1127_SHIFT (27u) +#define GPIO_PMSR11_PMSR1128_SHIFT (28u) +#define GPIO_PMSR11_PMSR1129_SHIFT (29u) +#define GPIO_PMSR11_PMSR1130_SHIFT (30u) +#define GPIO_PMSR11_PMSR1131_SHIFT (31u) + +#define GPIO_PMCSR11_PMCSR110_SHIFT (0u) +#define GPIO_PMCSR11_PMCSR111_SHIFT (1u) +#define GPIO_PMCSR11_PMCSR112_SHIFT (2u) +#define GPIO_PMCSR11_PMCSR113_SHIFT (3u) +#define GPIO_PMCSR11_PMCSR114_SHIFT (4u) +#define GPIO_PMCSR11_PMCSR115_SHIFT (5u) +#define GPIO_PMCSR11_PMCSR116_SHIFT (6u) +#define GPIO_PMCSR11_PMCSR117_SHIFT (7u) +#define GPIO_PMCSR11_PMCSR118_SHIFT (8u) +#define GPIO_PMCSR11_PMCSR119_SHIFT (9u) +#define GPIO_PMCSR11_PMCSR1110_SHIFT (10u) +#define GPIO_PMCSR11_PMCSR1111_SHIFT (11u) +#define GPIO_PMCSR11_PMCSR1112_SHIFT (12u) +#define GPIO_PMCSR11_PMCSR1113_SHIFT (13u) +#define GPIO_PMCSR11_PMCSR1114_SHIFT (14u) +#define GPIO_PMCSR11_PMCSR1115_SHIFT (15u) +#define GPIO_PMCSR11_PMCSR1116_SHIFT (16u) +#define GPIO_PMCSR11_PMCSR1117_SHIFT (17u) +#define GPIO_PMCSR11_PMCSR1118_SHIFT (18u) +#define GPIO_PMCSR11_PMCSR1119_SHIFT (19u) +#define GPIO_PMCSR11_PMCSR1120_SHIFT (20u) +#define GPIO_PMCSR11_PMCSR1121_SHIFT (21u) +#define GPIO_PMCSR11_PMCSR1122_SHIFT (22u) +#define GPIO_PMCSR11_PMCSR1123_SHIFT (23u) +#define GPIO_PMCSR11_PMCSR1124_SHIFT (24u) +#define GPIO_PMCSR11_PMCSR1125_SHIFT (25u) +#define GPIO_PMCSR11_PMCSR1126_SHIFT (26u) +#define GPIO_PMCSR11_PMCSR1127_SHIFT (27u) +#define GPIO_PMCSR11_PMCSR1128_SHIFT (28u) +#define GPIO_PMCSR11_PMCSR1129_SHIFT (29u) +#define GPIO_PMCSR11_PMCSR1130_SHIFT (30u) +#define GPIO_PMCSR11_PMCSR1131_SHIFT (31u) + +#define GPIO_PFCAE11_PFCAE110_SHIFT (0u) +#define GPIO_PFCAE11_PFCAE111_SHIFT (1u) +#define GPIO_PFCAE11_PFCAE112_SHIFT (2u) +#define GPIO_PFCAE11_PFCAE113_SHIFT (3u) +#define GPIO_PFCAE11_PFCAE114_SHIFT (4u) +#define GPIO_PFCAE11_PFCAE115_SHIFT (5u) +#define GPIO_PFCAE11_PFCAE116_SHIFT (6u) +#define GPIO_PFCAE11_PFCAE117_SHIFT (7u) +#define GPIO_PFCAE11_PFCAE118_SHIFT (8u) +#define GPIO_PFCAE11_PFCAE119_SHIFT (9u) +#define GPIO_PFCAE11_PFCAE1110_SHIFT (10u) +#define GPIO_PFCAE11_PFCAE1111_SHIFT (11u) +#define GPIO_PFCAE11_PFCAE1112_SHIFT (12u) +#define GPIO_PFCAE11_PFCAE1113_SHIFT (13u) +#define GPIO_PFCAE11_PFCAE1114_SHIFT (14u) +#define GPIO_PFCAE11_PFCAE1115_SHIFT (15u) + +#define GPIO_PIBC11_PIBC110_SHIFT (0u) +#define GPIO_PIBC11_PIBC111_SHIFT (1u) +#define GPIO_PIBC11_PIBC112_SHIFT (2u) +#define GPIO_PIBC11_PIBC113_SHIFT (3u) +#define GPIO_PIBC11_PIBC114_SHIFT (4u) +#define GPIO_PIBC11_PIBC115_SHIFT (5u) +#define GPIO_PIBC11_PIBC116_SHIFT (6u) +#define GPIO_PIBC11_PIBC117_SHIFT (7u) +#define GPIO_PIBC11_PIBC118_SHIFT (8u) +#define GPIO_PIBC11_PIBC119_SHIFT (9u) +#define GPIO_PIBC11_PIBC1110_SHIFT (10u) +#define GPIO_PIBC11_PIBC1111_SHIFT (11u) +#define GPIO_PIBC11_PIBC1112_SHIFT (12u) +#define GPIO_PIBC11_PIBC1113_SHIFT (13u) +#define GPIO_PIBC11_PIBC1114_SHIFT (14u) +#define GPIO_PIBC11_PIBC1115_SHIFT (15u) + +#define GPIO_PBDC11_PBDC110_SHIFT (0u) +#define GPIO_PBDC11_PBDC111_SHIFT (1u) +#define GPIO_PBDC11_PBDC112_SHIFT (2u) +#define GPIO_PBDC11_PBDC113_SHIFT (3u) +#define GPIO_PBDC11_PBDC114_SHIFT (4u) +#define GPIO_PBDC11_PBDC115_SHIFT (5u) +#define GPIO_PBDC11_PBDC116_SHIFT (6u) +#define GPIO_PBDC11_PBDC117_SHIFT (7u) +#define GPIO_PBDC11_PBDC118_SHIFT (8u) +#define GPIO_PBDC11_PBDC119_SHIFT (9u) +#define GPIO_PBDC11_PBDC1110_SHIFT (10u) +#define GPIO_PBDC11_PBDC1111_SHIFT (11u) +#define GPIO_PBDC11_PBDC1112_SHIFT (12u) +#define GPIO_PBDC11_PBDC1113_SHIFT (13u) +#define GPIO_PBDC11_PBDC1114_SHIFT (14u) +#define GPIO_PBDC11_PBDC1115_SHIFT (15u) + +#define GPIO_PIPC11_PIPC110_SHIFT (0u) +#define GPIO_PIPC11_PIPC111_SHIFT (1u) +#define GPIO_PIPC11_PIPC112_SHIFT (2u) +#define GPIO_PIPC11_PIPC113_SHIFT (3u) +#define GPIO_PIPC11_PIPC114_SHIFT (4u) +#define GPIO_PIPC11_PIPC115_SHIFT (5u) +#define GPIO_PIPC11_PIPC116_SHIFT (6u) +#define GPIO_PIPC11_PIPC117_SHIFT (7u) +#define GPIO_PIPC11_PIPC118_SHIFT (8u) +#define GPIO_PIPC11_PIPC119_SHIFT (9u) +#define GPIO_PIPC11_PIPC1110_SHIFT (10u) +#define GPIO_PIPC11_PIPC1111_SHIFT (11u) +#define GPIO_PIPC11_PIPC1112_SHIFT (12u) +#define GPIO_PIPC11_PIPC1113_SHIFT (13u) +#define GPIO_PIPC11_PIPC1114_SHIFT (14u) +#define GPIO_PIPC11_PIPC1115_SHIFT (15u) + + +#endif /* GPIO_IOBITMASK_H */ + +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,11237 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : intc_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : INTC register define header +*******************************************************************************/ +#ifndef INTC_IOBITMASK_H +#define INTC_IOBITMASK_H + +/* ==== Mask values for IO registers ==== */ +#define INTC_ICDDCR_Enable (0x00000001uL) + +#define INTC_ICDICTR_ITLinesNumber (0x0000001FuL) +#define INTC_ICDICTR_CPUNumber (0x000000E0uL) +#define INTC_ICDICTR_SecurityExtn (0x00000400uL) +#define INTC_ICDICTR_LSPI (0x0000F800uL) + +#define INTC_ICDIIDR_Implementer (0x00000FFFuL) +#define INTC_ICDIIDR_Revision (0x0000F000uL) +#define INTC_ICDIIDR_Variant (0x000F0000uL) +#define INTC_ICDIIDR_ProductID (0xFF000000uL) + +#define INTC_ICDISR0_SW0 (0x00000001uL) +#define INTC_ICDISR0_SW1 (0x00000002uL) +#define INTC_ICDISR0_SW2 (0x00000004uL) +#define INTC_ICDISR0_SW3 (0x00000008uL) +#define INTC_ICDISR0_SW4 (0x00000010uL) +#define INTC_ICDISR0_SW5 (0x00000020uL) +#define INTC_ICDISR0_SW6 (0x00000040uL) +#define INTC_ICDISR0_SW7 (0x00000080uL) +#define INTC_ICDISR0_SW8 (0x00000100uL) +#define INTC_ICDISR0_SW9 (0x00000200uL) +#define INTC_ICDISR0_SW10 (0x00000400uL) +#define INTC_ICDISR0_SW11 (0x00000800uL) +#define INTC_ICDISR0_SW12 (0x00001000uL) +#define INTC_ICDISR0_SW13 (0x00002000uL) +#define INTC_ICDISR0_SW14 (0x00004000uL) +#define INTC_ICDISR0_SW15 (0x00008000uL) +#define INTC_ICDISR0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDISR0_COMMRX0 (0x00020000uL) +#define INTC_ICDISR0_COMMTX0 (0x00040000uL) +#define INTC_ICDISR0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDISR1_IRQ0 (0x00000001uL) +#define INTC_ICDISR1_IRQ1 (0x00000002uL) +#define INTC_ICDISR1_IRQ2 (0x00000004uL) +#define INTC_ICDISR1_IRQ3 (0x00000008uL) +#define INTC_ICDISR1_IRQ4 (0x00000010uL) +#define INTC_ICDISR1_IRQ5 (0x00000020uL) +#define INTC_ICDISR1_IRQ6 (0x00000040uL) +#define INTC_ICDISR1_IRQ7 (0x00000080uL) +#define INTC_ICDISR1_PL310ERR (0x00000100uL) +#define INTC_ICDISR1_DMAINT0 (0x00000200uL) +#define INTC_ICDISR1_DMAINT1 (0x00000400uL) +#define INTC_ICDISR1_DMAINT2 (0x00000800uL) +#define INTC_ICDISR1_DMAINT3 (0x00001000uL) +#define INTC_ICDISR1_DMAINT4 (0x00002000uL) +#define INTC_ICDISR1_DMAINT5 (0x00004000uL) +#define INTC_ICDISR1_DMAINT6 (0x00008000uL) +#define INTC_ICDISR1_DMAINT7 (0x00010000uL) +#define INTC_ICDISR1_DMAINT8 (0x00020000uL) +#define INTC_ICDISR1_DMAINT9 (0x00040000uL) +#define INTC_ICDISR1_DMAINT10 (0x00080000uL) +#define INTC_ICDISR1_DMAINT11 (0x00100000uL) +#define INTC_ICDISR1_DMAINT12 (0x00200000uL) +#define INTC_ICDISR1_DMAINT13 (0x00400000uL) +#define INTC_ICDISR1_DMAINT14 (0x00800000uL) +#define INTC_ICDISR1_DMAINT15 (0x01000000uL) +#define INTC_ICDISR1_DMAERR (0x02000000uL) + +#define INTC_ICDISR2_USBI0 (0x00000200uL) +#define INTC_ICDISR2_USBI1 (0x00000400uL) +#define INTC_ICDISR2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDISR2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDISR2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDISR2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDISR2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDISR2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDISR2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDISR2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDISR2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDISR2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDISR2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDISR2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDISR2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDISR2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDISR2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDISR2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDISR2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDISR2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDISR2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDISR2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDISR2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDISR3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDISR3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDISR3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDISR3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDISR3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDISR3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDISR3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDISR3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDISR3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDISR3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDISR3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDISR3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDISR3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDISR3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDISR3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDISR3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDISR3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDISR3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDISR3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDISR3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDISR3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDISR3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDISR3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDISR3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDISR3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDISR3_IMRDI (0x08000000uL) +#define INTC_ICDISR3_IMR2I0 (0x10000000uL) +#define INTC_ICDISR3_IMR2I1 (0x20000000uL) +#define INTC_ICDISR3_JEDI (0x40000000uL) +#define INTC_ICDISR3_JDTI (0x80000000uL) + +#define INTC_ICDISR4_CMP0 (0x00000001uL) +#define INTC_ICDISR4_CMP1 (0x00000002uL) +#define INTC_ICDISR4_INT0 (0x00000004uL) +#define INTC_ICDISR4_INT1 (0x00000008uL) +#define INTC_ICDISR4_INT2 (0x00000010uL) +#define INTC_ICDISR4_INT3 (0x00000020uL) +#define INTC_ICDISR4_OSTM0TINT (0x00000040uL) +#define INTC_ICDISR4_OSTM1TINT (0x00000080uL) +#define INTC_ICDISR4_CMI (0x00000100uL) +#define INTC_ICDISR4_WTOUT (0x00000200uL) +#define INTC_ICDISR4_ITI (0x00000400uL) +#define INTC_ICDISR4_TGI0A (0x00000800uL) +#define INTC_ICDISR4_TGI0B (0x00001000uL) +#define INTC_ICDISR4_TGI0C (0x00002000uL) +#define INTC_ICDISR4_TGI0D (0x00004000uL) +#define INTC_ICDISR4_TGI0V (0x00008000uL) +#define INTC_ICDISR4_TGI0E (0x00010000uL) +#define INTC_ICDISR4_TGI0F (0x00020000uL) +#define INTC_ICDISR4_TGI1A (0x00040000uL) +#define INTC_ICDISR4_TGI1B (0x00080000uL) +#define INTC_ICDISR4_TGI1V (0x00100000uL) +#define INTC_ICDISR4_TGI1U (0x00200000uL) +#define INTC_ICDISR4_TGI2A (0x00400000uL) +#define INTC_ICDISR4_TGI2B (0x00800000uL) +#define INTC_ICDISR4_TGI2V (0x01000000uL) +#define INTC_ICDISR4_TGI2U (0x02000000uL) +#define INTC_ICDISR4_TGI3A (0x04000000uL) +#define INTC_ICDISR4_TGI3B (0x08000000uL) +#define INTC_ICDISR4_TGI3C (0x10000000uL) +#define INTC_ICDISR4_TGI3D (0x20000000uL) +#define INTC_ICDISR4_TGI3V (0x40000000uL) +#define INTC_ICDISR4_TGI4A (0x80000000uL) + +#define INTC_ICDISR5_TGI4B (0x00000001uL) +#define INTC_ICDISR5_TGI4C (0x00000002uL) +#define INTC_ICDISR5_TGI4D (0x00000004uL) +#define INTC_ICDISR5_TGI4V (0x00000008uL) +#define INTC_ICDISR5_CMI1 (0x00000010uL) +#define INTC_ICDISR5_CMI2 (0x00000020uL) +#define INTC_ICDISR5_SGDEI0 (0x00000040uL) +#define INTC_ICDISR5_SGDEI1 (0x00000080uL) +#define INTC_ICDISR5_SGDEI2 (0x00000100uL) +#define INTC_ICDISR5_SGDEI3 (0x00000200uL) +#define INTC_ICDISR5_ADI (0x00000400uL) +#define INTC_ICDISR5_LMTI (0x00000800uL) +#define INTC_ICDISR5_SSII0 (0x00001000uL) +#define INTC_ICDISR5_SSIRXI0 (0x00002000uL) +#define INTC_ICDISR5_SSITXI0 (0x00004000uL) +#define INTC_ICDISR5_SSII1 (0x00008000uL) +#define INTC_ICDISR5_SSIRXI1 (0x00010000uL) +#define INTC_ICDISR5_SSITXI1 (0x00020000uL) +#define INTC_ICDISR5_SSII2 (0x00040000uL) +#define INTC_ICDISR5_SSIRTI2 (0x00080000uL) +#define INTC_ICDISR5_SSII3 (0x00100000uL) +#define INTC_ICDISR5_SSIRXI3 (0x00200000uL) +#define INTC_ICDISR5_SSITXI3 (0x00400000uL) +#define INTC_ICDISR5_SSII4 (0x00800000uL) +#define INTC_ICDISR5_SSIRTI4 (0x01000000uL) +#define INTC_ICDISR5_SSII5 (0x02000000uL) +#define INTC_ICDISR5_SSIRXI5 (0x04000000uL) +#define INTC_ICDISR5_SSITXI5 (0x08000000uL) +#define INTC_ICDISR5_SPDIFI (0x10000000uL) +#define INTC_ICDISR5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDISR5_INTIICRI0 (0x40000000uL) +#define INTC_ICDISR5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDISR6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDISR6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDISR6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDISR6_INTIICALI0 (0x00000008uL) +#define INTC_ICDISR6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDISR6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDISR6_INTIICRI1 (0x00000040uL) +#define INTC_ICDISR6_INTIICTI1 (0x00000080uL) +#define INTC_ICDISR6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDISR6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDISR6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDISR6_INTIICALI1 (0x00000800uL) +#define INTC_ICDISR6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDISR6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDISR6_INTIICRI2 (0x00004000uL) +#define INTC_ICDISR6_INTIICTI2 (0x00008000uL) +#define INTC_ICDISR6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDISR6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDISR6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDISR6_INTIICALI2 (0x00080000uL) +#define INTC_ICDISR6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDISR6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDISR6_INTIICRI3 (0x00400000uL) +#define INTC_ICDISR6_INTIICTI3 (0x00800000uL) +#define INTC_ICDISR6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDISR6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDISR6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDISR6_INTIICALI3 (0x08000000uL) +#define INTC_ICDISR6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDISR6_BRI0 (0x20000000uL) +#define INTC_ICDISR6_ERI0 (0x40000000uL) +#define INTC_ICDISR6_RXI0 (0x80000000uL) + +#define INTC_ICDISR7_TXI0 (0x00000001uL) +#define INTC_ICDISR7_BRI1 (0x00000002uL) +#define INTC_ICDISR7_ERI1 (0x00000004uL) +#define INTC_ICDISR7_RXI1 (0x00000008uL) +#define INTC_ICDISR7_TXI1 (0x00000010uL) +#define INTC_ICDISR7_BRI2 (0x00000020uL) +#define INTC_ICDISR7_ERI2 (0x00000040uL) +#define INTC_ICDISR7_RXI2 (0x00000080uL) +#define INTC_ICDISR7_TXI2 (0x00000100uL) +#define INTC_ICDISR7_BRI3 (0x00000200uL) +#define INTC_ICDISR7_ERI3 (0x00000400uL) +#define INTC_ICDISR7_RXI3 (0x00000800uL) +#define INTC_ICDISR7_TXI3 (0x00001000uL) +#define INTC_ICDISR7_BRI4 (0x00002000uL) +#define INTC_ICDISR7_ERI4 (0x00004000uL) +#define INTC_ICDISR7_RXI4 (0x00008000uL) +#define INTC_ICDISR7_TXI4 (0x00010000uL) +#define INTC_ICDISR7_BRI5 (0x00020000uL) +#define INTC_ICDISR7_ERI5 (0x00040000uL) +#define INTC_ICDISR7_RXI5 (0x00080000uL) +#define INTC_ICDISR7_TXI5 (0x00100000uL) +#define INTC_ICDISR7_BRI6 (0x00200000uL) +#define INTC_ICDISR7_ERI6 (0x00400000uL) +#define INTC_ICDISR7_RXI6 (0x00800000uL) +#define INTC_ICDISR7_TXI6 (0x01000000uL) +#define INTC_ICDISR7_BRI7 (0x02000000uL) +#define INTC_ICDISR7_ERI7 (0x04000000uL) +#define INTC_ICDISR7_RXI7 (0x08000000uL) +#define INTC_ICDISR7_TXI7 (0x10000000uL) +#define INTC_ICDISR7_INTRCANGERR (0x20000000uL) +#define INTC_ICDISR7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDISR7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDISR8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDISR8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDISR8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDISR8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDISR8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDISR8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDISR8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDISR8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDISR8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDISR8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDISR8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDISR8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDISR8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDISR8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDISR8_SPEI0 (0x00004000uL) +#define INTC_ICDISR8_SPRI0 (0x00008000uL) +#define INTC_ICDISR8_SPTI0 (0x00010000uL) +#define INTC_ICDISR8_SPEI1 (0x00020000uL) +#define INTC_ICDISR8_SPRI1 (0x00040000uL) +#define INTC_ICDISR8_SPTI1 (0x00080000uL) +#define INTC_ICDISR8_SPEI2 (0x00100000uL) +#define INTC_ICDISR8_SPRI2 (0x00200000uL) +#define INTC_ICDISR8_SPTI2 (0x00400000uL) +#define INTC_ICDISR8_SPEI3 (0x00800000uL) +#define INTC_ICDISR8_SPRI3 (0x01000000uL) +#define INTC_ICDISR8_SPTI3 (0x02000000uL) +#define INTC_ICDISR8_SPEI4 (0x04000000uL) +#define INTC_ICDISR8_SPRI4 (0x08000000uL) +#define INTC_ICDISR8_SPTI4 (0x10000000uL) +#define INTC_ICDISR8_IEBBTD (0x20000000uL) +#define INTC_ICDISR8_IEBBTERR (0x40000000uL) +#define INTC_ICDISR8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDISR9_IEBBTV (0x00000001uL) +#define INTC_ICDISR9_ISY (0x00000002uL) +#define INTC_ICDISR9_IERR (0x00000004uL) +#define INTC_ICDISR9_ITARG (0x00000008uL) +#define INTC_ICDISR9_ISEC (0x00000010uL) +#define INTC_ICDISR9_IBUF (0x00000020uL) +#define INTC_ICDISR9_IREADY (0x00000040uL) +#define INTC_ICDISR9_FLSTE (0x00000080uL) +#define INTC_ICDISR9_FLTENDI (0x00000100uL) +#define INTC_ICDISR9_FLTREQ0I (0x00000200uL) +#define INTC_ICDISR9_FLTREQ1I (0x00000400uL) +#define INTC_ICDISR9_MMC0 (0x00000800uL) +#define INTC_ICDISR9_MMC1 (0x00001000uL) +#define INTC_ICDISR9_MMC2 (0x00002000uL) +#define INTC_ICDISR9_SDHI0_3 (0x00004000uL) +#define INTC_ICDISR9_SDHI0_0 (0x00008000uL) +#define INTC_ICDISR9_SDHI0_1 (0x00010000uL) +#define INTC_ICDISR9_SDHI1_3 (0x00020000uL) +#define INTC_ICDISR9_SDHI1_0 (0x00040000uL) +#define INTC_ICDISR9_SDHI1_1 (0x00080000uL) +#define INTC_ICDISR9_ARM (0x00100000uL) +#define INTC_ICDISR9_PRD (0x00200000uL) +#define INTC_ICDISR9_CUP (0x00400000uL) +#define INTC_ICDISR9_SCUAI0 (0x00800000uL) +#define INTC_ICDISR9_SCUAI1 (0x01000000uL) +#define INTC_ICDISR9_SCUFDI0 (0x02000000uL) +#define INTC_ICDISR9_SCUFDI1 (0x04000000uL) +#define INTC_ICDISR9_SCUFDI2 (0x08000000uL) +#define INTC_ICDISR9_SCUFDI3 (0x10000000uL) +#define INTC_ICDISR9_SCUFUI0 (0x20000000uL) +#define INTC_ICDISR9_SCUFUI1 (0x40000000uL) +#define INTC_ICDISR9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDISR10_SCUFUI3 (0x00000001uL) +#define INTC_ICDISR10_SCUDVI0 (0x00000002uL) +#define INTC_ICDISR10_SCUDVI1 (0x00000004uL) +#define INTC_ICDISR10_SCUDVI2 (0x00000008uL) +#define INTC_ICDISR10_SCUDVI3 (0x00000010uL) +#define INTC_ICDISR10_MLB_CINT (0x00000020uL) +#define INTC_ICDISR10_MLB_SINT (0x00000040uL) +#define INTC_ICDISR10_DRC0 (0x00000080uL) +#define INTC_ICDISR10_DRC1 (0x00000100uL) +#define INTC_ICDISR10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDISR10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDISR10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDISR10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDISR10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDISR10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDISR10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDISR10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDISR10_ERI0 (0x08000000uL) +#define INTC_ICDISR10_RXI0 (0x10000000uL) +#define INTC_ICDISR10_TXI0 (0x20000000uL) +#define INTC_ICDISR10_TEI0 (0x40000000uL) +#define INTC_ICDISR10_ERI1 (0x80000000uL) + +#define INTC_ICDISR11_RXI1 (0x00000001uL) +#define INTC_ICDISR11_TXI1 (0x00000002uL) +#define INTC_ICDISR11_TEI1 (0x00000004uL) +#define INTC_ICDISR11_AVBI_DATA (0x00000008uL) +#define INTC_ICDISR11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDISR11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDISR11_AVBI_MAC (0x00000040uL) +#define INTC_ICDISR11_ETHERI (0x00000080uL) +#define INTC_ICDISR11_CEUI (0x00001000uL) +#define INTC_ICDISR11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDISR11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDISR11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDISR12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDISR12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDISR12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDISR12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDISR12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDISR12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDISR12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDISR12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDISR12_PRRI (0x00000100uL) +#define INTC_ICDISR12_IFEI0 (0x00000200uL) +#define INTC_ICDISR12_OFFI0 (0x00000400uL) +#define INTC_ICDISR12_PFVEI0 (0x00000800uL) +#define INTC_ICDISR12_IFEI1 (0x00001000uL) +#define INTC_ICDISR12_OFFI1 (0x00002000uL) +#define INTC_ICDISR12_PFVEI1 (0x00004000uL) + +#define INTC_ICDISR13_TINT0 (0x00000001uL) +#define INTC_ICDISR13_TINT1 (0x00000002uL) +#define INTC_ICDISR13_TINT2 (0x00000004uL) +#define INTC_ICDISR13_TINT3 (0x00000008uL) +#define INTC_ICDISR13_TINT4 (0x00000010uL) +#define INTC_ICDISR13_TINT5 (0x00000020uL) +#define INTC_ICDISR13_TINT6 (0x00000040uL) +#define INTC_ICDISR13_TINT7 (0x00000080uL) +#define INTC_ICDISR13_TINT8 (0x00000100uL) +#define INTC_ICDISR13_TINT9 (0x00000200uL) +#define INTC_ICDISR13_TINT10 (0x00000400uL) +#define INTC_ICDISR13_TINT11 (0x00000800uL) +#define INTC_ICDISR13_TINT12 (0x00001000uL) +#define INTC_ICDISR13_TINT13 (0x00002000uL) +#define INTC_ICDISR13_TINT14 (0x00004000uL) +#define INTC_ICDISR13_TINT15 (0x00008000uL) +#define INTC_ICDISR13_TINT16 (0x00010000uL) +#define INTC_ICDISR13_TINT17 (0x00020000uL) +#define INTC_ICDISR13_TINT18 (0x00040000uL) +#define INTC_ICDISR13_TINT19 (0x00080000uL) +#define INTC_ICDISR13_TINT20 (0x00100000uL) +#define INTC_ICDISR13_TINT21 (0x00200000uL) +#define INTC_ICDISR13_TINT22 (0x00400000uL) +#define INTC_ICDISR13_TINT23 (0x00800000uL) +#define INTC_ICDISR13_TINT24 (0x01000000uL) +#define INTC_ICDISR13_TINT25 (0x02000000uL) +#define INTC_ICDISR13_TINT26 (0x04000000uL) +#define INTC_ICDISR13_TINT27 (0x08000000uL) +#define INTC_ICDISR13_TINT28 (0x10000000uL) +#define INTC_ICDISR13_TINT29 (0x20000000uL) +#define INTC_ICDISR13_TINT30 (0x40000000uL) +#define INTC_ICDISR13_TINT31 (0x80000000uL) + +#define INTC_ICDISR14_TINT32 (0x00000001uL) +#define INTC_ICDISR14_TINT33 (0x00000002uL) +#define INTC_ICDISR14_TINT34 (0x00000004uL) +#define INTC_ICDISR14_TINT35 (0x00000008uL) +#define INTC_ICDISR14_TINT36 (0x00000010uL) +#define INTC_ICDISR14_TINT37 (0x00000020uL) +#define INTC_ICDISR14_TINT38 (0x00000040uL) +#define INTC_ICDISR14_TINT39 (0x00000080uL) +#define INTC_ICDISR14_TINT40 (0x00000100uL) +#define INTC_ICDISR14_TINT41 (0x00000200uL) +#define INTC_ICDISR14_TINT42 (0x00000400uL) +#define INTC_ICDISR14_TINT43 (0x00000800uL) +#define INTC_ICDISR14_TINT44 (0x00001000uL) +#define INTC_ICDISR14_TINT45 (0x00002000uL) +#define INTC_ICDISR14_TINT46 (0x00004000uL) +#define INTC_ICDISR14_TINT47 (0x00008000uL) +#define INTC_ICDISR14_TINT48 (0x00010000uL) +#define INTC_ICDISR14_TINT49 (0x00020000uL) +#define INTC_ICDISR14_TINT50 (0x00040000uL) +#define INTC_ICDISR14_TINT51 (0x00080000uL) +#define INTC_ICDISR14_TINT52 (0x00100000uL) +#define INTC_ICDISR14_TINT53 (0x00200000uL) +#define INTC_ICDISR14_TINT54 (0x00400000uL) +#define INTC_ICDISR14_TINT55 (0x00800000uL) +#define INTC_ICDISR14_TINT56 (0x01000000uL) +#define INTC_ICDISR14_TINT57 (0x02000000uL) +#define INTC_ICDISR14_TINT58 (0x04000000uL) +#define INTC_ICDISR14_TINT59 (0x08000000uL) +#define INTC_ICDISR14_TINT60 (0x10000000uL) +#define INTC_ICDISR14_TINT61 (0x20000000uL) +#define INTC_ICDISR14_TINT62 (0x40000000uL) +#define INTC_ICDISR14_TINT63 (0x80000000uL) + +#define INTC_ICDISR15_TINT64 (0x00000001uL) +#define INTC_ICDISR15_TINT65 (0x00000002uL) +#define INTC_ICDISR15_TINT66 (0x00000004uL) +#define INTC_ICDISR15_TINT67 (0x00000008uL) +#define INTC_ICDISR15_TINT68 (0x00000010uL) +#define INTC_ICDISR15_TINT69 (0x00000020uL) +#define INTC_ICDISR15_TINT70 (0x00000040uL) +#define INTC_ICDISR15_TINT71 (0x00000080uL) +#define INTC_ICDISR15_TINT72 (0x00000100uL) +#define INTC_ICDISR15_TINT73 (0x00000200uL) +#define INTC_ICDISR15_TINT74 (0x00000400uL) +#define INTC_ICDISR15_TINT75 (0x00000800uL) +#define INTC_ICDISR15_TINT76 (0x00001000uL) +#define INTC_ICDISR15_TINT77 (0x00002000uL) +#define INTC_ICDISR15_TINT78 (0x00004000uL) +#define INTC_ICDISR15_TINT79 (0x00008000uL) +#define INTC_ICDISR15_TINT80 (0x00010000uL) +#define INTC_ICDISR15_TINT81 (0x00020000uL) +#define INTC_ICDISR15_TINT82 (0x00040000uL) +#define INTC_ICDISR15_TINT83 (0x00080000uL) +#define INTC_ICDISR15_TINT84 (0x00100000uL) +#define INTC_ICDISR15_TINT85 (0x00200000uL) +#define INTC_ICDISR15_TINT86 (0x00400000uL) +#define INTC_ICDISR15_TINT87 (0x00800000uL) +#define INTC_ICDISR15_TINT88 (0x01000000uL) +#define INTC_ICDISR15_TINT89 (0x02000000uL) +#define INTC_ICDISR15_TINT90 (0x04000000uL) +#define INTC_ICDISR15_TINT91 (0x08000000uL) +#define INTC_ICDISR15_TINT92 (0x10000000uL) +#define INTC_ICDISR15_TINT93 (0x20000000uL) +#define INTC_ICDISR15_TINT94 (0x40000000uL) +#define INTC_ICDISR15_TINT95 (0x80000000uL) + +#define INTC_ICDISR16_TINT96 (0x00000001uL) +#define INTC_ICDISR16_TINT97 (0x00000002uL) +#define INTC_ICDISR16_TINT98 (0x00000004uL) +#define INTC_ICDISR16_TINT99 (0x00000008uL) +#define INTC_ICDISR16_TINT100 (0x00000010uL) +#define INTC_ICDISR16_TINT101 (0x00000020uL) +#define INTC_ICDISR16_TINT102 (0x00000040uL) +#define INTC_ICDISR16_TINT103 (0x00000080uL) +#define INTC_ICDISR16_TINT104 (0x00000100uL) +#define INTC_ICDISR16_TINT105 (0x00000200uL) +#define INTC_ICDISR16_TINT106 (0x00000400uL) +#define INTC_ICDISR16_TINT107 (0x00000800uL) +#define INTC_ICDISR16_TINT108 (0x00001000uL) +#define INTC_ICDISR16_TINT109 (0x00002000uL) +#define INTC_ICDISR16_TINT110 (0x00004000uL) +#define INTC_ICDISR16_TINT111 (0x00008000uL) +#define INTC_ICDISR16_TINT112 (0x00010000uL) +#define INTC_ICDISR16_TINT113 (0x00020000uL) +#define INTC_ICDISR16_TINT114 (0x00040000uL) +#define INTC_ICDISR16_TINT115 (0x00080000uL) +#define INTC_ICDISR16_TINT116 (0x00100000uL) +#define INTC_ICDISR16_TINT117 (0x00200000uL) +#define INTC_ICDISR16_TINT118 (0x00400000uL) +#define INTC_ICDISR16_TINT119 (0x00800000uL) +#define INTC_ICDISR16_TINT120 (0x01000000uL) +#define INTC_ICDISR16_TINT121 (0x02000000uL) +#define INTC_ICDISR16_TINT122 (0x04000000uL) +#define INTC_ICDISR16_TINT123 (0x08000000uL) +#define INTC_ICDISR16_TINT124 (0x10000000uL) +#define INTC_ICDISR16_TINT125 (0x20000000uL) +#define INTC_ICDISR16_TINT126 (0x40000000uL) +#define INTC_ICDISR16_TINT127 (0x80000000uL) + +#define INTC_ICDISR17_TINT128 (0x00000001uL) +#define INTC_ICDISR17_TINT129 (0x00000002uL) +#define INTC_ICDISR17_TINT130 (0x00000004uL) +#define INTC_ICDISR17_TINT131 (0x00000008uL) +#define INTC_ICDISR17_TINT132 (0x00000010uL) +#define INTC_ICDISR17_TINT133 (0x00000020uL) +#define INTC_ICDISR17_TINT134 (0x00000040uL) +#define INTC_ICDISR17_TINT135 (0x00000080uL) +#define INTC_ICDISR17_TINT136 (0x00000100uL) +#define INTC_ICDISR17_TINT137 (0x00000200uL) +#define INTC_ICDISR17_TINT138 (0x00000400uL) +#define INTC_ICDISR17_TINT139 (0x00000800uL) +#define INTC_ICDISR17_TINT140 (0x00001000uL) +#define INTC_ICDISR17_TINT141 (0x00002000uL) +#define INTC_ICDISR17_TINT142 (0x00004000uL) +#define INTC_ICDISR17_TINT143 (0x00008000uL) +#define INTC_ICDISR17_TINT144 (0x00010000uL) +#define INTC_ICDISR17_TINT145 (0x00020000uL) +#define INTC_ICDISR17_TINT146 (0x00040000uL) +#define INTC_ICDISR17_TINT147 (0x00080000uL) +#define INTC_ICDISR17_TINT148 (0x00100000uL) +#define INTC_ICDISR17_TINT149 (0x00200000uL) +#define INTC_ICDISR17_TINT150 (0x00400000uL) +#define INTC_ICDISR17_TINT151 (0x00800000uL) +#define INTC_ICDISR17_TINT152 (0x01000000uL) +#define INTC_ICDISR17_TINT153 (0x02000000uL) +#define INTC_ICDISR17_TINT154 (0x04000000uL) +#define INTC_ICDISR17_TINT155 (0x08000000uL) +#define INTC_ICDISR17_TINT156 (0x10000000uL) +#define INTC_ICDISR17_TINT157 (0x20000000uL) +#define INTC_ICDISR17_TINT158 (0x40000000uL) +#define INTC_ICDISR17_TINT159 (0x80000000uL) + +#define INTC_ICDISR18_TINT160 (0x00000001uL) +#define INTC_ICDISR18_TINT161 (0x00000002uL) +#define INTC_ICDISR18_TINT162 (0x00000004uL) +#define INTC_ICDISR18_TINT163 (0x00000008uL) +#define INTC_ICDISR18_TINT164 (0x00000010uL) +#define INTC_ICDISR18_TINT165 (0x00000020uL) +#define INTC_ICDISR18_TINT166 (0x00000040uL) +#define INTC_ICDISR18_TINT167 (0x00000080uL) +#define INTC_ICDISR18_TINT168 (0x00000100uL) +#define INTC_ICDISR18_TINT169 (0x00000200uL) +#define INTC_ICDISR18_TINT170 (0x00000400uL) + +#define INTC_ICDISER0_SW0 (0x00000001uL) +#define INTC_ICDISER0_SW1 (0x00000002uL) +#define INTC_ICDISER0_SW2 (0x00000004uL) +#define INTC_ICDISER0_SW3 (0x00000008uL) +#define INTC_ICDISER0_SW4 (0x00000010uL) +#define INTC_ICDISER0_SW5 (0x00000020uL) +#define INTC_ICDISER0_SW6 (0x00000040uL) +#define INTC_ICDISER0_SW7 (0x00000080uL) +#define INTC_ICDISER0_SW8 (0x00000100uL) +#define INTC_ICDISER0_SW9 (0x00000200uL) +#define INTC_ICDISER0_SW10 (0x00000400uL) +#define INTC_ICDISER0_SW11 (0x00000800uL) +#define INTC_ICDISER0_SW12 (0x00001000uL) +#define INTC_ICDISER0_SW13 (0x00002000uL) +#define INTC_ICDISER0_SW14 (0x00004000uL) +#define INTC_ICDISER0_SW15 (0x00008000uL) +#define INTC_ICDISER0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDISER0_COMMRX0 (0x00020000uL) +#define INTC_ICDISER0_COMMTX0 (0x00040000uL) +#define INTC_ICDISER0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDISER1_IRQ0 (0x00000001uL) +#define INTC_ICDISER1_IRQ1 (0x00000002uL) +#define INTC_ICDISER1_IRQ2 (0x00000004uL) +#define INTC_ICDISER1_IRQ3 (0x00000008uL) +#define INTC_ICDISER1_IRQ4 (0x00000010uL) +#define INTC_ICDISER1_IRQ5 (0x00000020uL) +#define INTC_ICDISER1_IRQ6 (0x00000040uL) +#define INTC_ICDISER1_IRQ7 (0x00000080uL) +#define INTC_ICDISER1_PL310ERR (0x00000100uL) +#define INTC_ICDISER1_DMAINT0 (0x00000200uL) +#define INTC_ICDISER1_DMAINT1 (0x00000400uL) +#define INTC_ICDISER1_DMAINT2 (0x00000800uL) +#define INTC_ICDISER1_DMAINT3 (0x00001000uL) +#define INTC_ICDISER1_DMAINT4 (0x00002000uL) +#define INTC_ICDISER1_DMAINT5 (0x00004000uL) +#define INTC_ICDISER1_DMAINT6 (0x00008000uL) +#define INTC_ICDISER1_DMAINT7 (0x00010000uL) +#define INTC_ICDISER1_DMAINT8 (0x00020000uL) +#define INTC_ICDISER1_DMAINT9 (0x00040000uL) +#define INTC_ICDISER1_DMAINT10 (0x00080000uL) +#define INTC_ICDISER1_DMAINT11 (0x00100000uL) +#define INTC_ICDISER1_DMAINT12 (0x00200000uL) +#define INTC_ICDISER1_DMAINT13 (0x00400000uL) +#define INTC_ICDISER1_DMAINT14 (0x00800000uL) +#define INTC_ICDISER1_DMAINT15 (0x01000000uL) +#define INTC_ICDISER1_DMAERR (0x02000000uL) + +#define INTC_ICDISER2_USBI0 (0x00000200uL) +#define INTC_ICDISER2_USBI1 (0x00000400uL) +#define INTC_ICDISER2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDISER2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDISER2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDISER2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDISER2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDISER2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDISER2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDISER2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDISER2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDISER2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDISER2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDISER2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDISER2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDISER2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDISER2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDISER2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDISER2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDISER2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDISER2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDISER2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDISER2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDISER3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDISER3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDISER3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDISER3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDISER3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDISER3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDISER3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDISER3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDISER3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDISER3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDISER3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDISER3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDISER3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDISER3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDISER3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDISER3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDISER3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDISER3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDISER3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDISER3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDISER3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDISER3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDISER3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDISER3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDISER3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDISER3_IMRDI (0x08000000uL) +#define INTC_ICDISER3_IMR2I0 (0x10000000uL) +#define INTC_ICDISER3_IMR2I1 (0x20000000uL) +#define INTC_ICDISER3_JEDI (0x40000000uL) +#define INTC_ICDISER3_JDTI (0x80000000uL) + +#define INTC_ICDISER4_CMP0 (0x00000001uL) +#define INTC_ICDISER4_CMP1 (0x00000002uL) +#define INTC_ICDISER4_INT0 (0x00000004uL) +#define INTC_ICDISER4_INT1 (0x00000008uL) +#define INTC_ICDISER4_INT2 (0x00000010uL) +#define INTC_ICDISER4_INT3 (0x00000020uL) +#define INTC_ICDISER4_OSTM0TINT (0x00000040uL) +#define INTC_ICDISER4_OSTM1TINT (0x00000080uL) +#define INTC_ICDISER4_CMI (0x00000100uL) +#define INTC_ICDISER4_WTOUT (0x00000200uL) +#define INTC_ICDISER4_ITI (0x00000400uL) +#define INTC_ICDISER4_TGI0A (0x00000800uL) +#define INTC_ICDISER4_TGI0B (0x00001000uL) +#define INTC_ICDISER4_TGI0C (0x00002000uL) +#define INTC_ICDISER4_TGI0D (0x00004000uL) +#define INTC_ICDISER4_TGI0V (0x00008000uL) +#define INTC_ICDISER4_TGI0E (0x00010000uL) +#define INTC_ICDISER4_TGI0F (0x00020000uL) +#define INTC_ICDISER4_TGI1A (0x00040000uL) +#define INTC_ICDISER4_TGI1B (0x00080000uL) +#define INTC_ICDISER4_TGI1V (0x00100000uL) +#define INTC_ICDISER4_TGI1U (0x00200000uL) +#define INTC_ICDISER4_TGI2A (0x00400000uL) +#define INTC_ICDISER4_TGI2B (0x00800000uL) +#define INTC_ICDISER4_TGI2V (0x01000000uL) +#define INTC_ICDISER4_TGI2U (0x02000000uL) +#define INTC_ICDISER4_TGI3A (0x04000000uL) +#define INTC_ICDISER4_TGI3B (0x08000000uL) +#define INTC_ICDISER4_TGI3C (0x10000000uL) +#define INTC_ICDISER4_TGI3D (0x20000000uL) +#define INTC_ICDISER4_TGI3V (0x40000000uL) +#define INTC_ICDISER4_TGI4A (0x80000000uL) + +#define INTC_ICDISER5_TGI4B (0x00000001uL) +#define INTC_ICDISER5_TGI4C (0x00000002uL) +#define INTC_ICDISER5_TGI4D (0x00000004uL) +#define INTC_ICDISER5_TGI4V (0x00000008uL) +#define INTC_ICDISER5_CMI1 (0x00000010uL) +#define INTC_ICDISER5_CMI2 (0x00000020uL) +#define INTC_ICDISER5_SGDEI0 (0x00000040uL) +#define INTC_ICDISER5_SGDEI1 (0x00000080uL) +#define INTC_ICDISER5_SGDEI2 (0x00000100uL) +#define INTC_ICDISER5_SGDEI3 (0x00000200uL) +#define INTC_ICDISER5_ADI (0x00000400uL) +#define INTC_ICDISER5_LMTI (0x00000800uL) +#define INTC_ICDISER5_SSII0 (0x00001000uL) +#define INTC_ICDISER5_SSIRXI0 (0x00002000uL) +#define INTC_ICDISER5_SSITXI0 (0x00004000uL) +#define INTC_ICDISER5_SSII1 (0x00008000uL) +#define INTC_ICDISER5_SSIRXI1 (0x00010000uL) +#define INTC_ICDISER5_SSITXI1 (0x00020000uL) +#define INTC_ICDISER5_SSII2 (0x00040000uL) +#define INTC_ICDISER5_SSIRTI2 (0x00080000uL) +#define INTC_ICDISER5_SSII3 (0x00100000uL) +#define INTC_ICDISER5_SSIRXI3 (0x00200000uL) +#define INTC_ICDISER5_SSITXI3 (0x00400000uL) +#define INTC_ICDISER5_SSII4 (0x00800000uL) +#define INTC_ICDISER5_SSIRTI4 (0x01000000uL) +#define INTC_ICDISER5_SSII5 (0x02000000uL) +#define INTC_ICDISER5_SSIRXI5 (0x04000000uL) +#define INTC_ICDISER5_SSITXI5 (0x08000000uL) +#define INTC_ICDISER5_SPDIFI (0x10000000uL) +#define INTC_ICDISER5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDISER5_INTIICRI0 (0x40000000uL) +#define INTC_ICDISER5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDISER6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDISER6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDISER6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDISER6_INTIICALI0 (0x00000008uL) +#define INTC_ICDISER6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDISER6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDISER6_INTIICRI1 (0x00000040uL) +#define INTC_ICDISER6_INTIICTI1 (0x00000080uL) +#define INTC_ICDISER6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDISER6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDISER6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDISER6_INTIICALI1 (0x00000800uL) +#define INTC_ICDISER6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDISER6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDISER6_INTIICRI2 (0x00004000uL) +#define INTC_ICDISER6_INTIICTI2 (0x00008000uL) +#define INTC_ICDISER6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDISER6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDISER6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDISER6_INTIICALI2 (0x00080000uL) +#define INTC_ICDISER6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDISER6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDISER6_INTIICRI3 (0x00400000uL) +#define INTC_ICDISER6_INTIICTI3 (0x00800000uL) +#define INTC_ICDISER6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDISER6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDISER6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDISER6_INTIICALI3 (0x08000000uL) +#define INTC_ICDISER6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDISER6_BRI0 (0x20000000uL) +#define INTC_ICDISER6_ERI0 (0x40000000uL) +#define INTC_ICDISER6_RXI0 (0x80000000uL) + +#define INTC_ICDISER7_TXI0 (0x00000001uL) +#define INTC_ICDISER7_BRI1 (0x00000002uL) +#define INTC_ICDISER7_ERI1 (0x00000004uL) +#define INTC_ICDISER7_RXI1 (0x00000008uL) +#define INTC_ICDISER7_TXI1 (0x00000010uL) +#define INTC_ICDISER7_BRI2 (0x00000020uL) +#define INTC_ICDISER7_ERI2 (0x00000040uL) +#define INTC_ICDISER7_RXI2 (0x00000080uL) +#define INTC_ICDISER7_TXI2 (0x00000100uL) +#define INTC_ICDISER7_BRI3 (0x00000200uL) +#define INTC_ICDISER7_ERI3 (0x00000400uL) +#define INTC_ICDISER7_RXI3 (0x00000800uL) +#define INTC_ICDISER7_TXI3 (0x00001000uL) +#define INTC_ICDISER7_BRI4 (0x00002000uL) +#define INTC_ICDISER7_ERI4 (0x00004000uL) +#define INTC_ICDISER7_RXI4 (0x00008000uL) +#define INTC_ICDISER7_TXI4 (0x00010000uL) +#define INTC_ICDISER7_BRI5 (0x00020000uL) +#define INTC_ICDISER7_ERI5 (0x00040000uL) +#define INTC_ICDISER7_RXI5 (0x00080000uL) +#define INTC_ICDISER7_TXI5 (0x00100000uL) +#define INTC_ICDISER7_BRI6 (0x00200000uL) +#define INTC_ICDISER7_ERI6 (0x00400000uL) +#define INTC_ICDISER7_RXI6 (0x00800000uL) +#define INTC_ICDISER7_TXI6 (0x01000000uL) +#define INTC_ICDISER7_BRI7 (0x02000000uL) +#define INTC_ICDISER7_ERI7 (0x04000000uL) +#define INTC_ICDISER7_RXI7 (0x08000000uL) +#define INTC_ICDISER7_TXI7 (0x10000000uL) +#define INTC_ICDISER7_INTRCANGERR (0x20000000uL) +#define INTC_ICDISER7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDISER7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDISER8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDISER8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDISER8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDISER8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDISER8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDISER8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDISER8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDISER8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDISER8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDISER8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDISER8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDISER8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDISER8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDISER8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDISER8_SPEI0 (0x00004000uL) +#define INTC_ICDISER8_SPRI0 (0x00008000uL) +#define INTC_ICDISER8_SPTI0 (0x00010000uL) +#define INTC_ICDISER8_SPEI1 (0x00020000uL) +#define INTC_ICDISER8_SPRI1 (0x00040000uL) +#define INTC_ICDISER8_SPTI1 (0x00080000uL) +#define INTC_ICDISER8_SPEI2 (0x00100000uL) +#define INTC_ICDISER8_SPRI2 (0x00200000uL) +#define INTC_ICDISER8_SPTI2 (0x00400000uL) +#define INTC_ICDISER8_SPEI3 (0x00800000uL) +#define INTC_ICDISER8_SPRI3 (0x01000000uL) +#define INTC_ICDISER8_SPTI3 (0x02000000uL) +#define INTC_ICDISER8_SPEI4 (0x04000000uL) +#define INTC_ICDISER8_SPRI4 (0x08000000uL) +#define INTC_ICDISER8_SPTI4 (0x10000000uL) +#define INTC_ICDISER8_IEBBTD (0x20000000uL) +#define INTC_ICDISER8_IEBBTERR (0x40000000uL) +#define INTC_ICDISER8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDISER9_IEBBTV (0x00000001uL) +#define INTC_ICDISER9_ISY (0x00000002uL) +#define INTC_ICDISER9_IERR (0x00000004uL) +#define INTC_ICDISER9_ITARG (0x00000008uL) +#define INTC_ICDISER9_ISEC (0x00000010uL) +#define INTC_ICDISER9_IBUF (0x00000020uL) +#define INTC_ICDISER9_IREADY (0x00000040uL) +#define INTC_ICDISER9_FLSTE (0x00000080uL) +#define INTC_ICDISER9_FLTENDI (0x00000100uL) +#define INTC_ICDISER9_FLTREQ0I (0x00000200uL) +#define INTC_ICDISER9_FLTREQ1I (0x00000400uL) +#define INTC_ICDISER9_MMC0 (0x00000800uL) +#define INTC_ICDISER9_MMC1 (0x00001000uL) +#define INTC_ICDISER9_MMC2 (0x00002000uL) +#define INTC_ICDISER9_SDHI0_3 (0x00004000uL) +#define INTC_ICDISER9_SDHI0_0 (0x00008000uL) +#define INTC_ICDISER9_SDHI0_1 (0x00010000uL) +#define INTC_ICDISER9_SDHI1_3 (0x00020000uL) +#define INTC_ICDISER9_SDHI1_0 (0x00040000uL) +#define INTC_ICDISER9_SDHI1_1 (0x00080000uL) +#define INTC_ICDISER9_ARM (0x00100000uL) +#define INTC_ICDISER9_PRD (0x00200000uL) +#define INTC_ICDISER9_CUP (0x00400000uL) +#define INTC_ICDISER9_SCUAI0 (0x00800000uL) +#define INTC_ICDISER9_SCUAI1 (0x01000000uL) +#define INTC_ICDISER9_SCUFDI0 (0x02000000uL) +#define INTC_ICDISER9_SCUFDI1 (0x04000000uL) +#define INTC_ICDISER9_SCUFDI2 (0x08000000uL) +#define INTC_ICDISER9_SCUFDI3 (0x10000000uL) +#define INTC_ICDISER9_SCUFUI0 (0x20000000uL) +#define INTC_ICDISER9_SCUFUI1 (0x40000000uL) +#define INTC_ICDISER9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDISER10_SCUFUI3 (0x00000001uL) +#define INTC_ICDISER10_SCUDVI0 (0x00000002uL) +#define INTC_ICDISER10_SCUDVI1 (0x00000004uL) +#define INTC_ICDISER10_SCUDVI2 (0x00000008uL) +#define INTC_ICDISER10_SCUDVI3 (0x00000010uL) +#define INTC_ICDISER10_MLB_CINT (0x00000020uL) +#define INTC_ICDISER10_MLB_SINT (0x00000040uL) +#define INTC_ICDISER10_DRC0 (0x00000080uL) +#define INTC_ICDISER10_DRC1 (0x00000100uL) +#define INTC_ICDISER10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDISER10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDISER10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDISER10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDISER10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDISER10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDISER10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDISER10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDISER10_ERI0 (0x08000000uL) +#define INTC_ICDISER10_RXI0 (0x10000000uL) +#define INTC_ICDISER10_TXI0 (0x20000000uL) +#define INTC_ICDISER10_TEI0 (0x40000000uL) +#define INTC_ICDISER10_ERI1 (0x80000000uL) + +#define INTC_ICDISER11_RXI1 (0x00000001uL) +#define INTC_ICDISER11_TXI1 (0x00000002uL) +#define INTC_ICDISER11_TEI1 (0x00000004uL) +#define INTC_ICDISER11_AVBI_DATA (0x00000008uL) +#define INTC_ICDISER11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDISER11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDISER11_AVBI_MAC (0x00000040uL) +#define INTC_ICDISER11_ETHERI (0x00000080uL) +#define INTC_ICDISER11_CEUI (0x00001000uL) +#define INTC_ICDISER11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDISER11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDISER11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDISER12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDISER12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDISER12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDISER12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDISER12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDISER12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDISER12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDISER12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDISER12_PRRI (0x00000100uL) +#define INTC_ICDISER12_IFEI0 (0x00000200uL) +#define INTC_ICDISER12_OFFI0 (0x00000400uL) +#define INTC_ICDISER12_PFVEI0 (0x00000800uL) +#define INTC_ICDISER12_IFEI1 (0x00001000uL) +#define INTC_ICDISER12_OFFI1 (0x00002000uL) +#define INTC_ICDISER12_PFVEI1 (0x00004000uL) + +#define INTC_ICDISER13_TINT0 (0x00000001uL) +#define INTC_ICDISER13_TINT1 (0x00000002uL) +#define INTC_ICDISER13_TINT2 (0x00000004uL) +#define INTC_ICDISER13_TINT3 (0x00000008uL) +#define INTC_ICDISER13_TINT4 (0x00000010uL) +#define INTC_ICDISER13_TINT5 (0x00000020uL) +#define INTC_ICDISER13_TINT6 (0x00000040uL) +#define INTC_ICDISER13_TINT7 (0x00000080uL) +#define INTC_ICDISER13_TINT8 (0x00000100uL) +#define INTC_ICDISER13_TINT9 (0x00000200uL) +#define INTC_ICDISER13_TINT10 (0x00000400uL) +#define INTC_ICDISER13_TINT11 (0x00000800uL) +#define INTC_ICDISER13_TINT12 (0x00001000uL) +#define INTC_ICDISER13_TINT13 (0x00002000uL) +#define INTC_ICDISER13_TINT14 (0x00004000uL) +#define INTC_ICDISER13_TINT15 (0x00008000uL) +#define INTC_ICDISER13_TINT16 (0x00010000uL) +#define INTC_ICDISER13_TINT17 (0x00020000uL) +#define INTC_ICDISER13_TINT18 (0x00040000uL) +#define INTC_ICDISER13_TINT19 (0x00080000uL) +#define INTC_ICDISER13_TINT20 (0x00100000uL) +#define INTC_ICDISER13_TINT21 (0x00200000uL) +#define INTC_ICDISER13_TINT22 (0x00400000uL) +#define INTC_ICDISER13_TINT23 (0x00800000uL) +#define INTC_ICDISER13_TINT24 (0x01000000uL) +#define INTC_ICDISER13_TINT25 (0x02000000uL) +#define INTC_ICDISER13_TINT26 (0x04000000uL) +#define INTC_ICDISER13_TINT27 (0x08000000uL) +#define INTC_ICDISER13_TINT28 (0x10000000uL) +#define INTC_ICDISER13_TINT29 (0x20000000uL) +#define INTC_ICDISER13_TINT30 (0x40000000uL) +#define INTC_ICDISER13_TINT31 (0x80000000uL) + +#define INTC_ICDISER14_TINT32 (0x00000001uL) +#define INTC_ICDISER14_TINT33 (0x00000002uL) +#define INTC_ICDISER14_TINT34 (0x00000004uL) +#define INTC_ICDISER14_TINT35 (0x00000008uL) +#define INTC_ICDISER14_TINT36 (0x00000010uL) +#define INTC_ICDISER14_TINT37 (0x00000020uL) +#define INTC_ICDISER14_TINT38 (0x00000040uL) +#define INTC_ICDISER14_TINT39 (0x00000080uL) +#define INTC_ICDISER14_TINT40 (0x00000100uL) +#define INTC_ICDISER14_TINT41 (0x00000200uL) +#define INTC_ICDISER14_TINT42 (0x00000400uL) +#define INTC_ICDISER14_TINT43 (0x00000800uL) +#define INTC_ICDISER14_TINT44 (0x00001000uL) +#define INTC_ICDISER14_TINT45 (0x00002000uL) +#define INTC_ICDISER14_TINT46 (0x00004000uL) +#define INTC_ICDISER14_TINT47 (0x00008000uL) +#define INTC_ICDISER14_TINT48 (0x00010000uL) +#define INTC_ICDISER14_TINT49 (0x00020000uL) +#define INTC_ICDISER14_TINT50 (0x00040000uL) +#define INTC_ICDISER14_TINT51 (0x00080000uL) +#define INTC_ICDISER14_TINT52 (0x00100000uL) +#define INTC_ICDISER14_TINT53 (0x00200000uL) +#define INTC_ICDISER14_TINT54 (0x00400000uL) +#define INTC_ICDISER14_TINT55 (0x00800000uL) +#define INTC_ICDISER14_TINT56 (0x01000000uL) +#define INTC_ICDISER14_TINT57 (0x02000000uL) +#define INTC_ICDISER14_TINT58 (0x04000000uL) +#define INTC_ICDISER14_TINT59 (0x08000000uL) +#define INTC_ICDISER14_TINT60 (0x10000000uL) +#define INTC_ICDISER14_TINT61 (0x20000000uL) +#define INTC_ICDISER14_TINT62 (0x40000000uL) +#define INTC_ICDISER14_TINT63 (0x80000000uL) + +#define INTC_ICDISER15_TINT64 (0x00000001uL) +#define INTC_ICDISER15_TINT65 (0x00000002uL) +#define INTC_ICDISER15_TINT66 (0x00000004uL) +#define INTC_ICDISER15_TINT67 (0x00000008uL) +#define INTC_ICDISER15_TINT68 (0x00000010uL) +#define INTC_ICDISER15_TINT69 (0x00000020uL) +#define INTC_ICDISER15_TINT70 (0x00000040uL) +#define INTC_ICDISER15_TINT71 (0x00000080uL) +#define INTC_ICDISER15_TINT72 (0x00000100uL) +#define INTC_ICDISER15_TINT73 (0x00000200uL) +#define INTC_ICDISER15_TINT74 (0x00000400uL) +#define INTC_ICDISER15_TINT75 (0x00000800uL) +#define INTC_ICDISER15_TINT76 (0x00001000uL) +#define INTC_ICDISER15_TINT77 (0x00002000uL) +#define INTC_ICDISER15_TINT78 (0x00004000uL) +#define INTC_ICDISER15_TINT79 (0x00008000uL) +#define INTC_ICDISER15_TINT80 (0x00010000uL) +#define INTC_ICDISER15_TINT81 (0x00020000uL) +#define INTC_ICDISER15_TINT82 (0x00040000uL) +#define INTC_ICDISER15_TINT83 (0x00080000uL) +#define INTC_ICDISER15_TINT84 (0x00100000uL) +#define INTC_ICDISER15_TINT85 (0x00200000uL) +#define INTC_ICDISER15_TINT86 (0x00400000uL) +#define INTC_ICDISER15_TINT87 (0x00800000uL) +#define INTC_ICDISER15_TINT88 (0x01000000uL) +#define INTC_ICDISER15_TINT89 (0x02000000uL) +#define INTC_ICDISER15_TINT90 (0x04000000uL) +#define INTC_ICDISER15_TINT91 (0x08000000uL) +#define INTC_ICDISER15_TINT92 (0x10000000uL) +#define INTC_ICDISER15_TINT93 (0x20000000uL) +#define INTC_ICDISER15_TINT94 (0x40000000uL) +#define INTC_ICDISER15_TINT95 (0x80000000uL) + +#define INTC_ICDISER16_TINT96 (0x00000001uL) +#define INTC_ICDISER16_TINT97 (0x00000002uL) +#define INTC_ICDISER16_TINT98 (0x00000004uL) +#define INTC_ICDISER16_TINT99 (0x00000008uL) +#define INTC_ICDISER16_TINT100 (0x00000010uL) +#define INTC_ICDISER16_TINT101 (0x00000020uL) +#define INTC_ICDISER16_TINT102 (0x00000040uL) +#define INTC_ICDISER16_TINT103 (0x00000080uL) +#define INTC_ICDISER16_TINT104 (0x00000100uL) +#define INTC_ICDISER16_TINT105 (0x00000200uL) +#define INTC_ICDISER16_TINT106 (0x00000400uL) +#define INTC_ICDISER16_TINT107 (0x00000800uL) +#define INTC_ICDISER16_TINT108 (0x00001000uL) +#define INTC_ICDISER16_TINT109 (0x00002000uL) +#define INTC_ICDISER16_TINT110 (0x00004000uL) +#define INTC_ICDISER16_TINT111 (0x00008000uL) +#define INTC_ICDISER16_TINT112 (0x00010000uL) +#define INTC_ICDISER16_TINT113 (0x00020000uL) +#define INTC_ICDISER16_TINT114 (0x00040000uL) +#define INTC_ICDISER16_TINT115 (0x00080000uL) +#define INTC_ICDISER16_TINT116 (0x00100000uL) +#define INTC_ICDISER16_TINT117 (0x00200000uL) +#define INTC_ICDISER16_TINT118 (0x00400000uL) +#define INTC_ICDISER16_TINT119 (0x00800000uL) +#define INTC_ICDISER16_TINT120 (0x01000000uL) +#define INTC_ICDISER16_TINT121 (0x02000000uL) +#define INTC_ICDISER16_TINT122 (0x04000000uL) +#define INTC_ICDISER16_TINT123 (0x08000000uL) +#define INTC_ICDISER16_TINT124 (0x10000000uL) +#define INTC_ICDISER16_TINT125 (0x20000000uL) +#define INTC_ICDISER16_TINT126 (0x40000000uL) +#define INTC_ICDISER16_TINT127 (0x80000000uL) + +#define INTC_ICDISER17_TINT128 (0x00000001uL) +#define INTC_ICDISER17_TINT129 (0x00000002uL) +#define INTC_ICDISER17_TINT130 (0x00000004uL) +#define INTC_ICDISER17_TINT131 (0x00000008uL) +#define INTC_ICDISER17_TINT132 (0x00000010uL) +#define INTC_ICDISER17_TINT133 (0x00000020uL) +#define INTC_ICDISER17_TINT134 (0x00000040uL) +#define INTC_ICDISER17_TINT135 (0x00000080uL) +#define INTC_ICDISER17_TINT136 (0x00000100uL) +#define INTC_ICDISER17_TINT137 (0x00000200uL) +#define INTC_ICDISER17_TINT138 (0x00000400uL) +#define INTC_ICDISER17_TINT139 (0x00000800uL) +#define INTC_ICDISER17_TINT140 (0x00001000uL) +#define INTC_ICDISER17_TINT141 (0x00002000uL) +#define INTC_ICDISER17_TINT142 (0x00004000uL) +#define INTC_ICDISER17_TINT143 (0x00008000uL) +#define INTC_ICDISER17_TINT144 (0x00010000uL) +#define INTC_ICDISER17_TINT145 (0x00020000uL) +#define INTC_ICDISER17_TINT146 (0x00040000uL) +#define INTC_ICDISER17_TINT147 (0x00080000uL) +#define INTC_ICDISER17_TINT148 (0x00100000uL) +#define INTC_ICDISER17_TINT149 (0x00200000uL) +#define INTC_ICDISER17_TINT150 (0x00400000uL) +#define INTC_ICDISER17_TINT151 (0x00800000uL) +#define INTC_ICDISER17_TINT152 (0x01000000uL) +#define INTC_ICDISER17_TINT153 (0x02000000uL) +#define INTC_ICDISER17_TINT154 (0x04000000uL) +#define INTC_ICDISER17_TINT155 (0x08000000uL) +#define INTC_ICDISER17_TINT156 (0x10000000uL) +#define INTC_ICDISER17_TINT157 (0x20000000uL) +#define INTC_ICDISER17_TINT158 (0x40000000uL) +#define INTC_ICDISER17_TINT159 (0x80000000uL) + +#define INTC_ICDISER18_TINT160 (0x00000001uL) +#define INTC_ICDISER18_TINT161 (0x00000002uL) +#define INTC_ICDISER18_TINT162 (0x00000004uL) +#define INTC_ICDISER18_TINT163 (0x00000008uL) +#define INTC_ICDISER18_TINT164 (0x00000010uL) +#define INTC_ICDISER18_TINT165 (0x00000020uL) +#define INTC_ICDISER18_TINT166 (0x00000040uL) +#define INTC_ICDISER18_TINT167 (0x00000080uL) +#define INTC_ICDISER18_TINT168 (0x00000100uL) +#define INTC_ICDISER18_TINT169 (0x00000200uL) +#define INTC_ICDISER18_TINT170 (0x00000400uL) + +#define INTC_ICDICER0_SW0 (0x00000001uL) +#define INTC_ICDICER0_SW1 (0x00000002uL) +#define INTC_ICDICER0_SW2 (0x00000004uL) +#define INTC_ICDICER0_SW3 (0x00000008uL) +#define INTC_ICDICER0_SW4 (0x00000010uL) +#define INTC_ICDICER0_SW5 (0x00000020uL) +#define INTC_ICDICER0_SW6 (0x00000040uL) +#define INTC_ICDICER0_SW7 (0x00000080uL) +#define INTC_ICDICER0_SW8 (0x00000100uL) +#define INTC_ICDICER0_SW9 (0x00000200uL) +#define INTC_ICDICER0_SW10 (0x00000400uL) +#define INTC_ICDICER0_SW11 (0x00000800uL) +#define INTC_ICDICER0_SW12 (0x00001000uL) +#define INTC_ICDICER0_SW13 (0x00002000uL) +#define INTC_ICDICER0_SW14 (0x00004000uL) +#define INTC_ICDICER0_SW15 (0x00008000uL) +#define INTC_ICDICER0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDICER0_COMMRX0 (0x00020000uL) +#define INTC_ICDICER0_COMMTX0 (0x00040000uL) +#define INTC_ICDICER0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDICER1_IRQ0 (0x00000001uL) +#define INTC_ICDICER1_IRQ1 (0x00000002uL) +#define INTC_ICDICER1_IRQ2 (0x00000004uL) +#define INTC_ICDICER1_IRQ3 (0x00000008uL) +#define INTC_ICDICER1_IRQ4 (0x00000010uL) +#define INTC_ICDICER1_IRQ5 (0x00000020uL) +#define INTC_ICDICER1_IRQ6 (0x00000040uL) +#define INTC_ICDICER1_IRQ7 (0x00000080uL) +#define INTC_ICDICER1_PL310ERR (0x00000100uL) +#define INTC_ICDICER1_DMAINT0 (0x00000200uL) +#define INTC_ICDICER1_DMAINT1 (0x00000400uL) +#define INTC_ICDICER1_DMAINT2 (0x00000800uL) +#define INTC_ICDICER1_DMAINT3 (0x00001000uL) +#define INTC_ICDICER1_DMAINT4 (0x00002000uL) +#define INTC_ICDICER1_DMAINT5 (0x00004000uL) +#define INTC_ICDICER1_DMAINT6 (0x00008000uL) +#define INTC_ICDICER1_DMAINT7 (0x00010000uL) +#define INTC_ICDICER1_DMAINT8 (0x00020000uL) +#define INTC_ICDICER1_DMAINT9 (0x00040000uL) +#define INTC_ICDICER1_DMAINT10 (0x00080000uL) +#define INTC_ICDICER1_DMAINT11 (0x00100000uL) +#define INTC_ICDICER1_DMAINT12 (0x00200000uL) +#define INTC_ICDICER1_DMAINT13 (0x00400000uL) +#define INTC_ICDICER1_DMAINT14 (0x00800000uL) +#define INTC_ICDICER1_DMAINT15 (0x01000000uL) +#define INTC_ICDICER1_DMAERR (0x02000000uL) + +#define INTC_ICDICER2_USBI0 (0x00000200uL) +#define INTC_ICDICER2_USBI1 (0x00000400uL) +#define INTC_ICDICER2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDICER2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDICER2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDICER2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDICER2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDICER2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDICER2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDICER2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDICER2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDICER2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDICER2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDICER2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDICER2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDICER2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDICER2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDICER2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDICER2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDICER2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDICER2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDICER2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDICER2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDICER3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDICER3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDICER3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDICER3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDICER3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDICER3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDICER3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDICER3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDICER3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDICER3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDICER3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDICER3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDICER3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDICER3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDICER3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDICER3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDICER3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDICER3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDICER3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDICER3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDICER3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDICER3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDICER3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDICER3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDICER3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDICER3_IMRDI (0x08000000uL) +#define INTC_ICDICER3_IMR2I0 (0x10000000uL) +#define INTC_ICDICER3_IMR2I1 (0x20000000uL) +#define INTC_ICDICER3_JEDI (0x40000000uL) +#define INTC_ICDICER3_JDTI (0x80000000uL) + +#define INTC_ICDICER4_CMP0 (0x00000001uL) +#define INTC_ICDICER4_CMP1 (0x00000002uL) +#define INTC_ICDICER4_INT0 (0x00000004uL) +#define INTC_ICDICER4_INT1 (0x00000008uL) +#define INTC_ICDICER4_INT2 (0x00000010uL) +#define INTC_ICDICER4_INT3 (0x00000020uL) +#define INTC_ICDICER4_OSTM0TINT (0x00000040uL) +#define INTC_ICDICER4_OSTM1TINT (0x00000080uL) +#define INTC_ICDICER4_CMI (0x00000100uL) +#define INTC_ICDICER4_WTOUT (0x00000200uL) +#define INTC_ICDICER4_ITI (0x00000400uL) +#define INTC_ICDICER4_TGI0A (0x00000800uL) +#define INTC_ICDICER4_TGI0B (0x00001000uL) +#define INTC_ICDICER4_TGI0C (0x00002000uL) +#define INTC_ICDICER4_TGI0D (0x00004000uL) +#define INTC_ICDICER4_TGI0V (0x00008000uL) +#define INTC_ICDICER4_TGI0E (0x00010000uL) +#define INTC_ICDICER4_TGI0F (0x00020000uL) +#define INTC_ICDICER4_TGI1A (0x00040000uL) +#define INTC_ICDICER4_TGI1B (0x00080000uL) +#define INTC_ICDICER4_TGI1V (0x00100000uL) +#define INTC_ICDICER4_TGI1U (0x00200000uL) +#define INTC_ICDICER4_TGI2A (0x00400000uL) +#define INTC_ICDICER4_TGI2B (0x00800000uL) +#define INTC_ICDICER4_TGI2V (0x01000000uL) +#define INTC_ICDICER4_TGI2U (0x02000000uL) +#define INTC_ICDICER4_TGI3A (0x04000000uL) +#define INTC_ICDICER4_TGI3B (0x08000000uL) +#define INTC_ICDICER4_TGI3C (0x10000000uL) +#define INTC_ICDICER4_TGI3D (0x20000000uL) +#define INTC_ICDICER4_TGI3V (0x40000000uL) +#define INTC_ICDICER4_TGI4A (0x80000000uL) + +#define INTC_ICDICER5_TGI4B (0x00000001uL) +#define INTC_ICDICER5_TGI4C (0x00000002uL) +#define INTC_ICDICER5_TGI4D (0x00000004uL) +#define INTC_ICDICER5_TGI4V (0x00000008uL) +#define INTC_ICDICER5_CMI1 (0x00000010uL) +#define INTC_ICDICER5_CMI2 (0x00000020uL) +#define INTC_ICDICER5_SGDEI0 (0x00000040uL) +#define INTC_ICDICER5_SGDEI1 (0x00000080uL) +#define INTC_ICDICER5_SGDEI2 (0x00000100uL) +#define INTC_ICDICER5_SGDEI3 (0x00000200uL) +#define INTC_ICDICER5_ADI (0x00000400uL) +#define INTC_ICDICER5_LMTI (0x00000800uL) +#define INTC_ICDICER5_SSII0 (0x00001000uL) +#define INTC_ICDICER5_SSIRXI0 (0x00002000uL) +#define INTC_ICDICER5_SSITXI0 (0x00004000uL) +#define INTC_ICDICER5_SSII1 (0x00008000uL) +#define INTC_ICDICER5_SSIRXI1 (0x00010000uL) +#define INTC_ICDICER5_SSITXI1 (0x00020000uL) +#define INTC_ICDICER5_SSII2 (0x00040000uL) +#define INTC_ICDICER5_SSIRTI2 (0x00080000uL) +#define INTC_ICDICER5_SSII3 (0x00100000uL) +#define INTC_ICDICER5_SSIRXI3 (0x00200000uL) +#define INTC_ICDICER5_SSITXI3 (0x00400000uL) +#define INTC_ICDICER5_SSII4 (0x00800000uL) +#define INTC_ICDICER5_SSIRTI4 (0x01000000uL) +#define INTC_ICDICER5_SSII5 (0x02000000uL) +#define INTC_ICDICER5_SSIRXI5 (0x04000000uL) +#define INTC_ICDICER5_SSITXI5 (0x08000000uL) +#define INTC_ICDICER5_SPDIFI (0x10000000uL) +#define INTC_ICDICER5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDICER5_INTIICRI0 (0x40000000uL) +#define INTC_ICDICER5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDICER6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDICER6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDICER6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDICER6_INTIICALI0 (0x00000008uL) +#define INTC_ICDICER6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDICER6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDICER6_INTIICRI1 (0x00000040uL) +#define INTC_ICDICER6_INTIICTI1 (0x00000080uL) +#define INTC_ICDICER6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDICER6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDICER6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDICER6_INTIICALI1 (0x00000800uL) +#define INTC_ICDICER6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDICER6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDICER6_INTIICRI2 (0x00004000uL) +#define INTC_ICDICER6_INTIICTI2 (0x00008000uL) +#define INTC_ICDICER6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDICER6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDICER6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDICER6_INTIICALI2 (0x00080000uL) +#define INTC_ICDICER6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDICER6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDICER6_INTIICRI3 (0x00400000uL) +#define INTC_ICDICER6_INTIICTI3 (0x00800000uL) +#define INTC_ICDICER6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDICER6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDICER6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDICER6_INTIICALI3 (0x08000000uL) +#define INTC_ICDICER6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDICER6_BRI0 (0x20000000uL) +#define INTC_ICDICER6_ERI0 (0x40000000uL) +#define INTC_ICDICER6_RXI0 (0x80000000uL) + +#define INTC_ICDICER7_TXI0 (0x00000001uL) +#define INTC_ICDICER7_BRI1 (0x00000002uL) +#define INTC_ICDICER7_ERI1 (0x00000004uL) +#define INTC_ICDICER7_RXI1 (0x00000008uL) +#define INTC_ICDICER7_TXI1 (0x00000010uL) +#define INTC_ICDICER7_BRI2 (0x00000020uL) +#define INTC_ICDICER7_ERI2 (0x00000040uL) +#define INTC_ICDICER7_RXI2 (0x00000080uL) +#define INTC_ICDICER7_TXI2 (0x00000100uL) +#define INTC_ICDICER7_BRI3 (0x00000200uL) +#define INTC_ICDICER7_ERI3 (0x00000400uL) +#define INTC_ICDICER7_RXI3 (0x00000800uL) +#define INTC_ICDICER7_TXI3 (0x00001000uL) +#define INTC_ICDICER7_BRI4 (0x00002000uL) +#define INTC_ICDICER7_ERI4 (0x00004000uL) +#define INTC_ICDICER7_RXI4 (0x00008000uL) +#define INTC_ICDICER7_TXI4 (0x00010000uL) +#define INTC_ICDICER7_BRI5 (0x00020000uL) +#define INTC_ICDICER7_ERI5 (0x00040000uL) +#define INTC_ICDICER7_RXI5 (0x00080000uL) +#define INTC_ICDICER7_TXI5 (0x00100000uL) +#define INTC_ICDICER7_BRI6 (0x00200000uL) +#define INTC_ICDICER7_ERI6 (0x00400000uL) +#define INTC_ICDICER7_RXI6 (0x00800000uL) +#define INTC_ICDICER7_TXI6 (0x01000000uL) +#define INTC_ICDICER7_BRI7 (0x02000000uL) +#define INTC_ICDICER7_ERI7 (0x04000000uL) +#define INTC_ICDICER7_RXI7 (0x08000000uL) +#define INTC_ICDICER7_TXI7 (0x10000000uL) +#define INTC_ICDICER7_INTRCANGERR (0x20000000uL) +#define INTC_ICDICER7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDICER7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDICER8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDICER8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDICER8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDICER8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDICER8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDICER8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDICER8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDICER8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDICER8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDICER8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDICER8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDICER8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDICER8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDICER8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDICER8_SPEI0 (0x00004000uL) +#define INTC_ICDICER8_SPRI0 (0x00008000uL) +#define INTC_ICDICER8_SPTI0 (0x00010000uL) +#define INTC_ICDICER8_SPEI1 (0x00020000uL) +#define INTC_ICDICER8_SPRI1 (0x00040000uL) +#define INTC_ICDICER8_SPTI1 (0x00080000uL) +#define INTC_ICDICER8_SPEI2 (0x00100000uL) +#define INTC_ICDICER8_SPRI2 (0x00200000uL) +#define INTC_ICDICER8_SPTI2 (0x00400000uL) +#define INTC_ICDICER8_SPEI3 (0x00800000uL) +#define INTC_ICDICER8_SPRI3 (0x01000000uL) +#define INTC_ICDICER8_SPTI3 (0x02000000uL) +#define INTC_ICDICER8_SPEI4 (0x04000000uL) +#define INTC_ICDICER8_SPRI4 (0x08000000uL) +#define INTC_ICDICER8_SPTI4 (0x10000000uL) +#define INTC_ICDICER8_IEBBTD (0x20000000uL) +#define INTC_ICDICER8_IEBBTERR (0x40000000uL) +#define INTC_ICDICER8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDICER9_IEBBTV (0x00000001uL) +#define INTC_ICDICER9_ISY (0x00000002uL) +#define INTC_ICDICER9_IERR (0x00000004uL) +#define INTC_ICDICER9_ITARG (0x00000008uL) +#define INTC_ICDICER9_ISEC (0x00000010uL) +#define INTC_ICDICER9_IBUF (0x00000020uL) +#define INTC_ICDICER9_IREADY (0x00000040uL) +#define INTC_ICDICER9_FLSTE (0x00000080uL) +#define INTC_ICDICER9_FLTENDI (0x00000100uL) +#define INTC_ICDICER9_FLTREQ0I (0x00000200uL) +#define INTC_ICDICER9_FLTREQ1I (0x00000400uL) +#define INTC_ICDICER9_MMC0 (0x00000800uL) +#define INTC_ICDICER9_MMC1 (0x00001000uL) +#define INTC_ICDICER9_MMC2 (0x00002000uL) +#define INTC_ICDICER9_SDHI0_3 (0x00004000uL) +#define INTC_ICDICER9_SDHI0_0 (0x00008000uL) +#define INTC_ICDICER9_SDHI0_1 (0x00010000uL) +#define INTC_ICDICER9_SDHI1_3 (0x00020000uL) +#define INTC_ICDICER9_SDHI1_0 (0x00040000uL) +#define INTC_ICDICER9_SDHI1_1 (0x00080000uL) +#define INTC_ICDICER9_ARM (0x00100000uL) +#define INTC_ICDICER9_PRD (0x00200000uL) +#define INTC_ICDICER9_CUP (0x00400000uL) +#define INTC_ICDICER9_SCUAI0 (0x00800000uL) +#define INTC_ICDICER9_SCUAI1 (0x01000000uL) +#define INTC_ICDICER9_SCUFDI0 (0x02000000uL) +#define INTC_ICDICER9_SCUFDI1 (0x04000000uL) +#define INTC_ICDICER9_SCUFDI2 (0x08000000uL) +#define INTC_ICDICER9_SCUFDI3 (0x10000000uL) +#define INTC_ICDICER9_SCUFUI0 (0x20000000uL) +#define INTC_ICDICER9_SCUFUI1 (0x40000000uL) +#define INTC_ICDICER9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDICER10_SCUFUI3 (0x00000001uL) +#define INTC_ICDICER10_SCUDVI0 (0x00000002uL) +#define INTC_ICDICER10_SCUDVI1 (0x00000004uL) +#define INTC_ICDICER10_SCUDVI2 (0x00000008uL) +#define INTC_ICDICER10_SCUDVI3 (0x00000010uL) +#define INTC_ICDICER10_MLB_CINT (0x00000020uL) +#define INTC_ICDICER10_MLB_SINT (0x00000040uL) +#define INTC_ICDICER10_DRC0 (0x00000080uL) +#define INTC_ICDICER10_DRC1 (0x00000100uL) +#define INTC_ICDICER10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDICER10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDICER10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDICER10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDICER10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDICER10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDICER10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDICER10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDICER10_ERI0 (0x08000000uL) +#define INTC_ICDICER10_RXI0 (0x10000000uL) +#define INTC_ICDICER10_TXI0 (0x20000000uL) +#define INTC_ICDICER10_TEI0 (0x40000000uL) +#define INTC_ICDICER10_ERI1 (0x80000000uL) + +#define INTC_ICDICER11_RXI1 (0x00000001uL) +#define INTC_ICDICER11_TXI1 (0x00000002uL) +#define INTC_ICDICER11_TEI1 (0x00000004uL) +#define INTC_ICDICER11_AVBI_DATA (0x00000008uL) +#define INTC_ICDICER11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDICER11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDICER11_AVBI_MAC (0x00000040uL) +#define INTC_ICDICER11_ETHERI (0x00000080uL) +#define INTC_ICDICER11_CEUI (0x00001000uL) +#define INTC_ICDICER11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDICER11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDICER11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDICER12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDICER12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDICER12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDICER12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDICER12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDICER12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDICER12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDICER12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDICER12_PRRI (0x00000100uL) +#define INTC_ICDICER12_IFEI0 (0x00000200uL) +#define INTC_ICDICER12_OFFI0 (0x00000400uL) +#define INTC_ICDICER12_PFVEI0 (0x00000800uL) +#define INTC_ICDICER12_IFEI1 (0x00001000uL) +#define INTC_ICDICER12_OFFI1 (0x00002000uL) +#define INTC_ICDICER12_PFVEI1 (0x00004000uL) + +#define INTC_ICDICER13_TINT0 (0x00000001uL) +#define INTC_ICDICER13_TINT1 (0x00000002uL) +#define INTC_ICDICER13_TINT2 (0x00000004uL) +#define INTC_ICDICER13_TINT3 (0x00000008uL) +#define INTC_ICDICER13_TINT4 (0x00000010uL) +#define INTC_ICDICER13_TINT5 (0x00000020uL) +#define INTC_ICDICER13_TINT6 (0x00000040uL) +#define INTC_ICDICER13_TINT7 (0x00000080uL) +#define INTC_ICDICER13_TINT8 (0x00000100uL) +#define INTC_ICDICER13_TINT9 (0x00000200uL) +#define INTC_ICDICER13_TINT10 (0x00000400uL) +#define INTC_ICDICER13_TINT11 (0x00000800uL) +#define INTC_ICDICER13_TINT12 (0x00001000uL) +#define INTC_ICDICER13_TINT13 (0x00002000uL) +#define INTC_ICDICER13_TINT14 (0x00004000uL) +#define INTC_ICDICER13_TINT15 (0x00008000uL) +#define INTC_ICDICER13_TINT16 (0x00010000uL) +#define INTC_ICDICER13_TINT17 (0x00020000uL) +#define INTC_ICDICER13_TINT18 (0x00040000uL) +#define INTC_ICDICER13_TINT19 (0x00080000uL) +#define INTC_ICDICER13_TINT20 (0x00100000uL) +#define INTC_ICDICER13_TINT21 (0x00200000uL) +#define INTC_ICDICER13_TINT22 (0x00400000uL) +#define INTC_ICDICER13_TINT23 (0x00800000uL) +#define INTC_ICDICER13_TINT24 (0x01000000uL) +#define INTC_ICDICER13_TINT25 (0x02000000uL) +#define INTC_ICDICER13_TINT26 (0x04000000uL) +#define INTC_ICDICER13_TINT27 (0x08000000uL) +#define INTC_ICDICER13_TINT28 (0x10000000uL) +#define INTC_ICDICER13_TINT29 (0x20000000uL) +#define INTC_ICDICER13_TINT30 (0x40000000uL) +#define INTC_ICDICER13_TINT31 (0x80000000uL) + +#define INTC_ICDICER14_TINT32 (0x00000001uL) +#define INTC_ICDICER14_TINT33 (0x00000002uL) +#define INTC_ICDICER14_TINT34 (0x00000004uL) +#define INTC_ICDICER14_TINT35 (0x00000008uL) +#define INTC_ICDICER14_TINT36 (0x00000010uL) +#define INTC_ICDICER14_TINT37 (0x00000020uL) +#define INTC_ICDICER14_TINT38 (0x00000040uL) +#define INTC_ICDICER14_TINT39 (0x00000080uL) +#define INTC_ICDICER14_TINT40 (0x00000100uL) +#define INTC_ICDICER14_TINT41 (0x00000200uL) +#define INTC_ICDICER14_TINT42 (0x00000400uL) +#define INTC_ICDICER14_TINT43 (0x00000800uL) +#define INTC_ICDICER14_TINT44 (0x00001000uL) +#define INTC_ICDICER14_TINT45 (0x00002000uL) +#define INTC_ICDICER14_TINT46 (0x00004000uL) +#define INTC_ICDICER14_TINT47 (0x00008000uL) +#define INTC_ICDICER14_TINT48 (0x00010000uL) +#define INTC_ICDICER14_TINT49 (0x00020000uL) +#define INTC_ICDICER14_TINT50 (0x00040000uL) +#define INTC_ICDICER14_TINT51 (0x00080000uL) +#define INTC_ICDICER14_TINT52 (0x00100000uL) +#define INTC_ICDICER14_TINT53 (0x00200000uL) +#define INTC_ICDICER14_TINT54 (0x00400000uL) +#define INTC_ICDICER14_TINT55 (0x00800000uL) +#define INTC_ICDICER14_TINT56 (0x01000000uL) +#define INTC_ICDICER14_TINT57 (0x02000000uL) +#define INTC_ICDICER14_TINT58 (0x04000000uL) +#define INTC_ICDICER14_TINT59 (0x08000000uL) +#define INTC_ICDICER14_TINT60 (0x10000000uL) +#define INTC_ICDICER14_TINT61 (0x20000000uL) +#define INTC_ICDICER14_TINT62 (0x40000000uL) +#define INTC_ICDICER14_TINT63 (0x80000000uL) + +#define INTC_ICDICER15_TINT64 (0x00000001uL) +#define INTC_ICDICER15_TINT65 (0x00000002uL) +#define INTC_ICDICER15_TINT66 (0x00000004uL) +#define INTC_ICDICER15_TINT67 (0x00000008uL) +#define INTC_ICDICER15_TINT68 (0x00000010uL) +#define INTC_ICDICER15_TINT69 (0x00000020uL) +#define INTC_ICDICER15_TINT70 (0x00000040uL) +#define INTC_ICDICER15_TINT71 (0x00000080uL) +#define INTC_ICDICER15_TINT72 (0x00000100uL) +#define INTC_ICDICER15_TINT73 (0x00000200uL) +#define INTC_ICDICER15_TINT74 (0x00000400uL) +#define INTC_ICDICER15_TINT75 (0x00000800uL) +#define INTC_ICDICER15_TINT76 (0x00001000uL) +#define INTC_ICDICER15_TINT77 (0x00002000uL) +#define INTC_ICDICER15_TINT78 (0x00004000uL) +#define INTC_ICDICER15_TINT79 (0x00008000uL) +#define INTC_ICDICER15_TINT80 (0x00010000uL) +#define INTC_ICDICER15_TINT81 (0x00020000uL) +#define INTC_ICDICER15_TINT82 (0x00040000uL) +#define INTC_ICDICER15_TINT83 (0x00080000uL) +#define INTC_ICDICER15_TINT84 (0x00100000uL) +#define INTC_ICDICER15_TINT85 (0x00200000uL) +#define INTC_ICDICER15_TINT86 (0x00400000uL) +#define INTC_ICDICER15_TINT87 (0x00800000uL) +#define INTC_ICDICER15_TINT88 (0x01000000uL) +#define INTC_ICDICER15_TINT89 (0x02000000uL) +#define INTC_ICDICER15_TINT90 (0x04000000uL) +#define INTC_ICDICER15_TINT91 (0x08000000uL) +#define INTC_ICDICER15_TINT92 (0x10000000uL) +#define INTC_ICDICER15_TINT93 (0x20000000uL) +#define INTC_ICDICER15_TINT94 (0x40000000uL) +#define INTC_ICDICER15_TINT95 (0x80000000uL) + +#define INTC_ICDICER16_TINT96 (0x00000001uL) +#define INTC_ICDICER16_TINT97 (0x00000002uL) +#define INTC_ICDICER16_TINT98 (0x00000004uL) +#define INTC_ICDICER16_TINT99 (0x00000008uL) +#define INTC_ICDICER16_TINT100 (0x00000010uL) +#define INTC_ICDICER16_TINT101 (0x00000020uL) +#define INTC_ICDICER16_TINT102 (0x00000040uL) +#define INTC_ICDICER16_TINT103 (0x00000080uL) +#define INTC_ICDICER16_TINT104 (0x00000100uL) +#define INTC_ICDICER16_TINT105 (0x00000200uL) +#define INTC_ICDICER16_TINT106 (0x00000400uL) +#define INTC_ICDICER16_TINT107 (0x00000800uL) +#define INTC_ICDICER16_TINT108 (0x00001000uL) +#define INTC_ICDICER16_TINT109 (0x00002000uL) +#define INTC_ICDICER16_TINT110 (0x00004000uL) +#define INTC_ICDICER16_TINT111 (0x00008000uL) +#define INTC_ICDICER16_TINT112 (0x00010000uL) +#define INTC_ICDICER16_TINT113 (0x00020000uL) +#define INTC_ICDICER16_TINT114 (0x00040000uL) +#define INTC_ICDICER16_TINT115 (0x00080000uL) +#define INTC_ICDICER16_TINT116 (0x00100000uL) +#define INTC_ICDICER16_TINT117 (0x00200000uL) +#define INTC_ICDICER16_TINT118 (0x00400000uL) +#define INTC_ICDICER16_TINT119 (0x00800000uL) +#define INTC_ICDICER16_TINT120 (0x01000000uL) +#define INTC_ICDICER16_TINT121 (0x02000000uL) +#define INTC_ICDICER16_TINT122 (0x04000000uL) +#define INTC_ICDICER16_TINT123 (0x08000000uL) +#define INTC_ICDICER16_TINT124 (0x10000000uL) +#define INTC_ICDICER16_TINT125 (0x20000000uL) +#define INTC_ICDICER16_TINT126 (0x40000000uL) +#define INTC_ICDICER16_TINT127 (0x80000000uL) + +#define INTC_ICDICER17_TINT128 (0x00000001uL) +#define INTC_ICDICER17_TINT129 (0x00000002uL) +#define INTC_ICDICER17_TINT130 (0x00000004uL) +#define INTC_ICDICER17_TINT131 (0x00000008uL) +#define INTC_ICDICER17_TINT132 (0x00000010uL) +#define INTC_ICDICER17_TINT133 (0x00000020uL) +#define INTC_ICDICER17_TINT134 (0x00000040uL) +#define INTC_ICDICER17_TINT135 (0x00000080uL) +#define INTC_ICDICER17_TINT136 (0x00000100uL) +#define INTC_ICDICER17_TINT137 (0x00000200uL) +#define INTC_ICDICER17_TINT138 (0x00000400uL) +#define INTC_ICDICER17_TINT139 (0x00000800uL) +#define INTC_ICDICER17_TINT140 (0x00001000uL) +#define INTC_ICDICER17_TINT141 (0x00002000uL) +#define INTC_ICDICER17_TINT142 (0x00004000uL) +#define INTC_ICDICER17_TINT143 (0x00008000uL) +#define INTC_ICDICER17_TINT144 (0x00010000uL) +#define INTC_ICDICER17_TINT145 (0x00020000uL) +#define INTC_ICDICER17_TINT146 (0x00040000uL) +#define INTC_ICDICER17_TINT147 (0x00080000uL) +#define INTC_ICDICER17_TINT148 (0x00100000uL) +#define INTC_ICDICER17_TINT149 (0x00200000uL) +#define INTC_ICDICER17_TINT150 (0x00400000uL) +#define INTC_ICDICER17_TINT151 (0x00800000uL) +#define INTC_ICDICER17_TINT152 (0x01000000uL) +#define INTC_ICDICER17_TINT153 (0x02000000uL) +#define INTC_ICDICER17_TINT154 (0x04000000uL) +#define INTC_ICDICER17_TINT155 (0x08000000uL) +#define INTC_ICDICER17_TINT156 (0x10000000uL) +#define INTC_ICDICER17_TINT157 (0x20000000uL) +#define INTC_ICDICER17_TINT158 (0x40000000uL) +#define INTC_ICDICER17_TINT159 (0x80000000uL) + +#define INTC_ICDICER18_TINT160 (0x00000001uL) +#define INTC_ICDICER18_TINT161 (0x00000002uL) +#define INTC_ICDICER18_TINT162 (0x00000004uL) +#define INTC_ICDICER18_TINT163 (0x00000008uL) +#define INTC_ICDICER18_TINT164 (0x00000010uL) +#define INTC_ICDICER18_TINT165 (0x00000020uL) +#define INTC_ICDICER18_TINT166 (0x00000040uL) +#define INTC_ICDICER18_TINT167 (0x00000080uL) +#define INTC_ICDICER18_TINT168 (0x00000100uL) +#define INTC_ICDICER18_TINT169 (0x00000200uL) +#define INTC_ICDICER18_TINT170 (0x00000400uL) + +#define INTC_ICDISPR0_SW0 (0x00000001uL) +#define INTC_ICDISPR0_SW1 (0x00000002uL) +#define INTC_ICDISPR0_SW2 (0x00000004uL) +#define INTC_ICDISPR0_SW3 (0x00000008uL) +#define INTC_ICDISPR0_SW4 (0x00000010uL) +#define INTC_ICDISPR0_SW5 (0x00000020uL) +#define INTC_ICDISPR0_SW6 (0x00000040uL) +#define INTC_ICDISPR0_SW7 (0x00000080uL) +#define INTC_ICDISPR0_SW8 (0x00000100uL) +#define INTC_ICDISPR0_SW9 (0x00000200uL) +#define INTC_ICDISPR0_SW10 (0x00000400uL) +#define INTC_ICDISPR0_SW11 (0x00000800uL) +#define INTC_ICDISPR0_SW12 (0x00001000uL) +#define INTC_ICDISPR0_SW13 (0x00002000uL) +#define INTC_ICDISPR0_SW14 (0x00004000uL) +#define INTC_ICDISPR0_SW15 (0x00008000uL) +#define INTC_ICDISPR0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDISPR0_COMMRX0 (0x00020000uL) +#define INTC_ICDISPR0_COMMTX0 (0x00040000uL) +#define INTC_ICDISPR0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDISPR1_IRQ0 (0x00000001uL) +#define INTC_ICDISPR1_IRQ1 (0x00000002uL) +#define INTC_ICDISPR1_IRQ2 (0x00000004uL) +#define INTC_ICDISPR1_IRQ3 (0x00000008uL) +#define INTC_ICDISPR1_IRQ4 (0x00000010uL) +#define INTC_ICDISPR1_IRQ5 (0x00000020uL) +#define INTC_ICDISPR1_IRQ6 (0x00000040uL) +#define INTC_ICDISPR1_IRQ7 (0x00000080uL) +#define INTC_ICDISPR1_PL310ERR (0x00000100uL) +#define INTC_ICDISPR1_DMAINT0 (0x00000200uL) +#define INTC_ICDISPR1_DMAINT1 (0x00000400uL) +#define INTC_ICDISPR1_DMAINT2 (0x00000800uL) +#define INTC_ICDISPR1_DMAINT3 (0x00001000uL) +#define INTC_ICDISPR1_DMAINT4 (0x00002000uL) +#define INTC_ICDISPR1_DMAINT5 (0x00004000uL) +#define INTC_ICDISPR1_DMAINT6 (0x00008000uL) +#define INTC_ICDISPR1_DMAINT7 (0x00010000uL) +#define INTC_ICDISPR1_DMAINT8 (0x00020000uL) +#define INTC_ICDISPR1_DMAINT9 (0x00040000uL) +#define INTC_ICDISPR1_DMAINT10 (0x00080000uL) +#define INTC_ICDISPR1_DMAINT11 (0x00100000uL) +#define INTC_ICDISPR1_DMAINT12 (0x00200000uL) +#define INTC_ICDISPR1_DMAINT13 (0x00400000uL) +#define INTC_ICDISPR1_DMAINT14 (0x00800000uL) +#define INTC_ICDISPR1_DMAINT15 (0x01000000uL) +#define INTC_ICDISPR1_DMAERR (0x02000000uL) + +#define INTC_ICDISPR2_USBI0 (0x00000200uL) +#define INTC_ICDISPR2_USBI1 (0x00000400uL) +#define INTC_ICDISPR2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDISPR2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDISPR2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDISPR2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDISPR2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDISPR2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDISPR2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDISPR2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDISPR2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDISPR2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDISPR2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDISPR2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDISPR2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDISPR2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDISPR2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDISPR2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDISPR2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDISPR2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDISPR2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDISPR2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDISPR2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDISPR3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDISPR3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDISPR3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDISPR3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDISPR3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDISPR3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDISPR3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDISPR3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDISPR3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDISPR3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDISPR3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDISPR3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDISPR3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDISPR3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDISPR3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDISPR3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDISPR3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDISPR3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDISPR3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDISPR3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDISPR3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDISPR3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDISPR3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDISPR3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDISPR3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDISPR3_IMRDI (0x08000000uL) +#define INTC_ICDISPR3_IMR2I0 (0x10000000uL) +#define INTC_ICDISPR3_IMR2I1 (0x20000000uL) +#define INTC_ICDISPR3_JEDI (0x40000000uL) +#define INTC_ICDISPR3_JDTI (0x80000000uL) + +#define INTC_ICDISPR4_CMP0 (0x00000001uL) +#define INTC_ICDISPR4_CMP1 (0x00000002uL) +#define INTC_ICDISPR4_INT0 (0x00000004uL) +#define INTC_ICDISPR4_INT1 (0x00000008uL) +#define INTC_ICDISPR4_INT2 (0x00000010uL) +#define INTC_ICDISPR4_INT3 (0x00000020uL) +#define INTC_ICDISPR4_OSTM0TINT (0x00000040uL) +#define INTC_ICDISPR4_OSTM1TINT (0x00000080uL) +#define INTC_ICDISPR4_CMI (0x00000100uL) +#define INTC_ICDISPR4_WTOUT (0x00000200uL) +#define INTC_ICDISPR4_ITI (0x00000400uL) +#define INTC_ICDISPR4_TGI0A (0x00000800uL) +#define INTC_ICDISPR4_TGI0B (0x00001000uL) +#define INTC_ICDISPR4_TGI0C (0x00002000uL) +#define INTC_ICDISPR4_TGI0D (0x00004000uL) +#define INTC_ICDISPR4_TGI0V (0x00008000uL) +#define INTC_ICDISPR4_TGI0E (0x00010000uL) +#define INTC_ICDISPR4_TGI0F (0x00020000uL) +#define INTC_ICDISPR4_TGI1A (0x00040000uL) +#define INTC_ICDISPR4_TGI1B (0x00080000uL) +#define INTC_ICDISPR4_TGI1V (0x00100000uL) +#define INTC_ICDISPR4_TGI1U (0x00200000uL) +#define INTC_ICDISPR4_TGI2A (0x00400000uL) +#define INTC_ICDISPR4_TGI2B (0x00800000uL) +#define INTC_ICDISPR4_TGI2V (0x01000000uL) +#define INTC_ICDISPR4_TGI2U (0x02000000uL) +#define INTC_ICDISPR4_TGI3A (0x04000000uL) +#define INTC_ICDISPR4_TGI3B (0x08000000uL) +#define INTC_ICDISPR4_TGI3C (0x10000000uL) +#define INTC_ICDISPR4_TGI3D (0x20000000uL) +#define INTC_ICDISPR4_TGI3V (0x40000000uL) +#define INTC_ICDISPR4_TGI4A (0x80000000uL) + +#define INTC_ICDISPR5_TGI4B (0x00000001uL) +#define INTC_ICDISPR5_TGI4C (0x00000002uL) +#define INTC_ICDISPR5_TGI4D (0x00000004uL) +#define INTC_ICDISPR5_TGI4V (0x00000008uL) +#define INTC_ICDISPR5_CMI1 (0x00000010uL) +#define INTC_ICDISPR5_CMI2 (0x00000020uL) +#define INTC_ICDISPR5_SGDEI0 (0x00000040uL) +#define INTC_ICDISPR5_SGDEI1 (0x00000080uL) +#define INTC_ICDISPR5_SGDEI2 (0x00000100uL) +#define INTC_ICDISPR5_SGDEI3 (0x00000200uL) +#define INTC_ICDISPR5_ADI (0x00000400uL) +#define INTC_ICDISPR5_LMTI (0x00000800uL) +#define INTC_ICDISPR5_SSII0 (0x00001000uL) +#define INTC_ICDISPR5_SSIRXI0 (0x00002000uL) +#define INTC_ICDISPR5_SSITXI0 (0x00004000uL) +#define INTC_ICDISPR5_SSII1 (0x00008000uL) +#define INTC_ICDISPR5_SSIRXI1 (0x00010000uL) +#define INTC_ICDISPR5_SSITXI1 (0x00020000uL) +#define INTC_ICDISPR5_SSII2 (0x00040000uL) +#define INTC_ICDISPR5_SSIRTI2 (0x00080000uL) +#define INTC_ICDISPR5_SSII3 (0x00100000uL) +#define INTC_ICDISPR5_SSIRXI3 (0x00200000uL) +#define INTC_ICDISPR5_SSITXI3 (0x00400000uL) +#define INTC_ICDISPR5_SSII4 (0x00800000uL) +#define INTC_ICDISPR5_SSIRTI4 (0x01000000uL) +#define INTC_ICDISPR5_SSII5 (0x02000000uL) +#define INTC_ICDISPR5_SSIRXI5 (0x04000000uL) +#define INTC_ICDISPR5_SSITXI5 (0x08000000uL) +#define INTC_ICDISPR5_SPDIFI (0x10000000uL) +#define INTC_ICDISPR5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDISPR5_INTIICRI0 (0x40000000uL) +#define INTC_ICDISPR5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDISPR6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDISPR6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDISPR6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDISPR6_INTIICALI0 (0x00000008uL) +#define INTC_ICDISPR6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDISPR6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDISPR6_INTIICRI1 (0x00000040uL) +#define INTC_ICDISPR6_INTIICTI1 (0x00000080uL) +#define INTC_ICDISPR6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDISPR6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDISPR6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDISPR6_INTIICALI1 (0x00000800uL) +#define INTC_ICDISPR6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDISPR6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDISPR6_INTIICRI2 (0x00004000uL) +#define INTC_ICDISPR6_INTIICTI2 (0x00008000uL) +#define INTC_ICDISPR6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDISPR6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDISPR6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDISPR6_INTIICALI2 (0x00080000uL) +#define INTC_ICDISPR6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDISPR6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDISPR6_INTIICRI3 (0x00400000uL) +#define INTC_ICDISPR6_INTIICTI3 (0x00800000uL) +#define INTC_ICDISPR6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDISPR6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDISPR6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDISPR6_INTIICALI3 (0x08000000uL) +#define INTC_ICDISPR6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDISPR6_BRI0 (0x20000000uL) +#define INTC_ICDISPR6_ERI0 (0x40000000uL) +#define INTC_ICDISPR6_RXI0 (0x80000000uL) + +#define INTC_ICDISPR7_TXI0 (0x00000001uL) +#define INTC_ICDISPR7_BRI1 (0x00000002uL) +#define INTC_ICDISPR7_ERI1 (0x00000004uL) +#define INTC_ICDISPR7_RXI1 (0x00000008uL) +#define INTC_ICDISPR7_TXI1 (0x00000010uL) +#define INTC_ICDISPR7_BRI2 (0x00000020uL) +#define INTC_ICDISPR7_ERI2 (0x00000040uL) +#define INTC_ICDISPR7_RXI2 (0x00000080uL) +#define INTC_ICDISPR7_TXI2 (0x00000100uL) +#define INTC_ICDISPR7_BRI3 (0x00000200uL) +#define INTC_ICDISPR7_ERI3 (0x00000400uL) +#define INTC_ICDISPR7_RXI3 (0x00000800uL) +#define INTC_ICDISPR7_TXI3 (0x00001000uL) +#define INTC_ICDISPR7_BRI4 (0x00002000uL) +#define INTC_ICDISPR7_ERI4 (0x00004000uL) +#define INTC_ICDISPR7_RXI4 (0x00008000uL) +#define INTC_ICDISPR7_TXI4 (0x00010000uL) +#define INTC_ICDISPR7_BRI5 (0x00020000uL) +#define INTC_ICDISPR7_ERI5 (0x00040000uL) +#define INTC_ICDISPR7_RXI5 (0x00080000uL) +#define INTC_ICDISPR7_TXI5 (0x00100000uL) +#define INTC_ICDISPR7_BRI6 (0x00200000uL) +#define INTC_ICDISPR7_ERI6 (0x00400000uL) +#define INTC_ICDISPR7_RXI6 (0x00800000uL) +#define INTC_ICDISPR7_TXI6 (0x01000000uL) +#define INTC_ICDISPR7_BRI7 (0x02000000uL) +#define INTC_ICDISPR7_ERI7 (0x04000000uL) +#define INTC_ICDISPR7_RXI7 (0x08000000uL) +#define INTC_ICDISPR7_TXI7 (0x10000000uL) +#define INTC_ICDISPR7_INTRCANGERR (0x20000000uL) +#define INTC_ICDISPR7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDISPR7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDISPR8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDISPR8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDISPR8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDISPR8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDISPR8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDISPR8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDISPR8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDISPR8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDISPR8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDISPR8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDISPR8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDISPR8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDISPR8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDISPR8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDISPR8_SPEI0 (0x00004000uL) +#define INTC_ICDISPR8_SPRI0 (0x00008000uL) +#define INTC_ICDISPR8_SPTI0 (0x00010000uL) +#define INTC_ICDISPR8_SPEI1 (0x00020000uL) +#define INTC_ICDISPR8_SPRI1 (0x00040000uL) +#define INTC_ICDISPR8_SPTI1 (0x00080000uL) +#define INTC_ICDISPR8_SPEI2 (0x00100000uL) +#define INTC_ICDISPR8_SPRI2 (0x00200000uL) +#define INTC_ICDISPR8_SPTI2 (0x00400000uL) +#define INTC_ICDISPR8_SPEI3 (0x00800000uL) +#define INTC_ICDISPR8_SPRI3 (0x01000000uL) +#define INTC_ICDISPR8_SPTI3 (0x02000000uL) +#define INTC_ICDISPR8_SPEI4 (0x04000000uL) +#define INTC_ICDISPR8_SPRI4 (0x08000000uL) +#define INTC_ICDISPR8_SPTI4 (0x10000000uL) +#define INTC_ICDISPR8_IEBBTD (0x20000000uL) +#define INTC_ICDISPR8_IEBBTERR (0x40000000uL) +#define INTC_ICDISPR8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDISPR9_IEBBTV (0x00000001uL) +#define INTC_ICDISPR9_ISY (0x00000002uL) +#define INTC_ICDISPR9_IERR (0x00000004uL) +#define INTC_ICDISPR9_ITARG (0x00000008uL) +#define INTC_ICDISPR9_ISEC (0x00000010uL) +#define INTC_ICDISPR9_IBUF (0x00000020uL) +#define INTC_ICDISPR9_IREADY (0x00000040uL) +#define INTC_ICDISPR9_FLSTE (0x00000080uL) +#define INTC_ICDISPR9_FLTENDI (0x00000100uL) +#define INTC_ICDISPR9_FLTREQ0I (0x00000200uL) +#define INTC_ICDISPR9_FLTREQ1I (0x00000400uL) +#define INTC_ICDISPR9_MMC0 (0x00000800uL) +#define INTC_ICDISPR9_MMC1 (0x00001000uL) +#define INTC_ICDISPR9_MMC2 (0x00002000uL) +#define INTC_ICDISPR9_SDHI0_3 (0x00004000uL) +#define INTC_ICDISPR9_SDHI0_0 (0x00008000uL) +#define INTC_ICDISPR9_SDHI0_1 (0x00010000uL) +#define INTC_ICDISPR9_SDHI1_3 (0x00020000uL) +#define INTC_ICDISPR9_SDHI1_0 (0x00040000uL) +#define INTC_ICDISPR9_SDHI1_1 (0x00080000uL) +#define INTC_ICDISPR9_ARM (0x00100000uL) +#define INTC_ICDISPR9_PRD (0x00200000uL) +#define INTC_ICDISPR9_CUP (0x00400000uL) +#define INTC_ICDISPR9_SCUAI0 (0x00800000uL) +#define INTC_ICDISPR9_SCUAI1 (0x01000000uL) +#define INTC_ICDISPR9_SCUFDI0 (0x02000000uL) +#define INTC_ICDISPR9_SCUFDI1 (0x04000000uL) +#define INTC_ICDISPR9_SCUFDI2 (0x08000000uL) +#define INTC_ICDISPR9_SCUFDI3 (0x10000000uL) +#define INTC_ICDISPR9_SCUFUI0 (0x20000000uL) +#define INTC_ICDISPR9_SCUFUI1 (0x40000000uL) +#define INTC_ICDISPR9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDISPR10_SCUFUI3 (0x00000001uL) +#define INTC_ICDISPR10_SCUDVI0 (0x00000002uL) +#define INTC_ICDISPR10_SCUDVI1 (0x00000004uL) +#define INTC_ICDISPR10_SCUDVI2 (0x00000008uL) +#define INTC_ICDISPR10_SCUDVI3 (0x00000010uL) +#define INTC_ICDISPR10_MLB_CINT (0x00000020uL) +#define INTC_ICDISPR10_MLB_SINT (0x00000040uL) +#define INTC_ICDISPR10_DRC0 (0x00000080uL) +#define INTC_ICDISPR10_DRC1 (0x00000100uL) +#define INTC_ICDISPR10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDISPR10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDISPR10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDISPR10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDISPR10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDISPR10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDISPR10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDISPR10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDISPR10_ERI0 (0x08000000uL) +#define INTC_ICDISPR10_RXI0 (0x10000000uL) +#define INTC_ICDISPR10_TXI0 (0x20000000uL) +#define INTC_ICDISPR10_TEI0 (0x40000000uL) +#define INTC_ICDISPR10_ERI1 (0x80000000uL) + +#define INTC_ICDISPR11_RXI1 (0x00000001uL) +#define INTC_ICDISPR11_TXI1 (0x00000002uL) +#define INTC_ICDISPR11_TEI1 (0x00000004uL) +#define INTC_ICDISPR11_AVBI_DATA (0x00000008uL) +#define INTC_ICDISPR11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDISPR11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDISPR11_AVBI_MAC (0x00000040uL) +#define INTC_ICDISPR11_ETHERI (0x00000080uL) +#define INTC_ICDISPR11_CEUI (0x00001000uL) +#define INTC_ICDISPR11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDISPR11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDISPR11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDISPR12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDISPR12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDISPR12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDISPR12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDISPR12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDISPR12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDISPR12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDISPR12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDISPR12_PRRI (0x00000100uL) +#define INTC_ICDISPR12_IFEI0 (0x00000200uL) +#define INTC_ICDISPR12_OFFI0 (0x00000400uL) +#define INTC_ICDISPR12_PFVEI0 (0x00000800uL) +#define INTC_ICDISPR12_IFEI1 (0x00001000uL) +#define INTC_ICDISPR12_OFFI1 (0x00002000uL) +#define INTC_ICDISPR12_PFVEI1 (0x00004000uL) + +#define INTC_ICDISPR13_TINT0 (0x00000001uL) +#define INTC_ICDISPR13_TINT1 (0x00000002uL) +#define INTC_ICDISPR13_TINT2 (0x00000004uL) +#define INTC_ICDISPR13_TINT3 (0x00000008uL) +#define INTC_ICDISPR13_TINT4 (0x00000010uL) +#define INTC_ICDISPR13_TINT5 (0x00000020uL) +#define INTC_ICDISPR13_TINT6 (0x00000040uL) +#define INTC_ICDISPR13_TINT7 (0x00000080uL) +#define INTC_ICDISPR13_TINT8 (0x00000100uL) +#define INTC_ICDISPR13_TINT9 (0x00000200uL) +#define INTC_ICDISPR13_TINT10 (0x00000400uL) +#define INTC_ICDISPR13_TINT11 (0x00000800uL) +#define INTC_ICDISPR13_TINT12 (0x00001000uL) +#define INTC_ICDISPR13_TINT13 (0x00002000uL) +#define INTC_ICDISPR13_TINT14 (0x00004000uL) +#define INTC_ICDISPR13_TINT15 (0x00008000uL) +#define INTC_ICDISPR13_TINT16 (0x00010000uL) +#define INTC_ICDISPR13_TINT17 (0x00020000uL) +#define INTC_ICDISPR13_TINT18 (0x00040000uL) +#define INTC_ICDISPR13_TINT19 (0x00080000uL) +#define INTC_ICDISPR13_TINT20 (0x00100000uL) +#define INTC_ICDISPR13_TINT21 (0x00200000uL) +#define INTC_ICDISPR13_TINT22 (0x00400000uL) +#define INTC_ICDISPR13_TINT23 (0x00800000uL) +#define INTC_ICDISPR13_TINT24 (0x01000000uL) +#define INTC_ICDISPR13_TINT25 (0x02000000uL) +#define INTC_ICDISPR13_TINT26 (0x04000000uL) +#define INTC_ICDISPR13_TINT27 (0x08000000uL) +#define INTC_ICDISPR13_TINT28 (0x10000000uL) +#define INTC_ICDISPR13_TINT29 (0x20000000uL) +#define INTC_ICDISPR13_TINT30 (0x40000000uL) +#define INTC_ICDISPR13_TINT31 (0x80000000uL) + +#define INTC_ICDISPR14_TINT32 (0x00000001uL) +#define INTC_ICDISPR14_TINT33 (0x00000002uL) +#define INTC_ICDISPR14_TINT34 (0x00000004uL) +#define INTC_ICDISPR14_TINT35 (0x00000008uL) +#define INTC_ICDISPR14_TINT36 (0x00000010uL) +#define INTC_ICDISPR14_TINT37 (0x00000020uL) +#define INTC_ICDISPR14_TINT38 (0x00000040uL) +#define INTC_ICDISPR14_TINT39 (0x00000080uL) +#define INTC_ICDISPR14_TINT40 (0x00000100uL) +#define INTC_ICDISPR14_TINT41 (0x00000200uL) +#define INTC_ICDISPR14_TINT42 (0x00000400uL) +#define INTC_ICDISPR14_TINT43 (0x00000800uL) +#define INTC_ICDISPR14_TINT44 (0x00001000uL) +#define INTC_ICDISPR14_TINT45 (0x00002000uL) +#define INTC_ICDISPR14_TINT46 (0x00004000uL) +#define INTC_ICDISPR14_TINT47 (0x00008000uL) +#define INTC_ICDISPR14_TINT48 (0x00010000uL) +#define INTC_ICDISPR14_TINT49 (0x00020000uL) +#define INTC_ICDISPR14_TINT50 (0x00040000uL) +#define INTC_ICDISPR14_TINT51 (0x00080000uL) +#define INTC_ICDISPR14_TINT52 (0x00100000uL) +#define INTC_ICDISPR14_TINT53 (0x00200000uL) +#define INTC_ICDISPR14_TINT54 (0x00400000uL) +#define INTC_ICDISPR14_TINT55 (0x00800000uL) +#define INTC_ICDISPR14_TINT56 (0x01000000uL) +#define INTC_ICDISPR14_TINT57 (0x02000000uL) +#define INTC_ICDISPR14_TINT58 (0x04000000uL) +#define INTC_ICDISPR14_TINT59 (0x08000000uL) +#define INTC_ICDISPR14_TINT60 (0x10000000uL) +#define INTC_ICDISPR14_TINT61 (0x20000000uL) +#define INTC_ICDISPR14_TINT62 (0x40000000uL) +#define INTC_ICDISPR14_TINT63 (0x80000000uL) + +#define INTC_ICDISPR15_TINT64 (0x00000001uL) +#define INTC_ICDISPR15_TINT65 (0x00000002uL) +#define INTC_ICDISPR15_TINT66 (0x00000004uL) +#define INTC_ICDISPR15_TINT67 (0x00000008uL) +#define INTC_ICDISPR15_TINT68 (0x00000010uL) +#define INTC_ICDISPR15_TINT69 (0x00000020uL) +#define INTC_ICDISPR15_TINT70 (0x00000040uL) +#define INTC_ICDISPR15_TINT71 (0x00000080uL) +#define INTC_ICDISPR15_TINT72 (0x00000100uL) +#define INTC_ICDISPR15_TINT73 (0x00000200uL) +#define INTC_ICDISPR15_TINT74 (0x00000400uL) +#define INTC_ICDISPR15_TINT75 (0x00000800uL) +#define INTC_ICDISPR15_TINT76 (0x00001000uL) +#define INTC_ICDISPR15_TINT77 (0x00002000uL) +#define INTC_ICDISPR15_TINT78 (0x00004000uL) +#define INTC_ICDISPR15_TINT79 (0x00008000uL) +#define INTC_ICDISPR15_TINT80 (0x00010000uL) +#define INTC_ICDISPR15_TINT81 (0x00020000uL) +#define INTC_ICDISPR15_TINT82 (0x00040000uL) +#define INTC_ICDISPR15_TINT83 (0x00080000uL) +#define INTC_ICDISPR15_TINT84 (0x00100000uL) +#define INTC_ICDISPR15_TINT85 (0x00200000uL) +#define INTC_ICDISPR15_TINT86 (0x00400000uL) +#define INTC_ICDISPR15_TINT87 (0x00800000uL) +#define INTC_ICDISPR15_TINT88 (0x01000000uL) +#define INTC_ICDISPR15_TINT89 (0x02000000uL) +#define INTC_ICDISPR15_TINT90 (0x04000000uL) +#define INTC_ICDISPR15_TINT91 (0x08000000uL) +#define INTC_ICDISPR15_TINT92 (0x10000000uL) +#define INTC_ICDISPR15_TINT93 (0x20000000uL) +#define INTC_ICDISPR15_TINT94 (0x40000000uL) +#define INTC_ICDISPR15_TINT95 (0x80000000uL) + +#define INTC_ICDISPR16_TINT96 (0x00000001uL) +#define INTC_ICDISPR16_TINT97 (0x00000002uL) +#define INTC_ICDISPR16_TINT98 (0x00000004uL) +#define INTC_ICDISPR16_TINT99 (0x00000008uL) +#define INTC_ICDISPR16_TINT100 (0x00000010uL) +#define INTC_ICDISPR16_TINT101 (0x00000020uL) +#define INTC_ICDISPR16_TINT102 (0x00000040uL) +#define INTC_ICDISPR16_TINT103 (0x00000080uL) +#define INTC_ICDISPR16_TINT104 (0x00000100uL) +#define INTC_ICDISPR16_TINT105 (0x00000200uL) +#define INTC_ICDISPR16_TINT106 (0x00000400uL) +#define INTC_ICDISPR16_TINT107 (0x00000800uL) +#define INTC_ICDISPR16_TINT108 (0x00001000uL) +#define INTC_ICDISPR16_TINT109 (0x00002000uL) +#define INTC_ICDISPR16_TINT110 (0x00004000uL) +#define INTC_ICDISPR16_TINT111 (0x00008000uL) +#define INTC_ICDISPR16_TINT112 (0x00010000uL) +#define INTC_ICDISPR16_TINT113 (0x00020000uL) +#define INTC_ICDISPR16_TINT114 (0x00040000uL) +#define INTC_ICDISPR16_TINT115 (0x00080000uL) +#define INTC_ICDISPR16_TINT116 (0x00100000uL) +#define INTC_ICDISPR16_TINT117 (0x00200000uL) +#define INTC_ICDISPR16_TINT118 (0x00400000uL) +#define INTC_ICDISPR16_TINT119 (0x00800000uL) +#define INTC_ICDISPR16_TINT120 (0x01000000uL) +#define INTC_ICDISPR16_TINT121 (0x02000000uL) +#define INTC_ICDISPR16_TINT122 (0x04000000uL) +#define INTC_ICDISPR16_TINT123 (0x08000000uL) +#define INTC_ICDISPR16_TINT124 (0x10000000uL) +#define INTC_ICDISPR16_TINT125 (0x20000000uL) +#define INTC_ICDISPR16_TINT126 (0x40000000uL) +#define INTC_ICDISPR16_TINT127 (0x80000000uL) + +#define INTC_ICDISPR17_TINT128 (0x00000001uL) +#define INTC_ICDISPR17_TINT129 (0x00000002uL) +#define INTC_ICDISPR17_TINT130 (0x00000004uL) +#define INTC_ICDISPR17_TINT131 (0x00000008uL) +#define INTC_ICDISPR17_TINT132 (0x00000010uL) +#define INTC_ICDISPR17_TINT133 (0x00000020uL) +#define INTC_ICDISPR17_TINT134 (0x00000040uL) +#define INTC_ICDISPR17_TINT135 (0x00000080uL) +#define INTC_ICDISPR17_TINT136 (0x00000100uL) +#define INTC_ICDISPR17_TINT137 (0x00000200uL) +#define INTC_ICDISPR17_TINT138 (0x00000400uL) +#define INTC_ICDISPR17_TINT139 (0x00000800uL) +#define INTC_ICDISPR17_TINT140 (0x00001000uL) +#define INTC_ICDISPR17_TINT141 (0x00002000uL) +#define INTC_ICDISPR17_TINT142 (0x00004000uL) +#define INTC_ICDISPR17_TINT143 (0x00008000uL) +#define INTC_ICDISPR17_TINT144 (0x00010000uL) +#define INTC_ICDISPR17_TINT145 (0x00020000uL) +#define INTC_ICDISPR17_TINT146 (0x00040000uL) +#define INTC_ICDISPR17_TINT147 (0x00080000uL) +#define INTC_ICDISPR17_TINT148 (0x00100000uL) +#define INTC_ICDISPR17_TINT149 (0x00200000uL) +#define INTC_ICDISPR17_TINT150 (0x00400000uL) +#define INTC_ICDISPR17_TINT151 (0x00800000uL) +#define INTC_ICDISPR17_TINT152 (0x01000000uL) +#define INTC_ICDISPR17_TINT153 (0x02000000uL) +#define INTC_ICDISPR17_TINT154 (0x04000000uL) +#define INTC_ICDISPR17_TINT155 (0x08000000uL) +#define INTC_ICDISPR17_TINT156 (0x10000000uL) +#define INTC_ICDISPR17_TINT157 (0x20000000uL) +#define INTC_ICDISPR17_TINT158 (0x40000000uL) +#define INTC_ICDISPR17_TINT159 (0x80000000uL) + +#define INTC_ICDISPR18_TINT160 (0x00000001uL) +#define INTC_ICDISPR18_TINT161 (0x00000002uL) +#define INTC_ICDISPR18_TINT162 (0x00000004uL) +#define INTC_ICDISPR18_TINT163 (0x00000008uL) +#define INTC_ICDISPR18_TINT164 (0x00000010uL) +#define INTC_ICDISPR18_TINT165 (0x00000020uL) +#define INTC_ICDISPR18_TINT166 (0x00000040uL) +#define INTC_ICDISPR18_TINT167 (0x00000080uL) +#define INTC_ICDISPR18_TINT168 (0x00000100uL) +#define INTC_ICDISPR18_TINT169 (0x00000200uL) +#define INTC_ICDISPR18_TINT170 (0x00000400uL) + +#define INTC_ICDICPR0_SW0 (0x00000001uL) +#define INTC_ICDICPR0_SW1 (0x00000002uL) +#define INTC_ICDICPR0_SW2 (0x00000004uL) +#define INTC_ICDICPR0_SW3 (0x00000008uL) +#define INTC_ICDICPR0_SW4 (0x00000010uL) +#define INTC_ICDICPR0_SW5 (0x00000020uL) +#define INTC_ICDICPR0_SW6 (0x00000040uL) +#define INTC_ICDICPR0_SW7 (0x00000080uL) +#define INTC_ICDICPR0_SW8 (0x00000100uL) +#define INTC_ICDICPR0_SW9 (0x00000200uL) +#define INTC_ICDICPR0_SW10 (0x00000400uL) +#define INTC_ICDICPR0_SW11 (0x00000800uL) +#define INTC_ICDICPR0_SW12 (0x00001000uL) +#define INTC_ICDICPR0_SW13 (0x00002000uL) +#define INTC_ICDICPR0_SW14 (0x00004000uL) +#define INTC_ICDICPR0_SW15 (0x00008000uL) +#define INTC_ICDICPR0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDICPR0_COMMRX0 (0x00020000uL) +#define INTC_ICDICPR0_COMMTX0 (0x00040000uL) +#define INTC_ICDICPR0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDICPR1_IRQ0 (0x00000001uL) +#define INTC_ICDICPR1_IRQ1 (0x00000002uL) +#define INTC_ICDICPR1_IRQ2 (0x00000004uL) +#define INTC_ICDICPR1_IRQ3 (0x00000008uL) +#define INTC_ICDICPR1_IRQ4 (0x00000010uL) +#define INTC_ICDICPR1_IRQ5 (0x00000020uL) +#define INTC_ICDICPR1_IRQ6 (0x00000040uL) +#define INTC_ICDICPR1_IRQ7 (0x00000080uL) +#define INTC_ICDICPR1_PL310ERR (0x00000100uL) +#define INTC_ICDICPR1_DMAINT0 (0x00000200uL) +#define INTC_ICDICPR1_DMAINT1 (0x00000400uL) +#define INTC_ICDICPR1_DMAINT2 (0x00000800uL) +#define INTC_ICDICPR1_DMAINT3 (0x00001000uL) +#define INTC_ICDICPR1_DMAINT4 (0x00002000uL) +#define INTC_ICDICPR1_DMAINT5 (0x00004000uL) +#define INTC_ICDICPR1_DMAINT6 (0x00008000uL) +#define INTC_ICDICPR1_DMAINT7 (0x00010000uL) +#define INTC_ICDICPR1_DMAINT8 (0x00020000uL) +#define INTC_ICDICPR1_DMAINT9 (0x00040000uL) +#define INTC_ICDICPR1_DMAINT10 (0x00080000uL) +#define INTC_ICDICPR1_DMAINT11 (0x00100000uL) +#define INTC_ICDICPR1_DMAINT12 (0x00200000uL) +#define INTC_ICDICPR1_DMAINT13 (0x00400000uL) +#define INTC_ICDICPR1_DMAINT14 (0x00800000uL) +#define INTC_ICDICPR1_DMAINT15 (0x01000000uL) +#define INTC_ICDICPR1_DMAERR (0x02000000uL) + +#define INTC_ICDICPR2_USBI0 (0x00000200uL) +#define INTC_ICDICPR2_USBI1 (0x00000400uL) +#define INTC_ICDICPR2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDICPR2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDICPR2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDICPR2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDICPR2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDICPR2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDICPR2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDICPR2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDICPR2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDICPR2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDICPR2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDICPR2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDICPR2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDICPR2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDICPR2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDICPR2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDICPR2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDICPR2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDICPR2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDICPR2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDICPR2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDICPR3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDICPR3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDICPR3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDICPR3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDICPR3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDICPR3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDICPR3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDICPR3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDICPR3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDICPR3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDICPR3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDICPR3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDICPR3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDICPR3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDICPR3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDICPR3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDICPR3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDICPR3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDICPR3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDICPR3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDICPR3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDICPR3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDICPR3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDICPR3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDICPR3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDICPR3_IMRDI (0x08000000uL) +#define INTC_ICDICPR3_IMR2I0 (0x10000000uL) +#define INTC_ICDICPR3_IMR2I1 (0x20000000uL) +#define INTC_ICDICPR3_JEDI (0x40000000uL) +#define INTC_ICDICPR3_JDTI (0x80000000uL) + +#define INTC_ICDICPR4_CMP0 (0x00000001uL) +#define INTC_ICDICPR4_CMP1 (0x00000002uL) +#define INTC_ICDICPR4_INT0 (0x00000004uL) +#define INTC_ICDICPR4_INT1 (0x00000008uL) +#define INTC_ICDICPR4_INT2 (0x00000010uL) +#define INTC_ICDICPR4_INT3 (0x00000020uL) +#define INTC_ICDICPR4_OSTM0TINT (0x00000040uL) +#define INTC_ICDICPR4_OSTM1TINT (0x00000080uL) +#define INTC_ICDICPR4_CMI (0x00000100uL) +#define INTC_ICDICPR4_WTOUT (0x00000200uL) +#define INTC_ICDICPR4_ITI (0x00000400uL) +#define INTC_ICDICPR4_TGI0A (0x00000800uL) +#define INTC_ICDICPR4_TGI0B (0x00001000uL) +#define INTC_ICDICPR4_TGI0C (0x00002000uL) +#define INTC_ICDICPR4_TGI0D (0x00004000uL) +#define INTC_ICDICPR4_TGI0V (0x00008000uL) +#define INTC_ICDICPR4_TGI0E (0x00010000uL) +#define INTC_ICDICPR4_TGI0F (0x00020000uL) +#define INTC_ICDICPR4_TGI1A (0x00040000uL) +#define INTC_ICDICPR4_TGI1B (0x00080000uL) +#define INTC_ICDICPR4_TGI1V (0x00100000uL) +#define INTC_ICDICPR4_TGI1U (0x00200000uL) +#define INTC_ICDICPR4_TGI2A (0x00400000uL) +#define INTC_ICDICPR4_TGI2B (0x00800000uL) +#define INTC_ICDICPR4_TGI2V (0x01000000uL) +#define INTC_ICDICPR4_TGI2U (0x02000000uL) +#define INTC_ICDICPR4_TGI3A (0x04000000uL) +#define INTC_ICDICPR4_TGI3B (0x08000000uL) +#define INTC_ICDICPR4_TGI3C (0x10000000uL) +#define INTC_ICDICPR4_TGI3D (0x20000000uL) +#define INTC_ICDICPR4_TGI3V (0x40000000uL) +#define INTC_ICDICPR4_TGI4A (0x80000000uL) + +#define INTC_ICDICPR5_TGI4B (0x00000001uL) +#define INTC_ICDICPR5_TGI4C (0x00000002uL) +#define INTC_ICDICPR5_TGI4D (0x00000004uL) +#define INTC_ICDICPR5_TGI4V (0x00000008uL) +#define INTC_ICDICPR5_CMI1 (0x00000010uL) +#define INTC_ICDICPR5_CMI2 (0x00000020uL) +#define INTC_ICDICPR5_SGDEI0 (0x00000040uL) +#define INTC_ICDICPR5_SGDEI1 (0x00000080uL) +#define INTC_ICDICPR5_SGDEI2 (0x00000100uL) +#define INTC_ICDICPR5_SGDEI3 (0x00000200uL) +#define INTC_ICDICPR5_ADI (0x00000400uL) +#define INTC_ICDICPR5_LMTI (0x00000800uL) +#define INTC_ICDICPR5_SSII0 (0x00001000uL) +#define INTC_ICDICPR5_SSIRXI0 (0x00002000uL) +#define INTC_ICDICPR5_SSITXI0 (0x00004000uL) +#define INTC_ICDICPR5_SSII1 (0x00008000uL) +#define INTC_ICDICPR5_SSIRXI1 (0x00010000uL) +#define INTC_ICDICPR5_SSITXI1 (0x00020000uL) +#define INTC_ICDICPR5_SSII2 (0x00040000uL) +#define INTC_ICDICPR5_SSIRTI2 (0x00080000uL) +#define INTC_ICDICPR5_SSII3 (0x00100000uL) +#define INTC_ICDICPR5_SSIRXI3 (0x00200000uL) +#define INTC_ICDICPR5_SSITXI3 (0x00400000uL) +#define INTC_ICDICPR5_SSII4 (0x00800000uL) +#define INTC_ICDICPR5_SSIRTI4 (0x01000000uL) +#define INTC_ICDICPR5_SSII5 (0x02000000uL) +#define INTC_ICDICPR5_SSIRXI5 (0x04000000uL) +#define INTC_ICDICPR5_SSITXI5 (0x08000000uL) +#define INTC_ICDICPR5_SPDIFI (0x10000000uL) +#define INTC_ICDICPR5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDICPR5_INTIICRI0 (0x40000000uL) +#define INTC_ICDICPR5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDICPR6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDICPR6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDICPR6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDICPR6_INTIICALI0 (0x00000008uL) +#define INTC_ICDICPR6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDICPR6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDICPR6_INTIICRI1 (0x00000040uL) +#define INTC_ICDICPR6_INTIICTI1 (0x00000080uL) +#define INTC_ICDICPR6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDICPR6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDICPR6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDICPR6_INTIICALI1 (0x00000800uL) +#define INTC_ICDICPR6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDICPR6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDICPR6_INTIICRI2 (0x00004000uL) +#define INTC_ICDICPR6_INTIICTI2 (0x00008000uL) +#define INTC_ICDICPR6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDICPR6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDICPR6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDICPR6_INTIICALI2 (0x00080000uL) +#define INTC_ICDICPR6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDICPR6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDICPR6_INTIICRI3 (0x00400000uL) +#define INTC_ICDICPR6_INTIICTI3 (0x00800000uL) +#define INTC_ICDICPR6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDICPR6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDICPR6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDICPR6_INTIICALI3 (0x08000000uL) +#define INTC_ICDICPR6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDICPR6_BRI0 (0x20000000uL) +#define INTC_ICDICPR6_ERI0 (0x40000000uL) +#define INTC_ICDICPR6_RXI0 (0x80000000uL) + +#define INTC_ICDICPR7_TXI0 (0x00000001uL) +#define INTC_ICDICPR7_BRI1 (0x00000002uL) +#define INTC_ICDICPR7_ERI1 (0x00000004uL) +#define INTC_ICDICPR7_RXI1 (0x00000008uL) +#define INTC_ICDICPR7_TXI1 (0x00000010uL) +#define INTC_ICDICPR7_BRI2 (0x00000020uL) +#define INTC_ICDICPR7_ERI2 (0x00000040uL) +#define INTC_ICDICPR7_RXI2 (0x00000080uL) +#define INTC_ICDICPR7_TXI2 (0x00000100uL) +#define INTC_ICDICPR7_BRI3 (0x00000200uL) +#define INTC_ICDICPR7_ERI3 (0x00000400uL) +#define INTC_ICDICPR7_RXI3 (0x00000800uL) +#define INTC_ICDICPR7_TXI3 (0x00001000uL) +#define INTC_ICDICPR7_BRI4 (0x00002000uL) +#define INTC_ICDICPR7_ERI4 (0x00004000uL) +#define INTC_ICDICPR7_RXI4 (0x00008000uL) +#define INTC_ICDICPR7_TXI4 (0x00010000uL) +#define INTC_ICDICPR7_BRI5 (0x00020000uL) +#define INTC_ICDICPR7_ERI5 (0x00040000uL) +#define INTC_ICDICPR7_RXI5 (0x00080000uL) +#define INTC_ICDICPR7_TXI5 (0x00100000uL) +#define INTC_ICDICPR7_BRI6 (0x00200000uL) +#define INTC_ICDICPR7_ERI6 (0x00400000uL) +#define INTC_ICDICPR7_RXI6 (0x00800000uL) +#define INTC_ICDICPR7_TXI6 (0x01000000uL) +#define INTC_ICDICPR7_BRI7 (0x02000000uL) +#define INTC_ICDICPR7_ERI7 (0x04000000uL) +#define INTC_ICDICPR7_RXI7 (0x08000000uL) +#define INTC_ICDICPR7_TXI7 (0x10000000uL) +#define INTC_ICDICPR7_INTRCANGERR (0x20000000uL) +#define INTC_ICDICPR7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDICPR7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDICPR8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDICPR8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDICPR8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDICPR8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDICPR8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDICPR8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDICPR8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDICPR8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDICPR8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDICPR8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDICPR8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDICPR8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDICPR8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDICPR8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDICPR8_SPEI0 (0x00004000uL) +#define INTC_ICDICPR8_SPRI0 (0x00008000uL) +#define INTC_ICDICPR8_SPTI0 (0x00010000uL) +#define INTC_ICDICPR8_SPEI1 (0x00020000uL) +#define INTC_ICDICPR8_SPRI1 (0x00040000uL) +#define INTC_ICDICPR8_SPTI1 (0x00080000uL) +#define INTC_ICDICPR8_SPEI2 (0x00100000uL) +#define INTC_ICDICPR8_SPRI2 (0x00200000uL) +#define INTC_ICDICPR8_SPTI2 (0x00400000uL) +#define INTC_ICDICPR8_SPEI3 (0x00800000uL) +#define INTC_ICDICPR8_SPRI3 (0x01000000uL) +#define INTC_ICDICPR8_SPTI3 (0x02000000uL) +#define INTC_ICDICPR8_SPEI4 (0x04000000uL) +#define INTC_ICDICPR8_SPRI4 (0x08000000uL) +#define INTC_ICDICPR8_SPTI4 (0x10000000uL) +#define INTC_ICDICPR8_IEBBTD (0x20000000uL) +#define INTC_ICDICPR8_IEBBTERR (0x40000000uL) +#define INTC_ICDICPR8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDICPR9_IEBBTV (0x00000001uL) +#define INTC_ICDICPR9_ISY (0x00000002uL) +#define INTC_ICDICPR9_IERR (0x00000004uL) +#define INTC_ICDICPR9_ITARG (0x00000008uL) +#define INTC_ICDICPR9_ISEC (0x00000010uL) +#define INTC_ICDICPR9_IBUF (0x00000020uL) +#define INTC_ICDICPR9_IREADY (0x00000040uL) +#define INTC_ICDICPR9_FLSTE (0x00000080uL) +#define INTC_ICDICPR9_FLTENDI (0x00000100uL) +#define INTC_ICDICPR9_FLTREQ0I (0x00000200uL) +#define INTC_ICDICPR9_FLTREQ1I (0x00000400uL) +#define INTC_ICDICPR9_MMC0 (0x00000800uL) +#define INTC_ICDICPR9_MMC1 (0x00001000uL) +#define INTC_ICDICPR9_MMC2 (0x00002000uL) +#define INTC_ICDICPR9_SDHI0_3 (0x00004000uL) +#define INTC_ICDICPR9_SDHI0_0 (0x00008000uL) +#define INTC_ICDICPR9_SDHI0_1 (0x00010000uL) +#define INTC_ICDICPR9_SDHI1_3 (0x00020000uL) +#define INTC_ICDICPR9_SDHI1_0 (0x00040000uL) +#define INTC_ICDICPR9_SDHI1_1 (0x00080000uL) +#define INTC_ICDICPR9_ARM (0x00100000uL) +#define INTC_ICDICPR9_PRD (0x00200000uL) +#define INTC_ICDICPR9_CUP (0x00400000uL) +#define INTC_ICDICPR9_SCUAI0 (0x00800000uL) +#define INTC_ICDICPR9_SCUAI1 (0x01000000uL) +#define INTC_ICDICPR9_SCUFDI0 (0x02000000uL) +#define INTC_ICDICPR9_SCUFDI1 (0x04000000uL) +#define INTC_ICDICPR9_SCUFDI2 (0x08000000uL) +#define INTC_ICDICPR9_SCUFDI3 (0x10000000uL) +#define INTC_ICDICPR9_SCUFUI0 (0x20000000uL) +#define INTC_ICDICPR9_SCUFUI1 (0x40000000uL) +#define INTC_ICDICPR9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDICPR10_SCUFUI3 (0x00000001uL) +#define INTC_ICDICPR10_SCUDVI0 (0x00000002uL) +#define INTC_ICDICPR10_SCUDVI1 (0x00000004uL) +#define INTC_ICDICPR10_SCUDVI2 (0x00000008uL) +#define INTC_ICDICPR10_SCUDVI3 (0x00000010uL) +#define INTC_ICDICPR10_MLB_CINT (0x00000020uL) +#define INTC_ICDICPR10_MLB_SINT (0x00000040uL) +#define INTC_ICDICPR10_DRC0 (0x00000080uL) +#define INTC_ICDICPR10_DRC1 (0x00000100uL) +#define INTC_ICDICPR10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDICPR10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDICPR10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDICPR10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDICPR10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDICPR10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDICPR10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDICPR10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDICPR10_ERI0 (0x08000000uL) +#define INTC_ICDICPR10_RXI0 (0x10000000uL) +#define INTC_ICDICPR10_TXI0 (0x20000000uL) +#define INTC_ICDICPR10_TEI0 (0x40000000uL) +#define INTC_ICDICPR10_ERI1 (0x80000000uL) + +#define INTC_ICDICPR11_RXI1 (0x00000001uL) +#define INTC_ICDICPR11_TXI1 (0x00000002uL) +#define INTC_ICDICPR11_TEI1 (0x00000004uL) +#define INTC_ICDICPR11_AVBI_DATA (0x00000008uL) +#define INTC_ICDICPR11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDICPR11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDICPR11_AVBI_MAC (0x00000040uL) +#define INTC_ICDICPR11_ETHERI (0x00000080uL) +#define INTC_ICDICPR11_CEUI (0x00001000uL) +#define INTC_ICDICPR11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDICPR11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDICPR11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDICPR12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDICPR12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDICPR12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDICPR12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDICPR12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDICPR12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDICPR12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDICPR12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDICPR12_PRRI (0x00000100uL) +#define INTC_ICDICPR12_IFEI0 (0x00000200uL) +#define INTC_ICDICPR12_OFFI0 (0x00000400uL) +#define INTC_ICDICPR12_PFVEI0 (0x00000800uL) +#define INTC_ICDICPR12_IFEI1 (0x00001000uL) +#define INTC_ICDICPR12_OFFI1 (0x00002000uL) +#define INTC_ICDICPR12_PFVEI1 (0x00004000uL) + +#define INTC_ICDICPR13_TINT0 (0x00000001uL) +#define INTC_ICDICPR13_TINT1 (0x00000002uL) +#define INTC_ICDICPR13_TINT2 (0x00000004uL) +#define INTC_ICDICPR13_TINT3 (0x00000008uL) +#define INTC_ICDICPR13_TINT4 (0x00000010uL) +#define INTC_ICDICPR13_TINT5 (0x00000020uL) +#define INTC_ICDICPR13_TINT6 (0x00000040uL) +#define INTC_ICDICPR13_TINT7 (0x00000080uL) +#define INTC_ICDICPR13_TINT8 (0x00000100uL) +#define INTC_ICDICPR13_TINT9 (0x00000200uL) +#define INTC_ICDICPR13_TINT10 (0x00000400uL) +#define INTC_ICDICPR13_TINT11 (0x00000800uL) +#define INTC_ICDICPR13_TINT12 (0x00001000uL) +#define INTC_ICDICPR13_TINT13 (0x00002000uL) +#define INTC_ICDICPR13_TINT14 (0x00004000uL) +#define INTC_ICDICPR13_TINT15 (0x00008000uL) +#define INTC_ICDICPR13_TINT16 (0x00010000uL) +#define INTC_ICDICPR13_TINT17 (0x00020000uL) +#define INTC_ICDICPR13_TINT18 (0x00040000uL) +#define INTC_ICDICPR13_TINT19 (0x00080000uL) +#define INTC_ICDICPR13_TINT20 (0x00100000uL) +#define INTC_ICDICPR13_TINT21 (0x00200000uL) +#define INTC_ICDICPR13_TINT22 (0x00400000uL) +#define INTC_ICDICPR13_TINT23 (0x00800000uL) +#define INTC_ICDICPR13_TINT24 (0x01000000uL) +#define INTC_ICDICPR13_TINT25 (0x02000000uL) +#define INTC_ICDICPR13_TINT26 (0x04000000uL) +#define INTC_ICDICPR13_TINT27 (0x08000000uL) +#define INTC_ICDICPR13_TINT28 (0x10000000uL) +#define INTC_ICDICPR13_TINT29 (0x20000000uL) +#define INTC_ICDICPR13_TINT30 (0x40000000uL) +#define INTC_ICDICPR13_TINT31 (0x80000000uL) + +#define INTC_ICDICPR14_TINT32 (0x00000001uL) +#define INTC_ICDICPR14_TINT33 (0x00000002uL) +#define INTC_ICDICPR14_TINT34 (0x00000004uL) +#define INTC_ICDICPR14_TINT35 (0x00000008uL) +#define INTC_ICDICPR14_TINT36 (0x00000010uL) +#define INTC_ICDICPR14_TINT37 (0x00000020uL) +#define INTC_ICDICPR14_TINT38 (0x00000040uL) +#define INTC_ICDICPR14_TINT39 (0x00000080uL) +#define INTC_ICDICPR14_TINT40 (0x00000100uL) +#define INTC_ICDICPR14_TINT41 (0x00000200uL) +#define INTC_ICDICPR14_TINT42 (0x00000400uL) +#define INTC_ICDICPR14_TINT43 (0x00000800uL) +#define INTC_ICDICPR14_TINT44 (0x00001000uL) +#define INTC_ICDICPR14_TINT45 (0x00002000uL) +#define INTC_ICDICPR14_TINT46 (0x00004000uL) +#define INTC_ICDICPR14_TINT47 (0x00008000uL) +#define INTC_ICDICPR14_TINT48 (0x00010000uL) +#define INTC_ICDICPR14_TINT49 (0x00020000uL) +#define INTC_ICDICPR14_TINT50 (0x00040000uL) +#define INTC_ICDICPR14_TINT51 (0x00080000uL) +#define INTC_ICDICPR14_TINT52 (0x00100000uL) +#define INTC_ICDICPR14_TINT53 (0x00200000uL) +#define INTC_ICDICPR14_TINT54 (0x00400000uL) +#define INTC_ICDICPR14_TINT55 (0x00800000uL) +#define INTC_ICDICPR14_TINT56 (0x01000000uL) +#define INTC_ICDICPR14_TINT57 (0x02000000uL) +#define INTC_ICDICPR14_TINT58 (0x04000000uL) +#define INTC_ICDICPR14_TINT59 (0x08000000uL) +#define INTC_ICDICPR14_TINT60 (0x10000000uL) +#define INTC_ICDICPR14_TINT61 (0x20000000uL) +#define INTC_ICDICPR14_TINT62 (0x40000000uL) +#define INTC_ICDICPR14_TINT63 (0x80000000uL) + +#define INTC_ICDICPR15_TINT64 (0x00000001uL) +#define INTC_ICDICPR15_TINT65 (0x00000002uL) +#define INTC_ICDICPR15_TINT66 (0x00000004uL) +#define INTC_ICDICPR15_TINT67 (0x00000008uL) +#define INTC_ICDICPR15_TINT68 (0x00000010uL) +#define INTC_ICDICPR15_TINT69 (0x00000020uL) +#define INTC_ICDICPR15_TINT70 (0x00000040uL) +#define INTC_ICDICPR15_TINT71 (0x00000080uL) +#define INTC_ICDICPR15_TINT72 (0x00000100uL) +#define INTC_ICDICPR15_TINT73 (0x00000200uL) +#define INTC_ICDICPR15_TINT74 (0x00000400uL) +#define INTC_ICDICPR15_TINT75 (0x00000800uL) +#define INTC_ICDICPR15_TINT76 (0x00001000uL) +#define INTC_ICDICPR15_TINT77 (0x00002000uL) +#define INTC_ICDICPR15_TINT78 (0x00004000uL) +#define INTC_ICDICPR15_TINT79 (0x00008000uL) +#define INTC_ICDICPR15_TINT80 (0x00010000uL) +#define INTC_ICDICPR15_TINT81 (0x00020000uL) +#define INTC_ICDICPR15_TINT82 (0x00040000uL) +#define INTC_ICDICPR15_TINT83 (0x00080000uL) +#define INTC_ICDICPR15_TINT84 (0x00100000uL) +#define INTC_ICDICPR15_TINT85 (0x00200000uL) +#define INTC_ICDICPR15_TINT86 (0x00400000uL) +#define INTC_ICDICPR15_TINT87 (0x00800000uL) +#define INTC_ICDICPR15_TINT88 (0x01000000uL) +#define INTC_ICDICPR15_TINT89 (0x02000000uL) +#define INTC_ICDICPR15_TINT90 (0x04000000uL) +#define INTC_ICDICPR15_TINT91 (0x08000000uL) +#define INTC_ICDICPR15_TINT92 (0x10000000uL) +#define INTC_ICDICPR15_TINT93 (0x20000000uL) +#define INTC_ICDICPR15_TINT94 (0x40000000uL) +#define INTC_ICDICPR15_TINT95 (0x80000000uL) + +#define INTC_ICDICPR16_TINT96 (0x00000001uL) +#define INTC_ICDICPR16_TINT97 (0x00000002uL) +#define INTC_ICDICPR16_TINT98 (0x00000004uL) +#define INTC_ICDICPR16_TINT99 (0x00000008uL) +#define INTC_ICDICPR16_TINT100 (0x00000010uL) +#define INTC_ICDICPR16_TINT101 (0x00000020uL) +#define INTC_ICDICPR16_TINT102 (0x00000040uL) +#define INTC_ICDICPR16_TINT103 (0x00000080uL) +#define INTC_ICDICPR16_TINT104 (0x00000100uL) +#define INTC_ICDICPR16_TINT105 (0x00000200uL) +#define INTC_ICDICPR16_TINT106 (0x00000400uL) +#define INTC_ICDICPR16_TINT107 (0x00000800uL) +#define INTC_ICDICPR16_TINT108 (0x00001000uL) +#define INTC_ICDICPR16_TINT109 (0x00002000uL) +#define INTC_ICDICPR16_TINT110 (0x00004000uL) +#define INTC_ICDICPR16_TINT111 (0x00008000uL) +#define INTC_ICDICPR16_TINT112 (0x00010000uL) +#define INTC_ICDICPR16_TINT113 (0x00020000uL) +#define INTC_ICDICPR16_TINT114 (0x00040000uL) +#define INTC_ICDICPR16_TINT115 (0x00080000uL) +#define INTC_ICDICPR16_TINT116 (0x00100000uL) +#define INTC_ICDICPR16_TINT117 (0x00200000uL) +#define INTC_ICDICPR16_TINT118 (0x00400000uL) +#define INTC_ICDICPR16_TINT119 (0x00800000uL) +#define INTC_ICDICPR16_TINT120 (0x01000000uL) +#define INTC_ICDICPR16_TINT121 (0x02000000uL) +#define INTC_ICDICPR16_TINT122 (0x04000000uL) +#define INTC_ICDICPR16_TINT123 (0x08000000uL) +#define INTC_ICDICPR16_TINT124 (0x10000000uL) +#define INTC_ICDICPR16_TINT125 (0x20000000uL) +#define INTC_ICDICPR16_TINT126 (0x40000000uL) +#define INTC_ICDICPR16_TINT127 (0x80000000uL) + +#define INTC_ICDICPR17_TINT128 (0x00000001uL) +#define INTC_ICDICPR17_TINT129 (0x00000002uL) +#define INTC_ICDICPR17_TINT130 (0x00000004uL) +#define INTC_ICDICPR17_TINT131 (0x00000008uL) +#define INTC_ICDICPR17_TINT132 (0x00000010uL) +#define INTC_ICDICPR17_TINT133 (0x00000020uL) +#define INTC_ICDICPR17_TINT134 (0x00000040uL) +#define INTC_ICDICPR17_TINT135 (0x00000080uL) +#define INTC_ICDICPR17_TINT136 (0x00000100uL) +#define INTC_ICDICPR17_TINT137 (0x00000200uL) +#define INTC_ICDICPR17_TINT138 (0x00000400uL) +#define INTC_ICDICPR17_TINT139 (0x00000800uL) +#define INTC_ICDICPR17_TINT140 (0x00001000uL) +#define INTC_ICDICPR17_TINT141 (0x00002000uL) +#define INTC_ICDICPR17_TINT142 (0x00004000uL) +#define INTC_ICDICPR17_TINT143 (0x00008000uL) +#define INTC_ICDICPR17_TINT144 (0x00010000uL) +#define INTC_ICDICPR17_TINT145 (0x00020000uL) +#define INTC_ICDICPR17_TINT146 (0x00040000uL) +#define INTC_ICDICPR17_TINT147 (0x00080000uL) +#define INTC_ICDICPR17_TINT148 (0x00100000uL) +#define INTC_ICDICPR17_TINT149 (0x00200000uL) +#define INTC_ICDICPR17_TINT150 (0x00400000uL) +#define INTC_ICDICPR17_TINT151 (0x00800000uL) +#define INTC_ICDICPR17_TINT152 (0x01000000uL) +#define INTC_ICDICPR17_TINT153 (0x02000000uL) +#define INTC_ICDICPR17_TINT154 (0x04000000uL) +#define INTC_ICDICPR17_TINT155 (0x08000000uL) +#define INTC_ICDICPR17_TINT156 (0x10000000uL) +#define INTC_ICDICPR17_TINT157 (0x20000000uL) +#define INTC_ICDICPR17_TINT158 (0x40000000uL) +#define INTC_ICDICPR17_TINT159 (0x80000000uL) + +#define INTC_ICDICPR18_TINT160 (0x00000001uL) +#define INTC_ICDICPR18_TINT161 (0x00000002uL) +#define INTC_ICDICPR18_TINT162 (0x00000004uL) +#define INTC_ICDICPR18_TINT163 (0x00000008uL) +#define INTC_ICDICPR18_TINT164 (0x00000010uL) +#define INTC_ICDICPR18_TINT165 (0x00000020uL) +#define INTC_ICDICPR18_TINT166 (0x00000040uL) +#define INTC_ICDICPR18_TINT167 (0x00000080uL) +#define INTC_ICDICPR18_TINT168 (0x00000100uL) +#define INTC_ICDICPR18_TINT169 (0x00000200uL) +#define INTC_ICDICPR18_TINT170 (0x00000400uL) + +#define INTC_ICDABR0_SW0 (0x00000001uL) +#define INTC_ICDABR0_SW1 (0x00000002uL) +#define INTC_ICDABR0_SW2 (0x00000004uL) +#define INTC_ICDABR0_SW3 (0x00000008uL) +#define INTC_ICDABR0_SW4 (0x00000010uL) +#define INTC_ICDABR0_SW5 (0x00000020uL) +#define INTC_ICDABR0_SW6 (0x00000040uL) +#define INTC_ICDABR0_SW7 (0x00000080uL) +#define INTC_ICDABR0_SW8 (0x00000100uL) +#define INTC_ICDABR0_SW9 (0x00000200uL) +#define INTC_ICDABR0_SW10 (0x00000400uL) +#define INTC_ICDABR0_SW11 (0x00000800uL) +#define INTC_ICDABR0_SW12 (0x00001000uL) +#define INTC_ICDABR0_SW13 (0x00002000uL) +#define INTC_ICDABR0_SW14 (0x00004000uL) +#define INTC_ICDABR0_SW15 (0x00008000uL) +#define INTC_ICDABR0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDABR0_COMMRX0 (0x00020000uL) +#define INTC_ICDABR0_COMMTX0 (0x00040000uL) +#define INTC_ICDABR0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDABR1_IRQ0 (0x00000001uL) +#define INTC_ICDABR1_IRQ1 (0x00000002uL) +#define INTC_ICDABR1_IRQ2 (0x00000004uL) +#define INTC_ICDABR1_IRQ3 (0x00000008uL) +#define INTC_ICDABR1_IRQ4 (0x00000010uL) +#define INTC_ICDABR1_IRQ5 (0x00000020uL) +#define INTC_ICDABR1_IRQ6 (0x00000040uL) +#define INTC_ICDABR1_IRQ7 (0x00000080uL) +#define INTC_ICDABR1_PL310ERR (0x00000100uL) +#define INTC_ICDABR1_DMAINT0 (0x00000200uL) +#define INTC_ICDABR1_DMAINT1 (0x00000400uL) +#define INTC_ICDABR1_DMAINT2 (0x00000800uL) +#define INTC_ICDABR1_DMAINT3 (0x00001000uL) +#define INTC_ICDABR1_DMAINT4 (0x00002000uL) +#define INTC_ICDABR1_DMAINT5 (0x00004000uL) +#define INTC_ICDABR1_DMAINT6 (0x00008000uL) +#define INTC_ICDABR1_DMAINT7 (0x00010000uL) +#define INTC_ICDABR1_DMAINT8 (0x00020000uL) +#define INTC_ICDABR1_DMAINT9 (0x00040000uL) +#define INTC_ICDABR1_DMAINT10 (0x00080000uL) +#define INTC_ICDABR1_DMAINT11 (0x00100000uL) +#define INTC_ICDABR1_DMAINT12 (0x00200000uL) +#define INTC_ICDABR1_DMAINT13 (0x00400000uL) +#define INTC_ICDABR1_DMAINT14 (0x00800000uL) +#define INTC_ICDABR1_DMAINT15 (0x01000000uL) +#define INTC_ICDABR1_DMAERR (0x02000000uL) + +#define INTC_ICDABR2_USBI0 (0x00000200uL) +#define INTC_ICDABR2_USBI1 (0x00000400uL) +#define INTC_ICDABR2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDABR2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDABR2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDABR2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDABR2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDABR2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDABR2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDABR2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDABR2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDABR2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDABR2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDABR2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDABR2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDABR2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDABR2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDABR2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDABR2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDABR2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDABR2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDABR2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDABR2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDABR3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDABR3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDABR3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDABR3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDABR3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDABR3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDABR3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDABR3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDABR3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDABR3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDABR3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDABR3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDABR3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDABR3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDABR3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDABR3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDABR3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDABR3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDABR3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDABR3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDABR3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDABR3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDABR3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDABR3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDABR3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDABR3_IMRDI (0x08000000uL) +#define INTC_ICDABR3_IMR2I0 (0x10000000uL) +#define INTC_ICDABR3_IMR2I1 (0x20000000uL) +#define INTC_ICDABR3_JEDI (0x40000000uL) +#define INTC_ICDABR3_JDTI (0x80000000uL) + +#define INTC_ICDABR4_CMP0 (0x00000001uL) +#define INTC_ICDABR4_CMP1 (0x00000002uL) +#define INTC_ICDABR4_INT0 (0x00000004uL) +#define INTC_ICDABR4_INT1 (0x00000008uL) +#define INTC_ICDABR4_INT2 (0x00000010uL) +#define INTC_ICDABR4_INT3 (0x00000020uL) +#define INTC_ICDABR4_OSTM0TINT (0x00000040uL) +#define INTC_ICDABR4_OSTM1TINT (0x00000080uL) +#define INTC_ICDABR4_CMI (0x00000100uL) +#define INTC_ICDABR4_WTOUT (0x00000200uL) +#define INTC_ICDABR4_ITI (0x00000400uL) +#define INTC_ICDABR4_TGI0A (0x00000800uL) +#define INTC_ICDABR4_TGI0B (0x00001000uL) +#define INTC_ICDABR4_TGI0C (0x00002000uL) +#define INTC_ICDABR4_TGI0D (0x00004000uL) +#define INTC_ICDABR4_TGI0V (0x00008000uL) +#define INTC_ICDABR4_TGI0E (0x00010000uL) +#define INTC_ICDABR4_TGI0F (0x00020000uL) +#define INTC_ICDABR4_TGI1A (0x00040000uL) +#define INTC_ICDABR4_TGI1B (0x00080000uL) +#define INTC_ICDABR4_TGI1V (0x00100000uL) +#define INTC_ICDABR4_TGI1U (0x00200000uL) +#define INTC_ICDABR4_TGI2A (0x00400000uL) +#define INTC_ICDABR4_TGI2B (0x00800000uL) +#define INTC_ICDABR4_TGI2V (0x01000000uL) +#define INTC_ICDABR4_TGI2U (0x02000000uL) +#define INTC_ICDABR4_TGI3A (0x04000000uL) +#define INTC_ICDABR4_TGI3B (0x08000000uL) +#define INTC_ICDABR4_TGI3C (0x10000000uL) +#define INTC_ICDABR4_TGI3D (0x20000000uL) +#define INTC_ICDABR4_TGI3V (0x40000000uL) +#define INTC_ICDABR4_TGI4A (0x80000000uL) + +#define INTC_ICDABR5_TGI4B (0x00000001uL) +#define INTC_ICDABR5_TGI4C (0x00000002uL) +#define INTC_ICDABR5_TGI4D (0x00000004uL) +#define INTC_ICDABR5_TGI4V (0x00000008uL) +#define INTC_ICDABR5_CMI1 (0x00000010uL) +#define INTC_ICDABR5_CMI2 (0x00000020uL) +#define INTC_ICDABR5_SGDEI0 (0x00000040uL) +#define INTC_ICDABR5_SGDEI1 (0x00000080uL) +#define INTC_ICDABR5_SGDEI2 (0x00000100uL) +#define INTC_ICDABR5_SGDEI3 (0x00000200uL) +#define INTC_ICDABR5_ADI (0x00000400uL) +#define INTC_ICDABR5_LMTI (0x00000800uL) +#define INTC_ICDABR5_SSII0 (0x00001000uL) +#define INTC_ICDABR5_SSIRXI0 (0x00002000uL) +#define INTC_ICDABR5_SSITXI0 (0x00004000uL) +#define INTC_ICDABR5_SSII1 (0x00008000uL) +#define INTC_ICDABR5_SSIRXI1 (0x00010000uL) +#define INTC_ICDABR5_SSITXI1 (0x00020000uL) +#define INTC_ICDABR5_SSII2 (0x00040000uL) +#define INTC_ICDABR5_SSIRTI2 (0x00080000uL) +#define INTC_ICDABR5_SSII3 (0x00100000uL) +#define INTC_ICDABR5_SSIRXI3 (0x00200000uL) +#define INTC_ICDABR5_SSITXI3 (0x00400000uL) +#define INTC_ICDABR5_SSII4 (0x00800000uL) +#define INTC_ICDABR5_SSIRTI4 (0x01000000uL) +#define INTC_ICDABR5_SSII5 (0x02000000uL) +#define INTC_ICDABR5_SSIRXI5 (0x04000000uL) +#define INTC_ICDABR5_SSITXI5 (0x08000000uL) +#define INTC_ICDABR5_SPDIFI (0x10000000uL) +#define INTC_ICDABR5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDABR5_INTIICRI0 (0x40000000uL) +#define INTC_ICDABR5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDABR6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDABR6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDABR6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDABR6_INTIICALI0 (0x00000008uL) +#define INTC_ICDABR6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDABR6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDABR6_INTIICRI1 (0x00000040uL) +#define INTC_ICDABR6_INTIICTI1 (0x00000080uL) +#define INTC_ICDABR6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDABR6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDABR6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDABR6_INTIICALI1 (0x00000800uL) +#define INTC_ICDABR6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDABR6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDABR6_INTIICRI2 (0x00004000uL) +#define INTC_ICDABR6_INTIICTI2 (0x00008000uL) +#define INTC_ICDABR6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDABR6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDABR6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDABR6_INTIICALI2 (0x00080000uL) +#define INTC_ICDABR6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDABR6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDABR6_INTIICRI3 (0x00400000uL) +#define INTC_ICDABR6_INTIICTI3 (0x00800000uL) +#define INTC_ICDABR6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDABR6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDABR6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDABR6_INTIICALI3 (0x08000000uL) +#define INTC_ICDABR6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDABR6_BRI0 (0x20000000uL) +#define INTC_ICDABR6_ERI0 (0x40000000uL) +#define INTC_ICDABR6_RXI0 (0x80000000uL) + +#define INTC_ICDABR7_TXI0 (0x00000001uL) +#define INTC_ICDABR7_BRI1 (0x00000002uL) +#define INTC_ICDABR7_ERI1 (0x00000004uL) +#define INTC_ICDABR7_RXI1 (0x00000008uL) +#define INTC_ICDABR7_TXI1 (0x00000010uL) +#define INTC_ICDABR7_BRI2 (0x00000020uL) +#define INTC_ICDABR7_ERI2 (0x00000040uL) +#define INTC_ICDABR7_RXI2 (0x00000080uL) +#define INTC_ICDABR7_TXI2 (0x00000100uL) +#define INTC_ICDABR7_BRI3 (0x00000200uL) +#define INTC_ICDABR7_ERI3 (0x00000400uL) +#define INTC_ICDABR7_RXI3 (0x00000800uL) +#define INTC_ICDABR7_TXI3 (0x00001000uL) +#define INTC_ICDABR7_BRI4 (0x00002000uL) +#define INTC_ICDABR7_ERI4 (0x00004000uL) +#define INTC_ICDABR7_RXI4 (0x00008000uL) +#define INTC_ICDABR7_TXI4 (0x00010000uL) +#define INTC_ICDABR7_BRI5 (0x00020000uL) +#define INTC_ICDABR7_ERI5 (0x00040000uL) +#define INTC_ICDABR7_RXI5 (0x00080000uL) +#define INTC_ICDABR7_TXI5 (0x00100000uL) +#define INTC_ICDABR7_BRI6 (0x00200000uL) +#define INTC_ICDABR7_ERI6 (0x00400000uL) +#define INTC_ICDABR7_RXI6 (0x00800000uL) +#define INTC_ICDABR7_TXI6 (0x01000000uL) +#define INTC_ICDABR7_BRI7 (0x02000000uL) +#define INTC_ICDABR7_ERI7 (0x04000000uL) +#define INTC_ICDABR7_RXI7 (0x08000000uL) +#define INTC_ICDABR7_TXI7 (0x10000000uL) +#define INTC_ICDABR7_INTRCANGERR (0x20000000uL) +#define INTC_ICDABR7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDABR7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDABR8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDABR8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDABR8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDABR8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDABR8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDABR8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDABR8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDABR8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDABR8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDABR8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDABR8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDABR8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDABR8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDABR8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDABR8_SPEI0 (0x00004000uL) +#define INTC_ICDABR8_SPRI0 (0x00008000uL) +#define INTC_ICDABR8_SPTI0 (0x00010000uL) +#define INTC_ICDABR8_SPEI1 (0x00020000uL) +#define INTC_ICDABR8_SPRI1 (0x00040000uL) +#define INTC_ICDABR8_SPTI1 (0x00080000uL) +#define INTC_ICDABR8_SPEI2 (0x00100000uL) +#define INTC_ICDABR8_SPRI2 (0x00200000uL) +#define INTC_ICDABR8_SPTI2 (0x00400000uL) +#define INTC_ICDABR8_SPEI3 (0x00800000uL) +#define INTC_ICDABR8_SPRI3 (0x01000000uL) +#define INTC_ICDABR8_SPTI3 (0x02000000uL) +#define INTC_ICDABR8_SPEI4 (0x04000000uL) +#define INTC_ICDABR8_SPRI4 (0x08000000uL) +#define INTC_ICDABR8_SPTI4 (0x10000000uL) +#define INTC_ICDABR8_IEBBTD (0x20000000uL) +#define INTC_ICDABR8_IEBBTERR (0x40000000uL) +#define INTC_ICDABR8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDABR9_IEBBTV (0x00000001uL) +#define INTC_ICDABR9_ISY (0x00000002uL) +#define INTC_ICDABR9_IERR (0x00000004uL) +#define INTC_ICDABR9_ITARG (0x00000008uL) +#define INTC_ICDABR9_ISEC (0x00000010uL) +#define INTC_ICDABR9_IBUF (0x00000020uL) +#define INTC_ICDABR9_IREADY (0x00000040uL) +#define INTC_ICDABR9_FLSTE (0x00000080uL) +#define INTC_ICDABR9_FLTENDI (0x00000100uL) +#define INTC_ICDABR9_FLTREQ0I (0x00000200uL) +#define INTC_ICDABR9_FLTREQ1I (0x00000400uL) +#define INTC_ICDABR9_MMC0 (0x00000800uL) +#define INTC_ICDABR9_MMC1 (0x00001000uL) +#define INTC_ICDABR9_MMC2 (0x00002000uL) +#define INTC_ICDABR9_SDHI0_3 (0x00004000uL) +#define INTC_ICDABR9_SDHI0_0 (0x00008000uL) +#define INTC_ICDABR9_SDHI0_1 (0x00010000uL) +#define INTC_ICDABR9_SDHI1_3 (0x00020000uL) +#define INTC_ICDABR9_SDHI1_0 (0x00040000uL) +#define INTC_ICDABR9_SDHI1_1 (0x00080000uL) +#define INTC_ICDABR9_ARM (0x00100000uL) +#define INTC_ICDABR9_PRD (0x00200000uL) +#define INTC_ICDABR9_CUP (0x00400000uL) +#define INTC_ICDABR9_SCUAI0 (0x00800000uL) +#define INTC_ICDABR9_SCUAI1 (0x01000000uL) +#define INTC_ICDABR9_SCUFDI0 (0x02000000uL) +#define INTC_ICDABR9_SCUFDI1 (0x04000000uL) +#define INTC_ICDABR9_SCUFDI2 (0x08000000uL) +#define INTC_ICDABR9_SCUFDI3 (0x10000000uL) +#define INTC_ICDABR9_SCUFUI0 (0x20000000uL) +#define INTC_ICDABR9_SCUFUI1 (0x40000000uL) +#define INTC_ICDABR9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDABR10_SCUFUI3 (0x00000001uL) +#define INTC_ICDABR10_SCUDVI0 (0x00000002uL) +#define INTC_ICDABR10_SCUDVI1 (0x00000004uL) +#define INTC_ICDABR10_SCUDVI2 (0x00000008uL) +#define INTC_ICDABR10_SCUDVI3 (0x00000010uL) +#define INTC_ICDABR10_MLB_CINT (0x00000020uL) +#define INTC_ICDABR10_MLB_SINT (0x00000040uL) +#define INTC_ICDABR10_DRC0 (0x00000080uL) +#define INTC_ICDABR10_DRC1 (0x00000100uL) +#define INTC_ICDABR10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDABR10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDABR10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDABR10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDABR10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDABR10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDABR10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDABR10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDABR10_ERI0 (0x08000000uL) +#define INTC_ICDABR10_RXI0 (0x10000000uL) +#define INTC_ICDABR10_TXI0 (0x20000000uL) +#define INTC_ICDABR10_TEI0 (0x40000000uL) +#define INTC_ICDABR10_ERI1 (0x80000000uL) + +#define INTC_ICDABR11_RXI1 (0x00000001uL) +#define INTC_ICDABR11_TXI1 (0x00000002uL) +#define INTC_ICDABR11_TEI1 (0x00000004uL) +#define INTC_ICDABR11_AVBI_DATA (0x00000008uL) +#define INTC_ICDABR11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDABR11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDABR11_AVBI_MAC (0x00000040uL) +#define INTC_ICDABR11_ETHERI (0x00000080uL) +#define INTC_ICDABR11_CEUI (0x00001000uL) +#define INTC_ICDABR11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDABR11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDABR11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDABR12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDABR12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDABR12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDABR12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDABR12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDABR12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDABR12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDABR12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDABR12_PRRI (0x00000100uL) +#define INTC_ICDABR12_IFEI0 (0x00000200uL) +#define INTC_ICDABR12_OFFI0 (0x00000400uL) +#define INTC_ICDABR12_PFVEI0 (0x00000800uL) +#define INTC_ICDABR12_IFEI1 (0x00001000uL) +#define INTC_ICDABR12_OFFI1 (0x00002000uL) +#define INTC_ICDABR12_PFVEI1 (0x00004000uL) + +#define INTC_ICDABR13_TINT0 (0x00000001uL) +#define INTC_ICDABR13_TINT1 (0x00000002uL) +#define INTC_ICDABR13_TINT2 (0x00000004uL) +#define INTC_ICDABR13_TINT3 (0x00000008uL) +#define INTC_ICDABR13_TINT4 (0x00000010uL) +#define INTC_ICDABR13_TINT5 (0x00000020uL) +#define INTC_ICDABR13_TINT6 (0x00000040uL) +#define INTC_ICDABR13_TINT7 (0x00000080uL) +#define INTC_ICDABR13_TINT8 (0x00000100uL) +#define INTC_ICDABR13_TINT9 (0x00000200uL) +#define INTC_ICDABR13_TINT10 (0x00000400uL) +#define INTC_ICDABR13_TINT11 (0x00000800uL) +#define INTC_ICDABR13_TINT12 (0x00001000uL) +#define INTC_ICDABR13_TINT13 (0x00002000uL) +#define INTC_ICDABR13_TINT14 (0x00004000uL) +#define INTC_ICDABR13_TINT15 (0x00008000uL) +#define INTC_ICDABR13_TINT16 (0x00010000uL) +#define INTC_ICDABR13_TINT17 (0x00020000uL) +#define INTC_ICDABR13_TINT18 (0x00040000uL) +#define INTC_ICDABR13_TINT19 (0x00080000uL) +#define INTC_ICDABR13_TINT20 (0x00100000uL) +#define INTC_ICDABR13_TINT21 (0x00200000uL) +#define INTC_ICDABR13_TINT22 (0x00400000uL) +#define INTC_ICDABR13_TINT23 (0x00800000uL) +#define INTC_ICDABR13_TINT24 (0x01000000uL) +#define INTC_ICDABR13_TINT25 (0x02000000uL) +#define INTC_ICDABR13_TINT26 (0x04000000uL) +#define INTC_ICDABR13_TINT27 (0x08000000uL) +#define INTC_ICDABR13_TINT28 (0x10000000uL) +#define INTC_ICDABR13_TINT29 (0x20000000uL) +#define INTC_ICDABR13_TINT30 (0x40000000uL) +#define INTC_ICDABR13_TINT31 (0x80000000uL) + +#define INTC_ICDABR14_TINT32 (0x00000001uL) +#define INTC_ICDABR14_TINT33 (0x00000002uL) +#define INTC_ICDABR14_TINT34 (0x00000004uL) +#define INTC_ICDABR14_TINT35 (0x00000008uL) +#define INTC_ICDABR14_TINT36 (0x00000010uL) +#define INTC_ICDABR14_TINT37 (0x00000020uL) +#define INTC_ICDABR14_TINT38 (0x00000040uL) +#define INTC_ICDABR14_TINT39 (0x00000080uL) +#define INTC_ICDABR14_TINT40 (0x00000100uL) +#define INTC_ICDABR14_TINT41 (0x00000200uL) +#define INTC_ICDABR14_TINT42 (0x00000400uL) +#define INTC_ICDABR14_TINT43 (0x00000800uL) +#define INTC_ICDABR14_TINT44 (0x00001000uL) +#define INTC_ICDABR14_TINT45 (0x00002000uL) +#define INTC_ICDABR14_TINT46 (0x00004000uL) +#define INTC_ICDABR14_TINT47 (0x00008000uL) +#define INTC_ICDABR14_TINT48 (0x00010000uL) +#define INTC_ICDABR14_TINT49 (0x00020000uL) +#define INTC_ICDABR14_TINT50 (0x00040000uL) +#define INTC_ICDABR14_TINT51 (0x00080000uL) +#define INTC_ICDABR14_TINT52 (0x00100000uL) +#define INTC_ICDABR14_TINT53 (0x00200000uL) +#define INTC_ICDABR14_TINT54 (0x00400000uL) +#define INTC_ICDABR14_TINT55 (0x00800000uL) +#define INTC_ICDABR14_TINT56 (0x01000000uL) +#define INTC_ICDABR14_TINT57 (0x02000000uL) +#define INTC_ICDABR14_TINT58 (0x04000000uL) +#define INTC_ICDABR14_TINT59 (0x08000000uL) +#define INTC_ICDABR14_TINT60 (0x10000000uL) +#define INTC_ICDABR14_TINT61 (0x20000000uL) +#define INTC_ICDABR14_TINT62 (0x40000000uL) +#define INTC_ICDABR14_TINT63 (0x80000000uL) + +#define INTC_ICDABR15_TINT64 (0x00000001uL) +#define INTC_ICDABR15_TINT65 (0x00000002uL) +#define INTC_ICDABR15_TINT66 (0x00000004uL) +#define INTC_ICDABR15_TINT67 (0x00000008uL) +#define INTC_ICDABR15_TINT68 (0x00000010uL) +#define INTC_ICDABR15_TINT69 (0x00000020uL) +#define INTC_ICDABR15_TINT70 (0x00000040uL) +#define INTC_ICDABR15_TINT71 (0x00000080uL) +#define INTC_ICDABR15_TINT72 (0x00000100uL) +#define INTC_ICDABR15_TINT73 (0x00000200uL) +#define INTC_ICDABR15_TINT74 (0x00000400uL) +#define INTC_ICDABR15_TINT75 (0x00000800uL) +#define INTC_ICDABR15_TINT76 (0x00001000uL) +#define INTC_ICDABR15_TINT77 (0x00002000uL) +#define INTC_ICDABR15_TINT78 (0x00004000uL) +#define INTC_ICDABR15_TINT79 (0x00008000uL) +#define INTC_ICDABR15_TINT80 (0x00010000uL) +#define INTC_ICDABR15_TINT81 (0x00020000uL) +#define INTC_ICDABR15_TINT82 (0x00040000uL) +#define INTC_ICDABR15_TINT83 (0x00080000uL) +#define INTC_ICDABR15_TINT84 (0x00100000uL) +#define INTC_ICDABR15_TINT85 (0x00200000uL) +#define INTC_ICDABR15_TINT86 (0x00400000uL) +#define INTC_ICDABR15_TINT87 (0x00800000uL) +#define INTC_ICDABR15_TINT88 (0x01000000uL) +#define INTC_ICDABR15_TINT89 (0x02000000uL) +#define INTC_ICDABR15_TINT90 (0x04000000uL) +#define INTC_ICDABR15_TINT91 (0x08000000uL) +#define INTC_ICDABR15_TINT92 (0x10000000uL) +#define INTC_ICDABR15_TINT93 (0x20000000uL) +#define INTC_ICDABR15_TINT94 (0x40000000uL) +#define INTC_ICDABR15_TINT95 (0x80000000uL) + +#define INTC_ICDABR16_TINT96 (0x00000001uL) +#define INTC_ICDABR16_TINT97 (0x00000002uL) +#define INTC_ICDABR16_TINT98 (0x00000004uL) +#define INTC_ICDABR16_TINT99 (0x00000008uL) +#define INTC_ICDABR16_TINT100 (0x00000010uL) +#define INTC_ICDABR16_TINT101 (0x00000020uL) +#define INTC_ICDABR16_TINT102 (0x00000040uL) +#define INTC_ICDABR16_TINT103 (0x00000080uL) +#define INTC_ICDABR16_TINT104 (0x00000100uL) +#define INTC_ICDABR16_TINT105 (0x00000200uL) +#define INTC_ICDABR16_TINT106 (0x00000400uL) +#define INTC_ICDABR16_TINT107 (0x00000800uL) +#define INTC_ICDABR16_TINT108 (0x00001000uL) +#define INTC_ICDABR16_TINT109 (0x00002000uL) +#define INTC_ICDABR16_TINT110 (0x00004000uL) +#define INTC_ICDABR16_TINT111 (0x00008000uL) +#define INTC_ICDABR16_TINT112 (0x00010000uL) +#define INTC_ICDABR16_TINT113 (0x00020000uL) +#define INTC_ICDABR16_TINT114 (0x00040000uL) +#define INTC_ICDABR16_TINT115 (0x00080000uL) +#define INTC_ICDABR16_TINT116 (0x00100000uL) +#define INTC_ICDABR16_TINT117 (0x00200000uL) +#define INTC_ICDABR16_TINT118 (0x00400000uL) +#define INTC_ICDABR16_TINT119 (0x00800000uL) +#define INTC_ICDABR16_TINT120 (0x01000000uL) +#define INTC_ICDABR16_TINT121 (0x02000000uL) +#define INTC_ICDABR16_TINT122 (0x04000000uL) +#define INTC_ICDABR16_TINT123 (0x08000000uL) +#define INTC_ICDABR16_TINT124 (0x10000000uL) +#define INTC_ICDABR16_TINT125 (0x20000000uL) +#define INTC_ICDABR16_TINT126 (0x40000000uL) +#define INTC_ICDABR16_TINT127 (0x80000000uL) + +#define INTC_ICDABR17_TINT128 (0x00000001uL) +#define INTC_ICDABR17_TINT129 (0x00000002uL) +#define INTC_ICDABR17_TINT130 (0x00000004uL) +#define INTC_ICDABR17_TINT131 (0x00000008uL) +#define INTC_ICDABR17_TINT132 (0x00000010uL) +#define INTC_ICDABR17_TINT133 (0x00000020uL) +#define INTC_ICDABR17_TINT134 (0x00000040uL) +#define INTC_ICDABR17_TINT135 (0x00000080uL) +#define INTC_ICDABR17_TINT136 (0x00000100uL) +#define INTC_ICDABR17_TINT137 (0x00000200uL) +#define INTC_ICDABR17_TINT138 (0x00000400uL) +#define INTC_ICDABR17_TINT139 (0x00000800uL) +#define INTC_ICDABR17_TINT140 (0x00001000uL) +#define INTC_ICDABR17_TINT141 (0x00002000uL) +#define INTC_ICDABR17_TINT142 (0x00004000uL) +#define INTC_ICDABR17_TINT143 (0x00008000uL) +#define INTC_ICDABR17_TINT144 (0x00010000uL) +#define INTC_ICDABR17_TINT145 (0x00020000uL) +#define INTC_ICDABR17_TINT146 (0x00040000uL) +#define INTC_ICDABR17_TINT147 (0x00080000uL) +#define INTC_ICDABR17_TINT148 (0x00100000uL) +#define INTC_ICDABR17_TINT149 (0x00200000uL) +#define INTC_ICDABR17_TINT150 (0x00400000uL) +#define INTC_ICDABR17_TINT151 (0x00800000uL) +#define INTC_ICDABR17_TINT152 (0x01000000uL) +#define INTC_ICDABR17_TINT153 (0x02000000uL) +#define INTC_ICDABR17_TINT154 (0x04000000uL) +#define INTC_ICDABR17_TINT155 (0x08000000uL) +#define INTC_ICDABR17_TINT156 (0x10000000uL) +#define INTC_ICDABR17_TINT157 (0x20000000uL) +#define INTC_ICDABR17_TINT158 (0x40000000uL) +#define INTC_ICDABR17_TINT159 (0x80000000uL) + +#define INTC_ICDABR18_TINT160 (0x00000001uL) +#define INTC_ICDABR18_TINT161 (0x00000002uL) +#define INTC_ICDABR18_TINT162 (0x00000004uL) +#define INTC_ICDABR18_TINT163 (0x00000008uL) +#define INTC_ICDABR18_TINT164 (0x00000010uL) +#define INTC_ICDABR18_TINT165 (0x00000020uL) +#define INTC_ICDABR18_TINT166 (0x00000040uL) +#define INTC_ICDABR18_TINT167 (0x00000080uL) +#define INTC_ICDABR18_TINT168 (0x00000100uL) +#define INTC_ICDABR18_TINT169 (0x00000200uL) +#define INTC_ICDABR18_TINT170 (0x00000400uL) + +#define INTC_ICDIPR0_SW0 (0x000000FFuL) +#define INTC_ICDIPR0_SW1 (0x0000FF00uL) +#define INTC_ICDIPR0_SW2 (0x00FF0000uL) +#define INTC_ICDIPR0_SW3 (0xFF000000uL) + +#define INTC_ICDIPR1_SW4 (0x000000FFuL) +#define INTC_ICDIPR1_SW5 (0x0000FF00uL) +#define INTC_ICDIPR1_SW6 (0x00FF0000uL) +#define INTC_ICDIPR1_SW7 (0xFF000000uL) + +#define INTC_ICDIPR2_SW8 (0x000000FFuL) +#define INTC_ICDIPR2_SW9 (0x0000FF00uL) +#define INTC_ICDIPR2_SW10 (0x00FF0000uL) +#define INTC_ICDIPR2_SW11 (0xFF000000uL) + +#define INTC_ICDIPR3_SW12 (0x000000FFuL) +#define INTC_ICDIPR3_SW13 (0x0000FF00uL) +#define INTC_ICDIPR3_SW14 (0x00FF0000uL) +#define INTC_ICDIPR3_SW15 (0xFF000000uL) + +#define INTC_ICDIPR4_PMUIRQ0 (0x000000FFuL) +#define INTC_ICDIPR4_COMMRX0 (0x0000FF00uL) +#define INTC_ICDIPR4_COMMTX0 (0x00FF0000uL) +#define INTC_ICDIPR4_CTIIRQ0 (0xFF000000uL) + +#define INTC_ICDIPR8_IRQ0 (0x000000FFuL) +#define INTC_ICDIPR8_IRQ1 (0x0000FF00uL) +#define INTC_ICDIPR8_IRQ2 (0x00FF0000uL) +#define INTC_ICDIPR8_IRQ3 (0xFF000000uL) + +#define INTC_ICDIPR9_IRQ4 (0x000000FFuL) +#define INTC_ICDIPR9_IRQ5 (0x0000FF00uL) +#define INTC_ICDIPR9_IRQ6 (0x00FF0000uL) +#define INTC_ICDIPR9_IRQ7 (0xFF000000uL) + +#define INTC_ICDIPR10_PL310ERR (0x000000FFuL) +#define INTC_ICDIPR10_DMAINT0 (0x0000FF00uL) +#define INTC_ICDIPR10_DMAINT1 (0x00FF0000uL) +#define INTC_ICDIPR10_DMAINT2 (0xFF000000uL) + +#define INTC_ICDIPR11_DMAINT3 (0x000000FFuL) +#define INTC_ICDIPR11_DMAINT4 (0x0000FF00uL) +#define INTC_ICDIPR11_DMAINT5 (0x00FF0000uL) +#define INTC_ICDIPR11_DMAINT6 (0xFF000000uL) + +#define INTC_ICDIPR12_DMAINT7 (0x000000FFuL) +#define INTC_ICDIPR12_DMAINT8 (0x0000FF00uL) +#define INTC_ICDIPR12_DMAINT9 (0x00FF0000uL) +#define INTC_ICDIPR12_DMAINT10 (0xFF000000uL) + +#define INTC_ICDIPR13_DMAINT11 (0x000000FFuL) +#define INTC_ICDIPR13_DMAINT12 (0x0000FF00uL) +#define INTC_ICDIPR13_DMAINT13 (0x00FF0000uL) +#define INTC_ICDIPR13_DMAINT14 (0xFF000000uL) + +#define INTC_ICDIPR14_DMAINT15 (0x000000FFuL) +#define INTC_ICDIPR14_DMAERR (0x0000FF00uL) + +#define INTC_ICDIPR18_USBI0 (0x0000FF00uL) +#define INTC_ICDIPR18_USBI1 (0x00FF0000uL) +#define INTC_ICDIPR18_S0_VI_VSYNC0 (0xFF000000uL) + +#define INTC_ICDIPR19_S0_LO_VSYNC0 (0x000000FFuL) +#define INTC_ICDIPR19_S0_VSYNCERR0 (0x0000FF00uL) +#define INTC_ICDIPR19_GR3_VLINE0 (0x00FF0000uL) +#define INTC_ICDIPR19_S0_VFIELD0 (0xFF000000uL) + +#define INTC_ICDIPR20_IV1_VBUFERR0 (0x000000FFuL) +#define INTC_ICDIPR20_IV3_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPR20_IV5_VBUFERR0 (0x00FF0000uL) +#define INTC_ICDIPR20_IV6_VBUFERR0 (0xFF000000uL) + +#define INTC_ICDIPR21_S0_WLINE0 (0x000000FFuL) +#define INTC_ICDIPR21_S1_VI_VSYNC0 (0x0000FF00uL) +#define INTC_ICDIPR21_S1_LO_VSYNC0 (0x00FF0000uL) +#define INTC_ICDIPR21_S1_VSYNCERR0 (0xFF000000uL) + +#define INTC_ICDIPR22_S1_VFIELD0 (0x000000FFuL) +#define INTC_ICDIPR22_IV2_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPR22_IV4_VBUFERR0 (0x00FF0000uL) +#define INTC_ICDIPR22_S1_WLINE0 (0xFF000000uL) + +#define INTC_ICDIPR23_OIR_VI_VSYNC0 (0x000000FFuL) +#define INTC_ICDIPR23_OIR_LO_VSYNC0 (0x0000FF00uL) +#define INTC_ICDIPR23_OIR_VSYNCERR0 (0x00FF0000uL) +#define INTC_ICDIPR23_OIR_VFIELD0 (0xFF000000uL) + +#define INTC_ICDIPR24_IV7_VBUFERR0 (0x000000FFuL) +#define INTC_ICDIPR24_IV8_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPR24_S0_VI_VSYNC1 (0xFF000000uL) + +#define INTC_ICDIPR25_S0_LO_VSYNC1 (0x000000FFuL) +#define INTC_ICDIPR25_S0_VSYNCERR1 (0x0000FF00uL) +#define INTC_ICDIPR25_GR3_VLINE1 (0x00FF0000uL) +#define INTC_ICDIPR25_S0_VFIELD1 (0xFF000000uL) + +#define INTC_ICDIPR26_IV1_VBUFERR1 (0x000000FFuL) +#define INTC_ICDIPR26_IV3_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPR26_IV5_VBUFERR1 (0x00FF0000uL) +#define INTC_ICDIPR26_IV6_VBUFERR1 (0xFF000000uL) + +#define INTC_ICDIPR27_S0_WLINE1 (0x000000FFuL) +#define INTC_ICDIPR27_S1_VI_VSYNC1 (0x0000FF00uL) +#define INTC_ICDIPR27_S1_LO_VSYNC1 (0x00FF0000uL) +#define INTC_ICDIPR27_S1_VSYNCERR1 (0xFF000000uL) + +#define INTC_ICDIPR28_S1_VFIELD1 (0x000000FFuL) +#define INTC_ICDIPR28_IV2_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPR28_IV4_VBUFERR1 (0x00FF0000uL) +#define INTC_ICDIPR28_S1_WLINE1 (0xFF000000uL) + +#define INTC_ICDIPR29_OIR_VI_VSYNC1 (0x000000FFuL) +#define INTC_ICDIPR29_OIR_LO_VSYNC1 (0x0000FF00uL) +#define INTC_ICDIPR29_OIR_VLINE1 (0x00FF0000uL) +#define INTC_ICDIPR29_OIR_VFIELD1 (0xFF000000uL) + +#define INTC_ICDIPR30_IV7_VBUFERR1 (0x000000FFuL) +#define INTC_ICDIPR30_IV8_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPR30_IMRDI (0xFF000000uL) + +#define INTC_ICDIPR31_IMR2I0 (0x000000FFuL) +#define INTC_ICDIPR31_IMR2I1 (0x0000FF00uL) +#define INTC_ICDIPR31_JEDI (0x00FF0000uL) +#define INTC_ICDIPR31_JDTI (0xFF000000uL) + +#define INTC_ICDIPR32_CMP0 (0x000000FFuL) +#define INTC_ICDIPR32_CMP1 (0x0000FF00uL) +#define INTC_ICDIPR32_INT0 (0x00FF0000uL) +#define INTC_ICDIPR32_INT1 (0xFF000000uL) + +#define INTC_ICDIPR33_INT2 (0x000000FFuL) +#define INTC_ICDIPR33_INT3 (0x0000FF00uL) +#define INTC_ICDIPR33_OSTM0TINT (0x00FF0000uL) +#define INTC_ICDIPR33_OSTM1TINT (0xFF000000uL) + +#define INTC_ICDIPR34_CMI (0x000000FFuL) +#define INTC_ICDIPR34_WTOUT (0x0000FF00uL) +#define INTC_ICDIPR34_ITI (0x00FF0000uL) +#define INTC_ICDIPR34_TGI0A (0xFF000000uL) + +#define INTC_ICDIPR35_TGI0B (0x000000FFuL) +#define INTC_ICDIPR35_TGI0C (0x0000FF00uL) +#define INTC_ICDIPR35_TGI0D (0x00FF0000uL) +#define INTC_ICDIPR35_TGI0V (0xFF000000uL) + +#define INTC_ICDIPR36_TGI0E (0x000000FFuL) +#define INTC_ICDIPR36_TGI0F (0x0000FF00uL) +#define INTC_ICDIPR36_TGI1A (0x00FF0000uL) +#define INTC_ICDIPR36_TGI1B (0xFF000000uL) + +#define INTC_ICDIPR37_TGI1V (0x000000FFuL) +#define INTC_ICDIPR37_TGI1U (0x0000FF00uL) +#define INTC_ICDIPR37_TGI2A (0x00FF0000uL) +#define INTC_ICDIPR37_TGI2B (0xFF000000uL) + +#define INTC_ICDIPR38_TGI2V (0x000000FFuL) +#define INTC_ICDIPR38_TGI2U (0x0000FF00uL) +#define INTC_ICDIPR38_TGI3A (0x00FF0000uL) +#define INTC_ICDIPR38_TGI3B (0xFF000000uL) + +#define INTC_ICDIPR39_TGI3C (0x000000FFuL) +#define INTC_ICDIPR39_TGI3D (0x0000FF00uL) +#define INTC_ICDIPR39_TGI3V (0x00FF0000uL) +#define INTC_ICDIPR39_TGI4A (0xFF000000uL) + +#define INTC_ICDIPR40_TGI4B (0x000000FFuL) +#define INTC_ICDIPR40_TGI4C (0x0000FF00uL) +#define INTC_ICDIPR40_TGI4D (0x00FF0000uL) +#define INTC_ICDIPR40_TGI4V (0xFF000000uL) + +#define INTC_ICDIPR41_CMI1 (0x000000FFuL) +#define INTC_ICDIPR41_CMI2 (0x0000FF00uL) +#define INTC_ICDIPR41_SGDEI0 (0x00FF0000uL) +#define INTC_ICDIPR41_SGDEI1 (0xFF000000uL) + +#define INTC_ICDIPR42_SGDEI2 (0x000000FFuL) +#define INTC_ICDIPR42_SGDEI3 (0x0000FF00uL) +#define INTC_ICDIPR42_ADI (0x00FF0000uL) +#define INTC_ICDIPR42_LMTI (0xFF000000uL) + +#define INTC_ICDIPR43_SSII0 (0x000000FFuL) +#define INTC_ICDIPR43_SSIRXI0 (0x0000FF00uL) +#define INTC_ICDIPR43_SSITXI0 (0x00FF0000uL) +#define INTC_ICDIPR43_SSII1 (0xFF000000uL) + +#define INTC_ICDIPR44_SSIRXI1 (0x000000FFuL) +#define INTC_ICDIPR44_SSITXI1 (0x0000FF00uL) +#define INTC_ICDIPR44_SSII2 (0x00FF0000uL) +#define INTC_ICDIPR44_SSIRTI2 (0xFF000000uL) + +#define INTC_ICDIPR45_SSII3 (0x000000FFuL) +#define INTC_ICDIPR45_SSIRXI3 (0x0000FF00uL) +#define INTC_ICDIPR45_SSITXI3 (0x00FF0000uL) +#define INTC_ICDIPR45_SSII4 (0xFF000000uL) + +#define INTC_ICDIPR46_SSIRTI4 (0x000000FFuL) +#define INTC_ICDIPR46_SSII5 (0x0000FF00uL) +#define INTC_ICDIPR46_SSIRXI5 (0x00FF0000uL) +#define INTC_ICDIPR46_SSITXI5 (0xFF000000uL) + +#define INTC_ICDIPR47_SPDIFI (0x000000FFuL) +#define INTC_ICDIPR47_INTIICTEI0 (0x0000FF00uL) +#define INTC_ICDIPR47_INTIICRI0 (0x00FF0000uL) +#define INTC_ICDIPR47_INTIICTI0 (0xFF000000uL) + +#define INTC_ICDIPR48_INTIICSPI0 (0x000000FFuL) +#define INTC_ICDIPR48_INTIICSTI0 (0x0000FF00uL) +#define INTC_ICDIPR48_INTIICNAKI0 (0x00FF0000uL) +#define INTC_ICDIPR48_INTIICALI0 (0xFF000000uL) + +#define INTC_ICDIPR49_INTIICTMOI0 (0x000000FFuL) +#define INTC_ICDIPR49_INTIICTEI1 (0x0000FF00uL) +#define INTC_ICDIPR49_INTIICRI1 (0x00FF0000uL) +#define INTC_ICDIPR49_INTIICTI1 (0xFF000000uL) + +#define INTC_ICDIPR50_INTIICSPI1 (0x000000FFuL) +#define INTC_ICDIPR50_INTIICSTI1 (0x0000FF00uL) +#define INTC_ICDIPR50_INTIICNAKI1 (0x00FF0000uL) +#define INTC_ICDIPR50_INTIICALI1 (0xFF000000uL) + +#define INTC_ICDIPR51_INTIICTMOI1 (0x000000FFuL) +#define INTC_ICDIPR51_INTIICTEI2 (0x0000FF00uL) +#define INTC_ICDIPR51_INTIICRI2 (0x00FF0000uL) +#define INTC_ICDIPR51_INTIICTI2 (0xFF000000uL) + +#define INTC_ICDIPR52_INTIICSPI2 (0x000000FFuL) +#define INTC_ICDIPR52_INTIICSTI2 (0x0000FF00uL) +#define INTC_ICDIPR52_INTIICNAKI2 (0x00FF0000uL) +#define INTC_ICDIPR52_INTIICALI2 (0xFF000000uL) + +#define INTC_ICDIPR53_INTIICTMOI2 (0x000000FFuL) +#define INTC_ICDIPR53_INTIICTEI3 (0x0000FF00uL) +#define INTC_ICDIPR53_INTIICRI3 (0x00FF0000uL) +#define INTC_ICDIPR53_INTIICTI3 (0xFF000000uL) + +#define INTC_ICDIPR54_INTIICSPI3 (0x000000FFuL) +#define INTC_ICDIPR54_INTIICSTI3 (0x0000FF00uL) +#define INTC_ICDIPR54_INTIICNAKI3 (0x00FF0000uL) +#define INTC_ICDIPR54_INTIICALI3 (0xFF000000uL) + +#define INTC_ICDIPR55_INTIICTMOI3 (0x000000FFuL) +#define INTC_ICDIPR55_BRI0 (0x0000FF00uL) +#define INTC_ICDIPR55_ERI0 (0x00FF0000uL) +#define INTC_ICDIPR55_RXI0 (0xFF000000uL) + +#define INTC_ICDIPR56_TXI0 (0x000000FFuL) +#define INTC_ICDIPR56_BRI1 (0x0000FF00uL) +#define INTC_ICDIPR56_ERI1 (0x00FF0000uL) +#define INTC_ICDIPR56_RXI1 (0xFF000000uL) + +#define INTC_ICDIPR57_TXI1 (0x000000FFuL) +#define INTC_ICDIPR57_BRI2 (0x0000FF00uL) +#define INTC_ICDIPR57_ERI2 (0x00FF0000uL) +#define INTC_ICDIPR57_RXI2 (0xFF000000uL) + +#define INTC_ICDIPR58_TXI2 (0x000000FFuL) +#define INTC_ICDIPR58_BRI3 (0x0000FF00uL) +#define INTC_ICDIPR58_ERI3 (0x00FF0000uL) +#define INTC_ICDIPR58_RXI3 (0xFF000000uL) + +#define INTC_ICDIPR59_TXI3 (0x000000FFuL) +#define INTC_ICDIPR59_BRI4 (0x0000FF00uL) +#define INTC_ICDIPR59_ERI4 (0x00FF0000uL) +#define INTC_ICDIPR59_RXI4 (0xFF000000uL) + +#define INTC_ICDIPR60_TXI4 (0x000000FFuL) +#define INTC_ICDIPR60_BRI5 (0x0000FF00uL) +#define INTC_ICDIPR60_ERI5 (0x00FF0000uL) +#define INTC_ICDIPR60_RXI5 (0xFF000000uL) + +#define INTC_ICDIPR61_TXI5 (0x000000FFuL) +#define INTC_ICDIPR61_BRI6 (0x0000FF00uL) +#define INTC_ICDIPR61_ERI6 (0x00FF0000uL) +#define INTC_ICDIPR61_RXI6 (0xFF000000uL) + +#define INTC_ICDIPR62_TXI6 (0x000000FFuL) +#define INTC_ICDIPR62_BRI7 (0x0000FF00uL) +#define INTC_ICDIPR62_ERI7 (0x00FF0000uL) +#define INTC_ICDIPR62_RXI7 (0xFF000000uL) + +#define INTC_ICDIPR63_TXI7 (0x000000FFuL) +#define INTC_ICDIPR63_INTRCANGERR (0x0000FF00uL) +#define INTC_ICDIPR63_INTRCANGRECC (0x00FF0000uL) +#define INTC_ICDIPR63_INTRCAN0REC (0xFF000000uL) + +#define INTC_ICDIPR64_INTRCAN0ERR (0x000000FFuL) +#define INTC_ICDIPR64_INTRCAN0TRX (0x0000FF00uL) +#define INTC_ICDIPR64_INTRCAN1REC (0x00FF0000uL) +#define INTC_ICDIPR64_INTRCAN1ERR (0xFF000000uL) + +#define INTC_ICDIPR65_INTRCAN1TRX (0x000000FFuL) +#define INTC_ICDIPR65_INTRCAN2REC (0x0000FF00uL) +#define INTC_ICDIPR65_INTRCAN2ERR (0x00FF0000uL) +#define INTC_ICDIPR65_INTRCAN2TRX (0xFF000000uL) + +#define INTC_ICDIPR66_INTRCAN3REC (0x000000FFuL) +#define INTC_ICDIPR66_INTRCAN3ERR (0x0000FF00uL) +#define INTC_ICDIPR66_INTRCAN3TRX (0x00FF0000uL) +#define INTC_ICDIPR66_INTRCAN4REC (0xFF000000uL) + +#define INTC_ICDIPR67_INTRCAN4ERR (0x000000FFuL) +#define INTC_ICDIPR67_INTRCAN4TRX (0x0000FF00uL) +#define INTC_ICDIPR67_SPEI0 (0x00FF0000uL) +#define INTC_ICDIPR67_SPRI0 (0xFF000000uL) + +#define INTC_ICDIPR68_SPTI0 (0x000000FFuL) +#define INTC_ICDIPR68_SPEI1 (0x0000FF00uL) +#define INTC_ICDIPR68_SPRI1 (0x00FF0000uL) +#define INTC_ICDIPR68_SPTI1 (0xFF000000uL) + +#define INTC_ICDIPR69_SPEI2 (0x000000FFuL) +#define INTC_ICDIPR69_SPRI2 (0x0000FF00uL) +#define INTC_ICDIPR69_SPTI2 (0x00FF0000uL) +#define INTC_ICDIPR69_SPEI3 (0xFF000000uL) + +#define INTC_ICDIPR70_SPRI3 (0x000000FFuL) +#define INTC_ICDIPR70_SPTI3 (0x0000FF00uL) +#define INTC_ICDIPR70_SPEI4 (0x00FF0000uL) +#define INTC_ICDIPR70_SPRI4 (0xFF000000uL) + +#define INTC_ICDIPR71_SPTI4 (0x000000FFuL) +#define INTC_ICDIPR71_IEBBTD (0x0000FF00uL) +#define INTC_ICDIPR71_IEBBTERR (0x00FF0000uL) +#define INTC_ICDIPR71_IEBBTSTA (0xFF000000uL) + +#define INTC_ICDIPR72_IEBBTV (0x000000FFuL) +#define INTC_ICDIPR72_ISY (0x0000FF00uL) +#define INTC_ICDIPR72_IERR (0x00FF0000uL) +#define INTC_ICDIPR72_ITARG (0xFF000000uL) + +#define INTC_ICDIPR73_ISEC (0x000000FFuL) +#define INTC_ICDIPR73_IBUF (0x0000FF00uL) +#define INTC_ICDIPR73_IREADY (0x00FF0000uL) +#define INTC_ICDIPR73_FLSTE (0xFF000000uL) + +#define INTC_ICDIPR74_FLTENDI (0x000000FFuL) +#define INTC_ICDIPR74_FLTREQ0I (0x0000FF00uL) +#define INTC_ICDIPR74_FLTREQ1I (0x00FF0000uL) +#define INTC_ICDIPR74_MMC0 (0xFF000000uL) + +#define INTC_ICDIPR75_MMC1 (0x000000FFuL) +#define INTC_ICDIPR75_MMC2 (0x0000FF00uL) +#define INTC_ICDIPR75_SDHI0_3 (0x00FF0000uL) +#define INTC_ICDIPR75_SDHI0_0 (0xFF000000uL) + +#define INTC_ICDIPR76_SDHI0_1 (0x000000FFuL) +#define INTC_ICDIPR76_SDHI1_3 (0x0000FF00uL) +#define INTC_ICDIPR76_SDHI1_0 (0x00FF0000uL) +#define INTC_ICDIPR76_SDHI1_1 (0xFF000000uL) + +#define INTC_ICDIPR77_ARM (0x000000FFuL) +#define INTC_ICDIPR77_PRD (0x0000FF00uL) +#define INTC_ICDIPR77_CUP (0x00FF0000uL) +#define INTC_ICDIPR77_SCUAI0 (0xFF000000uL) + +#define INTC_ICDIPR78_SCUAI1 (0x000000FFuL) +#define INTC_ICDIPR78_SCUFDI0 (0x0000FF00uL) +#define INTC_ICDIPR78_SCUFDI1 (0x00FF0000uL) +#define INTC_ICDIPR78_SCUFDI2 (0xFF000000uL) + +#define INTC_ICDIPR79_SCUFDI3 (0x000000FFuL) +#define INTC_ICDIPR79_SCUFUI0 (0x0000FF00uL) +#define INTC_ICDIPR79_SCUFUI1 (0x00FF0000uL) +#define INTC_ICDIPR79_SCUFUI2 (0xFF000000uL) + +#define INTC_ICDIPR80_SCUFUI3 (0x000000FFuL) +#define INTC_ICDIPR80_SCUDVI0 (0x0000FF00uL) +#define INTC_ICDIPR80_SCUDVI1 (0x00FF0000uL) +#define INTC_ICDIPR80_SCUDVI2 (0xFF000000uL) + +#define INTC_ICDIPR81_SCUDVI3 (0x000000FFuL) +#define INTC_ICDIPR81_MLB_CINT (0x0000FF00uL) +#define INTC_ICDIPR81_MLB_SINT (0x00FF0000uL) +#define INTC_ICDIPR81_DRC0 (0xFF000000uL) + +#define INTC_ICDIPR82_DRC1 (0x000000FFuL) +#define INTC_ICDIPR82_LINI0_INT_T (0xFF000000uL) + +#define INTC_ICDIPR83_LINI0_INT_R (0x000000FFuL) +#define INTC_ICDIPR83_LINI0_INT_S (0x0000FF00uL) +#define INTC_ICDIPR83_LINI0_INT_M (0x00FF0000uL) +#define INTC_ICDIPR83_LINI1_INT_T (0xFF000000uL) + +#define INTC_ICDIPR84_LINI1_INT_R (0x000000FFuL) +#define INTC_ICDIPR84_LINI1_INT_S (0x0000FF00uL) +#define INTC_ICDIPR84_LINI1_INT_M (0x00FF0000uL) + +#define INTC_ICDIPR86_ERI0 (0xFF000000uL) + +#define INTC_ICDIPR87_RXI0 (0x000000FFuL) +#define INTC_ICDIPR87_TXI0 (0x0000FF00uL) +#define INTC_ICDIPR87_TEI0 (0x00FF0000uL) +#define INTC_ICDIPR87_ERI1 (0xFF000000uL) + +#define INTC_ICDIPR88_RXI1 (0x000000FFuL) +#define INTC_ICDIPR88_TXI1 (0x0000FF00uL) +#define INTC_ICDIPR88_TEI1 (0x00FF0000uL) +#define INTC_ICDIPR88_AVBI_DATA (0xFF000000uL) + +#define INTC_ICDIPR89_AVBI_ERROR (0x000000FFuL) +#define INTC_ICDIPR89_AVBI_MANAGE (0x0000FF00uL) +#define INTC_ICDIPR89_AVBI_MAC (0x00FF0000uL) +#define INTC_ICDIPR89_ETHERI (0xFF000000uL) + +#define INTC_ICDIPR91_CEUI (0x000000FFuL) + +#define INTC_ICDIPR95_H2XMLB_ERRINT (0x0000FF00uL) +#define INTC_ICDIPR95_H2XIC1_ERRINT (0x00FF0000uL) +#define INTC_ICDIPR95_X2HPERI1_ERRINT (0xFF000000uL) + +#define INTC_ICDIPR96_X2HPERI2_ERRINT (0x000000FFuL) +#define INTC_ICDIPR96_X2HPERI34_ERRINT (0x0000FF00uL) +#define INTC_ICDIPR96_X2HPERI5_ERRINT (0x00FF0000uL) +#define INTC_ICDIPR96_X2HPERI67_ERRINT (0xFF000000uL) + +#define INTC_ICDIPR97_X2HDBGR_ERRINT (0x000000FFuL) +#define INTC_ICDIPR97_X2HBSC_ERRINT (0x0000FF00uL) +#define INTC_ICDIPR97_X2HSPI1_ERRINT (0x00FF0000uL) +#define INTC_ICDIPR97_X2HSPI2_ERRINT (0xFF000000uL) + +#define INTC_ICDIPR98_PRRI (0x000000FFuL) +#define INTC_ICDIPR98_IFEI0 (0x0000FF00uL) +#define INTC_ICDIPR98_OFFI0 (0x00FF0000uL) +#define INTC_ICDIPR98_PFVEI0 (0xFF000000uL) + +#define INTC_ICDIPR99_IFEI1 (0x000000FFuL) +#define INTC_ICDIPR99_OFFI1 (0x0000FF00uL) +#define INTC_ICDIPR99_PFVEI1 (0x00FF0000uL) + +#define INTC_ICDIPR104_TINT0 (0x000000FFuL) +#define INTC_ICDIPR104_TINT1 (0x0000FF00uL) +#define INTC_ICDIPR104_TINT2 (0x00FF0000uL) +#define INTC_ICDIPR104_TINT3 (0xFF000000uL) + +#define INTC_ICDIPR105_TINT4 (0x000000FFuL) +#define INTC_ICDIPR105_TINT5 (0x0000FF00uL) +#define INTC_ICDIPR105_TINT6 (0x00FF0000uL) +#define INTC_ICDIPR105_TINT7 (0xFF000000uL) + +#define INTC_ICDIPR106_TINT8 (0x000000FFuL) +#define INTC_ICDIPR106_TINT9 (0x0000FF00uL) +#define INTC_ICDIPR106_TINT10 (0x00FF0000uL) +#define INTC_ICDIPR106_TINT11 (0xFF000000uL) + +#define INTC_ICDIPR107_TINT12 (0x000000FFuL) +#define INTC_ICDIPR107_TINT13 (0x0000FF00uL) +#define INTC_ICDIPR107_TINT14 (0x00FF0000uL) +#define INTC_ICDIPR107_TINT15 (0xFF000000uL) + +#define INTC_ICDIPR108_TINT16 (0x000000FFuL) +#define INTC_ICDIPR108_TINT17 (0x0000FF00uL) +#define INTC_ICDIPR108_TINT18 (0x00FF0000uL) +#define INTC_ICDIPR108_TINT19 (0xFF000000uL) + +#define INTC_ICDIPR109_TINT20 (0x000000FFuL) +#define INTC_ICDIPR109_TINT21 (0x0000FF00uL) +#define INTC_ICDIPR109_TINT22 (0x00FF0000uL) +#define INTC_ICDIPR109_TINT23 (0xFF000000uL) + +#define INTC_ICDIPR110_TINT24 (0x000000FFuL) +#define INTC_ICDIPR110_TINT25 (0x0000FF00uL) +#define INTC_ICDIPR110_TINT26 (0x00FF0000uL) +#define INTC_ICDIPR110_TINT27 (0xFF000000uL) + +#define INTC_ICDIPR111_TINT28 (0x000000FFuL) +#define INTC_ICDIPR111_TINT29 (0x0000FF00uL) +#define INTC_ICDIPR111_TINT30 (0x00FF0000uL) +#define INTC_ICDIPR111_TINT31 (0xFF000000uL) + +#define INTC_ICDIPR112_TINT32 (0x000000FFuL) +#define INTC_ICDIPR112_TINT33 (0x0000FF00uL) +#define INTC_ICDIPR112_TINT34 (0x00FF0000uL) +#define INTC_ICDIPR112_TINT35 (0xFF000000uL) + +#define INTC_ICDIPR113_TINT36 (0x000000FFuL) +#define INTC_ICDIPR113_TINT37 (0x0000FF00uL) +#define INTC_ICDIPR113_TINT38 (0x00FF0000uL) +#define INTC_ICDIPR113_TINT39 (0xFF000000uL) + +#define INTC_ICDIPR114_TINT40 (0x000000FFuL) +#define INTC_ICDIPR114_TINT41 (0x0000FF00uL) +#define INTC_ICDIPR114_TINT42 (0x00FF0000uL) +#define INTC_ICDIPR114_TINT43 (0xFF000000uL) + +#define INTC_ICDIPR115_TINT44 (0x000000FFuL) +#define INTC_ICDIPR115_TINT45 (0x0000FF00uL) +#define INTC_ICDIPR115_TINT46 (0x00FF0000uL) +#define INTC_ICDIPR115_TINT47 (0xFF000000uL) + +#define INTC_ICDIPR116_TINT48 (0x000000FFuL) +#define INTC_ICDIPR116_TINT49 (0x0000FF00uL) +#define INTC_ICDIPR116_TINT50 (0x00FF0000uL) +#define INTC_ICDIPR116_TINT51 (0xFF000000uL) + +#define INTC_ICDIPR117_TINT52 (0x000000FFuL) +#define INTC_ICDIPR117_TINT53 (0x0000FF00uL) +#define INTC_ICDIPR117_TINT54 (0x00FF0000uL) +#define INTC_ICDIPR117_TINT55 (0xFF000000uL) + +#define INTC_ICDIPR118_TINT56 (0x000000FFuL) +#define INTC_ICDIPR118_TINT57 (0x0000FF00uL) +#define INTC_ICDIPR118_TINT58 (0x00FF0000uL) +#define INTC_ICDIPR118_TINT59 (0xFF000000uL) + +#define INTC_ICDIPR119_TINT60 (0x000000FFuL) +#define INTC_ICDIPR119_TINT61 (0x0000FF00uL) +#define INTC_ICDIPR119_TINT62 (0x00FF0000uL) +#define INTC_ICDIPR119_TINT63 (0xFF000000uL) + +#define INTC_ICDIPR120_TINT64 (0x000000FFuL) +#define INTC_ICDIPR120_TINT65 (0x0000FF00uL) +#define INTC_ICDIPR120_TINT66 (0x00FF0000uL) +#define INTC_ICDIPR120_TINT67 (0xFF000000uL) + +#define INTC_ICDIPR121_TINT68 (0x000000FFuL) +#define INTC_ICDIPR121_TINT69 (0x0000FF00uL) +#define INTC_ICDIPR121_TINT70 (0x00FF0000uL) +#define INTC_ICDIPR121_TINT71 (0xFF000000uL) + +#define INTC_ICDIPR122_TINT72 (0x000000FFuL) +#define INTC_ICDIPR122_TINT73 (0x0000FF00uL) +#define INTC_ICDIPR122_TINT74 (0x00FF0000uL) +#define INTC_ICDIPR122_TINT75 (0xFF000000uL) + +#define INTC_ICDIPR123_TINT76 (0x000000FFuL) +#define INTC_ICDIPR123_TINT77 (0x0000FF00uL) +#define INTC_ICDIPR123_TINT78 (0x00FF0000uL) +#define INTC_ICDIPR123_TINT79 (0xFF000000uL) + +#define INTC_ICDIPR124_TINT80 (0x000000FFuL) +#define INTC_ICDIPR124_TINT81 (0x0000FF00uL) +#define INTC_ICDIPR124_TINT82 (0x00FF0000uL) +#define INTC_ICDIPR124_TINT83 (0xFF000000uL) + +#define INTC_ICDIPR125_TINT84 (0x000000FFuL) +#define INTC_ICDIPR125_TINT85 (0x0000FF00uL) +#define INTC_ICDIPR125_TINT86 (0x00FF0000uL) +#define INTC_ICDIPR125_TINT87 (0xFF000000uL) + +#define INTC_ICDIPR126_TINT88 (0x000000FFuL) +#define INTC_ICDIPR126_TINT89 (0x0000FF00uL) +#define INTC_ICDIPR126_TINT90 (0x00FF0000uL) +#define INTC_ICDIPR126_TINT91 (0xFF000000uL) + +#define INTC_ICDIPR127_TINT92 (0x000000FFuL) +#define INTC_ICDIPR127_TINT93 (0x0000FF00uL) +#define INTC_ICDIPR127_TINT94 (0x00FF0000uL) +#define INTC_ICDIPR127_TINT95 (0xFF000000uL) + +#define INTC_ICDIPR128_TINT96 (0x000000FFuL) +#define INTC_ICDIPR128_TINT97 (0x0000FF00uL) +#define INTC_ICDIPR128_TINT98 (0x00FF0000uL) +#define INTC_ICDIPR128_TINT99 (0xFF000000uL) + +#define INTC_ICDIPR129_TINT100 (0x000000FFuL) +#define INTC_ICDIPR129_TINT101 (0x0000FF00uL) +#define INTC_ICDIPR129_TINT102 (0x00FF0000uL) +#define INTC_ICDIPR129_TINT103 (0xFF000000uL) + +#define INTC_ICDIPR130_TINT104 (0x000000FFuL) +#define INTC_ICDIPR130_TINT105 (0x0000FF00uL) +#define INTC_ICDIPR130_TINT106 (0x00FF0000uL) +#define INTC_ICDIPR130_TINT107 (0xFF000000uL) + +#define INTC_ICDIPR131_TINT108 (0x000000FFuL) +#define INTC_ICDIPR131_TINT109 (0x0000FF00uL) +#define INTC_ICDIPR131_TINT110 (0x00FF0000uL) +#define INTC_ICDIPR131_TINT111 (0xFF000000uL) + +#define INTC_ICDIPR132_TINT112 (0x000000FFuL) +#define INTC_ICDIPR132_TINT113 (0x0000FF00uL) +#define INTC_ICDIPR132_TINT114 (0x00FF0000uL) +#define INTC_ICDIPR132_TINT115 (0xFF000000uL) + +#define INTC_ICDIPR133_TINT116 (0x000000FFuL) +#define INTC_ICDIPR133_TINT117 (0x0000FF00uL) +#define INTC_ICDIPR133_TINT118 (0x00FF0000uL) +#define INTC_ICDIPR133_TINT119 (0xFF000000uL) + +#define INTC_ICDIPR134_TINT120 (0x000000FFuL) +#define INTC_ICDIPR134_TINT121 (0x0000FF00uL) +#define INTC_ICDIPR134_TINT122 (0x00FF0000uL) +#define INTC_ICDIPR134_TINT123 (0xFF000000uL) + +#define INTC_ICDIPR135_TINT124 (0x000000FFuL) +#define INTC_ICDIPR135_TINT125 (0x0000FF00uL) +#define INTC_ICDIPR135_TINT126 (0x00FF0000uL) +#define INTC_ICDIPR135_TINT127 (0xFF000000uL) + +#define INTC_ICDIPR136_TINT128 (0x000000FFuL) +#define INTC_ICDIPR136_TINT129 (0x0000FF00uL) +#define INTC_ICDIPR136_TINT130 (0x00FF0000uL) +#define INTC_ICDIPR136_TINT131 (0xFF000000uL) + +#define INTC_ICDIPR137_TINT132 (0x000000FFuL) +#define INTC_ICDIPR137_TINT133 (0x0000FF00uL) +#define INTC_ICDIPR137_TINT134 (0x00FF0000uL) +#define INTC_ICDIPR137_TINT135 (0xFF000000uL) + +#define INTC_ICDIPR138_TINT136 (0x000000FFuL) +#define INTC_ICDIPR138_TINT137 (0x0000FF00uL) +#define INTC_ICDIPR138_TINT138 (0x00FF0000uL) +#define INTC_ICDIPR138_TINT139 (0xFF000000uL) + +#define INTC_ICDIPR139_TINT140 (0x000000FFuL) +#define INTC_ICDIPR139_TINT141 (0x0000FF00uL) +#define INTC_ICDIPR139_TINT142 (0x00FF0000uL) +#define INTC_ICDIPR139_TINT143 (0xFF000000uL) + +#define INTC_ICDIPR140_TINT144 (0x000000FFuL) +#define INTC_ICDIPR140_TINT145 (0x0000FF00uL) +#define INTC_ICDIPR140_TINT146 (0x00FF0000uL) +#define INTC_ICDIPR140_TINT147 (0xFF000000uL) + +#define INTC_ICDIPR141_TINT148 (0x000000FFuL) +#define INTC_ICDIPR141_TINT149 (0x0000FF00uL) +#define INTC_ICDIPR141_TINT150 (0x00FF0000uL) +#define INTC_ICDIPR141_TINT151 (0xFF000000uL) + +#define INTC_ICDIPR142_TINT152 (0x000000FFuL) +#define INTC_ICDIPR142_TINT153 (0x0000FF00uL) +#define INTC_ICDIPR142_TINT154 (0x00FF0000uL) +#define INTC_ICDIPR142_TINT155 (0xFF000000uL) + +#define INTC_ICDIPR143_TINT156 (0x000000FFuL) +#define INTC_ICDIPR143_TINT157 (0x0000FF00uL) +#define INTC_ICDIPR143_TINT158 (0x00FF0000uL) +#define INTC_ICDIPR143_TINT159 (0xFF000000uL) + +#define INTC_ICDIPR144_TINT160 (0x000000FFuL) +#define INTC_ICDIPR144_TINT161 (0x0000FF00uL) +#define INTC_ICDIPR144_TINT162 (0x00FF0000uL) +#define INTC_ICDIPR144_TINT163 (0xFF000000uL) + +#define INTC_ICDIPR145_TINT164 (0x000000FFuL) +#define INTC_ICDIPR145_TINT165 (0x0000FF00uL) +#define INTC_ICDIPR145_TINT166 (0x00FF0000uL) +#define INTC_ICDIPR145_TINT167 (0xFF000000uL) + +#define INTC_ICDIPR146_TINT168 (0x000000FFuL) +#define INTC_ICDIPR146_TINT169 (0x0000FF00uL) +#define INTC_ICDIPR146_TINT170 (0x00FF0000uL) + +#define INTC_ICDIPTR0_SW0 (0x000000FFuL) +#define INTC_ICDIPTR0_SW1 (0x0000FF00uL) +#define INTC_ICDIPTR0_SW2 (0x00FF0000uL) +#define INTC_ICDIPTR0_SW3 (0xFF000000uL) + +#define INTC_ICDIPTR1_SW4 (0x000000FFuL) +#define INTC_ICDIPTR1_SW5 (0x0000FF00uL) +#define INTC_ICDIPTR1_SW6 (0x00FF0000uL) +#define INTC_ICDIPTR1_SW7 (0xFF000000uL) + +#define INTC_ICDIPTR2_SW8 (0x000000FFuL) +#define INTC_ICDIPTR2_SW9 (0x0000FF00uL) +#define INTC_ICDIPTR2_SW10 (0x00FF0000uL) +#define INTC_ICDIPTR2_SW11 (0xFF000000uL) + +#define INTC_ICDIPTR3_SW12 (0x000000FFuL) +#define INTC_ICDIPTR3_SW13 (0x0000FF00uL) +#define INTC_ICDIPTR3_SW14 (0x00FF0000uL) +#define INTC_ICDIPTR3_SW15 (0xFF000000uL) + +#define INTC_ICDIPTR4_PMUIRQ0 (0x000000FFuL) +#define INTC_ICDIPTR4_COMMRX0 (0x0000FF00uL) +#define INTC_ICDIPTR4_COMMTX0 (0x00FF0000uL) +#define INTC_ICDIPTR4_CTIIRQ0 (0xFF000000uL) + +#define INTC_ICDIPTR8_IRQ0 (0x000000FFuL) +#define INTC_ICDIPTR8_IRQ1 (0x0000FF00uL) +#define INTC_ICDIPTR8_IRQ2 (0x00FF0000uL) +#define INTC_ICDIPTR8_IRQ3 (0xFF000000uL) + +#define INTC_ICDIPTR9_IRQ4 (0x000000FFuL) +#define INTC_ICDIPTR9_IRQ5 (0x0000FF00uL) +#define INTC_ICDIPTR9_IRQ6 (0x00FF0000uL) +#define INTC_ICDIPTR9_IRQ7 (0xFF000000uL) + +#define INTC_ICDIPTR10_PL310ERR (0x000000FFuL) +#define INTC_ICDIPTR10_DMAINT0 (0x0000FF00uL) +#define INTC_ICDIPTR10_DMAINT1 (0x00FF0000uL) +#define INTC_ICDIPTR10_DMAINT2 (0xFF000000uL) + +#define INTC_ICDIPTR11_DMAINT3 (0x000000FFuL) +#define INTC_ICDIPTR11_DMAINT4 (0x0000FF00uL) +#define INTC_ICDIPTR11_DMAINT5 (0x00FF0000uL) +#define INTC_ICDIPTR11_DMAINT6 (0xFF000000uL) + +#define INTC_ICDIPTR12_DMAINT7 (0x000000FFuL) +#define INTC_ICDIPTR12_DMAINT8 (0x0000FF00uL) +#define INTC_ICDIPTR12_DMAINT9 (0x00FF0000uL) +#define INTC_ICDIPTR12_DMAINT10 (0xFF000000uL) + +#define INTC_ICDIPTR13_DMAINT11 (0x000000FFuL) +#define INTC_ICDIPTR13_DMAINT12 (0x0000FF00uL) +#define INTC_ICDIPTR13_DMAINT13 (0x00FF0000uL) +#define INTC_ICDIPTR13_DMAINT14 (0xFF000000uL) + +#define INTC_ICDIPTR14_DMAINT15 (0x000000FFuL) +#define INTC_ICDIPTR14_DMAERR (0x0000FF00uL) + +#define INTC_ICDIPTR18_USBI0 (0x0000FF00uL) +#define INTC_ICDIPTR18_USBI1 (0x00FF0000uL) +#define INTC_ICDIPTR18_S0_VI_VSYNC0 (0xFF000000uL) + +#define INTC_ICDIPTR19_S0_LO_VSYNC0 (0x000000FFuL) +#define INTC_ICDIPTR19_S0_VSYNCERR0 (0x0000FF00uL) +#define INTC_ICDIPTR19_GR3_VLINE0 (0x00FF0000uL) +#define INTC_ICDIPTR19_S0_VFIELD0 (0xFF000000uL) + +#define INTC_ICDIPTR20_IV1_VBUFERR0 (0x000000FFuL) +#define INTC_ICDIPTR20_IV3_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPTR20_IV5_VBUFERR0 (0x00FF0000uL) +#define INTC_ICDIPTR20_IV6_VBUFERR0 (0xFF000000uL) + +#define INTC_ICDIPTR21_S0_WLINE0 (0x000000FFuL) +#define INTC_ICDIPTR21_S1_VI_VSYNC0 (0x0000FF00uL) +#define INTC_ICDIPTR21_S1_LO_VSYNC0 (0x00FF0000uL) +#define INTC_ICDIPTR21_S1_VSYNCERR0 (0xFF000000uL) + +#define INTC_ICDIPTR22_S1_VFIELD0 (0x000000FFuL) +#define INTC_ICDIPTR22_IV2_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPTR22_IV4_VBUFERR0 (0x00FF0000uL) +#define INTC_ICDIPTR22_S1_WLINE0 (0xFF000000uL) + +#define INTC_ICDIPTR23_OIR_VI_VSYNC0 (0x000000FFuL) +#define INTC_ICDIPTR23_OIR_LO_VSYNC0 (0x0000FF00uL) +#define INTC_ICDIPTR23_OIR_VSYNCERR0 (0x00FF0000uL) +#define INTC_ICDIPTR23_OIR_VFIELD0 (0xFF000000uL) + +#define INTC_ICDIPTR24_IV7_VBUFERR0 (0x000000FFuL) +#define INTC_ICDIPTR24_IV8_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPTR24_S0_VI_VSYNC1 (0xFF000000uL) + +#define INTC_ICDIPTR25_S0_LO_VSYNC1 (0x000000FFuL) +#define INTC_ICDIPTR25_S0_VSYNCERR1 (0x0000FF00uL) +#define INTC_ICDIPTR25_GR3_VLINE1 (0x00FF0000uL) +#define INTC_ICDIPTR25_S0_VFIELD1 (0xFF000000uL) + +#define INTC_ICDIPTR26_IV1_VBUFERR1 (0x000000FFuL) +#define INTC_ICDIPTR26_IV3_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPTR26_IV5_VBUFERR1 (0x00FF0000uL) +#define INTC_ICDIPTR26_IV6_VBUFERR1 (0xFF000000uL) + +#define INTC_ICDIPTR27_S0_WLINE1 (0x000000FFuL) +#define INTC_ICDIPTR27_S1_VI_VSYNC1 (0x0000FF00uL) +#define INTC_ICDIPTR27_S1_LO_VSYNC1 (0x00FF0000uL) +#define INTC_ICDIPTR27_S1_VSYNCERR1 (0xFF000000uL) + +#define INTC_ICDIPTR28_S1_VFIELD1 (0x000000FFuL) +#define INTC_ICDIPTR28_IV2_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPTR28_IV4_VBUFERR1 (0x00FF0000uL) +#define INTC_ICDIPTR28_S1_WLINE1 (0xFF000000uL) + +#define INTC_ICDIPTR29_OIR_VI_VSYNC1 (0x000000FFuL) +#define INTC_ICDIPTR29_OIR_LO_VSYNC1 (0x0000FF00uL) +#define INTC_ICDIPTR29_OIR_VLINE1 (0x00FF0000uL) +#define INTC_ICDIPTR29_OIR_VFIELD1 (0xFF000000uL) + +#define INTC_ICDIPTR30_IV7_VBUFERR1 (0x000000FFuL) +#define INTC_ICDIPTR30_IV8_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPTR30_IMRDI (0xFF000000uL) + +#define INTC_ICDIPTR31_IMR2I0 (0x000000FFuL) +#define INTC_ICDIPTR31_IMR2I1 (0x0000FF00uL) +#define INTC_ICDIPTR31_JEDI (0x00FF0000uL) +#define INTC_ICDIPTR31_JDTI (0xFF000000uL) + +#define INTC_ICDIPTR32_CMP0 (0x000000FFuL) +#define INTC_ICDIPTR32_CMP1 (0x0000FF00uL) +#define INTC_ICDIPTR32_INT0 (0x00FF0000uL) +#define INTC_ICDIPTR32_INT1 (0xFF000000uL) + +#define INTC_ICDIPTR33_INT2 (0x000000FFuL) +#define INTC_ICDIPTR33_INT3 (0x0000FF00uL) +#define INTC_ICDIPTR33_OSTM0TINT (0x00FF0000uL) +#define INTC_ICDIPTR33_OSTM1TINT (0xFF000000uL) + +#define INTC_ICDIPTR34_CMI (0x000000FFuL) +#define INTC_ICDIPTR34_WTOUT (0x0000FF00uL) +#define INTC_ICDIPTR34_ITI (0x00FF0000uL) +#define INTC_ICDIPTR34_TGI0A (0xFF000000uL) + +#define INTC_ICDIPTR35_TGI0B (0x000000FFuL) +#define INTC_ICDIPTR35_TGI0C (0x0000FF00uL) +#define INTC_ICDIPTR35_TGI0D (0x00FF0000uL) +#define INTC_ICDIPTR35_TGI0V (0xFF000000uL) + +#define INTC_ICDIPTR36_TGI0E (0x000000FFuL) +#define INTC_ICDIPTR36_TGI0F (0x0000FF00uL) +#define INTC_ICDIPTR36_TGI1A (0x00FF0000uL) +#define INTC_ICDIPTR36_TGI1B (0xFF000000uL) + +#define INTC_ICDIPTR37_TGI1V (0x000000FFuL) +#define INTC_ICDIPTR37_TGI1U (0x0000FF00uL) +#define INTC_ICDIPTR37_TGI2A (0x00FF0000uL) +#define INTC_ICDIPTR37_TGI2B (0xFF000000uL) + +#define INTC_ICDIPTR38_TGI2V (0x000000FFuL) +#define INTC_ICDIPTR38_TGI2U (0x0000FF00uL) +#define INTC_ICDIPTR38_TGI3A (0x00FF0000uL) +#define INTC_ICDIPTR38_TGI3B (0xFF000000uL) + +#define INTC_ICDIPTR39_TGI3C (0x000000FFuL) +#define INTC_ICDIPTR39_TGI3D (0x0000FF00uL) +#define INTC_ICDIPTR39_TGI3V (0x00FF0000uL) +#define INTC_ICDIPTR39_TGI4A (0xFF000000uL) + +#define INTC_ICDIPTR40_TGI4B (0x000000FFuL) +#define INTC_ICDIPTR40_TGI4C (0x0000FF00uL) +#define INTC_ICDIPTR40_TGI4D (0x00FF0000uL) +#define INTC_ICDIPTR40_TGI4V (0xFF000000uL) + +#define INTC_ICDIPTR41_CMI1 (0x000000FFuL) +#define INTC_ICDIPTR41_CMI2 (0x0000FF00uL) +#define INTC_ICDIPTR41_SGDEI0 (0x00FF0000uL) +#define INTC_ICDIPTR41_SGDEI1 (0xFF000000uL) + +#define INTC_ICDIPTR42_SGDEI2 (0x000000FFuL) +#define INTC_ICDIPTR42_SGDEI3 (0x0000FF00uL) +#define INTC_ICDIPTR42_ADI (0x00FF0000uL) +#define INTC_ICDIPTR42_LMTI (0xFF000000uL) + +#define INTC_ICDIPTR43_SSII0 (0x000000FFuL) +#define INTC_ICDIPTR43_SSIRXI0 (0x0000FF00uL) +#define INTC_ICDIPTR43_SSITXI0 (0x00FF0000uL) +#define INTC_ICDIPTR43_SSII1 (0xFF000000uL) + +#define INTC_ICDIPTR44_SSIRXI1 (0x000000FFuL) +#define INTC_ICDIPTR44_SSITXI1 (0x0000FF00uL) +#define INTC_ICDIPTR44_SSII2 (0x00FF0000uL) +#define INTC_ICDIPTR44_SSIRTI2 (0xFF000000uL) + +#define INTC_ICDIPTR45_SSII3 (0x000000FFuL) +#define INTC_ICDIPTR45_SSIRXI3 (0x0000FF00uL) +#define INTC_ICDIPTR45_SSITXI3 (0x00FF0000uL) +#define INTC_ICDIPTR45_SSII4 (0xFF000000uL) + +#define INTC_ICDIPTR46_SSIRTI4 (0x000000FFuL) +#define INTC_ICDIPTR46_SSII5 (0x0000FF00uL) +#define INTC_ICDIPTR46_SSIRXI5 (0x00FF0000uL) +#define INTC_ICDIPTR46_SSITXI5 (0xFF000000uL) + +#define INTC_ICDIPTR47_SPDIFI (0x000000FFuL) +#define INTC_ICDIPTR47_INTIICTEI0 (0x0000FF00uL) +#define INTC_ICDIPTR47_INTIICRI0 (0x00FF0000uL) +#define INTC_ICDIPTR47_INTIICTI0 (0xFF000000uL) + +#define INTC_ICDIPTR48_INTIICSPI0 (0x000000FFuL) +#define INTC_ICDIPTR48_INTIICSTI0 (0x0000FF00uL) +#define INTC_ICDIPTR48_INTIICNAKI0 (0x00FF0000uL) +#define INTC_ICDIPTR48_INTIICALI0 (0xFF000000uL) + +#define INTC_ICDIPTR49_INTIICTMOI0 (0x000000FFuL) +#define INTC_ICDIPTR49_INTIICTEI1 (0x0000FF00uL) +#define INTC_ICDIPTR49_INTIICRI1 (0x00FF0000uL) +#define INTC_ICDIPTR49_INTIICTI1 (0xFF000000uL) + +#define INTC_ICDIPTR50_INTIICSPI1 (0x000000FFuL) +#define INTC_ICDIPTR50_INTIICSTI1 (0x0000FF00uL) +#define INTC_ICDIPTR50_INTIICNAKI1 (0x00FF0000uL) +#define INTC_ICDIPTR50_INTIICALI1 (0xFF000000uL) + +#define INTC_ICDIPTR51_INTIICTMOI1 (0x000000FFuL) +#define INTC_ICDIPTR51_INTIICTEI2 (0x0000FF00uL) +#define INTC_ICDIPTR51_INTIICRI2 (0x00FF0000uL) +#define INTC_ICDIPTR51_INTIICTI2 (0xFF000000uL) + +#define INTC_ICDIPTR52_INTIICSPI2 (0x000000FFuL) +#define INTC_ICDIPTR52_INTIICSTI2 (0x0000FF00uL) +#define INTC_ICDIPTR52_INTIICNAKI2 (0x00FF0000uL) +#define INTC_ICDIPTR52_INTIICALI2 (0xFF000000uL) + +#define INTC_ICDIPTR53_INTIICTMOI2 (0x000000FFuL) +#define INTC_ICDIPTR53_INTIICTEI3 (0x0000FF00uL) +#define INTC_ICDIPTR53_INTIICRI3 (0x00FF0000uL) +#define INTC_ICDIPTR53_INTIICTI3 (0xFF000000uL) + +#define INTC_ICDIPTR54_INTIICSPI3 (0x000000FFuL) +#define INTC_ICDIPTR54_INTIICSTI3 (0x0000FF00uL) +#define INTC_ICDIPTR54_INTIICNAKI3 (0x00FF0000uL) +#define INTC_ICDIPTR54_INTIICALI3 (0xFF000000uL) + +#define INTC_ICDIPTR55_INTIICTMOI3 (0x000000FFuL) +#define INTC_ICDIPTR55_BRI0 (0x0000FF00uL) +#define INTC_ICDIPTR55_ERI0 (0x00FF0000uL) +#define INTC_ICDIPTR55_RXI0 (0xFF000000uL) + +#define INTC_ICDIPTR56_TXI0 (0x000000FFuL) +#define INTC_ICDIPTR56_BRI1 (0x0000FF00uL) +#define INTC_ICDIPTR56_ERI1 (0x00FF0000uL) +#define INTC_ICDIPTR56_RXI1 (0xFF000000uL) + +#define INTC_ICDIPTR57_TXI1 (0x000000FFuL) +#define INTC_ICDIPTR57_BRI2 (0x0000FF00uL) +#define INTC_ICDIPTR57_ERI2 (0x00FF0000uL) +#define INTC_ICDIPTR57_RXI2 (0xFF000000uL) + +#define INTC_ICDIPTR58_TXI2 (0x000000FFuL) +#define INTC_ICDIPTR58_BRI3 (0x0000FF00uL) +#define INTC_ICDIPTR58_ERI3 (0x00FF0000uL) +#define INTC_ICDIPTR58_RXI3 (0xFF000000uL) + +#define INTC_ICDIPTR59_TXI3 (0x000000FFuL) +#define INTC_ICDIPTR59_BRI4 (0x0000FF00uL) +#define INTC_ICDIPTR59_ERI4 (0x00FF0000uL) +#define INTC_ICDIPTR59_RXI4 (0xFF000000uL) + +#define INTC_ICDIPTR60_TXI4 (0x000000FFuL) +#define INTC_ICDIPTR60_BRI5 (0x0000FF00uL) +#define INTC_ICDIPTR60_ERI5 (0x00FF0000uL) +#define INTC_ICDIPTR60_RXI5 (0xFF000000uL) + +#define INTC_ICDIPTR61_TXI5 (0x000000FFuL) +#define INTC_ICDIPTR61_BRI6 (0x0000FF00uL) +#define INTC_ICDIPTR61_ERI6 (0x00FF0000uL) +#define INTC_ICDIPTR61_RXI6 (0xFF000000uL) + +#define INTC_ICDIPTR62_TXI6 (0x000000FFuL) +#define INTC_ICDIPTR62_BRI7 (0x0000FF00uL) +#define INTC_ICDIPTR62_ERI7 (0x00FF0000uL) +#define INTC_ICDIPTR62_RXI7 (0xFF000000uL) + +#define INTC_ICDIPTR63_TXI7 (0x000000FFuL) +#define INTC_ICDIPTR63_INTRCANGERR (0x0000FF00uL) +#define INTC_ICDIPTR63_INTRCANGRECC (0x00FF0000uL) +#define INTC_ICDIPTR63_INTRCAN0REC (0xFF000000uL) + +#define INTC_ICDIPTR64_INTRCAN0ERR (0x000000FFuL) +#define INTC_ICDIPTR64_INTRCAN0TRX (0x0000FF00uL) +#define INTC_ICDIPTR64_INTRCAN1REC (0x00FF0000uL) +#define INTC_ICDIPTR64_INTRCAN1ERR (0xFF000000uL) + +#define INTC_ICDIPTR65_INTRCAN1TRX (0x000000FFuL) +#define INTC_ICDIPTR65_INTRCAN2REC (0x0000FF00uL) +#define INTC_ICDIPTR65_INTRCAN2ERR (0x00FF0000uL) +#define INTC_ICDIPTR65_INTRCAN2TRX (0xFF000000uL) + +#define INTC_ICDIPTR66_INTRCAN3REC (0x000000FFuL) +#define INTC_ICDIPTR66_INTRCAN3ERR (0x0000FF00uL) +#define INTC_ICDIPTR66_INTRCAN3TRX (0x00FF0000uL) +#define INTC_ICDIPTR66_INTRCAN4REC (0xFF000000uL) + +#define INTC_ICDIPTR67_INTRCAN4ERR (0x000000FFuL) +#define INTC_ICDIPTR67_INTRCAN4TRX (0x0000FF00uL) +#define INTC_ICDIPTR67_SPEI0 (0x00FF0000uL) +#define INTC_ICDIPTR67_SPRI0 (0xFF000000uL) + +#define INTC_ICDIPTR68_SPTI0 (0x000000FFuL) +#define INTC_ICDIPTR68_SPEI1 (0x0000FF00uL) +#define INTC_ICDIPTR68_SPRI1 (0x00FF0000uL) +#define INTC_ICDIPTR68_SPTI1 (0xFF000000uL) + +#define INTC_ICDIPTR69_SPEI2 (0x000000FFuL) +#define INTC_ICDIPTR69_SPRI2 (0x0000FF00uL) +#define INTC_ICDIPTR69_SPTI2 (0x00FF0000uL) +#define INTC_ICDIPTR69_SPEI3 (0xFF000000uL) + +#define INTC_ICDIPTR70_SPRI3 (0x000000FFuL) +#define INTC_ICDIPTR70_SPTI3 (0x0000FF00uL) +#define INTC_ICDIPTR70_SPEI4 (0x00FF0000uL) +#define INTC_ICDIPTR70_SPRI4 (0xFF000000uL) + +#define INTC_ICDIPTR71_SPTI4 (0x000000FFuL) +#define INTC_ICDIPTR71_IEBBTD (0x0000FF00uL) +#define INTC_ICDIPTR71_IEBBTERR (0x00FF0000uL) +#define INTC_ICDIPTR71_IEBBTSTA (0xFF000000uL) + +#define INTC_ICDIPTR72_IEBBTV (0x000000FFuL) +#define INTC_ICDIPTR72_ISY (0x0000FF00uL) +#define INTC_ICDIPTR72_IERR (0x00FF0000uL) +#define INTC_ICDIPTR72_ITARG (0xFF000000uL) + +#define INTC_ICDIPTR73_ISEC (0x000000FFuL) +#define INTC_ICDIPTR73_IBUF (0x0000FF00uL) +#define INTC_ICDIPTR73_IREADY (0x00FF0000uL) +#define INTC_ICDIPTR73_FLSTE (0xFF000000uL) + +#define INTC_ICDIPTR74_FLTENDI (0x000000FFuL) +#define INTC_ICDIPTR74_FLTREQ0I (0x0000FF00uL) +#define INTC_ICDIPTR74_FLTREQ1I (0x00FF0000uL) +#define INTC_ICDIPTR74_MMC0 (0xFF000000uL) + +#define INTC_ICDIPTR75_MMC1 (0x000000FFuL) +#define INTC_ICDIPTR75_MMC2 (0x0000FF00uL) +#define INTC_ICDIPTR75_SDHI0_3 (0x00FF0000uL) +#define INTC_ICDIPTR75_SDHI0_0 (0xFF000000uL) + +#define INTC_ICDIPTR76_SDHI0_1 (0x000000FFuL) +#define INTC_ICDIPTR76_SDHI1_3 (0x0000FF00uL) +#define INTC_ICDIPTR76_SDHI1_0 (0x00FF0000uL) +#define INTC_ICDIPTR76_SDHI1_1 (0xFF000000uL) + +#define INTC_ICDIPTR77_ARM (0x000000FFuL) +#define INTC_ICDIPTR77_PRD (0x0000FF00uL) +#define INTC_ICDIPTR77_CUP (0x00FF0000uL) +#define INTC_ICDIPTR77_SCUAI0 (0xFF000000uL) + +#define INTC_ICDIPTR78_SCUAI1 (0x000000FFuL) +#define INTC_ICDIPTR78_SCUFDI0 (0x0000FF00uL) +#define INTC_ICDIPTR78_SCUFDI1 (0x00FF0000uL) +#define INTC_ICDIPTR78_SCUFDI2 (0xFF000000uL) + +#define INTC_ICDIPTR79_SCUFDI3 (0x000000FFuL) +#define INTC_ICDIPTR79_SCUFUI0 (0x0000FF00uL) +#define INTC_ICDIPTR79_SCUFUI1 (0x00FF0000uL) +#define INTC_ICDIPTR79_SCUFUI2 (0xFF000000uL) + +#define INTC_ICDIPTR80_SCUFUI3 (0x000000FFuL) +#define INTC_ICDIPTR80_SCUDVI0 (0x0000FF00uL) +#define INTC_ICDIPTR80_SCUDVI1 (0x00FF0000uL) +#define INTC_ICDIPTR80_SCUDVI2 (0xFF000000uL) + +#define INTC_ICDIPTR81_SCUDVI3 (0x000000FFuL) +#define INTC_ICDIPTR81_MLB_CINT (0x0000FF00uL) +#define INTC_ICDIPTR81_MLB_SINT (0x00FF0000uL) +#define INTC_ICDIPTR81_DRC0 (0xFF000000uL) + +#define INTC_ICDIPTR82_DRC1 (0x000000FFuL) +#define INTC_ICDIPTR82_LINI0_INT_T (0xFF000000uL) + +#define INTC_ICDIPTR83_LINI0_INT_R (0x000000FFuL) +#define INTC_ICDIPTR83_LINI0_INT_S (0x0000FF00uL) +#define INTC_ICDIPTR83_LINI0_INT_M (0x00FF0000uL) +#define INTC_ICDIPTR83_LINI1_INT_T (0xFF000000uL) + +#define INTC_ICDIPTR84_LINI1_INT_R (0x000000FFuL) +#define INTC_ICDIPTR84_LINI1_INT_S (0x0000FF00uL) +#define INTC_ICDIPTR84_LINI1_INT_M (0x00FF0000uL) + +#define INTC_ICDIPTR86_ERI0 (0xFF000000uL) + +#define INTC_ICDIPTR87_RXI0 (0x000000FFuL) +#define INTC_ICDIPTR87_TXI0 (0x0000FF00uL) +#define INTC_ICDIPTR87_TEI0 (0x00FF0000uL) +#define INTC_ICDIPTR87_ERI1 (0xFF000000uL) + +#define INTC_ICDIPTR88_RXI1 (0x000000FFuL) +#define INTC_ICDIPTR88_TXI1 (0x0000FF00uL) +#define INTC_ICDIPTR88_TEI1 (0x00FF0000uL) +#define INTC_ICDIPTR88_AVBI_DATA (0xFF000000uL) + +#define INTC_ICDIPTR89_AVBI_ERROR (0x000000FFuL) +#define INTC_ICDIPTR89_AVBI_MANAGE (0x0000FF00uL) +#define INTC_ICDIPTR89_AVBI_MAC (0x00FF0000uL) +#define INTC_ICDIPTR89_ETHERI (0xFF000000uL) + +#define INTC_ICDIPTR91_CEUI (0x000000FFuL) + +#define INTC_ICDIPTR95_H2XMLB_ERRINT (0x0000FF00uL) +#define INTC_ICDIPTR95_H2XIC1_ERRINT (0x00FF0000uL) +#define INTC_ICDIPTR95_X2HPERI1_ERRINT (0xFF000000uL) + +#define INTC_ICDIPTR96_X2HPERI2_ERRINT (0x000000FFuL) +#define INTC_ICDIPTR96_X2HPERI34_ERRINT (0x0000FF00uL) +#define INTC_ICDIPTR96_X2HPERI5_ERRINT (0x00FF0000uL) +#define INTC_ICDIPTR96_X2HPERI67_ERRINT (0xFF000000uL) + +#define INTC_ICDIPTR97_X2HDBGR_ERRINT (0x000000FFuL) +#define INTC_ICDIPTR97_X2HBSC_ERRINT (0x0000FF00uL) +#define INTC_ICDIPTR97_X2HSPI1_ERRINT (0x00FF0000uL) +#define INTC_ICDIPTR97_X2HSPI2_ERRINT (0xFF000000uL) + +#define INTC_ICDIPTR98_PRRI (0x000000FFuL) +#define INTC_ICDIPTR98_IFEI0 (0x0000FF00uL) +#define INTC_ICDIPTR98_OFFI0 (0x00FF0000uL) +#define INTC_ICDIPTR98_PFVEI0 (0xFF000000uL) + +#define INTC_ICDIPTR99_IFEI1 (0x000000FFuL) +#define INTC_ICDIPTR99_OFFI1 (0x0000FF00uL) +#define INTC_ICDIPTR99_PFVEI1 (0x00FF0000uL) + +#define INTC_ICDIPTR104_TINT0 (0x000000FFuL) +#define INTC_ICDIPTR104_TINT1 (0x0000FF00uL) +#define INTC_ICDIPTR104_TINT2 (0x00FF0000uL) +#define INTC_ICDIPTR104_TINT3 (0xFF000000uL) + +#define INTC_ICDIPTR105_TINT4 (0x000000FFuL) +#define INTC_ICDIPTR105_TINT5 (0x0000FF00uL) +#define INTC_ICDIPTR105_TINT6 (0x00FF0000uL) +#define INTC_ICDIPTR105_TINT7 (0xFF000000uL) + +#define INTC_ICDIPTR106_TINT8 (0x000000FFuL) +#define INTC_ICDIPTR106_TINT9 (0x0000FF00uL) +#define INTC_ICDIPTR106_TINT10 (0x00FF0000uL) +#define INTC_ICDIPTR106_TINT11 (0xFF000000uL) + +#define INTC_ICDIPTR107_TINT12 (0x000000FFuL) +#define INTC_ICDIPTR107_TINT13 (0x0000FF00uL) +#define INTC_ICDIPTR107_TINT14 (0x00FF0000uL) +#define INTC_ICDIPTR107_TINT15 (0xFF000000uL) + +#define INTC_ICDIPTR108_TINT16 (0x000000FFuL) +#define INTC_ICDIPTR108_TINT17 (0x0000FF00uL) +#define INTC_ICDIPTR108_TINT18 (0x00FF0000uL) +#define INTC_ICDIPTR108_TINT19 (0xFF000000uL) + +#define INTC_ICDIPTR109_TINT20 (0x000000FFuL) +#define INTC_ICDIPTR109_TINT21 (0x0000FF00uL) +#define INTC_ICDIPTR109_TINT22 (0x00FF0000uL) +#define INTC_ICDIPTR109_TINT23 (0xFF000000uL) + +#define INTC_ICDIPTR110_TINT24 (0x000000FFuL) +#define INTC_ICDIPTR110_TINT25 (0x0000FF00uL) +#define INTC_ICDIPTR110_TINT26 (0x00FF0000uL) +#define INTC_ICDIPTR110_TINT27 (0xFF000000uL) + +#define INTC_ICDIPTR111_TINT28 (0x000000FFuL) +#define INTC_ICDIPTR111_TINT29 (0x0000FF00uL) +#define INTC_ICDIPTR111_TINT30 (0x00FF0000uL) +#define INTC_ICDIPTR111_TINT31 (0xFF000000uL) + +#define INTC_ICDIPTR112_TINT32 (0x000000FFuL) +#define INTC_ICDIPTR112_TINT33 (0x0000FF00uL) +#define INTC_ICDIPTR112_TINT34 (0x00FF0000uL) +#define INTC_ICDIPTR112_TINT35 (0xFF000000uL) + +#define INTC_ICDIPTR113_TINT36 (0x000000FFuL) +#define INTC_ICDIPTR113_TINT37 (0x0000FF00uL) +#define INTC_ICDIPTR113_TINT38 (0x00FF0000uL) +#define INTC_ICDIPTR113_TINT39 (0xFF000000uL) + +#define INTC_ICDIPTR114_TINT40 (0x000000FFuL) +#define INTC_ICDIPTR114_TINT41 (0x0000FF00uL) +#define INTC_ICDIPTR114_TINT42 (0x00FF0000uL) +#define INTC_ICDIPTR114_TINT43 (0xFF000000uL) + +#define INTC_ICDIPTR115_TINT44 (0x000000FFuL) +#define INTC_ICDIPTR115_TINT45 (0x0000FF00uL) +#define INTC_ICDIPTR115_TINT46 (0x00FF0000uL) +#define INTC_ICDIPTR115_TINT47 (0xFF000000uL) + +#define INTC_ICDIPTR116_TINT48 (0x000000FFuL) +#define INTC_ICDIPTR116_TINT49 (0x0000FF00uL) +#define INTC_ICDIPTR116_TINT50 (0x00FF0000uL) +#define INTC_ICDIPTR116_TINT51 (0xFF000000uL) + +#define INTC_ICDIPTR117_TINT52 (0x000000FFuL) +#define INTC_ICDIPTR117_TINT53 (0x0000FF00uL) +#define INTC_ICDIPTR117_TINT54 (0x00FF0000uL) +#define INTC_ICDIPTR117_TINT55 (0xFF000000uL) + +#define INTC_ICDIPTR118_TINT56 (0x000000FFuL) +#define INTC_ICDIPTR118_TINT57 (0x0000FF00uL) +#define INTC_ICDIPTR118_TINT58 (0x00FF0000uL) +#define INTC_ICDIPTR118_TINT59 (0xFF000000uL) + +#define INTC_ICDIPTR119_TINT60 (0x000000FFuL) +#define INTC_ICDIPTR119_TINT61 (0x0000FF00uL) +#define INTC_ICDIPTR119_TINT62 (0x00FF0000uL) +#define INTC_ICDIPTR119_TINT63 (0xFF000000uL) + +#define INTC_ICDIPTR120_TINT64 (0x000000FFuL) +#define INTC_ICDIPTR120_TINT65 (0x0000FF00uL) +#define INTC_ICDIPTR120_TINT66 (0x00FF0000uL) +#define INTC_ICDIPTR120_TINT67 (0xFF000000uL) + +#define INTC_ICDIPTR121_TINT68 (0x000000FFuL) +#define INTC_ICDIPTR121_TINT69 (0x0000FF00uL) +#define INTC_ICDIPTR121_TINT70 (0x00FF0000uL) +#define INTC_ICDIPTR121_TINT71 (0xFF000000uL) + +#define INTC_ICDIPTR122_TINT72 (0x000000FFuL) +#define INTC_ICDIPTR122_TINT73 (0x0000FF00uL) +#define INTC_ICDIPTR122_TINT74 (0x00FF0000uL) +#define INTC_ICDIPTR122_TINT75 (0xFF000000uL) + +#define INTC_ICDIPTR123_TINT76 (0x000000FFuL) +#define INTC_ICDIPTR123_TINT77 (0x0000FF00uL) +#define INTC_ICDIPTR123_TINT78 (0x00FF0000uL) +#define INTC_ICDIPTR123_TINT79 (0xFF000000uL) + +#define INTC_ICDIPTR124_TINT80 (0x000000FFuL) +#define INTC_ICDIPTR124_TINT81 (0x0000FF00uL) +#define INTC_ICDIPTR124_TINT82 (0x00FF0000uL) +#define INTC_ICDIPTR124_TINT83 (0xFF000000uL) + +#define INTC_ICDIPTR125_TINT84 (0x000000FFuL) +#define INTC_ICDIPTR125_TINT85 (0x0000FF00uL) +#define INTC_ICDIPTR125_TINT86 (0x00FF0000uL) +#define INTC_ICDIPTR125_TINT87 (0xFF000000uL) + +#define INTC_ICDIPTR126_TINT88 (0x000000FFuL) +#define INTC_ICDIPTR126_TINT89 (0x0000FF00uL) +#define INTC_ICDIPTR126_TINT90 (0x00FF0000uL) +#define INTC_ICDIPTR126_TINT91 (0xFF000000uL) + +#define INTC_ICDIPTR127_TINT92 (0x000000FFuL) +#define INTC_ICDIPTR127_TINT93 (0x0000FF00uL) +#define INTC_ICDIPTR127_TINT94 (0x00FF0000uL) +#define INTC_ICDIPTR127_TINT95 (0xFF000000uL) + +#define INTC_ICDIPTR128_TINT96 (0x000000FFuL) +#define INTC_ICDIPTR128_TINT97 (0x0000FF00uL) +#define INTC_ICDIPTR128_TINT98 (0x00FF0000uL) +#define INTC_ICDIPTR128_TINT99 (0xFF000000uL) + +#define INTC_ICDIPTR129_TINT100 (0x000000FFuL) +#define INTC_ICDIPTR129_TINT101 (0x0000FF00uL) +#define INTC_ICDIPTR129_TINT102 (0x00FF0000uL) +#define INTC_ICDIPTR129_TINT103 (0xFF000000uL) + +#define INTC_ICDIPTR130_TINT104 (0x000000FFuL) +#define INTC_ICDIPTR130_TINT105 (0x0000FF00uL) +#define INTC_ICDIPTR130_TINT106 (0x00FF0000uL) +#define INTC_ICDIPTR130_TINT107 (0xFF000000uL) + +#define INTC_ICDIPTR131_TINT108 (0x000000FFuL) +#define INTC_ICDIPTR131_TINT109 (0x0000FF00uL) +#define INTC_ICDIPTR131_TINT110 (0x00FF0000uL) +#define INTC_ICDIPTR131_TINT111 (0xFF000000uL) + +#define INTC_ICDIPTR132_TINT112 (0x000000FFuL) +#define INTC_ICDIPTR132_TINT113 (0x0000FF00uL) +#define INTC_ICDIPTR132_TINT114 (0x00FF0000uL) +#define INTC_ICDIPTR132_TINT115 (0xFF000000uL) + +#define INTC_ICDIPTR133_TINT116 (0x000000FFuL) +#define INTC_ICDIPTR133_TINT117 (0x0000FF00uL) +#define INTC_ICDIPTR133_TINT118 (0x00FF0000uL) +#define INTC_ICDIPTR133_TINT119 (0xFF000000uL) + +#define INTC_ICDIPTR134_TINT120 (0x000000FFuL) +#define INTC_ICDIPTR134_TINT121 (0x0000FF00uL) +#define INTC_ICDIPTR134_TINT122 (0x00FF0000uL) +#define INTC_ICDIPTR134_TINT123 (0xFF000000uL) + +#define INTC_ICDIPTR135_TINT124 (0x000000FFuL) +#define INTC_ICDIPTR135_TINT125 (0x0000FF00uL) +#define INTC_ICDIPTR135_TINT126 (0x00FF0000uL) +#define INTC_ICDIPTR135_TINT127 (0xFF000000uL) + +#define INTC_ICDIPTR136_TINT128 (0x000000FFuL) +#define INTC_ICDIPTR136_TINT129 (0x0000FF00uL) +#define INTC_ICDIPTR136_TINT130 (0x00FF0000uL) +#define INTC_ICDIPTR136_TINT131 (0xFF000000uL) + +#define INTC_ICDIPTR137_TINT132 (0x000000FFuL) +#define INTC_ICDIPTR137_TINT133 (0x0000FF00uL) +#define INTC_ICDIPTR137_TINT134 (0x00FF0000uL) +#define INTC_ICDIPTR137_TINT135 (0xFF000000uL) + +#define INTC_ICDIPTR138_TINT136 (0x000000FFuL) +#define INTC_ICDIPTR138_TINT137 (0x0000FF00uL) +#define INTC_ICDIPTR138_TINT138 (0x00FF0000uL) +#define INTC_ICDIPTR138_TINT139 (0xFF000000uL) + +#define INTC_ICDIPTR139_TINT140 (0x000000FFuL) +#define INTC_ICDIPTR139_TINT141 (0x0000FF00uL) +#define INTC_ICDIPTR139_TINT142 (0x00FF0000uL) +#define INTC_ICDIPTR139_TINT143 (0xFF000000uL) + +#define INTC_ICDIPTR140_TINT144 (0x000000FFuL) +#define INTC_ICDIPTR140_TINT145 (0x0000FF00uL) +#define INTC_ICDIPTR140_TINT146 (0x00FF0000uL) +#define INTC_ICDIPTR140_TINT147 (0xFF000000uL) + +#define INTC_ICDIPTR141_TINT148 (0x000000FFuL) +#define INTC_ICDIPTR141_TINT149 (0x0000FF00uL) +#define INTC_ICDIPTR141_TINT150 (0x00FF0000uL) +#define INTC_ICDIPTR141_TINT151 (0xFF000000uL) + +#define INTC_ICDIPTR142_TINT152 (0x000000FFuL) +#define INTC_ICDIPTR142_TINT153 (0x0000FF00uL) +#define INTC_ICDIPTR142_TINT154 (0x00FF0000uL) +#define INTC_ICDIPTR142_TINT155 (0xFF000000uL) + +#define INTC_ICDIPTR143_TINT156 (0x000000FFuL) +#define INTC_ICDIPTR143_TINT157 (0x0000FF00uL) +#define INTC_ICDIPTR143_TINT158 (0x00FF0000uL) +#define INTC_ICDIPTR143_TINT159 (0xFF000000uL) + +#define INTC_ICDIPTR144_TINT160 (0x000000FFuL) +#define INTC_ICDIPTR144_TINT161 (0x0000FF00uL) +#define INTC_ICDIPTR144_TINT162 (0x00FF0000uL) +#define INTC_ICDIPTR144_TINT163 (0xFF000000uL) + +#define INTC_ICDIPTR145_TINT164 (0x000000FFuL) +#define INTC_ICDIPTR145_TINT165 (0x0000FF00uL) +#define INTC_ICDIPTR145_TINT166 (0x00FF0000uL) +#define INTC_ICDIPTR145_TINT167 (0xFF000000uL) + +#define INTC_ICDIPTR146_TINT168 (0x000000FFuL) +#define INTC_ICDIPTR146_TINT169 (0x0000FF00uL) +#define INTC_ICDIPTR146_TINT170 (0x00FF0000uL) + +#define INTC_ICDICFR0_SW0_0 (0x00000001uL) +#define INTC_ICDICFR0_SW0_1 (0x00000002uL) +#define INTC_ICDICFR0_SW1_0 (0x00000004uL) +#define INTC_ICDICFR0_SW1_1 (0x00000008uL) +#define INTC_ICDICFR0_SW2_0 (0x00000010uL) +#define INTC_ICDICFR0_SW2_1 (0x00000020uL) +#define INTC_ICDICFR0_SW3_0 (0x00000040uL) +#define INTC_ICDICFR0_SW3_1 (0x00000080uL) +#define INTC_ICDICFR0_SW4_0 (0x00000100uL) +#define INTC_ICDICFR0_SW4_1 (0x00000200uL) +#define INTC_ICDICFR0_SW5_0 (0x00000400uL) +#define INTC_ICDICFR0_SW5_1 (0x00000800uL) +#define INTC_ICDICFR0_SW6_0 (0x00001000uL) +#define INTC_ICDICFR0_SW6_1 (0x00002000uL) +#define INTC_ICDICFR0_SW7_0 (0x00004000uL) +#define INTC_ICDICFR0_SW7_1 (0x00008000uL) +#define INTC_ICDICFR0_SW8_0 (0x00010000uL) +#define INTC_ICDICFR0_SW8_1 (0x00020000uL) +#define INTC_ICDICFR0_SW9_0 (0x00040000uL) +#define INTC_ICDICFR0_SW9_1 (0x00080000uL) +#define INTC_ICDICFR0_SW10_0 (0x00100000uL) +#define INTC_ICDICFR0_SW10_1 (0x00200000uL) +#define INTC_ICDICFR0_SW11_0 (0x00400000uL) +#define INTC_ICDICFR0_SW11_1 (0x00800000uL) +#define INTC_ICDICFR0_SW12_0 (0x01000000uL) +#define INTC_ICDICFR0_SW12_1 (0x02000000uL) +#define INTC_ICDICFR0_SW13_0 (0x04000000uL) +#define INTC_ICDICFR0_SW13_1 (0x08000000uL) +#define INTC_ICDICFR0_SW14_0 (0x10000000uL) +#define INTC_ICDICFR0_SW14_1 (0x20000000uL) +#define INTC_ICDICFR0_SW15_0 (0x40000000uL) +#define INTC_ICDICFR0_SW15_1 (0x80000000uL) + +#define INTC_ICDICFR1_PMUIRQ0_0 (0x00000001uL) +#define INTC_ICDICFR1_PMUIRQ0_1 (0x00000002uL) +#define INTC_ICDICFR1_COMMRX0_0 (0x00000004uL) +#define INTC_ICDICFR1_COMMRX0_1 (0x00000008uL) +#define INTC_ICDICFR1_COMMTX0_0 (0x00000010uL) +#define INTC_ICDICFR1_COMMTX0_1 (0x00000020uL) +#define INTC_ICDICFR1_CTIIRQ0_0 (0x00000040uL) +#define INTC_ICDICFR1_CTIIRQ0_1 (0x00000080uL) + +#define INTC_ICDICFR2_IRQ0_0 (0x00000001uL) +#define INTC_ICDICFR2_IRQ0_1 (0x00000002uL) +#define INTC_ICDICFR2_IRQ1_0 (0x00000004uL) +#define INTC_ICDICFR2_IRQ1_1 (0x00000008uL) +#define INTC_ICDICFR2_IRQ2_0 (0x00000010uL) +#define INTC_ICDICFR2_IRQ2_1 (0x00000020uL) +#define INTC_ICDICFR2_IRQ3_0 (0x00000040uL) +#define INTC_ICDICFR2_IRQ3_1 (0x00000080uL) +#define INTC_ICDICFR2_IRQ4_0 (0x00000100uL) +#define INTC_ICDICFR2_IRQ4_1 (0x00000200uL) +#define INTC_ICDICFR2_IRQ5_0 (0x00000400uL) +#define INTC_ICDICFR2_IRQ5_1 (0x00000800uL) +#define INTC_ICDICFR2_IRQ6_0 (0x00001000uL) +#define INTC_ICDICFR2_IRQ6_1 (0x00002000uL) +#define INTC_ICDICFR2_IRQ7_0 (0x00004000uL) +#define INTC_ICDICFR2_IRQ7_1 (0x00008000uL) +#define INTC_ICDICFR2_PL310ERR_0 (0x00010000uL) +#define INTC_ICDICFR2_PL310ERR_1 (0x00020000uL) +#define INTC_ICDICFR2_DMAINT0_0 (0x00040000uL) +#define INTC_ICDICFR2_DMAINT0_1 (0x00080000uL) +#define INTC_ICDICFR2_DMAINT1_0 (0x00100000uL) +#define INTC_ICDICFR2_DMAINT1_1 (0x00200000uL) +#define INTC_ICDICFR2_DMAINT2_0 (0x00400000uL) +#define INTC_ICDICFR2_DMAINT2_1 (0x00800000uL) +#define INTC_ICDICFR2_DMAINT3_0 (0x01000000uL) +#define INTC_ICDICFR2_DMAINT3_1 (0x02000000uL) +#define INTC_ICDICFR2_DMAINT4_0 (0x04000000uL) +#define INTC_ICDICFR2_DMAINT4_1 (0x08000000uL) +#define INTC_ICDICFR2_DMAINT5_0 (0x10000000uL) +#define INTC_ICDICFR2_DMAINT5_1 (0x20000000uL) +#define INTC_ICDICFR2_DMAINT6_0 (0x40000000uL) +#define INTC_ICDICFR2_DMAINT6_1 (0x80000000uL) + +#define INTC_ICDICFR3_DMAINT7_0 (0x00000001uL) +#define INTC_ICDICFR3_DMAINT7_1 (0x00000002uL) +#define INTC_ICDICFR3_DMAINT8_0 (0x00000004uL) +#define INTC_ICDICFR3_DMAINT8_1 (0x00000008uL) +#define INTC_ICDICFR3_DMAINT9_0 (0x00000010uL) +#define INTC_ICDICFR3_DMAINT9_1 (0x00000020uL) +#define INTC_ICDICFR3_DMAINT10_0 (0x00000040uL) +#define INTC_ICDICFR3_DMAINT10_1 (0x00000080uL) +#define INTC_ICDICFR3_DMAINT11_0 (0x00000100uL) +#define INTC_ICDICFR3_DMAINT11_1 (0x00000200uL) +#define INTC_ICDICFR3_DMAINT12_0 (0x00000400uL) +#define INTC_ICDICFR3_DMAINT12_1 (0x00000800uL) +#define INTC_ICDICFR3_DMAINT13_0 (0x00001000uL) +#define INTC_ICDICFR3_DMAINT13_1 (0x00002000uL) +#define INTC_ICDICFR3_DMAINT14_0 (0x00004000uL) +#define INTC_ICDICFR3_DMAINT14_1 (0x00008000uL) +#define INTC_ICDICFR3_DMAINT15_0 (0x00010000uL) +#define INTC_ICDICFR3_DMAINT15_1 (0x00020000uL) +#define INTC_ICDICFR3_DMAERR_0 (0x00040000uL) +#define INTC_ICDICFR3_DMAERR_1 (0x00080000uL) + +#define INTC_ICDICFR4_USBI0_0 (0x00040000uL) +#define INTC_ICDICFR4_USBI0_1 (0x00080000uL) +#define INTC_ICDICFR4_USBI1_0 (0x00100000uL) +#define INTC_ICDICFR4_USBI1_1 (0x00200000uL) +#define INTC_ICDICFR4_S0_VI_VSYNC0_0 (0x00400000uL) +#define INTC_ICDICFR4_S0_VI_VSYNC0_1 (0x00800000uL) +#define INTC_ICDICFR4_S0_LO_VSYNC0_0 (0x01000000uL) +#define INTC_ICDICFR4_S0_LO_VSYNC0_1 (0x02000000uL) +#define INTC_ICDICFR4_S0_VSYNCERR0_0 (0x04000000uL) +#define INTC_ICDICFR4_S0_VSYNCERR0_1 (0x08000000uL) +#define INTC_ICDICFR4_GR3_VLINE0_0 (0x10000000uL) +#define INTC_ICDICFR4_GR3_VLINE0_1 (0x20000000uL) +#define INTC_ICDICFR4_S0_VFIELD0_0 (0x40000000uL) +#define INTC_ICDICFR4_S0_VFIELD0_1 (0x80000000uL) + +#define INTC_ICDICFR5_IV1_VBUFERR0_0 (0x00000001uL) +#define INTC_ICDICFR5_IV1_VBUFERR0_1 (0x00000002uL) +#define INTC_ICDICFR5_IV3_VBUFERR0_0 (0x00000004uL) +#define INTC_ICDICFR5_IV3_VBUFERR0_1 (0x00000008uL) +#define INTC_ICDICFR5_IV5_VBUFERR0_0 (0x00000010uL) +#define INTC_ICDICFR5_IV5_VBUFERR0_1 (0x00000020uL) +#define INTC_ICDICFR5_IV6_VBUFERR0_0 (0x00000040uL) +#define INTC_ICDICFR5_IV6_VBUFERR0_1 (0x00000080uL) +#define INTC_ICDICFR5_S0_WLINE0_0 (0x00000100uL) +#define INTC_ICDICFR5_S0_WLINE0_1 (0x00000200uL) +#define INTC_ICDICFR5_S1_VI_VSYNC0_0 (0x00000400uL) +#define INTC_ICDICFR5_S1_VI_VSYNC0_1 (0x00000800uL) +#define INTC_ICDICFR5_S1_LO_VSYNC0_0 (0x00001000uL) +#define INTC_ICDICFR5_S1_LO_VSYNC0_1 (0x00002000uL) +#define INTC_ICDICFR5_S1_VSYNCERR0_0 (0x00004000uL) +#define INTC_ICDICFR5_S1_VSYNCERR0_1 (0x00008000uL) +#define INTC_ICDICFR5_S1_VFIELD0_0 (0x00010000uL) +#define INTC_ICDICFR5_S1_VFIELD0_1 (0x00020000uL) +#define INTC_ICDICFR5_IV2_VBUFERR0_0 (0x00040000uL) +#define INTC_ICDICFR5_IV2_VBUFERR0_1 (0x00080000uL) +#define INTC_ICDICFR5_IV4_VBUFERR0_0 (0x00100000uL) +#define INTC_ICDICFR5_IV4_VBUFERR0_1 (0x00200000uL) +#define INTC_ICDICFR5_S1_WLINE0_0 (0x00400000uL) +#define INTC_ICDICFR5_S1_WLINE0_1 (0x00800000uL) +#define INTC_ICDICFR5_OIR_VI_VSYNC0_0 (0x01000000uL) +#define INTC_ICDICFR5_OIR_VI_VSYNC0_1 (0x02000000uL) +#define INTC_ICDICFR5_OIR_LO_VSYNC0_0 (0x04000000uL) +#define INTC_ICDICFR5_OIR_LO_VSYNC0_1 (0x08000000uL) +#define INTC_ICDICFR5_OIR_VSYNCERR0_0 (0x10000000uL) +#define INTC_ICDICFR5_OIR_VSYNCERR0_1 (0x20000000uL) +#define INTC_ICDICFR5_OIR_VFIELD0_0 (0x40000000uL) +#define INTC_ICDICFR5_OIR_VFIELD0_1 (0x80000000uL) + +#define INTC_ICDICFR6_IV7_VBUFERR0_0 (0x00000001uL) +#define INTC_ICDICFR6_IV7_VBUFERR0_1 (0x00000002uL) +#define INTC_ICDICFR6_IV8_VBUFERR0_0 (0x00000004uL) +#define INTC_ICDICFR6_IV8_VBUFERR0_1 (0x00000008uL) +#define INTC_ICDICFR6_S0_VI_VSYNC1_0 (0x00000040uL) +#define INTC_ICDICFR6_S0_VI_VSYNC1_1 (0x00000080uL) +#define INTC_ICDICFR6_S0_LO_VSYNC1_0 (0x00000100uL) +#define INTC_ICDICFR6_S0_LO_VSYNC1_1 (0x00000200uL) +#define INTC_ICDICFR6_S0_VSYNCERR1_0 (0x00000400uL) +#define INTC_ICDICFR6_S0_VSYNCERR1_1 (0x00000800uL) +#define INTC_ICDICFR6_GR3_VLINE1_0 (0x00001000uL) +#define INTC_ICDICFR6_GR3_VLINE1_1 (0x00002000uL) +#define INTC_ICDICFR6_S0_VFIELD1_0 (0x00004000uL) +#define INTC_ICDICFR6_S0_VFIELD1_1 (0x00008000uL) +#define INTC_ICDICFR6_IV1_VBUFERR1_0 (0x00010000uL) +#define INTC_ICDICFR6_IV1_VBUFERR1_1 (0x00020000uL) +#define INTC_ICDICFR6_IV3_VBUFERR1_0 (0x00040000uL) +#define INTC_ICDICFR6_IV3_VBUFERR1_1 (0x00080000uL) +#define INTC_ICDICFR6_IV5_VBUFERR1_0 (0x00100000uL) +#define INTC_ICDICFR6_IV5_VBUFERR1_1 (0x00200000uL) +#define INTC_ICDICFR6_IV6_VBUFERR1_0 (0x00400000uL) +#define INTC_ICDICFR6_IV6_VBUFERR1_1 (0x00800000uL) +#define INTC_ICDICFR6_S0_WLINE1_0 (0x01000000uL) +#define INTC_ICDICFR6_S0_WLINE1_1 (0x02000000uL) +#define INTC_ICDICFR6_S1_VI_VSYNC1_0 (0x04000000uL) +#define INTC_ICDICFR6_S1_VI_VSYNC1_1 (0x08000000uL) +#define INTC_ICDICFR6_S1_LO_VSYNC1_0 (0x10000000uL) +#define INTC_ICDICFR6_S1_LO_VSYNC1_1 (0x20000000uL) +#define INTC_ICDICFR6_S1_VSYNCERR1_0 (0x40000000uL) +#define INTC_ICDICFR6_S1_VSYNCERR1_1 (0x80000000uL) + +#define INTC_ICDICFR7_S1_VFIELD1_0 (0x00000001uL) +#define INTC_ICDICFR7_S1_VFIELD1_1 (0x00000002uL) +#define INTC_ICDICFR7_IV2_VBUFERR1_0 (0x00000004uL) +#define INTC_ICDICFR7_IV2_VBUFERR1_1 (0x00000008uL) +#define INTC_ICDICFR7_IV4_VBUFERR1_0 (0x00000010uL) +#define INTC_ICDICFR7_IV4_VBUFERR1_1 (0x00000020uL) +#define INTC_ICDICFR7_S1_WLINE1_0 (0x00000040uL) +#define INTC_ICDICFR7_S1_WLINE1_1 (0x00000080uL) +#define INTC_ICDICFR7_OIR_VI_VSYNC1_0 (0x00000100uL) +#define INTC_ICDICFR7_OIR_VI_VSYNC1_1 (0x00000200uL) +#define INTC_ICDICFR7_OIR_LO_VSYNC1_0 (0x00000400uL) +#define INTC_ICDICFR7_OIR_LO_VSYNC1_1 (0x00000800uL) +#define INTC_ICDICFR7_OIR_VLINE1_0 (0x00001000uL) +#define INTC_ICDICFR7_OIR_VLINE1_1 (0x00002000uL) +#define INTC_ICDICFR7_OIR_VFIELD1_0 (0x00004000uL) +#define INTC_ICDICFR7_OIR_VFIELD1_1 (0x00008000uL) +#define INTC_ICDICFR7_IV7_VBUFERR1_0 (0x00010000uL) +#define INTC_ICDICFR7_IV7_VBUFERR1_1 (0x00020000uL) +#define INTC_ICDICFR7_IV8_VBUFERR1_0 (0x00040000uL) +#define INTC_ICDICFR7_IV8_VBUFERR1_1 (0x00080000uL) +#define INTC_ICDICFR7_IMRDI_0 (0x00400000uL) +#define INTC_ICDICFR7_IMRDI_1 (0x00800000uL) +#define INTC_ICDICFR7_IMR2I0_0 (0x01000000uL) +#define INTC_ICDICFR7_IMR2I0_1 (0x02000000uL) +#define INTC_ICDICFR7_IMR2I1_0 (0x04000000uL) +#define INTC_ICDICFR7_IMR2I1_1 (0x08000000uL) +#define INTC_ICDICFR7_JEDI_0 (0x10000000uL) +#define INTC_ICDICFR7_JEDI_1 (0x20000000uL) +#define INTC_ICDICFR7_JDTI_0 (0x40000000uL) +#define INTC_ICDICFR7_JDTI_1 (0x80000000uL) + +#define INTC_ICDICFR8_CMP0_0 (0x00000001uL) +#define INTC_ICDICFR8_CMP0_1 (0x00000002uL) +#define INTC_ICDICFR8_CMP1_0 (0x00000004uL) +#define INTC_ICDICFR8_CMP1_1 (0x00000008uL) +#define INTC_ICDICFR8_INT0_0 (0x00000010uL) +#define INTC_ICDICFR8_INT0_1 (0x00000020uL) +#define INTC_ICDICFR8_INT1_0 (0x00000040uL) +#define INTC_ICDICFR8_INT1_1 (0x00000080uL) +#define INTC_ICDICFR8_INT2_0 (0x00000100uL) +#define INTC_ICDICFR8_INT2_1 (0x00000200uL) +#define INTC_ICDICFR8_INT3_0 (0x00000400uL) +#define INTC_ICDICFR8_INT3_1 (0x00000800uL) +#define INTC_ICDICFR8_OSTM0TINT_0 (0x00001000uL) +#define INTC_ICDICFR8_OSTM0TINT_1 (0x00002000uL) +#define INTC_ICDICFR8_OSTM1TINT_0 (0x00004000uL) +#define INTC_ICDICFR8_OSTM1TINT_1 (0x00008000uL) +#define INTC_ICDICFR8_CMI_0 (0x00010000uL) +#define INTC_ICDICFR8_CMI_1 (0x00020000uL) +#define INTC_ICDICFR8_WTOUT_0 (0x00040000uL) +#define INTC_ICDICFR8_WTOUT_1 (0x00080000uL) +#define INTC_ICDICFR8_ITI_0 (0x00100000uL) +#define INTC_ICDICFR8_ITI_1 (0x00200000uL) +#define INTC_ICDICFR8_TGI0A_0 (0x00400000uL) +#define INTC_ICDICFR8_TGI0A_1 (0x00800000uL) +#define INTC_ICDICFR8_TGI0B_0 (0x01000000uL) +#define INTC_ICDICFR8_TGI0B_1 (0x02000000uL) +#define INTC_ICDICFR8_TGI0C_0 (0x04000000uL) +#define INTC_ICDICFR8_TGI0C_1 (0x08000000uL) +#define INTC_ICDICFR8_TGI0D_0 (0x10000000uL) +#define INTC_ICDICFR8_TGI0D_1 (0x20000000uL) +#define INTC_ICDICFR8_TGI0V_0 (0x40000000uL) +#define INTC_ICDICFR8_TGI0V_1 (0x80000000uL) + +#define INTC_ICDICFR9_TGI0E_0 (0x00000001uL) +#define INTC_ICDICFR9_TGI0E_1 (0x00000002uL) +#define INTC_ICDICFR9_TGI0F_0 (0x00000004uL) +#define INTC_ICDICFR9_TGI0F_1 (0x00000008uL) +#define INTC_ICDICFR9_TGI1A_0 (0x00000010uL) +#define INTC_ICDICFR9_TGI1A_1 (0x00000020uL) +#define INTC_ICDICFR9_TGI1B_0 (0x00000040uL) +#define INTC_ICDICFR9_TGI1B_1 (0x00000080uL) +#define INTC_ICDICFR9_TGI1V_0 (0x00000100uL) +#define INTC_ICDICFR9_TGI1V_1 (0x00000200uL) +#define INTC_ICDICFR9_TGI1U_0 (0x00000400uL) +#define INTC_ICDICFR9_TGI1U_1 (0x00000800uL) +#define INTC_ICDICFR9_TGI2A_0 (0x00001000uL) +#define INTC_ICDICFR9_TGI2A_1 (0x00002000uL) +#define INTC_ICDICFR9_TGI2B_0 (0x00004000uL) +#define INTC_ICDICFR9_TGI2B_1 (0x00008000uL) +#define INTC_ICDICFR9_TGI2V_0 (0x00010000uL) +#define INTC_ICDICFR9_TGI2V_1 (0x00020000uL) +#define INTC_ICDICFR9_TGI2U_0 (0x00040000uL) +#define INTC_ICDICFR9_TGI2U_1 (0x00080000uL) +#define INTC_ICDICFR9_TGI3A_0 (0x00100000uL) +#define INTC_ICDICFR9_TGI3A_1 (0x00200000uL) +#define INTC_ICDICFR9_TGI3B_0 (0x00400000uL) +#define INTC_ICDICFR9_TGI3B_1 (0x00800000uL) +#define INTC_ICDICFR9_TGI3C_0 (0x01000000uL) +#define INTC_ICDICFR9_TGI3C_1 (0x02000000uL) +#define INTC_ICDICFR9_TGI3D_0 (0x04000000uL) +#define INTC_ICDICFR9_TGI3D_1 (0x08000000uL) +#define INTC_ICDICFR9_TGI3V_0 (0x10000000uL) +#define INTC_ICDICFR9_TGI3V_1 (0x20000000uL) +#define INTC_ICDICFR9_TGI4A_0 (0x40000000uL) +#define INTC_ICDICFR9_TGI4A_1 (0x80000000uL) + +#define INTC_ICDICFR10_TGI4B_0 (0x00000001uL) +#define INTC_ICDICFR10_TGI4B_1 (0x00000002uL) +#define INTC_ICDICFR10_TGI4C_0 (0x00000004uL) +#define INTC_ICDICFR10_TGI4C_1 (0x00000008uL) +#define INTC_ICDICFR10_TGI4D_0 (0x00000010uL) +#define INTC_ICDICFR10_TGI4D_1 (0x00000020uL) +#define INTC_ICDICFR10_TGI4V_0 (0x00000040uL) +#define INTC_ICDICFR10_TGI4V_1 (0x00000080uL) +#define INTC_ICDICFR10_CMI1_0 (0x00000100uL) +#define INTC_ICDICFR10_CMI1_1 (0x00000200uL) +#define INTC_ICDICFR10_CMI2_0 (0x00000400uL) +#define INTC_ICDICFR10_CMI2_1 (0x00000800uL) +#define INTC_ICDICFR10_SGDEI0_0 (0x00001000uL) +#define INTC_ICDICFR10_SGDEI0_1 (0x00002000uL) +#define INTC_ICDICFR10_SGDEI1_0 (0x00004000uL) +#define INTC_ICDICFR10_SGDEI1_1 (0x00008000uL) +#define INTC_ICDICFR10_SGDEI2_0 (0x00010000uL) +#define INTC_ICDICFR10_SGDEI2_1 (0x00020000uL) +#define INTC_ICDICFR10_SGDEI3_0 (0x00040000uL) +#define INTC_ICDICFR10_SGDEI3_1 (0x00080000uL) +#define INTC_ICDICFR10_ADI_0 (0x00100000uL) +#define INTC_ICDICFR10_ADI_1 (0x00200000uL) +#define INTC_ICDICFR10_LMTI_0 (0x00400000uL) +#define INTC_ICDICFR10_LMTI_1 (0x00800000uL) +#define INTC_ICDICFR10_SSII0_0 (0x01000000uL) +#define INTC_ICDICFR10_SSII0_1 (0x02000000uL) +#define INTC_ICDICFR10_SSIRXI0_0 (0x04000000uL) +#define INTC_ICDICFR10_SSIRXI0_1 (0x08000000uL) +#define INTC_ICDICFR10_SSITXI0_0 (0x10000000uL) +#define INTC_ICDICFR10_SSITXI0_1 (0x20000000uL) +#define INTC_ICDICFR10_SSII1_0 (0x40000000uL) +#define INTC_ICDICFR10_SSII1_1 (0x80000000uL) + +#define INTC_ICDICFR11_SSIRXI1_0 (0x00000001uL) +#define INTC_ICDICFR11_SSIRXI1_1 (0x00000002uL) +#define INTC_ICDICFR11_SSITXI1_0 (0x00000004uL) +#define INTC_ICDICFR11_SSITXI1_1 (0x00000008uL) +#define INTC_ICDICFR11_SSII2_0 (0x00000010uL) +#define INTC_ICDICFR11_SSII2_1 (0x00000020uL) +#define INTC_ICDICFR11_SSIRTI2_0 (0x00000040uL) +#define INTC_ICDICFR11_SSIRTI2_1 (0x00000080uL) +#define INTC_ICDICFR11_SSII3_0 (0x00000100uL) +#define INTC_ICDICFR11_SSII3_1 (0x00000200uL) +#define INTC_ICDICFR11_SSIRXI3_0 (0x00000400uL) +#define INTC_ICDICFR11_SSIRXI3_1 (0x00000800uL) +#define INTC_ICDICFR11_SSITXI3_0 (0x00001000uL) +#define INTC_ICDICFR11_SSITXI3_1 (0x00002000uL) +#define INTC_ICDICFR11_SSII4_0 (0x00004000uL) +#define INTC_ICDICFR11_SSII4_1 (0x00008000uL) +#define INTC_ICDICFR11_SSIRTI4_0 (0x00010000uL) +#define INTC_ICDICFR11_SSIRTI4_1 (0x00020000uL) +#define INTC_ICDICFR11_SSII5_0 (0x00040000uL) +#define INTC_ICDICFR11_SSII5_1 (0x00080000uL) +#define INTC_ICDICFR11_SSIRXI5_0 (0x00100000uL) +#define INTC_ICDICFR11_SSIRXI5_1 (0x00200000uL) +#define INTC_ICDICFR11_SSITXI5_0 (0x00400000uL) +#define INTC_ICDICFR11_SSITXI5_1 (0x00800000uL) +#define INTC_ICDICFR11_SPDIFI_0 (0x01000000uL) +#define INTC_ICDICFR11_SPDIFI_1 (0x02000000uL) +#define INTC_ICDICFR11_INTIICTEI0_0 (0x04000000uL) +#define INTC_ICDICFR11_INTIICTEI0_1 (0x08000000uL) +#define INTC_ICDICFR11_INTIICRI0_0 (0x10000000uL) +#define INTC_ICDICFR11_INTIICRI0_1 (0x20000000uL) +#define INTC_ICDICFR11_INTIICTI0_0 (0x40000000uL) +#define INTC_ICDICFR11_INTIICTI0_1 (0x80000000uL) + +#define INTC_ICDICFR12_INTIICSPI0_0 (0x00000001uL) +#define INTC_ICDICFR12_INTIICSPI0_1 (0x00000002uL) +#define INTC_ICDICFR12_INTIICSTI0_0 (0x00000004uL) +#define INTC_ICDICFR12_INTIICSTI0_1 (0x00000008uL) +#define INTC_ICDICFR12_INTIICNAKI0_0 (0x00000010uL) +#define INTC_ICDICFR12_INTIICNAKI0_1 (0x00000020uL) +#define INTC_ICDICFR12_INTIICALI0_0 (0x00000040uL) +#define INTC_ICDICFR12_INTIICALI0_1 (0x00000080uL) +#define INTC_ICDICFR12_INTIICTMOI0_0 (0x00000100uL) +#define INTC_ICDICFR12_INTIICTMOI0_1 (0x00000200uL) +#define INTC_ICDICFR12_INTIICTEI1_0 (0x00000400uL) +#define INTC_ICDICFR12_INTIICTEI1_1 (0x00000800uL) +#define INTC_ICDICFR12_INTIICRI1_0 (0x00001000uL) +#define INTC_ICDICFR12_INTIICRI1_1 (0x00002000uL) +#define INTC_ICDICFR12_INTIICTI1_0 (0x00004000uL) +#define INTC_ICDICFR12_INTIICTI1_1 (0x00008000uL) +#define INTC_ICDICFR12_INTIICSPI1_0 (0x00010000uL) +#define INTC_ICDICFR12_INTIICSPI1_1 (0x00020000uL) +#define INTC_ICDICFR12_INTIICSTI1_0 (0x00040000uL) +#define INTC_ICDICFR12_INTIICSTI1_1 (0x00080000uL) +#define INTC_ICDICFR12_INTIICNAKI1_0 (0x00100000uL) +#define INTC_ICDICFR12_INTIICNAKI1_1 (0x00200000uL) +#define INTC_ICDICFR12_INTIICALI1_0 (0x00400000uL) +#define INTC_ICDICFR12_INTIICALI1_1 (0x00800000uL) +#define INTC_ICDICFR12_INTIICTMOI1_0 (0x01000000uL) +#define INTC_ICDICFR12_INTIICTMOI1_1 (0x02000000uL) +#define INTC_ICDICFR12_INTIICTEI2_0 (0x04000000uL) +#define INTC_ICDICFR12_INTIICTEI2_1 (0x08000000uL) +#define INTC_ICDICFR12_INTIICRI2_0 (0x10000000uL) +#define INTC_ICDICFR12_INTIICRI2_1 (0x20000000uL) +#define INTC_ICDICFR12_INTIICTI2_0 (0x40000000uL) +#define INTC_ICDICFR12_INTIICTI2_1 (0x80000000uL) + +#define INTC_ICDICFR13_INTIICSPI2_0 (0x00000001uL) +#define INTC_ICDICFR13_INTIICSPI2_1 (0x00000002uL) +#define INTC_ICDICFR13_INTIICSTI2_0 (0x00000004uL) +#define INTC_ICDICFR13_INTIICSTI2_1 (0x00000008uL) +#define INTC_ICDICFR13_INTIICNAKI2_0 (0x00000010uL) +#define INTC_ICDICFR13_INTIICNAKI2_1 (0x00000020uL) +#define INTC_ICDICFR13_INTIICALI2_0 (0x00000040uL) +#define INTC_ICDICFR13_INTIICALI2_1 (0x00000080uL) +#define INTC_ICDICFR13_INTIICTMOI2_0 (0x00000100uL) +#define INTC_ICDICFR13_INTIICTMOI2_1 (0x00000200uL) +#define INTC_ICDICFR13_INTIICTEI3_0 (0x00000400uL) +#define INTC_ICDICFR13_INTIICTEI3_1 (0x00000800uL) +#define INTC_ICDICFR13_INTIICRI3_0 (0x00001000uL) +#define INTC_ICDICFR13_INTIICRI3_1 (0x00002000uL) +#define INTC_ICDICFR13_INTIICTI3_0 (0x00004000uL) +#define INTC_ICDICFR13_INTIICTI3_1 (0x00008000uL) +#define INTC_ICDICFR13_INTIICSPI3_0 (0x00010000uL) +#define INTC_ICDICFR13_INTIICSPI3_1 (0x00020000uL) +#define INTC_ICDICFR13_INTIICSTI3_0 (0x00040000uL) +#define INTC_ICDICFR13_INTIICSTI3_1 (0x00080000uL) +#define INTC_ICDICFR13_INTIICNAKI3_0 (0x00100000uL) +#define INTC_ICDICFR13_INTIICNAKI3_1 (0x00200000uL) +#define INTC_ICDICFR13_INTIICALI3_0 (0x00400000uL) +#define INTC_ICDICFR13_INTIICALI3_1 (0x00800000uL) +#define INTC_ICDICFR13_INTIICTMOI3_0 (0x01000000uL) +#define INTC_ICDICFR13_INTIICTMOI3_1 (0x02000000uL) +#define INTC_ICDICFR13_BRI0_0 (0x04000000uL) +#define INTC_ICDICFR13_BRI0_1 (0x08000000uL) +#define INTC_ICDICFR13_ERI0_0 (0x10000000uL) +#define INTC_ICDICFR13_ERI0_1 (0x20000000uL) +#define INTC_ICDICFR13_RXI0_0 (0x40000000uL) +#define INTC_ICDICFR13_RXI0_1 (0x80000000uL) + +#define INTC_ICDICFR14_TXI0_0 (0x00000001uL) +#define INTC_ICDICFR14_TXI0_1 (0x00000002uL) +#define INTC_ICDICFR14_BRI1_0 (0x00000004uL) +#define INTC_ICDICFR14_BRI1_1 (0x00000008uL) +#define INTC_ICDICFR14_ERI1_0 (0x00000010uL) +#define INTC_ICDICFR14_ERI1_1 (0x00000020uL) +#define INTC_ICDICFR14_RXI1_0 (0x00000040uL) +#define INTC_ICDICFR14_RXI1_1 (0x00000080uL) +#define INTC_ICDICFR14_TXI1_0 (0x00000100uL) +#define INTC_ICDICFR14_TXI1_1 (0x00000200uL) +#define INTC_ICDICFR14_BRI2_0 (0x00000400uL) +#define INTC_ICDICFR14_BRI2_1 (0x00000800uL) +#define INTC_ICDICFR14_ERI2_0 (0x00001000uL) +#define INTC_ICDICFR14_ERI2_1 (0x00002000uL) +#define INTC_ICDICFR14_RXI2_0 (0x00004000uL) +#define INTC_ICDICFR14_RXI2_1 (0x00008000uL) +#define INTC_ICDICFR14_TXI2_0 (0x00010000uL) +#define INTC_ICDICFR14_TXI2_1 (0x00020000uL) +#define INTC_ICDICFR14_BRI3_0 (0x00040000uL) +#define INTC_ICDICFR14_BRI3_1 (0x00080000uL) +#define INTC_ICDICFR14_ERI3_0 (0x00100000uL) +#define INTC_ICDICFR14_ERI3_1 (0x00200000uL) +#define INTC_ICDICFR14_RXI3_0 (0x00400000uL) +#define INTC_ICDICFR14_RXI3_1 (0x00800000uL) +#define INTC_ICDICFR14_TXI3_0 (0x01000000uL) +#define INTC_ICDICFR14_TXI3_1 (0x02000000uL) +#define INTC_ICDICFR14_BRI4_0 (0x04000000uL) +#define INTC_ICDICFR14_BRI4_1 (0x08000000uL) +#define INTC_ICDICFR14_ERI4_0 (0x10000000uL) +#define INTC_ICDICFR14_ERI4_1 (0x20000000uL) +#define INTC_ICDICFR14_RXI4_0 (0x40000000uL) +#define INTC_ICDICFR14_RXI4_1 (0x80000000uL) + +#define INTC_ICDICFR15_TXI4_0 (0x00000001uL) +#define INTC_ICDICFR15_TXI4_1 (0x00000002uL) +#define INTC_ICDICFR15_BRI5_0 (0x00000004uL) +#define INTC_ICDICFR15_BRI5_1 (0x00000008uL) +#define INTC_ICDICFR15_ERI5_0 (0x00000010uL) +#define INTC_ICDICFR15_ERI5_1 (0x00000020uL) +#define INTC_ICDICFR15_RXI5_0 (0x00000040uL) +#define INTC_ICDICFR15_RXI5_1 (0x00000080uL) +#define INTC_ICDICFR15_TXI5_0 (0x00000100uL) +#define INTC_ICDICFR15_TXI5_1 (0x00000200uL) +#define INTC_ICDICFR15_BRI6_0 (0x00000400uL) +#define INTC_ICDICFR15_BRI6_1 (0x00000800uL) +#define INTC_ICDICFR15_ERI6_0 (0x00001000uL) +#define INTC_ICDICFR15_ERI6_1 (0x00002000uL) +#define INTC_ICDICFR15_RXI6_0 (0x00004000uL) +#define INTC_ICDICFR15_RXI6_1 (0x00008000uL) +#define INTC_ICDICFR15_TXI6_0 (0x00010000uL) +#define INTC_ICDICFR15_TXI6_1 (0x00020000uL) +#define INTC_ICDICFR15_BRI7_0 (0x00040000uL) +#define INTC_ICDICFR15_BRI7_1 (0x00080000uL) +#define INTC_ICDICFR15_ERI7_0 (0x00100000uL) +#define INTC_ICDICFR15_ERI7_1 (0x00200000uL) +#define INTC_ICDICFR15_RXI7_0 (0x00400000uL) +#define INTC_ICDICFR15_RXI7_1 (0x00800000uL) +#define INTC_ICDICFR15_TXI7_0 (0x01000000uL) +#define INTC_ICDICFR15_TXI7_1 (0x02000000uL) +#define INTC_ICDICFR15_INTRCANGERR_0 (0x04000000uL) +#define INTC_ICDICFR15_INTRCANGERR_1 (0x08000000uL) +#define INTC_ICDICFR15_INTRCANGRECC_0 (0x10000000uL) +#define INTC_ICDICFR15_INTRCANGRECC_1 (0x20000000uL) +#define INTC_ICDICFR15_INTRCAN0REC_0 (0x40000000uL) +#define INTC_ICDICFR15_INTRCAN0REC_1 (0x80000000uL) + +#define INTC_ICDICFR16_INTRCAN0ERR_0 (0x00000001uL) +#define INTC_ICDICFR16_INTRCAN0ERR_1 (0x00000002uL) +#define INTC_ICDICFR16_INTRCAN0TRX_0 (0x00000004uL) +#define INTC_ICDICFR16_INTRCAN0TRX_1 (0x00000008uL) +#define INTC_ICDICFR16_INTRCAN1REC_0 (0x00000010uL) +#define INTC_ICDICFR16_INTRCAN1REC_1 (0x00000020uL) +#define INTC_ICDICFR16_INTRCAN1ERR_0 (0x00000040uL) +#define INTC_ICDICFR16_INTRCAN1ERR_1 (0x00000080uL) +#define INTC_ICDICFR16_INTRCAN1TRX_0 (0x00000100uL) +#define INTC_ICDICFR16_INTRCAN1TRX_1 (0x00000200uL) +#define INTC_ICDICFR16_INTRCAN2REC_0 (0x00000400uL) +#define INTC_ICDICFR16_INTRCAN2REC_1 (0x00000800uL) +#define INTC_ICDICFR16_INTRCAN2ERR_0 (0x00001000uL) +#define INTC_ICDICFR16_INTRCAN2ERR_1 (0x00002000uL) +#define INTC_ICDICFR16_INTRCAN2TRX_0 (0x00004000uL) +#define INTC_ICDICFR16_INTRCAN2TRX_1 (0x00008000uL) +#define INTC_ICDICFR16_INTRCAN3REC_0 (0x00010000uL) +#define INTC_ICDICFR16_INTRCAN3REC_1 (0x00020000uL) +#define INTC_ICDICFR16_INTRCAN3ERR_0 (0x00040000uL) +#define INTC_ICDICFR16_INTRCAN3ERR_1 (0x00080000uL) +#define INTC_ICDICFR16_INTRCAN3TRX_0 (0x00100000uL) +#define INTC_ICDICFR16_INTRCAN3TRX_1 (0x00200000uL) +#define INTC_ICDICFR16_INTRCAN4REC_0 (0x00400000uL) +#define INTC_ICDICFR16_INTRCAN4REC_1 (0x00800000uL) +#define INTC_ICDICFR16_INTRCAN4ERR_0 (0x01000000uL) +#define INTC_ICDICFR16_INTRCAN4ERR_1 (0x02000000uL) +#define INTC_ICDICFR16_INTRCAN4TRX_0 (0x04000000uL) +#define INTC_ICDICFR16_INTRCAN4TRX_1 (0x08000000uL) +#define INTC_ICDICFR16_SPEI0_0 (0x10000000uL) +#define INTC_ICDICFR16_SPEI0_1 (0x20000000uL) +#define INTC_ICDICFR16_SPRI0_0 (0x40000000uL) +#define INTC_ICDICFR16_SPRI0_1 (0x80000000uL) + +#define INTC_ICDICFR17_SPTI0_0 (0x00000001uL) +#define INTC_ICDICFR17_SPTI0_1 (0x00000002uL) +#define INTC_ICDICFR17_SPEI1_0 (0x00000004uL) +#define INTC_ICDICFR17_SPEI1_1 (0x00000008uL) +#define INTC_ICDICFR17_SPRI1_0 (0x00000010uL) +#define INTC_ICDICFR17_SPRI1_1 (0x00000020uL) +#define INTC_ICDICFR17_SPTI1_0 (0x00000040uL) +#define INTC_ICDICFR17_SPTI1_1 (0x00000080uL) +#define INTC_ICDICFR17_SPEI2_0 (0x00000100uL) +#define INTC_ICDICFR17_SPEI2_1 (0x00000200uL) +#define INTC_ICDICFR17_SPRI2_0 (0x00000400uL) +#define INTC_ICDICFR17_SPRI2_1 (0x00000800uL) +#define INTC_ICDICFR17_SPTI2_0 (0x00001000uL) +#define INTC_ICDICFR17_SPTI2_1 (0x00002000uL) +#define INTC_ICDICFR17_SPEI3_0 (0x00004000uL) +#define INTC_ICDICFR17_SPEI3_1 (0x00008000uL) +#define INTC_ICDICFR17_SPRI3_0 (0x00010000uL) +#define INTC_ICDICFR17_SPRI3_1 (0x00020000uL) +#define INTC_ICDICFR17_SPTI3_0 (0x00040000uL) +#define INTC_ICDICFR17_SPTI3_1 (0x00080000uL) +#define INTC_ICDICFR17_SPEI4_0 (0x00100000uL) +#define INTC_ICDICFR17_SPEI4_1 (0x00200000uL) +#define INTC_ICDICFR17_SPRI4_0 (0x00400000uL) +#define INTC_ICDICFR17_SPRI4_1 (0x00800000uL) +#define INTC_ICDICFR17_SPTI4_0 (0x01000000uL) +#define INTC_ICDICFR17_SPTI4_1 (0x02000000uL) +#define INTC_ICDICFR17_IEBBTD_0 (0x04000000uL) +#define INTC_ICDICFR17_IEBBTD_1 (0x08000000uL) +#define INTC_ICDICFR17_IEBBTERR_0 (0x10000000uL) +#define INTC_ICDICFR17_IEBBTERR_1 (0x20000000uL) +#define INTC_ICDICFR17_IEBBTSTA_0 (0x40000000uL) +#define INTC_ICDICFR17_IEBBTSTA_1 (0x80000000uL) + +#define INTC_ICDICFR18_IEBBTV_0 (0x00000001uL) +#define INTC_ICDICFR18_IEBBTV_1 (0x00000002uL) +#define INTC_ICDICFR18_ISY_0 (0x00000004uL) +#define INTC_ICDICFR18_ISY_1 (0x00000008uL) +#define INTC_ICDICFR18_IERR_0 (0x00000010uL) +#define INTC_ICDICFR18_IERR_1 (0x00000020uL) +#define INTC_ICDICFR18_ITARG_0 (0x00000040uL) +#define INTC_ICDICFR18_ITARG_1 (0x00000080uL) +#define INTC_ICDICFR18_ISEC_0 (0x00000100uL) +#define INTC_ICDICFR18_ISEC_1 (0x00000200uL) +#define INTC_ICDICFR18_IBUF_0 (0x00000400uL) +#define INTC_ICDICFR18_IBUF_1 (0x00000800uL) +#define INTC_ICDICFR18_IREADY_0 (0x00001000uL) +#define INTC_ICDICFR18_IREADY_1 (0x00002000uL) +#define INTC_ICDICFR18_FLSTE_0 (0x00004000uL) +#define INTC_ICDICFR18_FLSTE_1 (0x00008000uL) +#define INTC_ICDICFR18_FLTENDI_0 (0x00010000uL) +#define INTC_ICDICFR18_FLTENDI_1 (0x00020000uL) +#define INTC_ICDICFR18_FLTREQ0I_0 (0x00040000uL) +#define INTC_ICDICFR18_FLTREQ0I_1 (0x00080000uL) +#define INTC_ICDICFR18_FLTREQ1I_0 (0x00100000uL) +#define INTC_ICDICFR18_FLTREQ1I_1 (0x00200000uL) +#define INTC_ICDICFR18_MMC0_0 (0x00400000uL) +#define INTC_ICDICFR18_MMC0_1 (0x00800000uL) +#define INTC_ICDICFR18_MMC1_0 (0x01000000uL) +#define INTC_ICDICFR18_MMC1_1 (0x02000000uL) +#define INTC_ICDICFR18_MMC2_0 (0x04000000uL) +#define INTC_ICDICFR18_MMC2_1 (0x08000000uL) +#define INTC_ICDICFR18_SDHI0_3_0 (0x10000000uL) +#define INTC_ICDICFR18_SDHI0_3_1 (0x20000000uL) +#define INTC_ICDICFR18_SDHI0_0_0 (0x40000000uL) +#define INTC_ICDICFR18_SDHI0_0_1 (0x80000000uL) + +#define INTC_ICDICFR19_SDHI0_1_0 (0x00000001uL) +#define INTC_ICDICFR19_SDHI0_1_1 (0x00000002uL) +#define INTC_ICDICFR19_SDHI1_3_0 (0x00000004uL) +#define INTC_ICDICFR19_SDHI1_3_1 (0x00000008uL) +#define INTC_ICDICFR19_SDHI1_0_0 (0x00000010uL) +#define INTC_ICDICFR19_SDHI1_0_1 (0x00000020uL) +#define INTC_ICDICFR19_SDHI1_1_0 (0x00000040uL) +#define INTC_ICDICFR19_SDHI1_1_1 (0x00000080uL) +#define INTC_ICDICFR19_ARM_0 (0x00000100uL) +#define INTC_ICDICFR19_ARM_1 (0x00000200uL) +#define INTC_ICDICFR19_PRD_0 (0x00000400uL) +#define INTC_ICDICFR19_PRD_1 (0x00000800uL) +#define INTC_ICDICFR19_CUP_0 (0x00001000uL) +#define INTC_ICDICFR19_CUP_1 (0x00002000uL) +#define INTC_ICDICFR19_SCUAI0_0 (0x00004000uL) +#define INTC_ICDICFR19_SCUAI0_1 (0x00008000uL) +#define INTC_ICDICFR19_SCUAI1_0 (0x00010000uL) +#define INTC_ICDICFR19_SCUAI1_1 (0x00020000uL) +#define INTC_ICDICFR19_SCUFDI0_0 (0x00040000uL) +#define INTC_ICDICFR19_SCUFDI0_1 (0x00080000uL) +#define INTC_ICDICFR19_SCUFDI1_0 (0x00100000uL) +#define INTC_ICDICFR19_SCUFDI1_1 (0x00200000uL) +#define INTC_ICDICFR19_SCUFDI2_0 (0x00400000uL) +#define INTC_ICDICFR19_SCUFDI2_1 (0x00800000uL) +#define INTC_ICDICFR19_SCUFDI3_0 (0x01000000uL) +#define INTC_ICDICFR19_SCUFDI3_1 (0x02000000uL) +#define INTC_ICDICFR19_SCUFUI0_0 (0x04000000uL) +#define INTC_ICDICFR19_SCUFUI0_1 (0x08000000uL) +#define INTC_ICDICFR19_SCUFUI1_0 (0x10000000uL) +#define INTC_ICDICFR19_SCUFUI1_1 (0x20000000uL) +#define INTC_ICDICFR19_SCUFUI2_0 (0x40000000uL) +#define INTC_ICDICFR19_SCUFUI2_1 (0x80000000uL) + +#define INTC_ICDICFR20_SCUFUI3_0 (0x00000001uL) +#define INTC_ICDICFR20_SCUFUI3_1 (0x00000002uL) +#define INTC_ICDICFR20_SCUDVI0_0 (0x00000004uL) +#define INTC_ICDICFR20_SCUDVI0_1 (0x00000008uL) +#define INTC_ICDICFR20_SCUDVI1_0 (0x00000010uL) +#define INTC_ICDICFR20_SCUDVI1_1 (0x00000020uL) +#define INTC_ICDICFR20_SCUDVI2_0 (0x00000040uL) +#define INTC_ICDICFR20_SCUDVI2_1 (0x00000080uL) +#define INTC_ICDICFR20_SCUDVI3_0 (0x00000100uL) +#define INTC_ICDICFR20_SCUDVI3_1 (0x00000200uL) +#define INTC_ICDICFR20_MLB_CINT_0 (0x00000400uL) +#define INTC_ICDICFR20_MLB_CINT_1 (0x00000800uL) +#define INTC_ICDICFR20_MLB_SINT_0 (0x00001000uL) +#define INTC_ICDICFR20_MLB_SINT_1 (0x00002000uL) +#define INTC_ICDICFR20_DRC0_0 (0x00004000uL) +#define INTC_ICDICFR20_DRC0_1 (0x00008000uL) +#define INTC_ICDICFR20_DRC1_0 (0x00010000uL) +#define INTC_ICDICFR20_DRC1_1 (0x00020000uL) +#define INTC_ICDICFR20_LINI0_INT_T_0 (0x00400000uL) +#define INTC_ICDICFR20_LINI0_INT_T_1 (0x00800000uL) +#define INTC_ICDICFR20_LINI0_INT_R_0 (0x01000000uL) +#define INTC_ICDICFR20_LINI0_INT_R_1 (0x02000000uL) +#define INTC_ICDICFR20_LINI0_INT_S_0 (0x04000000uL) +#define INTC_ICDICFR20_LINI0_INT_S_1 (0x08000000uL) +#define INTC_ICDICFR20_LINI0_INT_M_0 (0x10000000uL) +#define INTC_ICDICFR20_LINI0_INT_M_1 (0x20000000uL) +#define INTC_ICDICFR20_LINI1_INT_T_0 (0x40000000uL) +#define INTC_ICDICFR20_LINI1_INT_T_1 (0x80000000uL) + +#define INTC_ICDICFR21_LINI1_INT_R_0 (0x00000001uL) +#define INTC_ICDICFR21_LINI1_INT_R_1 (0x00000002uL) +#define INTC_ICDICFR21_LINI1_INT_S_0 (0x00000004uL) +#define INTC_ICDICFR21_LINI1_INT_S_1 (0x00000008uL) +#define INTC_ICDICFR21_LINI1_INT_M_0 (0x00000010uL) +#define INTC_ICDICFR21_LINI1_INT_M_1 (0x00000020uL) +#define INTC_ICDICFR21_ERI0_0 (0x00400000uL) +#define INTC_ICDICFR21_ERI0_1 (0x00800000uL) +#define INTC_ICDICFR21_RXI0_0 (0x01000000uL) +#define INTC_ICDICFR21_RXI0_1 (0x02000000uL) +#define INTC_ICDICFR21_TXI0_0 (0x04000000uL) +#define INTC_ICDICFR21_TXI0_1 (0x08000000uL) +#define INTC_ICDICFR21_TEI0_0 (0x10000000uL) +#define INTC_ICDICFR21_TEI0_1 (0x20000000uL) +#define INTC_ICDICFR21_ERI1_0 (0x40000000uL) +#define INTC_ICDICFR21_ERI1_1 (0x80000000uL) + +#define INTC_ICDICFR22_RXI1_0 (0x00000001uL) +#define INTC_ICDICFR22_RXI1_1 (0x00000002uL) +#define INTC_ICDICFR22_TXI1_0 (0x00000004uL) +#define INTC_ICDICFR22_TXI1_1 (0x00000008uL) +#define INTC_ICDICFR22_TEI1_0 (0x00000010uL) +#define INTC_ICDICFR22_TEI1_1 (0x00000020uL) +#define INTC_ICDICFR22_AVBI_DATA_0 (0x00000040uL) +#define INTC_ICDICFR22_AVBI_DATA_1 (0x00000080uL) +#define INTC_ICDICFR22_AVBI_ERROR_0 (0x00000100uL) +#define INTC_ICDICFR22_AVBI_ERROR_1 (0x00000200uL) +#define INTC_ICDICFR22_AVBI_MANAGE_0 (0x00000400uL) +#define INTC_ICDICFR22_AVBI_MANAGE_1 (0x00000800uL) +#define INTC_ICDICFR22_AVBI_MAC_0 (0x00001000uL) +#define INTC_ICDICFR22_AVBI_MAC_1 (0x00002000uL) +#define INTC_ICDICFR22_ETHERI_0 (0x00004000uL) +#define INTC_ICDICFR22_ETHERI_1 (0x00008000uL) +#define INTC_ICDICFR22_CEUI_0 (0x01000000uL) +#define INTC_ICDICFR22_CEUI_1 (0x02000000uL) + +#define INTC_ICDICFR23_H2XMLB_ERRINT_0 (0x04000000uL) +#define INTC_ICDICFR23_H2XMLB_ERRINT_1 (0x08000000uL) +#define INTC_ICDICFR23_H2XIC1_ERRINT_0 (0x10000000uL) +#define INTC_ICDICFR23_H2XIC1_ERRINT_1 (0x20000000uL) +#define INTC_ICDICFR23_X2HPERI1_ERRINT_0 (0x40000000uL) +#define INTC_ICDICFR23_X2HPERI1_ERRINT_1 (0x80000000uL) + +#define INTC_ICDICFR24_X2HPERI2_ERRINT_0 (0x00000001uL) +#define INTC_ICDICFR24_X2HPERI2_ERRINT_1 (0x00000002uL) +#define INTC_ICDICFR24_X2HPERI34_ERRINT_0 (0x00000004uL) +#define INTC_ICDICFR24_X2HPERI34_ERRINT_1 (0x00000008uL) +#define INTC_ICDICFR24_X2HPERI5_ERRINT_0 (0x00000010uL) +#define INTC_ICDICFR24_X2HPERI5_ERRINT_1 (0x00000020uL) +#define INTC_ICDICFR24_X2HPERI67_ERRINT_0 (0x00000040uL) +#define INTC_ICDICFR24_X2HPERI67_ERRINT_1 (0x00000080uL) +#define INTC_ICDICFR24_X2HDBGR_ERRINT_0 (0x00000100uL) +#define INTC_ICDICFR24_X2HDBGR_ERRINT_1 (0x00000200uL) +#define INTC_ICDICFR24_X2HBSC_ERRINT_0 (0x00000400uL) +#define INTC_ICDICFR24_X2HBSC_ERRINT_1 (0x00000800uL) +#define INTC_ICDICFR24_X2HSPI1_ERRINT_0 (0x00001000uL) +#define INTC_ICDICFR24_X2HSPI1_ERRINT_1 (0x00002000uL) +#define INTC_ICDICFR24_X2HSPI2_ERRINT_0 (0x00004000uL) +#define INTC_ICDICFR24_X2HSPI2_ERRINT_1 (0x00008000uL) +#define INTC_ICDICFR24_PRRI_0 (0x00010000uL) +#define INTC_ICDICFR24_PRRI_1 (0x00020000uL) +#define INTC_ICDICFR24_IFEI0_0 (0x00040000uL) +#define INTC_ICDICFR24_IFEI0_1 (0x00080000uL) +#define INTC_ICDICFR24_OFFI0_0 (0x00100000uL) +#define INTC_ICDICFR24_OFFI0_1 (0x00200000uL) +#define INTC_ICDICFR24_PFVEI0_0 (0x00400000uL) +#define INTC_ICDICFR24_PFVEI0_1 (0x00800000uL) +#define INTC_ICDICFR24_IFEI1_0 (0x01000000uL) +#define INTC_ICDICFR24_IFEI1_1 (0x02000000uL) +#define INTC_ICDICFR24_OFFI1_0 (0x04000000uL) +#define INTC_ICDICFR24_OFFI1_1 (0x08000000uL) +#define INTC_ICDICFR24_PFVEI1_0 (0x10000000uL) +#define INTC_ICDICFR24_PFVEI1_1 (0x20000000uL) + +#define INTC_ICDICFR26_TINT0_0 (0x00000001uL) +#define INTC_ICDICFR26_TINT0_1 (0x00000002uL) +#define INTC_ICDICFR26_TINT1_0 (0x00000004uL) +#define INTC_ICDICFR26_TINT1_1 (0x00000008uL) +#define INTC_ICDICFR26_TINT2_0 (0x00000010uL) +#define INTC_ICDICFR26_TINT2_1 (0x00000020uL) +#define INTC_ICDICFR26_TINT3_0 (0x00000040uL) +#define INTC_ICDICFR26_TINT3_1 (0x00000080uL) +#define INTC_ICDICFR26_TINT4_0 (0x00000100uL) +#define INTC_ICDICFR26_TINT4_1 (0x00000200uL) +#define INTC_ICDICFR26_TINT5_0 (0x00000400uL) +#define INTC_ICDICFR26_TINT5_1 (0x00000800uL) +#define INTC_ICDICFR26_TINT6_0 (0x00001000uL) +#define INTC_ICDICFR26_TINT6_1 (0x00002000uL) +#define INTC_ICDICFR26_TINT7_0 (0x00004000uL) +#define INTC_ICDICFR26_TINT7_1 (0x00008000uL) +#define INTC_ICDICFR26_TINT8_0 (0x00010000uL) +#define INTC_ICDICFR26_TINT8_1 (0x00020000uL) +#define INTC_ICDICFR26_TINT9_0 (0x00040000uL) +#define INTC_ICDICFR26_TINT9_1 (0x00080000uL) +#define INTC_ICDICFR26_TINT10_0 (0x00100000uL) +#define INTC_ICDICFR26_TINT10_1 (0x00200000uL) +#define INTC_ICDICFR26_TINT11_0 (0x00400000uL) +#define INTC_ICDICFR26_TINT11_1 (0x00800000uL) +#define INTC_ICDICFR26_TINT12_0 (0x01000000uL) +#define INTC_ICDICFR26_TINT12_1 (0x02000000uL) +#define INTC_ICDICFR26_TINT13_0 (0x04000000uL) +#define INTC_ICDICFR26_TINT13_1 (0x08000000uL) +#define INTC_ICDICFR26_TINT14_0 (0x10000000uL) +#define INTC_ICDICFR26_TINT14_1 (0x20000000uL) +#define INTC_ICDICFR26_TINT15_0 (0x40000000uL) +#define INTC_ICDICFR26_TINT15_1 (0x80000000uL) + +#define INTC_ICDICFR27_TINT16_0 (0x00000001uL) +#define INTC_ICDICFR27_TINT16_1 (0x00000002uL) +#define INTC_ICDICFR27_TINT17_0 (0x00000004uL) +#define INTC_ICDICFR27_TINT17_1 (0x00000008uL) +#define INTC_ICDICFR27_TINT18_0 (0x00000010uL) +#define INTC_ICDICFR27_TINT18_1 (0x00000020uL) +#define INTC_ICDICFR27_TINT19_0 (0x00000040uL) +#define INTC_ICDICFR27_TINT19_1 (0x00000080uL) +#define INTC_ICDICFR27_TINT20_0 (0x00000100uL) +#define INTC_ICDICFR27_TINT20_1 (0x00000200uL) +#define INTC_ICDICFR27_TINT21_0 (0x00000400uL) +#define INTC_ICDICFR27_TINT21_1 (0x00000800uL) +#define INTC_ICDICFR27_TINT22_0 (0x00001000uL) +#define INTC_ICDICFR27_TINT22_1 (0x00002000uL) +#define INTC_ICDICFR27_TINT23_0 (0x00004000uL) +#define INTC_ICDICFR27_TINT23_1 (0x00008000uL) +#define INTC_ICDICFR27_TINT24_0 (0x00010000uL) +#define INTC_ICDICFR27_TINT24_1 (0x00020000uL) +#define INTC_ICDICFR27_TINT25_0 (0x00040000uL) +#define INTC_ICDICFR27_TINT25_1 (0x00080000uL) +#define INTC_ICDICFR27_TINT26_0 (0x00100000uL) +#define INTC_ICDICFR27_TINT26_1 (0x00200000uL) +#define INTC_ICDICFR27_TINT27_0 (0x00400000uL) +#define INTC_ICDICFR27_TINT27_1 (0x00800000uL) +#define INTC_ICDICFR27_TINT28_0 (0x01000000uL) +#define INTC_ICDICFR27_TINT28_1 (0x02000000uL) +#define INTC_ICDICFR27_TINT29_0 (0x04000000uL) +#define INTC_ICDICFR27_TINT29_1 (0x08000000uL) +#define INTC_ICDICFR27_TINT30_0 (0x10000000uL) +#define INTC_ICDICFR27_TINT30_1 (0x20000000uL) +#define INTC_ICDICFR27_TINT31_0 (0x40000000uL) +#define INTC_ICDICFR27_TINT31_1 (0x80000000uL) + +#define INTC_ICDICFR28_TINT32_0 (0x00000001uL) +#define INTC_ICDICFR28_TINT32_1 (0x00000002uL) +#define INTC_ICDICFR28_TINT33_0 (0x00000004uL) +#define INTC_ICDICFR28_TINT33_1 (0x00000008uL) +#define INTC_ICDICFR28_TINT34_0 (0x00000010uL) +#define INTC_ICDICFR28_TINT34_1 (0x00000020uL) +#define INTC_ICDICFR28_TINT35_0 (0x00000040uL) +#define INTC_ICDICFR28_TINT35_1 (0x00000080uL) +#define INTC_ICDICFR28_TINT36_0 (0x00000100uL) +#define INTC_ICDICFR28_TINT36_1 (0x00000200uL) +#define INTC_ICDICFR28_TINT37_0 (0x00000400uL) +#define INTC_ICDICFR28_TINT37_1 (0x00000800uL) +#define INTC_ICDICFR28_TINT38_0 (0x00001000uL) +#define INTC_ICDICFR28_TINT38_1 (0x00002000uL) +#define INTC_ICDICFR28_TINT39_0 (0x00004000uL) +#define INTC_ICDICFR28_TINT39_1 (0x00008000uL) +#define INTC_ICDICFR28_TINT40_0 (0x00010000uL) +#define INTC_ICDICFR28_TINT40_1 (0x00020000uL) +#define INTC_ICDICFR28_TINT41_0 (0x00040000uL) +#define INTC_ICDICFR28_TINT41_1 (0x00080000uL) +#define INTC_ICDICFR28_TINT42_0 (0x00100000uL) +#define INTC_ICDICFR28_TINT42_1 (0x00200000uL) +#define INTC_ICDICFR28_TINT43_0 (0x00400000uL) +#define INTC_ICDICFR28_TINT43_1 (0x00800000uL) +#define INTC_ICDICFR28_TINT44_0 (0x01000000uL) +#define INTC_ICDICFR28_TINT44_1 (0x02000000uL) +#define INTC_ICDICFR28_TINT45_0 (0x04000000uL) +#define INTC_ICDICFR28_TINT45_1 (0x08000000uL) +#define INTC_ICDICFR28_TINT46_0 (0x10000000uL) +#define INTC_ICDICFR28_TINT46_1 (0x20000000uL) +#define INTC_ICDICFR28_TINT47_0 (0x40000000uL) +#define INTC_ICDICFR28_TINT47_1 (0x80000000uL) + +#define INTC_ICDICFR29_TINT48_0 (0x00000001uL) +#define INTC_ICDICFR29_TINT48_1 (0x00000002uL) +#define INTC_ICDICFR29_TINT49_0 (0x00000004uL) +#define INTC_ICDICFR29_TINT49_1 (0x00000008uL) +#define INTC_ICDICFR29_TINT50_0 (0x00000010uL) +#define INTC_ICDICFR29_TINT50_1 (0x00000020uL) +#define INTC_ICDICFR29_TINT51_0 (0x00000040uL) +#define INTC_ICDICFR29_TINT51_1 (0x00000080uL) +#define INTC_ICDICFR29_TINT52_0 (0x00000100uL) +#define INTC_ICDICFR29_TINT52_1 (0x00000200uL) +#define INTC_ICDICFR29_TINT53_0 (0x00000400uL) +#define INTC_ICDICFR29_TINT53_1 (0x00000800uL) +#define INTC_ICDICFR29_TINT54_0 (0x00001000uL) +#define INTC_ICDICFR29_TINT54_1 (0x00002000uL) +#define INTC_ICDICFR29_TINT55_0 (0x00004000uL) +#define INTC_ICDICFR29_TINT55_1 (0x00008000uL) +#define INTC_ICDICFR29_TINT56_0 (0x00010000uL) +#define INTC_ICDICFR29_TINT56_1 (0x00020000uL) +#define INTC_ICDICFR29_TINT57_0 (0x00040000uL) +#define INTC_ICDICFR29_TINT57_1 (0x00080000uL) +#define INTC_ICDICFR29_TINT58_0 (0x00100000uL) +#define INTC_ICDICFR29_TINT58_1 (0x00200000uL) +#define INTC_ICDICFR29_TINT59_0 (0x00400000uL) +#define INTC_ICDICFR29_TINT59_1 (0x00800000uL) +#define INTC_ICDICFR29_TINT60_0 (0x01000000uL) +#define INTC_ICDICFR29_TINT60_1 (0x02000000uL) +#define INTC_ICDICFR29_TINT61_0 (0x04000000uL) +#define INTC_ICDICFR29_TINT61_1 (0x08000000uL) +#define INTC_ICDICFR29_TINT62_0 (0x10000000uL) +#define INTC_ICDICFR29_TINT62_1 (0x20000000uL) +#define INTC_ICDICFR29_TINT63_0 (0x40000000uL) +#define INTC_ICDICFR29_TINT63_1 (0x80000000uL) + +#define INTC_ICDICFR30_TINT64_0 (0x00000001uL) +#define INTC_ICDICFR30_TINT64_1 (0x00000002uL) +#define INTC_ICDICFR30_TINT65_0 (0x00000004uL) +#define INTC_ICDICFR30_TINT65_1 (0x00000008uL) +#define INTC_ICDICFR30_TINT66_0 (0x00000010uL) +#define INTC_ICDICFR30_TINT66_1 (0x00000020uL) +#define INTC_ICDICFR30_TINT67_0 (0x00000040uL) +#define INTC_ICDICFR30_TINT67_1 (0x00000080uL) +#define INTC_ICDICFR30_TINT68_0 (0x00000100uL) +#define INTC_ICDICFR30_TINT68_1 (0x00000200uL) +#define INTC_ICDICFR30_TINT69_0 (0x00000400uL) +#define INTC_ICDICFR30_TINT69_1 (0x00000800uL) +#define INTC_ICDICFR30_TINT70_0 (0x00001000uL) +#define INTC_ICDICFR30_TINT70_1 (0x00002000uL) +#define INTC_ICDICFR30_TINT71_0 (0x00004000uL) +#define INTC_ICDICFR30_TINT71_1 (0x00008000uL) +#define INTC_ICDICFR30_TINT72_0 (0x00010000uL) +#define INTC_ICDICFR30_TINT72_1 (0x00020000uL) +#define INTC_ICDICFR30_TINT73_0 (0x00040000uL) +#define INTC_ICDICFR30_TINT73_1 (0x00080000uL) +#define INTC_ICDICFR30_TINT74_0 (0x00100000uL) +#define INTC_ICDICFR30_TINT74_1 (0x00200000uL) +#define INTC_ICDICFR30_TINT75_0 (0x00400000uL) +#define INTC_ICDICFR30_TINT75_1 (0x00800000uL) +#define INTC_ICDICFR30_TINT76_0 (0x01000000uL) +#define INTC_ICDICFR30_TINT76_1 (0x02000000uL) +#define INTC_ICDICFR30_TINT77_0 (0x04000000uL) +#define INTC_ICDICFR30_TINT77_1 (0x08000000uL) +#define INTC_ICDICFR30_TINT78_0 (0x10000000uL) +#define INTC_ICDICFR30_TINT78_1 (0x20000000uL) +#define INTC_ICDICFR30_TINT79_0 (0x40000000uL) +#define INTC_ICDICFR30_TINT79_1 (0x80000000uL) + +#define INTC_ICDICFR31_TINT80_0 (0x00000001uL) +#define INTC_ICDICFR31_TINT80_1 (0x00000002uL) +#define INTC_ICDICFR31_TINT81_0 (0x00000004uL) +#define INTC_ICDICFR31_TINT81_1 (0x00000008uL) +#define INTC_ICDICFR31_TINT82_0 (0x00000010uL) +#define INTC_ICDICFR31_TINT82_1 (0x00000020uL) +#define INTC_ICDICFR31_TINT83_0 (0x00000040uL) +#define INTC_ICDICFR31_TINT83_1 (0x00000080uL) +#define INTC_ICDICFR31_TINT84_0 (0x00000100uL) +#define INTC_ICDICFR31_TINT84_1 (0x00000200uL) +#define INTC_ICDICFR31_TINT85_0 (0x00000400uL) +#define INTC_ICDICFR31_TINT85_1 (0x00000800uL) +#define INTC_ICDICFR31_TINT86_0 (0x00001000uL) +#define INTC_ICDICFR31_TINT86_1 (0x00002000uL) +#define INTC_ICDICFR31_TINT87_0 (0x00004000uL) +#define INTC_ICDICFR31_TINT87_1 (0x00008000uL) +#define INTC_ICDICFR31_TINT88_0 (0x00010000uL) +#define INTC_ICDICFR31_TINT88_1 (0x00020000uL) +#define INTC_ICDICFR31_TINT89_0 (0x00040000uL) +#define INTC_ICDICFR31_TINT89_1 (0x00080000uL) +#define INTC_ICDICFR31_TINT90_0 (0x00100000uL) +#define INTC_ICDICFR31_TINT90_1 (0x00200000uL) +#define INTC_ICDICFR31_TINT91_0 (0x00400000uL) +#define INTC_ICDICFR31_TINT91_1 (0x00800000uL) +#define INTC_ICDICFR31_TINT92_0 (0x01000000uL) +#define INTC_ICDICFR31_TINT92_1 (0x02000000uL) +#define INTC_ICDICFR31_TINT93_0 (0x04000000uL) +#define INTC_ICDICFR31_TINT93_1 (0x08000000uL) +#define INTC_ICDICFR31_TINT94_0 (0x10000000uL) +#define INTC_ICDICFR31_TINT94_1 (0x20000000uL) +#define INTC_ICDICFR31_TINT95_0 (0x40000000uL) +#define INTC_ICDICFR31_TINT95_1 (0x80000000uL) + +#define INTC_ICDICFR32_TINT96_0 (0x00000001uL) +#define INTC_ICDICFR32_TINT96_1 (0x00000002uL) +#define INTC_ICDICFR32_TINT97_0 (0x00000004uL) +#define INTC_ICDICFR32_TINT97_1 (0x00000008uL) +#define INTC_ICDICFR32_TINT98_0 (0x00000010uL) +#define INTC_ICDICFR32_TINT98_1 (0x00000020uL) +#define INTC_ICDICFR32_TINT99_0 (0x00000040uL) +#define INTC_ICDICFR32_TINT99_1 (0x00000080uL) +#define INTC_ICDICFR32_TINT100_0 (0x00000100uL) +#define INTC_ICDICFR32_TINT100_1 (0x00000200uL) +#define INTC_ICDICFR32_TINT101_0 (0x00000400uL) +#define INTC_ICDICFR32_TINT101_1 (0x00000800uL) +#define INTC_ICDICFR32_TINT102_0 (0x00001000uL) +#define INTC_ICDICFR32_TINT102_1 (0x00002000uL) +#define INTC_ICDICFR32_TINT103_0 (0x00004000uL) +#define INTC_ICDICFR32_TINT103_1 (0x00008000uL) +#define INTC_ICDICFR32_TINT104_0 (0x00010000uL) +#define INTC_ICDICFR32_TINT104_1 (0x00020000uL) +#define INTC_ICDICFR32_TINT105_0 (0x00040000uL) +#define INTC_ICDICFR32_TINT105_1 (0x00080000uL) +#define INTC_ICDICFR32_TINT106_0 (0x00100000uL) +#define INTC_ICDICFR32_TINT106_1 (0x00200000uL) +#define INTC_ICDICFR32_TINT107_0 (0x00400000uL) +#define INTC_ICDICFR32_TINT107_1 (0x00800000uL) +#define INTC_ICDICFR32_TINT108_0 (0x01000000uL) +#define INTC_ICDICFR32_TINT108_1 (0x02000000uL) +#define INTC_ICDICFR32_TINT109_0 (0x04000000uL) +#define INTC_ICDICFR32_TINT109_1 (0x08000000uL) +#define INTC_ICDICFR32_TINT110_0 (0x10000000uL) +#define INTC_ICDICFR32_TINT110_1 (0x20000000uL) +#define INTC_ICDICFR32_TINT111_0 (0x40000000uL) +#define INTC_ICDICFR32_TINT111_1 (0x80000000uL) + +#define INTC_ICDICFR33_TINT112_0 (0x00000001uL) +#define INTC_ICDICFR33_TINT112_1 (0x00000002uL) +#define INTC_ICDICFR33_TINT113_0 (0x00000004uL) +#define INTC_ICDICFR33_TINT113_1 (0x00000008uL) +#define INTC_ICDICFR33_TINT114_0 (0x00000010uL) +#define INTC_ICDICFR33_TINT114_1 (0x00000020uL) +#define INTC_ICDICFR33_TINT115_0 (0x00000040uL) +#define INTC_ICDICFR33_TINT115_1 (0x00000080uL) +#define INTC_ICDICFR33_TINT116_0 (0x00000100uL) +#define INTC_ICDICFR33_TINT116_1 (0x00000200uL) +#define INTC_ICDICFR33_TINT117_0 (0x00000400uL) +#define INTC_ICDICFR33_TINT117_1 (0x00000800uL) +#define INTC_ICDICFR33_TINT118_0 (0x00001000uL) +#define INTC_ICDICFR33_TINT118_1 (0x00002000uL) +#define INTC_ICDICFR33_TINT119_0 (0x00004000uL) +#define INTC_ICDICFR33_TINT119_1 (0x00008000uL) +#define INTC_ICDICFR33_TINT120_0 (0x00010000uL) +#define INTC_ICDICFR33_TINT120_1 (0x00020000uL) +#define INTC_ICDICFR33_TINT121_0 (0x00040000uL) +#define INTC_ICDICFR33_TINT121_1 (0x00080000uL) +#define INTC_ICDICFR33_TINT122_0 (0x00100000uL) +#define INTC_ICDICFR33_TINT122_1 (0x00200000uL) +#define INTC_ICDICFR33_TINT123_0 (0x00400000uL) +#define INTC_ICDICFR33_TINT123_1 (0x00800000uL) +#define INTC_ICDICFR33_TINT124_0 (0x01000000uL) +#define INTC_ICDICFR33_TINT124_1 (0x02000000uL) +#define INTC_ICDICFR33_TINT125_0 (0x04000000uL) +#define INTC_ICDICFR33_TINT125_1 (0x08000000uL) +#define INTC_ICDICFR33_TINT126_0 (0x10000000uL) +#define INTC_ICDICFR33_TINT126_1 (0x20000000uL) +#define INTC_ICDICFR33_TINT127_0 (0x40000000uL) +#define INTC_ICDICFR33_TINT127_1 (0x80000000uL) + +#define INTC_ICDICFR34_TINT128_0 (0x00000001uL) +#define INTC_ICDICFR34_TINT128_1 (0x00000002uL) +#define INTC_ICDICFR34_TINT129_0 (0x00000004uL) +#define INTC_ICDICFR34_TINT129_1 (0x00000008uL) +#define INTC_ICDICFR34_TINT130_0 (0x00000010uL) +#define INTC_ICDICFR34_TINT130_1 (0x00000020uL) +#define INTC_ICDICFR34_TINT131_0 (0x00000040uL) +#define INTC_ICDICFR34_TINT131_1 (0x00000080uL) +#define INTC_ICDICFR34_TINT132_0 (0x00000100uL) +#define INTC_ICDICFR34_TINT132_1 (0x00000200uL) +#define INTC_ICDICFR34_TINT133_0 (0x00000400uL) +#define INTC_ICDICFR34_TINT133_1 (0x00000800uL) +#define INTC_ICDICFR34_TINT134_0 (0x00001000uL) +#define INTC_ICDICFR34_TINT134_1 (0x00002000uL) +#define INTC_ICDICFR34_TINT135_0 (0x00004000uL) +#define INTC_ICDICFR34_TINT135_1 (0x00008000uL) +#define INTC_ICDICFR34_TINT136_0 (0x00010000uL) +#define INTC_ICDICFR34_TINT136_1 (0x00020000uL) +#define INTC_ICDICFR34_TINT137_0 (0x00040000uL) +#define INTC_ICDICFR34_TINT137_1 (0x00080000uL) +#define INTC_ICDICFR34_TINT138_0 (0x00100000uL) +#define INTC_ICDICFR34_TINT138_1 (0x00200000uL) +#define INTC_ICDICFR34_TINT139_0 (0x00400000uL) +#define INTC_ICDICFR34_TINT139_1 (0x00800000uL) +#define INTC_ICDICFR34_TINT140_0 (0x01000000uL) +#define INTC_ICDICFR34_TINT140_1 (0x02000000uL) +#define INTC_ICDICFR34_TINT141_0 (0x04000000uL) +#define INTC_ICDICFR34_TINT141_1 (0x08000000uL) +#define INTC_ICDICFR34_TINT142_0 (0x10000000uL) +#define INTC_ICDICFR34_TINT142_1 (0x20000000uL) +#define INTC_ICDICFR34_TINT143_0 (0x40000000uL) +#define INTC_ICDICFR34_TINT143_1 (0x80000000uL) + +#define INTC_ICDICFR35_TINT144_0 (0x00000001uL) +#define INTC_ICDICFR35_TINT144_1 (0x00000002uL) +#define INTC_ICDICFR35_TINT145_0 (0x00000004uL) +#define INTC_ICDICFR35_TINT145_1 (0x00000008uL) +#define INTC_ICDICFR35_TINT146_0 (0x00000010uL) +#define INTC_ICDICFR35_TINT146_1 (0x00000020uL) +#define INTC_ICDICFR35_TINT147_0 (0x00000040uL) +#define INTC_ICDICFR35_TINT147_1 (0x00000080uL) +#define INTC_ICDICFR35_TINT148_0 (0x00000100uL) +#define INTC_ICDICFR35_TINT148_1 (0x00000200uL) +#define INTC_ICDICFR35_TINT149_0 (0x00000400uL) +#define INTC_ICDICFR35_TINT149_1 (0x00000800uL) +#define INTC_ICDICFR35_TINT150_0 (0x00001000uL) +#define INTC_ICDICFR35_TINT150_1 (0x00002000uL) +#define INTC_ICDICFR35_TINT151_0 (0x00004000uL) +#define INTC_ICDICFR35_TINT151_1 (0x00008000uL) +#define INTC_ICDICFR35_TINT152_0 (0x00010000uL) +#define INTC_ICDICFR35_TINT152_1 (0x00020000uL) +#define INTC_ICDICFR35_TINT153_0 (0x00040000uL) +#define INTC_ICDICFR35_TINT153_1 (0x00080000uL) +#define INTC_ICDICFR35_TINT154_0 (0x00100000uL) +#define INTC_ICDICFR35_TINT154_1 (0x00200000uL) +#define INTC_ICDICFR35_TINT155_0 (0x00400000uL) +#define INTC_ICDICFR35_TINT155_1 (0x00800000uL) +#define INTC_ICDICFR35_TINT156_0 (0x01000000uL) +#define INTC_ICDICFR35_TINT156_1 (0x02000000uL) +#define INTC_ICDICFR35_TINT157_0 (0x04000000uL) +#define INTC_ICDICFR35_TINT157_1 (0x08000000uL) +#define INTC_ICDICFR35_TINT158_0 (0x10000000uL) +#define INTC_ICDICFR35_TINT158_1 (0x20000000uL) +#define INTC_ICDICFR35_TINT159_0 (0x40000000uL) +#define INTC_ICDICFR35_TINT159_1 (0x80000000uL) + +#define INTC_ICDICFR36_TINT160_0 (0x00000001uL) +#define INTC_ICDICFR36_TINT160_1 (0x00000002uL) +#define INTC_ICDICFR36_TINT161_0 (0x00000004uL) +#define INTC_ICDICFR36_TINT161_1 (0x00000008uL) +#define INTC_ICDICFR36_TINT162_0 (0x00000010uL) +#define INTC_ICDICFR36_TINT162_1 (0x00000020uL) +#define INTC_ICDICFR36_TINT163_0 (0x00000040uL) +#define INTC_ICDICFR36_TINT163_1 (0x00000080uL) +#define INTC_ICDICFR36_TINT164_0 (0x00000100uL) +#define INTC_ICDICFR36_TINT164_1 (0x00000200uL) +#define INTC_ICDICFR36_TINT165_0 (0x00000400uL) +#define INTC_ICDICFR36_TINT165_1 (0x00000800uL) +#define INTC_ICDICFR36_TINT166_0 (0x00001000uL) +#define INTC_ICDICFR36_TINT166_1 (0x00002000uL) +#define INTC_ICDICFR36_TINT167_0 (0x00004000uL) +#define INTC_ICDICFR36_TINT167_1 (0x00008000uL) +#define INTC_ICDICFR36_TINT168_0 (0x00010000uL) +#define INTC_ICDICFR36_TINT168_1 (0x00020000uL) +#define INTC_ICDICFR36_TINT169_0 (0x00040000uL) +#define INTC_ICDICFR36_TINT169_1 (0x00080000uL) +#define INTC_ICDICFR36_TINT170_0 (0x00100000uL) +#define INTC_ICDICFR36_TINT170_1 (0x00200000uL) + +#define INTC_ICDSGIR_SGIINTID (0x0000000FuL) +#define INTC_ICDSGIR_SATT (0x00008000uL) +#define INTC_ICDSGIR_CPUTargetList (0x00FF0000uL) +#define INTC_ICDSGIR_TargetListFilter (0x03000000uL) + +#define INTC_ICCICR_EnableS (0x00000001uL) +#define INTC_ICCICR_EnableNS (0x00000002uL) +#define INTC_ICCICR_AckCtl (0x00000004uL) +#define INTC_ICCICR_FIQEn (0x00000008uL) +#define INTC_ICCICR_SBPR (0x00000010uL) + +#define INTC_ICCPMR_Priority (0x000000FFuL) + +#define INTC_ICCBPR_Binarypoint (0x00000007uL) + +#define INTC_ICCIAR_ACKINTID (0x000003FFuL) +#define INTC_ICCIAR_CPUID (0x00001C00uL) + +#define INTC_ICCEOIR_EOIINTID (0x000003FFuL) +#define INTC_ICCEOIR_CPUID (0x00001C00uL) + +#define INTC_ICCRPR_Priority (0x000000FFuL) + +#define INTC_ICCHPIR_PENDINTID (0x000003FFuL) +#define INTC_ICCHPIR_CPUID (0x00001C00uL) + +#define INTC_ICCABPR_Binarypoint (0x00000007uL) + +#define INTC_ICCIIDR_Implementer (0x00000FFFuL) +#define INTC_ICCIIDR_Revision (0x0000F000uL) +#define INTC_ICCIIDR_Architecture_version (0x000F0000uL) +#define INTC_ICCIIDR_ProductID (0xFFF00000uL) + +#define INTC_ICR0_NMIF (0x0002u) +#define INTC_ICR0_NMIE (0x0100u) +#define INTC_ICR0_NMIL (0x8000u) + +#define INTC_ICR1_IRQ00S (0x0001u) +#define INTC_ICR1_IRQ01S (0x0002u) +#define INTC_ICR1_IRQ10S (0x0004u) +#define INTC_ICR1_IRQ11S (0x0008u) +#define INTC_ICR1_IRQ20S (0x0010u) +#define INTC_ICR1_IRQ21S (0x0020u) +#define INTC_ICR1_IRQ30S (0x0040u) +#define INTC_ICR1_IRQ31S (0x0080u) +#define INTC_ICR1_IRQ40S (0x0100u) +#define INTC_ICR1_IRQ41S (0x0200u) +#define INTC_ICR1_IRQ50S (0x0400u) +#define INTC_ICR1_IRQ51S (0x0800u) +#define INTC_ICR1_IRQ60S (0x1000u) +#define INTC_ICR1_IRQ61S (0x2000u) +#define INTC_ICR1_IRQ70S (0x4000u) +#define INTC_ICR1_IRQ71S (0x8000u) + +#define INTC_IRQRR_IRQ0F (0x0001u) +#define INTC_IRQRR_IRQ1F (0x0002u) +#define INTC_IRQRR_IRQ2F (0x0004u) +#define INTC_IRQRR_IRQ3F (0x0008u) +#define INTC_IRQRR_IRQ4F (0x0010u) +#define INTC_IRQRR_IRQ5F (0x0020u) +#define INTC_IRQRR_IRQ6F (0x0040u) +#define INTC_IRQRR_IRQ7F (0x0080u) + + +/* ==== Shift values for IO registers ==== */ +#define INTC_ICDDCR_Enable_SHIFT (0u) + +#define INTC_ICDICTR_ITLinesNumber_SHIFT (0u) +#define INTC_ICDICTR_CPUNumber_SHIFT (5u) +#define INTC_ICDICTR_SecurityExtn_SHIFT (10u) +#define INTC_ICDICTR_LSPI_SHIFT (11u) + +#define INTC_ICDIIDR_Implementer_SHIFT (0u) +#define INTC_ICDIIDR_Revision_SHIFT (12u) +#define INTC_ICDIIDR_Variant_SHIFT (16u) +#define INTC_ICDIIDR_ProductID_SHIFT (24u) + +#define INTC_ICDISR0_SW0_SHIFT (0u) +#define INTC_ICDISR0_SW1_SHIFT (1u) +#define INTC_ICDISR0_SW2_SHIFT (2u) +#define INTC_ICDISR0_SW3_SHIFT (3u) +#define INTC_ICDISR0_SW4_SHIFT (4u) +#define INTC_ICDISR0_SW5_SHIFT (5u) +#define INTC_ICDISR0_SW6_SHIFT (6u) +#define INTC_ICDISR0_SW7_SHIFT (7u) +#define INTC_ICDISR0_SW8_SHIFT (8u) +#define INTC_ICDISR0_SW9_SHIFT (9u) +#define INTC_ICDISR0_SW10_SHIFT (10u) +#define INTC_ICDISR0_SW11_SHIFT (11u) +#define INTC_ICDISR0_SW12_SHIFT (12u) +#define INTC_ICDISR0_SW13_SHIFT (13u) +#define INTC_ICDISR0_SW14_SHIFT (14u) +#define INTC_ICDISR0_SW15_SHIFT (15u) +#define INTC_ICDISR0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDISR0_COMMRX0_SHIFT (17u) +#define INTC_ICDISR0_COMMTX0_SHIFT (18u) +#define INTC_ICDISR0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDISR1_IRQ0_SHIFT (0u) +#define INTC_ICDISR1_IRQ1_SHIFT (1u) +#define INTC_ICDISR1_IRQ2_SHIFT (2u) +#define INTC_ICDISR1_IRQ3_SHIFT (3u) +#define INTC_ICDISR1_IRQ4_SHIFT (4u) +#define INTC_ICDISR1_IRQ5_SHIFT (5u) +#define INTC_ICDISR1_IRQ6_SHIFT (6u) +#define INTC_ICDISR1_IRQ7_SHIFT (7u) +#define INTC_ICDISR1_PL310ERR_SHIFT (8u) +#define INTC_ICDISR1_DMAINT0_SHIFT (9u) +#define INTC_ICDISR1_DMAINT1_SHIFT (10u) +#define INTC_ICDISR1_DMAINT2_SHIFT (11u) +#define INTC_ICDISR1_DMAINT3_SHIFT (12u) +#define INTC_ICDISR1_DMAINT4_SHIFT (13u) +#define INTC_ICDISR1_DMAINT5_SHIFT (14u) +#define INTC_ICDISR1_DMAINT6_SHIFT (15u) +#define INTC_ICDISR1_DMAINT7_SHIFT (16u) +#define INTC_ICDISR1_DMAINT8_SHIFT (17u) +#define INTC_ICDISR1_DMAINT9_SHIFT (18u) +#define INTC_ICDISR1_DMAINT10_SHIFT (19u) +#define INTC_ICDISR1_DMAINT11_SHIFT (20u) +#define INTC_ICDISR1_DMAINT12_SHIFT (21u) +#define INTC_ICDISR1_DMAINT13_SHIFT (22u) +#define INTC_ICDISR1_DMAINT14_SHIFT (23u) +#define INTC_ICDISR1_DMAINT15_SHIFT (24u) +#define INTC_ICDISR1_DMAERR_SHIFT (25u) + +#define INTC_ICDISR2_USBI0_SHIFT (9u) +#define INTC_ICDISR2_USBI1_SHIFT (10u) +#define INTC_ICDISR2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDISR2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDISR2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDISR2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDISR2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDISR2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDISR2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDISR2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDISR2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDISR2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDISR2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDISR2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDISR2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDISR2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDISR2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDISR2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDISR2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDISR2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDISR2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDISR2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDISR2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDISR3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDISR3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDISR3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDISR3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDISR3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDISR3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDISR3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDISR3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDISR3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDISR3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDISR3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDISR3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDISR3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDISR3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDISR3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDISR3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDISR3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDISR3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDISR3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDISR3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDISR3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDISR3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDISR3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDISR3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDISR3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDISR3_IMRDI_SHIFT (27u) +#define INTC_ICDISR3_IMR2I0_SHIFT (28u) +#define INTC_ICDISR3_IMR2I1_SHIFT (29u) +#define INTC_ICDISR3_JEDI_SHIFT (30u) +#define INTC_ICDISR3_JDTI_SHIFT (31u) + +#define INTC_ICDISR4_CMP0_SHIFT (0u) +#define INTC_ICDISR4_CMP1_SHIFT (1u) +#define INTC_ICDISR4_INT0_SHIFT (2u) +#define INTC_ICDISR4_INT1_SHIFT (3u) +#define INTC_ICDISR4_INT2_SHIFT (4u) +#define INTC_ICDISR4_INT3_SHIFT (5u) +#define INTC_ICDISR4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDISR4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDISR4_CMI_SHIFT (8u) +#define INTC_ICDISR4_WTOUT_SHIFT (9u) +#define INTC_ICDISR4_ITI_SHIFT (10u) +#define INTC_ICDISR4_TGI0A_SHIFT (11u) +#define INTC_ICDISR4_TGI0B_SHIFT (12u) +#define INTC_ICDISR4_TGI0C_SHIFT (13u) +#define INTC_ICDISR4_TGI0D_SHIFT (14u) +#define INTC_ICDISR4_TGI0V_SHIFT (15u) +#define INTC_ICDISR4_TGI0E_SHIFT (16u) +#define INTC_ICDISR4_TGI0F_SHIFT (17u) +#define INTC_ICDISR4_TGI1A_SHIFT (18u) +#define INTC_ICDISR4_TGI1B_SHIFT (19u) +#define INTC_ICDISR4_TGI1V_SHIFT (20u) +#define INTC_ICDISR4_TGI1U_SHIFT (21u) +#define INTC_ICDISR4_TGI2A_SHIFT (22u) +#define INTC_ICDISR4_TGI2B_SHIFT (23u) +#define INTC_ICDISR4_TGI2V_SHIFT (24u) +#define INTC_ICDISR4_TGI2U_SHIFT (25u) +#define INTC_ICDISR4_TGI3A_SHIFT (26u) +#define INTC_ICDISR4_TGI3B_SHIFT (27u) +#define INTC_ICDISR4_TGI3C_SHIFT (28u) +#define INTC_ICDISR4_TGI3D_SHIFT (29u) +#define INTC_ICDISR4_TGI3V_SHIFT (30u) +#define INTC_ICDISR4_TGI4A_SHIFT (31u) + +#define INTC_ICDISR5_TGI4B_SHIFT (0u) +#define INTC_ICDISR5_TGI4C_SHIFT (1u) +#define INTC_ICDISR5_TGI4D_SHIFT (2u) +#define INTC_ICDISR5_TGI4V_SHIFT (3u) +#define INTC_ICDISR5_CMI1_SHIFT (4u) +#define INTC_ICDISR5_CMI2_SHIFT (5u) +#define INTC_ICDISR5_SGDEI0_SHIFT (6u) +#define INTC_ICDISR5_SGDEI1_SHIFT (7u) +#define INTC_ICDISR5_SGDEI2_SHIFT (8u) +#define INTC_ICDISR5_SGDEI3_SHIFT (9u) +#define INTC_ICDISR5_ADI_SHIFT (10u) +#define INTC_ICDISR5_LMTI_SHIFT (11u) +#define INTC_ICDISR5_SSII0_SHIFT (12u) +#define INTC_ICDISR5_SSIRXI0_SHIFT (13u) +#define INTC_ICDISR5_SSITXI0_SHIFT (14u) +#define INTC_ICDISR5_SSII1_SHIFT (15u) +#define INTC_ICDISR5_SSIRXI1_SHIFT (16u) +#define INTC_ICDISR5_SSITXI1_SHIFT (17u) +#define INTC_ICDISR5_SSII2_SHIFT (18u) +#define INTC_ICDISR5_SSIRTI2_SHIFT (19u) +#define INTC_ICDISR5_SSII3_SHIFT (20u) +#define INTC_ICDISR5_SSIRXI3_SHIFT (21u) +#define INTC_ICDISR5_SSITXI3_SHIFT (22u) +#define INTC_ICDISR5_SSII4_SHIFT (23u) +#define INTC_ICDISR5_SSIRTI4_SHIFT (24u) +#define INTC_ICDISR5_SSII5_SHIFT (25u) +#define INTC_ICDISR5_SSIRXI5_SHIFT (26u) +#define INTC_ICDISR5_SSITXI5_SHIFT (27u) +#define INTC_ICDISR5_SPDIFI_SHIFT (28u) +#define INTC_ICDISR5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDISR5_INTIICRI0_SHIFT (30u) +#define INTC_ICDISR5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDISR6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDISR6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDISR6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDISR6_INTIICALI0_SHIFT (3u) +#define INTC_ICDISR6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDISR6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDISR6_INTIICRI1_SHIFT (6u) +#define INTC_ICDISR6_INTIICTI1_SHIFT (7u) +#define INTC_ICDISR6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDISR6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDISR6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDISR6_INTIICALI1_SHIFT (11u) +#define INTC_ICDISR6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDISR6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDISR6_INTIICRI2_SHIFT (14u) +#define INTC_ICDISR6_INTIICTI2_SHIFT (15u) +#define INTC_ICDISR6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDISR6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDISR6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDISR6_INTIICALI2_SHIFT (19u) +#define INTC_ICDISR6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDISR6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDISR6_INTIICRI3_SHIFT (22u) +#define INTC_ICDISR6_INTIICTI3_SHIFT (23u) +#define INTC_ICDISR6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDISR6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDISR6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDISR6_INTIICALI3_SHIFT (27u) +#define INTC_ICDISR6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDISR6_BRI0_SHIFT (29u) +#define INTC_ICDISR6_ERI0_SHIFT (30u) +#define INTC_ICDISR6_RXI0_SHIFT (31u) + +#define INTC_ICDISR7_TXI0_SHIFT (0u) +#define INTC_ICDISR7_BRI1_SHIFT (1u) +#define INTC_ICDISR7_ERI1_SHIFT (2u) +#define INTC_ICDISR7_RXI1_SHIFT (3u) +#define INTC_ICDISR7_TXI1_SHIFT (4u) +#define INTC_ICDISR7_BRI2_SHIFT (5u) +#define INTC_ICDISR7_ERI2_SHIFT (6u) +#define INTC_ICDISR7_RXI2_SHIFT (7u) +#define INTC_ICDISR7_TXI2_SHIFT (8u) +#define INTC_ICDISR7_BRI3_SHIFT (9u) +#define INTC_ICDISR7_ERI3_SHIFT (10u) +#define INTC_ICDISR7_RXI3_SHIFT (11u) +#define INTC_ICDISR7_TXI3_SHIFT (12u) +#define INTC_ICDISR7_BRI4_SHIFT (13u) +#define INTC_ICDISR7_ERI4_SHIFT (14u) +#define INTC_ICDISR7_RXI4_SHIFT (15u) +#define INTC_ICDISR7_TXI4_SHIFT (16u) +#define INTC_ICDISR7_BRI5_SHIFT (17u) +#define INTC_ICDISR7_ERI5_SHIFT (18u) +#define INTC_ICDISR7_RXI5_SHIFT (19u) +#define INTC_ICDISR7_TXI5_SHIFT (20u) +#define INTC_ICDISR7_BRI6_SHIFT (21u) +#define INTC_ICDISR7_ERI6_SHIFT (22u) +#define INTC_ICDISR7_RXI6_SHIFT (23u) +#define INTC_ICDISR7_TXI6_SHIFT (24u) +#define INTC_ICDISR7_BRI7_SHIFT (25u) +#define INTC_ICDISR7_ERI7_SHIFT (26u) +#define INTC_ICDISR7_RXI7_SHIFT (27u) +#define INTC_ICDISR7_TXI7_SHIFT (28u) +#define INTC_ICDISR7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDISR7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDISR7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDISR8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDISR8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDISR8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDISR8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDISR8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDISR8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDISR8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDISR8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDISR8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDISR8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDISR8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDISR8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDISR8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDISR8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDISR8_SPEI0_SHIFT (14u) +#define INTC_ICDISR8_SPRI0_SHIFT (15u) +#define INTC_ICDISR8_SPTI0_SHIFT (16u) +#define INTC_ICDISR8_SPEI1_SHIFT (17u) +#define INTC_ICDISR8_SPRI1_SHIFT (18u) +#define INTC_ICDISR8_SPTI1_SHIFT (19u) +#define INTC_ICDISR8_SPEI2_SHIFT (20u) +#define INTC_ICDISR8_SPRI2_SHIFT (21u) +#define INTC_ICDISR8_SPTI2_SHIFT (22u) +#define INTC_ICDISR8_SPEI3_SHIFT (23u) +#define INTC_ICDISR8_SPRI3_SHIFT (24u) +#define INTC_ICDISR8_SPTI3_SHIFT (25u) +#define INTC_ICDISR8_SPEI4_SHIFT (26u) +#define INTC_ICDISR8_SPRI4_SHIFT (27u) +#define INTC_ICDISR8_SPTI4_SHIFT (28u) +#define INTC_ICDISR8_IEBBTD_SHIFT (29u) +#define INTC_ICDISR8_IEBBTERR_SHIFT (30u) +#define INTC_ICDISR8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDISR9_IEBBTV_SHIFT (0u) +#define INTC_ICDISR9_ISY_SHIFT (1u) +#define INTC_ICDISR9_IERR_SHIFT (2u) +#define INTC_ICDISR9_ITARG_SHIFT (3u) +#define INTC_ICDISR9_ISEC_SHIFT (4u) +#define INTC_ICDISR9_IBUF_SHIFT (5u) +#define INTC_ICDISR9_IREADY_SHIFT (6u) +#define INTC_ICDISR9_FLSTE_SHIFT (7u) +#define INTC_ICDISR9_FLTENDI_SHIFT (8u) +#define INTC_ICDISR9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDISR9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDISR9_MMC0_SHIFT (11u) +#define INTC_ICDISR9_MMC1_SHIFT (12u) +#define INTC_ICDISR9_MMC2_SHIFT (13u) +#define INTC_ICDISR9_SDHI0_3_SHIFT (14u) +#define INTC_ICDISR9_SDHI0_0_SHIFT (15u) +#define INTC_ICDISR9_SDHI0_1_SHIFT (16u) +#define INTC_ICDISR9_SDHI1_3_SHIFT (17u) +#define INTC_ICDISR9_SDHI1_0_SHIFT (18u) +#define INTC_ICDISR9_SDHI1_1_SHIFT (19u) +#define INTC_ICDISR9_ARM_SHIFT (20u) +#define INTC_ICDISR9_PRD_SHIFT (21u) +#define INTC_ICDISR9_CUP_SHIFT (22u) +#define INTC_ICDISR9_SCUAI0_SHIFT (23u) +#define INTC_ICDISR9_SCUAI1_SHIFT (24u) +#define INTC_ICDISR9_SCUFDI0_SHIFT (25u) +#define INTC_ICDISR9_SCUFDI1_SHIFT (26u) +#define INTC_ICDISR9_SCUFDI2_SHIFT (27u) +#define INTC_ICDISR9_SCUFDI3_SHIFT (28u) +#define INTC_ICDISR9_SCUFUI0_SHIFT (29u) +#define INTC_ICDISR9_SCUFUI1_SHIFT (30u) +#define INTC_ICDISR9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDISR10_SCUFUI3_SHIFT (0u) +#define INTC_ICDISR10_SCUDVI0_SHIFT (1u) +#define INTC_ICDISR10_SCUDVI1_SHIFT (2u) +#define INTC_ICDISR10_SCUDVI2_SHIFT (3u) +#define INTC_ICDISR10_SCUDVI3_SHIFT (4u) +#define INTC_ICDISR10_MLB_CINT_SHIFT (5u) +#define INTC_ICDISR10_MLB_SINT_SHIFT (6u) +#define INTC_ICDISR10_DRC0_SHIFT (7u) +#define INTC_ICDISR10_DRC1_SHIFT (8u) +#define INTC_ICDISR10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDISR10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDISR10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDISR10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDISR10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDISR10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDISR10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDISR10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDISR10_ERI0_SHIFT (27u) +#define INTC_ICDISR10_RXI0_SHIFT (28u) +#define INTC_ICDISR10_TXI0_SHIFT (29u) +#define INTC_ICDISR10_TEI0_SHIFT (30u) +#define INTC_ICDISR10_ERI1_SHIFT (31u) + +#define INTC_ICDISR11_RXI1_SHIFT (0u) +#define INTC_ICDISR11_TXI1_SHIFT (1u) +#define INTC_ICDISR11_TEI1_SHIFT (2u) +#define INTC_ICDISR11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDISR11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDISR11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDISR11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDISR11_ETHERI_SHIFT (7u) +#define INTC_ICDISR11_CEUI_SHIFT (12u) +#define INTC_ICDISR11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDISR11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDISR11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDISR12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDISR12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDISR12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDISR12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDISR12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDISR12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDISR12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDISR12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDISR12_PRRI_SHIFT (8u) +#define INTC_ICDISR12_IFEI0_SHIFT (9u) +#define INTC_ICDISR12_OFFI0_SHIFT (10u) +#define INTC_ICDISR12_PFVEI0_SHIFT (11u) +#define INTC_ICDISR12_IFEI1_SHIFT (12u) +#define INTC_ICDISR12_OFFI1_SHIFT (13u) +#define INTC_ICDISR12_PFVEI1_SHIFT (14u) + +#define INTC_ICDISR13_TINT0_SHIFT (0u) +#define INTC_ICDISR13_TINT1_SHIFT (1u) +#define INTC_ICDISR13_TINT2_SHIFT (2u) +#define INTC_ICDISR13_TINT3_SHIFT (3u) +#define INTC_ICDISR13_TINT4_SHIFT (4u) +#define INTC_ICDISR13_TINT5_SHIFT (5u) +#define INTC_ICDISR13_TINT6_SHIFT (6u) +#define INTC_ICDISR13_TINT7_SHIFT (7u) +#define INTC_ICDISR13_TINT8_SHIFT (8u) +#define INTC_ICDISR13_TINT9_SHIFT (9u) +#define INTC_ICDISR13_TINT10_SHIFT (10u) +#define INTC_ICDISR13_TINT11_SHIFT (11u) +#define INTC_ICDISR13_TINT12_SHIFT (12u) +#define INTC_ICDISR13_TINT13_SHIFT (13u) +#define INTC_ICDISR13_TINT14_SHIFT (14u) +#define INTC_ICDISR13_TINT15_SHIFT (15u) +#define INTC_ICDISR13_TINT16_SHIFT (16u) +#define INTC_ICDISR13_TINT17_SHIFT (17u) +#define INTC_ICDISR13_TINT18_SHIFT (18u) +#define INTC_ICDISR13_TINT19_SHIFT (19u) +#define INTC_ICDISR13_TINT20_SHIFT (20u) +#define INTC_ICDISR13_TINT21_SHIFT (21u) +#define INTC_ICDISR13_TINT22_SHIFT (22u) +#define INTC_ICDISR13_TINT23_SHIFT (23u) +#define INTC_ICDISR13_TINT24_SHIFT (24u) +#define INTC_ICDISR13_TINT25_SHIFT (25u) +#define INTC_ICDISR13_TINT26_SHIFT (26u) +#define INTC_ICDISR13_TINT27_SHIFT (27u) +#define INTC_ICDISR13_TINT28_SHIFT (28u) +#define INTC_ICDISR13_TINT29_SHIFT (29u) +#define INTC_ICDISR13_TINT30_SHIFT (30u) +#define INTC_ICDISR13_TINT31_SHIFT (31u) + +#define INTC_ICDISR14_TINT32_SHIFT (0u) +#define INTC_ICDISR14_TINT33_SHIFT (1u) +#define INTC_ICDISR14_TINT34_SHIFT (2u) +#define INTC_ICDISR14_TINT35_SHIFT (3u) +#define INTC_ICDISR14_TINT36_SHIFT (4u) +#define INTC_ICDISR14_TINT37_SHIFT (5u) +#define INTC_ICDISR14_TINT38_SHIFT (6u) +#define INTC_ICDISR14_TINT39_SHIFT (7u) +#define INTC_ICDISR14_TINT40_SHIFT (8u) +#define INTC_ICDISR14_TINT41_SHIFT (9u) +#define INTC_ICDISR14_TINT42_SHIFT (10u) +#define INTC_ICDISR14_TINT43_SHIFT (11u) +#define INTC_ICDISR14_TINT44_SHIFT (12u) +#define INTC_ICDISR14_TINT45_SHIFT (13u) +#define INTC_ICDISR14_TINT46_SHIFT (14u) +#define INTC_ICDISR14_TINT47_SHIFT (15u) +#define INTC_ICDISR14_TINT48_SHIFT (16u) +#define INTC_ICDISR14_TINT49_SHIFT (17u) +#define INTC_ICDISR14_TINT50_SHIFT (18u) +#define INTC_ICDISR14_TINT51_SHIFT (19u) +#define INTC_ICDISR14_TINT52_SHIFT (20u) +#define INTC_ICDISR14_TINT53_SHIFT (21u) +#define INTC_ICDISR14_TINT54_SHIFT (22u) +#define INTC_ICDISR14_TINT55_SHIFT (23u) +#define INTC_ICDISR14_TINT56_SHIFT (24u) +#define INTC_ICDISR14_TINT57_SHIFT (25u) +#define INTC_ICDISR14_TINT58_SHIFT (26u) +#define INTC_ICDISR14_TINT59_SHIFT (27u) +#define INTC_ICDISR14_TINT60_SHIFT (28u) +#define INTC_ICDISR14_TINT61_SHIFT (29u) +#define INTC_ICDISR14_TINT62_SHIFT (30u) +#define INTC_ICDISR14_TINT63_SHIFT (31u) + +#define INTC_ICDISR15_TINT64_SHIFT (0u) +#define INTC_ICDISR15_TINT65_SHIFT (1u) +#define INTC_ICDISR15_TINT66_SHIFT (2u) +#define INTC_ICDISR15_TINT67_SHIFT (3u) +#define INTC_ICDISR15_TINT68_SHIFT (4u) +#define INTC_ICDISR15_TINT69_SHIFT (5u) +#define INTC_ICDISR15_TINT70_SHIFT (6u) +#define INTC_ICDISR15_TINT71_SHIFT (7u) +#define INTC_ICDISR15_TINT72_SHIFT (8u) +#define INTC_ICDISR15_TINT73_SHIFT (9u) +#define INTC_ICDISR15_TINT74_SHIFT (10u) +#define INTC_ICDISR15_TINT75_SHIFT (11u) +#define INTC_ICDISR15_TINT76_SHIFT (12u) +#define INTC_ICDISR15_TINT77_SHIFT (13u) +#define INTC_ICDISR15_TINT78_SHIFT (14u) +#define INTC_ICDISR15_TINT79_SHIFT (15u) +#define INTC_ICDISR15_TINT80_SHIFT (16u) +#define INTC_ICDISR15_TINT81_SHIFT (17u) +#define INTC_ICDISR15_TINT82_SHIFT (18u) +#define INTC_ICDISR15_TINT83_SHIFT (19u) +#define INTC_ICDISR15_TINT84_SHIFT (20u) +#define INTC_ICDISR15_TINT85_SHIFT (21u) +#define INTC_ICDISR15_TINT86_SHIFT (22u) +#define INTC_ICDISR15_TINT87_SHIFT (23u) +#define INTC_ICDISR15_TINT88_SHIFT (24u) +#define INTC_ICDISR15_TINT89_SHIFT (25u) +#define INTC_ICDISR15_TINT90_SHIFT (26u) +#define INTC_ICDISR15_TINT91_SHIFT (27u) +#define INTC_ICDISR15_TINT92_SHIFT (28u) +#define INTC_ICDISR15_TINT93_SHIFT (29u) +#define INTC_ICDISR15_TINT94_SHIFT (30u) +#define INTC_ICDISR15_TINT95_SHIFT (31u) + +#define INTC_ICDISR16_TINT96_SHIFT (0u) +#define INTC_ICDISR16_TINT97_SHIFT (1u) +#define INTC_ICDISR16_TINT98_SHIFT (2u) +#define INTC_ICDISR16_TINT99_SHIFT (3u) +#define INTC_ICDISR16_TINT100_SHIFT (4u) +#define INTC_ICDISR16_TINT101_SHIFT (5u) +#define INTC_ICDISR16_TINT102_SHIFT (6u) +#define INTC_ICDISR16_TINT103_SHIFT (7u) +#define INTC_ICDISR16_TINT104_SHIFT (8u) +#define INTC_ICDISR16_TINT105_SHIFT (9u) +#define INTC_ICDISR16_TINT106_SHIFT (10u) +#define INTC_ICDISR16_TINT107_SHIFT (11u) +#define INTC_ICDISR16_TINT108_SHIFT (12u) +#define INTC_ICDISR16_TINT109_SHIFT (13u) +#define INTC_ICDISR16_TINT110_SHIFT (14u) +#define INTC_ICDISR16_TINT111_SHIFT (15u) +#define INTC_ICDISR16_TINT112_SHIFT (16u) +#define INTC_ICDISR16_TINT113_SHIFT (17u) +#define INTC_ICDISR16_TINT114_SHIFT (18u) +#define INTC_ICDISR16_TINT115_SHIFT (19u) +#define INTC_ICDISR16_TINT116_SHIFT (20u) +#define INTC_ICDISR16_TINT117_SHIFT (21u) +#define INTC_ICDISR16_TINT118_SHIFT (22u) +#define INTC_ICDISR16_TINT119_SHIFT (23u) +#define INTC_ICDISR16_TINT120_SHIFT (24u) +#define INTC_ICDISR16_TINT121_SHIFT (25u) +#define INTC_ICDISR16_TINT122_SHIFT (26u) +#define INTC_ICDISR16_TINT123_SHIFT (27u) +#define INTC_ICDISR16_TINT124_SHIFT (28u) +#define INTC_ICDISR16_TINT125_SHIFT (29u) +#define INTC_ICDISR16_TINT126_SHIFT (30u) +#define INTC_ICDISR16_TINT127_SHIFT (31u) + +#define INTC_ICDISR17_TINT128_SHIFT (0u) +#define INTC_ICDISR17_TINT129_SHIFT (1u) +#define INTC_ICDISR17_TINT130_SHIFT (2u) +#define INTC_ICDISR17_TINT131_SHIFT (3u) +#define INTC_ICDISR17_TINT132_SHIFT (4u) +#define INTC_ICDISR17_TINT133_SHIFT (5u) +#define INTC_ICDISR17_TINT134_SHIFT (6u) +#define INTC_ICDISR17_TINT135_SHIFT (7u) +#define INTC_ICDISR17_TINT136_SHIFT (8u) +#define INTC_ICDISR17_TINT137_SHIFT (9u) +#define INTC_ICDISR17_TINT138_SHIFT (10u) +#define INTC_ICDISR17_TINT139_SHIFT (11u) +#define INTC_ICDISR17_TINT140_SHIFT (12u) +#define INTC_ICDISR17_TINT141_SHIFT (13u) +#define INTC_ICDISR17_TINT142_SHIFT (14u) +#define INTC_ICDISR17_TINT143_SHIFT (15u) +#define INTC_ICDISR17_TINT144_SHIFT (16u) +#define INTC_ICDISR17_TINT145_SHIFT (17u) +#define INTC_ICDISR17_TINT146_SHIFT (18u) +#define INTC_ICDISR17_TINT147_SHIFT (19u) +#define INTC_ICDISR17_TINT148_SHIFT (20u) +#define INTC_ICDISR17_TINT149_SHIFT (21u) +#define INTC_ICDISR17_TINT150_SHIFT (22u) +#define INTC_ICDISR17_TINT151_SHIFT (23u) +#define INTC_ICDISR17_TINT152_SHIFT (24u) +#define INTC_ICDISR17_TINT153_SHIFT (25u) +#define INTC_ICDISR17_TINT154_SHIFT (26u) +#define INTC_ICDISR17_TINT155_SHIFT (27u) +#define INTC_ICDISR17_TINT156_SHIFT (28u) +#define INTC_ICDISR17_TINT157_SHIFT (29u) +#define INTC_ICDISR17_TINT158_SHIFT (30u) +#define INTC_ICDISR17_TINT159_SHIFT (31u) + +#define INTC_ICDISR18_TINT160_SHIFT (0u) +#define INTC_ICDISR18_TINT161_SHIFT (1u) +#define INTC_ICDISR18_TINT162_SHIFT (2u) +#define INTC_ICDISR18_TINT163_SHIFT (3u) +#define INTC_ICDISR18_TINT164_SHIFT (4u) +#define INTC_ICDISR18_TINT165_SHIFT (5u) +#define INTC_ICDISR18_TINT166_SHIFT (6u) +#define INTC_ICDISR18_TINT167_SHIFT (7u) +#define INTC_ICDISR18_TINT168_SHIFT (8u) +#define INTC_ICDISR18_TINT169_SHIFT (9u) +#define INTC_ICDISR18_TINT170_SHIFT (10u) + +#define INTC_ICDISER0_SW0_SHIFT (0u) +#define INTC_ICDISER0_SW1_SHIFT (1u) +#define INTC_ICDISER0_SW2_SHIFT (2u) +#define INTC_ICDISER0_SW3_SHIFT (3u) +#define INTC_ICDISER0_SW4_SHIFT (4u) +#define INTC_ICDISER0_SW5_SHIFT (5u) +#define INTC_ICDISER0_SW6_SHIFT (6u) +#define INTC_ICDISER0_SW7_SHIFT (7u) +#define INTC_ICDISER0_SW8_SHIFT (8u) +#define INTC_ICDISER0_SW9_SHIFT (9u) +#define INTC_ICDISER0_SW10_SHIFT (10u) +#define INTC_ICDISER0_SW11_SHIFT (11u) +#define INTC_ICDISER0_SW12_SHIFT (12u) +#define INTC_ICDISER0_SW13_SHIFT (13u) +#define INTC_ICDISER0_SW14_SHIFT (14u) +#define INTC_ICDISER0_SW15_SHIFT (15u) +#define INTC_ICDISER0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDISER0_COMMRX0_SHIFT (17u) +#define INTC_ICDISER0_COMMTX0_SHIFT (18u) +#define INTC_ICDISER0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDISER1_IRQ0_SHIFT (0u) +#define INTC_ICDISER1_IRQ1_SHIFT (1u) +#define INTC_ICDISER1_IRQ2_SHIFT (2u) +#define INTC_ICDISER1_IRQ3_SHIFT (3u) +#define INTC_ICDISER1_IRQ4_SHIFT (4u) +#define INTC_ICDISER1_IRQ5_SHIFT (5u) +#define INTC_ICDISER1_IRQ6_SHIFT (6u) +#define INTC_ICDISER1_IRQ7_SHIFT (7u) +#define INTC_ICDISER1_PL310ERR_SHIFT (8u) +#define INTC_ICDISER1_DMAINT0_SHIFT (9u) +#define INTC_ICDISER1_DMAINT1_SHIFT (10u) +#define INTC_ICDISER1_DMAINT2_SHIFT (11u) +#define INTC_ICDISER1_DMAINT3_SHIFT (12u) +#define INTC_ICDISER1_DMAINT4_SHIFT (13u) +#define INTC_ICDISER1_DMAINT5_SHIFT (14u) +#define INTC_ICDISER1_DMAINT6_SHIFT (15u) +#define INTC_ICDISER1_DMAINT7_SHIFT (16u) +#define INTC_ICDISER1_DMAINT8_SHIFT (17u) +#define INTC_ICDISER1_DMAINT9_SHIFT (18u) +#define INTC_ICDISER1_DMAINT10_SHIFT (19u) +#define INTC_ICDISER1_DMAINT11_SHIFT (20u) +#define INTC_ICDISER1_DMAINT12_SHIFT (21u) +#define INTC_ICDISER1_DMAINT13_SHIFT (22u) +#define INTC_ICDISER1_DMAINT14_SHIFT (23u) +#define INTC_ICDISER1_DMAINT15_SHIFT (24u) +#define INTC_ICDISER1_DMAERR_SHIFT (25u) + +#define INTC_ICDISER2_USBI0_SHIFT (9u) +#define INTC_ICDISER2_USBI1_SHIFT (10u) +#define INTC_ICDISER2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDISER2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDISER2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDISER2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDISER2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDISER2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDISER2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDISER2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDISER2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDISER2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDISER2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDISER2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDISER2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDISER2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDISER2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDISER2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDISER2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDISER2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDISER2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDISER2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDISER2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDISER3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDISER3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDISER3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDISER3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDISER3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDISER3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDISER3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDISER3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDISER3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDISER3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDISER3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDISER3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDISER3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDISER3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDISER3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDISER3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDISER3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDISER3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDISER3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDISER3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDISER3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDISER3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDISER3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDISER3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDISER3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDISER3_IMRDI_SHIFT (27u) +#define INTC_ICDISER3_IMR2I0_SHIFT (28u) +#define INTC_ICDISER3_IMR2I1_SHIFT (29u) +#define INTC_ICDISER3_JEDI_SHIFT (30u) +#define INTC_ICDISER3_JDTI_SHIFT (31u) + +#define INTC_ICDISER4_CMP0_SHIFT (0u) +#define INTC_ICDISER4_CMP1_SHIFT (1u) +#define INTC_ICDISER4_INT0_SHIFT (2u) +#define INTC_ICDISER4_INT1_SHIFT (3u) +#define INTC_ICDISER4_INT2_SHIFT (4u) +#define INTC_ICDISER4_INT3_SHIFT (5u) +#define INTC_ICDISER4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDISER4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDISER4_CMI_SHIFT (8u) +#define INTC_ICDISER4_WTOUT_SHIFT (9u) +#define INTC_ICDISER4_ITI_SHIFT (10u) +#define INTC_ICDISER4_TGI0A_SHIFT (11u) +#define INTC_ICDISER4_TGI0B_SHIFT (12u) +#define INTC_ICDISER4_TGI0C_SHIFT (13u) +#define INTC_ICDISER4_TGI0D_SHIFT (14u) +#define INTC_ICDISER4_TGI0V_SHIFT (15u) +#define INTC_ICDISER4_TGI0E_SHIFT (16u) +#define INTC_ICDISER4_TGI0F_SHIFT (17u) +#define INTC_ICDISER4_TGI1A_SHIFT (18u) +#define INTC_ICDISER4_TGI1B_SHIFT (19u) +#define INTC_ICDISER4_TGI1V_SHIFT (20u) +#define INTC_ICDISER4_TGI1U_SHIFT (21u) +#define INTC_ICDISER4_TGI2A_SHIFT (22u) +#define INTC_ICDISER4_TGI2B_SHIFT (23u) +#define INTC_ICDISER4_TGI2V_SHIFT (24u) +#define INTC_ICDISER4_TGI2U_SHIFT (25u) +#define INTC_ICDISER4_TGI3A_SHIFT (26u) +#define INTC_ICDISER4_TGI3B_SHIFT (27u) +#define INTC_ICDISER4_TGI3C_SHIFT (28u) +#define INTC_ICDISER4_TGI3D_SHIFT (29u) +#define INTC_ICDISER4_TGI3V_SHIFT (30u) +#define INTC_ICDISER4_TGI4A_SHIFT (31u) + +#define INTC_ICDISER5_TGI4B_SHIFT (0u) +#define INTC_ICDISER5_TGI4C_SHIFT (1u) +#define INTC_ICDISER5_TGI4D_SHIFT (2u) +#define INTC_ICDISER5_TGI4V_SHIFT (3u) +#define INTC_ICDISER5_CMI1_SHIFT (4u) +#define INTC_ICDISER5_CMI2_SHIFT (5u) +#define INTC_ICDISER5_SGDEI0_SHIFT (6u) +#define INTC_ICDISER5_SGDEI1_SHIFT (7u) +#define INTC_ICDISER5_SGDEI2_SHIFT (8u) +#define INTC_ICDISER5_SGDEI3_SHIFT (9u) +#define INTC_ICDISER5_ADI_SHIFT (10u) +#define INTC_ICDISER5_LMTI_SHIFT (11u) +#define INTC_ICDISER5_SSII0_SHIFT (12u) +#define INTC_ICDISER5_SSIRXI0_SHIFT (13u) +#define INTC_ICDISER5_SSITXI0_SHIFT (14u) +#define INTC_ICDISER5_SSII1_SHIFT (15u) +#define INTC_ICDISER5_SSIRXI1_SHIFT (16u) +#define INTC_ICDISER5_SSITXI1_SHIFT (17u) +#define INTC_ICDISER5_SSII2_SHIFT (18u) +#define INTC_ICDISER5_SSIRTI2_SHIFT (19u) +#define INTC_ICDISER5_SSII3_SHIFT (20u) +#define INTC_ICDISER5_SSIRXI3_SHIFT (21u) +#define INTC_ICDISER5_SSITXI3_SHIFT (22u) +#define INTC_ICDISER5_SSII4_SHIFT (23u) +#define INTC_ICDISER5_SSIRTI4_SHIFT (24u) +#define INTC_ICDISER5_SSII5_SHIFT (25u) +#define INTC_ICDISER5_SSIRXI5_SHIFT (26u) +#define INTC_ICDISER5_SSITXI5_SHIFT (27u) +#define INTC_ICDISER5_SPDIFI_SHIFT (28u) +#define INTC_ICDISER5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDISER5_INTIICRI0_SHIFT (30u) +#define INTC_ICDISER5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDISER6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDISER6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDISER6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDISER6_INTIICALI0_SHIFT (3u) +#define INTC_ICDISER6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDISER6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDISER6_INTIICRI1_SHIFT (6u) +#define INTC_ICDISER6_INTIICTI1_SHIFT (7u) +#define INTC_ICDISER6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDISER6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDISER6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDISER6_INTIICALI1_SHIFT (11u) +#define INTC_ICDISER6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDISER6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDISER6_INTIICRI2_SHIFT (14u) +#define INTC_ICDISER6_INTIICTI2_SHIFT (15u) +#define INTC_ICDISER6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDISER6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDISER6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDISER6_INTIICALI2_SHIFT (19u) +#define INTC_ICDISER6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDISER6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDISER6_INTIICRI3_SHIFT (22u) +#define INTC_ICDISER6_INTIICTI3_SHIFT (23u) +#define INTC_ICDISER6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDISER6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDISER6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDISER6_INTIICALI3_SHIFT (27u) +#define INTC_ICDISER6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDISER6_BRI0_SHIFT (29u) +#define INTC_ICDISER6_ERI0_SHIFT (30u) +#define INTC_ICDISER6_RXI0_SHIFT (31u) + +#define INTC_ICDISER7_TXI0_SHIFT (0u) +#define INTC_ICDISER7_BRI1_SHIFT (1u) +#define INTC_ICDISER7_ERI1_SHIFT (2u) +#define INTC_ICDISER7_RXI1_SHIFT (3u) +#define INTC_ICDISER7_TXI1_SHIFT (4u) +#define INTC_ICDISER7_BRI2_SHIFT (5u) +#define INTC_ICDISER7_ERI2_SHIFT (6u) +#define INTC_ICDISER7_RXI2_SHIFT (7u) +#define INTC_ICDISER7_TXI2_SHIFT (8u) +#define INTC_ICDISER7_BRI3_SHIFT (9u) +#define INTC_ICDISER7_ERI3_SHIFT (10u) +#define INTC_ICDISER7_RXI3_SHIFT (11u) +#define INTC_ICDISER7_TXI3_SHIFT (12u) +#define INTC_ICDISER7_BRI4_SHIFT (13u) +#define INTC_ICDISER7_ERI4_SHIFT (14u) +#define INTC_ICDISER7_RXI4_SHIFT (15u) +#define INTC_ICDISER7_TXI4_SHIFT (16u) +#define INTC_ICDISER7_BRI5_SHIFT (17u) +#define INTC_ICDISER7_ERI5_SHIFT (18u) +#define INTC_ICDISER7_RXI5_SHIFT (19u) +#define INTC_ICDISER7_TXI5_SHIFT (20u) +#define INTC_ICDISER7_BRI6_SHIFT (21u) +#define INTC_ICDISER7_ERI6_SHIFT (22u) +#define INTC_ICDISER7_RXI6_SHIFT (23u) +#define INTC_ICDISER7_TXI6_SHIFT (24u) +#define INTC_ICDISER7_BRI7_SHIFT (25u) +#define INTC_ICDISER7_ERI7_SHIFT (26u) +#define INTC_ICDISER7_RXI7_SHIFT (27u) +#define INTC_ICDISER7_TXI7_SHIFT (28u) +#define INTC_ICDISER7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDISER7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDISER7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDISER8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDISER8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDISER8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDISER8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDISER8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDISER8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDISER8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDISER8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDISER8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDISER8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDISER8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDISER8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDISER8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDISER8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDISER8_SPEI0_SHIFT (14u) +#define INTC_ICDISER8_SPRI0_SHIFT (15u) +#define INTC_ICDISER8_SPTI0_SHIFT (16u) +#define INTC_ICDISER8_SPEI1_SHIFT (17u) +#define INTC_ICDISER8_SPRI1_SHIFT (18u) +#define INTC_ICDISER8_SPTI1_SHIFT (19u) +#define INTC_ICDISER8_SPEI2_SHIFT (20u) +#define INTC_ICDISER8_SPRI2_SHIFT (21u) +#define INTC_ICDISER8_SPTI2_SHIFT (22u) +#define INTC_ICDISER8_SPEI3_SHIFT (23u) +#define INTC_ICDISER8_SPRI3_SHIFT (24u) +#define INTC_ICDISER8_SPTI3_SHIFT (25u) +#define INTC_ICDISER8_SPEI4_SHIFT (26u) +#define INTC_ICDISER8_SPRI4_SHIFT (27u) +#define INTC_ICDISER8_SPTI4_SHIFT (28u) +#define INTC_ICDISER8_IEBBTD_SHIFT (29u) +#define INTC_ICDISER8_IEBBTERR_SHIFT (30u) +#define INTC_ICDISER8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDISER9_IEBBTV_SHIFT (0u) +#define INTC_ICDISER9_ISY_SHIFT (1u) +#define INTC_ICDISER9_IERR_SHIFT (2u) +#define INTC_ICDISER9_ITARG_SHIFT (3u) +#define INTC_ICDISER9_ISEC_SHIFT (4u) +#define INTC_ICDISER9_IBUF_SHIFT (5u) +#define INTC_ICDISER9_IREADY_SHIFT (6u) +#define INTC_ICDISER9_FLSTE_SHIFT (7u) +#define INTC_ICDISER9_FLTENDI_SHIFT (8u) +#define INTC_ICDISER9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDISER9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDISER9_MMC0_SHIFT (11u) +#define INTC_ICDISER9_MMC1_SHIFT (12u) +#define INTC_ICDISER9_MMC2_SHIFT (13u) +#define INTC_ICDISER9_SDHI0_3_SHIFT (14u) +#define INTC_ICDISER9_SDHI0_0_SHIFT (15u) +#define INTC_ICDISER9_SDHI0_1_SHIFT (16u) +#define INTC_ICDISER9_SDHI1_3_SHIFT (17u) +#define INTC_ICDISER9_SDHI1_0_SHIFT (18u) +#define INTC_ICDISER9_SDHI1_1_SHIFT (19u) +#define INTC_ICDISER9_ARM_SHIFT (20u) +#define INTC_ICDISER9_PRD_SHIFT (21u) +#define INTC_ICDISER9_CUP_SHIFT (22u) +#define INTC_ICDISER9_SCUAI0_SHIFT (23u) +#define INTC_ICDISER9_SCUAI1_SHIFT (24u) +#define INTC_ICDISER9_SCUFDI0_SHIFT (25u) +#define INTC_ICDISER9_SCUFDI1_SHIFT (26u) +#define INTC_ICDISER9_SCUFDI2_SHIFT (27u) +#define INTC_ICDISER9_SCUFDI3_SHIFT (28u) +#define INTC_ICDISER9_SCUFUI0_SHIFT (29u) +#define INTC_ICDISER9_SCUFUI1_SHIFT (30u) +#define INTC_ICDISER9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDISER10_SCUFUI3_SHIFT (0u) +#define INTC_ICDISER10_SCUDVI0_SHIFT (1u) +#define INTC_ICDISER10_SCUDVI1_SHIFT (2u) +#define INTC_ICDISER10_SCUDVI2_SHIFT (3u) +#define INTC_ICDISER10_SCUDVI3_SHIFT (4u) +#define INTC_ICDISER10_MLB_CINT_SHIFT (5u) +#define INTC_ICDISER10_MLB_SINT_SHIFT (6u) +#define INTC_ICDISER10_DRC0_SHIFT (7u) +#define INTC_ICDISER10_DRC1_SHIFT (8u) +#define INTC_ICDISER10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDISER10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDISER10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDISER10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDISER10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDISER10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDISER10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDISER10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDISER10_ERI0_SHIFT (27u) +#define INTC_ICDISER10_RXI0_SHIFT (28u) +#define INTC_ICDISER10_TXI0_SHIFT (29u) +#define INTC_ICDISER10_TEI0_SHIFT (30u) +#define INTC_ICDISER10_ERI1_SHIFT (31u) + +#define INTC_ICDISER11_RXI1_SHIFT (0u) +#define INTC_ICDISER11_TXI1_SHIFT (1u) +#define INTC_ICDISER11_TEI1_SHIFT (2u) +#define INTC_ICDISER11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDISER11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDISER11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDISER11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDISER11_ETHERI_SHIFT (7u) +#define INTC_ICDISER11_CEUI_SHIFT (12u) +#define INTC_ICDISER11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDISER11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDISER11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDISER12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDISER12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDISER12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDISER12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDISER12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDISER12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDISER12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDISER12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDISER12_PRRI_SHIFT (8u) +#define INTC_ICDISER12_IFEI0_SHIFT (9u) +#define INTC_ICDISER12_OFFI0_SHIFT (10u) +#define INTC_ICDISER12_PFVEI0_SHIFT (11u) +#define INTC_ICDISER12_IFEI1_SHIFT (12u) +#define INTC_ICDISER12_OFFI1_SHIFT (13u) +#define INTC_ICDISER12_PFVEI1_SHIFT (14u) + +#define INTC_ICDISER13_TINT0_SHIFT (0u) +#define INTC_ICDISER13_TINT1_SHIFT (1u) +#define INTC_ICDISER13_TINT2_SHIFT (2u) +#define INTC_ICDISER13_TINT3_SHIFT (3u) +#define INTC_ICDISER13_TINT4_SHIFT (4u) +#define INTC_ICDISER13_TINT5_SHIFT (5u) +#define INTC_ICDISER13_TINT6_SHIFT (6u) +#define INTC_ICDISER13_TINT7_SHIFT (7u) +#define INTC_ICDISER13_TINT8_SHIFT (8u) +#define INTC_ICDISER13_TINT9_SHIFT (9u) +#define INTC_ICDISER13_TINT10_SHIFT (10u) +#define INTC_ICDISER13_TINT11_SHIFT (11u) +#define INTC_ICDISER13_TINT12_SHIFT (12u) +#define INTC_ICDISER13_TINT13_SHIFT (13u) +#define INTC_ICDISER13_TINT14_SHIFT (14u) +#define INTC_ICDISER13_TINT15_SHIFT (15u) +#define INTC_ICDISER13_TINT16_SHIFT (16u) +#define INTC_ICDISER13_TINT17_SHIFT (17u) +#define INTC_ICDISER13_TINT18_SHIFT (18u) +#define INTC_ICDISER13_TINT19_SHIFT (19u) +#define INTC_ICDISER13_TINT20_SHIFT (20u) +#define INTC_ICDISER13_TINT21_SHIFT (21u) +#define INTC_ICDISER13_TINT22_SHIFT (22u) +#define INTC_ICDISER13_TINT23_SHIFT (23u) +#define INTC_ICDISER13_TINT24_SHIFT (24u) +#define INTC_ICDISER13_TINT25_SHIFT (25u) +#define INTC_ICDISER13_TINT26_SHIFT (26u) +#define INTC_ICDISER13_TINT27_SHIFT (27u) +#define INTC_ICDISER13_TINT28_SHIFT (28u) +#define INTC_ICDISER13_TINT29_SHIFT (29u) +#define INTC_ICDISER13_TINT30_SHIFT (30u) +#define INTC_ICDISER13_TINT31_SHIFT (31u) + +#define INTC_ICDISER14_TINT32_SHIFT (0u) +#define INTC_ICDISER14_TINT33_SHIFT (1u) +#define INTC_ICDISER14_TINT34_SHIFT (2u) +#define INTC_ICDISER14_TINT35_SHIFT (3u) +#define INTC_ICDISER14_TINT36_SHIFT (4u) +#define INTC_ICDISER14_TINT37_SHIFT (5u) +#define INTC_ICDISER14_TINT38_SHIFT (6u) +#define INTC_ICDISER14_TINT39_SHIFT (7u) +#define INTC_ICDISER14_TINT40_SHIFT (8u) +#define INTC_ICDISER14_TINT41_SHIFT (9u) +#define INTC_ICDISER14_TINT42_SHIFT (10u) +#define INTC_ICDISER14_TINT43_SHIFT (11u) +#define INTC_ICDISER14_TINT44_SHIFT (12u) +#define INTC_ICDISER14_TINT45_SHIFT (13u) +#define INTC_ICDISER14_TINT46_SHIFT (14u) +#define INTC_ICDISER14_TINT47_SHIFT (15u) +#define INTC_ICDISER14_TINT48_SHIFT (16u) +#define INTC_ICDISER14_TINT49_SHIFT (17u) +#define INTC_ICDISER14_TINT50_SHIFT (18u) +#define INTC_ICDISER14_TINT51_SHIFT (19u) +#define INTC_ICDISER14_TINT52_SHIFT (20u) +#define INTC_ICDISER14_TINT53_SHIFT (21u) +#define INTC_ICDISER14_TINT54_SHIFT (22u) +#define INTC_ICDISER14_TINT55_SHIFT (23u) +#define INTC_ICDISER14_TINT56_SHIFT (24u) +#define INTC_ICDISER14_TINT57_SHIFT (25u) +#define INTC_ICDISER14_TINT58_SHIFT (26u) +#define INTC_ICDISER14_TINT59_SHIFT (27u) +#define INTC_ICDISER14_TINT60_SHIFT (28u) +#define INTC_ICDISER14_TINT61_SHIFT (29u) +#define INTC_ICDISER14_TINT62_SHIFT (30u) +#define INTC_ICDISER14_TINT63_SHIFT (31u) + +#define INTC_ICDISER15_TINT64_SHIFT (0u) +#define INTC_ICDISER15_TINT65_SHIFT (1u) +#define INTC_ICDISER15_TINT66_SHIFT (2u) +#define INTC_ICDISER15_TINT67_SHIFT (3u) +#define INTC_ICDISER15_TINT68_SHIFT (4u) +#define INTC_ICDISER15_TINT69_SHIFT (5u) +#define INTC_ICDISER15_TINT70_SHIFT (6u) +#define INTC_ICDISER15_TINT71_SHIFT (7u) +#define INTC_ICDISER15_TINT72_SHIFT (8u) +#define INTC_ICDISER15_TINT73_SHIFT (9u) +#define INTC_ICDISER15_TINT74_SHIFT (10u) +#define INTC_ICDISER15_TINT75_SHIFT (11u) +#define INTC_ICDISER15_TINT76_SHIFT (12u) +#define INTC_ICDISER15_TINT77_SHIFT (13u) +#define INTC_ICDISER15_TINT78_SHIFT (14u) +#define INTC_ICDISER15_TINT79_SHIFT (15u) +#define INTC_ICDISER15_TINT80_SHIFT (16u) +#define INTC_ICDISER15_TINT81_SHIFT (17u) +#define INTC_ICDISER15_TINT82_SHIFT (18u) +#define INTC_ICDISER15_TINT83_SHIFT (19u) +#define INTC_ICDISER15_TINT84_SHIFT (20u) +#define INTC_ICDISER15_TINT85_SHIFT (21u) +#define INTC_ICDISER15_TINT86_SHIFT (22u) +#define INTC_ICDISER15_TINT87_SHIFT (23u) +#define INTC_ICDISER15_TINT88_SHIFT (24u) +#define INTC_ICDISER15_TINT89_SHIFT (25u) +#define INTC_ICDISER15_TINT90_SHIFT (26u) +#define INTC_ICDISER15_TINT91_SHIFT (27u) +#define INTC_ICDISER15_TINT92_SHIFT (28u) +#define INTC_ICDISER15_TINT93_SHIFT (29u) +#define INTC_ICDISER15_TINT94_SHIFT (30u) +#define INTC_ICDISER15_TINT95_SHIFT (31u) + +#define INTC_ICDISER16_TINT96_SHIFT (0u) +#define INTC_ICDISER16_TINT97_SHIFT (1u) +#define INTC_ICDISER16_TINT98_SHIFT (2u) +#define INTC_ICDISER16_TINT99_SHIFT (3u) +#define INTC_ICDISER16_TINT100_SHIFT (4u) +#define INTC_ICDISER16_TINT101_SHIFT (5u) +#define INTC_ICDISER16_TINT102_SHIFT (6u) +#define INTC_ICDISER16_TINT103_SHIFT (7u) +#define INTC_ICDISER16_TINT104_SHIFT (8u) +#define INTC_ICDISER16_TINT105_SHIFT (9u) +#define INTC_ICDISER16_TINT106_SHIFT (10u) +#define INTC_ICDISER16_TINT107_SHIFT (11u) +#define INTC_ICDISER16_TINT108_SHIFT (12u) +#define INTC_ICDISER16_TINT109_SHIFT (13u) +#define INTC_ICDISER16_TINT110_SHIFT (14u) +#define INTC_ICDISER16_TINT111_SHIFT (15u) +#define INTC_ICDISER16_TINT112_SHIFT (16u) +#define INTC_ICDISER16_TINT113_SHIFT (17u) +#define INTC_ICDISER16_TINT114_SHIFT (18u) +#define INTC_ICDISER16_TINT115_SHIFT (19u) +#define INTC_ICDISER16_TINT116_SHIFT (20u) +#define INTC_ICDISER16_TINT117_SHIFT (21u) +#define INTC_ICDISER16_TINT118_SHIFT (22u) +#define INTC_ICDISER16_TINT119_SHIFT (23u) +#define INTC_ICDISER16_TINT120_SHIFT (24u) +#define INTC_ICDISER16_TINT121_SHIFT (25u) +#define INTC_ICDISER16_TINT122_SHIFT (26u) +#define INTC_ICDISER16_TINT123_SHIFT (27u) +#define INTC_ICDISER16_TINT124_SHIFT (28u) +#define INTC_ICDISER16_TINT125_SHIFT (29u) +#define INTC_ICDISER16_TINT126_SHIFT (30u) +#define INTC_ICDISER16_TINT127_SHIFT (31u) + +#define INTC_ICDISER17_TINT128_SHIFT (0u) +#define INTC_ICDISER17_TINT129_SHIFT (1u) +#define INTC_ICDISER17_TINT130_SHIFT (2u) +#define INTC_ICDISER17_TINT131_SHIFT (3u) +#define INTC_ICDISER17_TINT132_SHIFT (4u) +#define INTC_ICDISER17_TINT133_SHIFT (5u) +#define INTC_ICDISER17_TINT134_SHIFT (6u) +#define INTC_ICDISER17_TINT135_SHIFT (7u) +#define INTC_ICDISER17_TINT136_SHIFT (8u) +#define INTC_ICDISER17_TINT137_SHIFT (9u) +#define INTC_ICDISER17_TINT138_SHIFT (10u) +#define INTC_ICDISER17_TINT139_SHIFT (11u) +#define INTC_ICDISER17_TINT140_SHIFT (12u) +#define INTC_ICDISER17_TINT141_SHIFT (13u) +#define INTC_ICDISER17_TINT142_SHIFT (14u) +#define INTC_ICDISER17_TINT143_SHIFT (15u) +#define INTC_ICDISER17_TINT144_SHIFT (16u) +#define INTC_ICDISER17_TINT145_SHIFT (17u) +#define INTC_ICDISER17_TINT146_SHIFT (18u) +#define INTC_ICDISER17_TINT147_SHIFT (19u) +#define INTC_ICDISER17_TINT148_SHIFT (20u) +#define INTC_ICDISER17_TINT149_SHIFT (21u) +#define INTC_ICDISER17_TINT150_SHIFT (22u) +#define INTC_ICDISER17_TINT151_SHIFT (23u) +#define INTC_ICDISER17_TINT152_SHIFT (24u) +#define INTC_ICDISER17_TINT153_SHIFT (25u) +#define INTC_ICDISER17_TINT154_SHIFT (26u) +#define INTC_ICDISER17_TINT155_SHIFT (27u) +#define INTC_ICDISER17_TINT156_SHIFT (28u) +#define INTC_ICDISER17_TINT157_SHIFT (29u) +#define INTC_ICDISER17_TINT158_SHIFT (30u) +#define INTC_ICDISER17_TINT159_SHIFT (31u) + +#define INTC_ICDISER18_TINT160_SHIFT (0u) +#define INTC_ICDISER18_TINT161_SHIFT (1u) +#define INTC_ICDISER18_TINT162_SHIFT (2u) +#define INTC_ICDISER18_TINT163_SHIFT (3u) +#define INTC_ICDISER18_TINT164_SHIFT (4u) +#define INTC_ICDISER18_TINT165_SHIFT (5u) +#define INTC_ICDISER18_TINT166_SHIFT (6u) +#define INTC_ICDISER18_TINT167_SHIFT (7u) +#define INTC_ICDISER18_TINT168_SHIFT (8u) +#define INTC_ICDISER18_TINT169_SHIFT (9u) +#define INTC_ICDISER18_TINT170_SHIFT (10u) + +#define INTC_ICDICER0_SW0_SHIFT (0u) +#define INTC_ICDICER0_SW1_SHIFT (1u) +#define INTC_ICDICER0_SW2_SHIFT (2u) +#define INTC_ICDICER0_SW3_SHIFT (3u) +#define INTC_ICDICER0_SW4_SHIFT (4u) +#define INTC_ICDICER0_SW5_SHIFT (5u) +#define INTC_ICDICER0_SW6_SHIFT (6u) +#define INTC_ICDICER0_SW7_SHIFT (7u) +#define INTC_ICDICER0_SW8_SHIFT (8u) +#define INTC_ICDICER0_SW9_SHIFT (9u) +#define INTC_ICDICER0_SW10_SHIFT (10u) +#define INTC_ICDICER0_SW11_SHIFT (11u) +#define INTC_ICDICER0_SW12_SHIFT (12u) +#define INTC_ICDICER0_SW13_SHIFT (13u) +#define INTC_ICDICER0_SW14_SHIFT (14u) +#define INTC_ICDICER0_SW15_SHIFT (15u) +#define INTC_ICDICER0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDICER0_COMMRX0_SHIFT (17u) +#define INTC_ICDICER0_COMMTX0_SHIFT (18u) +#define INTC_ICDICER0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDICER1_IRQ0_SHIFT (0u) +#define INTC_ICDICER1_IRQ1_SHIFT (1u) +#define INTC_ICDICER1_IRQ2_SHIFT (2u) +#define INTC_ICDICER1_IRQ3_SHIFT (3u) +#define INTC_ICDICER1_IRQ4_SHIFT (4u) +#define INTC_ICDICER1_IRQ5_SHIFT (5u) +#define INTC_ICDICER1_IRQ6_SHIFT (6u) +#define INTC_ICDICER1_IRQ7_SHIFT (7u) +#define INTC_ICDICER1_PL310ERR_SHIFT (8u) +#define INTC_ICDICER1_DMAINT0_SHIFT (9u) +#define INTC_ICDICER1_DMAINT1_SHIFT (10u) +#define INTC_ICDICER1_DMAINT2_SHIFT (11u) +#define INTC_ICDICER1_DMAINT3_SHIFT (12u) +#define INTC_ICDICER1_DMAINT4_SHIFT (13u) +#define INTC_ICDICER1_DMAINT5_SHIFT (14u) +#define INTC_ICDICER1_DMAINT6_SHIFT (15u) +#define INTC_ICDICER1_DMAINT7_SHIFT (16u) +#define INTC_ICDICER1_DMAINT8_SHIFT (17u) +#define INTC_ICDICER1_DMAINT9_SHIFT (18u) +#define INTC_ICDICER1_DMAINT10_SHIFT (19u) +#define INTC_ICDICER1_DMAINT11_SHIFT (20u) +#define INTC_ICDICER1_DMAINT12_SHIFT (21u) +#define INTC_ICDICER1_DMAINT13_SHIFT (22u) +#define INTC_ICDICER1_DMAINT14_SHIFT (23u) +#define INTC_ICDICER1_DMAINT15_SHIFT (24u) +#define INTC_ICDICER1_DMAERR_SHIFT (25u) + +#define INTC_ICDICER2_USBI0_SHIFT (9u) +#define INTC_ICDICER2_USBI1_SHIFT (10u) +#define INTC_ICDICER2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDICER2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDICER2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDICER2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDICER2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDICER2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDICER2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDICER2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDICER2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDICER2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDICER2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDICER2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDICER2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDICER2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDICER2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDICER2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDICER2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDICER2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDICER2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDICER2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDICER2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDICER3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDICER3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDICER3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDICER3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDICER3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDICER3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDICER3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDICER3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDICER3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDICER3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDICER3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDICER3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDICER3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDICER3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDICER3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDICER3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDICER3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDICER3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDICER3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDICER3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDICER3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDICER3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDICER3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDICER3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDICER3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDICER3_IMRDI_SHIFT (27u) +#define INTC_ICDICER3_IMR2I0_SHIFT (28u) +#define INTC_ICDICER3_IMR2I1_SHIFT (29u) +#define INTC_ICDICER3_JEDI_SHIFT (30u) +#define INTC_ICDICER3_JDTI_SHIFT (31u) + +#define INTC_ICDICER4_CMP0_SHIFT (0u) +#define INTC_ICDICER4_CMP1_SHIFT (1u) +#define INTC_ICDICER4_INT0_SHIFT (2u) +#define INTC_ICDICER4_INT1_SHIFT (3u) +#define INTC_ICDICER4_INT2_SHIFT (4u) +#define INTC_ICDICER4_INT3_SHIFT (5u) +#define INTC_ICDICER4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDICER4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDICER4_CMI_SHIFT (8u) +#define INTC_ICDICER4_WTOUT_SHIFT (9u) +#define INTC_ICDICER4_ITI_SHIFT (10u) +#define INTC_ICDICER4_TGI0A_SHIFT (11u) +#define INTC_ICDICER4_TGI0B_SHIFT (12u) +#define INTC_ICDICER4_TGI0C_SHIFT (13u) +#define INTC_ICDICER4_TGI0D_SHIFT (14u) +#define INTC_ICDICER4_TGI0V_SHIFT (15u) +#define INTC_ICDICER4_TGI0E_SHIFT (16u) +#define INTC_ICDICER4_TGI0F_SHIFT (17u) +#define INTC_ICDICER4_TGI1A_SHIFT (18u) +#define INTC_ICDICER4_TGI1B_SHIFT (19u) +#define INTC_ICDICER4_TGI1V_SHIFT (20u) +#define INTC_ICDICER4_TGI1U_SHIFT (21u) +#define INTC_ICDICER4_TGI2A_SHIFT (22u) +#define INTC_ICDICER4_TGI2B_SHIFT (23u) +#define INTC_ICDICER4_TGI2V_SHIFT (24u) +#define INTC_ICDICER4_TGI2U_SHIFT (25u) +#define INTC_ICDICER4_TGI3A_SHIFT (26u) +#define INTC_ICDICER4_TGI3B_SHIFT (27u) +#define INTC_ICDICER4_TGI3C_SHIFT (28u) +#define INTC_ICDICER4_TGI3D_SHIFT (29u) +#define INTC_ICDICER4_TGI3V_SHIFT (30u) +#define INTC_ICDICER4_TGI4A_SHIFT (31u) + +#define INTC_ICDICER5_TGI4B_SHIFT (0u) +#define INTC_ICDICER5_TGI4C_SHIFT (1u) +#define INTC_ICDICER5_TGI4D_SHIFT (2u) +#define INTC_ICDICER5_TGI4V_SHIFT (3u) +#define INTC_ICDICER5_CMI1_SHIFT (4u) +#define INTC_ICDICER5_CMI2_SHIFT (5u) +#define INTC_ICDICER5_SGDEI0_SHIFT (6u) +#define INTC_ICDICER5_SGDEI1_SHIFT (7u) +#define INTC_ICDICER5_SGDEI2_SHIFT (8u) +#define INTC_ICDICER5_SGDEI3_SHIFT (9u) +#define INTC_ICDICER5_ADI_SHIFT (10u) +#define INTC_ICDICER5_LMTI_SHIFT (11u) +#define INTC_ICDICER5_SSII0_SHIFT (12u) +#define INTC_ICDICER5_SSIRXI0_SHIFT (13u) +#define INTC_ICDICER5_SSITXI0_SHIFT (14u) +#define INTC_ICDICER5_SSII1_SHIFT (15u) +#define INTC_ICDICER5_SSIRXI1_SHIFT (16u) +#define INTC_ICDICER5_SSITXI1_SHIFT (17u) +#define INTC_ICDICER5_SSII2_SHIFT (18u) +#define INTC_ICDICER5_SSIRTI2_SHIFT (19u) +#define INTC_ICDICER5_SSII3_SHIFT (20u) +#define INTC_ICDICER5_SSIRXI3_SHIFT (21u) +#define INTC_ICDICER5_SSITXI3_SHIFT (22u) +#define INTC_ICDICER5_SSII4_SHIFT (23u) +#define INTC_ICDICER5_SSIRTI4_SHIFT (24u) +#define INTC_ICDICER5_SSII5_SHIFT (25u) +#define INTC_ICDICER5_SSIRXI5_SHIFT (26u) +#define INTC_ICDICER5_SSITXI5_SHIFT (27u) +#define INTC_ICDICER5_SPDIFI_SHIFT (28u) +#define INTC_ICDICER5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDICER5_INTIICRI0_SHIFT (30u) +#define INTC_ICDICER5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDICER6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDICER6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDICER6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDICER6_INTIICALI0_SHIFT (3u) +#define INTC_ICDICER6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDICER6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDICER6_INTIICRI1_SHIFT (6u) +#define INTC_ICDICER6_INTIICTI1_SHIFT (7u) +#define INTC_ICDICER6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDICER6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDICER6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDICER6_INTIICALI1_SHIFT (11u) +#define INTC_ICDICER6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDICER6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDICER6_INTIICRI2_SHIFT (14u) +#define INTC_ICDICER6_INTIICTI2_SHIFT (15u) +#define INTC_ICDICER6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDICER6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDICER6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDICER6_INTIICALI2_SHIFT (19u) +#define INTC_ICDICER6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDICER6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDICER6_INTIICRI3_SHIFT (22u) +#define INTC_ICDICER6_INTIICTI3_SHIFT (23u) +#define INTC_ICDICER6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDICER6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDICER6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDICER6_INTIICALI3_SHIFT (27u) +#define INTC_ICDICER6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDICER6_BRI0_SHIFT (29u) +#define INTC_ICDICER6_ERI0_SHIFT (30u) +#define INTC_ICDICER6_RXI0_SHIFT (31u) + +#define INTC_ICDICER7_TXI0_SHIFT (0u) +#define INTC_ICDICER7_BRI1_SHIFT (1u) +#define INTC_ICDICER7_ERI1_SHIFT (2u) +#define INTC_ICDICER7_RXI1_SHIFT (3u) +#define INTC_ICDICER7_TXI1_SHIFT (4u) +#define INTC_ICDICER7_BRI2_SHIFT (5u) +#define INTC_ICDICER7_ERI2_SHIFT (6u) +#define INTC_ICDICER7_RXI2_SHIFT (7u) +#define INTC_ICDICER7_TXI2_SHIFT (8u) +#define INTC_ICDICER7_BRI3_SHIFT (9u) +#define INTC_ICDICER7_ERI3_SHIFT (10u) +#define INTC_ICDICER7_RXI3_SHIFT (11u) +#define INTC_ICDICER7_TXI3_SHIFT (12u) +#define INTC_ICDICER7_BRI4_SHIFT (13u) +#define INTC_ICDICER7_ERI4_SHIFT (14u) +#define INTC_ICDICER7_RXI4_SHIFT (15u) +#define INTC_ICDICER7_TXI4_SHIFT (16u) +#define INTC_ICDICER7_BRI5_SHIFT (17u) +#define INTC_ICDICER7_ERI5_SHIFT (18u) +#define INTC_ICDICER7_RXI5_SHIFT (19u) +#define INTC_ICDICER7_TXI5_SHIFT (20u) +#define INTC_ICDICER7_BRI6_SHIFT (21u) +#define INTC_ICDICER7_ERI6_SHIFT (22u) +#define INTC_ICDICER7_RXI6_SHIFT (23u) +#define INTC_ICDICER7_TXI6_SHIFT (24u) +#define INTC_ICDICER7_BRI7_SHIFT (25u) +#define INTC_ICDICER7_ERI7_SHIFT (26u) +#define INTC_ICDICER7_RXI7_SHIFT (27u) +#define INTC_ICDICER7_TXI7_SHIFT (28u) +#define INTC_ICDICER7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDICER7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDICER7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDICER8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDICER8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDICER8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDICER8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDICER8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDICER8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDICER8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDICER8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDICER8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDICER8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDICER8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDICER8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDICER8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDICER8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDICER8_SPEI0_SHIFT (14u) +#define INTC_ICDICER8_SPRI0_SHIFT (15u) +#define INTC_ICDICER8_SPTI0_SHIFT (16u) +#define INTC_ICDICER8_SPEI1_SHIFT (17u) +#define INTC_ICDICER8_SPRI1_SHIFT (18u) +#define INTC_ICDICER8_SPTI1_SHIFT (19u) +#define INTC_ICDICER8_SPEI2_SHIFT (20u) +#define INTC_ICDICER8_SPRI2_SHIFT (21u) +#define INTC_ICDICER8_SPTI2_SHIFT (22u) +#define INTC_ICDICER8_SPEI3_SHIFT (23u) +#define INTC_ICDICER8_SPRI3_SHIFT (24u) +#define INTC_ICDICER8_SPTI3_SHIFT (25u) +#define INTC_ICDICER8_SPEI4_SHIFT (26u) +#define INTC_ICDICER8_SPRI4_SHIFT (27u) +#define INTC_ICDICER8_SPTI4_SHIFT (28u) +#define INTC_ICDICER8_IEBBTD_SHIFT (29u) +#define INTC_ICDICER8_IEBBTERR_SHIFT (30u) +#define INTC_ICDICER8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDICER9_IEBBTV_SHIFT (0u) +#define INTC_ICDICER9_ISY_SHIFT (1u) +#define INTC_ICDICER9_IERR_SHIFT (2u) +#define INTC_ICDICER9_ITARG_SHIFT (3u) +#define INTC_ICDICER9_ISEC_SHIFT (4u) +#define INTC_ICDICER9_IBUF_SHIFT (5u) +#define INTC_ICDICER9_IREADY_SHIFT (6u) +#define INTC_ICDICER9_FLSTE_SHIFT (7u) +#define INTC_ICDICER9_FLTENDI_SHIFT (8u) +#define INTC_ICDICER9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDICER9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDICER9_MMC0_SHIFT (11u) +#define INTC_ICDICER9_MMC1_SHIFT (12u) +#define INTC_ICDICER9_MMC2_SHIFT (13u) +#define INTC_ICDICER9_SDHI0_3_SHIFT (14u) +#define INTC_ICDICER9_SDHI0_0_SHIFT (15u) +#define INTC_ICDICER9_SDHI0_1_SHIFT (16u) +#define INTC_ICDICER9_SDHI1_3_SHIFT (17u) +#define INTC_ICDICER9_SDHI1_0_SHIFT (18u) +#define INTC_ICDICER9_SDHI1_1_SHIFT (19u) +#define INTC_ICDICER9_ARM_SHIFT (20u) +#define INTC_ICDICER9_PRD_SHIFT (21u) +#define INTC_ICDICER9_CUP_SHIFT (22u) +#define INTC_ICDICER9_SCUAI0_SHIFT (23u) +#define INTC_ICDICER9_SCUAI1_SHIFT (24u) +#define INTC_ICDICER9_SCUFDI0_SHIFT (25u) +#define INTC_ICDICER9_SCUFDI1_SHIFT (26u) +#define INTC_ICDICER9_SCUFDI2_SHIFT (27u) +#define INTC_ICDICER9_SCUFDI3_SHIFT (28u) +#define INTC_ICDICER9_SCUFUI0_SHIFT (29u) +#define INTC_ICDICER9_SCUFUI1_SHIFT (30u) +#define INTC_ICDICER9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDICER10_SCUFUI3_SHIFT (0u) +#define INTC_ICDICER10_SCUDVI0_SHIFT (1u) +#define INTC_ICDICER10_SCUDVI1_SHIFT (2u) +#define INTC_ICDICER10_SCUDVI2_SHIFT (3u) +#define INTC_ICDICER10_SCUDVI3_SHIFT (4u) +#define INTC_ICDICER10_MLB_CINT_SHIFT (5u) +#define INTC_ICDICER10_MLB_SINT_SHIFT (6u) +#define INTC_ICDICER10_DRC0_SHIFT (7u) +#define INTC_ICDICER10_DRC1_SHIFT (8u) +#define INTC_ICDICER10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDICER10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDICER10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDICER10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDICER10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDICER10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDICER10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDICER10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDICER10_ERI0_SHIFT (27u) +#define INTC_ICDICER10_RXI0_SHIFT (28u) +#define INTC_ICDICER10_TXI0_SHIFT (29u) +#define INTC_ICDICER10_TEI0_SHIFT (30u) +#define INTC_ICDICER10_ERI1_SHIFT (31u) + +#define INTC_ICDICER11_RXI1_SHIFT (0u) +#define INTC_ICDICER11_TXI1_SHIFT (1u) +#define INTC_ICDICER11_TEI1_SHIFT (2u) +#define INTC_ICDICER11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDICER11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDICER11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDICER11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDICER11_ETHERI_SHIFT (7u) +#define INTC_ICDICER11_CEUI_SHIFT (12u) +#define INTC_ICDICER11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDICER11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDICER11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDICER12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDICER12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDICER12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDICER12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDICER12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDICER12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDICER12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDICER12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDICER12_PRRI_SHIFT (8u) +#define INTC_ICDICER12_IFEI0_SHIFT (9u) +#define INTC_ICDICER12_OFFI0_SHIFT (10u) +#define INTC_ICDICER12_PFVEI0_SHIFT (11u) +#define INTC_ICDICER12_IFEI1_SHIFT (12u) +#define INTC_ICDICER12_OFFI1_SHIFT (13u) +#define INTC_ICDICER12_PFVEI1_SHIFT (14u) + +#define INTC_ICDICER13_TINT0_SHIFT (0u) +#define INTC_ICDICER13_TINT1_SHIFT (1u) +#define INTC_ICDICER13_TINT2_SHIFT (2u) +#define INTC_ICDICER13_TINT3_SHIFT (3u) +#define INTC_ICDICER13_TINT4_SHIFT (4u) +#define INTC_ICDICER13_TINT5_SHIFT (5u) +#define INTC_ICDICER13_TINT6_SHIFT (6u) +#define INTC_ICDICER13_TINT7_SHIFT (7u) +#define INTC_ICDICER13_TINT8_SHIFT (8u) +#define INTC_ICDICER13_TINT9_SHIFT (9u) +#define INTC_ICDICER13_TINT10_SHIFT (10u) +#define INTC_ICDICER13_TINT11_SHIFT (11u) +#define INTC_ICDICER13_TINT12_SHIFT (12u) +#define INTC_ICDICER13_TINT13_SHIFT (13u) +#define INTC_ICDICER13_TINT14_SHIFT (14u) +#define INTC_ICDICER13_TINT15_SHIFT (15u) +#define INTC_ICDICER13_TINT16_SHIFT (16u) +#define INTC_ICDICER13_TINT17_SHIFT (17u) +#define INTC_ICDICER13_TINT18_SHIFT (18u) +#define INTC_ICDICER13_TINT19_SHIFT (19u) +#define INTC_ICDICER13_TINT20_SHIFT (20u) +#define INTC_ICDICER13_TINT21_SHIFT (21u) +#define INTC_ICDICER13_TINT22_SHIFT (22u) +#define INTC_ICDICER13_TINT23_SHIFT (23u) +#define INTC_ICDICER13_TINT24_SHIFT (24u) +#define INTC_ICDICER13_TINT25_SHIFT (25u) +#define INTC_ICDICER13_TINT26_SHIFT (26u) +#define INTC_ICDICER13_TINT27_SHIFT (27u) +#define INTC_ICDICER13_TINT28_SHIFT (28u) +#define INTC_ICDICER13_TINT29_SHIFT (29u) +#define INTC_ICDICER13_TINT30_SHIFT (30u) +#define INTC_ICDICER13_TINT31_SHIFT (31u) + +#define INTC_ICDICER14_TINT32_SHIFT (0u) +#define INTC_ICDICER14_TINT33_SHIFT (1u) +#define INTC_ICDICER14_TINT34_SHIFT (2u) +#define INTC_ICDICER14_TINT35_SHIFT (3u) +#define INTC_ICDICER14_TINT36_SHIFT (4u) +#define INTC_ICDICER14_TINT37_SHIFT (5u) +#define INTC_ICDICER14_TINT38_SHIFT (6u) +#define INTC_ICDICER14_TINT39_SHIFT (7u) +#define INTC_ICDICER14_TINT40_SHIFT (8u) +#define INTC_ICDICER14_TINT41_SHIFT (9u) +#define INTC_ICDICER14_TINT42_SHIFT (10u) +#define INTC_ICDICER14_TINT43_SHIFT (11u) +#define INTC_ICDICER14_TINT44_SHIFT (12u) +#define INTC_ICDICER14_TINT45_SHIFT (13u) +#define INTC_ICDICER14_TINT46_SHIFT (14u) +#define INTC_ICDICER14_TINT47_SHIFT (15u) +#define INTC_ICDICER14_TINT48_SHIFT (16u) +#define INTC_ICDICER14_TINT49_SHIFT (17u) +#define INTC_ICDICER14_TINT50_SHIFT (18u) +#define INTC_ICDICER14_TINT51_SHIFT (19u) +#define INTC_ICDICER14_TINT52_SHIFT (20u) +#define INTC_ICDICER14_TINT53_SHIFT (21u) +#define INTC_ICDICER14_TINT54_SHIFT (22u) +#define INTC_ICDICER14_TINT55_SHIFT (23u) +#define INTC_ICDICER14_TINT56_SHIFT (24u) +#define INTC_ICDICER14_TINT57_SHIFT (25u) +#define INTC_ICDICER14_TINT58_SHIFT (26u) +#define INTC_ICDICER14_TINT59_SHIFT (27u) +#define INTC_ICDICER14_TINT60_SHIFT (28u) +#define INTC_ICDICER14_TINT61_SHIFT (29u) +#define INTC_ICDICER14_TINT62_SHIFT (30u) +#define INTC_ICDICER14_TINT63_SHIFT (31u) + +#define INTC_ICDICER15_TINT64_SHIFT (0u) +#define INTC_ICDICER15_TINT65_SHIFT (1u) +#define INTC_ICDICER15_TINT66_SHIFT (2u) +#define INTC_ICDICER15_TINT67_SHIFT (3u) +#define INTC_ICDICER15_TINT68_SHIFT (4u) +#define INTC_ICDICER15_TINT69_SHIFT (5u) +#define INTC_ICDICER15_TINT70_SHIFT (6u) +#define INTC_ICDICER15_TINT71_SHIFT (7u) +#define INTC_ICDICER15_TINT72_SHIFT (8u) +#define INTC_ICDICER15_TINT73_SHIFT (9u) +#define INTC_ICDICER15_TINT74_SHIFT (10u) +#define INTC_ICDICER15_TINT75_SHIFT (11u) +#define INTC_ICDICER15_TINT76_SHIFT (12u) +#define INTC_ICDICER15_TINT77_SHIFT (13u) +#define INTC_ICDICER15_TINT78_SHIFT (14u) +#define INTC_ICDICER15_TINT79_SHIFT (15u) +#define INTC_ICDICER15_TINT80_SHIFT (16u) +#define INTC_ICDICER15_TINT81_SHIFT (17u) +#define INTC_ICDICER15_TINT82_SHIFT (18u) +#define INTC_ICDICER15_TINT83_SHIFT (19u) +#define INTC_ICDICER15_TINT84_SHIFT (20u) +#define INTC_ICDICER15_TINT85_SHIFT (21u) +#define INTC_ICDICER15_TINT86_SHIFT (22u) +#define INTC_ICDICER15_TINT87_SHIFT (23u) +#define INTC_ICDICER15_TINT88_SHIFT (24u) +#define INTC_ICDICER15_TINT89_SHIFT (25u) +#define INTC_ICDICER15_TINT90_SHIFT (26u) +#define INTC_ICDICER15_TINT91_SHIFT (27u) +#define INTC_ICDICER15_TINT92_SHIFT (28u) +#define INTC_ICDICER15_TINT93_SHIFT (29u) +#define INTC_ICDICER15_TINT94_SHIFT (30u) +#define INTC_ICDICER15_TINT95_SHIFT (31u) + +#define INTC_ICDICER16_TINT96_SHIFT (0u) +#define INTC_ICDICER16_TINT97_SHIFT (1u) +#define INTC_ICDICER16_TINT98_SHIFT (2u) +#define INTC_ICDICER16_TINT99_SHIFT (3u) +#define INTC_ICDICER16_TINT100_SHIFT (4u) +#define INTC_ICDICER16_TINT101_SHIFT (5u) +#define INTC_ICDICER16_TINT102_SHIFT (6u) +#define INTC_ICDICER16_TINT103_SHIFT (7u) +#define INTC_ICDICER16_TINT104_SHIFT (8u) +#define INTC_ICDICER16_TINT105_SHIFT (9u) +#define INTC_ICDICER16_TINT106_SHIFT (10u) +#define INTC_ICDICER16_TINT107_SHIFT (11u) +#define INTC_ICDICER16_TINT108_SHIFT (12u) +#define INTC_ICDICER16_TINT109_SHIFT (13u) +#define INTC_ICDICER16_TINT110_SHIFT (14u) +#define INTC_ICDICER16_TINT111_SHIFT (15u) +#define INTC_ICDICER16_TINT112_SHIFT (16u) +#define INTC_ICDICER16_TINT113_SHIFT (17u) +#define INTC_ICDICER16_TINT114_SHIFT (18u) +#define INTC_ICDICER16_TINT115_SHIFT (19u) +#define INTC_ICDICER16_TINT116_SHIFT (20u) +#define INTC_ICDICER16_TINT117_SHIFT (21u) +#define INTC_ICDICER16_TINT118_SHIFT (22u) +#define INTC_ICDICER16_TINT119_SHIFT (23u) +#define INTC_ICDICER16_TINT120_SHIFT (24u) +#define INTC_ICDICER16_TINT121_SHIFT (25u) +#define INTC_ICDICER16_TINT122_SHIFT (26u) +#define INTC_ICDICER16_TINT123_SHIFT (27u) +#define INTC_ICDICER16_TINT124_SHIFT (28u) +#define INTC_ICDICER16_TINT125_SHIFT (29u) +#define INTC_ICDICER16_TINT126_SHIFT (30u) +#define INTC_ICDICER16_TINT127_SHIFT (31u) + +#define INTC_ICDICER17_TINT128_SHIFT (0u) +#define INTC_ICDICER17_TINT129_SHIFT (1u) +#define INTC_ICDICER17_TINT130_SHIFT (2u) +#define INTC_ICDICER17_TINT131_SHIFT (3u) +#define INTC_ICDICER17_TINT132_SHIFT (4u) +#define INTC_ICDICER17_TINT133_SHIFT (5u) +#define INTC_ICDICER17_TINT134_SHIFT (6u) +#define INTC_ICDICER17_TINT135_SHIFT (7u) +#define INTC_ICDICER17_TINT136_SHIFT (8u) +#define INTC_ICDICER17_TINT137_SHIFT (9u) +#define INTC_ICDICER17_TINT138_SHIFT (10u) +#define INTC_ICDICER17_TINT139_SHIFT (11u) +#define INTC_ICDICER17_TINT140_SHIFT (12u) +#define INTC_ICDICER17_TINT141_SHIFT (13u) +#define INTC_ICDICER17_TINT142_SHIFT (14u) +#define INTC_ICDICER17_TINT143_SHIFT (15u) +#define INTC_ICDICER17_TINT144_SHIFT (16u) +#define INTC_ICDICER17_TINT145_SHIFT (17u) +#define INTC_ICDICER17_TINT146_SHIFT (18u) +#define INTC_ICDICER17_TINT147_SHIFT (19u) +#define INTC_ICDICER17_TINT148_SHIFT (20u) +#define INTC_ICDICER17_TINT149_SHIFT (21u) +#define INTC_ICDICER17_TINT150_SHIFT (22u) +#define INTC_ICDICER17_TINT151_SHIFT (23u) +#define INTC_ICDICER17_TINT152_SHIFT (24u) +#define INTC_ICDICER17_TINT153_SHIFT (25u) +#define INTC_ICDICER17_TINT154_SHIFT (26u) +#define INTC_ICDICER17_TINT155_SHIFT (27u) +#define INTC_ICDICER17_TINT156_SHIFT (28u) +#define INTC_ICDICER17_TINT157_SHIFT (29u) +#define INTC_ICDICER17_TINT158_SHIFT (30u) +#define INTC_ICDICER17_TINT159_SHIFT (31u) + +#define INTC_ICDICER18_TINT160_SHIFT (0u) +#define INTC_ICDICER18_TINT161_SHIFT (1u) +#define INTC_ICDICER18_TINT162_SHIFT (2u) +#define INTC_ICDICER18_TINT163_SHIFT (3u) +#define INTC_ICDICER18_TINT164_SHIFT (4u) +#define INTC_ICDICER18_TINT165_SHIFT (5u) +#define INTC_ICDICER18_TINT166_SHIFT (6u) +#define INTC_ICDICER18_TINT167_SHIFT (7u) +#define INTC_ICDICER18_TINT168_SHIFT (8u) +#define INTC_ICDICER18_TINT169_SHIFT (9u) +#define INTC_ICDICER18_TINT170_SHIFT (10u) + +#define INTC_ICDISPR0_SW0_SHIFT (0u) +#define INTC_ICDISPR0_SW1_SHIFT (1u) +#define INTC_ICDISPR0_SW2_SHIFT (2u) +#define INTC_ICDISPR0_SW3_SHIFT (3u) +#define INTC_ICDISPR0_SW4_SHIFT (4u) +#define INTC_ICDISPR0_SW5_SHIFT (5u) +#define INTC_ICDISPR0_SW6_SHIFT (6u) +#define INTC_ICDISPR0_SW7_SHIFT (7u) +#define INTC_ICDISPR0_SW8_SHIFT (8u) +#define INTC_ICDISPR0_SW9_SHIFT (9u) +#define INTC_ICDISPR0_SW10_SHIFT (10u) +#define INTC_ICDISPR0_SW11_SHIFT (11u) +#define INTC_ICDISPR0_SW12_SHIFT (12u) +#define INTC_ICDISPR0_SW13_SHIFT (13u) +#define INTC_ICDISPR0_SW14_SHIFT (14u) +#define INTC_ICDISPR0_SW15_SHIFT (15u) +#define INTC_ICDISPR0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDISPR0_COMMRX0_SHIFT (17u) +#define INTC_ICDISPR0_COMMTX0_SHIFT (18u) +#define INTC_ICDISPR0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDISPR1_IRQ0_SHIFT (0u) +#define INTC_ICDISPR1_IRQ1_SHIFT (1u) +#define INTC_ICDISPR1_IRQ2_SHIFT (2u) +#define INTC_ICDISPR1_IRQ3_SHIFT (3u) +#define INTC_ICDISPR1_IRQ4_SHIFT (4u) +#define INTC_ICDISPR1_IRQ5_SHIFT (5u) +#define INTC_ICDISPR1_IRQ6_SHIFT (6u) +#define INTC_ICDISPR1_IRQ7_SHIFT (7u) +#define INTC_ICDISPR1_PL310ERR_SHIFT (8u) +#define INTC_ICDISPR1_DMAINT0_SHIFT (9u) +#define INTC_ICDISPR1_DMAINT1_SHIFT (10u) +#define INTC_ICDISPR1_DMAINT2_SHIFT (11u) +#define INTC_ICDISPR1_DMAINT3_SHIFT (12u) +#define INTC_ICDISPR1_DMAINT4_SHIFT (13u) +#define INTC_ICDISPR1_DMAINT5_SHIFT (14u) +#define INTC_ICDISPR1_DMAINT6_SHIFT (15u) +#define INTC_ICDISPR1_DMAINT7_SHIFT (16u) +#define INTC_ICDISPR1_DMAINT8_SHIFT (17u) +#define INTC_ICDISPR1_DMAINT9_SHIFT (18u) +#define INTC_ICDISPR1_DMAINT10_SHIFT (19u) +#define INTC_ICDISPR1_DMAINT11_SHIFT (20u) +#define INTC_ICDISPR1_DMAINT12_SHIFT (21u) +#define INTC_ICDISPR1_DMAINT13_SHIFT (22u) +#define INTC_ICDISPR1_DMAINT14_SHIFT (23u) +#define INTC_ICDISPR1_DMAINT15_SHIFT (24u) +#define INTC_ICDISPR1_DMAERR_SHIFT (25u) + +#define INTC_ICDISPR2_USBI0_SHIFT (9u) +#define INTC_ICDISPR2_USBI1_SHIFT (10u) +#define INTC_ICDISPR2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDISPR2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDISPR2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDISPR2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDISPR2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDISPR2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDISPR2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDISPR2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDISPR2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDISPR2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDISPR2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDISPR2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDISPR2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDISPR2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDISPR2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDISPR2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDISPR2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDISPR2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDISPR2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDISPR2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDISPR2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDISPR3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDISPR3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDISPR3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDISPR3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDISPR3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDISPR3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDISPR3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDISPR3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDISPR3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDISPR3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDISPR3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDISPR3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDISPR3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDISPR3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDISPR3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDISPR3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDISPR3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDISPR3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDISPR3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDISPR3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDISPR3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDISPR3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDISPR3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDISPR3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDISPR3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDISPR3_IMRDI_SHIFT (27u) +#define INTC_ICDISPR3_IMR2I0_SHIFT (28u) +#define INTC_ICDISPR3_IMR2I1_SHIFT (29u) +#define INTC_ICDISPR3_JEDI_SHIFT (30u) +#define INTC_ICDISPR3_JDTI_SHIFT (31u) + +#define INTC_ICDISPR4_CMP0_SHIFT (0u) +#define INTC_ICDISPR4_CMP1_SHIFT (1u) +#define INTC_ICDISPR4_INT0_SHIFT (2u) +#define INTC_ICDISPR4_INT1_SHIFT (3u) +#define INTC_ICDISPR4_INT2_SHIFT (4u) +#define INTC_ICDISPR4_INT3_SHIFT (5u) +#define INTC_ICDISPR4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDISPR4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDISPR4_CMI_SHIFT (8u) +#define INTC_ICDISPR4_WTOUT_SHIFT (9u) +#define INTC_ICDISPR4_ITI_SHIFT (10u) +#define INTC_ICDISPR4_TGI0A_SHIFT (11u) +#define INTC_ICDISPR4_TGI0B_SHIFT (12u) +#define INTC_ICDISPR4_TGI0C_SHIFT (13u) +#define INTC_ICDISPR4_TGI0D_SHIFT (14u) +#define INTC_ICDISPR4_TGI0V_SHIFT (15u) +#define INTC_ICDISPR4_TGI0E_SHIFT (16u) +#define INTC_ICDISPR4_TGI0F_SHIFT (17u) +#define INTC_ICDISPR4_TGI1A_SHIFT (18u) +#define INTC_ICDISPR4_TGI1B_SHIFT (19u) +#define INTC_ICDISPR4_TGI1V_SHIFT (20u) +#define INTC_ICDISPR4_TGI1U_SHIFT (21u) +#define INTC_ICDISPR4_TGI2A_SHIFT (22u) +#define INTC_ICDISPR4_TGI2B_SHIFT (23u) +#define INTC_ICDISPR4_TGI2V_SHIFT (24u) +#define INTC_ICDISPR4_TGI2U_SHIFT (25u) +#define INTC_ICDISPR4_TGI3A_SHIFT (26u) +#define INTC_ICDISPR4_TGI3B_SHIFT (27u) +#define INTC_ICDISPR4_TGI3C_SHIFT (28u) +#define INTC_ICDISPR4_TGI3D_SHIFT (29u) +#define INTC_ICDISPR4_TGI3V_SHIFT (30u) +#define INTC_ICDISPR4_TGI4A_SHIFT (31u) + +#define INTC_ICDISPR5_TGI4B_SHIFT (0u) +#define INTC_ICDISPR5_TGI4C_SHIFT (1u) +#define INTC_ICDISPR5_TGI4D_SHIFT (2u) +#define INTC_ICDISPR5_TGI4V_SHIFT (3u) +#define INTC_ICDISPR5_CMI1_SHIFT (4u) +#define INTC_ICDISPR5_CMI2_SHIFT (5u) +#define INTC_ICDISPR5_SGDEI0_SHIFT (6u) +#define INTC_ICDISPR5_SGDEI1_SHIFT (7u) +#define INTC_ICDISPR5_SGDEI2_SHIFT (8u) +#define INTC_ICDISPR5_SGDEI3_SHIFT (9u) +#define INTC_ICDISPR5_ADI_SHIFT (10u) +#define INTC_ICDISPR5_LMTI_SHIFT (11u) +#define INTC_ICDISPR5_SSII0_SHIFT (12u) +#define INTC_ICDISPR5_SSIRXI0_SHIFT (13u) +#define INTC_ICDISPR5_SSITXI0_SHIFT (14u) +#define INTC_ICDISPR5_SSII1_SHIFT (15u) +#define INTC_ICDISPR5_SSIRXI1_SHIFT (16u) +#define INTC_ICDISPR5_SSITXI1_SHIFT (17u) +#define INTC_ICDISPR5_SSII2_SHIFT (18u) +#define INTC_ICDISPR5_SSIRTI2_SHIFT (19u) +#define INTC_ICDISPR5_SSII3_SHIFT (20u) +#define INTC_ICDISPR5_SSIRXI3_SHIFT (21u) +#define INTC_ICDISPR5_SSITXI3_SHIFT (22u) +#define INTC_ICDISPR5_SSII4_SHIFT (23u) +#define INTC_ICDISPR5_SSIRTI4_SHIFT (24u) +#define INTC_ICDISPR5_SSII5_SHIFT (25u) +#define INTC_ICDISPR5_SSIRXI5_SHIFT (26u) +#define INTC_ICDISPR5_SSITXI5_SHIFT (27u) +#define INTC_ICDISPR5_SPDIFI_SHIFT (28u) +#define INTC_ICDISPR5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDISPR5_INTIICRI0_SHIFT (30u) +#define INTC_ICDISPR5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDISPR6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDISPR6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDISPR6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDISPR6_INTIICALI0_SHIFT (3u) +#define INTC_ICDISPR6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDISPR6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDISPR6_INTIICRI1_SHIFT (6u) +#define INTC_ICDISPR6_INTIICTI1_SHIFT (7u) +#define INTC_ICDISPR6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDISPR6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDISPR6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDISPR6_INTIICALI1_SHIFT (11u) +#define INTC_ICDISPR6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDISPR6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDISPR6_INTIICRI2_SHIFT (14u) +#define INTC_ICDISPR6_INTIICTI2_SHIFT (15u) +#define INTC_ICDISPR6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDISPR6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDISPR6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDISPR6_INTIICALI2_SHIFT (19u) +#define INTC_ICDISPR6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDISPR6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDISPR6_INTIICRI3_SHIFT (22u) +#define INTC_ICDISPR6_INTIICTI3_SHIFT (23u) +#define INTC_ICDISPR6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDISPR6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDISPR6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDISPR6_INTIICALI3_SHIFT (27u) +#define INTC_ICDISPR6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDISPR6_BRI0_SHIFT (29u) +#define INTC_ICDISPR6_ERI0_SHIFT (30u) +#define INTC_ICDISPR6_RXI0_SHIFT (31u) + +#define INTC_ICDISPR7_TXI0_SHIFT (0u) +#define INTC_ICDISPR7_BRI1_SHIFT (1u) +#define INTC_ICDISPR7_ERI1_SHIFT (2u) +#define INTC_ICDISPR7_RXI1_SHIFT (3u) +#define INTC_ICDISPR7_TXI1_SHIFT (4u) +#define INTC_ICDISPR7_BRI2_SHIFT (5u) +#define INTC_ICDISPR7_ERI2_SHIFT (6u) +#define INTC_ICDISPR7_RXI2_SHIFT (7u) +#define INTC_ICDISPR7_TXI2_SHIFT (8u) +#define INTC_ICDISPR7_BRI3_SHIFT (9u) +#define INTC_ICDISPR7_ERI3_SHIFT (10u) +#define INTC_ICDISPR7_RXI3_SHIFT (11u) +#define INTC_ICDISPR7_TXI3_SHIFT (12u) +#define INTC_ICDISPR7_BRI4_SHIFT (13u) +#define INTC_ICDISPR7_ERI4_SHIFT (14u) +#define INTC_ICDISPR7_RXI4_SHIFT (15u) +#define INTC_ICDISPR7_TXI4_SHIFT (16u) +#define INTC_ICDISPR7_BRI5_SHIFT (17u) +#define INTC_ICDISPR7_ERI5_SHIFT (18u) +#define INTC_ICDISPR7_RXI5_SHIFT (19u) +#define INTC_ICDISPR7_TXI5_SHIFT (20u) +#define INTC_ICDISPR7_BRI6_SHIFT (21u) +#define INTC_ICDISPR7_ERI6_SHIFT (22u) +#define INTC_ICDISPR7_RXI6_SHIFT (23u) +#define INTC_ICDISPR7_TXI6_SHIFT (24u) +#define INTC_ICDISPR7_BRI7_SHIFT (25u) +#define INTC_ICDISPR7_ERI7_SHIFT (26u) +#define INTC_ICDISPR7_RXI7_SHIFT (27u) +#define INTC_ICDISPR7_TXI7_SHIFT (28u) +#define INTC_ICDISPR7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDISPR7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDISPR7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDISPR8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDISPR8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDISPR8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDISPR8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDISPR8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDISPR8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDISPR8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDISPR8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDISPR8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDISPR8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDISPR8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDISPR8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDISPR8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDISPR8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDISPR8_SPEI0_SHIFT (14u) +#define INTC_ICDISPR8_SPRI0_SHIFT (15u) +#define INTC_ICDISPR8_SPTI0_SHIFT (16u) +#define INTC_ICDISPR8_SPEI1_SHIFT (17u) +#define INTC_ICDISPR8_SPRI1_SHIFT (18u) +#define INTC_ICDISPR8_SPTI1_SHIFT (19u) +#define INTC_ICDISPR8_SPEI2_SHIFT (20u) +#define INTC_ICDISPR8_SPRI2_SHIFT (21u) +#define INTC_ICDISPR8_SPTI2_SHIFT (22u) +#define INTC_ICDISPR8_SPEI3_SHIFT (23u) +#define INTC_ICDISPR8_SPRI3_SHIFT (24u) +#define INTC_ICDISPR8_SPTI3_SHIFT (25u) +#define INTC_ICDISPR8_SPEI4_SHIFT (26u) +#define INTC_ICDISPR8_SPRI4_SHIFT (27u) +#define INTC_ICDISPR8_SPTI4_SHIFT (28u) +#define INTC_ICDISPR8_IEBBTD_SHIFT (29u) +#define INTC_ICDISPR8_IEBBTERR_SHIFT (30u) +#define INTC_ICDISPR8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDISPR9_IEBBTV_SHIFT (0u) +#define INTC_ICDISPR9_ISY_SHIFT (1u) +#define INTC_ICDISPR9_IERR_SHIFT (2u) +#define INTC_ICDISPR9_ITARG_SHIFT (3u) +#define INTC_ICDISPR9_ISEC_SHIFT (4u) +#define INTC_ICDISPR9_IBUF_SHIFT (5u) +#define INTC_ICDISPR9_IREADY_SHIFT (6u) +#define INTC_ICDISPR9_FLSTE_SHIFT (7u) +#define INTC_ICDISPR9_FLTENDI_SHIFT (8u) +#define INTC_ICDISPR9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDISPR9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDISPR9_MMC0_SHIFT (11u) +#define INTC_ICDISPR9_MMC1_SHIFT (12u) +#define INTC_ICDISPR9_MMC2_SHIFT (13u) +#define INTC_ICDISPR9_SDHI0_3_SHIFT (14u) +#define INTC_ICDISPR9_SDHI0_0_SHIFT (15u) +#define INTC_ICDISPR9_SDHI0_1_SHIFT (16u) +#define INTC_ICDISPR9_SDHI1_3_SHIFT (17u) +#define INTC_ICDISPR9_SDHI1_0_SHIFT (18u) +#define INTC_ICDISPR9_SDHI1_1_SHIFT (19u) +#define INTC_ICDISPR9_ARM_SHIFT (20u) +#define INTC_ICDISPR9_PRD_SHIFT (21u) +#define INTC_ICDISPR9_CUP_SHIFT (22u) +#define INTC_ICDISPR9_SCUAI0_SHIFT (23u) +#define INTC_ICDISPR9_SCUAI1_SHIFT (24u) +#define INTC_ICDISPR9_SCUFDI0_SHIFT (25u) +#define INTC_ICDISPR9_SCUFDI1_SHIFT (26u) +#define INTC_ICDISPR9_SCUFDI2_SHIFT (27u) +#define INTC_ICDISPR9_SCUFDI3_SHIFT (28u) +#define INTC_ICDISPR9_SCUFUI0_SHIFT (29u) +#define INTC_ICDISPR9_SCUFUI1_SHIFT (30u) +#define INTC_ICDISPR9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDISPR10_SCUFUI3_SHIFT (0u) +#define INTC_ICDISPR10_SCUDVI0_SHIFT (1u) +#define INTC_ICDISPR10_SCUDVI1_SHIFT (2u) +#define INTC_ICDISPR10_SCUDVI2_SHIFT (3u) +#define INTC_ICDISPR10_SCUDVI3_SHIFT (4u) +#define INTC_ICDISPR10_MLB_CINT_SHIFT (5u) +#define INTC_ICDISPR10_MLB_SINT_SHIFT (6u) +#define INTC_ICDISPR10_DRC0_SHIFT (7u) +#define INTC_ICDISPR10_DRC1_SHIFT (8u) +#define INTC_ICDISPR10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDISPR10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDISPR10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDISPR10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDISPR10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDISPR10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDISPR10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDISPR10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDISPR10_ERI0_SHIFT (27u) +#define INTC_ICDISPR10_RXI0_SHIFT (28u) +#define INTC_ICDISPR10_TXI0_SHIFT (29u) +#define INTC_ICDISPR10_TEI0_SHIFT (30u) +#define INTC_ICDISPR10_ERI1_SHIFT (31u) + +#define INTC_ICDISPR11_RXI1_SHIFT (0u) +#define INTC_ICDISPR11_TXI1_SHIFT (1u) +#define INTC_ICDISPR11_TEI1_SHIFT (2u) +#define INTC_ICDISPR11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDISPR11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDISPR11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDISPR11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDISPR11_ETHERI_SHIFT (7u) +#define INTC_ICDISPR11_CEUI_SHIFT (12u) +#define INTC_ICDISPR11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDISPR11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDISPR11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDISPR12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDISPR12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDISPR12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDISPR12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDISPR12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDISPR12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDISPR12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDISPR12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDISPR12_PRRI_SHIFT (8u) +#define INTC_ICDISPR12_IFEI0_SHIFT (9u) +#define INTC_ICDISPR12_OFFI0_SHIFT (10u) +#define INTC_ICDISPR12_PFVEI0_SHIFT (11u) +#define INTC_ICDISPR12_IFEI1_SHIFT (12u) +#define INTC_ICDISPR12_OFFI1_SHIFT (13u) +#define INTC_ICDISPR12_PFVEI1_SHIFT (14u) + +#define INTC_ICDISPR13_TINT0_SHIFT (0u) +#define INTC_ICDISPR13_TINT1_SHIFT (1u) +#define INTC_ICDISPR13_TINT2_SHIFT (2u) +#define INTC_ICDISPR13_TINT3_SHIFT (3u) +#define INTC_ICDISPR13_TINT4_SHIFT (4u) +#define INTC_ICDISPR13_TINT5_SHIFT (5u) +#define INTC_ICDISPR13_TINT6_SHIFT (6u) +#define INTC_ICDISPR13_TINT7_SHIFT (7u) +#define INTC_ICDISPR13_TINT8_SHIFT (8u) +#define INTC_ICDISPR13_TINT9_SHIFT (9u) +#define INTC_ICDISPR13_TINT10_SHIFT (10u) +#define INTC_ICDISPR13_TINT11_SHIFT (11u) +#define INTC_ICDISPR13_TINT12_SHIFT (12u) +#define INTC_ICDISPR13_TINT13_SHIFT (13u) +#define INTC_ICDISPR13_TINT14_SHIFT (14u) +#define INTC_ICDISPR13_TINT15_SHIFT (15u) +#define INTC_ICDISPR13_TINT16_SHIFT (16u) +#define INTC_ICDISPR13_TINT17_SHIFT (17u) +#define INTC_ICDISPR13_TINT18_SHIFT (18u) +#define INTC_ICDISPR13_TINT19_SHIFT (19u) +#define INTC_ICDISPR13_TINT20_SHIFT (20u) +#define INTC_ICDISPR13_TINT21_SHIFT (21u) +#define INTC_ICDISPR13_TINT22_SHIFT (22u) +#define INTC_ICDISPR13_TINT23_SHIFT (23u) +#define INTC_ICDISPR13_TINT24_SHIFT (24u) +#define INTC_ICDISPR13_TINT25_SHIFT (25u) +#define INTC_ICDISPR13_TINT26_SHIFT (26u) +#define INTC_ICDISPR13_TINT27_SHIFT (27u) +#define INTC_ICDISPR13_TINT28_SHIFT (28u) +#define INTC_ICDISPR13_TINT29_SHIFT (29u) +#define INTC_ICDISPR13_TINT30_SHIFT (30u) +#define INTC_ICDISPR13_TINT31_SHIFT (31u) + +#define INTC_ICDISPR14_TINT32_SHIFT (0u) +#define INTC_ICDISPR14_TINT33_SHIFT (1u) +#define INTC_ICDISPR14_TINT34_SHIFT (2u) +#define INTC_ICDISPR14_TINT35_SHIFT (3u) +#define INTC_ICDISPR14_TINT36_SHIFT (4u) +#define INTC_ICDISPR14_TINT37_SHIFT (5u) +#define INTC_ICDISPR14_TINT38_SHIFT (6u) +#define INTC_ICDISPR14_TINT39_SHIFT (7u) +#define INTC_ICDISPR14_TINT40_SHIFT (8u) +#define INTC_ICDISPR14_TINT41_SHIFT (9u) +#define INTC_ICDISPR14_TINT42_SHIFT (10u) +#define INTC_ICDISPR14_TINT43_SHIFT (11u) +#define INTC_ICDISPR14_TINT44_SHIFT (12u) +#define INTC_ICDISPR14_TINT45_SHIFT (13u) +#define INTC_ICDISPR14_TINT46_SHIFT (14u) +#define INTC_ICDISPR14_TINT47_SHIFT (15u) +#define INTC_ICDISPR14_TINT48_SHIFT (16u) +#define INTC_ICDISPR14_TINT49_SHIFT (17u) +#define INTC_ICDISPR14_TINT50_SHIFT (18u) +#define INTC_ICDISPR14_TINT51_SHIFT (19u) +#define INTC_ICDISPR14_TINT52_SHIFT (20u) +#define INTC_ICDISPR14_TINT53_SHIFT (21u) +#define INTC_ICDISPR14_TINT54_SHIFT (22u) +#define INTC_ICDISPR14_TINT55_SHIFT (23u) +#define INTC_ICDISPR14_TINT56_SHIFT (24u) +#define INTC_ICDISPR14_TINT57_SHIFT (25u) +#define INTC_ICDISPR14_TINT58_SHIFT (26u) +#define INTC_ICDISPR14_TINT59_SHIFT (27u) +#define INTC_ICDISPR14_TINT60_SHIFT (28u) +#define INTC_ICDISPR14_TINT61_SHIFT (29u) +#define INTC_ICDISPR14_TINT62_SHIFT (30u) +#define INTC_ICDISPR14_TINT63_SHIFT (31u) + +#define INTC_ICDISPR15_TINT64_SHIFT (0u) +#define INTC_ICDISPR15_TINT65_SHIFT (1u) +#define INTC_ICDISPR15_TINT66_SHIFT (2u) +#define INTC_ICDISPR15_TINT67_SHIFT (3u) +#define INTC_ICDISPR15_TINT68_SHIFT (4u) +#define INTC_ICDISPR15_TINT69_SHIFT (5u) +#define INTC_ICDISPR15_TINT70_SHIFT (6u) +#define INTC_ICDISPR15_TINT71_SHIFT (7u) +#define INTC_ICDISPR15_TINT72_SHIFT (8u) +#define INTC_ICDISPR15_TINT73_SHIFT (9u) +#define INTC_ICDISPR15_TINT74_SHIFT (10u) +#define INTC_ICDISPR15_TINT75_SHIFT (11u) +#define INTC_ICDISPR15_TINT76_SHIFT (12u) +#define INTC_ICDISPR15_TINT77_SHIFT (13u) +#define INTC_ICDISPR15_TINT78_SHIFT (14u) +#define INTC_ICDISPR15_TINT79_SHIFT (15u) +#define INTC_ICDISPR15_TINT80_SHIFT (16u) +#define INTC_ICDISPR15_TINT81_SHIFT (17u) +#define INTC_ICDISPR15_TINT82_SHIFT (18u) +#define INTC_ICDISPR15_TINT83_SHIFT (19u) +#define INTC_ICDISPR15_TINT84_SHIFT (20u) +#define INTC_ICDISPR15_TINT85_SHIFT (21u) +#define INTC_ICDISPR15_TINT86_SHIFT (22u) +#define INTC_ICDISPR15_TINT87_SHIFT (23u) +#define INTC_ICDISPR15_TINT88_SHIFT (24u) +#define INTC_ICDISPR15_TINT89_SHIFT (25u) +#define INTC_ICDISPR15_TINT90_SHIFT (26u) +#define INTC_ICDISPR15_TINT91_SHIFT (27u) +#define INTC_ICDISPR15_TINT92_SHIFT (28u) +#define INTC_ICDISPR15_TINT93_SHIFT (29u) +#define INTC_ICDISPR15_TINT94_SHIFT (30u) +#define INTC_ICDISPR15_TINT95_SHIFT (31u) + +#define INTC_ICDISPR16_TINT96_SHIFT (0u) +#define INTC_ICDISPR16_TINT97_SHIFT (1u) +#define INTC_ICDISPR16_TINT98_SHIFT (2u) +#define INTC_ICDISPR16_TINT99_SHIFT (3u) +#define INTC_ICDISPR16_TINT100_SHIFT (4u) +#define INTC_ICDISPR16_TINT101_SHIFT (5u) +#define INTC_ICDISPR16_TINT102_SHIFT (6u) +#define INTC_ICDISPR16_TINT103_SHIFT (7u) +#define INTC_ICDISPR16_TINT104_SHIFT (8u) +#define INTC_ICDISPR16_TINT105_SHIFT (9u) +#define INTC_ICDISPR16_TINT106_SHIFT (10u) +#define INTC_ICDISPR16_TINT107_SHIFT (11u) +#define INTC_ICDISPR16_TINT108_SHIFT (12u) +#define INTC_ICDISPR16_TINT109_SHIFT (13u) +#define INTC_ICDISPR16_TINT110_SHIFT (14u) +#define INTC_ICDISPR16_TINT111_SHIFT (15u) +#define INTC_ICDISPR16_TINT112_SHIFT (16u) +#define INTC_ICDISPR16_TINT113_SHIFT (17u) +#define INTC_ICDISPR16_TINT114_SHIFT (18u) +#define INTC_ICDISPR16_TINT115_SHIFT (19u) +#define INTC_ICDISPR16_TINT116_SHIFT (20u) +#define INTC_ICDISPR16_TINT117_SHIFT (21u) +#define INTC_ICDISPR16_TINT118_SHIFT (22u) +#define INTC_ICDISPR16_TINT119_SHIFT (23u) +#define INTC_ICDISPR16_TINT120_SHIFT (24u) +#define INTC_ICDISPR16_TINT121_SHIFT (25u) +#define INTC_ICDISPR16_TINT122_SHIFT (26u) +#define INTC_ICDISPR16_TINT123_SHIFT (27u) +#define INTC_ICDISPR16_TINT124_SHIFT (28u) +#define INTC_ICDISPR16_TINT125_SHIFT (29u) +#define INTC_ICDISPR16_TINT126_SHIFT (30u) +#define INTC_ICDISPR16_TINT127_SHIFT (31u) + +#define INTC_ICDISPR17_TINT128_SHIFT (0u) +#define INTC_ICDISPR17_TINT129_SHIFT (1u) +#define INTC_ICDISPR17_TINT130_SHIFT (2u) +#define INTC_ICDISPR17_TINT131_SHIFT (3u) +#define INTC_ICDISPR17_TINT132_SHIFT (4u) +#define INTC_ICDISPR17_TINT133_SHIFT (5u) +#define INTC_ICDISPR17_TINT134_SHIFT (6u) +#define INTC_ICDISPR17_TINT135_SHIFT (7u) +#define INTC_ICDISPR17_TINT136_SHIFT (8u) +#define INTC_ICDISPR17_TINT137_SHIFT (9u) +#define INTC_ICDISPR17_TINT138_SHIFT (10u) +#define INTC_ICDISPR17_TINT139_SHIFT (11u) +#define INTC_ICDISPR17_TINT140_SHIFT (12u) +#define INTC_ICDISPR17_TINT141_SHIFT (13u) +#define INTC_ICDISPR17_TINT142_SHIFT (14u) +#define INTC_ICDISPR17_TINT143_SHIFT (15u) +#define INTC_ICDISPR17_TINT144_SHIFT (16u) +#define INTC_ICDISPR17_TINT145_SHIFT (17u) +#define INTC_ICDISPR17_TINT146_SHIFT (18u) +#define INTC_ICDISPR17_TINT147_SHIFT (19u) +#define INTC_ICDISPR17_TINT148_SHIFT (20u) +#define INTC_ICDISPR17_TINT149_SHIFT (21u) +#define INTC_ICDISPR17_TINT150_SHIFT (22u) +#define INTC_ICDISPR17_TINT151_SHIFT (23u) +#define INTC_ICDISPR17_TINT152_SHIFT (24u) +#define INTC_ICDISPR17_TINT153_SHIFT (25u) +#define INTC_ICDISPR17_TINT154_SHIFT (26u) +#define INTC_ICDISPR17_TINT155_SHIFT (27u) +#define INTC_ICDISPR17_TINT156_SHIFT (28u) +#define INTC_ICDISPR17_TINT157_SHIFT (29u) +#define INTC_ICDISPR17_TINT158_SHIFT (30u) +#define INTC_ICDISPR17_TINT159_SHIFT (31u) + +#define INTC_ICDISPR18_TINT160_SHIFT (0u) +#define INTC_ICDISPR18_TINT161_SHIFT (1u) +#define INTC_ICDISPR18_TINT162_SHIFT (2u) +#define INTC_ICDISPR18_TINT163_SHIFT (3u) +#define INTC_ICDISPR18_TINT164_SHIFT (4u) +#define INTC_ICDISPR18_TINT165_SHIFT (5u) +#define INTC_ICDISPR18_TINT166_SHIFT (6u) +#define INTC_ICDISPR18_TINT167_SHIFT (7u) +#define INTC_ICDISPR18_TINT168_SHIFT (8u) +#define INTC_ICDISPR18_TINT169_SHIFT (9u) +#define INTC_ICDISPR18_TINT170_SHIFT (10u) + +#define INTC_ICDICPR0_SW0_SHIFT (0u) +#define INTC_ICDICPR0_SW1_SHIFT (1u) +#define INTC_ICDICPR0_SW2_SHIFT (2u) +#define INTC_ICDICPR0_SW3_SHIFT (3u) +#define INTC_ICDICPR0_SW4_SHIFT (4u) +#define INTC_ICDICPR0_SW5_SHIFT (5u) +#define INTC_ICDICPR0_SW6_SHIFT (6u) +#define INTC_ICDICPR0_SW7_SHIFT (7u) +#define INTC_ICDICPR0_SW8_SHIFT (8u) +#define INTC_ICDICPR0_SW9_SHIFT (9u) +#define INTC_ICDICPR0_SW10_SHIFT (10u) +#define INTC_ICDICPR0_SW11_SHIFT (11u) +#define INTC_ICDICPR0_SW12_SHIFT (12u) +#define INTC_ICDICPR0_SW13_SHIFT (13u) +#define INTC_ICDICPR0_SW14_SHIFT (14u) +#define INTC_ICDICPR0_SW15_SHIFT (15u) +#define INTC_ICDICPR0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDICPR0_COMMRX0_SHIFT (17u) +#define INTC_ICDICPR0_COMMTX0_SHIFT (18u) +#define INTC_ICDICPR0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDICPR1_IRQ0_SHIFT (0u) +#define INTC_ICDICPR1_IRQ1_SHIFT (1u) +#define INTC_ICDICPR1_IRQ2_SHIFT (2u) +#define INTC_ICDICPR1_IRQ3_SHIFT (3u) +#define INTC_ICDICPR1_IRQ4_SHIFT (4u) +#define INTC_ICDICPR1_IRQ5_SHIFT (5u) +#define INTC_ICDICPR1_IRQ6_SHIFT (6u) +#define INTC_ICDICPR1_IRQ7_SHIFT (7u) +#define INTC_ICDICPR1_PL310ERR_SHIFT (8u) +#define INTC_ICDICPR1_DMAINT0_SHIFT (9u) +#define INTC_ICDICPR1_DMAINT1_SHIFT (10u) +#define INTC_ICDICPR1_DMAINT2_SHIFT (11u) +#define INTC_ICDICPR1_DMAINT3_SHIFT (12u) +#define INTC_ICDICPR1_DMAINT4_SHIFT (13u) +#define INTC_ICDICPR1_DMAINT5_SHIFT (14u) +#define INTC_ICDICPR1_DMAINT6_SHIFT (15u) +#define INTC_ICDICPR1_DMAINT7_SHIFT (16u) +#define INTC_ICDICPR1_DMAINT8_SHIFT (17u) +#define INTC_ICDICPR1_DMAINT9_SHIFT (18u) +#define INTC_ICDICPR1_DMAINT10_SHIFT (19u) +#define INTC_ICDICPR1_DMAINT11_SHIFT (20u) +#define INTC_ICDICPR1_DMAINT12_SHIFT (21u) +#define INTC_ICDICPR1_DMAINT13_SHIFT (22u) +#define INTC_ICDICPR1_DMAINT14_SHIFT (23u) +#define INTC_ICDICPR1_DMAINT15_SHIFT (24u) +#define INTC_ICDICPR1_DMAERR_SHIFT (25u) + +#define INTC_ICDICPR2_USBI0_SHIFT (9u) +#define INTC_ICDICPR2_USBI1_SHIFT (10u) +#define INTC_ICDICPR2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDICPR2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDICPR2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDICPR2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDICPR2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDICPR2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDICPR2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDICPR2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDICPR2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDICPR2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDICPR2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDICPR2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDICPR2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDICPR2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDICPR2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDICPR2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDICPR2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDICPR2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDICPR2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDICPR2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDICPR2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDICPR3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDICPR3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDICPR3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDICPR3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDICPR3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDICPR3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDICPR3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDICPR3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDICPR3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDICPR3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDICPR3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDICPR3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDICPR3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDICPR3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDICPR3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDICPR3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDICPR3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDICPR3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDICPR3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDICPR3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDICPR3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDICPR3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDICPR3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDICPR3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDICPR3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDICPR3_IMRDI_SHIFT (27u) +#define INTC_ICDICPR3_IMR2I0_SHIFT (28u) +#define INTC_ICDICPR3_IMR2I1_SHIFT (29u) +#define INTC_ICDICPR3_JEDI_SHIFT (30u) +#define INTC_ICDICPR3_JDTI_SHIFT (31u) + +#define INTC_ICDICPR4_CMP0_SHIFT (0u) +#define INTC_ICDICPR4_CMP1_SHIFT (1u) +#define INTC_ICDICPR4_INT0_SHIFT (2u) +#define INTC_ICDICPR4_INT1_SHIFT (3u) +#define INTC_ICDICPR4_INT2_SHIFT (4u) +#define INTC_ICDICPR4_INT3_SHIFT (5u) +#define INTC_ICDICPR4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDICPR4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDICPR4_CMI_SHIFT (8u) +#define INTC_ICDICPR4_WTOUT_SHIFT (9u) +#define INTC_ICDICPR4_ITI_SHIFT (10u) +#define INTC_ICDICPR4_TGI0A_SHIFT (11u) +#define INTC_ICDICPR4_TGI0B_SHIFT (12u) +#define INTC_ICDICPR4_TGI0C_SHIFT (13u) +#define INTC_ICDICPR4_TGI0D_SHIFT (14u) +#define INTC_ICDICPR4_TGI0V_SHIFT (15u) +#define INTC_ICDICPR4_TGI0E_SHIFT (16u) +#define INTC_ICDICPR4_TGI0F_SHIFT (17u) +#define INTC_ICDICPR4_TGI1A_SHIFT (18u) +#define INTC_ICDICPR4_TGI1B_SHIFT (19u) +#define INTC_ICDICPR4_TGI1V_SHIFT (20u) +#define INTC_ICDICPR4_TGI1U_SHIFT (21u) +#define INTC_ICDICPR4_TGI2A_SHIFT (22u) +#define INTC_ICDICPR4_TGI2B_SHIFT (23u) +#define INTC_ICDICPR4_TGI2V_SHIFT (24u) +#define INTC_ICDICPR4_TGI2U_SHIFT (25u) +#define INTC_ICDICPR4_TGI3A_SHIFT (26u) +#define INTC_ICDICPR4_TGI3B_SHIFT (27u) +#define INTC_ICDICPR4_TGI3C_SHIFT (28u) +#define INTC_ICDICPR4_TGI3D_SHIFT (29u) +#define INTC_ICDICPR4_TGI3V_SHIFT (30u) +#define INTC_ICDICPR4_TGI4A_SHIFT (31u) + +#define INTC_ICDICPR5_TGI4B_SHIFT (0u) +#define INTC_ICDICPR5_TGI4C_SHIFT (1u) +#define INTC_ICDICPR5_TGI4D_SHIFT (2u) +#define INTC_ICDICPR5_TGI4V_SHIFT (3u) +#define INTC_ICDICPR5_CMI1_SHIFT (4u) +#define INTC_ICDICPR5_CMI2_SHIFT (5u) +#define INTC_ICDICPR5_SGDEI0_SHIFT (6u) +#define INTC_ICDICPR5_SGDEI1_SHIFT (7u) +#define INTC_ICDICPR5_SGDEI2_SHIFT (8u) +#define INTC_ICDICPR5_SGDEI3_SHIFT (9u) +#define INTC_ICDICPR5_ADI_SHIFT (10u) +#define INTC_ICDICPR5_LMTI_SHIFT (11u) +#define INTC_ICDICPR5_SSII0_SHIFT (12u) +#define INTC_ICDICPR5_SSIRXI0_SHIFT (13u) +#define INTC_ICDICPR5_SSITXI0_SHIFT (14u) +#define INTC_ICDICPR5_SSII1_SHIFT (15u) +#define INTC_ICDICPR5_SSIRXI1_SHIFT (16u) +#define INTC_ICDICPR5_SSITXI1_SHIFT (17u) +#define INTC_ICDICPR5_SSII2_SHIFT (18u) +#define INTC_ICDICPR5_SSIRTI2_SHIFT (19u) +#define INTC_ICDICPR5_SSII3_SHIFT (20u) +#define INTC_ICDICPR5_SSIRXI3_SHIFT (21u) +#define INTC_ICDICPR5_SSITXI3_SHIFT (22u) +#define INTC_ICDICPR5_SSII4_SHIFT (23u) +#define INTC_ICDICPR5_SSIRTI4_SHIFT (24u) +#define INTC_ICDICPR5_SSII5_SHIFT (25u) +#define INTC_ICDICPR5_SSIRXI5_SHIFT (26u) +#define INTC_ICDICPR5_SSITXI5_SHIFT (27u) +#define INTC_ICDICPR5_SPDIFI_SHIFT (28u) +#define INTC_ICDICPR5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDICPR5_INTIICRI0_SHIFT (30u) +#define INTC_ICDICPR5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDICPR6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDICPR6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDICPR6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDICPR6_INTIICALI0_SHIFT (3u) +#define INTC_ICDICPR6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDICPR6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDICPR6_INTIICRI1_SHIFT (6u) +#define INTC_ICDICPR6_INTIICTI1_SHIFT (7u) +#define INTC_ICDICPR6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDICPR6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDICPR6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDICPR6_INTIICALI1_SHIFT (11u) +#define INTC_ICDICPR6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDICPR6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDICPR6_INTIICRI2_SHIFT (14u) +#define INTC_ICDICPR6_INTIICTI2_SHIFT (15u) +#define INTC_ICDICPR6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDICPR6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDICPR6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDICPR6_INTIICALI2_SHIFT (19u) +#define INTC_ICDICPR6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDICPR6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDICPR6_INTIICRI3_SHIFT (22u) +#define INTC_ICDICPR6_INTIICTI3_SHIFT (23u) +#define INTC_ICDICPR6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDICPR6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDICPR6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDICPR6_INTIICALI3_SHIFT (27u) +#define INTC_ICDICPR6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDICPR6_BRI0_SHIFT (29u) +#define INTC_ICDICPR6_ERI0_SHIFT (30u) +#define INTC_ICDICPR6_RXI0_SHIFT (31u) + +#define INTC_ICDICPR7_TXI0_SHIFT (0u) +#define INTC_ICDICPR7_BRI1_SHIFT (1u) +#define INTC_ICDICPR7_ERI1_SHIFT (2u) +#define INTC_ICDICPR7_RXI1_SHIFT (3u) +#define INTC_ICDICPR7_TXI1_SHIFT (4u) +#define INTC_ICDICPR7_BRI2_SHIFT (5u) +#define INTC_ICDICPR7_ERI2_SHIFT (6u) +#define INTC_ICDICPR7_RXI2_SHIFT (7u) +#define INTC_ICDICPR7_TXI2_SHIFT (8u) +#define INTC_ICDICPR7_BRI3_SHIFT (9u) +#define INTC_ICDICPR7_ERI3_SHIFT (10u) +#define INTC_ICDICPR7_RXI3_SHIFT (11u) +#define INTC_ICDICPR7_TXI3_SHIFT (12u) +#define INTC_ICDICPR7_BRI4_SHIFT (13u) +#define INTC_ICDICPR7_ERI4_SHIFT (14u) +#define INTC_ICDICPR7_RXI4_SHIFT (15u) +#define INTC_ICDICPR7_TXI4_SHIFT (16u) +#define INTC_ICDICPR7_BRI5_SHIFT (17u) +#define INTC_ICDICPR7_ERI5_SHIFT (18u) +#define INTC_ICDICPR7_RXI5_SHIFT (19u) +#define INTC_ICDICPR7_TXI5_SHIFT (20u) +#define INTC_ICDICPR7_BRI6_SHIFT (21u) +#define INTC_ICDICPR7_ERI6_SHIFT (22u) +#define INTC_ICDICPR7_RXI6_SHIFT (23u) +#define INTC_ICDICPR7_TXI6_SHIFT (24u) +#define INTC_ICDICPR7_BRI7_SHIFT (25u) +#define INTC_ICDICPR7_ERI7_SHIFT (26u) +#define INTC_ICDICPR7_RXI7_SHIFT (27u) +#define INTC_ICDICPR7_TXI7_SHIFT (28u) +#define INTC_ICDICPR7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDICPR7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDICPR7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDICPR8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDICPR8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDICPR8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDICPR8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDICPR8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDICPR8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDICPR8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDICPR8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDICPR8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDICPR8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDICPR8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDICPR8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDICPR8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDICPR8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDICPR8_SPEI0_SHIFT (14u) +#define INTC_ICDICPR8_SPRI0_SHIFT (15u) +#define INTC_ICDICPR8_SPTI0_SHIFT (16u) +#define INTC_ICDICPR8_SPEI1_SHIFT (17u) +#define INTC_ICDICPR8_SPRI1_SHIFT (18u) +#define INTC_ICDICPR8_SPTI1_SHIFT (19u) +#define INTC_ICDICPR8_SPEI2_SHIFT (20u) +#define INTC_ICDICPR8_SPRI2_SHIFT (21u) +#define INTC_ICDICPR8_SPTI2_SHIFT (22u) +#define INTC_ICDICPR8_SPEI3_SHIFT (23u) +#define INTC_ICDICPR8_SPRI3_SHIFT (24u) +#define INTC_ICDICPR8_SPTI3_SHIFT (25u) +#define INTC_ICDICPR8_SPEI4_SHIFT (26u) +#define INTC_ICDICPR8_SPRI4_SHIFT (27u) +#define INTC_ICDICPR8_SPTI4_SHIFT (28u) +#define INTC_ICDICPR8_IEBBTD_SHIFT (29u) +#define INTC_ICDICPR8_IEBBTERR_SHIFT (30u) +#define INTC_ICDICPR8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDICPR9_IEBBTV_SHIFT (0u) +#define INTC_ICDICPR9_ISY_SHIFT (1u) +#define INTC_ICDICPR9_IERR_SHIFT (2u) +#define INTC_ICDICPR9_ITARG_SHIFT (3u) +#define INTC_ICDICPR9_ISEC_SHIFT (4u) +#define INTC_ICDICPR9_IBUF_SHIFT (5u) +#define INTC_ICDICPR9_IREADY_SHIFT (6u) +#define INTC_ICDICPR9_FLSTE_SHIFT (7u) +#define INTC_ICDICPR9_FLTENDI_SHIFT (8u) +#define INTC_ICDICPR9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDICPR9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDICPR9_MMC0_SHIFT (11u) +#define INTC_ICDICPR9_MMC1_SHIFT (12u) +#define INTC_ICDICPR9_MMC2_SHIFT (13u) +#define INTC_ICDICPR9_SDHI0_3_SHIFT (14u) +#define INTC_ICDICPR9_SDHI0_0_SHIFT (15u) +#define INTC_ICDICPR9_SDHI0_1_SHIFT (16u) +#define INTC_ICDICPR9_SDHI1_3_SHIFT (17u) +#define INTC_ICDICPR9_SDHI1_0_SHIFT (18u) +#define INTC_ICDICPR9_SDHI1_1_SHIFT (19u) +#define INTC_ICDICPR9_ARM_SHIFT (20u) +#define INTC_ICDICPR9_PRD_SHIFT (21u) +#define INTC_ICDICPR9_CUP_SHIFT (22u) +#define INTC_ICDICPR9_SCUAI0_SHIFT (23u) +#define INTC_ICDICPR9_SCUAI1_SHIFT (24u) +#define INTC_ICDICPR9_SCUFDI0_SHIFT (25u) +#define INTC_ICDICPR9_SCUFDI1_SHIFT (26u) +#define INTC_ICDICPR9_SCUFDI2_SHIFT (27u) +#define INTC_ICDICPR9_SCUFDI3_SHIFT (28u) +#define INTC_ICDICPR9_SCUFUI0_SHIFT (29u) +#define INTC_ICDICPR9_SCUFUI1_SHIFT (30u) +#define INTC_ICDICPR9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDICPR10_SCUFUI3_SHIFT (0u) +#define INTC_ICDICPR10_SCUDVI0_SHIFT (1u) +#define INTC_ICDICPR10_SCUDVI1_SHIFT (2u) +#define INTC_ICDICPR10_SCUDVI2_SHIFT (3u) +#define INTC_ICDICPR10_SCUDVI3_SHIFT (4u) +#define INTC_ICDICPR10_MLB_CINT_SHIFT (5u) +#define INTC_ICDICPR10_MLB_SINT_SHIFT (6u) +#define INTC_ICDICPR10_DRC0_SHIFT (7u) +#define INTC_ICDICPR10_DRC1_SHIFT (8u) +#define INTC_ICDICPR10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDICPR10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDICPR10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDICPR10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDICPR10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDICPR10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDICPR10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDICPR10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDICPR10_ERI0_SHIFT (27u) +#define INTC_ICDICPR10_RXI0_SHIFT (28u) +#define INTC_ICDICPR10_TXI0_SHIFT (29u) +#define INTC_ICDICPR10_TEI0_SHIFT (30u) +#define INTC_ICDICPR10_ERI1_SHIFT (31u) + +#define INTC_ICDICPR11_RXI1_SHIFT (0u) +#define INTC_ICDICPR11_TXI1_SHIFT (1u) +#define INTC_ICDICPR11_TEI1_SHIFT (2u) +#define INTC_ICDICPR11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDICPR11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDICPR11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDICPR11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDICPR11_ETHERI_SHIFT (7u) +#define INTC_ICDICPR11_CEUI_SHIFT (12u) +#define INTC_ICDICPR11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDICPR11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDICPR11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDICPR12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDICPR12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDICPR12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDICPR12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDICPR12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDICPR12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDICPR12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDICPR12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDICPR12_PRRI_SHIFT (8u) +#define INTC_ICDICPR12_IFEI0_SHIFT (9u) +#define INTC_ICDICPR12_OFFI0_SHIFT (10u) +#define INTC_ICDICPR12_PFVEI0_SHIFT (11u) +#define INTC_ICDICPR12_IFEI1_SHIFT (12u) +#define INTC_ICDICPR12_OFFI1_SHIFT (13u) +#define INTC_ICDICPR12_PFVEI1_SHIFT (14u) + +#define INTC_ICDICPR13_TINT0_SHIFT (0u) +#define INTC_ICDICPR13_TINT1_SHIFT (1u) +#define INTC_ICDICPR13_TINT2_SHIFT (2u) +#define INTC_ICDICPR13_TINT3_SHIFT (3u) +#define INTC_ICDICPR13_TINT4_SHIFT (4u) +#define INTC_ICDICPR13_TINT5_SHIFT (5u) +#define INTC_ICDICPR13_TINT6_SHIFT (6u) +#define INTC_ICDICPR13_TINT7_SHIFT (7u) +#define INTC_ICDICPR13_TINT8_SHIFT (8u) +#define INTC_ICDICPR13_TINT9_SHIFT (9u) +#define INTC_ICDICPR13_TINT10_SHIFT (10u) +#define INTC_ICDICPR13_TINT11_SHIFT (11u) +#define INTC_ICDICPR13_TINT12_SHIFT (12u) +#define INTC_ICDICPR13_TINT13_SHIFT (13u) +#define INTC_ICDICPR13_TINT14_SHIFT (14u) +#define INTC_ICDICPR13_TINT15_SHIFT (15u) +#define INTC_ICDICPR13_TINT16_SHIFT (16u) +#define INTC_ICDICPR13_TINT17_SHIFT (17u) +#define INTC_ICDICPR13_TINT18_SHIFT (18u) +#define INTC_ICDICPR13_TINT19_SHIFT (19u) +#define INTC_ICDICPR13_TINT20_SHIFT (20u) +#define INTC_ICDICPR13_TINT21_SHIFT (21u) +#define INTC_ICDICPR13_TINT22_SHIFT (22u) +#define INTC_ICDICPR13_TINT23_SHIFT (23u) +#define INTC_ICDICPR13_TINT24_SHIFT (24u) +#define INTC_ICDICPR13_TINT25_SHIFT (25u) +#define INTC_ICDICPR13_TINT26_SHIFT (26u) +#define INTC_ICDICPR13_TINT27_SHIFT (27u) +#define INTC_ICDICPR13_TINT28_SHIFT (28u) +#define INTC_ICDICPR13_TINT29_SHIFT (29u) +#define INTC_ICDICPR13_TINT30_SHIFT (30u) +#define INTC_ICDICPR13_TINT31_SHIFT (31u) + +#define INTC_ICDICPR14_TINT32_SHIFT (0u) +#define INTC_ICDICPR14_TINT33_SHIFT (1u) +#define INTC_ICDICPR14_TINT34_SHIFT (2u) +#define INTC_ICDICPR14_TINT35_SHIFT (3u) +#define INTC_ICDICPR14_TINT36_SHIFT (4u) +#define INTC_ICDICPR14_TINT37_SHIFT (5u) +#define INTC_ICDICPR14_TINT38_SHIFT (6u) +#define INTC_ICDICPR14_TINT39_SHIFT (7u) +#define INTC_ICDICPR14_TINT40_SHIFT (8u) +#define INTC_ICDICPR14_TINT41_SHIFT (9u) +#define INTC_ICDICPR14_TINT42_SHIFT (10u) +#define INTC_ICDICPR14_TINT43_SHIFT (11u) +#define INTC_ICDICPR14_TINT44_SHIFT (12u) +#define INTC_ICDICPR14_TINT45_SHIFT (13u) +#define INTC_ICDICPR14_TINT46_SHIFT (14u) +#define INTC_ICDICPR14_TINT47_SHIFT (15u) +#define INTC_ICDICPR14_TINT48_SHIFT (16u) +#define INTC_ICDICPR14_TINT49_SHIFT (17u) +#define INTC_ICDICPR14_TINT50_SHIFT (18u) +#define INTC_ICDICPR14_TINT51_SHIFT (19u) +#define INTC_ICDICPR14_TINT52_SHIFT (20u) +#define INTC_ICDICPR14_TINT53_SHIFT (21u) +#define INTC_ICDICPR14_TINT54_SHIFT (22u) +#define INTC_ICDICPR14_TINT55_SHIFT (23u) +#define INTC_ICDICPR14_TINT56_SHIFT (24u) +#define INTC_ICDICPR14_TINT57_SHIFT (25u) +#define INTC_ICDICPR14_TINT58_SHIFT (26u) +#define INTC_ICDICPR14_TINT59_SHIFT (27u) +#define INTC_ICDICPR14_TINT60_SHIFT (28u) +#define INTC_ICDICPR14_TINT61_SHIFT (29u) +#define INTC_ICDICPR14_TINT62_SHIFT (30u) +#define INTC_ICDICPR14_TINT63_SHIFT (31u) + +#define INTC_ICDICPR15_TINT64_SHIFT (0u) +#define INTC_ICDICPR15_TINT65_SHIFT (1u) +#define INTC_ICDICPR15_TINT66_SHIFT (2u) +#define INTC_ICDICPR15_TINT67_SHIFT (3u) +#define INTC_ICDICPR15_TINT68_SHIFT (4u) +#define INTC_ICDICPR15_TINT69_SHIFT (5u) +#define INTC_ICDICPR15_TINT70_SHIFT (6u) +#define INTC_ICDICPR15_TINT71_SHIFT (7u) +#define INTC_ICDICPR15_TINT72_SHIFT (8u) +#define INTC_ICDICPR15_TINT73_SHIFT (9u) +#define INTC_ICDICPR15_TINT74_SHIFT (10u) +#define INTC_ICDICPR15_TINT75_SHIFT (11u) +#define INTC_ICDICPR15_TINT76_SHIFT (12u) +#define INTC_ICDICPR15_TINT77_SHIFT (13u) +#define INTC_ICDICPR15_TINT78_SHIFT (14u) +#define INTC_ICDICPR15_TINT79_SHIFT (15u) +#define INTC_ICDICPR15_TINT80_SHIFT (16u) +#define INTC_ICDICPR15_TINT81_SHIFT (17u) +#define INTC_ICDICPR15_TINT82_SHIFT (18u) +#define INTC_ICDICPR15_TINT83_SHIFT (19u) +#define INTC_ICDICPR15_TINT84_SHIFT (20u) +#define INTC_ICDICPR15_TINT85_SHIFT (21u) +#define INTC_ICDICPR15_TINT86_SHIFT (22u) +#define INTC_ICDICPR15_TINT87_SHIFT (23u) +#define INTC_ICDICPR15_TINT88_SHIFT (24u) +#define INTC_ICDICPR15_TINT89_SHIFT (25u) +#define INTC_ICDICPR15_TINT90_SHIFT (26u) +#define INTC_ICDICPR15_TINT91_SHIFT (27u) +#define INTC_ICDICPR15_TINT92_SHIFT (28u) +#define INTC_ICDICPR15_TINT93_SHIFT (29u) +#define INTC_ICDICPR15_TINT94_SHIFT (30u) +#define INTC_ICDICPR15_TINT95_SHIFT (31u) + +#define INTC_ICDICPR16_TINT96_SHIFT (0u) +#define INTC_ICDICPR16_TINT97_SHIFT (1u) +#define INTC_ICDICPR16_TINT98_SHIFT (2u) +#define INTC_ICDICPR16_TINT99_SHIFT (3u) +#define INTC_ICDICPR16_TINT100_SHIFT (4u) +#define INTC_ICDICPR16_TINT101_SHIFT (5u) +#define INTC_ICDICPR16_TINT102_SHIFT (6u) +#define INTC_ICDICPR16_TINT103_SHIFT (7u) +#define INTC_ICDICPR16_TINT104_SHIFT (8u) +#define INTC_ICDICPR16_TINT105_SHIFT (9u) +#define INTC_ICDICPR16_TINT106_SHIFT (10u) +#define INTC_ICDICPR16_TINT107_SHIFT (11u) +#define INTC_ICDICPR16_TINT108_SHIFT (12u) +#define INTC_ICDICPR16_TINT109_SHIFT (13u) +#define INTC_ICDICPR16_TINT110_SHIFT (14u) +#define INTC_ICDICPR16_TINT111_SHIFT (15u) +#define INTC_ICDICPR16_TINT112_SHIFT (16u) +#define INTC_ICDICPR16_TINT113_SHIFT (17u) +#define INTC_ICDICPR16_TINT114_SHIFT (18u) +#define INTC_ICDICPR16_TINT115_SHIFT (19u) +#define INTC_ICDICPR16_TINT116_SHIFT (20u) +#define INTC_ICDICPR16_TINT117_SHIFT (21u) +#define INTC_ICDICPR16_TINT118_SHIFT (22u) +#define INTC_ICDICPR16_TINT119_SHIFT (23u) +#define INTC_ICDICPR16_TINT120_SHIFT (24u) +#define INTC_ICDICPR16_TINT121_SHIFT (25u) +#define INTC_ICDICPR16_TINT122_SHIFT (26u) +#define INTC_ICDICPR16_TINT123_SHIFT (27u) +#define INTC_ICDICPR16_TINT124_SHIFT (28u) +#define INTC_ICDICPR16_TINT125_SHIFT (29u) +#define INTC_ICDICPR16_TINT126_SHIFT (30u) +#define INTC_ICDICPR16_TINT127_SHIFT (31u) + +#define INTC_ICDICPR17_TINT128_SHIFT (0u) +#define INTC_ICDICPR17_TINT129_SHIFT (1u) +#define INTC_ICDICPR17_TINT130_SHIFT (2u) +#define INTC_ICDICPR17_TINT131_SHIFT (3u) +#define INTC_ICDICPR17_TINT132_SHIFT (4u) +#define INTC_ICDICPR17_TINT133_SHIFT (5u) +#define INTC_ICDICPR17_TINT134_SHIFT (6u) +#define INTC_ICDICPR17_TINT135_SHIFT (7u) +#define INTC_ICDICPR17_TINT136_SHIFT (8u) +#define INTC_ICDICPR17_TINT137_SHIFT (9u) +#define INTC_ICDICPR17_TINT138_SHIFT (10u) +#define INTC_ICDICPR17_TINT139_SHIFT (11u) +#define INTC_ICDICPR17_TINT140_SHIFT (12u) +#define INTC_ICDICPR17_TINT141_SHIFT (13u) +#define INTC_ICDICPR17_TINT142_SHIFT (14u) +#define INTC_ICDICPR17_TINT143_SHIFT (15u) +#define INTC_ICDICPR17_TINT144_SHIFT (16u) +#define INTC_ICDICPR17_TINT145_SHIFT (17u) +#define INTC_ICDICPR17_TINT146_SHIFT (18u) +#define INTC_ICDICPR17_TINT147_SHIFT (19u) +#define INTC_ICDICPR17_TINT148_SHIFT (20u) +#define INTC_ICDICPR17_TINT149_SHIFT (21u) +#define INTC_ICDICPR17_TINT150_SHIFT (22u) +#define INTC_ICDICPR17_TINT151_SHIFT (23u) +#define INTC_ICDICPR17_TINT152_SHIFT (24u) +#define INTC_ICDICPR17_TINT153_SHIFT (25u) +#define INTC_ICDICPR17_TINT154_SHIFT (26u) +#define INTC_ICDICPR17_TINT155_SHIFT (27u) +#define INTC_ICDICPR17_TINT156_SHIFT (28u) +#define INTC_ICDICPR17_TINT157_SHIFT (29u) +#define INTC_ICDICPR17_TINT158_SHIFT (30u) +#define INTC_ICDICPR17_TINT159_SHIFT (31u) + +#define INTC_ICDICPR18_TINT160_SHIFT (0u) +#define INTC_ICDICPR18_TINT161_SHIFT (1u) +#define INTC_ICDICPR18_TINT162_SHIFT (2u) +#define INTC_ICDICPR18_TINT163_SHIFT (3u) +#define INTC_ICDICPR18_TINT164_SHIFT (4u) +#define INTC_ICDICPR18_TINT165_SHIFT (5u) +#define INTC_ICDICPR18_TINT166_SHIFT (6u) +#define INTC_ICDICPR18_TINT167_SHIFT (7u) +#define INTC_ICDICPR18_TINT168_SHIFT (8u) +#define INTC_ICDICPR18_TINT169_SHIFT (9u) +#define INTC_ICDICPR18_TINT170_SHIFT (10u) + +#define INTC_ICDABR0_SW0_SHIFT (0u) +#define INTC_ICDABR0_SW1_SHIFT (1u) +#define INTC_ICDABR0_SW2_SHIFT (2u) +#define INTC_ICDABR0_SW3_SHIFT (3u) +#define INTC_ICDABR0_SW4_SHIFT (4u) +#define INTC_ICDABR0_SW5_SHIFT (5u) +#define INTC_ICDABR0_SW6_SHIFT (6u) +#define INTC_ICDABR0_SW7_SHIFT (7u) +#define INTC_ICDABR0_SW8_SHIFT (8u) +#define INTC_ICDABR0_SW9_SHIFT (9u) +#define INTC_ICDABR0_SW10_SHIFT (10u) +#define INTC_ICDABR0_SW11_SHIFT (11u) +#define INTC_ICDABR0_SW12_SHIFT (12u) +#define INTC_ICDABR0_SW13_SHIFT (13u) +#define INTC_ICDABR0_SW14_SHIFT (14u) +#define INTC_ICDABR0_SW15_SHIFT (15u) +#define INTC_ICDABR0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDABR0_COMMRX0_SHIFT (17u) +#define INTC_ICDABR0_COMMTX0_SHIFT (18u) +#define INTC_ICDABR0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDABR1_IRQ0_SHIFT (0u) +#define INTC_ICDABR1_IRQ1_SHIFT (1u) +#define INTC_ICDABR1_IRQ2_SHIFT (2u) +#define INTC_ICDABR1_IRQ3_SHIFT (3u) +#define INTC_ICDABR1_IRQ4_SHIFT (4u) +#define INTC_ICDABR1_IRQ5_SHIFT (5u) +#define INTC_ICDABR1_IRQ6_SHIFT (6u) +#define INTC_ICDABR1_IRQ7_SHIFT (7u) +#define INTC_ICDABR1_PL310ERR_SHIFT (8u) +#define INTC_ICDABR1_DMAINT0_SHIFT (9u) +#define INTC_ICDABR1_DMAINT1_SHIFT (10u) +#define INTC_ICDABR1_DMAINT2_SHIFT (11u) +#define INTC_ICDABR1_DMAINT3_SHIFT (12u) +#define INTC_ICDABR1_DMAINT4_SHIFT (13u) +#define INTC_ICDABR1_DMAINT5_SHIFT (14u) +#define INTC_ICDABR1_DMAINT6_SHIFT (15u) +#define INTC_ICDABR1_DMAINT7_SHIFT (16u) +#define INTC_ICDABR1_DMAINT8_SHIFT (17u) +#define INTC_ICDABR1_DMAINT9_SHIFT (18u) +#define INTC_ICDABR1_DMAINT10_SHIFT (19u) +#define INTC_ICDABR1_DMAINT11_SHIFT (20u) +#define INTC_ICDABR1_DMAINT12_SHIFT (21u) +#define INTC_ICDABR1_DMAINT13_SHIFT (22u) +#define INTC_ICDABR1_DMAINT14_SHIFT (23u) +#define INTC_ICDABR1_DMAINT15_SHIFT (24u) +#define INTC_ICDABR1_DMAERR_SHIFT (25u) + +#define INTC_ICDABR2_USBI0_SHIFT (9u) +#define INTC_ICDABR2_USBI1_SHIFT (10u) +#define INTC_ICDABR2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDABR2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDABR2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDABR2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDABR2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDABR2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDABR2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDABR2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDABR2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDABR2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDABR2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDABR2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDABR2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDABR2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDABR2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDABR2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDABR2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDABR2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDABR2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDABR2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDABR2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDABR3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDABR3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDABR3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDABR3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDABR3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDABR3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDABR3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDABR3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDABR3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDABR3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDABR3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDABR3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDABR3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDABR3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDABR3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDABR3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDABR3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDABR3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDABR3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDABR3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDABR3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDABR3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDABR3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDABR3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDABR3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDABR3_IMRDI_SHIFT (27u) +#define INTC_ICDABR3_IMR2I0_SHIFT (28u) +#define INTC_ICDABR3_IMR2I1_SHIFT (29u) +#define INTC_ICDABR3_JEDI_SHIFT (30u) +#define INTC_ICDABR3_JDTI_SHIFT (31u) + +#define INTC_ICDABR4_CMP0_SHIFT (0u) +#define INTC_ICDABR4_CMP1_SHIFT (1u) +#define INTC_ICDABR4_INT0_SHIFT (2u) +#define INTC_ICDABR4_INT1_SHIFT (3u) +#define INTC_ICDABR4_INT2_SHIFT (4u) +#define INTC_ICDABR4_INT3_SHIFT (5u) +#define INTC_ICDABR4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDABR4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDABR4_CMI_SHIFT (8u) +#define INTC_ICDABR4_WTOUT_SHIFT (9u) +#define INTC_ICDABR4_ITI_SHIFT (10u) +#define INTC_ICDABR4_TGI0A_SHIFT (11u) +#define INTC_ICDABR4_TGI0B_SHIFT (12u) +#define INTC_ICDABR4_TGI0C_SHIFT (13u) +#define INTC_ICDABR4_TGI0D_SHIFT (14u) +#define INTC_ICDABR4_TGI0V_SHIFT (15u) +#define INTC_ICDABR4_TGI0E_SHIFT (16u) +#define INTC_ICDABR4_TGI0F_SHIFT (17u) +#define INTC_ICDABR4_TGI1A_SHIFT (18u) +#define INTC_ICDABR4_TGI1B_SHIFT (19u) +#define INTC_ICDABR4_TGI1V_SHIFT (20u) +#define INTC_ICDABR4_TGI1U_SHIFT (21u) +#define INTC_ICDABR4_TGI2A_SHIFT (22u) +#define INTC_ICDABR4_TGI2B_SHIFT (23u) +#define INTC_ICDABR4_TGI2V_SHIFT (24u) +#define INTC_ICDABR4_TGI2U_SHIFT (25u) +#define INTC_ICDABR4_TGI3A_SHIFT (26u) +#define INTC_ICDABR4_TGI3B_SHIFT (27u) +#define INTC_ICDABR4_TGI3C_SHIFT (28u) +#define INTC_ICDABR4_TGI3D_SHIFT (29u) +#define INTC_ICDABR4_TGI3V_SHIFT (30u) +#define INTC_ICDABR4_TGI4A_SHIFT (31u) + +#define INTC_ICDABR5_TGI4B_SHIFT (0u) +#define INTC_ICDABR5_TGI4C_SHIFT (1u) +#define INTC_ICDABR5_TGI4D_SHIFT (2u) +#define INTC_ICDABR5_TGI4V_SHIFT (3u) +#define INTC_ICDABR5_CMI1_SHIFT (4u) +#define INTC_ICDABR5_CMI2_SHIFT (5u) +#define INTC_ICDABR5_SGDEI0_SHIFT (6u) +#define INTC_ICDABR5_SGDEI1_SHIFT (7u) +#define INTC_ICDABR5_SGDEI2_SHIFT (8u) +#define INTC_ICDABR5_SGDEI3_SHIFT (9u) +#define INTC_ICDABR5_ADI_SHIFT (10u) +#define INTC_ICDABR5_LMTI_SHIFT (11u) +#define INTC_ICDABR5_SSII0_SHIFT (12u) +#define INTC_ICDABR5_SSIRXI0_SHIFT (13u) +#define INTC_ICDABR5_SSITXI0_SHIFT (14u) +#define INTC_ICDABR5_SSII1_SHIFT (15u) +#define INTC_ICDABR5_SSIRXI1_SHIFT (16u) +#define INTC_ICDABR5_SSITXI1_SHIFT (17u) +#define INTC_ICDABR5_SSII2_SHIFT (18u) +#define INTC_ICDABR5_SSIRTI2_SHIFT (19u) +#define INTC_ICDABR5_SSII3_SHIFT (20u) +#define INTC_ICDABR5_SSIRXI3_SHIFT (21u) +#define INTC_ICDABR5_SSITXI3_SHIFT (22u) +#define INTC_ICDABR5_SSII4_SHIFT (23u) +#define INTC_ICDABR5_SSIRTI4_SHIFT (24u) +#define INTC_ICDABR5_SSII5_SHIFT (25u) +#define INTC_ICDABR5_SSIRXI5_SHIFT (26u) +#define INTC_ICDABR5_SSITXI5_SHIFT (27u) +#define INTC_ICDABR5_SPDIFI_SHIFT (28u) +#define INTC_ICDABR5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDABR5_INTIICRI0_SHIFT (30u) +#define INTC_ICDABR5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDABR6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDABR6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDABR6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDABR6_INTIICALI0_SHIFT (3u) +#define INTC_ICDABR6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDABR6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDABR6_INTIICRI1_SHIFT (6u) +#define INTC_ICDABR6_INTIICTI1_SHIFT (7u) +#define INTC_ICDABR6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDABR6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDABR6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDABR6_INTIICALI1_SHIFT (11u) +#define INTC_ICDABR6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDABR6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDABR6_INTIICRI2_SHIFT (14u) +#define INTC_ICDABR6_INTIICTI2_SHIFT (15u) +#define INTC_ICDABR6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDABR6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDABR6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDABR6_INTIICALI2_SHIFT (19u) +#define INTC_ICDABR6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDABR6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDABR6_INTIICRI3_SHIFT (22u) +#define INTC_ICDABR6_INTIICTI3_SHIFT (23u) +#define INTC_ICDABR6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDABR6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDABR6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDABR6_INTIICALI3_SHIFT (27u) +#define INTC_ICDABR6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDABR6_BRI0_SHIFT (29u) +#define INTC_ICDABR6_ERI0_SHIFT (30u) +#define INTC_ICDABR6_RXI0_SHIFT (31u) + +#define INTC_ICDABR7_TXI0_SHIFT (0u) +#define INTC_ICDABR7_BRI1_SHIFT (1u) +#define INTC_ICDABR7_ERI1_SHIFT (2u) +#define INTC_ICDABR7_RXI1_SHIFT (3u) +#define INTC_ICDABR7_TXI1_SHIFT (4u) +#define INTC_ICDABR7_BRI2_SHIFT (5u) +#define INTC_ICDABR7_ERI2_SHIFT (6u) +#define INTC_ICDABR7_RXI2_SHIFT (7u) +#define INTC_ICDABR7_TXI2_SHIFT (8u) +#define INTC_ICDABR7_BRI3_SHIFT (9u) +#define INTC_ICDABR7_ERI3_SHIFT (10u) +#define INTC_ICDABR7_RXI3_SHIFT (11u) +#define INTC_ICDABR7_TXI3_SHIFT (12u) +#define INTC_ICDABR7_BRI4_SHIFT (13u) +#define INTC_ICDABR7_ERI4_SHIFT (14u) +#define INTC_ICDABR7_RXI4_SHIFT (15u) +#define INTC_ICDABR7_TXI4_SHIFT (16u) +#define INTC_ICDABR7_BRI5_SHIFT (17u) +#define INTC_ICDABR7_ERI5_SHIFT (18u) +#define INTC_ICDABR7_RXI5_SHIFT (19u) +#define INTC_ICDABR7_TXI5_SHIFT (20u) +#define INTC_ICDABR7_BRI6_SHIFT (21u) +#define INTC_ICDABR7_ERI6_SHIFT (22u) +#define INTC_ICDABR7_RXI6_SHIFT (23u) +#define INTC_ICDABR7_TXI6_SHIFT (24u) +#define INTC_ICDABR7_BRI7_SHIFT (25u) +#define INTC_ICDABR7_ERI7_SHIFT (26u) +#define INTC_ICDABR7_RXI7_SHIFT (27u) +#define INTC_ICDABR7_TXI7_SHIFT (28u) +#define INTC_ICDABR7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDABR7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDABR7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDABR8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDABR8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDABR8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDABR8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDABR8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDABR8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDABR8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDABR8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDABR8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDABR8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDABR8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDABR8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDABR8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDABR8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDABR8_SPEI0_SHIFT (14u) +#define INTC_ICDABR8_SPRI0_SHIFT (15u) +#define INTC_ICDABR8_SPTI0_SHIFT (16u) +#define INTC_ICDABR8_SPEI1_SHIFT (17u) +#define INTC_ICDABR8_SPRI1_SHIFT (18u) +#define INTC_ICDABR8_SPTI1_SHIFT (19u) +#define INTC_ICDABR8_SPEI2_SHIFT (20u) +#define INTC_ICDABR8_SPRI2_SHIFT (21u) +#define INTC_ICDABR8_SPTI2_SHIFT (22u) +#define INTC_ICDABR8_SPEI3_SHIFT (23u) +#define INTC_ICDABR8_SPRI3_SHIFT (24u) +#define INTC_ICDABR8_SPTI3_SHIFT (25u) +#define INTC_ICDABR8_SPEI4_SHIFT (26u) +#define INTC_ICDABR8_SPRI4_SHIFT (27u) +#define INTC_ICDABR8_SPTI4_SHIFT (28u) +#define INTC_ICDABR8_IEBBTD_SHIFT (29u) +#define INTC_ICDABR8_IEBBTERR_SHIFT (30u) +#define INTC_ICDABR8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDABR9_IEBBTV_SHIFT (0u) +#define INTC_ICDABR9_ISY_SHIFT (1u) +#define INTC_ICDABR9_IERR_SHIFT (2u) +#define INTC_ICDABR9_ITARG_SHIFT (3u) +#define INTC_ICDABR9_ISEC_SHIFT (4u) +#define INTC_ICDABR9_IBUF_SHIFT (5u) +#define INTC_ICDABR9_IREADY_SHIFT (6u) +#define INTC_ICDABR9_FLSTE_SHIFT (7u) +#define INTC_ICDABR9_FLTENDI_SHIFT (8u) +#define INTC_ICDABR9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDABR9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDABR9_MMC0_SHIFT (11u) +#define INTC_ICDABR9_MMC1_SHIFT (12u) +#define INTC_ICDABR9_MMC2_SHIFT (13u) +#define INTC_ICDABR9_SDHI0_3_SHIFT (14u) +#define INTC_ICDABR9_SDHI0_0_SHIFT (15u) +#define INTC_ICDABR9_SDHI0_1_SHIFT (16u) +#define INTC_ICDABR9_SDHI1_3_SHIFT (17u) +#define INTC_ICDABR9_SDHI1_0_SHIFT (18u) +#define INTC_ICDABR9_SDHI1_1_SHIFT (19u) +#define INTC_ICDABR9_ARM_SHIFT (20u) +#define INTC_ICDABR9_PRD_SHIFT (21u) +#define INTC_ICDABR9_CUP_SHIFT (22u) +#define INTC_ICDABR9_SCUAI0_SHIFT (23u) +#define INTC_ICDABR9_SCUAI1_SHIFT (24u) +#define INTC_ICDABR9_SCUFDI0_SHIFT (25u) +#define INTC_ICDABR9_SCUFDI1_SHIFT (26u) +#define INTC_ICDABR9_SCUFDI2_SHIFT (27u) +#define INTC_ICDABR9_SCUFDI3_SHIFT (28u) +#define INTC_ICDABR9_SCUFUI0_SHIFT (29u) +#define INTC_ICDABR9_SCUFUI1_SHIFT (30u) +#define INTC_ICDABR9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDABR10_SCUFUI3_SHIFT (0u) +#define INTC_ICDABR10_SCUDVI0_SHIFT (1u) +#define INTC_ICDABR10_SCUDVI1_SHIFT (2u) +#define INTC_ICDABR10_SCUDVI2_SHIFT (3u) +#define INTC_ICDABR10_SCUDVI3_SHIFT (4u) +#define INTC_ICDABR10_MLB_CINT_SHIFT (5u) +#define INTC_ICDABR10_MLB_SINT_SHIFT (6u) +#define INTC_ICDABR10_DRC0_SHIFT (7u) +#define INTC_ICDABR10_DRC1_SHIFT (8u) +#define INTC_ICDABR10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDABR10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDABR10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDABR10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDABR10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDABR10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDABR10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDABR10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDABR10_ERI0_SHIFT (27u) +#define INTC_ICDABR10_RXI0_SHIFT (28u) +#define INTC_ICDABR10_TXI0_SHIFT (29u) +#define INTC_ICDABR10_TEI0_SHIFT (30u) +#define INTC_ICDABR10_ERI1_SHIFT (31u) + +#define INTC_ICDABR11_RXI1_SHIFT (0u) +#define INTC_ICDABR11_TXI1_SHIFT (1u) +#define INTC_ICDABR11_TEI1_SHIFT (2u) +#define INTC_ICDABR11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDABR11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDABR11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDABR11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDABR11_ETHERI_SHIFT (7u) +#define INTC_ICDABR11_CEUI_SHIFT (12u) +#define INTC_ICDABR11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDABR11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDABR11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDABR12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDABR12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDABR12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDABR12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDABR12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDABR12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDABR12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDABR12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDABR12_PRRI_SHIFT (8u) +#define INTC_ICDABR12_IFEI0_SHIFT (9u) +#define INTC_ICDABR12_OFFI0_SHIFT (10u) +#define INTC_ICDABR12_PFVEI0_SHIFT (11u) +#define INTC_ICDABR12_IFEI1_SHIFT (12u) +#define INTC_ICDABR12_OFFI1_SHIFT (13u) +#define INTC_ICDABR12_PFVEI1_SHIFT (14u) + +#define INTC_ICDABR13_TINT0_SHIFT (0u) +#define INTC_ICDABR13_TINT1_SHIFT (1u) +#define INTC_ICDABR13_TINT2_SHIFT (2u) +#define INTC_ICDABR13_TINT3_SHIFT (3u) +#define INTC_ICDABR13_TINT4_SHIFT (4u) +#define INTC_ICDABR13_TINT5_SHIFT (5u) +#define INTC_ICDABR13_TINT6_SHIFT (6u) +#define INTC_ICDABR13_TINT7_SHIFT (7u) +#define INTC_ICDABR13_TINT8_SHIFT (8u) +#define INTC_ICDABR13_TINT9_SHIFT (9u) +#define INTC_ICDABR13_TINT10_SHIFT (10u) +#define INTC_ICDABR13_TINT11_SHIFT (11u) +#define INTC_ICDABR13_TINT12_SHIFT (12u) +#define INTC_ICDABR13_TINT13_SHIFT (13u) +#define INTC_ICDABR13_TINT14_SHIFT (14u) +#define INTC_ICDABR13_TINT15_SHIFT (15u) +#define INTC_ICDABR13_TINT16_SHIFT (16u) +#define INTC_ICDABR13_TINT17_SHIFT (17u) +#define INTC_ICDABR13_TINT18_SHIFT (18u) +#define INTC_ICDABR13_TINT19_SHIFT (19u) +#define INTC_ICDABR13_TINT20_SHIFT (20u) +#define INTC_ICDABR13_TINT21_SHIFT (21u) +#define INTC_ICDABR13_TINT22_SHIFT (22u) +#define INTC_ICDABR13_TINT23_SHIFT (23u) +#define INTC_ICDABR13_TINT24_SHIFT (24u) +#define INTC_ICDABR13_TINT25_SHIFT (25u) +#define INTC_ICDABR13_TINT26_SHIFT (26u) +#define INTC_ICDABR13_TINT27_SHIFT (27u) +#define INTC_ICDABR13_TINT28_SHIFT (28u) +#define INTC_ICDABR13_TINT29_SHIFT (29u) +#define INTC_ICDABR13_TINT30_SHIFT (30u) +#define INTC_ICDABR13_TINT31_SHIFT (31u) + +#define INTC_ICDABR14_TINT32_SHIFT (0u) +#define INTC_ICDABR14_TINT33_SHIFT (1u) +#define INTC_ICDABR14_TINT34_SHIFT (2u) +#define INTC_ICDABR14_TINT35_SHIFT (3u) +#define INTC_ICDABR14_TINT36_SHIFT (4u) +#define INTC_ICDABR14_TINT37_SHIFT (5u) +#define INTC_ICDABR14_TINT38_SHIFT (6u) +#define INTC_ICDABR14_TINT39_SHIFT (7u) +#define INTC_ICDABR14_TINT40_SHIFT (8u) +#define INTC_ICDABR14_TINT41_SHIFT (9u) +#define INTC_ICDABR14_TINT42_SHIFT (10u) +#define INTC_ICDABR14_TINT43_SHIFT (11u) +#define INTC_ICDABR14_TINT44_SHIFT (12u) +#define INTC_ICDABR14_TINT45_SHIFT (13u) +#define INTC_ICDABR14_TINT46_SHIFT (14u) +#define INTC_ICDABR14_TINT47_SHIFT (15u) +#define INTC_ICDABR14_TINT48_SHIFT (16u) +#define INTC_ICDABR14_TINT49_SHIFT (17u) +#define INTC_ICDABR14_TINT50_SHIFT (18u) +#define INTC_ICDABR14_TINT51_SHIFT (19u) +#define INTC_ICDABR14_TINT52_SHIFT (20u) +#define INTC_ICDABR14_TINT53_SHIFT (21u) +#define INTC_ICDABR14_TINT54_SHIFT (22u) +#define INTC_ICDABR14_TINT55_SHIFT (23u) +#define INTC_ICDABR14_TINT56_SHIFT (24u) +#define INTC_ICDABR14_TINT57_SHIFT (25u) +#define INTC_ICDABR14_TINT58_SHIFT (26u) +#define INTC_ICDABR14_TINT59_SHIFT (27u) +#define INTC_ICDABR14_TINT60_SHIFT (28u) +#define INTC_ICDABR14_TINT61_SHIFT (29u) +#define INTC_ICDABR14_TINT62_SHIFT (30u) +#define INTC_ICDABR14_TINT63_SHIFT (31u) + +#define INTC_ICDABR15_TINT64_SHIFT (0u) +#define INTC_ICDABR15_TINT65_SHIFT (1u) +#define INTC_ICDABR15_TINT66_SHIFT (2u) +#define INTC_ICDABR15_TINT67_SHIFT (3u) +#define INTC_ICDABR15_TINT68_SHIFT (4u) +#define INTC_ICDABR15_TINT69_SHIFT (5u) +#define INTC_ICDABR15_TINT70_SHIFT (6u) +#define INTC_ICDABR15_TINT71_SHIFT (7u) +#define INTC_ICDABR15_TINT72_SHIFT (8u) +#define INTC_ICDABR15_TINT73_SHIFT (9u) +#define INTC_ICDABR15_TINT74_SHIFT (10u) +#define INTC_ICDABR15_TINT75_SHIFT (11u) +#define INTC_ICDABR15_TINT76_SHIFT (12u) +#define INTC_ICDABR15_TINT77_SHIFT (13u) +#define INTC_ICDABR15_TINT78_SHIFT (14u) +#define INTC_ICDABR15_TINT79_SHIFT (15u) +#define INTC_ICDABR15_TINT80_SHIFT (16u) +#define INTC_ICDABR15_TINT81_SHIFT (17u) +#define INTC_ICDABR15_TINT82_SHIFT (18u) +#define INTC_ICDABR15_TINT83_SHIFT (19u) +#define INTC_ICDABR15_TINT84_SHIFT (20u) +#define INTC_ICDABR15_TINT85_SHIFT (21u) +#define INTC_ICDABR15_TINT86_SHIFT (22u) +#define INTC_ICDABR15_TINT87_SHIFT (23u) +#define INTC_ICDABR15_TINT88_SHIFT (24u) +#define INTC_ICDABR15_TINT89_SHIFT (25u) +#define INTC_ICDABR15_TINT90_SHIFT (26u) +#define INTC_ICDABR15_TINT91_SHIFT (27u) +#define INTC_ICDABR15_TINT92_SHIFT (28u) +#define INTC_ICDABR15_TINT93_SHIFT (29u) +#define INTC_ICDABR15_TINT94_SHIFT (30u) +#define INTC_ICDABR15_TINT95_SHIFT (31u) + +#define INTC_ICDABR16_TINT96_SHIFT (0u) +#define INTC_ICDABR16_TINT97_SHIFT (1u) +#define INTC_ICDABR16_TINT98_SHIFT (2u) +#define INTC_ICDABR16_TINT99_SHIFT (3u) +#define INTC_ICDABR16_TINT100_SHIFT (4u) +#define INTC_ICDABR16_TINT101_SHIFT (5u) +#define INTC_ICDABR16_TINT102_SHIFT (6u) +#define INTC_ICDABR16_TINT103_SHIFT (7u) +#define INTC_ICDABR16_TINT104_SHIFT (8u) +#define INTC_ICDABR16_TINT105_SHIFT (9u) +#define INTC_ICDABR16_TINT106_SHIFT (10u) +#define INTC_ICDABR16_TINT107_SHIFT (11u) +#define INTC_ICDABR16_TINT108_SHIFT (12u) +#define INTC_ICDABR16_TINT109_SHIFT (13u) +#define INTC_ICDABR16_TINT110_SHIFT (14u) +#define INTC_ICDABR16_TINT111_SHIFT (15u) +#define INTC_ICDABR16_TINT112_SHIFT (16u) +#define INTC_ICDABR16_TINT113_SHIFT (17u) +#define INTC_ICDABR16_TINT114_SHIFT (18u) +#define INTC_ICDABR16_TINT115_SHIFT (19u) +#define INTC_ICDABR16_TINT116_SHIFT (20u) +#define INTC_ICDABR16_TINT117_SHIFT (21u) +#define INTC_ICDABR16_TINT118_SHIFT (22u) +#define INTC_ICDABR16_TINT119_SHIFT (23u) +#define INTC_ICDABR16_TINT120_SHIFT (24u) +#define INTC_ICDABR16_TINT121_SHIFT (25u) +#define INTC_ICDABR16_TINT122_SHIFT (26u) +#define INTC_ICDABR16_TINT123_SHIFT (27u) +#define INTC_ICDABR16_TINT124_SHIFT (28u) +#define INTC_ICDABR16_TINT125_SHIFT (29u) +#define INTC_ICDABR16_TINT126_SHIFT (30u) +#define INTC_ICDABR16_TINT127_SHIFT (31u) + +#define INTC_ICDABR17_TINT128_SHIFT (0u) +#define INTC_ICDABR17_TINT129_SHIFT (1u) +#define INTC_ICDABR17_TINT130_SHIFT (2u) +#define INTC_ICDABR17_TINT131_SHIFT (3u) +#define INTC_ICDABR17_TINT132_SHIFT (4u) +#define INTC_ICDABR17_TINT133_SHIFT (5u) +#define INTC_ICDABR17_TINT134_SHIFT (6u) +#define INTC_ICDABR17_TINT135_SHIFT (7u) +#define INTC_ICDABR17_TINT136_SHIFT (8u) +#define INTC_ICDABR17_TINT137_SHIFT (9u) +#define INTC_ICDABR17_TINT138_SHIFT (10u) +#define INTC_ICDABR17_TINT139_SHIFT (11u) +#define INTC_ICDABR17_TINT140_SHIFT (12u) +#define INTC_ICDABR17_TINT141_SHIFT (13u) +#define INTC_ICDABR17_TINT142_SHIFT (14u) +#define INTC_ICDABR17_TINT143_SHIFT (15u) +#define INTC_ICDABR17_TINT144_SHIFT (16u) +#define INTC_ICDABR17_TINT145_SHIFT (17u) +#define INTC_ICDABR17_TINT146_SHIFT (18u) +#define INTC_ICDABR17_TINT147_SHIFT (19u) +#define INTC_ICDABR17_TINT148_SHIFT (20u) +#define INTC_ICDABR17_TINT149_SHIFT (21u) +#define INTC_ICDABR17_TINT150_SHIFT (22u) +#define INTC_ICDABR17_TINT151_SHIFT (23u) +#define INTC_ICDABR17_TINT152_SHIFT (24u) +#define INTC_ICDABR17_TINT153_SHIFT (25u) +#define INTC_ICDABR17_TINT154_SHIFT (26u) +#define INTC_ICDABR17_TINT155_SHIFT (27u) +#define INTC_ICDABR17_TINT156_SHIFT (28u) +#define INTC_ICDABR17_TINT157_SHIFT (29u) +#define INTC_ICDABR17_TINT158_SHIFT (30u) +#define INTC_ICDABR17_TINT159_SHIFT (31u) + +#define INTC_ICDABR18_TINT160_SHIFT (0u) +#define INTC_ICDABR18_TINT161_SHIFT (1u) +#define INTC_ICDABR18_TINT162_SHIFT (2u) +#define INTC_ICDABR18_TINT163_SHIFT (3u) +#define INTC_ICDABR18_TINT164_SHIFT (4u) +#define INTC_ICDABR18_TINT165_SHIFT (5u) +#define INTC_ICDABR18_TINT166_SHIFT (6u) +#define INTC_ICDABR18_TINT167_SHIFT (7u) +#define INTC_ICDABR18_TINT168_SHIFT (8u) +#define INTC_ICDABR18_TINT169_SHIFT (9u) +#define INTC_ICDABR18_TINT170_SHIFT (10u) + +#define INTC_ICDIPR0_SW0_SHIFT (0u) +#define INTC_ICDIPR0_SW1_SHIFT (8u) +#define INTC_ICDIPR0_SW2_SHIFT (16u) +#define INTC_ICDIPR0_SW3_SHIFT (24u) + +#define INTC_ICDIPR1_SW4_SHIFT (0u) +#define INTC_ICDIPR1_SW5_SHIFT (8u) +#define INTC_ICDIPR1_SW6_SHIFT (16u) +#define INTC_ICDIPR1_SW7_SHIFT (24u) + +#define INTC_ICDIPR2_SW8_SHIFT (0u) +#define INTC_ICDIPR2_SW9_SHIFT (8u) +#define INTC_ICDIPR2_SW10_SHIFT (16u) +#define INTC_ICDIPR2_SW11_SHIFT (24u) + +#define INTC_ICDIPR3_SW12_SHIFT (0u) +#define INTC_ICDIPR3_SW13_SHIFT (8u) +#define INTC_ICDIPR3_SW14_SHIFT (16u) +#define INTC_ICDIPR3_SW15_SHIFT (24u) + +#define INTC_ICDIPR4_PMUIRQ0_SHIFT (0u) +#define INTC_ICDIPR4_COMMRX0_SHIFT (8u) +#define INTC_ICDIPR4_COMMTX0_SHIFT (16u) +#define INTC_ICDIPR4_CTIIRQ0_SHIFT (24u) + +#define INTC_ICDIPR8_IRQ0_SHIFT (0u) +#define INTC_ICDIPR8_IRQ1_SHIFT (8u) +#define INTC_ICDIPR8_IRQ2_SHIFT (16u) +#define INTC_ICDIPR8_IRQ3_SHIFT (24u) + +#define INTC_ICDIPR9_IRQ4_SHIFT (0u) +#define INTC_ICDIPR9_IRQ5_SHIFT (8u) +#define INTC_ICDIPR9_IRQ6_SHIFT (16u) +#define INTC_ICDIPR9_IRQ7_SHIFT (24u) + +#define INTC_ICDIPR10_PL310ERR_SHIFT (0u) +#define INTC_ICDIPR10_DMAINT0_SHIFT (8u) +#define INTC_ICDIPR10_DMAINT1_SHIFT (16u) +#define INTC_ICDIPR10_DMAINT2_SHIFT (24u) + +#define INTC_ICDIPR11_DMAINT3_SHIFT (0u) +#define INTC_ICDIPR11_DMAINT4_SHIFT (8u) +#define INTC_ICDIPR11_DMAINT5_SHIFT (16u) +#define INTC_ICDIPR11_DMAINT6_SHIFT (24u) + +#define INTC_ICDIPR12_DMAINT7_SHIFT (0u) +#define INTC_ICDIPR12_DMAINT8_SHIFT (8u) +#define INTC_ICDIPR12_DMAINT9_SHIFT (16u) +#define INTC_ICDIPR12_DMAINT10_SHIFT (24u) + +#define INTC_ICDIPR13_DMAINT11_SHIFT (0u) +#define INTC_ICDIPR13_DMAINT12_SHIFT (8u) +#define INTC_ICDIPR13_DMAINT13_SHIFT (16u) +#define INTC_ICDIPR13_DMAINT14_SHIFT (24u) + +#define INTC_ICDIPR14_DMAINT15_SHIFT (0u) +#define INTC_ICDIPR14_DMAERR_SHIFT (8u) + +#define INTC_ICDIPR18_USBI0_SHIFT (8u) +#define INTC_ICDIPR18_USBI1_SHIFT (16u) +#define INTC_ICDIPR18_S0_VI_VSYNC0_SHIFT (24u) + +#define INTC_ICDIPR19_S0_LO_VSYNC0_SHIFT (0u) +#define INTC_ICDIPR19_S0_VSYNCERR0_SHIFT (8u) +#define INTC_ICDIPR19_GR3_VLINE0_SHIFT (16u) +#define INTC_ICDIPR19_S0_VFIELD0_SHIFT (24u) + +#define INTC_ICDIPR20_IV1_VBUFERR0_SHIFT (0u) +#define INTC_ICDIPR20_IV3_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPR20_IV5_VBUFERR0_SHIFT (16u) +#define INTC_ICDIPR20_IV6_VBUFERR0_SHIFT (24u) + +#define INTC_ICDIPR21_S0_WLINE0_SHIFT (0u) +#define INTC_ICDIPR21_S1_VI_VSYNC0_SHIFT (8u) +#define INTC_ICDIPR21_S1_LO_VSYNC0_SHIFT (16u) +#define INTC_ICDIPR21_S1_VSYNCERR0_SHIFT (24u) + +#define INTC_ICDIPR22_S1_VFIELD0_SHIFT (0u) +#define INTC_ICDIPR22_IV2_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPR22_IV4_VBUFERR0_SHIFT (16u) +#define INTC_ICDIPR22_S1_WLINE0_SHIFT (24u) + +#define INTC_ICDIPR23_OIR_VI_VSYNC0_SHIFT (0u) +#define INTC_ICDIPR23_OIR_LO_VSYNC0_SHIFT (8u) +#define INTC_ICDIPR23_OIR_VSYNCERR0_SHIFT (16u) +#define INTC_ICDIPR23_OIR_VFIELD0_SHIFT (24u) + +#define INTC_ICDIPR24_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDIPR24_IV8_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPR24_S0_VI_VSYNC1_SHIFT (24u) + +#define INTC_ICDIPR25_S0_LO_VSYNC1_SHIFT (0u) +#define INTC_ICDIPR25_S0_VSYNCERR1_SHIFT (8u) +#define INTC_ICDIPR25_GR3_VLINE1_SHIFT (16u) +#define INTC_ICDIPR25_S0_VFIELD1_SHIFT (24u) + +#define INTC_ICDIPR26_IV1_VBUFERR1_SHIFT (0u) +#define INTC_ICDIPR26_IV3_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPR26_IV5_VBUFERR1_SHIFT (16u) +#define INTC_ICDIPR26_IV6_VBUFERR1_SHIFT (24u) + +#define INTC_ICDIPR27_S0_WLINE1_SHIFT (0u) +#define INTC_ICDIPR27_S1_VI_VSYNC1_SHIFT (8u) +#define INTC_ICDIPR27_S1_LO_VSYNC1_SHIFT (16u) +#define INTC_ICDIPR27_S1_VSYNCERR1_SHIFT (24u) + +#define INTC_ICDIPR28_S1_VFIELD1_SHIFT (0u) +#define INTC_ICDIPR28_IV2_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPR28_IV4_VBUFERR1_SHIFT (16u) +#define INTC_ICDIPR28_S1_WLINE1_SHIFT (24u) + +#define INTC_ICDIPR29_OIR_VI_VSYNC1_SHIFT (0u) +#define INTC_ICDIPR29_OIR_LO_VSYNC1_SHIFT (8u) +#define INTC_ICDIPR29_OIR_VLINE1_SHIFT (16u) +#define INTC_ICDIPR29_OIR_VFIELD1_SHIFT (24u) + +#define INTC_ICDIPR30_IV7_VBUFERR1_SHIFT (0u) +#define INTC_ICDIPR30_IV8_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPR30_IMRDI_SHIFT (24u) + +#define INTC_ICDIPR31_IMR2I0_SHIFT (0u) +#define INTC_ICDIPR31_IMR2I1_SHIFT (8u) +#define INTC_ICDIPR31_JEDI_SHIFT (16u) +#define INTC_ICDIPR31_JDTI_SHIFT (24u) + +#define INTC_ICDIPR32_CMP0_SHIFT (0u) +#define INTC_ICDIPR32_CMP1_SHIFT (8u) +#define INTC_ICDIPR32_INT0_SHIFT (16u) +#define INTC_ICDIPR32_INT1_SHIFT (24u) + +#define INTC_ICDIPR33_INT2_SHIFT (0u) +#define INTC_ICDIPR33_INT3_SHIFT (8u) +#define INTC_ICDIPR33_OSTM0TINT_SHIFT (16u) +#define INTC_ICDIPR33_OSTM1TINT_SHIFT (24u) + +#define INTC_ICDIPR34_CMI_SHIFT (0u) +#define INTC_ICDIPR34_WTOUT_SHIFT (8u) +#define INTC_ICDIPR34_ITI_SHIFT (16u) +#define INTC_ICDIPR34_TGI0A_SHIFT (24u) + +#define INTC_ICDIPR35_TGI0B_SHIFT (0u) +#define INTC_ICDIPR35_TGI0C_SHIFT (8u) +#define INTC_ICDIPR35_TGI0D_SHIFT (16u) +#define INTC_ICDIPR35_TGI0V_SHIFT (24u) + +#define INTC_ICDIPR36_TGI0E_SHIFT (0u) +#define INTC_ICDIPR36_TGI0F_SHIFT (8u) +#define INTC_ICDIPR36_TGI1A_SHIFT (16u) +#define INTC_ICDIPR36_TGI1B_SHIFT (24u) + +#define INTC_ICDIPR37_TGI1V_SHIFT (0u) +#define INTC_ICDIPR37_TGI1U_SHIFT (8u) +#define INTC_ICDIPR37_TGI2A_SHIFT (16u) +#define INTC_ICDIPR37_TGI2B_SHIFT (24u) + +#define INTC_ICDIPR38_TGI2V_SHIFT (0u) +#define INTC_ICDIPR38_TGI2U_SHIFT (8u) +#define INTC_ICDIPR38_TGI3A_SHIFT (16u) +#define INTC_ICDIPR38_TGI3B_SHIFT (24u) + +#define INTC_ICDIPR39_TGI3C_SHIFT (0u) +#define INTC_ICDIPR39_TGI3D_SHIFT (8u) +#define INTC_ICDIPR39_TGI3V_SHIFT (16u) +#define INTC_ICDIPR39_TGI4A_SHIFT (24u) + +#define INTC_ICDIPR40_TGI4B_SHIFT (0u) +#define INTC_ICDIPR40_TGI4C_SHIFT (8u) +#define INTC_ICDIPR40_TGI4D_SHIFT (16u) +#define INTC_ICDIPR40_TGI4V_SHIFT (24u) + +#define INTC_ICDIPR41_CMI1_SHIFT (0u) +#define INTC_ICDIPR41_CMI2_SHIFT (8u) +#define INTC_ICDIPR41_SGDEI0_SHIFT (16u) +#define INTC_ICDIPR41_SGDEI1_SHIFT (24u) + +#define INTC_ICDIPR42_SGDEI2_SHIFT (0u) +#define INTC_ICDIPR42_SGDEI3_SHIFT (8u) +#define INTC_ICDIPR42_ADI_SHIFT (16u) +#define INTC_ICDIPR42_LMTI_SHIFT (24u) + +#define INTC_ICDIPR43_SSII0_SHIFT (0u) +#define INTC_ICDIPR43_SSIRXI0_SHIFT (8u) +#define INTC_ICDIPR43_SSITXI0_SHIFT (16u) +#define INTC_ICDIPR43_SSII1_SHIFT (24u) + +#define INTC_ICDIPR44_SSIRXI1_SHIFT (0u) +#define INTC_ICDIPR44_SSITXI1_SHIFT (8u) +#define INTC_ICDIPR44_SSII2_SHIFT (16u) +#define INTC_ICDIPR44_SSIRTI2_SHIFT (24u) + +#define INTC_ICDIPR45_SSII3_SHIFT (0u) +#define INTC_ICDIPR45_SSIRXI3_SHIFT (8u) +#define INTC_ICDIPR45_SSITXI3_SHIFT (16u) +#define INTC_ICDIPR45_SSII4_SHIFT (24u) + +#define INTC_ICDIPR46_SSIRTI4_SHIFT (0u) +#define INTC_ICDIPR46_SSII5_SHIFT (8u) +#define INTC_ICDIPR46_SSIRXI5_SHIFT (16u) +#define INTC_ICDIPR46_SSITXI5_SHIFT (24u) + +#define INTC_ICDIPR47_SPDIFI_SHIFT (0u) +#define INTC_ICDIPR47_INTIICTEI0_SHIFT (8u) +#define INTC_ICDIPR47_INTIICRI0_SHIFT (16u) +#define INTC_ICDIPR47_INTIICTI0_SHIFT (24u) + +#define INTC_ICDIPR48_INTIICSPI0_SHIFT (0u) +#define INTC_ICDIPR48_INTIICSTI0_SHIFT (8u) +#define INTC_ICDIPR48_INTIICNAKI0_SHIFT (16u) +#define INTC_ICDIPR48_INTIICALI0_SHIFT (24u) + +#define INTC_ICDIPR49_INTIICTMOI0_SHIFT (0u) +#define INTC_ICDIPR49_INTIICTEI1_SHIFT (8u) +#define INTC_ICDIPR49_INTIICRI1_SHIFT (16u) +#define INTC_ICDIPR49_INTIICTI1_SHIFT (24u) + +#define INTC_ICDIPR50_INTIICSPI1_SHIFT (0u) +#define INTC_ICDIPR50_INTIICSTI1_SHIFT (8u) +#define INTC_ICDIPR50_INTIICNAKI1_SHIFT (16u) +#define INTC_ICDIPR50_INTIICALI1_SHIFT (24u) + +#define INTC_ICDIPR51_INTIICTMOI1_SHIFT (0u) +#define INTC_ICDIPR51_INTIICTEI2_SHIFT (8u) +#define INTC_ICDIPR51_INTIICRI2_SHIFT (16u) +#define INTC_ICDIPR51_INTIICTI2_SHIFT (24u) + +#define INTC_ICDIPR52_INTIICSPI2_SHIFT (0u) +#define INTC_ICDIPR52_INTIICSTI2_SHIFT (8u) +#define INTC_ICDIPR52_INTIICNAKI2_SHIFT (16u) +#define INTC_ICDIPR52_INTIICALI2_SHIFT (24u) + +#define INTC_ICDIPR53_INTIICTMOI2_SHIFT (0u) +#define INTC_ICDIPR53_INTIICTEI3_SHIFT (8u) +#define INTC_ICDIPR53_INTIICRI3_SHIFT (16u) +#define INTC_ICDIPR53_INTIICTI3_SHIFT (24u) + +#define INTC_ICDIPR54_INTIICSPI3_SHIFT (0u) +#define INTC_ICDIPR54_INTIICSTI3_SHIFT (8u) +#define INTC_ICDIPR54_INTIICNAKI3_SHIFT (16u) +#define INTC_ICDIPR54_INTIICALI3_SHIFT (24u) + +#define INTC_ICDIPR55_INTIICTMOI3_SHIFT (0u) +#define INTC_ICDIPR55_BRI0_SHIFT (8u) +#define INTC_ICDIPR55_ERI0_SHIFT (16u) +#define INTC_ICDIPR55_RXI0_SHIFT (24u) + +#define INTC_ICDIPR56_TXI0_SHIFT (0u) +#define INTC_ICDIPR56_BRI1_SHIFT (8u) +#define INTC_ICDIPR56_ERI1_SHIFT (16u) +#define INTC_ICDIPR56_RXI1_SHIFT (24u) + +#define INTC_ICDIPR57_TXI1_SHIFT (0u) +#define INTC_ICDIPR57_BRI2_SHIFT (8u) +#define INTC_ICDIPR57_ERI2_SHIFT (16u) +#define INTC_ICDIPR57_RXI2_SHIFT (24u) + +#define INTC_ICDIPR58_TXI2_SHIFT (0u) +#define INTC_ICDIPR58_BRI3_SHIFT (8u) +#define INTC_ICDIPR58_ERI3_SHIFT (16u) +#define INTC_ICDIPR58_RXI3_SHIFT (24u) + +#define INTC_ICDIPR59_TXI3_SHIFT (0u) +#define INTC_ICDIPR59_BRI4_SHIFT (8u) +#define INTC_ICDIPR59_ERI4_SHIFT (16u) +#define INTC_ICDIPR59_RXI4_SHIFT (24u) + +#define INTC_ICDIPR60_TXI4_SHIFT (0u) +#define INTC_ICDIPR60_BRI5_SHIFT (8u) +#define INTC_ICDIPR60_ERI5_SHIFT (16u) +#define INTC_ICDIPR60_RXI5_SHIFT (24u) + +#define INTC_ICDIPR61_TXI5_SHIFT (0u) +#define INTC_ICDIPR61_BRI6_SHIFT (8u) +#define INTC_ICDIPR61_ERI6_SHIFT (16u) +#define INTC_ICDIPR61_RXI6_SHIFT (24u) + +#define INTC_ICDIPR62_TXI6_SHIFT (0u) +#define INTC_ICDIPR62_BRI7_SHIFT (8u) +#define INTC_ICDIPR62_ERI7_SHIFT (16u) +#define INTC_ICDIPR62_RXI7_SHIFT (24u) + +#define INTC_ICDIPR63_TXI7_SHIFT (0u) +#define INTC_ICDIPR63_INTRCANGERR_SHIFT (8u) +#define INTC_ICDIPR63_INTRCANGRECC_SHIFT (16u) +#define INTC_ICDIPR63_INTRCAN0REC_SHIFT (24u) + +#define INTC_ICDIPR64_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDIPR64_INTRCAN0TRX_SHIFT (8u) +#define INTC_ICDIPR64_INTRCAN1REC_SHIFT (16u) +#define INTC_ICDIPR64_INTRCAN1ERR_SHIFT (24u) + +#define INTC_ICDIPR65_INTRCAN1TRX_SHIFT (0u) +#define INTC_ICDIPR65_INTRCAN2REC_SHIFT (8u) +#define INTC_ICDIPR65_INTRCAN2ERR_SHIFT (16u) +#define INTC_ICDIPR65_INTRCAN2TRX_SHIFT (24u) + +#define INTC_ICDIPR66_INTRCAN3REC_SHIFT (0u) +#define INTC_ICDIPR66_INTRCAN3ERR_SHIFT (8u) +#define INTC_ICDIPR66_INTRCAN3TRX_SHIFT (16u) +#define INTC_ICDIPR66_INTRCAN4REC_SHIFT (24u) + +#define INTC_ICDIPR67_INTRCAN4ERR_SHIFT (0u) +#define INTC_ICDIPR67_INTRCAN4TRX_SHIFT (8u) +#define INTC_ICDIPR67_SPEI0_SHIFT (16u) +#define INTC_ICDIPR67_SPRI0_SHIFT (24u) + +#define INTC_ICDIPR68_SPTI0_SHIFT (0u) +#define INTC_ICDIPR68_SPEI1_SHIFT (8u) +#define INTC_ICDIPR68_SPRI1_SHIFT (16u) +#define INTC_ICDIPR68_SPTI1_SHIFT (24u) + +#define INTC_ICDIPR69_SPEI2_SHIFT (0u) +#define INTC_ICDIPR69_SPRI2_SHIFT (8u) +#define INTC_ICDIPR69_SPTI2_SHIFT (16u) +#define INTC_ICDIPR69_SPEI3_SHIFT (24u) + +#define INTC_ICDIPR70_SPRI3_SHIFT (0u) +#define INTC_ICDIPR70_SPTI3_SHIFT (8u) +#define INTC_ICDIPR70_SPEI4_SHIFT (16u) +#define INTC_ICDIPR70_SPRI4_SHIFT (24u) + +#define INTC_ICDIPR71_SPTI4_SHIFT (0u) +#define INTC_ICDIPR71_IEBBTD_SHIFT (8u) +#define INTC_ICDIPR71_IEBBTERR_SHIFT (16u) +#define INTC_ICDIPR71_IEBBTSTA_SHIFT (24u) + +#define INTC_ICDIPR72_IEBBTV_SHIFT (0u) +#define INTC_ICDIPR72_ISY_SHIFT (8u) +#define INTC_ICDIPR72_IERR_SHIFT (16u) +#define INTC_ICDIPR72_ITARG_SHIFT (24u) + +#define INTC_ICDIPR73_ISEC_SHIFT (0u) +#define INTC_ICDIPR73_IBUF_SHIFT (8u) +#define INTC_ICDIPR73_IREADY_SHIFT (16u) +#define INTC_ICDIPR73_FLSTE_SHIFT (24u) + +#define INTC_ICDIPR74_FLTENDI_SHIFT (0u) +#define INTC_ICDIPR74_FLTREQ0I_SHIFT (8u) +#define INTC_ICDIPR74_FLTREQ1I_SHIFT (16u) +#define INTC_ICDIPR74_MMC0_SHIFT (24u) + +#define INTC_ICDIPR75_MMC1_SHIFT (0u) +#define INTC_ICDIPR75_MMC2_SHIFT (8u) +#define INTC_ICDIPR75_SDHI0_3_SHIFT (16u) +#define INTC_ICDIPR75_SDHI0_0_SHIFT (24u) + +#define INTC_ICDIPR76_SDHI0_1_SHIFT (0u) +#define INTC_ICDIPR76_SDHI1_3_SHIFT (8u) +#define INTC_ICDIPR76_SDHI1_0_SHIFT (16u) +#define INTC_ICDIPR76_SDHI1_1_SHIFT (24u) + +#define INTC_ICDIPR77_ARM_SHIFT (0u) +#define INTC_ICDIPR77_PRD_SHIFT (8u) +#define INTC_ICDIPR77_CUP_SHIFT (16u) +#define INTC_ICDIPR77_SCUAI0_SHIFT (24u) + +#define INTC_ICDIPR78_SCUAI1_SHIFT (0u) +#define INTC_ICDIPR78_SCUFDI0_SHIFT (8u) +#define INTC_ICDIPR78_SCUFDI1_SHIFT (16u) +#define INTC_ICDIPR78_SCUFDI2_SHIFT (24u) + +#define INTC_ICDIPR79_SCUFDI3_SHIFT (0u) +#define INTC_ICDIPR79_SCUFUI0_SHIFT (8u) +#define INTC_ICDIPR79_SCUFUI1_SHIFT (16u) +#define INTC_ICDIPR79_SCUFUI2_SHIFT (24u) + +#define INTC_ICDIPR80_SCUFUI3_SHIFT (0u) +#define INTC_ICDIPR80_SCUDVI0_SHIFT (8u) +#define INTC_ICDIPR80_SCUDVI1_SHIFT (16u) +#define INTC_ICDIPR80_SCUDVI2_SHIFT (24u) + +#define INTC_ICDIPR81_SCUDVI3_SHIFT (0u) +#define INTC_ICDIPR81_MLB_CINT_SHIFT (8u) +#define INTC_ICDIPR81_MLB_SINT_SHIFT (16u) +#define INTC_ICDIPR81_DRC0_SHIFT (24u) + +#define INTC_ICDIPR82_DRC1_SHIFT (0u) +#define INTC_ICDIPR82_LINI0_INT_T_SHIFT (24u) + +#define INTC_ICDIPR83_LINI0_INT_R_SHIFT (0u) +#define INTC_ICDIPR83_LINI0_INT_S_SHIFT (8u) +#define INTC_ICDIPR83_LINI0_INT_M_SHIFT (16u) +#define INTC_ICDIPR83_LINI1_INT_T_SHIFT (24u) + +#define INTC_ICDIPR84_LINI1_INT_R_SHIFT (0u) +#define INTC_ICDIPR84_LINI1_INT_S_SHIFT (8u) +#define INTC_ICDIPR84_LINI1_INT_M_SHIFT (16u) + +#define INTC_ICDIPR86_ERI0_SHIFT (24u) + +#define INTC_ICDIPR87_RXI0_SHIFT (0u) +#define INTC_ICDIPR87_TXI0_SHIFT (8u) +#define INTC_ICDIPR87_TEI0_SHIFT (16u) +#define INTC_ICDIPR87_ERI1_SHIFT (24u) + +#define INTC_ICDIPR88_RXI1_SHIFT (0u) +#define INTC_ICDIPR88_TXI1_SHIFT (8u) +#define INTC_ICDIPR88_TEI1_SHIFT (16u) +#define INTC_ICDIPR88_AVBI_DATA_SHIFT (24u) + +#define INTC_ICDIPR89_AVBI_ERROR_SHIFT (0u) +#define INTC_ICDIPR89_AVBI_MANAGE_SHIFT (8u) +#define INTC_ICDIPR89_AVBI_MAC_SHIFT (16u) +#define INTC_ICDIPR89_ETHERI_SHIFT (24u) + +#define INTC_ICDIPR91_CEUI_SHIFT (0u) + +#define INTC_ICDIPR95_H2XMLB_ERRINT_SHIFT (8u) +#define INTC_ICDIPR95_H2XIC1_ERRINT_SHIFT (16u) +#define INTC_ICDIPR95_X2HPERI1_ERRINT_SHIFT (24u) + +#define INTC_ICDIPR96_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDIPR96_X2HPERI34_ERRINT_SHIFT (8u) +#define INTC_ICDIPR96_X2HPERI5_ERRINT_SHIFT (16u) +#define INTC_ICDIPR96_X2HPERI67_ERRINT_SHIFT (24u) + +#define INTC_ICDIPR97_X2HDBGR_ERRINT_SHIFT (0u) +#define INTC_ICDIPR97_X2HBSC_ERRINT_SHIFT (8u) +#define INTC_ICDIPR97_X2HSPI1_ERRINT_SHIFT (16u) +#define INTC_ICDIPR97_X2HSPI2_ERRINT_SHIFT (24u) + +#define INTC_ICDIPR98_PRRI_SHIFT (0u) +#define INTC_ICDIPR98_IFEI0_SHIFT (8u) +#define INTC_ICDIPR98_OFFI0_SHIFT (16u) +#define INTC_ICDIPR98_PFVEI0_SHIFT (24u) + +#define INTC_ICDIPR99_IFEI1_SHIFT (0u) +#define INTC_ICDIPR99_OFFI1_SHIFT (8u) +#define INTC_ICDIPR99_PFVEI1_SHIFT (16u) + +#define INTC_ICDIPR104_TINT0_SHIFT (0u) +#define INTC_ICDIPR104_TINT1_SHIFT (8u) +#define INTC_ICDIPR104_TINT2_SHIFT (16u) +#define INTC_ICDIPR104_TINT3_SHIFT (24u) + +#define INTC_ICDIPR105_TINT4_SHIFT (0u) +#define INTC_ICDIPR105_TINT5_SHIFT (8u) +#define INTC_ICDIPR105_TINT6_SHIFT (16u) +#define INTC_ICDIPR105_TINT7_SHIFT (24u) + +#define INTC_ICDIPR106_TINT8_SHIFT (0u) +#define INTC_ICDIPR106_TINT9_SHIFT (8u) +#define INTC_ICDIPR106_TINT10_SHIFT (16u) +#define INTC_ICDIPR106_TINT11_SHIFT (24u) + +#define INTC_ICDIPR107_TINT12_SHIFT (0u) +#define INTC_ICDIPR107_TINT13_SHIFT (8u) +#define INTC_ICDIPR107_TINT14_SHIFT (16u) +#define INTC_ICDIPR107_TINT15_SHIFT (24u) + +#define INTC_ICDIPR108_TINT16_SHIFT (0u) +#define INTC_ICDIPR108_TINT17_SHIFT (8u) +#define INTC_ICDIPR108_TINT18_SHIFT (16u) +#define INTC_ICDIPR108_TINT19_SHIFT (24u) + +#define INTC_ICDIPR109_TINT20_SHIFT (0u) +#define INTC_ICDIPR109_TINT21_SHIFT (8u) +#define INTC_ICDIPR109_TINT22_SHIFT (16u) +#define INTC_ICDIPR109_TINT23_SHIFT (24u) + +#define INTC_ICDIPR110_TINT24_SHIFT (0u) +#define INTC_ICDIPR110_TINT25_SHIFT (8u) +#define INTC_ICDIPR110_TINT26_SHIFT (16u) +#define INTC_ICDIPR110_TINT27_SHIFT (24u) + +#define INTC_ICDIPR111_TINT28_SHIFT (0u) +#define INTC_ICDIPR111_TINT29_SHIFT (8u) +#define INTC_ICDIPR111_TINT30_SHIFT (16u) +#define INTC_ICDIPR111_TINT31_SHIFT (24u) + +#define INTC_ICDIPR112_TINT32_SHIFT (0u) +#define INTC_ICDIPR112_TINT33_SHIFT (8u) +#define INTC_ICDIPR112_TINT34_SHIFT (16u) +#define INTC_ICDIPR112_TINT35_SHIFT (24u) + +#define INTC_ICDIPR113_TINT36_SHIFT (0u) +#define INTC_ICDIPR113_TINT37_SHIFT (8u) +#define INTC_ICDIPR113_TINT38_SHIFT (16u) +#define INTC_ICDIPR113_TINT39_SHIFT (24u) + +#define INTC_ICDIPR114_TINT40_SHIFT (0u) +#define INTC_ICDIPR114_TINT41_SHIFT (8u) +#define INTC_ICDIPR114_TINT42_SHIFT (16u) +#define INTC_ICDIPR114_TINT43_SHIFT (24u) + +#define INTC_ICDIPR115_TINT44_SHIFT (0u) +#define INTC_ICDIPR115_TINT45_SHIFT (8u) +#define INTC_ICDIPR115_TINT46_SHIFT (16u) +#define INTC_ICDIPR115_TINT47_SHIFT (24u) + +#define INTC_ICDIPR116_TINT48_SHIFT (0u) +#define INTC_ICDIPR116_TINT49_SHIFT (8u) +#define INTC_ICDIPR116_TINT50_SHIFT (16u) +#define INTC_ICDIPR116_TINT51_SHIFT (24u) + +#define INTC_ICDIPR117_TINT52_SHIFT (0u) +#define INTC_ICDIPR117_TINT53_SHIFT (8u) +#define INTC_ICDIPR117_TINT54_SHIFT (16u) +#define INTC_ICDIPR117_TINT55_SHIFT (24u) + +#define INTC_ICDIPR118_TINT56_SHIFT (0u) +#define INTC_ICDIPR118_TINT57_SHIFT (8u) +#define INTC_ICDIPR118_TINT58_SHIFT (16u) +#define INTC_ICDIPR118_TINT59_SHIFT (24u) + +#define INTC_ICDIPR119_TINT60_SHIFT (0u) +#define INTC_ICDIPR119_TINT61_SHIFT (8u) +#define INTC_ICDIPR119_TINT62_SHIFT (16u) +#define INTC_ICDIPR119_TINT63_SHIFT (24u) + +#define INTC_ICDIPR120_TINT64_SHIFT (0u) +#define INTC_ICDIPR120_TINT65_SHIFT (8u) +#define INTC_ICDIPR120_TINT66_SHIFT (16u) +#define INTC_ICDIPR120_TINT67_SHIFT (24u) + +#define INTC_ICDIPR121_TINT68_SHIFT (0u) +#define INTC_ICDIPR121_TINT69_SHIFT (8u) +#define INTC_ICDIPR121_TINT70_SHIFT (16u) +#define INTC_ICDIPR121_TINT71_SHIFT (24u) + +#define INTC_ICDIPR122_TINT72_SHIFT (0u) +#define INTC_ICDIPR122_TINT73_SHIFT (8u) +#define INTC_ICDIPR122_TINT74_SHIFT (16u) +#define INTC_ICDIPR122_TINT75_SHIFT (24u) + +#define INTC_ICDIPR123_TINT76_SHIFT (0u) +#define INTC_ICDIPR123_TINT77_SHIFT (8u) +#define INTC_ICDIPR123_TINT78_SHIFT (16u) +#define INTC_ICDIPR123_TINT79_SHIFT (24u) + +#define INTC_ICDIPR124_TINT80_SHIFT (0u) +#define INTC_ICDIPR124_TINT81_SHIFT (8u) +#define INTC_ICDIPR124_TINT82_SHIFT (16u) +#define INTC_ICDIPR124_TINT83_SHIFT (24u) + +#define INTC_ICDIPR125_TINT84_SHIFT (0u) +#define INTC_ICDIPR125_TINT85_SHIFT (8u) +#define INTC_ICDIPR125_TINT86_SHIFT (16u) +#define INTC_ICDIPR125_TINT87_SHIFT (24u) + +#define INTC_ICDIPR126_TINT88_SHIFT (0u) +#define INTC_ICDIPR126_TINT89_SHIFT (8u) +#define INTC_ICDIPR126_TINT90_SHIFT (16u) +#define INTC_ICDIPR126_TINT91_SHIFT (24u) + +#define INTC_ICDIPR127_TINT92_SHIFT (0u) +#define INTC_ICDIPR127_TINT93_SHIFT (8u) +#define INTC_ICDIPR127_TINT94_SHIFT (16u) +#define INTC_ICDIPR127_TINT95_SHIFT (24u) + +#define INTC_ICDIPR128_TINT96_SHIFT (0u) +#define INTC_ICDIPR128_TINT97_SHIFT (8u) +#define INTC_ICDIPR128_TINT98_SHIFT (16u) +#define INTC_ICDIPR128_TINT99_SHIFT (24u) + +#define INTC_ICDIPR129_TINT100_SHIFT (0u) +#define INTC_ICDIPR129_TINT101_SHIFT (8u) +#define INTC_ICDIPR129_TINT102_SHIFT (16u) +#define INTC_ICDIPR129_TINT103_SHIFT (24u) + +#define INTC_ICDIPR130_TINT104_SHIFT (0u) +#define INTC_ICDIPR130_TINT105_SHIFT (8u) +#define INTC_ICDIPR130_TINT106_SHIFT (16u) +#define INTC_ICDIPR130_TINT107_SHIFT (24u) + +#define INTC_ICDIPR131_TINT108_SHIFT (0u) +#define INTC_ICDIPR131_TINT109_SHIFT (8u) +#define INTC_ICDIPR131_TINT110_SHIFT (16u) +#define INTC_ICDIPR131_TINT111_SHIFT (24u) + +#define INTC_ICDIPR132_TINT112_SHIFT (0u) +#define INTC_ICDIPR132_TINT113_SHIFT (8u) +#define INTC_ICDIPR132_TINT114_SHIFT (16u) +#define INTC_ICDIPR132_TINT115_SHIFT (24u) + +#define INTC_ICDIPR133_TINT116_SHIFT (0u) +#define INTC_ICDIPR133_TINT117_SHIFT (8u) +#define INTC_ICDIPR133_TINT118_SHIFT (16u) +#define INTC_ICDIPR133_TINT119_SHIFT (24u) + +#define INTC_ICDIPR134_TINT120_SHIFT (0u) +#define INTC_ICDIPR134_TINT121_SHIFT (8u) +#define INTC_ICDIPR134_TINT122_SHIFT (16u) +#define INTC_ICDIPR134_TINT123_SHIFT (24u) + +#define INTC_ICDIPR135_TINT124_SHIFT (0u) +#define INTC_ICDIPR135_TINT125_SHIFT (8u) +#define INTC_ICDIPR135_TINT126_SHIFT (16u) +#define INTC_ICDIPR135_TINT127_SHIFT (24u) + +#define INTC_ICDIPR136_TINT128_SHIFT (0u) +#define INTC_ICDIPR136_TINT129_SHIFT (8u) +#define INTC_ICDIPR136_TINT130_SHIFT (16u) +#define INTC_ICDIPR136_TINT131_SHIFT (24u) + +#define INTC_ICDIPR137_TINT132_SHIFT (0u) +#define INTC_ICDIPR137_TINT133_SHIFT (8u) +#define INTC_ICDIPR137_TINT134_SHIFT (16u) +#define INTC_ICDIPR137_TINT135_SHIFT (24u) + +#define INTC_ICDIPR138_TINT136_SHIFT (0u) +#define INTC_ICDIPR138_TINT137_SHIFT (8u) +#define INTC_ICDIPR138_TINT138_SHIFT (16u) +#define INTC_ICDIPR138_TINT139_SHIFT (24u) + +#define INTC_ICDIPR139_TINT140_SHIFT (0u) +#define INTC_ICDIPR139_TINT141_SHIFT (8u) +#define INTC_ICDIPR139_TINT142_SHIFT (16u) +#define INTC_ICDIPR139_TINT143_SHIFT (24u) + +#define INTC_ICDIPR140_TINT144_SHIFT (0u) +#define INTC_ICDIPR140_TINT145_SHIFT (8u) +#define INTC_ICDIPR140_TINT146_SHIFT (16u) +#define INTC_ICDIPR140_TINT147_SHIFT (24u) + +#define INTC_ICDIPR141_TINT148_SHIFT (0u) +#define INTC_ICDIPR141_TINT149_SHIFT (8u) +#define INTC_ICDIPR141_TINT150_SHIFT (16u) +#define INTC_ICDIPR141_TINT151_SHIFT (24u) + +#define INTC_ICDIPR142_TINT152_SHIFT (0u) +#define INTC_ICDIPR142_TINT153_SHIFT (8u) +#define INTC_ICDIPR142_TINT154_SHIFT (16u) +#define INTC_ICDIPR142_TINT155_SHIFT (24u) + +#define INTC_ICDIPR143_TINT156_SHIFT (0u) +#define INTC_ICDIPR143_TINT157_SHIFT (8u) +#define INTC_ICDIPR143_TINT158_SHIFT (16u) +#define INTC_ICDIPR143_TINT159_SHIFT (24u) + +#define INTC_ICDIPR144_TINT160_SHIFT (0u) +#define INTC_ICDIPR144_TINT161_SHIFT (8u) +#define INTC_ICDIPR144_TINT162_SHIFT (16u) +#define INTC_ICDIPR144_TINT163_SHIFT (24u) + +#define INTC_ICDIPR145_TINT164_SHIFT (0u) +#define INTC_ICDIPR145_TINT165_SHIFT (8u) +#define INTC_ICDIPR145_TINT166_SHIFT (16u) +#define INTC_ICDIPR145_TINT167_SHIFT (24u) + +#define INTC_ICDIPR146_TINT168_SHIFT (0u) +#define INTC_ICDIPR146_TINT169_SHIFT (8u) +#define INTC_ICDIPR146_TINT170_SHIFT (16u) + +#define INTC_ICDIPTR0_SW0_SHIFT (0u) +#define INTC_ICDIPTR0_SW1_SHIFT (8u) +#define INTC_ICDIPTR0_SW2_SHIFT (16u) +#define INTC_ICDIPTR0_SW3_SHIFT (24u) + +#define INTC_ICDIPTR1_SW4_SHIFT (0u) +#define INTC_ICDIPTR1_SW5_SHIFT (8u) +#define INTC_ICDIPTR1_SW6_SHIFT (16u) +#define INTC_ICDIPTR1_SW7_SHIFT (24u) + +#define INTC_ICDIPTR2_SW8_SHIFT (0u) +#define INTC_ICDIPTR2_SW9_SHIFT (8u) +#define INTC_ICDIPTR2_SW10_SHIFT (16u) +#define INTC_ICDIPTR2_SW11_SHIFT (24u) + +#define INTC_ICDIPTR3_SW12_SHIFT (0u) +#define INTC_ICDIPTR3_SW13_SHIFT (8u) +#define INTC_ICDIPTR3_SW14_SHIFT (16u) +#define INTC_ICDIPTR3_SW15_SHIFT (24u) + +#define INTC_ICDIPTR4_PMUIRQ0_SHIFT (0u) +#define INTC_ICDIPTR4_COMMRX0_SHIFT (8u) +#define INTC_ICDIPTR4_COMMTX0_SHIFT (16u) +#define INTC_ICDIPTR4_CTIIRQ0_SHIFT (24u) + +#define INTC_ICDIPTR8_IRQ0_SHIFT (0u) +#define INTC_ICDIPTR8_IRQ1_SHIFT (8u) +#define INTC_ICDIPTR8_IRQ2_SHIFT (16u) +#define INTC_ICDIPTR8_IRQ3_SHIFT (24u) + +#define INTC_ICDIPTR9_IRQ4_SHIFT (0u) +#define INTC_ICDIPTR9_IRQ5_SHIFT (8u) +#define INTC_ICDIPTR9_IRQ6_SHIFT (16u) +#define INTC_ICDIPTR9_IRQ7_SHIFT (24u) + +#define INTC_ICDIPTR10_PL310ERR_SHIFT (0u) +#define INTC_ICDIPTR10_DMAINT0_SHIFT (8u) +#define INTC_ICDIPTR10_DMAINT1_SHIFT (16u) +#define INTC_ICDIPTR10_DMAINT2_SHIFT (24u) + +#define INTC_ICDIPTR11_DMAINT3_SHIFT (0u) +#define INTC_ICDIPTR11_DMAINT4_SHIFT (8u) +#define INTC_ICDIPTR11_DMAINT5_SHIFT (16u) +#define INTC_ICDIPTR11_DMAINT6_SHIFT (24u) + +#define INTC_ICDIPTR12_DMAINT7_SHIFT (0u) +#define INTC_ICDIPTR12_DMAINT8_SHIFT (8u) +#define INTC_ICDIPTR12_DMAINT9_SHIFT (16u) +#define INTC_ICDIPTR12_DMAINT10_SHIFT (24u) + +#define INTC_ICDIPTR13_DMAINT11_SHIFT (0u) +#define INTC_ICDIPTR13_DMAINT12_SHIFT (8u) +#define INTC_ICDIPTR13_DMAINT13_SHIFT (16u) +#define INTC_ICDIPTR13_DMAINT14_SHIFT (24u) + +#define INTC_ICDIPTR14_DMAINT15_SHIFT (0u) +#define INTC_ICDIPTR14_DMAERR_SHIFT (8u) + +#define INTC_ICDIPTR18_USBI0_SHIFT (8u) +#define INTC_ICDIPTR18_USBI1_SHIFT (16u) +#define INTC_ICDIPTR18_S0_VI_VSYNC0_SHIFT (24u) + +#define INTC_ICDIPTR19_S0_LO_VSYNC0_SHIFT (0u) +#define INTC_ICDIPTR19_S0_VSYNCERR0_SHIFT (8u) +#define INTC_ICDIPTR19_GR3_VLINE0_SHIFT (16u) +#define INTC_ICDIPTR19_S0_VFIELD0_SHIFT (24u) + +#define INTC_ICDIPTR20_IV1_VBUFERR0_SHIFT (0u) +#define INTC_ICDIPTR20_IV3_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPTR20_IV5_VBUFERR0_SHIFT (16u) +#define INTC_ICDIPTR20_IV6_VBUFERR0_SHIFT (24u) + +#define INTC_ICDIPTR21_S0_WLINE0_SHIFT (0u) +#define INTC_ICDIPTR21_S1_VI_VSYNC0_SHIFT (8u) +#define INTC_ICDIPTR21_S1_LO_VSYNC0_SHIFT (16u) +#define INTC_ICDIPTR21_S1_VSYNCERR0_SHIFT (24u) + +#define INTC_ICDIPTR22_S1_VFIELD0_SHIFT (0u) +#define INTC_ICDIPTR22_IV2_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPTR22_IV4_VBUFERR0_SHIFT (16u) +#define INTC_ICDIPTR22_S1_WLINE0_SHIFT (24u) + +#define INTC_ICDIPTR23_OIR_VI_VSYNC0_SHIFT (0u) +#define INTC_ICDIPTR23_OIR_LO_VSYNC0_SHIFT (8u) +#define INTC_ICDIPTR23_OIR_VSYNCERR0_SHIFT (16u) +#define INTC_ICDIPTR23_OIR_VFIELD0_SHIFT (24u) + +#define INTC_ICDIPTR24_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDIPTR24_IV8_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPTR24_S0_VI_VSYNC1_SHIFT (24u) + +#define INTC_ICDIPTR25_S0_LO_VSYNC1_SHIFT (0u) +#define INTC_ICDIPTR25_S0_VSYNCERR1_SHIFT (8u) +#define INTC_ICDIPTR25_GR3_VLINE1_SHIFT (16u) +#define INTC_ICDIPTR25_S0_VFIELD1_SHIFT (24u) + +#define INTC_ICDIPTR26_IV1_VBUFERR1_SHIFT (0u) +#define INTC_ICDIPTR26_IV3_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPTR26_IV5_VBUFERR1_SHIFT (16u) +#define INTC_ICDIPTR26_IV6_VBUFERR1_SHIFT (24u) + +#define INTC_ICDIPTR27_S0_WLINE1_SHIFT (0u) +#define INTC_ICDIPTR27_S1_VI_VSYNC1_SHIFT (8u) +#define INTC_ICDIPTR27_S1_LO_VSYNC1_SHIFT (16u) +#define INTC_ICDIPTR27_S1_VSYNCERR1_SHIFT (24u) + +#define INTC_ICDIPTR28_S1_VFIELD1_SHIFT (0u) +#define INTC_ICDIPTR28_IV2_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPTR28_IV4_VBUFERR1_SHIFT (16u) +#define INTC_ICDIPTR28_S1_WLINE1_SHIFT (24u) + +#define INTC_ICDIPTR29_OIR_VI_VSYNC1_SHIFT (0u) +#define INTC_ICDIPTR29_OIR_LO_VSYNC1_SHIFT (8u) +#define INTC_ICDIPTR29_OIR_VLINE1_SHIFT (16u) +#define INTC_ICDIPTR29_OIR_VFIELD1_SHIFT (24u) + +#define INTC_ICDIPTR30_IV7_VBUFERR1_SHIFT (0u) +#define INTC_ICDIPTR30_IV8_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPTR30_IMRDI_SHIFT (24u) + +#define INTC_ICDIPTR31_IMR2I0_SHIFT (0u) +#define INTC_ICDIPTR31_IMR2I1_SHIFT (8u) +#define INTC_ICDIPTR31_JEDI_SHIFT (16u) +#define INTC_ICDIPTR31_JDTI_SHIFT (24u) + +#define INTC_ICDIPTR32_CMP0_SHIFT (0u) +#define INTC_ICDIPTR32_CMP1_SHIFT (8u) +#define INTC_ICDIPTR32_INT0_SHIFT (16u) +#define INTC_ICDIPTR32_INT1_SHIFT (24u) + +#define INTC_ICDIPTR33_INT2_SHIFT (0u) +#define INTC_ICDIPTR33_INT3_SHIFT (8u) +#define INTC_ICDIPTR33_OSTM0TINT_SHIFT (16u) +#define INTC_ICDIPTR33_OSTM1TINT_SHIFT (24u) + +#define INTC_ICDIPTR34_CMI_SHIFT (0u) +#define INTC_ICDIPTR34_WTOUT_SHIFT (8u) +#define INTC_ICDIPTR34_ITI_SHIFT (16u) +#define INTC_ICDIPTR34_TGI0A_SHIFT (24u) + +#define INTC_ICDIPTR35_TGI0B_SHIFT (0u) +#define INTC_ICDIPTR35_TGI0C_SHIFT (8u) +#define INTC_ICDIPTR35_TGI0D_SHIFT (16u) +#define INTC_ICDIPTR35_TGI0V_SHIFT (24u) + +#define INTC_ICDIPTR36_TGI0E_SHIFT (0u) +#define INTC_ICDIPTR36_TGI0F_SHIFT (8u) +#define INTC_ICDIPTR36_TGI1A_SHIFT (16u) +#define INTC_ICDIPTR36_TGI1B_SHIFT (24u) + +#define INTC_ICDIPTR37_TGI1V_SHIFT (0u) +#define INTC_ICDIPTR37_TGI1U_SHIFT (8u) +#define INTC_ICDIPTR37_TGI2A_SHIFT (16u) +#define INTC_ICDIPTR37_TGI2B_SHIFT (24u) + +#define INTC_ICDIPTR38_TGI2V_SHIFT (0u) +#define INTC_ICDIPTR38_TGI2U_SHIFT (8u) +#define INTC_ICDIPTR38_TGI3A_SHIFT (16u) +#define INTC_ICDIPTR38_TGI3B_SHIFT (24u) + +#define INTC_ICDIPTR39_TGI3C_SHIFT (0u) +#define INTC_ICDIPTR39_TGI3D_SHIFT (8u) +#define INTC_ICDIPTR39_TGI3V_SHIFT (16u) +#define INTC_ICDIPTR39_TGI4A_SHIFT (24u) + +#define INTC_ICDIPTR40_TGI4B_SHIFT (0u) +#define INTC_ICDIPTR40_TGI4C_SHIFT (8u) +#define INTC_ICDIPTR40_TGI4D_SHIFT (16u) +#define INTC_ICDIPTR40_TGI4V_SHIFT (24u) + +#define INTC_ICDIPTR41_CMI1_SHIFT (0u) +#define INTC_ICDIPTR41_CMI2_SHIFT (8u) +#define INTC_ICDIPTR41_SGDEI0_SHIFT (16u) +#define INTC_ICDIPTR41_SGDEI1_SHIFT (24u) + +#define INTC_ICDIPTR42_SGDEI2_SHIFT (0u) +#define INTC_ICDIPTR42_SGDEI3_SHIFT (8u) +#define INTC_ICDIPTR42_ADI_SHIFT (16u) +#define INTC_ICDIPTR42_LMTI_SHIFT (24u) + +#define INTC_ICDIPTR43_SSII0_SHIFT (0u) +#define INTC_ICDIPTR43_SSIRXI0_SHIFT (8u) +#define INTC_ICDIPTR43_SSITXI0_SHIFT (16u) +#define INTC_ICDIPTR43_SSII1_SHIFT (24u) + +#define INTC_ICDIPTR44_SSIRXI1_SHIFT (0u) +#define INTC_ICDIPTR44_SSITXI1_SHIFT (8u) +#define INTC_ICDIPTR44_SSII2_SHIFT (16u) +#define INTC_ICDIPTR44_SSIRTI2_SHIFT (24u) + +#define INTC_ICDIPTR45_SSII3_SHIFT (0u) +#define INTC_ICDIPTR45_SSIRXI3_SHIFT (8u) +#define INTC_ICDIPTR45_SSITXI3_SHIFT (16u) +#define INTC_ICDIPTR45_SSII4_SHIFT (24u) + +#define INTC_ICDIPTR46_SSIRTI4_SHIFT (0u) +#define INTC_ICDIPTR46_SSII5_SHIFT (8u) +#define INTC_ICDIPTR46_SSIRXI5_SHIFT (16u) +#define INTC_ICDIPTR46_SSITXI5_SHIFT (24u) + +#define INTC_ICDIPTR47_SPDIFI_SHIFT (0u) +#define INTC_ICDIPTR47_INTIICTEI0_SHIFT (8u) +#define INTC_ICDIPTR47_INTIICRI0_SHIFT (16u) +#define INTC_ICDIPTR47_INTIICTI0_SHIFT (24u) + +#define INTC_ICDIPTR48_INTIICSPI0_SHIFT (0u) +#define INTC_ICDIPTR48_INTIICSTI0_SHIFT (8u) +#define INTC_ICDIPTR48_INTIICNAKI0_SHIFT (16u) +#define INTC_ICDIPTR48_INTIICALI0_SHIFT (24u) + +#define INTC_ICDIPTR49_INTIICTMOI0_SHIFT (0u) +#define INTC_ICDIPTR49_INTIICTEI1_SHIFT (8u) +#define INTC_ICDIPTR49_INTIICRI1_SHIFT (16u) +#define INTC_ICDIPTR49_INTIICTI1_SHIFT (24u) + +#define INTC_ICDIPTR50_INTIICSPI1_SHIFT (0u) +#define INTC_ICDIPTR50_INTIICSTI1_SHIFT (8u) +#define INTC_ICDIPTR50_INTIICNAKI1_SHIFT (16u) +#define INTC_ICDIPTR50_INTIICALI1_SHIFT (24u) + +#define INTC_ICDIPTR51_INTIICTMOI1_SHIFT (0u) +#define INTC_ICDIPTR51_INTIICTEI2_SHIFT (8u) +#define INTC_ICDIPTR51_INTIICRI2_SHIFT (16u) +#define INTC_ICDIPTR51_INTIICTI2_SHIFT (24u) + +#define INTC_ICDIPTR52_INTIICSPI2_SHIFT (0u) +#define INTC_ICDIPTR52_INTIICSTI2_SHIFT (8u) +#define INTC_ICDIPTR52_INTIICNAKI2_SHIFT (16u) +#define INTC_ICDIPTR52_INTIICALI2_SHIFT (24u) + +#define INTC_ICDIPTR53_INTIICTMOI2_SHIFT (0u) +#define INTC_ICDIPTR53_INTIICTEI3_SHIFT (8u) +#define INTC_ICDIPTR53_INTIICRI3_SHIFT (16u) +#define INTC_ICDIPTR53_INTIICTI3_SHIFT (24u) + +#define INTC_ICDIPTR54_INTIICSPI3_SHIFT (0u) +#define INTC_ICDIPTR54_INTIICSTI3_SHIFT (8u) +#define INTC_ICDIPTR54_INTIICNAKI3_SHIFT (16u) +#define INTC_ICDIPTR54_INTIICALI3_SHIFT (24u) + +#define INTC_ICDIPTR55_INTIICTMOI3_SHIFT (0u) +#define INTC_ICDIPTR55_BRI0_SHIFT (8u) +#define INTC_ICDIPTR55_ERI0_SHIFT (16u) +#define INTC_ICDIPTR55_RXI0_SHIFT (24u) + +#define INTC_ICDIPTR56_TXI0_SHIFT (0u) +#define INTC_ICDIPTR56_BRI1_SHIFT (8u) +#define INTC_ICDIPTR56_ERI1_SHIFT (16u) +#define INTC_ICDIPTR56_RXI1_SHIFT (24u) + +#define INTC_ICDIPTR57_TXI1_SHIFT (0u) +#define INTC_ICDIPTR57_BRI2_SHIFT (8u) +#define INTC_ICDIPTR57_ERI2_SHIFT (16u) +#define INTC_ICDIPTR57_RXI2_SHIFT (24u) + +#define INTC_ICDIPTR58_TXI2_SHIFT (0u) +#define INTC_ICDIPTR58_BRI3_SHIFT (8u) +#define INTC_ICDIPTR58_ERI3_SHIFT (16u) +#define INTC_ICDIPTR58_RXI3_SHIFT (24u) + +#define INTC_ICDIPTR59_TXI3_SHIFT (0u) +#define INTC_ICDIPTR59_BRI4_SHIFT (8u) +#define INTC_ICDIPTR59_ERI4_SHIFT (16u) +#define INTC_ICDIPTR59_RXI4_SHIFT (24u) + +#define INTC_ICDIPTR60_TXI4_SHIFT (0u) +#define INTC_ICDIPTR60_BRI5_SHIFT (8u) +#define INTC_ICDIPTR60_ERI5_SHIFT (16u) +#define INTC_ICDIPTR60_RXI5_SHIFT (24u) + +#define INTC_ICDIPTR61_TXI5_SHIFT (0u) +#define INTC_ICDIPTR61_BRI6_SHIFT (8u) +#define INTC_ICDIPTR61_ERI6_SHIFT (16u) +#define INTC_ICDIPTR61_RXI6_SHIFT (24u) + +#define INTC_ICDIPTR62_TXI6_SHIFT (0u) +#define INTC_ICDIPTR62_BRI7_SHIFT (8u) +#define INTC_ICDIPTR62_ERI7_SHIFT (16u) +#define INTC_ICDIPTR62_RXI7_SHIFT (24u) + +#define INTC_ICDIPTR63_TXI7_SHIFT (0u) +#define INTC_ICDIPTR63_INTRCANGERR_SHIFT (8u) +#define INTC_ICDIPTR63_INTRCANGRECC_SHIFT (16u) +#define INTC_ICDIPTR63_INTRCAN0REC_SHIFT (24u) + +#define INTC_ICDIPTR64_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDIPTR64_INTRCAN0TRX_SHIFT (8u) +#define INTC_ICDIPTR64_INTRCAN1REC_SHIFT (16u) +#define INTC_ICDIPTR64_INTRCAN1ERR_SHIFT (24u) + +#define INTC_ICDIPTR65_INTRCAN1TRX_SHIFT (0u) +#define INTC_ICDIPTR65_INTRCAN2REC_SHIFT (8u) +#define INTC_ICDIPTR65_INTRCAN2ERR_SHIFT (16u) +#define INTC_ICDIPTR65_INTRCAN2TRX_SHIFT (24u) + +#define INTC_ICDIPTR66_INTRCAN3REC_SHIFT (0u) +#define INTC_ICDIPTR66_INTRCAN3ERR_SHIFT (8u) +#define INTC_ICDIPTR66_INTRCAN3TRX_SHIFT (16u) +#define INTC_ICDIPTR66_INTRCAN4REC_SHIFT (24u) + +#define INTC_ICDIPTR67_INTRCAN4ERR_SHIFT (0u) +#define INTC_ICDIPTR67_INTRCAN4TRX_SHIFT (8u) +#define INTC_ICDIPTR67_SPEI0_SHIFT (16u) +#define INTC_ICDIPTR67_SPRI0_SHIFT (24u) + +#define INTC_ICDIPTR68_SPTI0_SHIFT (0u) +#define INTC_ICDIPTR68_SPEI1_SHIFT (8u) +#define INTC_ICDIPTR68_SPRI1_SHIFT (16u) +#define INTC_ICDIPTR68_SPTI1_SHIFT (24u) + +#define INTC_ICDIPTR69_SPEI2_SHIFT (0u) +#define INTC_ICDIPTR69_SPRI2_SHIFT (8u) +#define INTC_ICDIPTR69_SPTI2_SHIFT (16u) +#define INTC_ICDIPTR69_SPEI3_SHIFT (24u) + +#define INTC_ICDIPTR70_SPRI3_SHIFT (0u) +#define INTC_ICDIPTR70_SPTI3_SHIFT (8u) +#define INTC_ICDIPTR70_SPEI4_SHIFT (16u) +#define INTC_ICDIPTR70_SPRI4_SHIFT (24u) + +#define INTC_ICDIPTR71_SPTI4_SHIFT (0u) +#define INTC_ICDIPTR71_IEBBTD_SHIFT (8u) +#define INTC_ICDIPTR71_IEBBTERR_SHIFT (16u) +#define INTC_ICDIPTR71_IEBBTSTA_SHIFT (24u) + +#define INTC_ICDIPTR72_IEBBTV_SHIFT (0u) +#define INTC_ICDIPTR72_ISY_SHIFT (8u) +#define INTC_ICDIPTR72_IERR_SHIFT (16u) +#define INTC_ICDIPTR72_ITARG_SHIFT (24u) + +#define INTC_ICDIPTR73_ISEC_SHIFT (0u) +#define INTC_ICDIPTR73_IBUF_SHIFT (8u) +#define INTC_ICDIPTR73_IREADY_SHIFT (16u) +#define INTC_ICDIPTR73_FLSTE_SHIFT (24u) + +#define INTC_ICDIPTR74_FLTENDI_SHIFT (0u) +#define INTC_ICDIPTR74_FLTREQ0I_SHIFT (8u) +#define INTC_ICDIPTR74_FLTREQ1I_SHIFT (16u) +#define INTC_ICDIPTR74_MMC0_SHIFT (24u) + +#define INTC_ICDIPTR75_MMC1_SHIFT (0u) +#define INTC_ICDIPTR75_MMC2_SHIFT (8u) +#define INTC_ICDIPTR75_SDHI0_3_SHIFT (16u) +#define INTC_ICDIPTR75_SDHI0_0_SHIFT (24u) + +#define INTC_ICDIPTR76_SDHI0_1_SHIFT (0u) +#define INTC_ICDIPTR76_SDHI1_3_SHIFT (8u) +#define INTC_ICDIPTR76_SDHI1_0_SHIFT (16u) +#define INTC_ICDIPTR76_SDHI1_1_SHIFT (24u) + +#define INTC_ICDIPTR77_ARM_SHIFT (0u) +#define INTC_ICDIPTR77_PRD_SHIFT (8u) +#define INTC_ICDIPTR77_CUP_SHIFT (16u) +#define INTC_ICDIPTR77_SCUAI0_SHIFT (24u) + +#define INTC_ICDIPTR78_SCUAI1_SHIFT (0u) +#define INTC_ICDIPTR78_SCUFDI0_SHIFT (8u) +#define INTC_ICDIPTR78_SCUFDI1_SHIFT (16u) +#define INTC_ICDIPTR78_SCUFDI2_SHIFT (24u) + +#define INTC_ICDIPTR79_SCUFDI3_SHIFT (0u) +#define INTC_ICDIPTR79_SCUFUI0_SHIFT (8u) +#define INTC_ICDIPTR79_SCUFUI1_SHIFT (16u) +#define INTC_ICDIPTR79_SCUFUI2_SHIFT (24u) + +#define INTC_ICDIPTR80_SCUFUI3_SHIFT (0u) +#define INTC_ICDIPTR80_SCUDVI0_SHIFT (8u) +#define INTC_ICDIPTR80_SCUDVI1_SHIFT (16u) +#define INTC_ICDIPTR80_SCUDVI2_SHIFT (24u) + +#define INTC_ICDIPTR81_SCUDVI3_SHIFT (0u) +#define INTC_ICDIPTR81_MLB_CINT_SHIFT (8u) +#define INTC_ICDIPTR81_MLB_SINT_SHIFT (16u) +#define INTC_ICDIPTR81_DRC0_SHIFT (24u) + +#define INTC_ICDIPTR82_DRC1_SHIFT (0u) +#define INTC_ICDIPTR82_LINI0_INT_T_SHIFT (24u) + +#define INTC_ICDIPTR83_LINI0_INT_R_SHIFT (0u) +#define INTC_ICDIPTR83_LINI0_INT_S_SHIFT (8u) +#define INTC_ICDIPTR83_LINI0_INT_M_SHIFT (16u) +#define INTC_ICDIPTR83_LINI1_INT_T_SHIFT (24u) + +#define INTC_ICDIPTR84_LINI1_INT_R_SHIFT (0u) +#define INTC_ICDIPTR84_LINI1_INT_S_SHIFT (8u) +#define INTC_ICDIPTR84_LINI1_INT_M_SHIFT (16u) + +#define INTC_ICDIPTR86_ERI0_SHIFT (24u) + +#define INTC_ICDIPTR87_RXI0_SHIFT (0u) +#define INTC_ICDIPTR87_TXI0_SHIFT (8u) +#define INTC_ICDIPTR87_TEI0_SHIFT (16u) +#define INTC_ICDIPTR87_ERI1_SHIFT (24u) + +#define INTC_ICDIPTR88_RXI1_SHIFT (0u) +#define INTC_ICDIPTR88_TXI1_SHIFT (8u) +#define INTC_ICDIPTR88_TEI1_SHIFT (16u) +#define INTC_ICDIPTR88_AVBI_DATA_SHIFT (24u) + +#define INTC_ICDIPTR89_AVBI_ERROR_SHIFT (0u) +#define INTC_ICDIPTR89_AVBI_MANAGE_SHIFT (8u) +#define INTC_ICDIPTR89_AVBI_MAC_SHIFT (16u) +#define INTC_ICDIPTR89_ETHERI_SHIFT (24u) + +#define INTC_ICDIPTR91_CEUI_SHIFT (0u) + +#define INTC_ICDIPTR95_H2XMLB_ERRINT_SHIFT (8u) +#define INTC_ICDIPTR95_H2XIC1_ERRINT_SHIFT (16u) +#define INTC_ICDIPTR95_X2HPERI1_ERRINT_SHIFT (24u) + +#define INTC_ICDIPTR96_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDIPTR96_X2HPERI34_ERRINT_SHIFT (8u) +#define INTC_ICDIPTR96_X2HPERI5_ERRINT_SHIFT (16u) +#define INTC_ICDIPTR96_X2HPERI67_ERRINT_SHIFT (24u) + +#define INTC_ICDIPTR97_X2HDBGR_ERRINT_SHIFT (0u) +#define INTC_ICDIPTR97_X2HBSC_ERRINT_SHIFT (8u) +#define INTC_ICDIPTR97_X2HSPI1_ERRINT_SHIFT (16u) +#define INTC_ICDIPTR97_X2HSPI2_ERRINT_SHIFT (24u) + +#define INTC_ICDIPTR98_PRRI_SHIFT (0u) +#define INTC_ICDIPTR98_IFEI0_SHIFT (8u) +#define INTC_ICDIPTR98_OFFI0_SHIFT (16u) +#define INTC_ICDIPTR98_PFVEI0_SHIFT (24u) + +#define INTC_ICDIPTR99_IFEI1_SHIFT (0u) +#define INTC_ICDIPTR99_OFFI1_SHIFT (8u) +#define INTC_ICDIPTR99_PFVEI1_SHIFT (16u) + +#define INTC_ICDIPTR104_TINT0_SHIFT (0u) +#define INTC_ICDIPTR104_TINT1_SHIFT (8u) +#define INTC_ICDIPTR104_TINT2_SHIFT (16u) +#define INTC_ICDIPTR104_TINT3_SHIFT (24u) + +#define INTC_ICDIPTR105_TINT4_SHIFT (0u) +#define INTC_ICDIPTR105_TINT5_SHIFT (8u) +#define INTC_ICDIPTR105_TINT6_SHIFT (16u) +#define INTC_ICDIPTR105_TINT7_SHIFT (24u) + +#define INTC_ICDIPTR106_TINT8_SHIFT (0u) +#define INTC_ICDIPTR106_TINT9_SHIFT (8u) +#define INTC_ICDIPTR106_TINT10_SHIFT (16u) +#define INTC_ICDIPTR106_TINT11_SHIFT (24u) + +#define INTC_ICDIPTR107_TINT12_SHIFT (0u) +#define INTC_ICDIPTR107_TINT13_SHIFT (8u) +#define INTC_ICDIPTR107_TINT14_SHIFT (16u) +#define INTC_ICDIPTR107_TINT15_SHIFT (24u) + +#define INTC_ICDIPTR108_TINT16_SHIFT (0u) +#define INTC_ICDIPTR108_TINT17_SHIFT (8u) +#define INTC_ICDIPTR108_TINT18_SHIFT (16u) +#define INTC_ICDIPTR108_TINT19_SHIFT (24u) + +#define INTC_ICDIPTR109_TINT20_SHIFT (0u) +#define INTC_ICDIPTR109_TINT21_SHIFT (8u) +#define INTC_ICDIPTR109_TINT22_SHIFT (16u) +#define INTC_ICDIPTR109_TINT23_SHIFT (24u) + +#define INTC_ICDIPTR110_TINT24_SHIFT (0u) +#define INTC_ICDIPTR110_TINT25_SHIFT (8u) +#define INTC_ICDIPTR110_TINT26_SHIFT (16u) +#define INTC_ICDIPTR110_TINT27_SHIFT (24u) + +#define INTC_ICDIPTR111_TINT28_SHIFT (0u) +#define INTC_ICDIPTR111_TINT29_SHIFT (8u) +#define INTC_ICDIPTR111_TINT30_SHIFT (16u) +#define INTC_ICDIPTR111_TINT31_SHIFT (24u) + +#define INTC_ICDIPTR112_TINT32_SHIFT (0u) +#define INTC_ICDIPTR112_TINT33_SHIFT (8u) +#define INTC_ICDIPTR112_TINT34_SHIFT (16u) +#define INTC_ICDIPTR112_TINT35_SHIFT (24u) + +#define INTC_ICDIPTR113_TINT36_SHIFT (0u) +#define INTC_ICDIPTR113_TINT37_SHIFT (8u) +#define INTC_ICDIPTR113_TINT38_SHIFT (16u) +#define INTC_ICDIPTR113_TINT39_SHIFT (24u) + +#define INTC_ICDIPTR114_TINT40_SHIFT (0u) +#define INTC_ICDIPTR114_TINT41_SHIFT (8u) +#define INTC_ICDIPTR114_TINT42_SHIFT (16u) +#define INTC_ICDIPTR114_TINT43_SHIFT (24u) + +#define INTC_ICDIPTR115_TINT44_SHIFT (0u) +#define INTC_ICDIPTR115_TINT45_SHIFT (8u) +#define INTC_ICDIPTR115_TINT46_SHIFT (16u) +#define INTC_ICDIPTR115_TINT47_SHIFT (24u) + +#define INTC_ICDIPTR116_TINT48_SHIFT (0u) +#define INTC_ICDIPTR116_TINT49_SHIFT (8u) +#define INTC_ICDIPTR116_TINT50_SHIFT (16u) +#define INTC_ICDIPTR116_TINT51_SHIFT (24u) + +#define INTC_ICDIPTR117_TINT52_SHIFT (0u) +#define INTC_ICDIPTR117_TINT53_SHIFT (8u) +#define INTC_ICDIPTR117_TINT54_SHIFT (16u) +#define INTC_ICDIPTR117_TINT55_SHIFT (24u) + +#define INTC_ICDIPTR118_TINT56_SHIFT (0u) +#define INTC_ICDIPTR118_TINT57_SHIFT (8u) +#define INTC_ICDIPTR118_TINT58_SHIFT (16u) +#define INTC_ICDIPTR118_TINT59_SHIFT (24u) + +#define INTC_ICDIPTR119_TINT60_SHIFT (0u) +#define INTC_ICDIPTR119_TINT61_SHIFT (8u) +#define INTC_ICDIPTR119_TINT62_SHIFT (16u) +#define INTC_ICDIPTR119_TINT63_SHIFT (24u) + +#define INTC_ICDIPTR120_TINT64_SHIFT (0u) +#define INTC_ICDIPTR120_TINT65_SHIFT (8u) +#define INTC_ICDIPTR120_TINT66_SHIFT (16u) +#define INTC_ICDIPTR120_TINT67_SHIFT (24u) + +#define INTC_ICDIPTR121_TINT68_SHIFT (0u) +#define INTC_ICDIPTR121_TINT69_SHIFT (8u) +#define INTC_ICDIPTR121_TINT70_SHIFT (16u) +#define INTC_ICDIPTR121_TINT71_SHIFT (24u) + +#define INTC_ICDIPTR122_TINT72_SHIFT (0u) +#define INTC_ICDIPTR122_TINT73_SHIFT (8u) +#define INTC_ICDIPTR122_TINT74_SHIFT (16u) +#define INTC_ICDIPTR122_TINT75_SHIFT (24u) + +#define INTC_ICDIPTR123_TINT76_SHIFT (0u) +#define INTC_ICDIPTR123_TINT77_SHIFT (8u) +#define INTC_ICDIPTR123_TINT78_SHIFT (16u) +#define INTC_ICDIPTR123_TINT79_SHIFT (24u) + +#define INTC_ICDIPTR124_TINT80_SHIFT (0u) +#define INTC_ICDIPTR124_TINT81_SHIFT (8u) +#define INTC_ICDIPTR124_TINT82_SHIFT (16u) +#define INTC_ICDIPTR124_TINT83_SHIFT (24u) + +#define INTC_ICDIPTR125_TINT84_SHIFT (0u) +#define INTC_ICDIPTR125_TINT85_SHIFT (8u) +#define INTC_ICDIPTR125_TINT86_SHIFT (16u) +#define INTC_ICDIPTR125_TINT87_SHIFT (24u) + +#define INTC_ICDIPTR126_TINT88_SHIFT (0u) +#define INTC_ICDIPTR126_TINT89_SHIFT (8u) +#define INTC_ICDIPTR126_TINT90_SHIFT (16u) +#define INTC_ICDIPTR126_TINT91_SHIFT (24u) + +#define INTC_ICDIPTR127_TINT92_SHIFT (0u) +#define INTC_ICDIPTR127_TINT93_SHIFT (8u) +#define INTC_ICDIPTR127_TINT94_SHIFT (16u) +#define INTC_ICDIPTR127_TINT95_SHIFT (24u) + +#define INTC_ICDIPTR128_TINT96_SHIFT (0u) +#define INTC_ICDIPTR128_TINT97_SHIFT (8u) +#define INTC_ICDIPTR128_TINT98_SHIFT (16u) +#define INTC_ICDIPTR128_TINT99_SHIFT (24u) + +#define INTC_ICDIPTR129_TINT100_SHIFT (0u) +#define INTC_ICDIPTR129_TINT101_SHIFT (8u) +#define INTC_ICDIPTR129_TINT102_SHIFT (16u) +#define INTC_ICDIPTR129_TINT103_SHIFT (24u) + +#define INTC_ICDIPTR130_TINT104_SHIFT (0u) +#define INTC_ICDIPTR130_TINT105_SHIFT (8u) +#define INTC_ICDIPTR130_TINT106_SHIFT (16u) +#define INTC_ICDIPTR130_TINT107_SHIFT (24u) + +#define INTC_ICDIPTR131_TINT108_SHIFT (0u) +#define INTC_ICDIPTR131_TINT109_SHIFT (8u) +#define INTC_ICDIPTR131_TINT110_SHIFT (16u) +#define INTC_ICDIPTR131_TINT111_SHIFT (24u) + +#define INTC_ICDIPTR132_TINT112_SHIFT (0u) +#define INTC_ICDIPTR132_TINT113_SHIFT (8u) +#define INTC_ICDIPTR132_TINT114_SHIFT (16u) +#define INTC_ICDIPTR132_TINT115_SHIFT (24u) + +#define INTC_ICDIPTR133_TINT116_SHIFT (0u) +#define INTC_ICDIPTR133_TINT117_SHIFT (8u) +#define INTC_ICDIPTR133_TINT118_SHIFT (16u) +#define INTC_ICDIPTR133_TINT119_SHIFT (24u) + +#define INTC_ICDIPTR134_TINT120_SHIFT (0u) +#define INTC_ICDIPTR134_TINT121_SHIFT (8u) +#define INTC_ICDIPTR134_TINT122_SHIFT (16u) +#define INTC_ICDIPTR134_TINT123_SHIFT (24u) + +#define INTC_ICDIPTR135_TINT124_SHIFT (0u) +#define INTC_ICDIPTR135_TINT125_SHIFT (8u) +#define INTC_ICDIPTR135_TINT126_SHIFT (16u) +#define INTC_ICDIPTR135_TINT127_SHIFT (24u) + +#define INTC_ICDIPTR136_TINT128_SHIFT (0u) +#define INTC_ICDIPTR136_TINT129_SHIFT (8u) +#define INTC_ICDIPTR136_TINT130_SHIFT (16u) +#define INTC_ICDIPTR136_TINT131_SHIFT (24u) + +#define INTC_ICDIPTR137_TINT132_SHIFT (0u) +#define INTC_ICDIPTR137_TINT133_SHIFT (8u) +#define INTC_ICDIPTR137_TINT134_SHIFT (16u) +#define INTC_ICDIPTR137_TINT135_SHIFT (24u) + +#define INTC_ICDIPTR138_TINT136_SHIFT (0u) +#define INTC_ICDIPTR138_TINT137_SHIFT (8u) +#define INTC_ICDIPTR138_TINT138_SHIFT (16u) +#define INTC_ICDIPTR138_TINT139_SHIFT (24u) + +#define INTC_ICDIPTR139_TINT140_SHIFT (0u) +#define INTC_ICDIPTR139_TINT141_SHIFT (8u) +#define INTC_ICDIPTR139_TINT142_SHIFT (16u) +#define INTC_ICDIPTR139_TINT143_SHIFT (24u) + +#define INTC_ICDIPTR140_TINT144_SHIFT (0u) +#define INTC_ICDIPTR140_TINT145_SHIFT (8u) +#define INTC_ICDIPTR140_TINT146_SHIFT (16u) +#define INTC_ICDIPTR140_TINT147_SHIFT (24u) + +#define INTC_ICDIPTR141_TINT148_SHIFT (0u) +#define INTC_ICDIPTR141_TINT149_SHIFT (8u) +#define INTC_ICDIPTR141_TINT150_SHIFT (16u) +#define INTC_ICDIPTR141_TINT151_SHIFT (24u) + +#define INTC_ICDIPTR142_TINT152_SHIFT (0u) +#define INTC_ICDIPTR142_TINT153_SHIFT (8u) +#define INTC_ICDIPTR142_TINT154_SHIFT (16u) +#define INTC_ICDIPTR142_TINT155_SHIFT (24u) + +#define INTC_ICDIPTR143_TINT156_SHIFT (0u) +#define INTC_ICDIPTR143_TINT157_SHIFT (8u) +#define INTC_ICDIPTR143_TINT158_SHIFT (16u) +#define INTC_ICDIPTR143_TINT159_SHIFT (24u) + +#define INTC_ICDIPTR144_TINT160_SHIFT (0u) +#define INTC_ICDIPTR144_TINT161_SHIFT (8u) +#define INTC_ICDIPTR144_TINT162_SHIFT (16u) +#define INTC_ICDIPTR144_TINT163_SHIFT (24u) + +#define INTC_ICDIPTR145_TINT164_SHIFT (0u) +#define INTC_ICDIPTR145_TINT165_SHIFT (8u) +#define INTC_ICDIPTR145_TINT166_SHIFT (16u) +#define INTC_ICDIPTR145_TINT167_SHIFT (24u) + +#define INTC_ICDIPTR146_TINT168_SHIFT (0u) +#define INTC_ICDIPTR146_TINT169_SHIFT (8u) +#define INTC_ICDIPTR146_TINT170_SHIFT (16u) + +#define INTC_ICDICFR0_SW0_0_SHIFT (0u) +#define INTC_ICDICFR0_SW0_1_SHIFT (1u) +#define INTC_ICDICFR0_SW1_0_SHIFT (2u) +#define INTC_ICDICFR0_SW1_1_SHIFT (3u) +#define INTC_ICDICFR0_SW2_0_SHIFT (4u) +#define INTC_ICDICFR0_SW2_1_SHIFT (5u) +#define INTC_ICDICFR0_SW3_0_SHIFT (6u) +#define INTC_ICDICFR0_SW3_1_SHIFT (7u) +#define INTC_ICDICFR0_SW4_0_SHIFT (8u) +#define INTC_ICDICFR0_SW4_1_SHIFT (9u) +#define INTC_ICDICFR0_SW5_0_SHIFT (10u) +#define INTC_ICDICFR0_SW5_1_SHIFT (11u) +#define INTC_ICDICFR0_SW6_0_SHIFT (12u) +#define INTC_ICDICFR0_SW6_1_SHIFT (13u) +#define INTC_ICDICFR0_SW7_0_SHIFT (14u) +#define INTC_ICDICFR0_SW7_1_SHIFT (15u) +#define INTC_ICDICFR0_SW8_0_SHIFT (16u) +#define INTC_ICDICFR0_SW8_1_SHIFT (17u) +#define INTC_ICDICFR0_SW9_0_SHIFT (18u) +#define INTC_ICDICFR0_SW9_1_SHIFT (19u) +#define INTC_ICDICFR0_SW10_0_SHIFT (20u) +#define INTC_ICDICFR0_SW10_1_SHIFT (21u) +#define INTC_ICDICFR0_SW11_0_SHIFT (22u) +#define INTC_ICDICFR0_SW11_1_SHIFT (23u) +#define INTC_ICDICFR0_SW12_0_SHIFT (24u) +#define INTC_ICDICFR0_SW12_1_SHIFT (25u) +#define INTC_ICDICFR0_SW13_0_SHIFT (26u) +#define INTC_ICDICFR0_SW13_1_SHIFT (27u) +#define INTC_ICDICFR0_SW14_0_SHIFT (28u) +#define INTC_ICDICFR0_SW14_1_SHIFT (29u) +#define INTC_ICDICFR0_SW15_0_SHIFT (30u) +#define INTC_ICDICFR0_SW15_1_SHIFT (31u) + +#define INTC_ICDICFR1_PMUIRQ0_0_SHIFT (0u) +#define INTC_ICDICFR1_PMUIRQ0_1_SHIFT (1u) +#define INTC_ICDICFR1_COMMRX0_0_SHIFT (2u) +#define INTC_ICDICFR1_COMMRX0_1_SHIFT (3u) +#define INTC_ICDICFR1_COMMTX0_0_SHIFT (4u) +#define INTC_ICDICFR1_COMMTX0_1_SHIFT (5u) +#define INTC_ICDICFR1_CTIIRQ0_0_SHIFT (6u) +#define INTC_ICDICFR1_CTIIRQ0_1_SHIFT (7u) + +#define INTC_ICDICFR2_IRQ0_0_SHIFT (0u) +#define INTC_ICDICFR2_IRQ0_1_SHIFT (1u) +#define INTC_ICDICFR2_IRQ1_0_SHIFT (2u) +#define INTC_ICDICFR2_IRQ1_1_SHIFT (3u) +#define INTC_ICDICFR2_IRQ2_0_SHIFT (4u) +#define INTC_ICDICFR2_IRQ2_1_SHIFT (5u) +#define INTC_ICDICFR2_IRQ3_0_SHIFT (6u) +#define INTC_ICDICFR2_IRQ3_1_SHIFT (7u) +#define INTC_ICDICFR2_IRQ4_0_SHIFT (8u) +#define INTC_ICDICFR2_IRQ4_1_SHIFT (9u) +#define INTC_ICDICFR2_IRQ5_0_SHIFT (10u) +#define INTC_ICDICFR2_IRQ5_1_SHIFT (11u) +#define INTC_ICDICFR2_IRQ6_0_SHIFT (12u) +#define INTC_ICDICFR2_IRQ6_1_SHIFT (13u) +#define INTC_ICDICFR2_IRQ7_0_SHIFT (14u) +#define INTC_ICDICFR2_IRQ7_1_SHIFT (15u) +#define INTC_ICDICFR2_PL310ERR_0_SHIFT (16u) +#define INTC_ICDICFR2_PL310ERR_1_SHIFT (17u) +#define INTC_ICDICFR2_DMAINT0_0_SHIFT (18u) +#define INTC_ICDICFR2_DMAINT0_1_SHIFT (19u) +#define INTC_ICDICFR2_DMAINT1_0_SHIFT (20u) +#define INTC_ICDICFR2_DMAINT1_1_SHIFT (21u) +#define INTC_ICDICFR2_DMAINT2_0_SHIFT (22u) +#define INTC_ICDICFR2_DMAINT2_1_SHIFT (23u) +#define INTC_ICDICFR2_DMAINT3_0_SHIFT (24u) +#define INTC_ICDICFR2_DMAINT3_1_SHIFT (25u) +#define INTC_ICDICFR2_DMAINT4_0_SHIFT (26u) +#define INTC_ICDICFR2_DMAINT4_1_SHIFT (27u) +#define INTC_ICDICFR2_DMAINT5_0_SHIFT (28u) +#define INTC_ICDICFR2_DMAINT5_1_SHIFT (29u) +#define INTC_ICDICFR2_DMAINT6_0_SHIFT (30u) +#define INTC_ICDICFR2_DMAINT6_1_SHIFT (31u) + +#define INTC_ICDICFR3_DMAINT7_0_SHIFT (0u) +#define INTC_ICDICFR3_DMAINT7_1_SHIFT (1u) +#define INTC_ICDICFR3_DMAINT8_0_SHIFT (2u) +#define INTC_ICDICFR3_DMAINT8_1_SHIFT (3u) +#define INTC_ICDICFR3_DMAINT9_0_SHIFT (4u) +#define INTC_ICDICFR3_DMAINT9_1_SHIFT (5u) +#define INTC_ICDICFR3_DMAINT10_0_SHIFT (6u) +#define INTC_ICDICFR3_DMAINT10_1_SHIFT (7u) +#define INTC_ICDICFR3_DMAINT11_0_SHIFT (8u) +#define INTC_ICDICFR3_DMAINT11_1_SHIFT (9u) +#define INTC_ICDICFR3_DMAINT12_0_SHIFT (10u) +#define INTC_ICDICFR3_DMAINT12_1_SHIFT (11u) +#define INTC_ICDICFR3_DMAINT13_0_SHIFT (12u) +#define INTC_ICDICFR3_DMAINT13_1_SHIFT (13u) +#define INTC_ICDICFR3_DMAINT14_0_SHIFT (14u) +#define INTC_ICDICFR3_DMAINT14_1_SHIFT (15u) +#define INTC_ICDICFR3_DMAINT15_0_SHIFT (16u) +#define INTC_ICDICFR3_DMAINT15_1_SHIFT (17u) +#define INTC_ICDICFR3_DMAERR_0_SHIFT (18u) +#define INTC_ICDICFR3_DMAERR_1_SHIFT (19u) + +#define INTC_ICDICFR4_USBI0_0_SHIFT (18u) +#define INTC_ICDICFR4_USBI0_1_SHIFT (19u) +#define INTC_ICDICFR4_USBI1_0_SHIFT (20u) +#define INTC_ICDICFR4_USBI1_1_SHIFT (21u) +#define INTC_ICDICFR4_S0_VI_VSYNC0_0_SHIFT (22u) +#define INTC_ICDICFR4_S0_VI_VSYNC0_1_SHIFT (23u) +#define INTC_ICDICFR4_S0_LO_VSYNC0_0_SHIFT (24u) +#define INTC_ICDICFR4_S0_LO_VSYNC0_1_SHIFT (25u) +#define INTC_ICDICFR4_S0_VSYNCERR0_0_SHIFT (26u) +#define INTC_ICDICFR4_S0_VSYNCERR0_1_SHIFT (27u) +#define INTC_ICDICFR4_GR3_VLINE0_0_SHIFT (28u) +#define INTC_ICDICFR4_GR3_VLINE0_1_SHIFT (29u) +#define INTC_ICDICFR4_S0_VFIELD0_0_SHIFT (30u) +#define INTC_ICDICFR4_S0_VFIELD0_1_SHIFT (31u) + +#define INTC_ICDICFR5_IV1_VBUFERR0_0_SHIFT (0u) +#define INTC_ICDICFR5_IV1_VBUFERR0_1_SHIFT (1u) +#define INTC_ICDICFR5_IV3_VBUFERR0_0_SHIFT (2u) +#define INTC_ICDICFR5_IV3_VBUFERR0_1_SHIFT (3u) +#define INTC_ICDICFR5_IV5_VBUFERR0_0_SHIFT (4u) +#define INTC_ICDICFR5_IV5_VBUFERR0_1_SHIFT (5u) +#define INTC_ICDICFR5_IV6_VBUFERR0_0_SHIFT (6u) +#define INTC_ICDICFR5_IV6_VBUFERR0_1_SHIFT (7u) +#define INTC_ICDICFR5_S0_WLINE0_0_SHIFT (8u) +#define INTC_ICDICFR5_S0_WLINE0_1_SHIFT (9u) +#define INTC_ICDICFR5_S1_VI_VSYNC0_0_SHIFT (10u) +#define INTC_ICDICFR5_S1_VI_VSYNC0_1_SHIFT (11u) +#define INTC_ICDICFR5_S1_LO_VSYNC0_0_SHIFT (12u) +#define INTC_ICDICFR5_S1_LO_VSYNC0_1_SHIFT (13u) +#define INTC_ICDICFR5_S1_VSYNCERR0_0_SHIFT (14u) +#define INTC_ICDICFR5_S1_VSYNCERR0_1_SHIFT (15u) +#define INTC_ICDICFR5_S1_VFIELD0_0_SHIFT (16u) +#define INTC_ICDICFR5_S1_VFIELD0_1_SHIFT (17u) +#define INTC_ICDICFR5_IV2_VBUFERR0_0_SHIFT (18u) +#define INTC_ICDICFR5_IV2_VBUFERR0_1_SHIFT (19u) +#define INTC_ICDICFR5_IV4_VBUFERR0_0_SHIFT (20u) +#define INTC_ICDICFR5_IV4_VBUFERR0_1_SHIFT (21u) +#define INTC_ICDICFR5_S1_WLINE0_0_SHIFT (22u) +#define INTC_ICDICFR5_S1_WLINE0_1_SHIFT (23u) +#define INTC_ICDICFR5_OIR_VI_VSYNC0_0_SHIFT (24u) +#define INTC_ICDICFR5_OIR_VI_VSYNC0_1_SHIFT (25u) +#define INTC_ICDICFR5_OIR_LO_VSYNC0_0_SHIFT (26u) +#define INTC_ICDICFR5_OIR_LO_VSYNC0_1_SHIFT (27u) +#define INTC_ICDICFR5_OIR_VSYNCERR0_0_SHIFT (28u) +#define INTC_ICDICFR5_OIR_VSYNCERR0_1_SHIFT (29u) +#define INTC_ICDICFR5_OIR_VFIELD0_0_SHIFT (30u) +#define INTC_ICDICFR5_OIR_VFIELD0_1_SHIFT (31u) + +#define INTC_ICDICFR6_IV7_VBUFERR0_0_SHIFT (0u) +#define INTC_ICDICFR6_IV7_VBUFERR0_1_SHIFT (1u) +#define INTC_ICDICFR6_IV8_VBUFERR0_0_SHIFT (2u) +#define INTC_ICDICFR6_IV8_VBUFERR0_1_SHIFT (3u) +#define INTC_ICDICFR6_S0_VI_VSYNC1_0_SHIFT (6u) +#define INTC_ICDICFR6_S0_VI_VSYNC1_1_SHIFT (7u) +#define INTC_ICDICFR6_S0_LO_VSYNC1_0_SHIFT (8u) +#define INTC_ICDICFR6_S0_LO_VSYNC1_1_SHIFT (9u) +#define INTC_ICDICFR6_S0_VSYNCERR1_0_SHIFT (10u) +#define INTC_ICDICFR6_S0_VSYNCERR1_1_SHIFT (11u) +#define INTC_ICDICFR6_GR3_VLINE1_0_SHIFT (12u) +#define INTC_ICDICFR6_GR3_VLINE1_1_SHIFT (13u) +#define INTC_ICDICFR6_S0_VFIELD1_0_SHIFT (14u) +#define INTC_ICDICFR6_S0_VFIELD1_1_SHIFT (15u) +#define INTC_ICDICFR6_IV1_VBUFERR1_0_SHIFT (16u) +#define INTC_ICDICFR6_IV1_VBUFERR1_1_SHIFT (17u) +#define INTC_ICDICFR6_IV3_VBUFERR1_0_SHIFT (18u) +#define INTC_ICDICFR6_IV3_VBUFERR1_1_SHIFT (19u) +#define INTC_ICDICFR6_IV5_VBUFERR1_0_SHIFT (20u) +#define INTC_ICDICFR6_IV5_VBUFERR1_1_SHIFT (21u) +#define INTC_ICDICFR6_IV6_VBUFERR1_0_SHIFT (22u) +#define INTC_ICDICFR6_IV6_VBUFERR1_1_SHIFT (23u) +#define INTC_ICDICFR6_S0_WLINE1_0_SHIFT (24u) +#define INTC_ICDICFR6_S0_WLINE1_1_SHIFT (25u) +#define INTC_ICDICFR6_S1_VI_VSYNC1_0_SHIFT (26u) +#define INTC_ICDICFR6_S1_VI_VSYNC1_1_SHIFT (27u) +#define INTC_ICDICFR6_S1_LO_VSYNC1_0_SHIFT (28u) +#define INTC_ICDICFR6_S1_LO_VSYNC1_1_SHIFT (29u) +#define INTC_ICDICFR6_S1_VSYNCERR1_0_SHIFT (30u) +#define INTC_ICDICFR6_S1_VSYNCERR1_1_SHIFT (31u) + +#define INTC_ICDICFR7_S1_VFIELD1_0_SHIFT (0u) +#define INTC_ICDICFR7_S1_VFIELD1_1_SHIFT (1u) +#define INTC_ICDICFR7_IV2_VBUFERR1_0_SHIFT (2u) +#define INTC_ICDICFR7_IV2_VBUFERR1_1_SHIFT (3u) +#define INTC_ICDICFR7_IV4_VBUFERR1_0_SHIFT (4u) +#define INTC_ICDICFR7_IV4_VBUFERR1_1_SHIFT (5u) +#define INTC_ICDICFR7_S1_WLINE1_0_SHIFT (6u) +#define INTC_ICDICFR7_S1_WLINE1_1_SHIFT (7u) +#define INTC_ICDICFR7_OIR_VI_VSYNC1_0_SHIFT (8u) +#define INTC_ICDICFR7_OIR_VI_VSYNC1_1_SHIFT (9u) +#define INTC_ICDICFR7_OIR_LO_VSYNC1_0_SHIFT (10u) +#define INTC_ICDICFR7_OIR_LO_VSYNC1_1_SHIFT (11u) +#define INTC_ICDICFR7_OIR_VLINE1_0_SHIFT (12u) +#define INTC_ICDICFR7_OIR_VLINE1_1_SHIFT (13u) +#define INTC_ICDICFR7_OIR_VFIELD1_0_SHIFT (14u) +#define INTC_ICDICFR7_OIR_VFIELD1_1_SHIFT (15u) +#define INTC_ICDICFR7_IV7_VBUFERR1_0_SHIFT (16u) +#define INTC_ICDICFR7_IV7_VBUFERR1_1_SHIFT (17u) +#define INTC_ICDICFR7_IV8_VBUFERR1_0_SHIFT (18u) +#define INTC_ICDICFR7_IV8_VBUFERR1_1_SHIFT (19u) +#define INTC_ICDICFR7_IMRDI_0_SHIFT (22u) +#define INTC_ICDICFR7_IMRDI_1_SHIFT (23u) +#define INTC_ICDICFR7_IMR2I0_0_SHIFT (24u) +#define INTC_ICDICFR7_IMR2I0_1_SHIFT (25u) +#define INTC_ICDICFR7_IMR2I1_0_SHIFT (26u) +#define INTC_ICDICFR7_IMR2I1_1_SHIFT (27u) +#define INTC_ICDICFR7_JEDI_0_SHIFT (28u) +#define INTC_ICDICFR7_JEDI_1_SHIFT (29u) +#define INTC_ICDICFR7_JDTI_0_SHIFT (30u) +#define INTC_ICDICFR7_JDTI_1_SHIFT (31u) + +#define INTC_ICDICFR8_CMP0_0_SHIFT (0u) +#define INTC_ICDICFR8_CMP0_1_SHIFT (1u) +#define INTC_ICDICFR8_CMP1_0_SHIFT (2u) +#define INTC_ICDICFR8_CMP1_1_SHIFT (3u) +#define INTC_ICDICFR8_INT0_0_SHIFT (4u) +#define INTC_ICDICFR8_INT0_1_SHIFT (5u) +#define INTC_ICDICFR8_INT1_0_SHIFT (6u) +#define INTC_ICDICFR8_INT1_1_SHIFT (7u) +#define INTC_ICDICFR8_INT2_0_SHIFT (8u) +#define INTC_ICDICFR8_INT2_1_SHIFT (9u) +#define INTC_ICDICFR8_INT3_0_SHIFT (10u) +#define INTC_ICDICFR8_INT3_1_SHIFT (11u) +#define INTC_ICDICFR8_OSTM0TINT_0_SHIFT (12u) +#define INTC_ICDICFR8_OSTM0TINT_1_SHIFT (13u) +#define INTC_ICDICFR8_OSTM1TINT_0_SHIFT (14u) +#define INTC_ICDICFR8_OSTM1TINT_1_SHIFT (15u) +#define INTC_ICDICFR8_CMI_0_SHIFT (16u) +#define INTC_ICDICFR8_CMI_1_SHIFT (17u) +#define INTC_ICDICFR8_WTOUT_0_SHIFT (18u) +#define INTC_ICDICFR8_WTOUT_1_SHIFT (19u) +#define INTC_ICDICFR8_ITI_0_SHIFT (20u) +#define INTC_ICDICFR8_ITI_1_SHIFT (21u) +#define INTC_ICDICFR8_TGI0A_0_SHIFT (22u) +#define INTC_ICDICFR8_TGI0A_1_SHIFT (23u) +#define INTC_ICDICFR8_TGI0B_0_SHIFT (24u) +#define INTC_ICDICFR8_TGI0B_1_SHIFT (25u) +#define INTC_ICDICFR8_TGI0C_0_SHIFT (26u) +#define INTC_ICDICFR8_TGI0C_1_SHIFT (27u) +#define INTC_ICDICFR8_TGI0D_0_SHIFT (28u) +#define INTC_ICDICFR8_TGI0D_1_SHIFT (29u) +#define INTC_ICDICFR8_TGI0V_0_SHIFT (30u) +#define INTC_ICDICFR8_TGI0V_1_SHIFT (31u) + +#define INTC_ICDICFR9_TGI0E_0_SHIFT (0u) +#define INTC_ICDICFR9_TGI0E_1_SHIFT (1u) +#define INTC_ICDICFR9_TGI0F_0_SHIFT (2u) +#define INTC_ICDICFR9_TGI0F_1_SHIFT (3u) +#define INTC_ICDICFR9_TGI1A_0_SHIFT (4u) +#define INTC_ICDICFR9_TGI1A_1_SHIFT (5u) +#define INTC_ICDICFR9_TGI1B_0_SHIFT (6u) +#define INTC_ICDICFR9_TGI1B_1_SHIFT (7u) +#define INTC_ICDICFR9_TGI1V_0_SHIFT (8u) +#define INTC_ICDICFR9_TGI1V_1_SHIFT (9u) +#define INTC_ICDICFR9_TGI1U_0_SHIFT (10u) +#define INTC_ICDICFR9_TGI1U_1_SHIFT (11u) +#define INTC_ICDICFR9_TGI2A_0_SHIFT (12u) +#define INTC_ICDICFR9_TGI2A_1_SHIFT (13u) +#define INTC_ICDICFR9_TGI2B_0_SHIFT (14u) +#define INTC_ICDICFR9_TGI2B_1_SHIFT (15u) +#define INTC_ICDICFR9_TGI2V_0_SHIFT (16u) +#define INTC_ICDICFR9_TGI2V_1_SHIFT (17u) +#define INTC_ICDICFR9_TGI2U_0_SHIFT (18u) +#define INTC_ICDICFR9_TGI2U_1_SHIFT (19u) +#define INTC_ICDICFR9_TGI3A_0_SHIFT (20u) +#define INTC_ICDICFR9_TGI3A_1_SHIFT (21u) +#define INTC_ICDICFR9_TGI3B_0_SHIFT (22u) +#define INTC_ICDICFR9_TGI3B_1_SHIFT (23u) +#define INTC_ICDICFR9_TGI3C_0_SHIFT (24u) +#define INTC_ICDICFR9_TGI3C_1_SHIFT (25u) +#define INTC_ICDICFR9_TGI3D_0_SHIFT (26u) +#define INTC_ICDICFR9_TGI3D_1_SHIFT (27u) +#define INTC_ICDICFR9_TGI3V_0_SHIFT (28u) +#define INTC_ICDICFR9_TGI3V_1_SHIFT (29u) +#define INTC_ICDICFR9_TGI4A_0_SHIFT (30u) +#define INTC_ICDICFR9_TGI4A_1_SHIFT (31u) + +#define INTC_ICDICFR10_TGI4B_0_SHIFT (0u) +#define INTC_ICDICFR10_TGI4B_1_SHIFT (1u) +#define INTC_ICDICFR10_TGI4C_0_SHIFT (2u) +#define INTC_ICDICFR10_TGI4C_1_SHIFT (3u) +#define INTC_ICDICFR10_TGI4D_0_SHIFT (4u) +#define INTC_ICDICFR10_TGI4D_1_SHIFT (5u) +#define INTC_ICDICFR10_TGI4V_0_SHIFT (6u) +#define INTC_ICDICFR10_TGI4V_1_SHIFT (7u) +#define INTC_ICDICFR10_CMI1_0_SHIFT (8u) +#define INTC_ICDICFR10_CMI1_1_SHIFT (9u) +#define INTC_ICDICFR10_CMI2_0_SHIFT (10u) +#define INTC_ICDICFR10_CMI2_1_SHIFT (11u) +#define INTC_ICDICFR10_SGDEI0_0_SHIFT (12u) +#define INTC_ICDICFR10_SGDEI0_1_SHIFT (13u) +#define INTC_ICDICFR10_SGDEI1_0_SHIFT (14u) +#define INTC_ICDICFR10_SGDEI1_1_SHIFT (15u) +#define INTC_ICDICFR10_SGDEI2_0_SHIFT (16u) +#define INTC_ICDICFR10_SGDEI2_1_SHIFT (17u) +#define INTC_ICDICFR10_SGDEI3_0_SHIFT (18u) +#define INTC_ICDICFR10_SGDEI3_1_SHIFT (19u) +#define INTC_ICDICFR10_ADI_0_SHIFT (20u) +#define INTC_ICDICFR10_ADI_1_SHIFT (21u) +#define INTC_ICDICFR10_LMTI_0_SHIFT (22u) +#define INTC_ICDICFR10_LMTI_1_SHIFT (23u) +#define INTC_ICDICFR10_SSII0_0_SHIFT (24u) +#define INTC_ICDICFR10_SSII0_1_SHIFT (25u) +#define INTC_ICDICFR10_SSIRXI0_0_SHIFT (26u) +#define INTC_ICDICFR10_SSIRXI0_1_SHIFT (27u) +#define INTC_ICDICFR10_SSITXI0_0_SHIFT (28u) +#define INTC_ICDICFR10_SSITXI0_1_SHIFT (29u) +#define INTC_ICDICFR10_SSII1_0_SHIFT (30u) +#define INTC_ICDICFR10_SSII1_1_SHIFT (31u) + +#define INTC_ICDICFR11_SSIRXI1_0_SHIFT (0u) +#define INTC_ICDICFR11_SSIRXI1_1_SHIFT (1u) +#define INTC_ICDICFR11_SSITXI1_0_SHIFT (2u) +#define INTC_ICDICFR11_SSITXI1_1_SHIFT (3u) +#define INTC_ICDICFR11_SSII2_0_SHIFT (4u) +#define INTC_ICDICFR11_SSII2_1_SHIFT (5u) +#define INTC_ICDICFR11_SSIRTI2_0_SHIFT (6u) +#define INTC_ICDICFR11_SSIRTI2_1_SHIFT (7u) +#define INTC_ICDICFR11_SSII3_0_SHIFT (8u) +#define INTC_ICDICFR11_SSII3_1_SHIFT (9u) +#define INTC_ICDICFR11_SSIRXI3_0_SHIFT (10u) +#define INTC_ICDICFR11_SSIRXI3_1_SHIFT (11u) +#define INTC_ICDICFR11_SSITXI3_0_SHIFT (12u) +#define INTC_ICDICFR11_SSITXI3_1_SHIFT (13u) +#define INTC_ICDICFR11_SSII4_0_SHIFT (14u) +#define INTC_ICDICFR11_SSII4_1_SHIFT (15u) +#define INTC_ICDICFR11_SSIRTI4_0_SHIFT (16u) +#define INTC_ICDICFR11_SSIRTI4_1_SHIFT (17u) +#define INTC_ICDICFR11_SSII5_0_SHIFT (18u) +#define INTC_ICDICFR11_SSII5_1_SHIFT (19u) +#define INTC_ICDICFR11_SSIRXI5_0_SHIFT (20u) +#define INTC_ICDICFR11_SSIRXI5_1_SHIFT (21u) +#define INTC_ICDICFR11_SSITXI5_0_SHIFT (22u) +#define INTC_ICDICFR11_SSITXI5_1_SHIFT (23u) +#define INTC_ICDICFR11_SPDIFI_0_SHIFT (24u) +#define INTC_ICDICFR11_SPDIFI_1_SHIFT (25u) +#define INTC_ICDICFR11_INTIICTEI0_0_SHIFT (26u) +#define INTC_ICDICFR11_INTIICTEI0_1_SHIFT (27u) +#define INTC_ICDICFR11_INTIICRI0_0_SHIFT (28u) +#define INTC_ICDICFR11_INTIICRI0_1_SHIFT (29u) +#define INTC_ICDICFR11_INTIICTI0_0_SHIFT (30u) +#define INTC_ICDICFR11_INTIICTI0_1_SHIFT (31u) + +#define INTC_ICDICFR12_INTIICSPI0_0_SHIFT (0u) +#define INTC_ICDICFR12_INTIICSPI0_1_SHIFT (1u) +#define INTC_ICDICFR12_INTIICSTI0_0_SHIFT (2u) +#define INTC_ICDICFR12_INTIICSTI0_1_SHIFT (3u) +#define INTC_ICDICFR12_INTIICNAKI0_0_SHIFT (4u) +#define INTC_ICDICFR12_INTIICNAKI0_1_SHIFT (5u) +#define INTC_ICDICFR12_INTIICALI0_0_SHIFT (6u) +#define INTC_ICDICFR12_INTIICALI0_1_SHIFT (7u) +#define INTC_ICDICFR12_INTIICTMOI0_0_SHIFT (8u) +#define INTC_ICDICFR12_INTIICTMOI0_1_SHIFT (9u) +#define INTC_ICDICFR12_INTIICTEI1_0_SHIFT (10u) +#define INTC_ICDICFR12_INTIICTEI1_1_SHIFT (11u) +#define INTC_ICDICFR12_INTIICRI1_0_SHIFT (12u) +#define INTC_ICDICFR12_INTIICRI1_1_SHIFT (13u) +#define INTC_ICDICFR12_INTIICTI1_0_SHIFT (14u) +#define INTC_ICDICFR12_INTIICTI1_1_SHIFT (15u) +#define INTC_ICDICFR12_INTIICSPI1_0_SHIFT (16u) +#define INTC_ICDICFR12_INTIICSPI1_1_SHIFT (17u) +#define INTC_ICDICFR12_INTIICSTI1_0_SHIFT (18u) +#define INTC_ICDICFR12_INTIICSTI1_1_SHIFT (19u) +#define INTC_ICDICFR12_INTIICNAKI1_0_SHIFT (20u) +#define INTC_ICDICFR12_INTIICNAKI1_1_SHIFT (21u) +#define INTC_ICDICFR12_INTIICALI1_0_SHIFT (22u) +#define INTC_ICDICFR12_INTIICALI1_1_SHIFT (23u) +#define INTC_ICDICFR12_INTIICTMOI1_0_SHIFT (24u) +#define INTC_ICDICFR12_INTIICTMOI1_1_SHIFT (25u) +#define INTC_ICDICFR12_INTIICTEI2_0_SHIFT (26u) +#define INTC_ICDICFR12_INTIICTEI2_1_SHIFT (27u) +#define INTC_ICDICFR12_INTIICRI2_0_SHIFT (28u) +#define INTC_ICDICFR12_INTIICRI2_1_SHIFT (29u) +#define INTC_ICDICFR12_INTIICTI2_0_SHIFT (30u) +#define INTC_ICDICFR12_INTIICTI2_1_SHIFT (31u) + +#define INTC_ICDICFR13_INTIICSPI2_0_SHIFT (0u) +#define INTC_ICDICFR13_INTIICSPI2_1_SHIFT (1u) +#define INTC_ICDICFR13_INTIICSTI2_0_SHIFT (2u) +#define INTC_ICDICFR13_INTIICSTI2_1_SHIFT (3u) +#define INTC_ICDICFR13_INTIICNAKI2_0_SHIFT (4u) +#define INTC_ICDICFR13_INTIICNAKI2_1_SHIFT (5u) +#define INTC_ICDICFR13_INTIICALI2_0_SHIFT (6u) +#define INTC_ICDICFR13_INTIICALI2_1_SHIFT (7u) +#define INTC_ICDICFR13_INTIICTMOI2_0_SHIFT (8u) +#define INTC_ICDICFR13_INTIICTMOI2_1_SHIFT (9u) +#define INTC_ICDICFR13_INTIICTEI3_0_SHIFT (10u) +#define INTC_ICDICFR13_INTIICTEI3_1_SHIFT (11u) +#define INTC_ICDICFR13_INTIICRI3_0_SHIFT (12u) +#define INTC_ICDICFR13_INTIICRI3_1_SHIFT (13u) +#define INTC_ICDICFR13_INTIICTI3_0_SHIFT (14u) +#define INTC_ICDICFR13_INTIICTI3_1_SHIFT (15u) +#define INTC_ICDICFR13_INTIICSPI3_0_SHIFT (16u) +#define INTC_ICDICFR13_INTIICSPI3_1_SHIFT (17u) +#define INTC_ICDICFR13_INTIICSTI3_0_SHIFT (18u) +#define INTC_ICDICFR13_INTIICSTI3_1_SHIFT (19u) +#define INTC_ICDICFR13_INTIICNAKI3_0_SHIFT (20u) +#define INTC_ICDICFR13_INTIICNAKI3_1_SHIFT (21u) +#define INTC_ICDICFR13_INTIICALI3_0_SHIFT (22u) +#define INTC_ICDICFR13_INTIICALI3_1_SHIFT (23u) +#define INTC_ICDICFR13_INTIICTMOI3_0_SHIFT (24u) +#define INTC_ICDICFR13_INTIICTMOI3_1_SHIFT (25u) +#define INTC_ICDICFR13_BRI0_0_SHIFT (26u) +#define INTC_ICDICFR13_BRI0_1_SHIFT (27u) +#define INTC_ICDICFR13_ERI0_0_SHIFT (28u) +#define INTC_ICDICFR13_ERI0_1_SHIFT (29u) +#define INTC_ICDICFR13_RXI0_0_SHIFT (30u) +#define INTC_ICDICFR13_RXI0_1_SHIFT (31u) + +#define INTC_ICDICFR14_TXI0_0_SHIFT (0u) +#define INTC_ICDICFR14_TXI0_1_SHIFT (1u) +#define INTC_ICDICFR14_BRI1_0_SHIFT (2u) +#define INTC_ICDICFR14_BRI1_1_SHIFT (3u) +#define INTC_ICDICFR14_ERI1_0_SHIFT (4u) +#define INTC_ICDICFR14_ERI1_1_SHIFT (5u) +#define INTC_ICDICFR14_RXI1_0_SHIFT (6u) +#define INTC_ICDICFR14_RXI1_1_SHIFT (7u) +#define INTC_ICDICFR14_TXI1_0_SHIFT (8u) +#define INTC_ICDICFR14_TXI1_1_SHIFT (9u) +#define INTC_ICDICFR14_BRI2_0_SHIFT (10u) +#define INTC_ICDICFR14_BRI2_1_SHIFT (11u) +#define INTC_ICDICFR14_ERI2_0_SHIFT (12u) +#define INTC_ICDICFR14_ERI2_1_SHIFT (13u) +#define INTC_ICDICFR14_RXI2_0_SHIFT (14u) +#define INTC_ICDICFR14_RXI2_1_SHIFT (15u) +#define INTC_ICDICFR14_TXI2_0_SHIFT (16u) +#define INTC_ICDICFR14_TXI2_1_SHIFT (17u) +#define INTC_ICDICFR14_BRI3_0_SHIFT (18u) +#define INTC_ICDICFR14_BRI3_1_SHIFT (19u) +#define INTC_ICDICFR14_ERI3_0_SHIFT (20u) +#define INTC_ICDICFR14_ERI3_1_SHIFT (21u) +#define INTC_ICDICFR14_RXI3_0_SHIFT (22u) +#define INTC_ICDICFR14_RXI3_1_SHIFT (23u) +#define INTC_ICDICFR14_TXI3_0_SHIFT (24u) +#define INTC_ICDICFR14_TXI3_1_SHIFT (25u) +#define INTC_ICDICFR14_BRI4_0_SHIFT (26u) +#define INTC_ICDICFR14_BRI4_1_SHIFT (27u) +#define INTC_ICDICFR14_ERI4_0_SHIFT (28u) +#define INTC_ICDICFR14_ERI4_1_SHIFT (29u) +#define INTC_ICDICFR14_RXI4_0_SHIFT (30u) +#define INTC_ICDICFR14_RXI4_1_SHIFT (31u) + +#define INTC_ICDICFR15_TXI4_0_SHIFT (0u) +#define INTC_ICDICFR15_TXI4_1_SHIFT (1u) +#define INTC_ICDICFR15_BRI5_0_SHIFT (2u) +#define INTC_ICDICFR15_BRI5_1_SHIFT (3u) +#define INTC_ICDICFR15_ERI5_0_SHIFT (4u) +#define INTC_ICDICFR15_ERI5_1_SHIFT (5u) +#define INTC_ICDICFR15_RXI5_0_SHIFT (6u) +#define INTC_ICDICFR15_RXI5_1_SHIFT (7u) +#define INTC_ICDICFR15_TXI5_0_SHIFT (8u) +#define INTC_ICDICFR15_TXI5_1_SHIFT (9u) +#define INTC_ICDICFR15_BRI6_0_SHIFT (10u) +#define INTC_ICDICFR15_BRI6_1_SHIFT (11u) +#define INTC_ICDICFR15_ERI6_0_SHIFT (12u) +#define INTC_ICDICFR15_ERI6_1_SHIFT (13u) +#define INTC_ICDICFR15_RXI6_0_SHIFT (14u) +#define INTC_ICDICFR15_RXI6_1_SHIFT (15u) +#define INTC_ICDICFR15_TXI6_0_SHIFT (16u) +#define INTC_ICDICFR15_TXI6_1_SHIFT (17u) +#define INTC_ICDICFR15_BRI7_0_SHIFT (18u) +#define INTC_ICDICFR15_BRI7_1_SHIFT (19u) +#define INTC_ICDICFR15_ERI7_0_SHIFT (20u) +#define INTC_ICDICFR15_ERI7_1_SHIFT (21u) +#define INTC_ICDICFR15_RXI7_0_SHIFT (22u) +#define INTC_ICDICFR15_RXI7_1_SHIFT (23u) +#define INTC_ICDICFR15_TXI7_0_SHIFT (24u) +#define INTC_ICDICFR15_TXI7_1_SHIFT (25u) +#define INTC_ICDICFR15_INTRCANGERR_0_SHIFT (26u) +#define INTC_ICDICFR15_INTRCANGERR_1_SHIFT (27u) +#define INTC_ICDICFR15_INTRCANGRECC_0_SHIFT (28u) +#define INTC_ICDICFR15_INTRCANGRECC_1_SHIFT (29u) +#define INTC_ICDICFR15_INTRCAN0REC_0_SHIFT (30u) +#define INTC_ICDICFR15_INTRCAN0REC_1_SHIFT (31u) + +#define INTC_ICDICFR16_INTRCAN0ERR_0_SHIFT (0u) +#define INTC_ICDICFR16_INTRCAN0ERR_1_SHIFT (1u) +#define INTC_ICDICFR16_INTRCAN0TRX_0_SHIFT (2u) +#define INTC_ICDICFR16_INTRCAN0TRX_1_SHIFT (3u) +#define INTC_ICDICFR16_INTRCAN1REC_0_SHIFT (4u) +#define INTC_ICDICFR16_INTRCAN1REC_1_SHIFT (5u) +#define INTC_ICDICFR16_INTRCAN1ERR_0_SHIFT (6u) +#define INTC_ICDICFR16_INTRCAN1ERR_1_SHIFT (7u) +#define INTC_ICDICFR16_INTRCAN1TRX_0_SHIFT (8u) +#define INTC_ICDICFR16_INTRCAN1TRX_1_SHIFT (9u) +#define INTC_ICDICFR16_INTRCAN2REC_0_SHIFT (10u) +#define INTC_ICDICFR16_INTRCAN2REC_1_SHIFT (11u) +#define INTC_ICDICFR16_INTRCAN2ERR_0_SHIFT (12u) +#define INTC_ICDICFR16_INTRCAN2ERR_1_SHIFT (13u) +#define INTC_ICDICFR16_INTRCAN2TRX_0_SHIFT (14u) +#define INTC_ICDICFR16_INTRCAN2TRX_1_SHIFT (15u) +#define INTC_ICDICFR16_INTRCAN3REC_0_SHIFT (16u) +#define INTC_ICDICFR16_INTRCAN3REC_1_SHIFT (17u) +#define INTC_ICDICFR16_INTRCAN3ERR_0_SHIFT (18u) +#define INTC_ICDICFR16_INTRCAN3ERR_1_SHIFT (19u) +#define INTC_ICDICFR16_INTRCAN3TRX_0_SHIFT (20u) +#define INTC_ICDICFR16_INTRCAN3TRX_1_SHIFT (21u) +#define INTC_ICDICFR16_INTRCAN4REC_0_SHIFT (22u) +#define INTC_ICDICFR16_INTRCAN4REC_1_SHIFT (23u) +#define INTC_ICDICFR16_INTRCAN4ERR_0_SHIFT (24u) +#define INTC_ICDICFR16_INTRCAN4ERR_1_SHIFT (25u) +#define INTC_ICDICFR16_INTRCAN4TRX_0_SHIFT (26u) +#define INTC_ICDICFR16_INTRCAN4TRX_1_SHIFT (27u) +#define INTC_ICDICFR16_SPEI0_0_SHIFT (28u) +#define INTC_ICDICFR16_SPEI0_1_SHIFT (29u) +#define INTC_ICDICFR16_SPRI0_0_SHIFT (30u) +#define INTC_ICDICFR16_SPRI0_1_SHIFT (31u) + +#define INTC_ICDICFR17_SPTI0_0_SHIFT (0u) +#define INTC_ICDICFR17_SPTI0_1_SHIFT (1u) +#define INTC_ICDICFR17_SPEI1_0_SHIFT (2u) +#define INTC_ICDICFR17_SPEI1_1_SHIFT (3u) +#define INTC_ICDICFR17_SPRI1_0_SHIFT (4u) +#define INTC_ICDICFR17_SPRI1_1_SHIFT (5u) +#define INTC_ICDICFR17_SPTI1_0_SHIFT (6u) +#define INTC_ICDICFR17_SPTI1_1_SHIFT (7u) +#define INTC_ICDICFR17_SPEI2_0_SHIFT (8u) +#define INTC_ICDICFR17_SPEI2_1_SHIFT (9u) +#define INTC_ICDICFR17_SPRI2_0_SHIFT (10u) +#define INTC_ICDICFR17_SPRI2_1_SHIFT (11u) +#define INTC_ICDICFR17_SPTI2_0_SHIFT (12u) +#define INTC_ICDICFR17_SPTI2_1_SHIFT (13u) +#define INTC_ICDICFR17_SPEI3_0_SHIFT (14u) +#define INTC_ICDICFR17_SPEI3_1_SHIFT (15u) +#define INTC_ICDICFR17_SPRI3_0_SHIFT (16u) +#define INTC_ICDICFR17_SPRI3_1_SHIFT (17u) +#define INTC_ICDICFR17_SPTI3_0_SHIFT (18u) +#define INTC_ICDICFR17_SPTI3_1_SHIFT (19u) +#define INTC_ICDICFR17_SPEI4_0_SHIFT (20u) +#define INTC_ICDICFR17_SPEI4_1_SHIFT (21u) +#define INTC_ICDICFR17_SPRI4_0_SHIFT (22u) +#define INTC_ICDICFR17_SPRI4_1_SHIFT (23u) +#define INTC_ICDICFR17_SPTI4_0_SHIFT (24u) +#define INTC_ICDICFR17_SPTI4_1_SHIFT (25u) +#define INTC_ICDICFR17_IEBBTD_0_SHIFT (26u) +#define INTC_ICDICFR17_IEBBTD_1_SHIFT (27u) +#define INTC_ICDICFR17_IEBBTERR_0_SHIFT (28u) +#define INTC_ICDICFR17_IEBBTERR_1_SHIFT (29u) +#define INTC_ICDICFR17_IEBBTSTA_0_SHIFT (30u) +#define INTC_ICDICFR17_IEBBTSTA_1_SHIFT (31u) + +#define INTC_ICDICFR18_IEBBTV_0_SHIFT (0u) +#define INTC_ICDICFR18_IEBBTV_1_SHIFT (1u) +#define INTC_ICDICFR18_ISY_0_SHIFT (2u) +#define INTC_ICDICFR18_ISY_1_SHIFT (3u) +#define INTC_ICDICFR18_IERR_0_SHIFT (4u) +#define INTC_ICDICFR18_IERR_1_SHIFT (5u) +#define INTC_ICDICFR18_ITARG_0_SHIFT (6u) +#define INTC_ICDICFR18_ITARG_1_SHIFT (7u) +#define INTC_ICDICFR18_ISEC_0_SHIFT (8u) +#define INTC_ICDICFR18_ISEC_1_SHIFT (9u) +#define INTC_ICDICFR18_IBUF_0_SHIFT (10u) +#define INTC_ICDICFR18_IBUF_1_SHIFT (11u) +#define INTC_ICDICFR18_IREADY_0_SHIFT (12u) +#define INTC_ICDICFR18_IREADY_1_SHIFT (13u) +#define INTC_ICDICFR18_FLSTE_0_SHIFT (14u) +#define INTC_ICDICFR18_FLSTE_1_SHIFT (15u) +#define INTC_ICDICFR18_FLTENDI_0_SHIFT (16u) +#define INTC_ICDICFR18_FLTENDI_1_SHIFT (17u) +#define INTC_ICDICFR18_FLTREQ0I_0_SHIFT (18u) +#define INTC_ICDICFR18_FLTREQ0I_1_SHIFT (19u) +#define INTC_ICDICFR18_FLTREQ1I_0_SHIFT (20u) +#define INTC_ICDICFR18_FLTREQ1I_1_SHIFT (21u) +#define INTC_ICDICFR18_MMC0_0_SHIFT (22u) +#define INTC_ICDICFR18_MMC0_1_SHIFT (23u) +#define INTC_ICDICFR18_MMC1_0_SHIFT (24u) +#define INTC_ICDICFR18_MMC1_1_SHIFT (25u) +#define INTC_ICDICFR18_MMC2_0_SHIFT (26u) +#define INTC_ICDICFR18_MMC2_1_SHIFT (27u) +#define INTC_ICDICFR18_SDHI0_3_0_SHIFT (28u) +#define INTC_ICDICFR18_SDHI0_3_1_SHIFT (29u) +#define INTC_ICDICFR18_SDHI0_0_0_SHIFT (30u) +#define INTC_ICDICFR18_SDHI0_0_1_SHIFT (31u) + +#define INTC_ICDICFR19_SDHI0_1_0_SHIFT (0u) +#define INTC_ICDICFR19_SDHI0_1_1_SHIFT (1u) +#define INTC_ICDICFR19_SDHI1_3_0_SHIFT (2u) +#define INTC_ICDICFR19_SDHI1_3_1_SHIFT (3u) +#define INTC_ICDICFR19_SDHI1_0_0_SHIFT (4u) +#define INTC_ICDICFR19_SDHI1_0_1_SHIFT (5u) +#define INTC_ICDICFR19_SDHI1_1_0_SHIFT (6u) +#define INTC_ICDICFR19_SDHI1_1_1_SHIFT (7u) +#define INTC_ICDICFR19_ARM_0_SHIFT (8u) +#define INTC_ICDICFR19_ARM_1_SHIFT (9u) +#define INTC_ICDICFR19_PRD_0_SHIFT (10u) +#define INTC_ICDICFR19_PRD_1_SHIFT (11u) +#define INTC_ICDICFR19_CUP_0_SHIFT (12u) +#define INTC_ICDICFR19_CUP_1_SHIFT (13u) +#define INTC_ICDICFR19_SCUAI0_0_SHIFT (14u) +#define INTC_ICDICFR19_SCUAI0_1_SHIFT (15u) +#define INTC_ICDICFR19_SCUAI1_0_SHIFT (16u) +#define INTC_ICDICFR19_SCUAI1_1_SHIFT (17u) +#define INTC_ICDICFR19_SCUFDI0_0_SHIFT (18u) +#define INTC_ICDICFR19_SCUFDI0_1_SHIFT (19u) +#define INTC_ICDICFR19_SCUFDI1_0_SHIFT (20u) +#define INTC_ICDICFR19_SCUFDI1_1_SHIFT (21u) +#define INTC_ICDICFR19_SCUFDI2_0_SHIFT (22u) +#define INTC_ICDICFR19_SCUFDI2_1_SHIFT (23u) +#define INTC_ICDICFR19_SCUFDI3_0_SHIFT (24u) +#define INTC_ICDICFR19_SCUFDI3_1_SHIFT (25u) +#define INTC_ICDICFR19_SCUFUI0_0_SHIFT (26u) +#define INTC_ICDICFR19_SCUFUI0_1_SHIFT (27u) +#define INTC_ICDICFR19_SCUFUI1_0_SHIFT (28u) +#define INTC_ICDICFR19_SCUFUI1_1_SHIFT (29u) +#define INTC_ICDICFR19_SCUFUI2_0_SHIFT (30u) +#define INTC_ICDICFR19_SCUFUI2_1_SHIFT (31u) + +#define INTC_ICDICFR20_SCUFUI3_0_SHIFT (0u) +#define INTC_ICDICFR20_SCUFUI3_1_SHIFT (1u) +#define INTC_ICDICFR20_SCUDVI0_0_SHIFT (2u) +#define INTC_ICDICFR20_SCUDVI0_1_SHIFT (3u) +#define INTC_ICDICFR20_SCUDVI1_0_SHIFT (4u) +#define INTC_ICDICFR20_SCUDVI1_1_SHIFT (5u) +#define INTC_ICDICFR20_SCUDVI2_0_SHIFT (6u) +#define INTC_ICDICFR20_SCUDVI2_1_SHIFT (7u) +#define INTC_ICDICFR20_SCUDVI3_0_SHIFT (8u) +#define INTC_ICDICFR20_SCUDVI3_1_SHIFT (9u) +#define INTC_ICDICFR20_MLB_CINT_0_SHIFT (10u) +#define INTC_ICDICFR20_MLB_CINT_1_SHIFT (11u) +#define INTC_ICDICFR20_MLB_SINT_0_SHIFT (12u) +#define INTC_ICDICFR20_MLB_SINT_1_SHIFT (13u) +#define INTC_ICDICFR20_DRC0_0_SHIFT (14u) +#define INTC_ICDICFR20_DRC0_1_SHIFT (15u) +#define INTC_ICDICFR20_DRC1_0_SHIFT (16u) +#define INTC_ICDICFR20_DRC1_1_SHIFT (17u) +#define INTC_ICDICFR20_LINI0_INT_T_0_SHIFT (22u) +#define INTC_ICDICFR20_LINI0_INT_T_1_SHIFT (23u) +#define INTC_ICDICFR20_LINI0_INT_R_0_SHIFT (24u) +#define INTC_ICDICFR20_LINI0_INT_R_1_SHIFT (25u) +#define INTC_ICDICFR20_LINI0_INT_S_0_SHIFT (26u) +#define INTC_ICDICFR20_LINI0_INT_S_1_SHIFT (27u) +#define INTC_ICDICFR20_LINI0_INT_M_0_SHIFT (28u) +#define INTC_ICDICFR20_LINI0_INT_M_1_SHIFT (29u) +#define INTC_ICDICFR20_LINI1_INT_T_0_SHIFT (30u) +#define INTC_ICDICFR20_LINI1_INT_T_1_SHIFT (31u) + +#define INTC_ICDICFR21_LINI1_INT_R_0_SHIFT (0u) +#define INTC_ICDICFR21_LINI1_INT_R_1_SHIFT (1u) +#define INTC_ICDICFR21_LINI1_INT_S_0_SHIFT (2u) +#define INTC_ICDICFR21_LINI1_INT_S_1_SHIFT (3u) +#define INTC_ICDICFR21_LINI1_INT_M_0_SHIFT (4u) +#define INTC_ICDICFR21_LINI1_INT_M_1_SHIFT (5u) +#define INTC_ICDICFR21_ERI0_0_SHIFT (22u) +#define INTC_ICDICFR21_ERI0_1_SHIFT (23u) +#define INTC_ICDICFR21_RXI0_0_SHIFT (24u) +#define INTC_ICDICFR21_RXI0_1_SHIFT (25u) +#define INTC_ICDICFR21_TXI0_0_SHIFT (26u) +#define INTC_ICDICFR21_TXI0_1_SHIFT (27u) +#define INTC_ICDICFR21_TEI0_0_SHIFT (28u) +#define INTC_ICDICFR21_TEI0_1_SHIFT (29u) +#define INTC_ICDICFR21_ERI1_0_SHIFT (30u) +#define INTC_ICDICFR21_ERI1_1_SHIFT (31u) + +#define INTC_ICDICFR22_RXI1_0_SHIFT (0u) +#define INTC_ICDICFR22_RXI1_1_SHIFT (1u) +#define INTC_ICDICFR22_TXI1_0_SHIFT (2u) +#define INTC_ICDICFR22_TXI1_1_SHIFT (3u) +#define INTC_ICDICFR22_TEI1_0_SHIFT (4u) +#define INTC_ICDICFR22_TEI1_1_SHIFT (5u) +#define INTC_ICDICFR22_AVBI_DATA_0_SHIFT (6u) +#define INTC_ICDICFR22_AVBI_DATA_1_SHIFT (7u) +#define INTC_ICDICFR22_AVBI_ERROR_0_SHIFT (8u) +#define INTC_ICDICFR22_AVBI_ERROR_1_SHIFT (9u) +#define INTC_ICDICFR22_AVBI_MANAGE_0_SHIFT (10u) +#define INTC_ICDICFR22_AVBI_MANAGE_1_SHIFT (11u) +#define INTC_ICDICFR22_AVBI_MAC_0_SHIFT (12u) +#define INTC_ICDICFR22_AVBI_MAC_1_SHIFT (13u) +#define INTC_ICDICFR22_ETHERI_0_SHIFT (14u) +#define INTC_ICDICFR22_ETHERI_1_SHIFT (15u) +#define INTC_ICDICFR22_CEUI_0_SHIFT (24u) +#define INTC_ICDICFR22_CEUI_1_SHIFT (25u) + +#define INTC_ICDICFR23_H2XMLB_ERRINT_0_SHIFT (26u) +#define INTC_ICDICFR23_H2XMLB_ERRINT_1_SHIFT (27u) +#define INTC_ICDICFR23_H2XIC1_ERRINT_0_SHIFT (28u) +#define INTC_ICDICFR23_H2XIC1_ERRINT_1_SHIFT (29u) +#define INTC_ICDICFR23_X2HPERI1_ERRINT_0_SHIFT (30u) +#define INTC_ICDICFR23_X2HPERI1_ERRINT_1_SHIFT (31u) + +#define INTC_ICDICFR24_X2HPERI2_ERRINT_0_SHIFT (0u) +#define INTC_ICDICFR24_X2HPERI2_ERRINT_1_SHIFT (1u) +#define INTC_ICDICFR24_X2HPERI34_ERRINT_0_SHIFT (2u) +#define INTC_ICDICFR24_X2HPERI34_ERRINT_1_SHIFT (3u) +#define INTC_ICDICFR24_X2HPERI5_ERRINT_0_SHIFT (4u) +#define INTC_ICDICFR24_X2HPERI5_ERRINT_1_SHIFT (5u) +#define INTC_ICDICFR24_X2HPERI67_ERRINT_0_SHIFT (6u) +#define INTC_ICDICFR24_X2HPERI67_ERRINT_1_SHIFT (7u) +#define INTC_ICDICFR24_X2HDBGR_ERRINT_0_SHIFT (8u) +#define INTC_ICDICFR24_X2HDBGR_ERRINT_1_SHIFT (9u) +#define INTC_ICDICFR24_X2HBSC_ERRINT_0_SHIFT (10u) +#define INTC_ICDICFR24_X2HBSC_ERRINT_1_SHIFT (11u) +#define INTC_ICDICFR24_X2HSPI1_ERRINT_0_SHIFT (12u) +#define INTC_ICDICFR24_X2HSPI1_ERRINT_1_SHIFT (13u) +#define INTC_ICDICFR24_X2HSPI2_ERRINT_0_SHIFT (14u) +#define INTC_ICDICFR24_X2HSPI2_ERRINT_1_SHIFT (15u) +#define INTC_ICDICFR24_PRRI_0_SHIFT (16u) +#define INTC_ICDICFR24_PRRI_1_SHIFT (17u) +#define INTC_ICDICFR24_IFEI0_0_SHIFT (18u) +#define INTC_ICDICFR24_IFEI0_1_SHIFT (19u) +#define INTC_ICDICFR24_OFFI0_0_SHIFT (20u) +#define INTC_ICDICFR24_OFFI0_1_SHIFT (21u) +#define INTC_ICDICFR24_PFVEI0_0_SHIFT (22u) +#define INTC_ICDICFR24_PFVEI0_1_SHIFT (23u) +#define INTC_ICDICFR24_IFEI1_0_SHIFT (24u) +#define INTC_ICDICFR24_IFEI1_1_SHIFT (25u) +#define INTC_ICDICFR24_OFFI1_0_SHIFT (26u) +#define INTC_ICDICFR24_OFFI1_1_SHIFT (27u) +#define INTC_ICDICFR24_PFVEI1_0_SHIFT (28u) +#define INTC_ICDICFR24_PFVEI1_1_SHIFT (29u) + +#define INTC_ICDICFR26_TINT0_0_SHIFT (0u) +#define INTC_ICDICFR26_TINT0_1_SHIFT (1u) +#define INTC_ICDICFR26_TINT1_0_SHIFT (2u) +#define INTC_ICDICFR26_TINT1_1_SHIFT (3u) +#define INTC_ICDICFR26_TINT2_0_SHIFT (4u) +#define INTC_ICDICFR26_TINT2_1_SHIFT (5u) +#define INTC_ICDICFR26_TINT3_0_SHIFT (6u) +#define INTC_ICDICFR26_TINT3_1_SHIFT (7u) +#define INTC_ICDICFR26_TINT4_0_SHIFT (8u) +#define INTC_ICDICFR26_TINT4_1_SHIFT (9u) +#define INTC_ICDICFR26_TINT5_0_SHIFT (10u) +#define INTC_ICDICFR26_TINT5_1_SHIFT (11u) +#define INTC_ICDICFR26_TINT6_0_SHIFT (12u) +#define INTC_ICDICFR26_TINT6_1_SHIFT (13u) +#define INTC_ICDICFR26_TINT7_0_SHIFT (14u) +#define INTC_ICDICFR26_TINT7_1_SHIFT (15u) +#define INTC_ICDICFR26_TINT8_0_SHIFT (16u) +#define INTC_ICDICFR26_TINT8_1_SHIFT (17u) +#define INTC_ICDICFR26_TINT9_0_SHIFT (18u) +#define INTC_ICDICFR26_TINT9_1_SHIFT (19u) +#define INTC_ICDICFR26_TINT10_0_SHIFT (20u) +#define INTC_ICDICFR26_TINT10_1_SHIFT (21u) +#define INTC_ICDICFR26_TINT11_0_SHIFT (22u) +#define INTC_ICDICFR26_TINT11_1_SHIFT (23u) +#define INTC_ICDICFR26_TINT12_0_SHIFT (24u) +#define INTC_ICDICFR26_TINT12_1_SHIFT (25u) +#define INTC_ICDICFR26_TINT13_0_SHIFT (26u) +#define INTC_ICDICFR26_TINT13_1_SHIFT (27u) +#define INTC_ICDICFR26_TINT14_0_SHIFT (28u) +#define INTC_ICDICFR26_TINT14_1_SHIFT (29u) +#define INTC_ICDICFR26_TINT15_0_SHIFT (30u) +#define INTC_ICDICFR26_TINT15_1_SHIFT (31u) + +#define INTC_ICDICFR27_TINT16_0_SHIFT (0u) +#define INTC_ICDICFR27_TINT16_1_SHIFT (1u) +#define INTC_ICDICFR27_TINT17_0_SHIFT (2u) +#define INTC_ICDICFR27_TINT17_1_SHIFT (3u) +#define INTC_ICDICFR27_TINT18_0_SHIFT (4u) +#define INTC_ICDICFR27_TINT18_1_SHIFT (5u) +#define INTC_ICDICFR27_TINT19_0_SHIFT (6u) +#define INTC_ICDICFR27_TINT19_1_SHIFT (7u) +#define INTC_ICDICFR27_TINT20_0_SHIFT (8u) +#define INTC_ICDICFR27_TINT20_1_SHIFT (9u) +#define INTC_ICDICFR27_TINT21_0_SHIFT (10u) +#define INTC_ICDICFR27_TINT21_1_SHIFT (11u) +#define INTC_ICDICFR27_TINT22_0_SHIFT (12u) +#define INTC_ICDICFR27_TINT22_1_SHIFT (13u) +#define INTC_ICDICFR27_TINT23_0_SHIFT (14u) +#define INTC_ICDICFR27_TINT23_1_SHIFT (15u) +#define INTC_ICDICFR27_TINT24_0_SHIFT (16u) +#define INTC_ICDICFR27_TINT24_1_SHIFT (17u) +#define INTC_ICDICFR27_TINT25_0_SHIFT (18u) +#define INTC_ICDICFR27_TINT25_1_SHIFT (19u) +#define INTC_ICDICFR27_TINT26_0_SHIFT (20u) +#define INTC_ICDICFR27_TINT26_1_SHIFT (21u) +#define INTC_ICDICFR27_TINT27_0_SHIFT (22u) +#define INTC_ICDICFR27_TINT27_1_SHIFT (23u) +#define INTC_ICDICFR27_TINT28_0_SHIFT (24u) +#define INTC_ICDICFR27_TINT28_1_SHIFT (25u) +#define INTC_ICDICFR27_TINT29_0_SHIFT (26u) +#define INTC_ICDICFR27_TINT29_1_SHIFT (27u) +#define INTC_ICDICFR27_TINT30_0_SHIFT (28u) +#define INTC_ICDICFR27_TINT30_1_SHIFT (29u) +#define INTC_ICDICFR27_TINT31_0_SHIFT (30u) +#define INTC_ICDICFR27_TINT31_1_SHIFT (31u) + +#define INTC_ICDICFR28_TINT32_0_SHIFT (0u) +#define INTC_ICDICFR28_TINT32_1_SHIFT (1u) +#define INTC_ICDICFR28_TINT33_0_SHIFT (2u) +#define INTC_ICDICFR28_TINT33_1_SHIFT (3u) +#define INTC_ICDICFR28_TINT34_0_SHIFT (4u) +#define INTC_ICDICFR28_TINT34_1_SHIFT (5u) +#define INTC_ICDICFR28_TINT35_0_SHIFT (6u) +#define INTC_ICDICFR28_TINT35_1_SHIFT (7u) +#define INTC_ICDICFR28_TINT36_0_SHIFT (8u) +#define INTC_ICDICFR28_TINT36_1_SHIFT (9u) +#define INTC_ICDICFR28_TINT37_0_SHIFT (10u) +#define INTC_ICDICFR28_TINT37_1_SHIFT (11u) +#define INTC_ICDICFR28_TINT38_0_SHIFT (12u) +#define INTC_ICDICFR28_TINT38_1_SHIFT (13u) +#define INTC_ICDICFR28_TINT39_0_SHIFT (14u) +#define INTC_ICDICFR28_TINT39_1_SHIFT (15u) +#define INTC_ICDICFR28_TINT40_0_SHIFT (16u) +#define INTC_ICDICFR28_TINT40_1_SHIFT (17u) +#define INTC_ICDICFR28_TINT41_0_SHIFT (18u) +#define INTC_ICDICFR28_TINT41_1_SHIFT (19u) +#define INTC_ICDICFR28_TINT42_0_SHIFT (20u) +#define INTC_ICDICFR28_TINT42_1_SHIFT (21u) +#define INTC_ICDICFR28_TINT43_0_SHIFT (22u) +#define INTC_ICDICFR28_TINT43_1_SHIFT (23u) +#define INTC_ICDICFR28_TINT44_0_SHIFT (24u) +#define INTC_ICDICFR28_TINT44_1_SHIFT (25u) +#define INTC_ICDICFR28_TINT45_0_SHIFT (26u) +#define INTC_ICDICFR28_TINT45_1_SHIFT (27u) +#define INTC_ICDICFR28_TINT46_0_SHIFT (28u) +#define INTC_ICDICFR28_TINT46_1_SHIFT (29u) +#define INTC_ICDICFR28_TINT47_0_SHIFT (30u) +#define INTC_ICDICFR28_TINT47_1_SHIFT (31u) + +#define INTC_ICDICFR29_TINT48_0_SHIFT (0u) +#define INTC_ICDICFR29_TINT48_1_SHIFT (1u) +#define INTC_ICDICFR29_TINT49_0_SHIFT (2u) +#define INTC_ICDICFR29_TINT49_1_SHIFT (3u) +#define INTC_ICDICFR29_TINT50_0_SHIFT (4u) +#define INTC_ICDICFR29_TINT50_1_SHIFT (5u) +#define INTC_ICDICFR29_TINT51_0_SHIFT (6u) +#define INTC_ICDICFR29_TINT51_1_SHIFT (7u) +#define INTC_ICDICFR29_TINT52_0_SHIFT (8u) +#define INTC_ICDICFR29_TINT52_1_SHIFT (9u) +#define INTC_ICDICFR29_TINT53_0_SHIFT (10u) +#define INTC_ICDICFR29_TINT53_1_SHIFT (11u) +#define INTC_ICDICFR29_TINT54_0_SHIFT (12u) +#define INTC_ICDICFR29_TINT54_1_SHIFT (13u) +#define INTC_ICDICFR29_TINT55_0_SHIFT (14u) +#define INTC_ICDICFR29_TINT55_1_SHIFT (15u) +#define INTC_ICDICFR29_TINT56_0_SHIFT (16u) +#define INTC_ICDICFR29_TINT56_1_SHIFT (17u) +#define INTC_ICDICFR29_TINT57_0_SHIFT (18u) +#define INTC_ICDICFR29_TINT57_1_SHIFT (19u) +#define INTC_ICDICFR29_TINT58_0_SHIFT (20u) +#define INTC_ICDICFR29_TINT58_1_SHIFT (21u) +#define INTC_ICDICFR29_TINT59_0_SHIFT (22u) +#define INTC_ICDICFR29_TINT59_1_SHIFT (23u) +#define INTC_ICDICFR29_TINT60_0_SHIFT (24u) +#define INTC_ICDICFR29_TINT60_1_SHIFT (25u) +#define INTC_ICDICFR29_TINT61_0_SHIFT (26u) +#define INTC_ICDICFR29_TINT61_1_SHIFT (27u) +#define INTC_ICDICFR29_TINT62_0_SHIFT (28u) +#define INTC_ICDICFR29_TINT62_1_SHIFT (29u) +#define INTC_ICDICFR29_TINT63_0_SHIFT (30u) +#define INTC_ICDICFR29_TINT63_1_SHIFT (31u) + +#define INTC_ICDICFR30_TINT64_0_SHIFT (0u) +#define INTC_ICDICFR30_TINT64_1_SHIFT (1u) +#define INTC_ICDICFR30_TINT65_0_SHIFT (2u) +#define INTC_ICDICFR30_TINT65_1_SHIFT (3u) +#define INTC_ICDICFR30_TINT66_0_SHIFT (4u) +#define INTC_ICDICFR30_TINT66_1_SHIFT (5u) +#define INTC_ICDICFR30_TINT67_0_SHIFT (6u) +#define INTC_ICDICFR30_TINT67_1_SHIFT (7u) +#define INTC_ICDICFR30_TINT68_0_SHIFT (8u) +#define INTC_ICDICFR30_TINT68_1_SHIFT (9u) +#define INTC_ICDICFR30_TINT69_0_SHIFT (10u) +#define INTC_ICDICFR30_TINT69_1_SHIFT (11u) +#define INTC_ICDICFR30_TINT70_0_SHIFT (12u) +#define INTC_ICDICFR30_TINT70_1_SHIFT (13u) +#define INTC_ICDICFR30_TINT71_0_SHIFT (14u) +#define INTC_ICDICFR30_TINT71_1_SHIFT (15u) +#define INTC_ICDICFR30_TINT72_0_SHIFT (16u) +#define INTC_ICDICFR30_TINT72_1_SHIFT (17u) +#define INTC_ICDICFR30_TINT73_0_SHIFT (18u) +#define INTC_ICDICFR30_TINT73_1_SHIFT (19u) +#define INTC_ICDICFR30_TINT74_0_SHIFT (20u) +#define INTC_ICDICFR30_TINT74_1_SHIFT (21u) +#define INTC_ICDICFR30_TINT75_0_SHIFT (22u) +#define INTC_ICDICFR30_TINT75_1_SHIFT (23u) +#define INTC_ICDICFR30_TINT76_0_SHIFT (24u) +#define INTC_ICDICFR30_TINT76_1_SHIFT (25u) +#define INTC_ICDICFR30_TINT77_0_SHIFT (26u) +#define INTC_ICDICFR30_TINT77_1_SHIFT (27u) +#define INTC_ICDICFR30_TINT78_0_SHIFT (28u) +#define INTC_ICDICFR30_TINT78_1_SHIFT (29u) +#define INTC_ICDICFR30_TINT79_0_SHIFT (30u) +#define INTC_ICDICFR30_TINT79_1_SHIFT (31u) + +#define INTC_ICDICFR31_TINT80_0_SHIFT (0u) +#define INTC_ICDICFR31_TINT80_1_SHIFT (1u) +#define INTC_ICDICFR31_TINT81_0_SHIFT (2u) +#define INTC_ICDICFR31_TINT81_1_SHIFT (3u) +#define INTC_ICDICFR31_TINT82_0_SHIFT (4u) +#define INTC_ICDICFR31_TINT82_1_SHIFT (5u) +#define INTC_ICDICFR31_TINT83_0_SHIFT (6u) +#define INTC_ICDICFR31_TINT83_1_SHIFT (7u) +#define INTC_ICDICFR31_TINT84_0_SHIFT (8u) +#define INTC_ICDICFR31_TINT84_1_SHIFT (9u) +#define INTC_ICDICFR31_TINT85_0_SHIFT (10u) +#define INTC_ICDICFR31_TINT85_1_SHIFT (11u) +#define INTC_ICDICFR31_TINT86_0_SHIFT (12u) +#define INTC_ICDICFR31_TINT86_1_SHIFT (13u) +#define INTC_ICDICFR31_TINT87_0_SHIFT (14u) +#define INTC_ICDICFR31_TINT87_1_SHIFT (15u) +#define INTC_ICDICFR31_TINT88_0_SHIFT (16u) +#define INTC_ICDICFR31_TINT88_1_SHIFT (17u) +#define INTC_ICDICFR31_TINT89_0_SHIFT (18u) +#define INTC_ICDICFR31_TINT89_1_SHIFT (19u) +#define INTC_ICDICFR31_TINT90_0_SHIFT (20u) +#define INTC_ICDICFR31_TINT90_1_SHIFT (21u) +#define INTC_ICDICFR31_TINT91_0_SHIFT (22u) +#define INTC_ICDICFR31_TINT91_1_SHIFT (23u) +#define INTC_ICDICFR31_TINT92_0_SHIFT (24u) +#define INTC_ICDICFR31_TINT92_1_SHIFT (25u) +#define INTC_ICDICFR31_TINT93_0_SHIFT (26u) +#define INTC_ICDICFR31_TINT93_1_SHIFT (27u) +#define INTC_ICDICFR31_TINT94_0_SHIFT (28u) +#define INTC_ICDICFR31_TINT94_1_SHIFT (29u) +#define INTC_ICDICFR31_TINT95_0_SHIFT (30u) +#define INTC_ICDICFR31_TINT95_1_SHIFT (31u) + +#define INTC_ICDICFR32_TINT96_0_SHIFT (0u) +#define INTC_ICDICFR32_TINT96_1_SHIFT (1u) +#define INTC_ICDICFR32_TINT97_0_SHIFT (2u) +#define INTC_ICDICFR32_TINT97_1_SHIFT (3u) +#define INTC_ICDICFR32_TINT98_0_SHIFT (4u) +#define INTC_ICDICFR32_TINT98_1_SHIFT (5u) +#define INTC_ICDICFR32_TINT99_0_SHIFT (6u) +#define INTC_ICDICFR32_TINT99_1_SHIFT (7u) +#define INTC_ICDICFR32_TINT100_0_SHIFT (8u) +#define INTC_ICDICFR32_TINT100_1_SHIFT (9u) +#define INTC_ICDICFR32_TINT101_0_SHIFT (10u) +#define INTC_ICDICFR32_TINT101_1_SHIFT (11u) +#define INTC_ICDICFR32_TINT102_0_SHIFT (12u) +#define INTC_ICDICFR32_TINT102_1_SHIFT (13u) +#define INTC_ICDICFR32_TINT103_0_SHIFT (14u) +#define INTC_ICDICFR32_TINT103_1_SHIFT (15u) +#define INTC_ICDICFR32_TINT104_0_SHIFT (16u) +#define INTC_ICDICFR32_TINT104_1_SHIFT (17u) +#define INTC_ICDICFR32_TINT105_0_SHIFT (18u) +#define INTC_ICDICFR32_TINT105_1_SHIFT (19u) +#define INTC_ICDICFR32_TINT106_0_SHIFT (20u) +#define INTC_ICDICFR32_TINT106_1_SHIFT (21u) +#define INTC_ICDICFR32_TINT107_0_SHIFT (22u) +#define INTC_ICDICFR32_TINT107_1_SHIFT (23u) +#define INTC_ICDICFR32_TINT108_0_SHIFT (24u) +#define INTC_ICDICFR32_TINT108_1_SHIFT (25u) +#define INTC_ICDICFR32_TINT109_0_SHIFT (26u) +#define INTC_ICDICFR32_TINT109_1_SHIFT (27u) +#define INTC_ICDICFR32_TINT110_0_SHIFT (28u) +#define INTC_ICDICFR32_TINT110_1_SHIFT (29u) +#define INTC_ICDICFR32_TINT111_0_SHIFT (30u) +#define INTC_ICDICFR32_TINT111_1_SHIFT (31u) + +#define INTC_ICDICFR33_TINT112_0_SHIFT (0u) +#define INTC_ICDICFR33_TINT112_1_SHIFT (1u) +#define INTC_ICDICFR33_TINT113_0_SHIFT (2u) +#define INTC_ICDICFR33_TINT113_1_SHIFT (3u) +#define INTC_ICDICFR33_TINT114_0_SHIFT (4u) +#define INTC_ICDICFR33_TINT114_1_SHIFT (5u) +#define INTC_ICDICFR33_TINT115_0_SHIFT (6u) +#define INTC_ICDICFR33_TINT115_1_SHIFT (7u) +#define INTC_ICDICFR33_TINT116_0_SHIFT (8u) +#define INTC_ICDICFR33_TINT116_1_SHIFT (9u) +#define INTC_ICDICFR33_TINT117_0_SHIFT (10u) +#define INTC_ICDICFR33_TINT117_1_SHIFT (11u) +#define INTC_ICDICFR33_TINT118_0_SHIFT (12u) +#define INTC_ICDICFR33_TINT118_1_SHIFT (13u) +#define INTC_ICDICFR33_TINT119_0_SHIFT (14u) +#define INTC_ICDICFR33_TINT119_1_SHIFT (15u) +#define INTC_ICDICFR33_TINT120_0_SHIFT (16u) +#define INTC_ICDICFR33_TINT120_1_SHIFT (17u) +#define INTC_ICDICFR33_TINT121_0_SHIFT (18u) +#define INTC_ICDICFR33_TINT121_1_SHIFT (19u) +#define INTC_ICDICFR33_TINT122_0_SHIFT (20u) +#define INTC_ICDICFR33_TINT122_1_SHIFT (21u) +#define INTC_ICDICFR33_TINT123_0_SHIFT (22u) +#define INTC_ICDICFR33_TINT123_1_SHIFT (23u) +#define INTC_ICDICFR33_TINT124_0_SHIFT (24u) +#define INTC_ICDICFR33_TINT124_1_SHIFT (25u) +#define INTC_ICDICFR33_TINT125_0_SHIFT (26u) +#define INTC_ICDICFR33_TINT125_1_SHIFT (27u) +#define INTC_ICDICFR33_TINT126_0_SHIFT (28u) +#define INTC_ICDICFR33_TINT126_1_SHIFT (29u) +#define INTC_ICDICFR33_TINT127_0_SHIFT (30u) +#define INTC_ICDICFR33_TINT127_1_SHIFT (31u) + +#define INTC_ICDICFR34_TINT128_0_SHIFT (0u) +#define INTC_ICDICFR34_TINT128_1_SHIFT (1u) +#define INTC_ICDICFR34_TINT129_0_SHIFT (2u) +#define INTC_ICDICFR34_TINT129_1_SHIFT (3u) +#define INTC_ICDICFR34_TINT130_0_SHIFT (4u) +#define INTC_ICDICFR34_TINT130_1_SHIFT (5u) +#define INTC_ICDICFR34_TINT131_0_SHIFT (6u) +#define INTC_ICDICFR34_TINT131_1_SHIFT (7u) +#define INTC_ICDICFR34_TINT132_0_SHIFT (8u) +#define INTC_ICDICFR34_TINT132_1_SHIFT (9u) +#define INTC_ICDICFR34_TINT133_0_SHIFT (10u) +#define INTC_ICDICFR34_TINT133_1_SHIFT (11u) +#define INTC_ICDICFR34_TINT134_0_SHIFT (12u) +#define INTC_ICDICFR34_TINT134_1_SHIFT (13u) +#define INTC_ICDICFR34_TINT135_0_SHIFT (14u) +#define INTC_ICDICFR34_TINT135_1_SHIFT (15u) +#define INTC_ICDICFR34_TINT136_0_SHIFT (16u) +#define INTC_ICDICFR34_TINT136_1_SHIFT (17u) +#define INTC_ICDICFR34_TINT137_0_SHIFT (18u) +#define INTC_ICDICFR34_TINT137_1_SHIFT (19u) +#define INTC_ICDICFR34_TINT138_0_SHIFT (20u) +#define INTC_ICDICFR34_TINT138_1_SHIFT (21u) +#define INTC_ICDICFR34_TINT139_0_SHIFT (22u) +#define INTC_ICDICFR34_TINT139_1_SHIFT (23u) +#define INTC_ICDICFR34_TINT140_0_SHIFT (24u) +#define INTC_ICDICFR34_TINT140_1_SHIFT (25u) +#define INTC_ICDICFR34_TINT141_0_SHIFT (26u) +#define INTC_ICDICFR34_TINT141_1_SHIFT (27u) +#define INTC_ICDICFR34_TINT142_0_SHIFT (28u) +#define INTC_ICDICFR34_TINT142_1_SHIFT (29u) +#define INTC_ICDICFR34_TINT143_0_SHIFT (30u) +#define INTC_ICDICFR34_TINT143_1_SHIFT (31u) + +#define INTC_ICDICFR35_TINT144_0_SHIFT (0u) +#define INTC_ICDICFR35_TINT144_1_SHIFT (1u) +#define INTC_ICDICFR35_TINT145_0_SHIFT (2u) +#define INTC_ICDICFR35_TINT145_1_SHIFT (3u) +#define INTC_ICDICFR35_TINT146_0_SHIFT (4u) +#define INTC_ICDICFR35_TINT146_1_SHIFT (5u) +#define INTC_ICDICFR35_TINT147_0_SHIFT (6u) +#define INTC_ICDICFR35_TINT147_1_SHIFT (7u) +#define INTC_ICDICFR35_TINT148_0_SHIFT (8u) +#define INTC_ICDICFR35_TINT148_1_SHIFT (9u) +#define INTC_ICDICFR35_TINT149_0_SHIFT (10u) +#define INTC_ICDICFR35_TINT149_1_SHIFT (11u) +#define INTC_ICDICFR35_TINT150_0_SHIFT (12u) +#define INTC_ICDICFR35_TINT150_1_SHIFT (13u) +#define INTC_ICDICFR35_TINT151_0_SHIFT (14u) +#define INTC_ICDICFR35_TINT151_1_SHIFT (15u) +#define INTC_ICDICFR35_TINT152_0_SHIFT (16u) +#define INTC_ICDICFR35_TINT152_1_SHIFT (17u) +#define INTC_ICDICFR35_TINT153_0_SHIFT (18u) +#define INTC_ICDICFR35_TINT153_1_SHIFT (19u) +#define INTC_ICDICFR35_TINT154_0_SHIFT (20u) +#define INTC_ICDICFR35_TINT154_1_SHIFT (21u) +#define INTC_ICDICFR35_TINT155_0_SHIFT (22u) +#define INTC_ICDICFR35_TINT155_1_SHIFT (23u) +#define INTC_ICDICFR35_TINT156_0_SHIFT (24u) +#define INTC_ICDICFR35_TINT156_1_SHIFT (25u) +#define INTC_ICDICFR35_TINT157_0_SHIFT (26u) +#define INTC_ICDICFR35_TINT157_1_SHIFT (27u) +#define INTC_ICDICFR35_TINT158_0_SHIFT (28u) +#define INTC_ICDICFR35_TINT158_1_SHIFT (29u) +#define INTC_ICDICFR35_TINT159_0_SHIFT (30u) +#define INTC_ICDICFR35_TINT159_1_SHIFT (31u) + +#define INTC_ICDICFR36_TINT160_0_SHIFT (0u) +#define INTC_ICDICFR36_TINT160_1_SHIFT (1u) +#define INTC_ICDICFR36_TINT161_0_SHIFT (2u) +#define INTC_ICDICFR36_TINT161_1_SHIFT (3u) +#define INTC_ICDICFR36_TINT162_0_SHIFT (4u) +#define INTC_ICDICFR36_TINT162_1_SHIFT (5u) +#define INTC_ICDICFR36_TINT163_0_SHIFT (6u) +#define INTC_ICDICFR36_TINT163_1_SHIFT (7u) +#define INTC_ICDICFR36_TINT164_0_SHIFT (8u) +#define INTC_ICDICFR36_TINT164_1_SHIFT (9u) +#define INTC_ICDICFR36_TINT165_0_SHIFT (10u) +#define INTC_ICDICFR36_TINT165_1_SHIFT (11u) +#define INTC_ICDICFR36_TINT166_0_SHIFT (12u) +#define INTC_ICDICFR36_TINT166_1_SHIFT (13u) +#define INTC_ICDICFR36_TINT167_0_SHIFT (14u) +#define INTC_ICDICFR36_TINT167_1_SHIFT (15u) +#define INTC_ICDICFR36_TINT168_0_SHIFT (16u) +#define INTC_ICDICFR36_TINT168_1_SHIFT (17u) +#define INTC_ICDICFR36_TINT169_0_SHIFT (18u) +#define INTC_ICDICFR36_TINT169_1_SHIFT (19u) +#define INTC_ICDICFR36_TINT170_0_SHIFT (20u) +#define INTC_ICDICFR36_TINT170_1_SHIFT (21u) + +#define INTC_ICDSGIR_SGIINTID_SHIFT (0u) +#define INTC_ICDSGIR_SATT_SHIFT (15u) +#define INTC_ICDSGIR_CPUTargetList_SHIFT (16u) +#define INTC_ICDSGIR_TargetListFilter_SHIFT (24u) + +#define INTC_ICCICR_EnableS_SHIFT (0u) +#define INTC_ICCICR_EnableNS_SHIFT (1u) +#define INTC_ICCICR_AckCtl_SHIFT (2u) +#define INTC_ICCICR_FIQEn_SHIFT (3u) +#define INTC_ICCICR_SBPR_SHIFT (4u) + +#define INTC_ICCPMR_Priority_SHIFT (0u) + +#define INTC_ICCBPR_Binarypoint_SHIFT (0u) + +#define INTC_ICCIAR_ACKINTID_SHIFT (0u) +#define INTC_ICCIAR_CPUID_SHIFT (10u) + +#define INTC_ICCEOIR_EOIINTID_SHIFT (0u) +#define INTC_ICCEOIR_CPUID_SHIFT (10u) + +#define INTC_ICCRPR_Priority_SHIFT (0u) + +#define INTC_ICCHPIR_PENDINTID_SHIFT (0u) +#define INTC_ICCHPIR_CPUID_SHIFT (10u) + +#define INTC_ICCABPR_Binarypoint_SHIFT (0u) + +#define INTC_ICCIIDR_Implementer_SHIFT (0u) +#define INTC_ICCIIDR_Revision_SHIFT (12u) +#define INTC_ICCIIDR_Architecture_version_SHIFT (16u) +#define INTC_ICCIIDR_ProductID_SHIFT (20u) + +#define INTC_ICR0_NMIF_SHIFT (1u) +#define INTC_ICR0_NMIE_SHIFT (8u) +#define INTC_ICR0_NMIL_SHIFT (15u) + +#define INTC_ICR1_IRQ00S_SHIFT (0u) +#define INTC_ICR1_IRQ01S_SHIFT (1u) +#define INTC_ICR1_IRQ10S_SHIFT (2u) +#define INTC_ICR1_IRQ11S_SHIFT (3u) +#define INTC_ICR1_IRQ20S_SHIFT (4u) +#define INTC_ICR1_IRQ21S_SHIFT (5u) +#define INTC_ICR1_IRQ30S_SHIFT (6u) +#define INTC_ICR1_IRQ31S_SHIFT (7u) +#define INTC_ICR1_IRQ40S_SHIFT (8u) +#define INTC_ICR1_IRQ41S_SHIFT (9u) +#define INTC_ICR1_IRQ50S_SHIFT (10u) +#define INTC_ICR1_IRQ51S_SHIFT (11u) +#define INTC_ICR1_IRQ60S_SHIFT (12u) +#define INTC_ICR1_IRQ61S_SHIFT (13u) +#define INTC_ICR1_IRQ70S_SHIFT (14u) +#define INTC_ICR1_IRQ71S_SHIFT (15u) + +#define INTC_IRQRR_IRQ0F_SHIFT (0u) +#define INTC_IRQRR_IRQ1F_SHIFT (1u) +#define INTC_IRQRR_IRQ2F_SHIFT (2u) +#define INTC_IRQRR_IRQ3F_SHIFT (3u) +#define INTC_IRQRR_IRQ4F_SHIFT (4u) +#define INTC_IRQRR_IRQ5F_SHIFT (5u) +#define INTC_IRQRR_IRQ6F_SHIFT (6u) +#define INTC_IRQRR_IRQ7F_SHIFT (7u) + + +#endif /* INTC_IOBITMASK_H */ + +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,463 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : mtu2_iobitmask.h +* $Rev: 1138 $ +* $Date:: 2014-08-08 11:03:56 +0900#$ +* Description : MTU2 register define header +*******************************************************************************/ +#ifndef MTU2_IOBITMASK_H +#define MTU2_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define MTU2_TCR_n_TPSC (0x07u) +#define MTU2_TCR_n_CKEG (0x18u) +#define MTU2_TCR_n_CCLR (0xE0u) + +#define MTU2_TMDR_n_MD (0x0Fu) + +#define MTU2_TIOR_2_IOA (0x0Fu) +#define MTU2_TIOR_2_IOB (0xF0u) + +#define MTU2_TIER_n_TGIEA (0x01u) +#define MTU2_TIER_n_TGIEB (0x02u) +#define MTU2_TIER_n_TCIEV (0x10u) +#define MTU2_TIER_2_TCIEU (0x20u) +#define MTU2_TIER_n_TTGE (0x80u) + +#define MTU2_TSR_n_TGFA (0x01u) +#define MTU2_TSR_n_TGFB (0x02u) +#define MTU2_TSR_n_TCFV (0x10u) +#define MTU2_TSR_2_TCFU (0x20u) +#define MTU2_TSR_2_TCFD (0x80u) + +#define MTU2_TCNT_n_D (0xFFFFu) + +#define MTU2_TGRA_n_D (0xFFFFu) + +#define MTU2_TGRB_n_D (0xFFFFu) + +#define MTU2_TMDR_3_BFA (0x10u) +#define MTU2_TMDR_3_BFB (0x20u) + +#define MTU2_TMDR_4_BFA (0x10u) +#define MTU2_TMDR_4_BFB (0x20u) + +#define MTU2_TIORH_3_IOA (0x0Fu) +#define MTU2_TIORH_3_IOB (0xF0u) + +#define MTU2_TIORL_3_IOC (0x0Fu) +#define MTU2_TIORL_3_IOD (0xF0u) + +#define MTU2_TIORH_4_IOA (0x0Fu) +#define MTU2_TIORH_4_IOB (0xF0u) + +#define MTU2_TIORL_4_IOC (0x0Fu) +#define MTU2_TIORL_4_IOD (0xF0u) + +#define MTU2_TIER_3_TGIEC (0x04u) +#define MTU2_TIER_3_TGIED (0x08u) + +#define MTU2_TIER_4_TGIEC (0x04u) +#define MTU2_TIER_4_TGIED (0x08u) +#define MTU2_TIER_4_TTGE2 (0x40u) + +#define MTU2_TOER_OE3B (0x01u) +#define MTU2_TOER_OE4A (0x02u) +#define MTU2_TOER_OE4B (0x04u) +#define MTU2_TOER_OE3D (0x08u) +#define MTU2_TOER_OE4C (0x10u) +#define MTU2_TOER_OE4D (0x20u) + +#define MTU2_TGCR_UF (0x01u) +#define MTU2_TGCR_VF (0x02u) +#define MTU2_TGCR_WF (0x04u) +#define MTU2_TGCR_FB (0x08u) +#define MTU2_TGCR_P (0x10u) +#define MTU2_TGCR_N (0x20u) +#define MTU2_TGCR_BDC (0x40u) + +#define MTU2_TOCR1_OLSP (0x01u) +#define MTU2_TOCR1_OLSN (0x02u) +#define MTU2_TOCR1_TOCS (0x04u) +#define MTU2_TOCR1_TOCL (0x08u) +#define MTU2_TOCR1_PSYE (0x40u) + +#define MTU2_TOCR2_OLS1P (0x01u) +#define MTU2_TOCR2_OLS1N (0x02u) +#define MTU2_TOCR2_OLS2P (0x04u) +#define MTU2_TOCR2_OLS2N (0x08u) +#define MTU2_TOCR2_OLS3P (0x10u) +#define MTU2_TOCR2_OLS3N (0x20u) +#define MTU2_TOCR2_BF (0xC0u) + +#define MTU2_TCDR_D (0xFFFFu) + +#define MTU2_TDDR_D (0xFFFFu) + +#define MTU2_TCNTS_D (0xFFFFu) + +#define MTU2_TCBR_D (0xFFFFu) + +#define MTU2_TGRC_3_D (0xFFFFu) + +#define MTU2_TGRD_3_D (0xFFFFu) + +#define MTU2_TGRC_4_D (0xFFFFu) + +#define MTU2_TGRD_4_D (0xFFFFu) + +#define MTU2_TSR_3_TGFC (0x04u) +#define MTU2_TSR_3_TGFD (0x08u) +#define MTU2_TSR_3_TCFD (0x80u) + +#define MTU2_TSR_4_TGFC (0x04u) +#define MTU2_TSR_4_TGFD (0x08u) +#define MTU2_TSR_4_TCFD (0x80u) + +#define MTU2_TITCR_4VCOR (0x07u) +#define MTU2_TITCR_T4VEN (0x08u) +#define MTU2_TITCR_3ACOR (0x70u) +#define MTU2_TITCR_T3AEN (0x80u) + +#define MTU2_TITCNT_4VCNT (0x07u) +#define MTU2_TITCNT_3ACNT (0x70u) + +#define MTU2_TBTER_BTE (0x03u) + +#define MTU2_TDER_TDER (0x01u) + +#define MTU2_TOLBR_OLS1P (0x01u) +#define MTU2_TOLBR_OLS1N (0x02u) +#define MTU2_TOLBR_OLS2P (0x04u) +#define MTU2_TOLBR_OLS2N (0x08u) +#define MTU2_TOLBR_OLS3P (0x10u) +#define MTU2_TOLBR_OLS3N (0x20u) + +#define MTU2_TBTM_3_TTSA (0x01u) +#define MTU2_TBTM_3_TTSB (0x02u) + +#define MTU2_TBTM_4_TTSA (0x01u) +#define MTU2_TBTM_4_TTSB (0x02u) + +#define MTU2_TADCR_ITB4VE (0x0001u) +#define MTU2_TADCR_ITB3AE (0x0002u) +#define MTU2_TADCR_ITA4VE (0x0004u) +#define MTU2_TADCR_ITA3AE (0x0008u) +#define MTU2_TADCR_DT4BE (0x0010u) +#define MTU2_TADCR_UT4BE (0x0020u) +#define MTU2_TADCR_DT4AE (0x0040u) +#define MTU2_TADCR_UT4AE (0x0080u) +#define MTU2_TADCR_BF (0xC000u) + +#define MTU2_TADCORA_4_D (0xFFFFu) + +#define MTU2_TADCORB_4_D (0xFFFFu) + +#define MTU2_TADCOBRA_4_D (0xFFFFu) + +#define MTU2_TADCOBRB_4_D (0xFFFFu) + +#define MTU2_TWCR_WRE (0x01u) +#define MTU2_TWCR_CCE (0x80u) + +#define MTU2_TSTR_CST0 (0x01u) +#define MTU2_TSTR_CST1 (0x02u) +#define MTU2_TSTR_CST2 (0x04u) +#define MTU2_TSTR_CST3 (0x40u) +#define MTU2_TSTR_CST4 (0x80u) + +#define MTU2_TSYR_SYNC0 (0x01u) +#define MTU2_TSYR_SYNC1 (0x02u) +#define MTU2_TSYR_SYNC2 (0x04u) +#define MTU2_TSYR_SYNC3 (0x40u) +#define MTU2_TSYR_SYNC4 (0x80u) + +#define MTU2_TRWER_RWE (0x01u) + +#define MTU2_TMDR_0_BFA (0x10u) +#define MTU2_TMDR_0_BFB (0x20u) +#define MTU2_TMDR_0_BFE (0x40u) + +#define MTU2_TIORH_0_IOA (0x0Fu) +#define MTU2_TIORH_0_IOB (0xF0u) + +#define MTU2_TIORL_0_IOC (0x0Fu) +#define MTU2_TIORL_0_IOD (0xF0u) + +#define MTU2_TIER_0_TGIEC (0x04u) +#define MTU2_TIER_0_TGIED (0x08u) + +#define MTU2_TSR_0_TGFC (0x04u) +#define MTU2_TSR_0_TGFD (0x08u) + +#define MTU2_TGRC_0_D (0xFFFFu) + +#define MTU2_TGRD_0_D (0xFFFFu) + +#define MTU2_TGRE_0_D (0xFFFFu) + +#define MTU2_TGRF_0_D (0xFFFFu) + +#define MTU2_TIER2_0_TGIEE (0x01u) +#define MTU2_TIER2_0_TGIEF (0x02u) + +#define MTU2_TSR2_0_TGFE (0x01u) +#define MTU2_TSR2_0_TGFF (0x02u) + +#define MTU2_TBTM_0_TTSA (0x01u) +#define MTU2_TBTM_0_TTSB (0x02u) +#define MTU2_TBTM_0_TTSE (0x04u) + +#define MTU2_TIOR_1_IOA (0x0Fu) +#define MTU2_TIOR_1_IOB (0xF0u) + +#define MTU2_TIER_1_TCIEU (0x20u) + +#define MTU2_TSR_1_TCFU (0x20u) +#define MTU2_TSR_1_TCFD (0x80u) + +#define MTU2_TICCR_I1AE (0x01u) +#define MTU2_TICCR_I1BE (0x02u) +#define MTU2_TICCR_I2AE (0x04u) +#define MTU2_TICCR_I2BE (0x08u) + + +/* ==== Shift values for IO registers ==== */ +#define MTU2_TCR_n_TPSC_SHIFT (0u) +#define MTU2_TCR_n_CKEG_SHIFT (3u) +#define MTU2_TCR_n_CCLR_SHIFT (5u) + +#define MTU2_TMDR_n_MD_SHIFT (0u) + +#define MTU2_TIOR_2_IOA_SHIFT (0u) +#define MTU2_TIOR_2_IOB_SHIFT (4u) + +#define MTU2_TIER_n_TGIEA_SHIFT (0u) +#define MTU2_TIER_n_TGIEB_SHIFT (1u) +#define MTU2_TIER_n_TCIEV_SHIFT (4u) +#define MTU2_TIER_2_TCIEU_SHIFT (5u) +#define MTU2_TIER_n_TTGE_SHIFT (7u) + +#define MTU2_TSR_n_TGFA_SHIFT (0u) +#define MTU2_TSR_n_TGFB_SHIFT (1u) +#define MTU2_TSR_n_TCFV_SHIFT (4u) +#define MTU2_TSR_2_TCFU_SHIFT (5u) +#define MTU2_TSR_2_TCFD_SHIFT (7u) + +#define MTU2_TCNT_n_D_SHIFT (0u) + +#define MTU2_TGRA_n_D_SHIFT (0u) + +#define MTU2_TGRB_n_D_SHIFT (0u) + +#define MTU2_TMDR_3_BFA_SHIFT (4u) +#define MTU2_TMDR_3_BFB_SHIFT (5u) + +#define MTU2_TMDR_4_BFA_SHIFT (4u) +#define MTU2_TMDR_4_BFB_SHIFT (5u) + +#define MTU2_TIORH_3_IOA_SHIFT (0u) +#define MTU2_TIORH_3_IOB_SHIFT (4u) + +#define MTU2_TIORL_3_IOC_SHIFT (0u) +#define MTU2_TIORL_3_IOD_SHIFT (4u) + +#define MTU2_TIORH_4_IOA_SHIFT (0u) +#define MTU2_TIORH_4_IOB_SHIFT (4u) + +#define MTU2_TIORL_4_IOC_SHIFT (0u) +#define MTU2_TIORL_4_IOD_SHIFT (4u) + +#define MTU2_TIER_3_TGIEC_SHIFT (2u) +#define MTU2_TIER_3_TGIED_SHIFT (3u) + +#define MTU2_TIER_4_TGIEC_SHIFT (2u) +#define MTU2_TIER_4_TGIED_SHIFT (3u) +#define MTU2_TIER_4_TTGE2_SHIFT (6u) + +#define MTU2_TOER_OE3B_SHIFT (0u) +#define MTU2_TOER_OE4A_SHIFT (1u) +#define MTU2_TOER_OE4B_SHIFT (2u) +#define MTU2_TOER_OE3D_SHIFT (3u) +#define MTU2_TOER_OE4C_SHIFT (4u) +#define MTU2_TOER_OE4D_SHIFT (5u) + +#define MTU2_TGCR_UF_SHIFT (0u) +#define MTU2_TGCR_VF_SHIFT (1u) +#define MTU2_TGCR_WF_SHIFT (2u) +#define MTU2_TGCR_FB_SHIFT (3u) +#define MTU2_TGCR_P_SHIFT (4u) +#define MTU2_TGCR_N_SHIFT (5u) +#define MTU2_TGCR_BDC_SHIFT (6u) + +#define MTU2_TOCR1_OLSP_SHIFT (0u) +#define MTU2_TOCR1_OLSN_SHIFT (1u) +#define MTU2_TOCR1_TOCS_SHIFT (2u) +#define MTU2_TOCR1_TOCL_SHIFT (3u) +#define MTU2_TOCR1_PSYE_SHIFT (6u) + +#define MTU2_TOCR2_OLS1P_SHIFT (0u) +#define MTU2_TOCR2_OLS1N_SHIFT (1u) +#define MTU2_TOCR2_OLS2P_SHIFT (2u) +#define MTU2_TOCR2_OLS2N_SHIFT (3u) +#define MTU2_TOCR2_OLS3P_SHIFT (4u) +#define MTU2_TOCR2_OLS3N_SHIFT (5u) +#define MTU2_TOCR2_BF_SHIFT (6u) + +#define MTU2_TCDR_D_SHIFT (0u) + +#define MTU2_TDDR_D_SHIFT (0u) + +#define MTU2_TCNTS_D_SHIFT (0u) + +#define MTU2_TCBR_D_SHIFT (0u) + +#define MTU2_TGRC_3_D_SHIFT (0u) + +#define MTU2_TGRD_3_D_SHIFT (0u) + +#define MTU2_TGRC_4_D_SHIFT (0u) + +#define MTU2_TGRD_4_D_SHIFT (0u) + +#define MTU2_TSR_3_TGFC_SHIFT (2u) +#define MTU2_TSR_3_TGFD_SHIFT (3u) +#define MTU2_TSR_3_TCFD_SHIFT (7u) + +#define MTU2_TSR_4_TGFC_SHIFT (2u) +#define MTU2_TSR_4_TGFD_SHIFT (3u) +#define MTU2_TSR_4_TCFD_SHIFT (7u) + +#define MTU2_TITCR_4VCOR_SHIFT (0u) +#define MTU2_TITCR_T4VEN_SHIFT (3u) +#define MTU2_TITCR_3ACOR_SHIFT (4u) +#define MTU2_TITCR_T3AEN_SHIFT (7u) + +#define MTU2_TITCNT_4VCNT_SHIFT (0u) +#define MTU2_TITCNT_3ACNT_SHIFT (4u) + +#define MTU2_TBTER_BTE_SHIFT (0u) + +#define MTU2_TDER_TDER_SHIFT (0u) + +#define MTU2_TOLBR_OLS1P_SHIFT (0u) +#define MTU2_TOLBR_OLS1N_SHIFT (1u) +#define MTU2_TOLBR_OLS2P_SHIFT (2u) +#define MTU2_TOLBR_OLS2N_SHIFT (3u) +#define MTU2_TOLBR_OLS3P_SHIFT (4u) +#define MTU2_TOLBR_OLS3N_SHIFT (5u) + +#define MTU2_TBTM_3_TTSA_SHIFT (0u) +#define MTU2_TBTM_3_TTSB_SHIFT (1u) + +#define MTU2_TBTM_4_TTSA_SHIFT (0u) +#define MTU2_TBTM_4_TTSB_SHIFT (1u) + +#define MTU2_TADCR_ITB4VE_SHIFT (0u) +#define MTU2_TADCR_ITB3AE_SHIFT (1u) +#define MTU2_TADCR_ITA4VE_SHIFT (2u) +#define MTU2_TADCR_ITA3AE_SHIFT (3u) +#define MTU2_TADCR_DT4BE_SHIFT (4u) +#define MTU2_TADCR_UT4BE_SHIFT (5u) +#define MTU2_TADCR_DT4AE_SHIFT (6u) +#define MTU2_TADCR_UT4AE_SHIFT (7u) +#define MTU2_TADCR_BF_SHIFT (14u) + +#define MTU2_TADCORA_4_D_SHIFT (0u) + +#define MTU2_TADCORB_4_D_SHIFT (0u) + +#define MTU2_TADCOBRA_4_D_SHIFT (0u) + +#define MTU2_TADCOBRB_4_D_SHIFT (0u) + +#define MTU2_TWCR_WRE_SHIFT (0u) +#define MTU2_TWCR_CCE_SHIFT (7u) + +#define MTU2_TSTR_CST0_SHIFT (0u) +#define MTU2_TSTR_CST1_SHIFT (1u) +#define MTU2_TSTR_CST2_SHIFT (2u) +#define MTU2_TSTR_CST3_SHIFT (6u) +#define MTU2_TSTR_CST4_SHIFT (7u) + +#define MTU2_TSYR_SYNC0_SHIFT (0u) +#define MTU2_TSYR_SYNC1_SHIFT (1u) +#define MTU2_TSYR_SYNC2_SHIFT (2u) +#define MTU2_TSYR_SYNC3_SHIFT (6u) +#define MTU2_TSYR_SYNC4_SHIFT (7u) + +#define MTU2_TRWER_RWE_SHIFT (0u) + +#define MTU2_TMDR_0_BFA_SHIFT (4u) +#define MTU2_TMDR_0_BFB_SHIFT (5u) +#define MTU2_TMDR_0_BFE_SHIFT (6u) + +#define MTU2_TIORH_0_IOA_SHIFT (0u) +#define MTU2_TIORH_0_IOB_SHIFT (4u) + +#define MTU2_TIORL_0_IOC_SHIFT (0u) +#define MTU2_TIORL_0_IOD_SHIFT (4u) + +#define MTU2_TIER_0_TGIEC_SHIFT (2u) +#define MTU2_TIER_0_TGIED_SHIFT (3u) + +#define MTU2_TSR_0_TGFC_SHIFT (2u) +#define MTU2_TSR_0_TGFD_SHIFT (3u) + +#define MTU2_TGRC_0_D_SHIFT (0u) + +#define MTU2_TGRD_0_D_SHIFT (0u) + +#define MTU2_TGRE_0_D_SHIFT (0u) + +#define MTU2_TGRF_0_D_SHIFT (0u) + +#define MTU2_TIER2_0_TGIEE_SHIFT (0u) +#define MTU2_TIER2_0_TGIEF_SHIFT (1u) + +#define MTU2_TSR2_0_TGFE_SHIFT (0u) +#define MTU2_TSR2_0_TGFF_SHIFT (1u) + +#define MTU2_TBTM_0_TTSA_SHIFT (0u) +#define MTU2_TBTM_0_TTSB_SHIFT (1u) +#define MTU2_TBTM_0_TTSE_SHIFT (2u) + +#define MTU2_TIOR_1_IOA_SHIFT (0u) +#define MTU2_TIOR_1_IOB_SHIFT (4u) + +#define MTU2_TIER_1_TCIEU_SHIFT (5u) + +#define MTU2_TSR_1_TCFU_SHIFT (5u) +#define MTU2_TSR_1_TCFD_SHIFT (7u) + +#define MTU2_TICCR_I1AE_SHIFT (0u) +#define MTU2_TICCR_I1BE_SHIFT (1u) +#define MTU2_TICCR_I2AE_SHIFT (2u) +#define MTU2_TICCR_I2BE_SHIFT (3u) + + +#endif /* MTU2_IOBITMASK_H */ +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,124 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ostm_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : OSTM register define header +*******************************************************************************/ +#ifndef OSTM_IOBITMASK_H +#define OSTM_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +/* ---- OSTM0 ---- */ +#define OSTM0_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL) + +#define OSTM0_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL) + +#define OSTM0_OSTMnTE_OSTMnTE (0x01u) + +#define OSTM0_OSTMnTS_OSTMnTS (0x01u) + +#define OSTM0_OSTMnTT_OSTMnTT (0x01u) + +#define OSTM0_OSTMnCTL_MD0 (0x00000001uL) +#define OSTM0_OSTMnCTL_MD1 (0x00000002uL) + +/* ---- OSTM1 ---- */ +#define OSTM1_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL) + +#define OSTM1_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL) + +#define OSTM1_OSTMnTE_OSTMnTE (0x01u) + +#define OSTM1_OSTMnTS_OSTMnTS (0x01u) + +#define OSTM1_OSTMnTT_OSTMnTT (0x01u) + +#define OSTM1_OSTMnCTL_MD0 (0x00000001uL) +#define OSTM1_OSTMnCTL_MD1 (0x00000002uL) + +/* ---- OSTMn ---- */ +#define OSTMn_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL) + +#define OSTMn_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL) + +#define OSTMn_OSTMnTE_OSTMnTE (0x01u) + +#define OSTMn_OSTMnTS_OSTMnTS (0x01u) + +#define OSTMn_OSTMnTT_OSTMnTT (0x01u) + +#define OSTMn_OSTMnCTL_MD0 (0x00000001uL) +#define OSTMn_OSTMnCTL_MD1 (0x00000002uL) + + +/* ==== Shift values for IO registers ==== */ +/* ---- OSTM0 ---- */ +#define OSTM0_OSTMnCMP_OSTMnCMP_SHIFT (0u) + +#define OSTM0_OSTMnCNT_OSTMnCNT_SHIFT (0u) + +#define OSTM0_OSTMnTE_OSTMnTE_SHIFT (0u) + +#define OSTM0_OSTMnTS_OSTMnTS_SHIFT (0u) + +#define OSTM0_OSTMnTT_OSTMnTT_SHIFT (0u) + +#define OSTM0_OSTMnCTL_MD0_SHIFT (0u) +#define OSTM0_OSTMnCTL_MD1_SHIFT (1u) + +/* ---- OSTM1 ---- */ +#define OSTM1_OSTMnCMP_OSTMnCMP_SHIFT (0u) + +#define OSTM1_OSTMnCNT_OSTMnCNT_SHIFT (0u) + +#define OSTM1_OSTMnTE_OSTMnTE_SHIFT (0u) + +#define OSTM1_OSTMnTS_OSTMnTS_SHIFT (0u) + +#define OSTM1_OSTMnTT_OSTMnTT_SHIFT (0u) + +#define OSTM1_OSTMnCTL_MD0_SHIFT (0u) +#define OSTM1_OSTMnCTL_MD1_SHIFT (1u) + +/* ---- OSTMn ---- */ +#define OSTMn_OSTMnCMP_OSTMnCMP_SHIFT (0u) + +#define OSTMn_OSTMnCNT_OSTMnCNT_SHIFT (0u) + +#define OSTMn_OSTMnTE_OSTMnTE_SHIFT (0u) + +#define OSTMn_OSTMnTS_OSTMnTS_SHIFT (0u) + +#define OSTMn_OSTMnTT_OSTMnTT_SHIFT (0u) + +#define OSTMn_OSTMnCTL_MD0_SHIFT (0u) +#define OSTMn_OSTMnCTL_MD1_SHIFT (1u) + + +#endif /* OSTM_IOBITMASK_H */ + +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,232 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : riic_iobitmask.h +* $Rev: 1114 $ +* $Date:: 2014-07-09 14:56:39 +0900#$ +* Description : RIIC register define header +*******************************************************************************/ +#ifndef RIIC_IOBITMASK_H +#define RIIC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define RIICn_RIICnCR1_SDAI (0x01u) +#define RIICn_RIICnCR1_SCLI (0x02u) +#define RIICn_RIICnCR1_SDAO (0x04u) +#define RIICn_RIICnCR1_SCLO (0x08u) +#define RIICn_RIICnCR1_SOWP (0x10u) +#define RIICn_RIICnCR1_CLO (0x20u) +#define RIICn_RIICnCR1_IICRST (0x40u) +#define RIICn_RIICnCR1_ICE (0x80u) + +#define RIICn_RIICnCR2_ST (0x02u) +#define RIICn_RIICnCR2_RS (0x04u) +#define RIICn_RIICnCR2_SP (0x08u) +#define RIICn_RIICnCR2_TRS (0x20u) +#define RIICn_RIICnCR2_MST (0x40u) +#define RIICn_RIICnCR2_BBSY (0x80u) + +#define RIICn_RIICnMR1_BC (0x07u) +#define RIICn_RIICnMR1_BCWP (0x08u) +#define RIICn_RIICnMR1_CKS (0x70u) +#define RIICn_RIICnMR1_MTWP (0x80u) + +#define RIICn_RIICnMR2_TMOS (0x01u) +#define RIICn_RIICnMR2_TMOL (0x02u) +#define RIICn_RIICnMR2_TMOH (0x04u) +#define RIICn_RIICnMR2_SDDL (0x70u) +#define RIICn_RIICnMR2_DLCS (0x80u) + +#define RIICn_RIICnMR3_NF (0x03u) +#define RIICn_RIICnMR3_ACKBR (0x04u) +#define RIICn_RIICnMR3_ACKBT (0x08u) +#define RIICn_RIICnMR3_ACKWP (0x10u) +#define RIICn_RIICnMR3_RDRFS (0x20u) +#define RIICn_RIICnMR3_WAIT (0x40u) +#define RIICn_RIICnMR3_SMBS (0x80u) + +#define RIICn_RIICnFER_TMOE (0x01u) +#define RIICn_RIICnFER_MALE (0x02u) +#define RIICn_RIICnFER_NALE (0x04u) +#define RIICn_RIICnFER_SALE (0x08u) +#define RIICn_RIICnFER_NACKE (0x10u) +#define RIICn_RIICnFER_NFE (0x20u) +#define RIICn_RIICnFER_SCLE (0x40u) +#define RIICn_RIICnFER_FMPE (0x80u) + +#define RIICn_RIICnSER_SAR0E (0x01u) +#define RIICn_RIICnSER_SAR1E (0x02u) +#define RIICn_RIICnSER_SAR2E (0x04u) +#define RIICn_RIICnSER_GCAE (0x08u) +#define RIICn_RIICnSER_DIDE (0x20u) +#define RIICn_RIICnSER_HOAE (0x80u) + +#define RIICn_RIICnIER_TMOIE (0x01u) +#define RIICn_RIICnIER_ALIE (0x02u) +#define RIICn_RIICnIER_STIE (0x04u) +#define RIICn_RIICnIER_SPIE (0x08u) +#define RIICn_RIICnIER_NAKIE (0x10u) +#define RIICn_RIICnIER_RIE (0x20u) +#define RIICn_RIICnIER_TEIE (0x40u) +#define RIICn_RIICnIER_TIE (0x80u) + +#define RIICn_RIICnSR1_AAS0 (0x01u) +#define RIICn_RIICnSR1_AAS1 (0x02u) +#define RIICn_RIICnSR1_AAS2 (0x04u) +#define RIICn_RIICnSR1_GCA (0x08u) +#define RIICn_RIICnSR1_DID (0x20u) +#define RIICn_RIICnSR1_HOA (0x80u) + +#define RIICn_RIICnSR2_TMOF (0x01u) +#define RIICn_RIICnSR2_AL (0x02u) +#define RIICn_RIICnSR2_START (0x04u) +#define RIICn_RIICnSR2_STOP (0x08u) +#define RIICn_RIICnSR2_NACKF (0x10u) +#define RIICn_RIICnSR2_RDRF (0x20u) +#define RIICn_RIICnSR2_TEND (0x40u) +#define RIICn_RIICnSR2_TDRE (0x80u) + +#define RIICn_RIICnSAR0_SVA0 (0x0001u) +#define RIICn_RIICnSAR0_SVA (0x03FEu) +#define RIICn_RIICnSAR0_FSy (0x8000u) + +#define RIICn_RIICnSAR1_SVA0 (0x0001u) +#define RIICn_RIICnSAR1_SVA (0x03FEu) +#define RIICn_RIICnSAR1_FSy (0x8000u) + +#define RIICn_RIICnSAR2_SVA0 (0x0001u) +#define RIICn_RIICnSAR2_SVA (0x03FEu) +#define RIICn_RIICnSAR2_FSy (0x8000u) + +#define RIICn_RIICnBRL_BRL (0x1Fu) + +#define RIICn_RIICnBRH_BRH (0x1Fu) + +#define RIICn_RIICnDRT_DRT (0xFFu) + +#define RIICn_RIICnDRR_DRR (0xFFu) + + +/* ==== Shift values for IO registers ==== */ +#define RIICn_RIICnCR1_SDAI_SHIFT (0u) +#define RIICn_RIICnCR1_SCLI_SHIFT (1u) +#define RIICn_RIICnCR1_SDAO_SHIFT (2u) +#define RIICn_RIICnCR1_SCLO_SHIFT (3u) +#define RIICn_RIICnCR1_SOWP_SHIFT (4u) +#define RIICn_RIICnCR1_CLO_SHIFT (5u) +#define RIICn_RIICnCR1_IICRST_SHIFT (6u) +#define RIICn_RIICnCR1_ICE_SHIFT (7u) + +#define RIICn_RIICnCR2_ST_SHIFT (1u) +#define RIICn_RIICnCR2_RS_SHIFT (2u) +#define RIICn_RIICnCR2_SP_SHIFT (3u) +#define RIICn_RIICnCR2_TRS_SHIFT (5u) +#define RIICn_RIICnCR2_MST_SHIFT (6u) +#define RIICn_RIICnCR2_BBSY_SHIFT (7u) + +#define RIICn_RIICnMR1_BC_SHIFT (0u) +#define RIICn_RIICnMR1_BCWP_SHIFT (3u) +#define RIICn_RIICnMR1_CKS_SHIFT (4u) +#define RIICn_RIICnMR1_MTWP_SHIFT (7u) + +#define RIICn_RIICnMR2_TMOS_SHIFT (0u) +#define RIICn_RIICnMR2_TMOL_SHIFT (1u) +#define RIICn_RIICnMR2_TMOH_SHIFT (2u) +#define RIICn_RIICnMR2_SDDL_SHIFT (4u) +#define RIICn_RIICnMR2_DLCS_SHIFT (7u) + +#define RIICn_RIICnMR3_NF_SHIFT (0u) +#define RIICn_RIICnMR3_ACKBR_SHIFT (2u) +#define RIICn_RIICnMR3_ACKBT_SHIFT (3u) +#define RIICn_RIICnMR3_ACKWP_SHIFT (4u) +#define RIICn_RIICnMR3_RDRFS_SHIFT (5u) +#define RIICn_RIICnMR3_WAIT_SHIFT (6u) +#define RIICn_RIICnMR3_SMBS_SHIFT (7u) + +#define RIICn_RIICnFER_TMOE_SHIFT (0u) +#define RIICn_RIICnFER_MALE_SHIFT (1u) +#define RIICn_RIICnFER_NALE_SHIFT (2u) +#define RIICn_RIICnFER_SALE_SHIFT (3u) +#define RIICn_RIICnFER_NACKE_SHIFT (4u) +#define RIICn_RIICnFER_NFE_SHIFT (5u) +#define RIICn_RIICnFER_SCLE_SHIFT (6u) +#define RIICn_RIICnFER_FMPE_SHIFT (7u) + +#define RIICn_RIICnSER_SAR0E_SHIFT (0u) +#define RIICn_RIICnSER_SAR1E_SHIFT (1u) +#define RIICn_RIICnSER_SAR2E_SHIFT (2u) +#define RIICn_RIICnSER_GCAE_SHIFT (3u) +#define RIICn_RIICnSER_DIDE_SHIFT (5u) +#define RIICn_RIICnSER_HOAE_SHIFT (7u) + +#define RIICn_RIICnIER_TMOIE_SHIFT (0u) +#define RIICn_RIICnIER_ALIE_SHIFT (1u) +#define RIICn_RIICnIER_STIE_SHIFT (2u) +#define RIICn_RIICnIER_SPIE_SHIFT (3u) +#define RIICn_RIICnIER_NAKIE_SHIFT (4u) +#define RIICn_RIICnIER_RIE_SHIFT (5u) +#define RIICn_RIICnIER_TEIE_SHIFT (6u) +#define RIICn_RIICnIER_TIE_SHIFT (7u) + +#define RIICn_RIICnSR1_AAS0_SHIFT (0u) +#define RIICn_RIICnSR1_AAS1_SHIFT (1u) +#define RIICn_RIICnSR1_AAS2_SHIFT (2u) +#define RIICn_RIICnSR1_GCA_SHIFT (3u) +#define RIICn_RIICnSR1_DID_SHIFT (5u) +#define RIICn_RIICnSR1_HOA_SHIFT (7u) + +#define RIICn_RIICnSR2_TMOF_SHIFT (0u) +#define RIICn_RIICnSR2_AL_SHIFT (1u) +#define RIICn_RIICnSR2_START_SHIFT (2u) +#define RIICn_RIICnSR2_STOP_SHIFT (3u) +#define RIICn_RIICnSR2_NACKF_SHIFT (4u) +#define RIICn_RIICnSR2_RDRF_SHIFT (5u) +#define RIICn_RIICnSR2_TEND_SHIFT (6u) +#define RIICn_RIICnSR2_TDRE_SHIFT (7u) + +#define RIICn_RIICnSAR0_SVA0_SHIFT (0u) +#define RIICn_RIICnSAR0_SVA_SHIFT (1u) +#define RIICn_RIICnSAR0_FSy_SHIFT (15u) + +#define RIICn_RIICnSAR1_SVA0_SHIFT (0u) +#define RIICn_RIICnSAR1_SVA_SHIFT (1u) +#define RIICn_RIICnSAR1_FSy_SHIFT (15u) + +#define RIICn_RIICnSAR2_SVA0_SHIFT (0u) +#define RIICn_RIICnSAR2_SVA_SHIFT (1u) +#define RIICn_RIICnSAR2_FSy_SHIFT (15u) + +#define RIICn_RIICnBRL_BRL_SHIFT (0u) + +#define RIICn_RIICnBRH_BRH_SHIFT (0u) + +#define RIICn_RIICnDRT_DRT_SHIFT (0u) + +#define RIICn_RIICnDRR_DRR_SHIFT (0u) + + +#endif /* RIIC_IOBITMASK_H */ + +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,216 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rspi_iobitmask.h +* $Rev: 1114 $ +* $Date:: 2014-07-09 14:56:39 +0900#$ +* Description : Renesas Serial Peripheral Interface register define header +*******************************************************************************/ +#ifndef RSPI_IOBITMASK_H +#define RSPI_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define RSPIn_SPCR_MODFEN (0x04u) +#define RSPIn_SPCR_MSTR (0x08u) +#define RSPIn_SPCR_SPEIE (0x10u) +#define RSPIn_SPCR_SPTIE (0x20u) +#define RSPIn_SPCR_SPE (0x40u) +#define RSPIn_SPCR_SPRIE (0x80u) + +#define RSPIn_SSLP_SSL0P (0x01u) + +#define RSPIn_SPPCR_SPLP (0x01u) +#define RSPIn_SPPCR_MOIFV (0x10u) +#define RSPIn_SPPCR_MOIFE (0x20u) + +#define RSPIn_SPSR_OVRF (0x01u) +#define RSPIn_SPSR_MODF (0x04u) +#define RSPIn_SPSR_SPTEF (0x20u) +#define RSPIn_SPSR_TEND (0x40u) +#define RSPIn_SPSR_SPRF (0x80u) + +#define RSPIn_SPDR_UINT32 (0xFFFFFFFFuL) + +#define RSPIn_SPDR_UINT16 (0xFFFFu) + +#define RSPIn_SPDR_UINT8 (0xFFu) + +#define RSPIn_SPSCR_SPSLN (0x03u) + +#define RSPIn_SPSSR_SPCP (0x03u) + +#define RSPIn_SPBR_SPR (0xFFu) + +#define RSPIn_SPDCR_SPLW (0x60u) +#define RSPIn_SPDCR_TXDMY (0x80u) + +#define RSPIn_SPCKD_SCKDL (0x07u) + +#define RSPIn_SSLND_SLNDL (0x07u) + +#define RSPIn_SPND_SPNDL (0x07u) + +#define RSPIn_SPCMD0_CPHA (0x0001u) +#define RSPIn_SPCMD0_CPOL (0x0002u) +#define RSPIn_SPCMD0_BRDV (0x000Cu) +#define RSPIn_SPCMD0_SSLKP (0x0080u) +#define RSPIn_SPCMD0_SPB (0x0F00u) +#define RSPIn_SPCMD0_LSBF (0x1000u) +#define RSPIn_SPCMD0_SPNDEN (0x2000u) +#define RSPIn_SPCMD0_SLNDEN (0x4000u) +#define RSPIn_SPCMD0_SCKDEN (0x8000u) + +#define RSPIn_SPCMD1_CPHA (0x0001u) +#define RSPIn_SPCMD1_CPOL (0x0002u) +#define RSPIn_SPCMD1_BRDV (0x000Cu) +#define RSPIn_SPCMD1_SSLKP (0x0080u) +#define RSPIn_SPCMD1_SPB (0x0F00u) +#define RSPIn_SPCMD1_LSBF (0x1000u) +#define RSPIn_SPCMD1_SPNDEN (0x2000u) +#define RSPIn_SPCMD1_SLNDEN (0x4000u) +#define RSPIn_SPCMD1_SCKDEN (0x8000u) + +#define RSPIn_SPCMD2_CPHA (0x0001u) +#define RSPIn_SPCMD2_CPOL (0x0002u) +#define RSPIn_SPCMD2_BRDV (0x000Cu) +#define RSPIn_SPCMD2_SSLKP (0x0080u) +#define RSPIn_SPCMD2_SPB (0x0F00u) +#define RSPIn_SPCMD2_LSBF (0x1000u) +#define RSPIn_SPCMD2_SPNDEN (0x2000u) +#define RSPIn_SPCMD2_SLNDEN (0x4000u) +#define RSPIn_SPCMD2_SCKDEN (0x8000u) + +#define RSPIn_SPCMD3_CPHA (0x0001u) +#define RSPIn_SPCMD3_CPOL (0x0002u) +#define RSPIn_SPCMD3_BRDV (0x000Cu) +#define RSPIn_SPCMD3_SSLKP (0x0080u) +#define RSPIn_SPCMD3_SPB (0x0F00u) +#define RSPIn_SPCMD3_LSBF (0x1000u) +#define RSPIn_SPCMD3_SPNDEN (0x2000u) +#define RSPIn_SPCMD3_SLNDEN (0x4000u) +#define RSPIn_SPCMD3_SCKDEN (0x8000u) + +#define RSPIn_SPBFCR_RXTRG (0x07u) +#define RSPIn_SPBFCR_TXTRG (0x30u) +#define RSPIn_SPBFCR_RXRST (0x40u) +#define RSPIn_SPBFCR_TXRST (0x80u) + +#define RSPIn_SPBFDR_R (0x003Fu) +#define RSPIn_SPBFDR_T (0x0F00u) + + +/* ==== Shift values for IO registers ==== */ +#define RSPIn_SPCR_MODFEN_SHIFT (2u) +#define RSPIn_SPCR_MSTR_SHIFT (3u) +#define RSPIn_SPCR_SPEIE_SHIFT (4u) +#define RSPIn_SPCR_SPTIE_SHIFT (5u) +#define RSPIn_SPCR_SPE_SHIFT (6u) +#define RSPIn_SPCR_SPRIE_SHIFT (7u) + +#define RSPIn_SSLP_SSL0P_SHIFT (0u) + +#define RSPIn_SPPCR_SPLP_SHIFT (0u) +#define RSPIn_SPPCR_MOIFV_SHIFT (4u) +#define RSPIn_SPPCR_MOIFE_SHIFT (5u) + +#define RSPIn_SPSR_OVRF_SHIFT (0u) +#define RSPIn_SPSR_MODF_SHIFT (2u) +#define RSPIn_SPSR_SPTEF_SHIFT (5u) +#define RSPIn_SPSR_TEND_SHIFT (6u) +#define RSPIn_SPSR_SPRF_SHIFT (7u) + +#define RSPIn_SPDR_UINT32_SHIFT (0u) + +#define RSPIn_SPDR_UINT16_SHIFT (0u) + +#define RSPIn_SPDR_UINT8_SHIFT (0u) + +#define RSPIn_SPSCR_SPSLN_SHIFT (0u) + +#define RSPIn_SPSSR_SPCP_SHIFT (0u) + +#define RSPIn_SPBR_SPR_SHIFT (0u) + +#define RSPIn_SPDCR_SPLW_SHIFT (5u) +#define RSPIn_SPDCR_TXDMY_SHIFT (7u) + +#define RSPIn_SPCKD_SCKDL_SHIFT (0u) + +#define RSPIn_SSLND_SLNDL_SHIFT (0u) + +#define RSPIn_SPND_SPNDL_SHIFT (0u) + +#define RSPIn_SPCMD0_CPHA_SHIFT (0u) +#define RSPIn_SPCMD0_CPOL_SHIFT (1u) +#define RSPIn_SPCMD0_BRDV_SHIFT (2u) +#define RSPIn_SPCMD0_SSLKP_SHIFT (7u) +#define RSPIn_SPCMD0_SPB_SHIFT (8u) +#define RSPIn_SPCMD0_LSBF_SHIFT (12u) +#define RSPIn_SPCMD0_SPNDEN_SHIFT (13u) +#define RSPIn_SPCMD0_SLNDEN_SHIFT (14u) +#define RSPIn_SPCMD0_SCKDEN_SHIFT (15u) + +#define RSPIn_SPCMD1_CPHA_SHIFT (0u) +#define RSPIn_SPCMD1_CPOL_SHIFT (1u) +#define RSPIn_SPCMD1_BRDV_SHIFT (2u) +#define RSPIn_SPCMD1_SSLKP_SHIFT (7u) +#define RSPIn_SPCMD1_SPB_SHIFT (8u) +#define RSPIn_SPCMD1_LSBF_SHIFT (12u) +#define RSPIn_SPCMD1_SPNDEN_SHIFT (13u) +#define RSPIn_SPCMD1_SLNDEN_SHIFT (14u) +#define RSPIn_SPCMD1_SCKDEN_SHIFT (15u) + +#define RSPIn_SPCMD2_CPHA_SHIFT (0u) +#define RSPIn_SPCMD2_CPOL_SHIFT (1u) +#define RSPIn_SPCMD2_BRDV_SHIFT (2u) +#define RSPIn_SPCMD2_SSLKP_SHIFT (7u) +#define RSPIn_SPCMD2_SPB_SHIFT (8u) +#define RSPIn_SPCMD2_LSBF_SHIFT (12u) +#define RSPIn_SPCMD2_SPNDEN_SHIFT (13u) +#define RSPIn_SPCMD2_SLNDEN_SHIFT (14u) +#define RSPIn_SPCMD2_SCKDEN_SHIFT (15u) + +#define RSPIn_SPCMD3_CPHA_SHIFT (0u) +#define RSPIn_SPCMD3_CPOL_SHIFT (1u) +#define RSPIn_SPCMD3_BRDV_SHIFT (2u) +#define RSPIn_SPCMD3_SSLKP_SHIFT (7u) +#define RSPIn_SPCMD3_SPB_SHIFT (8u) +#define RSPIn_SPCMD3_LSBF_SHIFT (12u) +#define RSPIn_SPCMD3_SPNDEN_SHIFT (13u) +#define RSPIn_SPCMD3_SLNDEN_SHIFT (14u) +#define RSPIn_SPCMD3_SCKDEN_SHIFT (15u) + +#define RSPIn_SPBFCR_RXTRG_SHIFT (0u) +#define RSPIn_SPBFCR_TXTRG_SHIFT (4u) +#define RSPIn_SPBFCR_RXRST_SHIFT (6u) +#define RSPIn_SPBFCR_TXRST_SHIFT (7u) + +#define RSPIn_SPBFDR_R_SHIFT (0u) +#define RSPIn_SPBFDR_T_SHIFT (8u) + + +#endif /* RSPI_IOBITMASK_H */ + +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,1066 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : scif_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : SCIF register define header +*******************************************************************************/ +#ifndef SCIF_IOBITMASK_H +#define SCIF_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +/* ---- SCIF0 ---- */ +#define SCIF0_SCSMR_CKS (0x0003u) +#define SCIF0_SCSMR_STOP (0x0008u) +#define SCIF0_SCSMR_OE (0x0010u) +#define SCIF0_SCSMR_PE (0x0020u) +#define SCIF0_SCSMR_CHR (0x0040u) +#define SCIF0_SCSMR_CA (0x0080u) + +#define SCIF0_SCBRR_D (0xFFu) + +#define SCIF0_SCSCR_CKE (0x0003u) +#define SCIF0_SCSCR_REIE (0x0008u) +#define SCIF0_SCSCR_RE (0x0010u) +#define SCIF0_SCSCR_TE (0x0020u) +#define SCIF0_SCSCR_RIE (0x0040u) +#define SCIF0_SCSCR_TIE (0x0080u) + +#define SCIF0_SCFTDR_D (0xFFu) + +#define SCIF0_SCFSR_DR (0x0001u) +#define SCIF0_SCFSR_RDF (0x0002u) +#define SCIF0_SCFSR_PER (0x0004u) +#define SCIF0_SCFSR_FER (0x0008u) +#define SCIF0_SCFSR_BRK (0x0010u) +#define SCIF0_SCFSR_TDFE (0x0020u) +#define SCIF0_SCFSR_TEND (0x0040u) +#define SCIF0_SCFSR_ER (0x0080u) +#define SCIF0_SCFSR_FERN (0x0F00u) +#define SCIF0_SCFSR_PERN (0xF000u) + +#define SCIF0_SCFRDR_D (0xFFu) + +#define SCIF0_SCFCR_LOOP (0x0001u) +#define SCIF0_SCFCR_RFRST (0x0002u) +#define SCIF0_SCFCR_TFRST (0x0004u) +#define SCIF0_SCFCR_MCE (0x0008u) +#define SCIF0_SCFCR_TTRG (0x0030u) +#define SCIF0_SCFCR_RTRG (0x00C0u) +#define SCIF0_SCFCR_RSTRG (0x0700u) + +#define SCIF0_SCFDR_R (0x001Fu) +#define SCIF0_SCFDR_T (0x1F00u) + +#define SCIF0_SCSPTR_SPB2DT (0x0001u) +#define SCIF0_SCSPTR_SPB2IO (0x0002u) +#define SCIF0_SCSPTR_SCKDT (0x0004u) +#define SCIF0_SCSPTR_SCKIO (0x0008u) +#define SCIF0_SCSPTR_CTSDT (0x0010u) +#define SCIF0_SCSPTR_CTSIO (0x0020u) +#define SCIF0_SCSPTR_RTSDT (0x0040u) +#define SCIF0_SCSPTR_RTSIO (0x0080u) + +#define SCIF0_SCLSR_ORER (0x0001u) + +#define SCIF0_SCEMR_ABCS (0x0001u) +#define SCIF0_SCEMR_BGDM (0x0080u) + +/* ---- SCIF1 ---- */ +#define SCIF1_SCSMR_CKS (0x0003u) +#define SCIF1_SCSMR_STOP (0x0008u) +#define SCIF1_SCSMR_OE (0x0010u) +#define SCIF1_SCSMR_PE (0x0020u) +#define SCIF1_SCSMR_CHR (0x0040u) +#define SCIF1_SCSMR_CA (0x0080u) + +#define SCIF1_SCBRR_D (0xFFu) + +#define SCIF1_SCSCR_CKE (0x0003u) +#define SCIF1_SCSCR_REIE (0x0008u) +#define SCIF1_SCSCR_RE (0x0010u) +#define SCIF1_SCSCR_TE (0x0020u) +#define SCIF1_SCSCR_RIE (0x0040u) +#define SCIF1_SCSCR_TIE (0x0080u) + +#define SCIF1_SCFTDR_D (0xFFu) + +#define SCIF1_SCFSR_DR (0x0001u) +#define SCIF1_SCFSR_RDF (0x0002u) +#define SCIF1_SCFSR_PER (0x0004u) +#define SCIF1_SCFSR_FER (0x0008u) +#define SCIF1_SCFSR_BRK (0x0010u) +#define SCIF1_SCFSR_TDFE (0x0020u) +#define SCIF1_SCFSR_TEND (0x0040u) +#define SCIF1_SCFSR_ER (0x0080u) +#define SCIF1_SCFSR_FERN (0x0F00u) +#define SCIF1_SCFSR_PERN (0xF000u) + +#define SCIF1_SCFRDR_D (0xFFu) + +#define SCIF1_SCFCR_LOOP (0x0001u) +#define SCIF1_SCFCR_RFRST (0x0002u) +#define SCIF1_SCFCR_TFRST (0x0004u) +#define SCIF1_SCFCR_MCE (0x0008u) +#define SCIF1_SCFCR_TTRG (0x0030u) +#define SCIF1_SCFCR_RTRG (0x00C0u) +#define SCIF1_SCFCR_RSTRG (0x0700u) + +#define SCIF1_SCFDR_R (0x001Fu) +#define SCIF1_SCFDR_T (0x1F00u) + +#define SCIF1_SCSPTR_SPB2DT (0x0001u) +#define SCIF1_SCSPTR_SPB2IO (0x0002u) +#define SCIF1_SCSPTR_SCKDT (0x0004u) +#define SCIF1_SCSPTR_SCKIO (0x0008u) +#define SCIF1_SCSPTR_CTSDT (0x0010u) +#define SCIF1_SCSPTR_CTSIO (0x0020u) +#define SCIF1_SCSPTR_RTSDT (0x0040u) +#define SCIF1_SCSPTR_RTSIO (0x0080u) + +#define SCIF1_SCLSR_ORER (0x0001u) + +#define SCIF1_SCEMR_ABCS (0x0001u) +#define SCIF1_SCEMR_BGDM (0x0080u) + +/* ---- SCIF2 ---- */ +#define SCIF2_SCSMR_CKS (0x0003u) +#define SCIF2_SCSMR_STOP (0x0008u) +#define SCIF2_SCSMR_OE (0x0010u) +#define SCIF2_SCSMR_PE (0x0020u) +#define SCIF2_SCSMR_CHR (0x0040u) +#define SCIF2_SCSMR_CA (0x0080u) + +#define SCIF2_SCBRR_D (0xFFu) + +#define SCIF2_SCSCR_CKE (0x0003u) +#define SCIF2_SCSCR_REIE (0x0008u) +#define SCIF2_SCSCR_RE (0x0010u) +#define SCIF2_SCSCR_TE (0x0020u) +#define SCIF2_SCSCR_RIE (0x0040u) +#define SCIF2_SCSCR_TIE (0x0080u) + +#define SCIF2_SCFTDR_D (0xFFu) + +#define SCIF2_SCFSR_DR (0x0001u) +#define SCIF2_SCFSR_RDF (0x0002u) +#define SCIF2_SCFSR_PER (0x0004u) +#define SCIF2_SCFSR_FER (0x0008u) +#define SCIF2_SCFSR_BRK (0x0010u) +#define SCIF2_SCFSR_TDFE (0x0020u) +#define SCIF2_SCFSR_TEND (0x0040u) +#define SCIF2_SCFSR_ER (0x0080u) +#define SCIF2_SCFSR_FERN (0x0F00u) +#define SCIF2_SCFSR_PERN (0xF000u) + +#define SCIF2_SCFRDR_D (0xFFu) + +#define SCIF2_SCFCR_LOOP (0x0001u) +#define SCIF2_SCFCR_RFRST (0x0002u) +#define SCIF2_SCFCR_TFRST (0x0004u) +#define SCIF2_SCFCR_MCE (0x0008u) +#define SCIF2_SCFCR_TTRG (0x0030u) +#define SCIF2_SCFCR_RTRG (0x00C0u) +#define SCIF2_SCFCR_RSTRG (0x0700u) + +#define SCIF2_SCFDR_R (0x001Fu) +#define SCIF2_SCFDR_T (0x1F00u) + +#define SCIF2_SCSPTR_SPB2DT (0x0001u) +#define SCIF2_SCSPTR_SPB2IO (0x0002u) +#define SCIF2_SCSPTR_SCKDT (0x0004u) +#define SCIF2_SCSPTR_SCKIO (0x0008u) +#define SCIF2_SCSPTR_CTSDT (0x0010u) +#define SCIF2_SCSPTR_CTSIO (0x0020u) +#define SCIF2_SCSPTR_RTSDT (0x0040u) +#define SCIF2_SCSPTR_RTSIO (0x0080u) + +#define SCIF2_SCLSR_ORER (0x0001u) + +#define SCIF2_SCEMR_ABCS (0x0001u) +#define SCIF2_SCEMR_BGDM (0x0080u) + +/* ---- SCIF3 ---- */ +#define SCIF3_SCSMR_CKS (0x0003u) +#define SCIF3_SCSMR_STOP (0x0008u) +#define SCIF3_SCSMR_OE (0x0010u) +#define SCIF3_SCSMR_PE (0x0020u) +#define SCIF3_SCSMR_CHR (0x0040u) +#define SCIF3_SCSMR_CA (0x0080u) + +#define SCIF3_SCBRR_D (0xFFu) + +#define SCIF3_SCSCR_CKE (0x0003u) +#define SCIF3_SCSCR_REIE (0x0008u) +#define SCIF3_SCSCR_RE (0x0010u) +#define SCIF3_SCSCR_TE (0x0020u) +#define SCIF3_SCSCR_RIE (0x0040u) +#define SCIF3_SCSCR_TIE (0x0080u) + +#define SCIF3_SCFTDR_D (0xFFu) + +#define SCIF3_SCFSR_DR (0x0001u) +#define SCIF3_SCFSR_RDF (0x0002u) +#define SCIF3_SCFSR_PER (0x0004u) +#define SCIF3_SCFSR_FER (0x0008u) +#define SCIF3_SCFSR_BRK (0x0010u) +#define SCIF3_SCFSR_TDFE (0x0020u) +#define SCIF3_SCFSR_TEND (0x0040u) +#define SCIF3_SCFSR_ER (0x0080u) +#define SCIF3_SCFSR_FERN (0x0F00u) +#define SCIF3_SCFSR_PERN (0xF000u) + +#define SCIF3_SCFRDR_D (0xFFu) + +#define SCIF3_SCFCR_LOOP (0x0001u) +#define SCIF3_SCFCR_RFRST (0x0002u) +#define SCIF3_SCFCR_TFRST (0x0004u) +#define SCIF3_SCFCR_MCE (0x0008u) +#define SCIF3_SCFCR_TTRG (0x0030u) +#define SCIF3_SCFCR_RTRG (0x00C0u) +#define SCIF3_SCFCR_RSTRG (0x0700u) + +#define SCIF3_SCFDR_R (0x001Fu) +#define SCIF3_SCFDR_T (0x1F00u) + +#define SCIF3_SCSPTR_SPB2DT (0x0001u) +#define SCIF3_SCSPTR_SPB2IO (0x0002u) +#define SCIF3_SCSPTR_SCKDT (0x0004u) +#define SCIF3_SCSPTR_SCKIO (0x0008u) +#define SCIF3_SCSPTR_CTSDT (0x0010u) +#define SCIF3_SCSPTR_CTSIO (0x0020u) +#define SCIF3_SCSPTR_RTSDT (0x0040u) +#define SCIF3_SCSPTR_RTSIO (0x0080u) + +#define SCIF3_SCLSR_ORER (0x0001u) + +#define SCIF3_SCEMR_ABCS (0x0001u) +#define SCIF3_SCEMR_BGDM (0x0080u) + +/* ---- SCIF4 ---- */ +#define SCIF4_SCSMR_CKS (0x0003u) +#define SCIF4_SCSMR_STOP (0x0008u) +#define SCIF4_SCSMR_OE (0x0010u) +#define SCIF4_SCSMR_PE (0x0020u) +#define SCIF4_SCSMR_CHR (0x0040u) +#define SCIF4_SCSMR_CA (0x0080u) + +#define SCIF4_SCBRR_D (0xFFu) + +#define SCIF4_SCSCR_CKE (0x0003u) +#define SCIF4_SCSCR_REIE (0x0008u) +#define SCIF4_SCSCR_RE (0x0010u) +#define SCIF4_SCSCR_TE (0x0020u) +#define SCIF4_SCSCR_RIE (0x0040u) +#define SCIF4_SCSCR_TIE (0x0080u) + +#define SCIF4_SCFTDR_D (0xFFu) + +#define SCIF4_SCFSR_DR (0x0001u) +#define SCIF4_SCFSR_RDF (0x0002u) +#define SCIF4_SCFSR_PER (0x0004u) +#define SCIF4_SCFSR_FER (0x0008u) +#define SCIF4_SCFSR_BRK (0x0010u) +#define SCIF4_SCFSR_TDFE (0x0020u) +#define SCIF4_SCFSR_TEND (0x0040u) +#define SCIF4_SCFSR_ER (0x0080u) +#define SCIF4_SCFSR_FERN (0x0F00u) +#define SCIF4_SCFSR_PERN (0xF000u) + +#define SCIF4_SCFRDR_D (0xFFu) + +#define SCIF4_SCFCR_LOOP (0x0001u) +#define SCIF4_SCFCR_RFRST (0x0002u) +#define SCIF4_SCFCR_TFRST (0x0004u) +#define SCIF4_SCFCR_MCE (0x0008u) +#define SCIF4_SCFCR_TTRG (0x0030u) +#define SCIF4_SCFCR_RTRG (0x00C0u) +#define SCIF4_SCFCR_RSTRG (0x0700u) + +#define SCIF4_SCFDR_R (0x001Fu) +#define SCIF4_SCFDR_T (0x1F00u) + +#define SCIF4_SCSPTR_SPB2DT (0x0001u) +#define SCIF4_SCSPTR_SPB2IO (0x0002u) +#define SCIF4_SCSPTR_SCKDT (0x0004u) +#define SCIF4_SCSPTR_SCKIO (0x0008u) +#define SCIF4_SCSPTR_CTSDT (0x0010u) +#define SCIF4_SCSPTR_CTSIO (0x0020u) +#define SCIF4_SCSPTR_RTSDT (0x0040u) +#define SCIF4_SCSPTR_RTSIO (0x0080u) + +#define SCIF4_SCLSR_ORER (0x0001u) + +#define SCIF4_SCEMR_ABCS (0x0001u) +#define SCIF4_SCEMR_BGDM (0x0080u) + +/* ---- SCIF5 ---- */ +#define SCIF5_SCSMR_CKS (0x0003u) +#define SCIF5_SCSMR_STOP (0x0008u) +#define SCIF5_SCSMR_OE (0x0010u) +#define SCIF5_SCSMR_PE (0x0020u) +#define SCIF5_SCSMR_CHR (0x0040u) +#define SCIF5_SCSMR_CA (0x0080u) + +#define SCIF5_SCBRR_D (0xFFu) + +#define SCIF5_SCSCR_CKE (0x0003u) +#define SCIF5_SCSCR_REIE (0x0008u) +#define SCIF5_SCSCR_RE (0x0010u) +#define SCIF5_SCSCR_TE (0x0020u) +#define SCIF5_SCSCR_RIE (0x0040u) +#define SCIF5_SCSCR_TIE (0x0080u) + +#define SCIF5_SCFTDR_D (0xFFu) + +#define SCIF5_SCFSR_DR (0x0001u) +#define SCIF5_SCFSR_RDF (0x0002u) +#define SCIF5_SCFSR_PER (0x0004u) +#define SCIF5_SCFSR_FER (0x0008u) +#define SCIF5_SCFSR_BRK (0x0010u) +#define SCIF5_SCFSR_TDFE (0x0020u) +#define SCIF5_SCFSR_TEND (0x0040u) +#define SCIF5_SCFSR_ER (0x0080u) +#define SCIF5_SCFSR_FERN (0x0F00u) +#define SCIF5_SCFSR_PERN (0xF000u) + +#define SCIF5_SCFRDR_D (0xFFu) + +#define SCIF5_SCFCR_LOOP (0x0001u) +#define SCIF5_SCFCR_RFRST (0x0002u) +#define SCIF5_SCFCR_TFRST (0x0004u) +#define SCIF5_SCFCR_MCE (0x0008u) +#define SCIF5_SCFCR_TTRG (0x0030u) +#define SCIF5_SCFCR_RTRG (0x00C0u) +#define SCIF5_SCFCR_RSTRG (0x0700u) + +#define SCIF5_SCFDR_R (0x001Fu) +#define SCIF5_SCFDR_T (0x1F00u) + +#define SCIF5_SCSPTR_SPB2DT (0x0001u) +#define SCIF5_SCSPTR_SPB2IO (0x0002u) +#define SCIF5_SCSPTR_SCKDT (0x0004u) +#define SCIF5_SCSPTR_SCKIO (0x0008u) +#define SCIF5_SCSPTR_CTSDT (0x0010u) +#define SCIF5_SCSPTR_CTSIO (0x0020u) +#define SCIF5_SCSPTR_RTSDT (0x0040u) +#define SCIF5_SCSPTR_RTSIO (0x0080u) + +#define SCIF5_SCLSR_ORER (0x0001u) + +#define SCIF5_SCEMR_ABCS (0x0001u) +#define SCIF5_SCEMR_BGDM (0x0080u) + +/* ---- SCIF6 ---- */ +#define SCIF6_SCSMR_CKS (0x0003u) +#define SCIF6_SCSMR_STOP (0x0008u) +#define SCIF6_SCSMR_OE (0x0010u) +#define SCIF6_SCSMR_PE (0x0020u) +#define SCIF6_SCSMR_CHR (0x0040u) +#define SCIF6_SCSMR_CA (0x0080u) + +#define SCIF6_SCBRR_D (0xFFu) + +#define SCIF6_SCSCR_CKE (0x0003u) +#define SCIF6_SCSCR_REIE (0x0008u) +#define SCIF6_SCSCR_RE (0x0010u) +#define SCIF6_SCSCR_TE (0x0020u) +#define SCIF6_SCSCR_RIE (0x0040u) +#define SCIF6_SCSCR_TIE (0x0080u) + +#define SCIF6_SCFTDR_D (0xFFu) + +#define SCIF6_SCFSR_DR (0x0001u) +#define SCIF6_SCFSR_RDF (0x0002u) +#define SCIF6_SCFSR_PER (0x0004u) +#define SCIF6_SCFSR_FER (0x0008u) +#define SCIF6_SCFSR_BRK (0x0010u) +#define SCIF6_SCFSR_TDFE (0x0020u) +#define SCIF6_SCFSR_TEND (0x0040u) +#define SCIF6_SCFSR_ER (0x0080u) +#define SCIF6_SCFSR_FERN (0x0F00u) +#define SCIF6_SCFSR_PERN (0xF000u) + +#define SCIF6_SCFRDR_D (0xFFu) + +#define SCIF6_SCFCR_LOOP (0x0001u) +#define SCIF6_SCFCR_RFRST (0x0002u) +#define SCIF6_SCFCR_TFRST (0x0004u) +#define SCIF6_SCFCR_MCE (0x0008u) +#define SCIF6_SCFCR_TTRG (0x0030u) +#define SCIF6_SCFCR_RTRG (0x00C0u) +#define SCIF6_SCFCR_RSTRG (0x0700u) + +#define SCIF6_SCFDR_R (0x001Fu) +#define SCIF6_SCFDR_T (0x1F00u) + +#define SCIF6_SCSPTR_SPB2DT (0x0001u) +#define SCIF6_SCSPTR_SPB2IO (0x0002u) +#define SCIF6_SCSPTR_SCKDT (0x0004u) +#define SCIF6_SCSPTR_SCKIO (0x0008u) +#define SCIF6_SCSPTR_CTSDT (0x0010u) +#define SCIF6_SCSPTR_CTSIO (0x0020u) +#define SCIF6_SCSPTR_RTSDT (0x0040u) +#define SCIF6_SCSPTR_RTSIO (0x0080u) + +#define SCIF6_SCLSR_ORER (0x0001u) + +#define SCIF6_SCEMR_ABCS (0x0001u) +#define SCIF6_SCEMR_BGDM (0x0080u) + +/* ---- SCIF7 ---- */ +#define SCIF7_SCSMR_CKS (0x0003u) +#define SCIF7_SCSMR_STOP (0x0008u) +#define SCIF7_SCSMR_OE (0x0010u) +#define SCIF7_SCSMR_PE (0x0020u) +#define SCIF7_SCSMR_CHR (0x0040u) +#define SCIF7_SCSMR_CA (0x0080u) + +#define SCIF7_SCBRR_D (0xFFu) + +#define SCIF7_SCSCR_CKE (0x0003u) +#define SCIF7_SCSCR_REIE (0x0008u) +#define SCIF7_SCSCR_RE (0x0010u) +#define SCIF7_SCSCR_TE (0x0020u) +#define SCIF7_SCSCR_RIE (0x0040u) +#define SCIF7_SCSCR_TIE (0x0080u) + +#define SCIF7_SCFTDR_D (0xFFu) + +#define SCIF7_SCFSR_DR (0x0001u) +#define SCIF7_SCFSR_RDF (0x0002u) +#define SCIF7_SCFSR_PER (0x0004u) +#define SCIF7_SCFSR_FER (0x0008u) +#define SCIF7_SCFSR_BRK (0x0010u) +#define SCIF7_SCFSR_TDFE (0x0020u) +#define SCIF7_SCFSR_TEND (0x0040u) +#define SCIF7_SCFSR_ER (0x0080u) +#define SCIF7_SCFSR_FERN (0x0F00u) +#define SCIF7_SCFSR_PERN (0xF000u) + +#define SCIF7_SCFRDR_D (0xFFu) + +#define SCIF7_SCFCR_LOOP (0x0001u) +#define SCIF7_SCFCR_RFRST (0x0002u) +#define SCIF7_SCFCR_TFRST (0x0004u) +#define SCIF7_SCFCR_MCE (0x0008u) +#define SCIF7_SCFCR_TTRG (0x0030u) +#define SCIF7_SCFCR_RTRG (0x00C0u) +#define SCIF7_SCFCR_RSTRG (0x0700u) + +#define SCIF7_SCFDR_R (0x001Fu) +#define SCIF7_SCFDR_T (0x1F00u) + +#define SCIF7_SCSPTR_SPB2DT (0x0001u) +#define SCIF7_SCSPTR_SPB2IO (0x0002u) +#define SCIF7_SCSPTR_SCKDT (0x0004u) +#define SCIF7_SCSPTR_SCKIO (0x0008u) +#define SCIF7_SCSPTR_CTSDT (0x0010u) +#define SCIF7_SCSPTR_CTSIO (0x0020u) +#define SCIF7_SCSPTR_RTSDT (0x0040u) +#define SCIF7_SCSPTR_RTSIO (0x0080u) + +#define SCIF7_SCLSR_ORER (0x0001u) + +#define SCIF7_SCEMR_ABCS (0x0001u) +#define SCIF7_SCEMR_BGDM (0x0080u) + +/* ---- SCIFn ---- */ +#define SCIFn_SCSMR_CKS (0x0003u) +#define SCIFn_SCSMR_STOP (0x0008u) +#define SCIFn_SCSMR_OE (0x0010u) +#define SCIFn_SCSMR_PE (0x0020u) +#define SCIFn_SCSMR_CHR (0x0040u) +#define SCIFn_SCSMR_CA (0x0080u) + +#define SCIFn_SCBRR_D (0xFFu) + +#define SCIFn_SCSCR_CKE (0x0003u) +#define SCIFn_SCSCR_REIE (0x0008u) +#define SCIFn_SCSCR_RE (0x0010u) +#define SCIFn_SCSCR_TE (0x0020u) +#define SCIFn_SCSCR_RIE (0x0040u) +#define SCIFn_SCSCR_TIE (0x0080u) + +#define SCIFn_SCFTDR_D (0xFFu) + +#define SCIFn_SCFSR_DR (0x0001u) +#define SCIFn_SCFSR_RDF (0x0002u) +#define SCIFn_SCFSR_PER (0x0004u) +#define SCIFn_SCFSR_FER (0x0008u) +#define SCIFn_SCFSR_BRK (0x0010u) +#define SCIFn_SCFSR_TDFE (0x0020u) +#define SCIFn_SCFSR_TEND (0x0040u) +#define SCIFn_SCFSR_ER (0x0080u) +#define SCIFn_SCFSR_FERN (0x0F00u) +#define SCIFn_SCFSR_PERN (0xF000u) + +#define SCIFn_SCFRDR_D (0xFFu) + +#define SCIFn_SCFCR_LOOP (0x0001u) +#define SCIFn_SCFCR_RFRST (0x0002u) +#define SCIFn_SCFCR_TFRST (0x0004u) +#define SCIFn_SCFCR_MCE (0x0008u) +#define SCIFn_SCFCR_TTRG (0x0030u) +#define SCIFn_SCFCR_RTRG (0x00C0u) +#define SCIFn_SCFCR_RSTRG (0x0700u) + +#define SCIFn_SCFDR_R (0x001Fu) +#define SCIFn_SCFDR_T (0x1F00u) + +#define SCIFn_SCSPTR_SPB2DT (0x0001u) +#define SCIFn_SCSPTR_SPB2IO (0x0002u) +#define SCIFn_SCSPTR_SCKDT (0x0004u) +#define SCIFn_SCSPTR_SCKIO (0x0008u) +#define SCIFn_SCSPTR_CTSDT (0x0010u) +#define SCIFn_SCSPTR_CTSIO (0x0020u) +#define SCIFn_SCSPTR_RTSDT (0x0040u) +#define SCIFn_SCSPTR_RTSIO (0x0080u) + +#define SCIFn_SCLSR_ORER (0x0001u) + +#define SCIFn_SCEMR_ABCS (0x0001u) +#define SCIFn_SCEMR_BGDM (0x0080u) + + +/* ==== Shift values for IO registers ==== */ +/* ---- SCIF0 ---- */ +#define SCIF0_SCSMR_CKS_SHIFT (0u) +#define SCIF0_SCSMR_STOP_SHIFT (3u) +#define SCIF0_SCSMR_OE_SHIFT (4u) +#define SCIF0_SCSMR_PE_SHIFT (5u) +#define SCIF0_SCSMR_CHR_SHIFT (6u) +#define SCIF0_SCSMR_CA_SHIFT (7u) + +#define SCIF0_SCBRR_D_SHIFT (0u) + +#define SCIF0_SCSCR_CKE_SHIFT (0u) +#define SCIF0_SCSCR_REIE_SHIFT (3u) +#define SCIF0_SCSCR_RE_SHIFT (4u) +#define SCIF0_SCSCR_TE_SHIFT (5u) +#define SCIF0_SCSCR_RIE_SHIFT (6u) +#define SCIF0_SCSCR_TIE_SHIFT (7u) + +#define SCIF0_SCFTDR_D_SHIFT (0u) + +#define SCIF0_SCFSR_DR_SHIFT (0u) +#define SCIF0_SCFSR_RDF_SHIFT (1u) +#define SCIF0_SCFSR_PER_SHIFT (2u) +#define SCIF0_SCFSR_FER_SHIFT (3u) +#define SCIF0_SCFSR_BRK_SHIFT (4u) +#define SCIF0_SCFSR_TDFE_SHIFT (5u) +#define SCIF0_SCFSR_TEND_SHIFT (6u) +#define SCIF0_SCFSR_ER_SHIFT (7u) +#define SCIF0_SCFSR_FERN_SHIFT (8u) +#define SCIF0_SCFSR_PERN_SHIFT (12u) + +#define SCIF0_SCFRDR_D_SHIFT (0u) + +#define SCIF0_SCFCR_LOOP_SHIFT (0u) +#define SCIF0_SCFCR_RFRST_SHIFT (1u) +#define SCIF0_SCFCR_TFRST_SHIFT (2u) +#define SCIF0_SCFCR_MCE_SHIFT (3u) +#define SCIF0_SCFCR_TTRG_SHIFT (4u) +#define SCIF0_SCFCR_RTRG_SHIFT (6u) +#define SCIF0_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF0_SCFDR_R_SHIFT (0u) +#define SCIF0_SCFDR_T_SHIFT (8u) + +#define SCIF0_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF0_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF0_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF0_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF0_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF0_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF0_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF0_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF0_SCLSR_ORER_SHIFT (0u) + +#define SCIF0_SCEMR_ABCS_SHIFT (0u) +#define SCIF0_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF1 ---- */ +#define SCIF1_SCSMR_CKS_SHIFT (0u) +#define SCIF1_SCSMR_STOP_SHIFT (3u) +#define SCIF1_SCSMR_OE_SHIFT (4u) +#define SCIF1_SCSMR_PE_SHIFT (5u) +#define SCIF1_SCSMR_CHR_SHIFT (6u) +#define SCIF1_SCSMR_CA_SHIFT (7u) + +#define SCIF1_SCBRR_D_SHIFT (0u) + +#define SCIF1_SCSCR_CKE_SHIFT (0u) +#define SCIF1_SCSCR_REIE_SHIFT (3u) +#define SCIF1_SCSCR_RE_SHIFT (4u) +#define SCIF1_SCSCR_TE_SHIFT (5u) +#define SCIF1_SCSCR_RIE_SHIFT (6u) +#define SCIF1_SCSCR_TIE_SHIFT (7u) + +#define SCIF1_SCFTDR_D_SHIFT (0u) + +#define SCIF1_SCFSR_DR_SHIFT (0u) +#define SCIF1_SCFSR_RDF_SHIFT (1u) +#define SCIF1_SCFSR_PER_SHIFT (2u) +#define SCIF1_SCFSR_FER_SHIFT (3u) +#define SCIF1_SCFSR_BRK_SHIFT (4u) +#define SCIF1_SCFSR_TDFE_SHIFT (5u) +#define SCIF1_SCFSR_TEND_SHIFT (6u) +#define SCIF1_SCFSR_ER_SHIFT (7u) +#define SCIF1_SCFSR_FERN_SHIFT (8u) +#define SCIF1_SCFSR_PERN_SHIFT (12u) + +#define SCIF1_SCFRDR_D_SHIFT (0u) + +#define SCIF1_SCFCR_LOOP_SHIFT (0u) +#define SCIF1_SCFCR_RFRST_SHIFT (1u) +#define SCIF1_SCFCR_TFRST_SHIFT (2u) +#define SCIF1_SCFCR_MCE_SHIFT (3u) +#define SCIF1_SCFCR_TTRG_SHIFT (4u) +#define SCIF1_SCFCR_RTRG_SHIFT (6u) +#define SCIF1_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF1_SCFDR_R_SHIFT (0u) +#define SCIF1_SCFDR_T_SHIFT (8u) + +#define SCIF1_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF1_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF1_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF1_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF1_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF1_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF1_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF1_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF1_SCLSR_ORER_SHIFT (0u) + +#define SCIF1_SCEMR_ABCS_SHIFT (0u) +#define SCIF1_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF2 ---- */ +#define SCIF2_SCSMR_CKS_SHIFT (0u) +#define SCIF2_SCSMR_STOP_SHIFT (3u) +#define SCIF2_SCSMR_OE_SHIFT (4u) +#define SCIF2_SCSMR_PE_SHIFT (5u) +#define SCIF2_SCSMR_CHR_SHIFT (6u) +#define SCIF2_SCSMR_CA_SHIFT (7u) + +#define SCIF2_SCBRR_D_SHIFT (0u) + +#define SCIF2_SCSCR_CKE_SHIFT (0u) +#define SCIF2_SCSCR_REIE_SHIFT (3u) +#define SCIF2_SCSCR_RE_SHIFT (4u) +#define SCIF2_SCSCR_TE_SHIFT (5u) +#define SCIF2_SCSCR_RIE_SHIFT (6u) +#define SCIF2_SCSCR_TIE_SHIFT (7u) + +#define SCIF2_SCFTDR_D_SHIFT (0u) + +#define SCIF2_SCFSR_DR_SHIFT (0u) +#define SCIF2_SCFSR_RDF_SHIFT (1u) +#define SCIF2_SCFSR_PER_SHIFT (2u) +#define SCIF2_SCFSR_FER_SHIFT (3u) +#define SCIF2_SCFSR_BRK_SHIFT (4u) +#define SCIF2_SCFSR_TDFE_SHIFT (5u) +#define SCIF2_SCFSR_TEND_SHIFT (6u) +#define SCIF2_SCFSR_ER_SHIFT (7u) +#define SCIF2_SCFSR_FERN_SHIFT (8u) +#define SCIF2_SCFSR_PERN_SHIFT (12u) + +#define SCIF2_SCFRDR_D_SHIFT (0u) + +#define SCIF2_SCFCR_LOOP_SHIFT (0u) +#define SCIF2_SCFCR_RFRST_SHIFT (1u) +#define SCIF2_SCFCR_TFRST_SHIFT (2u) +#define SCIF2_SCFCR_MCE_SHIFT (3u) +#define SCIF2_SCFCR_TTRG_SHIFT (4u) +#define SCIF2_SCFCR_RTRG_SHIFT (6u) +#define SCIF2_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF2_SCFDR_R_SHIFT (0u) +#define SCIF2_SCFDR_T_SHIFT (8u) + +#define SCIF2_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF2_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF2_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF2_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF2_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF2_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF2_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF2_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF2_SCLSR_ORER_SHIFT (0u) + +#define SCIF2_SCEMR_ABCS_SHIFT (0u) +#define SCIF2_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF3 ---- */ +#define SCIF3_SCSMR_CKS_SHIFT (0u) +#define SCIF3_SCSMR_STOP_SHIFT (3u) +#define SCIF3_SCSMR_OE_SHIFT (4u) +#define SCIF3_SCSMR_PE_SHIFT (5u) +#define SCIF3_SCSMR_CHR_SHIFT (6u) +#define SCIF3_SCSMR_CA_SHIFT (7u) + +#define SCIF3_SCBRR_D_SHIFT (0u) + +#define SCIF3_SCSCR_CKE_SHIFT (0u) +#define SCIF3_SCSCR_REIE_SHIFT (3u) +#define SCIF3_SCSCR_RE_SHIFT (4u) +#define SCIF3_SCSCR_TE_SHIFT (5u) +#define SCIF3_SCSCR_RIE_SHIFT (6u) +#define SCIF3_SCSCR_TIE_SHIFT (7u) + +#define SCIF3_SCFTDR_D_SHIFT (0u) + +#define SCIF3_SCFSR_DR_SHIFT (0u) +#define SCIF3_SCFSR_RDF_SHIFT (1u) +#define SCIF3_SCFSR_PER_SHIFT (2u) +#define SCIF3_SCFSR_FER_SHIFT (3u) +#define SCIF3_SCFSR_BRK_SHIFT (4u) +#define SCIF3_SCFSR_TDFE_SHIFT (5u) +#define SCIF3_SCFSR_TEND_SHIFT (6u) +#define SCIF3_SCFSR_ER_SHIFT (7u) +#define SCIF3_SCFSR_FERN_SHIFT (8u) +#define SCIF3_SCFSR_PERN_SHIFT (12u) + +#define SCIF3_SCFRDR_D_SHIFT (0u) + +#define SCIF3_SCFCR_LOOP_SHIFT (0u) +#define SCIF3_SCFCR_RFRST_SHIFT (1u) +#define SCIF3_SCFCR_TFRST_SHIFT (2u) +#define SCIF3_SCFCR_MCE_SHIFT (3u) +#define SCIF3_SCFCR_TTRG_SHIFT (4u) +#define SCIF3_SCFCR_RTRG_SHIFT (6u) +#define SCIF3_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF3_SCFDR_R_SHIFT (0u) +#define SCIF3_SCFDR_T_SHIFT (8u) + +#define SCIF3_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF3_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF3_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF3_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF3_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF3_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF3_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF3_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF3_SCLSR_ORER_SHIFT (0u) + +#define SCIF3_SCEMR_ABCS_SHIFT (0u) +#define SCIF3_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF4 ---- */ +#define SCIF4_SCSMR_CKS_SHIFT (0u) +#define SCIF4_SCSMR_STOP_SHIFT (3u) +#define SCIF4_SCSMR_OE_SHIFT (4u) +#define SCIF4_SCSMR_PE_SHIFT (5u) +#define SCIF4_SCSMR_CHR_SHIFT (6u) +#define SCIF4_SCSMR_CA_SHIFT (7u) + +#define SCIF4_SCBRR_D_SHIFT (0u) + +#define SCIF4_SCSCR_CKE_SHIFT (0u) +#define SCIF4_SCSCR_REIE_SHIFT (3u) +#define SCIF4_SCSCR_RE_SHIFT (4u) +#define SCIF4_SCSCR_TE_SHIFT (5u) +#define SCIF4_SCSCR_RIE_SHIFT (6u) +#define SCIF4_SCSCR_TIE_SHIFT (7u) + +#define SCIF4_SCFTDR_D_SHIFT (0u) + +#define SCIF4_SCFSR_DR_SHIFT (0u) +#define SCIF4_SCFSR_RDF_SHIFT (1u) +#define SCIF4_SCFSR_PER_SHIFT (2u) +#define SCIF4_SCFSR_FER_SHIFT (3u) +#define SCIF4_SCFSR_BRK_SHIFT (4u) +#define SCIF4_SCFSR_TDFE_SHIFT (5u) +#define SCIF4_SCFSR_TEND_SHIFT (6u) +#define SCIF4_SCFSR_ER_SHIFT (7u) +#define SCIF4_SCFSR_FERN_SHIFT (8u) +#define SCIF4_SCFSR_PERN_SHIFT (12u) + +#define SCIF4_SCFRDR_D_SHIFT (0u) + +#define SCIF4_SCFCR_LOOP_SHIFT (0u) +#define SCIF4_SCFCR_RFRST_SHIFT (1u) +#define SCIF4_SCFCR_TFRST_SHIFT (2u) +#define SCIF4_SCFCR_MCE_SHIFT (3u) +#define SCIF4_SCFCR_TTRG_SHIFT (4u) +#define SCIF4_SCFCR_RTRG_SHIFT (6u) +#define SCIF4_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF4_SCFDR_R_SHIFT (0u) +#define SCIF4_SCFDR_T_SHIFT (8u) + +#define SCIF4_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF4_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF4_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF4_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF4_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF4_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF4_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF4_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF4_SCLSR_ORER_SHIFT (0u) + +#define SCIF4_SCEMR_ABCS_SHIFT (0u) +#define SCIF4_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF5 ---- */ +#define SCIF5_SCSMR_CKS_SHIFT (0u) +#define SCIF5_SCSMR_STOP_SHIFT (3u) +#define SCIF5_SCSMR_OE_SHIFT (4u) +#define SCIF5_SCSMR_PE_SHIFT (5u) +#define SCIF5_SCSMR_CHR_SHIFT (6u) +#define SCIF5_SCSMR_CA_SHIFT (7u) + +#define SCIF5_SCBRR_D_SHIFT (0u) + +#define SCIF5_SCSCR_CKE_SHIFT (0u) +#define SCIF5_SCSCR_REIE_SHIFT (3u) +#define SCIF5_SCSCR_RE_SHIFT (4u) +#define SCIF5_SCSCR_TE_SHIFT (5u) +#define SCIF5_SCSCR_RIE_SHIFT (6u) +#define SCIF5_SCSCR_TIE_SHIFT (7u) + +#define SCIF5_SCFTDR_D_SHIFT (0u) + +#define SCIF5_SCFSR_DR_SHIFT (0u) +#define SCIF5_SCFSR_RDF_SHIFT (1u) +#define SCIF5_SCFSR_PER_SHIFT (2u) +#define SCIF5_SCFSR_FER_SHIFT (3u) +#define SCIF5_SCFSR_BRK_SHIFT (4u) +#define SCIF5_SCFSR_TDFE_SHIFT (5u) +#define SCIF5_SCFSR_TEND_SHIFT (6u) +#define SCIF5_SCFSR_ER_SHIFT (7u) +#define SCIF5_SCFSR_FERN_SHIFT (8u) +#define SCIF5_SCFSR_PERN_SHIFT (12u) + +#define SCIF5_SCFRDR_D_SHIFT (0u) + +#define SCIF5_SCFCR_LOOP_SHIFT (0u) +#define SCIF5_SCFCR_RFRST_SHIFT (1u) +#define SCIF5_SCFCR_TFRST_SHIFT (2u) +#define SCIF5_SCFCR_MCE_SHIFT (3u) +#define SCIF5_SCFCR_TTRG_SHIFT (4u) +#define SCIF5_SCFCR_RTRG_SHIFT (6u) +#define SCIF5_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF5_SCFDR_R_SHIFT (0u) +#define SCIF5_SCFDR_T_SHIFT (8u) + +#define SCIF5_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF5_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF5_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF5_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF5_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF5_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF5_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF5_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF5_SCLSR_ORER_SHIFT (0u) + +#define SCIF5_SCEMR_ABCS_SHIFT (0u) +#define SCIF5_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF6 ---- */ +#define SCIF6_SCSMR_CKS_SHIFT (0u) +#define SCIF6_SCSMR_STOP_SHIFT (3u) +#define SCIF6_SCSMR_OE_SHIFT (4u) +#define SCIF6_SCSMR_PE_SHIFT (5u) +#define SCIF6_SCSMR_CHR_SHIFT (6u) +#define SCIF6_SCSMR_CA_SHIFT (7u) + +#define SCIF6_SCBRR_D_SHIFT (0u) + +#define SCIF6_SCSCR_CKE_SHIFT (0u) +#define SCIF6_SCSCR_REIE_SHIFT (3u) +#define SCIF6_SCSCR_RE_SHIFT (4u) +#define SCIF6_SCSCR_TE_SHIFT (5u) +#define SCIF6_SCSCR_RIE_SHIFT (6u) +#define SCIF6_SCSCR_TIE_SHIFT (7u) + +#define SCIF6_SCFTDR_D_SHIFT (0u) + +#define SCIF6_SCFSR_DR_SHIFT (0u) +#define SCIF6_SCFSR_RDF_SHIFT (1u) +#define SCIF6_SCFSR_PER_SHIFT (2u) +#define SCIF6_SCFSR_FER_SHIFT (3u) +#define SCIF6_SCFSR_BRK_SHIFT (4u) +#define SCIF6_SCFSR_TDFE_SHIFT (5u) +#define SCIF6_SCFSR_TEND_SHIFT (6u) +#define SCIF6_SCFSR_ER_SHIFT (7u) +#define SCIF6_SCFSR_FERN_SHIFT (8u) +#define SCIF6_SCFSR_PERN_SHIFT (12u) + +#define SCIF6_SCFRDR_D_SHIFT (0u) + +#define SCIF6_SCFCR_LOOP_SHIFT (0u) +#define SCIF6_SCFCR_RFRST_SHIFT (1u) +#define SCIF6_SCFCR_TFRST_SHIFT (2u) +#define SCIF6_SCFCR_MCE_SHIFT (3u) +#define SCIF6_SCFCR_TTRG_SHIFT (4u) +#define SCIF6_SCFCR_RTRG_SHIFT (6u) +#define SCIF6_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF6_SCFDR_R_SHIFT (0u) +#define SCIF6_SCFDR_T_SHIFT (8u) + +#define SCIF6_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF6_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF6_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF6_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF6_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF6_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF6_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF6_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF6_SCLSR_ORER_SHIFT (0u) + +#define SCIF6_SCEMR_ABCS_SHIFT (0u) +#define SCIF6_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF7 ---- */ +#define SCIF7_SCSMR_CKS_SHIFT (0u) +#define SCIF7_SCSMR_STOP_SHIFT (3u) +#define SCIF7_SCSMR_OE_SHIFT (4u) +#define SCIF7_SCSMR_PE_SHIFT (5u) +#define SCIF7_SCSMR_CHR_SHIFT (6u) +#define SCIF7_SCSMR_CA_SHIFT (7u) + +#define SCIF7_SCBRR_D_SHIFT (0u) + +#define SCIF7_SCSCR_CKE_SHIFT (0u) +#define SCIF7_SCSCR_REIE_SHIFT (3u) +#define SCIF7_SCSCR_RE_SHIFT (4u) +#define SCIF7_SCSCR_TE_SHIFT (5u) +#define SCIF7_SCSCR_RIE_SHIFT (6u) +#define SCIF7_SCSCR_TIE_SHIFT (7u) + +#define SCIF7_SCFTDR_D_SHIFT (0u) + +#define SCIF7_SCFSR_DR_SHIFT (0u) +#define SCIF7_SCFSR_RDF_SHIFT (1u) +#define SCIF7_SCFSR_PER_SHIFT (2u) +#define SCIF7_SCFSR_FER_SHIFT (3u) +#define SCIF7_SCFSR_BRK_SHIFT (4u) +#define SCIF7_SCFSR_TDFE_SHIFT (5u) +#define SCIF7_SCFSR_TEND_SHIFT (6u) +#define SCIF7_SCFSR_ER_SHIFT (7u) +#define SCIF7_SCFSR_FERN_SHIFT (8u) +#define SCIF7_SCFSR_PERN_SHIFT (12u) + +#define SCIF7_SCFRDR_D_SHIFT (0u) + +#define SCIF7_SCFCR_LOOP_SHIFT (0u) +#define SCIF7_SCFCR_RFRST_SHIFT (1u) +#define SCIF7_SCFCR_TFRST_SHIFT (2u) +#define SCIF7_SCFCR_MCE_SHIFT (3u) +#define SCIF7_SCFCR_TTRG_SHIFT (4u) +#define SCIF7_SCFCR_RTRG_SHIFT (6u) +#define SCIF7_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF7_SCFDR_R_SHIFT (0u) +#define SCIF7_SCFDR_T_SHIFT (8u) + +#define SCIF7_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF7_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF7_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF7_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF7_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF7_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF7_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF7_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF7_SCLSR_ORER_SHIFT (0u) + +#define SCIF7_SCEMR_ABCS_SHIFT (0u) +#define SCIF7_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIFn ---- */ +#define SCIFn_SCSMR_CKS_SHIFT (0u) +#define SCIFn_SCSMR_STOP_SHIFT (3u) +#define SCIFn_SCSMR_OE_SHIFT (4u) +#define SCIFn_SCSMR_PE_SHIFT (5u) +#define SCIFn_SCSMR_CHR_SHIFT (6u) +#define SCIFn_SCSMR_CA_SHIFT (7u) + +#define SCIFn_SCBRR_D_SHIFT (0u) + +#define SCIFn_SCSCR_CKE_SHIFT (0u) +#define SCIFn_SCSCR_REIE_SHIFT (3u) +#define SCIFn_SCSCR_RE_SHIFT (4u) +#define SCIFn_SCSCR_TE_SHIFT (5u) +#define SCIFn_SCSCR_RIE_SHIFT (6u) +#define SCIFn_SCSCR_TIE_SHIFT (7u) + +#define SCIFn_SCFTDR_D_SHIFT (0u) + +#define SCIFn_SCFSR_DR_SHIFT (0u) +#define SCIFn_SCFSR_RDF_SHIFT (1u) +#define SCIFn_SCFSR_PER_SHIFT (2u) +#define SCIFn_SCFSR_FER_SHIFT (3u) +#define SCIFn_SCFSR_BRK_SHIFT (4u) +#define SCIFn_SCFSR_TDFE_SHIFT (5u) +#define SCIFn_SCFSR_TEND_SHIFT (6u) +#define SCIFn_SCFSR_ER_SHIFT (7u) +#define SCIFn_SCFSR_FERN_SHIFT (8u) +#define SCIFn_SCFSR_PERN_SHIFT (12u) + +#define SCIFn_SCFRDR_D_SHIFT (0u) + +#define SCIFn_SCFCR_LOOP_SHIFT (0u) +#define SCIFn_SCFCR_RFRST_SHIFT (1u) +#define SCIFn_SCFCR_TFRST_SHIFT (2u) +#define SCIFn_SCFCR_MCE_SHIFT (3u) +#define SCIFn_SCFCR_TTRG_SHIFT (4u) +#define SCIFn_SCFCR_RTRG_SHIFT (6u) +#define SCIFn_SCFCR_RSTRG_SHIFT (8u) + +#define SCIFn_SCFDR_R_SHIFT (0u) +#define SCIFn_SCFDR_T_SHIFT (8u) + +#define SCIFn_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIFn_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIFn_SCSPTR_SCKDT_SHIFT (2u) +#define SCIFn_SCSPTR_SCKIO_SHIFT (3u) +#define SCIFn_SCSPTR_CTSDT_SHIFT (4u) +#define SCIFn_SCSPTR_CTSIO_SHIFT (5u) +#define SCIFn_SCSPTR_RTSDT_SHIFT (6u) +#define SCIFn_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIFn_SCLSR_ORER_SHIFT (0u) + +#define SCIFn_SCEMR_ABCS_SHIFT (0u) +#define SCIFn_SCEMR_BGDM_SHIFT (7u) + + +#endif /* SCIF_IOBITMASK_H */ + +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,732 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb_iobitmask.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : USB register define header +*******************************************************************************/ +#ifndef USB_IOBITMASK_H +#define USB_IOBITMASK_H + +/*==============================================*/ +/* SYSCFG */ +/*==============================================*/ +#define USB_SYSCFG_USBE (0x0001u) +#define USB_SYSCFG_UPLLE (0x0002u) +#define USB_SYSCFG_UCKSEL (0x0004u) +/* #define USB_SYSCFG_RESERVED1 (0x0008u) */ +#define USB_SYSCFG_DPRPU (0x0010u) +#define USB_SYSCFG_DRPD (0x0020u) +#define USB_SYSCFG_DCFM (0x0040u) +#define USB_SYSCFG_HSE (0x0080u) +/* #define USB_SYSCFG_RESERVED2 (0xFF00u) */ + +#define USB_SYSCFG_USBE_SHIFT (0) +#define USB_SYSCFG_UPLLE_SHIFT (1) +#define USB_SYSCFG_UCKSEL_SHIFT (2) +/* #define USB_SYSCFG_RESERVED1_SHIFT (3) */ +#define USB_SYSCFG_DPRPU_SHIFT (4) +#define USB_SYSCFG_DRPD_SHIFT (5) +#define USB_SYSCFG_DCFM_SHIFT (6) +#define USB_SYSCFG_HSE_SHIFT (7) +/* #define USB_SYSCFG_RESERVED2_SHIFT (8) */ + +/*==============================================*/ +/* BUSWAIT */ +/*==============================================*/ +#define USB_BUSWAIT_BWAIT (0x003Fu) + +#define USB_BUSWAIT_BWAIT_SHIFT (0) + +/*==============================================*/ +/* SYSSTS0 */ +/*==============================================*/ +#define USB_SYSSTS0_LNST (0x0003u) +#define USB_SYSSTS0_SOFEA (0x0020u) +#define USB_SYSSTS0_HTACT (0x0040u) + +#define USB_SYSSTS0_LNST_SHIFT (0) +#define USB_SYSSTS0_SOFEA_SHIFT (5) +#define USB_SYSSTS0_HTACT_SHIFT (6) + +/*==============================================*/ +/* DVSTCTR0 */ +/*==============================================*/ +#define USB_DVSTCTR0_RHST (0x0007u) +/* #define USB_DVSTCTR0_RESERVED (0x0008u) */ +#define USB_DVSTCTR0_UACT (0x0010u) +#define USB_DVSTCTR0_RESUME (0x0020u) +#define USB_DVSTCTR0_USBRST (0x0040u) +#define USB_DVSTCTR0_RWUPE (0x0080u) +#define USB_DVSTCTR0_WKUP (0x0100u) + +#define USB_DVSTCTR0_RHST_SHIFT (0) +/* #define USB_DVSTCTR0_RESERVED_SHIFT (3) */ +#define USB_DVSTCTR0_UACT_SHIFT (4) +#define USB_DVSTCTR0_RESUME_SHIFT (5) +#define USB_DVSTCTR0_USBRST_SHIFT (6) +#define USB_DVSTCTR0_RWUPE_SHIFT (7) +#define USB_DVSTCTR0_WKUP_SHIFT (8) + +/*==============================================*/ +/* TESTMODE */ +/*==============================================*/ +#define USB_TESTMODE_UTST (0x000Fu) +/* #define USB_TESTMODE_RESERVED (0xFFF0u) */ + +#define USB_TESTMODE_UTST_SHIFT (0) +/* #define USB_TESTMODE_RESERVED_SHIFT (4) */ + +/*==============================================*/ +/* DnFBCFG */ +/*==============================================*/ +/* #define USB_DnFBCFG_RESERVED1 (0x000Fu) */ +#define USB_DnFBCFG_TENDE (0x0010u) +/* #define USB_DnFBCFG_RESERVED2 (0x0FE0u) */ +#define USB_DnFBCFG_DFACC (0x3000u) +/* #define USB_DnFBCFG_RESERVED3 (0xC000u) */ + +/* #define USB_DnFBCFG_RESERVED1_SHIFT (0) */ +#define USB_DnFBCFG_TENDE_SHIFT (4) +/* #define USB_DnFBCFG_RESERVED2_SHIFT (5) */ +#define USB_DnFBCFG_DFACC_SHIFT (12) +/* #define USB_DnFBCFG_RESERVED3_SHIFT (14) */ + +/*==============================================*/ +/* CFIFO */ +/*==============================================*/ +#define USB_CFIFO_FIFOPORT (0xFFFFFFFFuL) + +#define USB_CFIFO_FIFOPORT_SHIFT (0) + +/*==============================================*/ +/* DnFIFO */ +/*==============================================*/ +#define USB_DnFIFO_FIFOPORT (0xFFFFFFFFuL) + +#define USB_DnFIFO_FIFOPORT_SHIFT (0) + +/*==============================================*/ +/* CFIFOSEL */ +/*==============================================*/ +#define USB_CFIFOSEL_CURPIPE (0x000Fu) +/* #define USB_CFIFOSEL_RESERVED1 (0x0010u) */ +#define USB_CFIFOSEL_ISEL_ (0x0020u) +/* #define USB_CFIFOSEL_RESERVED2 (0x00C0u) */ +#define USB_CFIFOSEL_BIGEND (0x0100u) +/* #define USB_CFIFOSEL_RESERVED3 (0x0200u) */ +#define USB_CFIFOSEL_MBW (0x0C00u) +/* #define USB_CFIFOSEL_RESERVED4 (0x3000u) */ +#define USB_CFIFOSEL_REW (0x4000u) +#define USB_CFIFOSEL_RCNT (0x8000u) + +#define USB_CFIFOSEL_CURPIPE_SHIFT (0) +/* #define USB_CFIFOSEL_RESERVED1_SHIFT (4) */ +#define USB_CFIFOSEL_ISEL_SHIFT_ (5) +/* #define USB_CFIFOSEL_RESERVED2_SHIFT (6) */ +#define USB_CFIFOSEL_BIGEND_SHIFT (8) +/* #define USB_CFIFOSEL_RESERVED3_SHIFT (9) */ +#define USB_CFIFOSEL_MBW_SHIFT (10) +/* #define USB_CFIFOSEL_RESERVED4_SHIFT (12) */ +#define USB_CFIFOSEL_REW_SHIFT (14) +#define USB_CFIFOSEL_RCNT_SHIFT (15) + +/*==============================================*/ +/* DnFIFOSEL */ +/*==============================================*/ +#define USB_DnFIFOSEL_CURPIPE (0x000Fu) +/* #define USB_DnFIFOSEL_RESERVED1 (0x00F0u) */ +#define USB_DnFIFOSEL_BIGEND (0x0100u) +/* #define USB_DnFIFOSEL_RESERVED2 (0x0200u) */ +#define USB_DnFIFOSEL_MBW (0x0C00u) +#define USB_DnFIFOSEL_DREQE (0x1000u) +#define USB_DnFIFOSEL_DCLRM (0x2000u) +#define USB_DnFIFOSEL_REW (0x4000u) +#define USB_DnFIFOSEL_RCNT (0x8000u) + +#define USB_DnFIFOSEL_CURPIPE_SHIFT (0) +/* #define USB_DnFIFOSEL_RESERVED1_SHIFT (4) */ +#define USB_DnFIFOSEL_BIGEND_SHIFT (8) +/* #define USB_DnFIFOSEL_RESERVED2_SHIFT (9) */ +#define USB_DnFIFOSEL_MBW_SHIFT (10) +#define USB_DnFIFOSEL_DREQE_SHIFT (12) +#define USB_DnFIFOSEL_DCLRM_SHIFT (13) +#define USB_DnFIFOSEL_REW_SHIFT (14) +#define USB_DnFIFOSEL_RCNT_SHIFT (15) + +/*==============================================*/ +/* CFIFOCTR */ +/*==============================================*/ +#define USB_CFIFOCTR_DTLN (0x0FFFu) +/* #define USB_CFIFOCTR_RESERVED (0x1000u) */ +#define USB_CFIFOCTR_FRDY (0x2000u) +#define USB_CFIFOCTR_BCLR (0x4000u) +#define USB_CFIFOCTR_BVAL (0x8000u) + +#define USB_CFIFOCTR_DTLN_SHIFT (0) +/* #define USB_CFIFOCTR_RESERVED_SHIFT (12) */ +#define USB_CFIFOCTR_FRDY_SHIFT (13) +#define USB_CFIFOCTR_BCLR_SHIFT (14) +#define USB_CFIFOCTR_BVAL_SHIFT (15) + +/*==============================================*/ +/* DnFIFOCTR */ +/*==============================================*/ +#define USB_DnFIFOCTR_DTLN (0x0FFFu) +/* #define USB_DnFIFOCTR_RESERVED (0x1000u) */ +#define USB_DnFIFOCTR_FRDY (0x2000u) +#define USB_DnFIFOCTR_BCLR (0x4000u) +#define USB_DnFIFOCTR_BVAL (0x8000u) + +#define USB_DnFIFOCTR_DTLN_SHIFT (0) +/* #define USB_DnFIFOCTR_RESERVED_SHIFT (12) */ +#define USB_DnFIFOCTR_FRDY_SHIFT (13) +#define USB_DnFIFOCTR_BCLR_SHIFT (14) +#define USB_DnFIFOCTR_BVAL_SHIFT (15) + +/*==============================================*/ +/* INTENB0 */ +/*==============================================*/ +/* #define USB_INTENB0_RESERVED (0x00FFu) */ +#define USB_INTENB0_BRDYE (0x0100u) +#define USB_INTENB0_NRDYE (0x0200u) +#define USB_INTENB0_BEMPE (0x0400u) +#define USB_INTENB0_CTRE (0x0800u) +#define USB_INTENB0_DVSE (0x1000u) +#define USB_INTENB0_SOFE (0x2000u) +#define USB_INTENB0_RSME (0x4000u) +#define USB_INTENB0_VBSE (0x8000u) + +/* #define USB_INTENB0_RESERVED_SHIFT (0) */ +#define USB_INTENB0_BRDYE_SHIFT (8) +#define USB_INTENB0_NRDYE_SHIFT (9) +#define USB_INTENB0_BEMPE_SHIFT (10) +#define USB_INTENB0_CTRE_SHIFT (11) +#define USB_INTENB0_DVSE_SHIFT (12) +#define USB_INTENB0_SOFE_SHIFT (13) +#define USB_INTENB0_RSME_SHIFT (14) +#define USB_INTENB0_VBSE_SHIFT (15) + +/*==============================================*/ +/* INTENB1 */ +/*==============================================*/ +/* #define USB_INTENB1_RESERVED1 (0x000Fu) */ +#define USB_INTENB1_SACKE (0x0010u) +#define USB_INTENB1_SIGNE (0x0020u) +#define USB_INTENB1_EOFERRE (0x0040u) +/* #define USB_INTENB1_RESERVED2 (0x0780u) */ +#define USB_INTENB1_ATTCHE (0x0800u) +#define USB_INTENB1_DTCHE (0x1000u) +/* #define USB_INTENB1_RESERVED3 (0x2000u) */ +#define USB_INTENB1_BCHGE (0x4000u) +/* #define USB_INTENB1_RESERVED4 (0x8000u) */ + +/* #define USB_INTENB1_RESERVED1_SHIFT (0) */ +#define USB_INTENB1_SACKE_SHIFT (4) +#define USB_INTENB1_SIGNE_SHIFT (5) +#define USB_INTENB1_EOFERRE_SHIFT (6) +/* #define USB_INTENB1_RESERVED2_SHIFT (7) */ +#define USB_INTENB1_ATTCHE_SHIFT (11) +#define USB_INTENB1_DTCHE_SHIFT (12) +/* #define USB_INTENB1_RESERVED3_SHIFT (13) */ +#define USB_INTENB1_BCHGE_SHIFT (14) +/* #define USB_INTENB1_RESERVED4_SHIFT (15) */ + +/*==============================================*/ +/* BRDYENB */ +/*==============================================*/ +#define USB_BRDYENB (0xFFFFu) + +#define USB_BRDYENB_SHIFT (0) + +/*==============================================*/ +/* NRDYENB */ +/*==============================================*/ +#define USB_NRDYENB (0xFFFFu) + +#define USB_NRDYENB_SHIFT (0) + +/*==============================================*/ +/* BEMPENB */ +/*==============================================*/ +#define USB_BEMPENB (0xFFFFu) + +#define USB_BEMPENB_SHIFT (0) + +/*==============================================*/ +/* SOFCFG */ +/*==============================================*/ +/* #define USB_SOFCFG_RESERVED1 (0x003Fu) */ +#define USB_SOFCFG_BRDYM (0x0040u) +/* #define USB_SOFCFG_RESERVED2 (0x0080u) */ +#define USB_SOFCFG_TRNENSEL (0x0100u) +/* #define USB_SOFCFG_RESERVED3 (0xFE00u) */ + +/* #define USB_SOFCFG_RESERVED1_SHIFT (0) */ +#define USB_SOFCFG_BRDYM_SHIFT (6) +/* #define USB_SOFCFG_RESERVED2_SHIFT (7) */ +#define USB_SOFCFG_TRNENSEL_SHIFT (8) +/* #define USB_SOFCFG_RESERVED3_SHIFT (9) */ + +/*==============================================*/ +/* INTSTS0 */ +/*==============================================*/ +#define USB_INTSTS0_CTSQ (0x0007u) +#define USB_INTSTS0_VALID (0x0008u) +#define USB_INTSTS0_DVSQ (0x0070u) +#define USB_INTSTS0_VBSTS (0x0080u) +#define USB_INTSTS0_BRDY (0x0100u) +#define USB_INTSTS0_NRDY (0x0200u) +#define USB_INTSTS0_BEMP (0x0400u) +#define USB_INTSTS0_CTRT (0x0800u) +#define USB_INTSTS0_DVST (0x1000u) +#define USB_INTSTS0_SOFR (0x2000u) +#define USB_INTSTS0_RESM (0x4000u) +#define USB_INTSTS0_VBINT (0x8000u) + +#define USB_INTSTS0_CTSQ_SHIFT (0) +#define USB_INTSTS0_VALID_SHIFT (3) +#define USB_INTSTS0_DVSQ_SHIFT (4) +#define USB_INTSTS0_VBSTS_SHIFT (7) +#define USB_INTSTS0_BRDY_SHIFT (8) +#define USB_INTSTS0_NRDY_SHIFT (9) +#define USB_INTSTS0_BEMP_SHIFT (10) +#define USB_INTSTS0_CTRT_SHIFT (11) +#define USB_INTSTS0_DVST_SHIFT (12) +#define USB_INTSTS0_SOFR_SHIFT (13) +#define USB_INTSTS0_RESM_SHIFT (14) +#define USB_INTSTS0_VBINT_SHIFT (15) + +/*==============================================*/ +/* INTSTS1 */ +/*==============================================*/ +/* #define USB_INTSTS1_RESERVED1 (0x000Fu) */ +#define USB_INTSTS1_SACK (0x0010u) +#define USB_INTSTS1_SIGN (0x0020u) +#define USB_INTSTS1_EOFERR (0x0040u) +/* #define USB_INTSTS1_RESERVED2 (0x0780u) */ +#define USB_INTSTS1_ATTCH (0x0800u) +#define USB_INTSTS1_DTCH (0x1000u) +/* #define USB_INTSTS1_RESERVED3 (0x2000u) */ +#define USB_INTSTS1_BCHG (0x4000u) +/* #define USB_INTSTS1_RESERVED4 (0x8000u) */ + +/* #define USB_INTSTS1_RESERVED1_SHIFT (0) */ +#define USB_INTSTS1_SACK_SHIFT (4) +#define USB_INTSTS1_SIGN_SHIFT (5) +#define USB_INTSTS1_EOFERR_SHIFT (6) +/* #define USB_INTSTS1_RESERVED2_SHIFT (7) */ +#define USB_INTSTS1_ATTCH_SHIFT (11) +#define USB_INTSTS1_DTCH_SHIFT (12) +/* #define USB_INTSTS1_RESERVED3_SHIFT (13) */ +#define USB_INTSTS1_BCHG_SHIFT (14) +/* #define USB_INTSTS1_RESERVED4_SHIFT (15) */ + +/*==============================================*/ +/* BRDYSTS */ +/*==============================================*/ +#define USB_BRDYSTS (0xFFFFu) + +#define USB_BRDYSTS_SHIFT (0) + +/*==============================================*/ +/* NRDYSTS */ +/*==============================================*/ +#define USB_NRDYSTS (0xFFFFu) + +#define USB_NRDYSTS_SHIFT (0) + +/*==============================================*/ +/* BEMPSTS */ +/*==============================================*/ +#define USB_BEMPSTS (0xFFFFu) + +#define USB_BEMPSTS_SHIFT (0) + +/*==============================================*/ +/* FRMNUM */ +/*==============================================*/ +#define USB_FRMNUM_FRNM (0x07FFu) +/* #define USB_FRMNUM_RESERVED (0x3800u) */ +#define USB_FRMNUM_CRCE (0x4000u) +#define USB_FRMNUM_OVRN (0x8000u) + +#define USB_FRMNUM_FRNM_SHIFT (0) +/* #define USB_FRMNUM_RESERVED_SHIFT (11) */ +#define USB_FRMNUM_CRCE_SHIFT (14) +#define USB_FRMNUM_OVRN_SHIFT (15) + +/*==============================================*/ +/* UFRMNUM */ +/*==============================================*/ +#define USB_UFRMNUM_UFRNM (0x0007u) +/* #define USB_UFRMNUM_RESERVED (0xFFF8u) */ + +#define USB_UFRMNUM_UFRNM_SHIFT (0) +/* #define USB_UFRMNUM_RESERVED_SHIFT (3) */ + +/*==============================================*/ +/* USBADDR */ +/*==============================================*/ +#define USB_USBADDR_USBADDR (0x007Fu) +/* #define USB_USBADDR_RESERVED (0xFF80u) */ + +#define USB_USBADDR_USBADDR_SHIFT (0) +/* #define USB_USBADDR_RESERVED_SHIFT (7) */ + +/*==============================================*/ +/* USBREQ */ +/*==============================================*/ +#define USB_USBREQ_BMREQUESTTYPE (0x00FFu) +#define USB_USBREQ_BREQUEST (0xFF00u) + +#define USB_USBREQ_BMREQUESTTYPE_SHIFT (0) +#define USB_USBREQ_BREQUEST_SHIFT (8) + +/*==============================================*/ +/* USBVAL */ +/*==============================================*/ +#define USB_USBVAL (0xFFFFu) + +#define USB_USBVAL_SHIFT (0) + +/*==============================================*/ +/* USBINDX */ +/*==============================================*/ +#define USB_USBINDX (0xFFFFu) + +#define USB_USBINDX_SHIFT (0) + +/*==============================================*/ +/* USBLENG */ +/*==============================================*/ +#define USB_USBLENG (0xFFFFu) + +#define USB_USBLENG_SHIFT (0) + +/*==============================================*/ +/* DCPCFG */ +/*==============================================*/ +/* #define USB_DCPCFG_RESERVED1 (0x000Fu) */ +#define USB_DCPCFG_DIR (0x0010u) +/* #define USB_DCPCFG_RESERVED2 (0x0060u) */ +#define USB_DCPCFG_SHTNAK (0x0080u) +#define USB_DCPCFG_CNTMD (0x0100u) +/* #define USB_DCPCFG_RESERVED3 (0xFE00u) */ + +/* #define USB_DCPCFG_RESERVED1_SHIFT (0) */ +#define USB_DCPCFG_DIR_SHIFT (4) +/* #define USB_DCPCFG_RESERVED2_SHIFT (5) */ +#define USB_DCPCFG_SHTNK_SHIFT (7) +#define USB_DCPCFG_CNTMD_SHIFT (8) +/* #define USB_DCPCFG_RESERVED3 (9) */ + +/*==============================================*/ +/* DCPMAXP */ +/*==============================================*/ +#define USB_DCPMAXP_MXPS (0x007Fu) +/* #define USB_DCPMAXP_RESERVED (0x0F80u) */ +#define USB_DCPMAXP_DEVSEL (0xF000u) + +#define USB_DCPMAXP_MXPS_SHIFT (0) +/* #define USB_DCPMAXP_RESERVED_SHIFT (7) */ +#define USB_DCPMAXP_DEVSEL_SHIFT (12) + +/*==============================================*/ +/* DCPCTR */ +/*==============================================*/ +#define USB_DCPCTR_PID (0x0003u) +#define USB_DCPCTR_CCPL (0x0004u) +/* #define USB_DCPCTR_RESERVED1 (0x0008u) */ +#define USB_DCPCTR_PINGE (0x0010u) +#define USB_DCPCTR_PBUSY (0x0020u) +#define USB_DCPCTR_SQMON (0x0040u) +#define USB_DCPCTR_SQSET (0x0080u) +#define USB_DCPCTR_SQCLR (0x0100u) +/* #define USB_DCPCTR_RESERVED2 (0x0600u) */ +#define USB_DCPCTR_SUREQCLR (0x0800u) +#define USB_DCPCTR_CSSTS (0x1000u) +#define USB_DCPCTR_CSCLR (0x2000u) +#define USB_DCPCTR_SUREQ (0x4000u) +#define USB_DCPCTR_BSTS (0x8000u) + +#define USB_DCPCTR_PID_SHIFT (0) +#define USB_DCPCTR_CCPL_SHIFT (2) +/* #define USB_DCPCTR_RESERVED1_SHIFT (3) */ +#define USB_DCPCTR_PINGE_SHIFT (4) +#define USB_DCPCTR_PBUSY_SHIFT (5) +#define USB_DCPCTR_SQMON_SHIFT (6) +#define USB_DCPCTR_SQSET_SHIFT (7) +#define USB_DCPCTR_SQCLR_SHIFT (8) +/* #define USB_DCPCTR_RESERVED2_SHIFT (9) */ +#define USB_DCPCTR_SUREQCLR_SHIFT (11) +#define USB_DCPCTR_CSSTS_SHIFT (12) +#define USB_DCPCTR_CSCLR_SHIFT (13) +#define USB_DCPCTR_SUREQ_SHIFT (14) +#define USB_DCPCTR_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPESEL */ +/*==============================================*/ +#define USB_PIPESEL_PIPESEL (0x000Fu) +/* #define USB_PIPESEL_RESERVED (0xFFF0u) */ + +#define USB_PIPESEL_PIPESEL_SHIFT (0) +/* #define USB_PIPESEL_RESERVED_SHIFT (4) */ + +/*==============================================*/ +/* PIPECFG */ +/*==============================================*/ +#define USB_PIPECFG_EPNUM (0x000Fu) +#define USB_PIPECFG_DIR (0x0010u) +/* #define USB_PIPECFG_RESERVED1 (0x0060u) */ +#define USB_PIPECFG_SHTNAK (0x0080u) +#define USB_PIPECFG_CNTMD (0x0100u) +#define USB_PIPECFG_DBLB (0x0200u) +#define USB_PIPECFG_BFRE (0x0400u) +/* #define USB_PIPECFG_RESERVED2 (0x3800u) */ +#define USB_PIPECFG_TYPE (0xC000u) + +#define USB_PIPECFG_EPNUM_SHIFT (0) +#define USB_PIPECFG_DIR_SHIFT (4) +/* #define USB_PIPECFG_RESERVED1_SHIFT (5) */ +#define USB_PIPECFG_SHTNAK_SHIFT (7) +#define USB_PIPECFG_CNTMD_SHIFT (8) +#define USB_PIPECFG_DBLB_SHIFT (9) +#define USB_PIPECFG_BFRE_SHIFT (10) +/* #define USB_PIPECFG_RESERVED2_SHIFT (11) */ +#define USB_PIPECFG_TYPE_SHIFT (14) + +/*==============================================*/ +/* PIPEBUF */ +/*==============================================*/ +#define USB_PIPEBUF_BUFNMB (0x00FFu) +/* #define USB_PIPEBUF_RESERVED1 (0x0300u) */ +#define USB_PIPEBUF_BUFSIZE (0x7C00u) +/* #define USB_PIPEBUF_RESERVED2 (0x8000u) */ + +#define USB_PIPEBUF_BUFNMB_SHIFT (0) +/* #define USB_PIPEBUF_RESERVED1_SHIFT (8) */ +#define USB_PIPEBUF_BUFSIZE_SHIFT (10) +/* #define USB_PIPEBUF_RESERVED2_SHIFT (15) */ + +/*==============================================*/ +/* PIPEMAXP */ +/*==============================================*/ +#define USB_PIPEMAXP_MXPS (0x07FFu) +/* #define USB_PIPEMAXP_RESERVED (0x0800u) */ +#define USB_PIPEMAXP_DEVSEL (0xF000u) + +#define USB_PIPEMAXP_MXPS_SHIFT (0) +/* #define USB_PIPEMAXP_RESERVED_SHIFT (11) */ +#define USB_PIPEMAXP_DEVSEL_SHIFT (12) + +/*==============================================*/ +/* PIPEPERI */ +/*==============================================*/ +#define USB_PIPEPERI_IITV (0x0007u) +/* #define USB_PIPEPERI_RESERVED1 (0x0FF8u) */ +#define USB_PIPEPERI_IFIS (0x1000u) +/* #define USB_PIPEPERI_RESERVED2 (0xE000u) */ + +#define USB_PIPEPERI_IITV_SHIFT (0) +/* #define USB_PIPEPERI_RESERVED1_SHIFT (3) */ +#define USB_PIPEPERI_IFIS_SHIFT (12) +/* #define USB_PIPEPERI_RESERVED2_SHIFT (13) */ + +/*==============================================*/ +/* PIPEnCTR_1_5 */ +/*==============================================*/ +#define USB_PIPEnCTR_1_5_PID (0x0003u) +/* #define USB_PIPEnCTR_1_5_RESERVED1 (0x001Cu) */ +#define USB_PIPEnCTR_1_5_PBUSY (0x0020u) +#define USB_PIPEnCTR_1_5_SQMON (0x0040u) +#define USB_PIPEnCTR_1_5_SQSET (0x0080u) +#define USB_PIPEnCTR_1_5_SQCLR (0x0100u) +#define USB_PIPEnCTR_1_5_ACLRM (0x0200u) +#define USB_PIPEnCTR_1_5_ATREPM (0x0400u) +/* #define USB_PIPEnCTR_1_5_RESERVED2 (0x0800u) */ +#define USB_PIPEnCTR_1_5_CSSTS (0x1000u) +#define USB_PIPEnCTR_1_5_CSCLR (0x2000u) +#define USB_PIPEnCTR_1_5_INBUFM (0x4000u) +#define USB_PIPEnCTR_1_5_BSTS (0x8000u) + +#define USB_PIPEnCTR_1_5_PID_SHIFT (0) +/* #define USB_PIPEnCTR_1_5_RESERVED1_SHIFT (2) */ +#define USB_PIPEnCTR_1_5_PBUSY_SHIFT (5) +#define USB_PIPEnCTR_1_5_SQMON_SHIFT (6) +#define USB_PIPEnCTR_1_5_SQSET_SHIFT (7) +#define USB_PIPEnCTR_1_5_SQCLR_SHIFT (8) +#define USB_PIPEnCTR_1_5_ACLRM_SHIFT (9) +#define USB_PIPEnCTR_1_5_ATREPM_SHIFT (10) +/* #define USB_PIPEnCTR_1_5_RESERVED2_SHIFT (11) */ +#define USB_PIPEnCTR_1_5_CSSTS_SHIFT (12) +#define USB_PIPEnCTR_1_5_CSCLR_SHIFT (13) +#define USB_PIPEnCTR_1_5_INBUFM_SHIFT (14) +#define USB_PIPEnCTR_1_5_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPEnCTR_6_8 */ +/*==============================================*/ +#define USB_PIPEnCTR_6_8_PID (0x0003u) +/* #define USB_PIPEnCTR_6_8_RESERVED1 (0x001Cu) */ +#define USB_PIPEnCTR_6_8_PBUSY (0x0020u) +#define USB_PIPEnCTR_6_8_SQMON (0x0040u) +#define USB_PIPEnCTR_6_8_SQSET (0x0080u) +#define USB_PIPEnCTR_6_8_SQCLR (0x0100u) +#define USB_PIPEnCTR_6_8_ACLRM (0x0200u) +/* #define USB_PIPEnCTR_6_8_RESERVED2 (0x0C00u) */ +#define USB_PIPEnCTR_6_8_CSSTS (0x1000u) +#define USB_PIPEnCTR_6_8_CSCLR (0x2000u) +/* #define USB_PIPEnCTR_6_8_RESERVED3 (0x4000u) */ +#define USB_PIPEnCTR_6_8_BSTS (0x8000u) + +#define USB_PIPEnCTR_6_8_PID_SHIFT (0) +/* #define USB_PIPEnCTR_6_8_RESERVED1_SHIFT (2) */ +#define USB_PIPEnCTR_6_8_PBUSY_SHIFT (5) +#define USB_PIPEnCTR_6_8_SQMON_SHIFT (6) +#define USB_PIPEnCTR_6_8_SQSET_SHIFT (7) +#define USB_PIPEnCTR_6_8_SQCLR_SHIFT (8) +#define USB_PIPEnCTR_6_8_ACLRM_SHIFT (9) +/* #define USB_PIPEnCTR_6_8_RESERVED2_SHIFT (10) */ +#define USB_PIPEnCTR_6_8_CSSTS_SHIFT (12) +#define USB_PIPEnCTR_6_8_CSCLR_SHIFT (13) +/* #define USB_PIPEnCTR_6_8_RESERVED3_SHIFT (14) */ +#define USB_PIPEnCTR_6_8_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPEnCTR_9 */ +/*==============================================*/ +#define USB_PIPEnCTR_9_PID (0x0003u) +/* #define USB_PIPEnCTR_9_RESERVED1 (0x001Cu) */ +#define USB_PIPEnCTR_9_PBUSY (0x0020u) +#define USB_PIPEnCTR_9_SQMON (0x0040u) +#define USB_PIPEnCTR_9_SQSET (0x0080u) +#define USB_PIPEnCTR_9_SQCLR (0x0100u) +#define USB_PIPEnCTR_9_ACLRM (0x0200u) +#define USB_PIPEnCTR_9_ATREPM (0x0400u) +/* #define USB_PIPEnCTR_9_RESERVED2 (0x0800u) */ +#define USB_PIPEnCTR_9_CSSTS (0x1000u) +#define USB_PIPEnCTR_9_CSCLR (0x2000u) +#define USB_PIPEnCTR_9_INBUFM (0x4000u) +#define USB_PIPEnCTR_9_BSTS (0x8000u) + +#define USB_PIPEnCTR_9_PID_SHIFT (0) +/* #define USB_PIPEnCTR_9_RESERVED1_SHIFT (2) */ +#define USB_PIPEnCTR_9_PBUSY_SHIFT (5) +#define USB_PIPEnCTR_9_SQMON_SHIFT (6) +#define USB_PIPEnCTR_9_SQSET_SHIFT (7) +#define USB_PIPEnCTR_9_SQCLR_SHIFT (8) +#define USB_PIPEnCTR_9_ACLRM_SHIFT (9) +#define USB_PIPEnCTR_9_ATREPM_SHIFT (10) +/* #define USB_PIPEnCTR_9_RESERVED2_SHIFT (11) */ +#define USB_PIPEnCTR_9_CSSTS_SHIFT (12) +#define USB_PIPEnCTR_9_CSCLR_SHIFT (13) +#define USB_PIPEnCTR_9_INBUFM_SHIFT (14) +#define USB_PIPEnCTR_9_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPEnCTR_A_F */ +/*==============================================*/ +#define USB_PIPEnCTR_A_F_PID (0x0003u) +/* #define USB_PIPEnCTR_A_F_RESERVED1 (0x001Cu) */ +#define USB_PIPEnCTR_A_F_PBUSY (0x0020u) +#define USB_PIPEnCTR_A_F_SQMON (0x0040u) +#define USB_PIPEnCTR_A_F_SQSET (0x0080u) +#define USB_PIPEnCTR_A_F_SQCLR (0x0100u) +#define USB_PIPEnCTR_A_F_ACLRM (0x0200u) +#define USB_PIPEnCTR_A_F_ATREPM (0x0400u) +/* #define USB_PIPEnCTR_A_F_RESERVED2 (0x3800u) */ +#define USB_PIPEnCTR_A_F_INBUFM (0x4000u) +#define USB_PIPEnCTR_A_F_BSTS (0x8000u) + +#define USB_PIPEnCTR_A_F_PID_SHIFT (0) +/* #define USB_PIPEnCTR_A_F_RESERVED1_SHIFT (2) */ +#define USB_PIPEnCTR_A_F_PBUSY_SHIFT (5) +#define USB_PIPEnCTR_A_F_SQMON_SHIFT (6) +#define USB_PIPEnCTR_A_F_SQSET_SHIFT (7) +#define USB_PIPEnCTR_A_F_SQCLR_SHIFT (8) +#define USB_PIPEnCTR_A_F_ACLRM_SHIFT (9) +#define USB_PIPEnCTR_A_F_ATREPM_SHIFT (10) +/* #define USB_PIPEnCTR_A_F_RESERVED2_SHIFT (11) */ +#define USB_PIPEnCTR_A_F_INBUFM_SHIFT (14) +#define USB_PIPEnCTR_A_F_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPEnTRE */ +/*==============================================*/ +/* #define USB_PIPEnTRE_RESERVED1 (0x00FFu) */ +#define USB_PIPEnTRE_TRCLR (0x0100u) +#define USB_PIPEnTRE_TRENB (0x0200u) +/* #define USB_PIPEnTRE_RESERVED2 (0xFC00u) */ + +/* #define USB_PIPEnTRE_RESERVED1_SHIFT (0) */ +#define USB_PIPEnTRE_TRCLR_SHIFT (8) +#define USB_PIPEnTRE_TRENB_SHIFT (9) +/* #define USB_PIPEnTRE_RESERVED2_SHIFT (10) */ + +/*==============================================*/ +/* PIPEnTRN */ +/*==============================================*/ +#define USB_PIPEnTRN (0xFFFFu) + +#define USB_PIPEnTRN_SHIFT (0) + +/*==============================================*/ +/* DEVADDn */ +/*==============================================*/ +/* #define USB_DEVADDn_RESERVED1 (0x003Fu) */ +#define USB_DEVADDn_USBSPD (0x00C0u) +#define USB_DEVADDn_HUBPORT (0x0700u) +#define USB_DEVADDn_UPPHUB (0x7800u) +/* #define USB_DEVADDn_RESERVED2 (0x8000u) */ + +/* #define USB_DEVADDn_RESERVED1_SHIFT (0) */ +#define USB_DEVADDn_USBSPD_SHIFT (6) +#define USB_DEVADDn_HUBPORT_SHIFT (8) +#define USB_DEVADDn_UPPHUB_SHIFT (11) +/* #define USB_DEVADDn_RESERVED2_SHIFT (15) */ + +/*==============================================*/ +/* SUSPMODE */ +/*==============================================*/ +/* #define USB_SUSPMODE_RESERVED1 (0x3FFFu) */ +#define USB_SUSPMODE_SUSPM (0x4000u) +/* #define USB_SUSPMODE_RESERVED2 (0x8000u) */ + +/* #define USB_SUSPMODE_RESERVED1_SHIFT (0) */ +#define USB_SUSPMODE_SUSPM_SHIFT (14) +/* #define USB_SUSPMODE_RESERVED2_SHIFT (15) */ + +/*==============================================*/ +/* DnFIFOBm */ +/*==============================================*/ +#define USB_DnFIFOBm (0xFFFFu) + +#define USB_DnFIFOBm_SHIFT (0) + +#endif /* USB_IOBITMASK_H */ + +/* End of File */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef R7S72100_IODEFINE_H
+#define R7S72100_IODEFINE_H
+#define IODEFINE_H_VERSION 100
+
+enum iodefine_byte_select_t
+{
+ L = 0, H = 1,
+ LL= 0, LH = 1, HL = 2, HH = 3
+};
+
+/***********************************************************************
+ <<< [iodefine_reg32_t] >>>
+- Padding : sizeof(iodefine_reg32_t) == 4
+- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
+- &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
+- Endian : Independent (Same as CPU endian as register endian)
+- Bit-Order : Independent
+************************************************************************/
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+union iodefine_reg32_t
+{
+ volatile uint32_t UINT32; /* 32-bit Access */
+ volatile uint16_t UINT16[2]; /* 16-bit Access */
+ volatile uint8_t UINT8[4]; /* 8-bit Access */
+};
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+
+/***********************************************************************
+ <<< [iodefine_reg32_16_t] >>>
+- Padding : sizeof(iodefine_reg32_16_t) == 4
+- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
+- Endian : Independent (Same as CPU endian as register endian)
+- Bit-Order : Independent
+************************************************************************/
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+union iodefine_reg32_16_t
+{
+ volatile uint32_t UINT32; /* 32-bit Access */
+ volatile uint16_t UINT16[2]; /* 16-bit Access */
+};
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+
+/***********************************************************************
+ <<< [iodefine_reg16_8_t] >>>
+- Padding : sizeof(iodefine_reg16_8_t) == 2
+- Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
+- Endian : Independent (Same as CPU endian as register endian)
+- Bit-Order : Independent
+************************************************************************/
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+union iodefine_reg16_8_t
+{
+ volatile uint16_t UINT16; /* 16-bit Access */
+ volatile uint8_t UINT8[2]; /* 8-bit Access */
+};
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+
+
+
+
+
+
+#include "adc_iodefine.h" /* (V1.00a) */
+#include "bsc_iodefine.h" /* (V1.00a) */
+#include "ceu_iodefine.h" /* (V1.00a) */
+#include "cpg_iodefine.h" /* (V1.00a) */
+#include "disc_iodefine.h" /* (V1.00a) */
+#include "dmac_iodefine.h" /* (V1.00a) */
+#include "dvdec_iodefine.h" /* (V1.00a) */
+#include "ether_iodefine.h" /* (V1.00a) */
+#include "flctl_iodefine.h" /* (V1.00a) */
+#include "gpio_iodefine.h" /* (V1.00a) */
+#include "ieb_iodefine.h" /* (V1.00a) */
+#include "inb_iodefine.h" /* (V1.00a) */
+#include "intc_iodefine.h" /* (V1.00a) */
+#include "irda_iodefine.h" /* (V1.00a) */
+#include "jcu_iodefine.h" /* (V1.00a) */
+#include "l2c_iodefine.h" /* (V1.00a) */
+#include "lin_iodefine.h" /* (V1.00a) */
+#include "lvds_iodefine.h" /* (V1.00a) */
+#include "mlb_iodefine.h" /* (V1.00a) */
+#include "mmc_iodefine.h" /* (V1.00a) */
+#include "mtu2_iodefine.h" /* (V1.00a) */
+#include "ostm_iodefine.h" /* (V1.00a) */
+#include "pfv_iodefine.h" /* (V1.00a) */
+#include "pwm_iodefine.h" /* (V1.00a) */
+#include "riic_iodefine.h" /* (V1.00a) */
+#include "romdec_iodefine.h" /* (V1.00a) */
+#include "rscan0_iodefine.h" /* (V1.00a) */
+#include "rspi_iodefine.h" /* (V1.00a) */
+#include "rtc_iodefine.h" /* (V1.00a) */
+#include "scif_iodefine.h" /* (V1.00a) */
+#include "scim_iodefine.h" /* (V1.00a) */
+#include "scux_iodefine.h" /* (V1.00a) */
+#include "sdg_iodefine.h" /* (V1.00a) */
+#include "spdif_iodefine.h" /* (V1.00a) */
+#include "spibsc_iodefine.h" /* (V1.00a) */
+#include "ssif_iodefine.h" /* (V1.00a) */
+#include "usb20_iodefine.h" /* (V1.00a) */
+#include "vdc5_iodefine.h" /* (V1.00a) */
+#include "wdt_iodefine.h" /* (V1.00a) */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,99 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : adc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef ADC_IODEFINE_H
+#define ADC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_adc
+{ /* ADC */
+ volatile uint16_t ADDRA; /* ADDRA */
+ volatile uint16_t ADDRB; /* ADDRB */
+ volatile uint16_t ADDRC; /* ADDRC */
+ volatile uint16_t ADDRD; /* ADDRD */
+ volatile uint16_t ADDRE; /* ADDRE */
+ volatile uint16_t ADDRF; /* ADDRF */
+ volatile uint16_t ADDRG; /* ADDRG */
+ volatile uint16_t ADDRH; /* ADDRH */
+ volatile uint8_t dummy32[16]; /* */
+ volatile uint16_t ADCMPHA; /* ADCMPHA */
+ volatile uint16_t ADCMPLA; /* ADCMPLA */
+ volatile uint16_t ADCMPHB; /* ADCMPHB */
+ volatile uint16_t ADCMPLB; /* ADCMPLB */
+ volatile uint16_t ADCMPHC; /* ADCMPHC */
+ volatile uint16_t ADCMPLC; /* ADCMPLC */
+ volatile uint16_t ADCMPHD; /* ADCMPHD */
+ volatile uint16_t ADCMPLD; /* ADCMPLD */
+ volatile uint16_t ADCMPHE; /* ADCMPHE */
+ volatile uint16_t ADCMPLE; /* ADCMPLE */
+ volatile uint16_t ADCMPHF; /* ADCMPHF */
+ volatile uint16_t ADCMPLF; /* ADCMPLF */
+ volatile uint16_t ADCMPHG; /* ADCMPHG */
+ volatile uint16_t ADCMPLG; /* ADCMPLG */
+ volatile uint16_t ADCMPHH; /* ADCMPHH */
+ volatile uint16_t ADCMPLH; /* ADCMPLH */
+ volatile uint8_t dummy33[32]; /* */
+ volatile uint16_t ADCSR; /* ADCSR */
+ volatile uint16_t ADCMPER; /* ADCMPER */
+ volatile uint16_t ADCMPSR; /* ADCMPSR */
+};
+
+
+#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */
+
+
+#define ADCADDRA ADC.ADDRA
+#define ADCADDRB ADC.ADDRB
+#define ADCADDRC ADC.ADDRC
+#define ADCADDRD ADC.ADDRD
+#define ADCADDRE ADC.ADDRE
+#define ADCADDRF ADC.ADDRF
+#define ADCADDRG ADC.ADDRG
+#define ADCADDRH ADC.ADDRH
+#define ADCADCMPHA ADC.ADCMPHA
+#define ADCADCMPLA ADC.ADCMPLA
+#define ADCADCMPHB ADC.ADCMPHB
+#define ADCADCMPLB ADC.ADCMPLB
+#define ADCADCMPHC ADC.ADCMPHC
+#define ADCADCMPLC ADC.ADCMPLC
+#define ADCADCMPHD ADC.ADCMPHD
+#define ADCADCMPLD ADC.ADCMPLD
+#define ADCADCMPHE ADC.ADCMPHE
+#define ADCADCMPLE ADC.ADCMPLE
+#define ADCADCMPHF ADC.ADCMPHF
+#define ADCADCMPLF ADC.ADCMPLF
+#define ADCADCMPHG ADC.ADCMPHG
+#define ADCADCMPLG ADC.ADCMPLG
+#define ADCADCMPHH ADC.ADCMPHH
+#define ADCADCMPLH ADC.ADCMPLH
+#define ADCADCSR ADC.ADCSR
+#define ADCADCMPER ADC.ADCMPER
+#define ADCADCMPSR ADC.ADCMPSR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,100 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : bsc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef BSC_IODEFINE_H
+#define BSC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_bsc
+{ /* BSC */
+ volatile uint32_t CMNCR; /* CMNCR */
+#define BSC_CSnBCR_COUNT 6
+ volatile uint32_t CS0BCR; /* CS0BCR */
+ volatile uint32_t CS1BCR; /* CS1BCR */
+ volatile uint32_t CS2BCR; /* CS2BCR */
+ volatile uint32_t CS3BCR; /* CS3BCR */
+ volatile uint32_t CS4BCR; /* CS4BCR */
+ volatile uint32_t CS5BCR; /* CS5BCR */
+ volatile uint8_t dummy4[12]; /* */
+#define BSC_CSnWCR_COUNT 6
+ volatile uint32_t CS0WCR; /* CS0WCR */
+ volatile uint32_t CS1WCR; /* CS1WCR */
+ volatile uint32_t CS2WCR; /* CS2WCR */
+ volatile uint32_t CS3WCR; /* CS3WCR */
+ volatile uint32_t CS4WCR; /* CS4WCR */
+ volatile uint32_t CS5WCR; /* CS5WCR */
+ volatile uint8_t dummy5[12]; /* */
+ volatile uint32_t SDCR; /* SDCR */
+ volatile uint32_t RTCSR; /* RTCSR */
+ volatile uint32_t RTCNT; /* RTCNT */
+ volatile uint32_t RTCOR; /* RTCOR */
+ volatile uint8_t dummy6[4]; /* */
+#define BSC_TOSCORn_COUNT 6
+ volatile uint32_t TOSCOR0; /* TOSCOR0 */
+ volatile uint32_t TOSCOR1; /* TOSCOR1 */
+ volatile uint32_t TOSCOR2; /* TOSCOR2 */
+ volatile uint32_t TOSCOR3; /* TOSCOR3 */
+ volatile uint32_t TOSCOR4; /* TOSCOR4 */
+ volatile uint32_t TOSCOR5; /* TOSCOR5 */
+ volatile uint8_t dummy7[8]; /* */
+ volatile uint32_t TOSTR; /* TOSTR */
+ volatile uint32_t TOENR; /* TOENR */
+};
+
+
+#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */
+
+
+#define BSCCMNCR BSC.CMNCR
+#define BSCCS0BCR BSC.CS0BCR
+#define BSCCS1BCR BSC.CS1BCR
+#define BSCCS2BCR BSC.CS2BCR
+#define BSCCS3BCR BSC.CS3BCR
+#define BSCCS4BCR BSC.CS4BCR
+#define BSCCS5BCR BSC.CS5BCR
+#define BSCCS0WCR BSC.CS0WCR
+#define BSCCS1WCR BSC.CS1WCR
+#define BSCCS2WCR BSC.CS2WCR
+#define BSCCS3WCR BSC.CS3WCR
+#define BSCCS4WCR BSC.CS4WCR
+#define BSCCS5WCR BSC.CS5WCR
+#define BSCSDCR BSC.SDCR
+#define BSCRTCSR BSC.RTCSR
+#define BSCRTCNT BSC.RTCNT
+#define BSCRTCOR BSC.RTCOR
+#define BSCTOSCOR0 BSC.TOSCOR0
+#define BSCTOSCOR1 BSC.TOSCOR1
+#define BSCTOSCOR2 BSC.TOSCOR2
+#define BSCTOSCOR3 BSC.TOSCOR3
+#define BSCTOSCOR4 BSC.TOSCOR4
+#define BSCTOSCOR5 BSC.TOSCOR5
+#define BSCTOSTR BSC.TOSTR
+#define BSCTOENR BSC.TOENR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,270 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ceu_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef CEU_IODEFINE_H
+#define CEU_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ceu
+{ /* CEU */
+/* start of struct st_ceu_n */
+ volatile uint32_t CAPSR; /* CAPSR */
+ volatile uint32_t CAPCR; /* CAPCR */
+ volatile uint32_t CAMCR; /* CAMCR */
+ volatile uint32_t CMCYR; /* CMCYR */
+ volatile uint32_t CAMOR_A; /* CAMOR_A */
+ volatile uint32_t CAPWR_A; /* CAPWR_A */
+ volatile uint32_t CAIFR; /* CAIFR */
+ volatile uint8_t dummy305[12]; /* */
+ volatile uint32_t CRCNTR; /* CRCNTR */
+ volatile uint32_t CRCMPR; /* CRCMPR */
+ volatile uint32_t CFLCR_A; /* CFLCR_A */
+ volatile uint32_t CFSZR_A; /* CFSZR_A */
+ volatile uint32_t CDWDR_A; /* CDWDR_A */
+ volatile uint32_t CDAYR_A; /* CDAYR_A */
+ volatile uint32_t CDACR_A; /* CDACR_A */
+ volatile uint32_t CDBYR_A; /* CDBYR_A */
+ volatile uint32_t CDBCR_A; /* CDBCR_A */
+ volatile uint32_t CBDSR_A; /* CBDSR_A */
+ volatile uint8_t dummy306[12]; /* */
+ volatile uint32_t CFWCR; /* CFWCR */
+ volatile uint32_t CLFCR_A; /* CLFCR_A */
+ volatile uint32_t CDOCR_A; /* CDOCR_A */
+ volatile uint8_t dummy307[8]; /* */
+ volatile uint32_t CEIER; /* CEIER */
+ volatile uint32_t CETCR; /* CETCR */
+ volatile uint8_t dummy308[4]; /* */
+ volatile uint32_t CSTSR; /* CSTSR */
+ volatile uint8_t dummy309[4]; /* */
+ volatile uint32_t CDSSR; /* CDSSR */
+ volatile uint8_t dummy310[8]; /* */
+ volatile uint32_t CDAYR2_A; /* CDAYR2_A */
+ volatile uint32_t CDACR2_A; /* CDACR2_A */
+ volatile uint32_t CDBYR2_A; /* CDBYR2_A */
+ volatile uint32_t CDBCR2_A; /* CDBCR2_A */
+/* end of struct st_ceu_n */
+ volatile uint8_t dummy3110[3936]; /* */
+/* start of struct st_ceu_n */
+ volatile uint8_t dummy3111[4]; /* */
+ volatile uint8_t dummy3112[4]; /* */
+ volatile uint8_t dummy3113[4]; /* */
+ volatile uint8_t dummy3114[4]; /* */
+ volatile uint32_t CAMOR_B; /* CAMOR_B */
+ volatile uint32_t CAPWR_B; /* CAPWR_B */
+ volatile uint8_t dummy3120[4]; /* */
+ volatile uint8_t dummy3121[12]; /* */
+ volatile uint8_t dummy3122[4]; /* */
+ volatile uint8_t dummy3123[4]; /* */
+ volatile uint32_t CFLCR_B; /* CFLCR_B */
+ volatile uint32_t CFSZR_B; /* CFSZR_B */
+ volatile uint32_t CDWDR_B; /* CDWDR_B */
+ volatile uint32_t CDAYR_B; /* CDAYR_B */
+ volatile uint32_t CDACR_B; /* CDACR_B */
+ volatile uint32_t CDBYR_B; /* CDBYR_B */
+ volatile uint32_t CDBCR_B; /* CDBCR_B */
+ volatile uint32_t CBDSR_B; /* CBDSR_B */
+ volatile uint8_t dummy3130[12]; /* */
+ volatile uint8_t dummy3131[4]; /* */
+ volatile uint32_t CLFCR_B; /* CLFCR_B */
+ volatile uint32_t CDOCR_B; /* CDOCR_B */
+ volatile uint8_t dummy3140[8]; /* */
+ volatile uint8_t dummy3141[4]; /* */
+ volatile uint8_t dummy3142[4]; /* */
+ volatile uint8_t dummy3143[4]; /* */
+ volatile uint8_t dummy3144[4]; /* */
+ volatile uint8_t dummy3145[4]; /* */
+ volatile uint8_t dummy3146[4]; /* */
+ volatile uint8_t dummy3147[8]; /* */
+ volatile uint32_t CDAYR2_B; /* CDAYR2_B */
+ volatile uint32_t CDACR2_B; /* CDACR2_B */
+ volatile uint32_t CDBYR2_B; /* CDBYR2_B */
+ volatile uint32_t CDBCR2_B; /* CDBCR2_B */
+/* end of struct st_ceu_n */
+ volatile uint8_t dummy3150[3936]; /* */
+/* start of struct st_ceu_n */
+ volatile uint8_t dummy3151[4]; /* */
+ volatile uint8_t dummy3152[4]; /* */
+ volatile uint8_t dummy3153[4]; /* */
+ volatile uint8_t dummy3154[4]; /* */
+ volatile uint32_t CAMOR_M; /* CAMOR_M */
+ volatile uint32_t CAPWR_M; /* CAPWR_M */
+ volatile uint8_t dummy3160[4]; /* */
+ volatile uint8_t dummy3161[12]; /* */
+ volatile uint8_t dummy3162[4]; /* */
+ volatile uint8_t dummy3163[4]; /* */
+ volatile uint32_t CFLCR_M; /* CFLCR_M */
+ volatile uint32_t CFSZR_M; /* CFSZR_M */
+ volatile uint32_t CDWDR_M; /* CDWDR_M */
+ volatile uint32_t CDAYR_M; /* CDAYR_M */
+ volatile uint32_t CDACR_M; /* CDACR_M */
+ volatile uint32_t CDBYR_M; /* CDBYR_M */
+ volatile uint32_t CDBCR_M; /* CDBCR_M */
+ volatile uint32_t CBDSR_M; /* CBDSR_M */
+ volatile uint8_t dummy3170[12]; /* */
+ volatile uint8_t dummy3171[4]; /* */
+ volatile uint32_t CLFCR_M; /* CLFCR_M */
+ volatile uint32_t CDOCR_M; /* CDOCR_M */
+ volatile uint8_t dummy3180[8]; /* */
+ volatile uint8_t dummy3181[4]; /* */
+ volatile uint8_t dummy3182[4]; /* */
+ volatile uint8_t dummy3183[4]; /* */
+ volatile uint8_t dummy3184[4]; /* */
+ volatile uint8_t dummy3185[4]; /* */
+ volatile uint8_t dummy3186[4]; /* */
+ volatile uint8_t dummy3187[8]; /* */
+ volatile uint32_t CDAYR2_M; /* CDAYR2_M */
+ volatile uint32_t CDACR2_M; /* CDACR2_M */
+ volatile uint32_t CDBYR2_M; /* CDBYR2_M */
+ volatile uint32_t CDBCR2_M; /* CDBCR2_M */
+/* end of struct st_ceu_n */
+};
+
+
+struct st_ceu_n
+{
+ volatile uint32_t not_common1; /* */
+ volatile uint32_t not_common2; /* */
+ volatile uint32_t not_common3; /* */
+ volatile uint32_t not_common4; /* */
+ volatile uint32_t CAMOR; /* CAMOR */
+ volatile uint32_t CAPWR; /* CAPWR */
+ volatile uint32_t not_common5; /* */
+ volatile uint8_t dummy322[12]; /* */
+ volatile uint32_t not_common6; /* */
+ volatile uint32_t not_common7; /* */
+ volatile uint32_t CFLCR; /* CFLCR */
+ volatile uint32_t CFSZR; /* CFSZR */
+ volatile uint32_t CDWDR; /* CDWDR */
+ volatile uint32_t CDAYR; /* CDAYR */
+ volatile uint32_t CDACR; /* CDACR */
+ volatile uint32_t CDBYR; /* CDBYR */
+ volatile uint32_t CDBCR; /* CDBCR */
+ volatile uint32_t CBDSR; /* CBDSR */
+ volatile uint8_t dummy323[12]; /* */
+ volatile uint32_t not_common8; /* */
+ volatile uint32_t CLFCR; /* CLFCR */
+ volatile uint32_t CDOCR; /* CDOCR */
+ volatile uint8_t dummy324[8]; /* */
+ volatile uint32_t not_common9; /* */
+ volatile uint32_t not_common10; /* */
+ volatile uint8_t dummy325[4]; /* */
+ volatile uint32_t not_common11; /* */
+ volatile uint8_t dummy326[4]; /* */
+ volatile uint32_t not_common12; /* */
+ volatile uint8_t dummy327[8]; /* */
+ volatile uint32_t CDAYR2; /* CDAYR2 */
+ volatile uint32_t CDACR2; /* CDACR2 */
+ volatile uint32_t CDBYR2; /* CDBYR2 */
+ volatile uint32_t CDBCR2; /* CDBCR2 */
+};
+
+
+#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */
+
+
+/* Start of channnel array defines of CEU */
+
+/* Channnel array defines of CEUn */
+/*(Sample) value = CEUn[ channel ]->CAMOR; */
+#define CEUn_COUNT 3
+#define CEUn_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ (volatile struct st_ceu_n*)&CEU_A, \
+ (volatile struct st_ceu_n*)&CEU_B, \
+ (volatile struct st_ceu_n*)&CEU_M \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */
+#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */
+#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */
+
+/* End of channnel array defines of CEU */
+
+
+#define CEUCAPSR CEU.CAPSR
+#define CEUCAPCR CEU.CAPCR
+#define CEUCAMCR CEU.CAMCR
+#define CEUCMCYR CEU.CMCYR
+#define CEUCAMOR_A CEU.CAMOR_A
+#define CEUCAPWR_A CEU.CAPWR_A
+#define CEUCAIFR CEU.CAIFR
+#define CEUCRCNTR CEU.CRCNTR
+#define CEUCRCMPR CEU.CRCMPR
+#define CEUCFLCR_A CEU.CFLCR_A
+#define CEUCFSZR_A CEU.CFSZR_A
+#define CEUCDWDR_A CEU.CDWDR_A
+#define CEUCDAYR_A CEU.CDAYR_A
+#define CEUCDACR_A CEU.CDACR_A
+#define CEUCDBYR_A CEU.CDBYR_A
+#define CEUCDBCR_A CEU.CDBCR_A
+#define CEUCBDSR_A CEU.CBDSR_A
+#define CEUCFWCR CEU.CFWCR
+#define CEUCLFCR_A CEU.CLFCR_A
+#define CEUCDOCR_A CEU.CDOCR_A
+#define CEUCEIER CEU.CEIER
+#define CEUCETCR CEU.CETCR
+#define CEUCSTSR CEU.CSTSR
+#define CEUCDSSR CEU.CDSSR
+#define CEUCDAYR2_A CEU.CDAYR2_A
+#define CEUCDACR2_A CEU.CDACR2_A
+#define CEUCDBYR2_A CEU.CDBYR2_A
+#define CEUCDBCR2_A CEU.CDBCR2_A
+#define CEUCAMOR_B CEU.CAMOR_B
+#define CEUCAPWR_B CEU.CAPWR_B
+#define CEUCFLCR_B CEU.CFLCR_B
+#define CEUCFSZR_B CEU.CFSZR_B
+#define CEUCDWDR_B CEU.CDWDR_B
+#define CEUCDAYR_B CEU.CDAYR_B
+#define CEUCDACR_B CEU.CDACR_B
+#define CEUCDBYR_B CEU.CDBYR_B
+#define CEUCDBCR_B CEU.CDBCR_B
+#define CEUCBDSR_B CEU.CBDSR_B
+#define CEUCLFCR_B CEU.CLFCR_B
+#define CEUCDOCR_B CEU.CDOCR_B
+#define CEUCDAYR2_B CEU.CDAYR2_B
+#define CEUCDACR2_B CEU.CDACR2_B
+#define CEUCDBYR2_B CEU.CDBYR2_B
+#define CEUCDBCR2_B CEU.CDBCR2_B
+#define CEUCAMOR_M CEU.CAMOR_M
+#define CEUCAPWR_M CEU.CAPWR_M
+#define CEUCFLCR_M CEU.CFLCR_M
+#define CEUCFSZR_M CEU.CFSZR_M
+#define CEUCDWDR_M CEU.CDWDR_M
+#define CEUCDAYR_M CEU.CDAYR_M
+#define CEUCDACR_M CEU.CDACR_M
+#define CEUCDBYR_M CEU.CDBYR_M
+#define CEUCDBCR_M CEU.CDBCR_M
+#define CEUCBDSR_M CEU.CBDSR_M
+#define CEUCLFCR_M CEU.CLFCR_M
+#define CEUCDOCR_M CEU.CDOCR_M
+#define CEUCDAYR2_M CEU.CDAYR2_M
+#define CEUCDACR2_M CEU.CDACR2_M
+#define CEUCDBYR2_M CEU.CDBYR2_M
+#define CEUCDBCR2_M CEU.CDBCR2_M
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,240 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : cpg_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef CPG_IODEFINE_H
+#define CPG_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_cpg
+{ /* CPG */
+ volatile uint16_t FRQCR; /* FRQCR */
+ volatile uint8_t dummy319[2]; /* */
+ volatile uint16_t FRQCR2; /* FRQCR2 */
+ volatile uint8_t dummy320[2]; /* */
+ volatile uint8_t CPUSTS; /* CPUSTS */
+ volatile uint8_t dummy321[7]; /* */
+ volatile uint8_t STBCR1; /* STBCR1 */
+ volatile uint8_t dummy322[3]; /* */
+ volatile uint8_t STBCR2; /* STBCR2 */
+ volatile uint8_t dummy323[11]; /* */
+ volatile uint8_t STBREQ1; /* STBREQ1 */
+ volatile uint8_t dummy324[3]; /* */
+ volatile uint8_t STBREQ2; /* STBREQ2 */
+ volatile uint8_t dummy325[11]; /* */
+ volatile uint8_t STBACK1; /* STBACK1 */
+ volatile uint8_t dummy326[3]; /* */
+ volatile uint8_t STBACK2; /* STBACK2 */
+ volatile uint8_t dummy327[955]; /* */
+/* start of struct st_cpg_from_syscr1 */
+ volatile uint8_t SYSCR1; /* SYSCR1 */
+ volatile uint8_t dummy328[3]; /* */
+/* end of struct st_cpg_from_syscr1 */
+/* start of struct st_cpg_from_syscr1 */
+ volatile uint8_t SYSCR2; /* SYSCR2 */
+ volatile uint8_t dummy329[3]; /* */
+/* end of struct st_cpg_from_syscr1 */
+/* start of struct st_cpg_from_syscr1 */
+ volatile uint8_t SYSCR3; /* SYSCR3 */
+ volatile uint8_t dummy3300[3]; /* */
+/* end of struct st_cpg_from_syscr1 */
+ volatile uint8_t dummy3301[20]; /* */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR3; /* STBCR3 */
+ volatile uint8_t dummy331[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR4; /* STBCR4 */
+ volatile uint8_t dummy332[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR5; /* STBCR5 */
+ volatile uint8_t dummy333[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR6; /* STBCR6 */
+ volatile uint8_t dummy334[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR7; /* STBCR7 */
+ volatile uint8_t dummy335[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR8; /* STBCR8 */
+ volatile uint8_t dummy336[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR9; /* STBCR9 */
+ volatile uint8_t dummy337[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR10; /* STBCR10 */
+ volatile uint8_t dummy338[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR11; /* STBCR11 */
+ volatile uint8_t dummy339[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+ volatile uint8_t STBCR12; /* STBCR12 */
+ volatile uint8_t dummy3400[3]; /* */
+/* end of struct st_cpg_from_stbcr3 */
+ volatile uint8_t dummy3401[24]; /* */
+/* start of struct st_cpg_from_swrstcr1 */
+ volatile uint8_t SWRSTCR1; /* SWRSTCR1 */
+ volatile uint8_t dummy341[3]; /* */
+/* end of struct st_cpg_from_swrstcr1 */
+/* start of struct st_cpg_from_swrstcr1 */
+ volatile uint8_t SWRSTCR2; /* SWRSTCR2 */
+ volatile uint8_t dummy342[3]; /* */
+/* end of struct st_cpg_from_swrstcr1 */
+/* start of struct st_cpg_from_swrstcr1 */
+ volatile uint8_t SWRSTCR3; /* SWRSTCR3 */
+ volatile uint8_t dummy3430[3]; /* */
+/* end of struct st_cpg_from_swrstcr1 */
+ volatile uint8_t dummy3431[4]; /* */
+ volatile uint8_t STBCR13; /* STBCR13 */
+ volatile uint8_t dummy344[70543]; /* */
+ volatile uint8_t RRAMKP; /* RRAMKP */
+ volatile uint8_t dummy345[1]; /* */
+ volatile uint8_t DSCTR; /* DSCTR */
+ volatile uint8_t dummy346[1]; /* */
+ volatile uint16_t DSSSR; /* DSSSR */
+ volatile uint16_t DSESR; /* DSESR */
+ volatile uint16_t DSFR; /* DSFR */
+ volatile uint8_t dummy347[6]; /* */
+ volatile uint8_t XTALCTR; /* XTALCTR */
+};
+
+
+struct st_cpg_from_syscr1
+{
+ volatile uint8_t SYSCR1; /* SYSCR1 */
+ volatile uint8_t dummy1[3]; /* */
+};
+
+
+struct st_cpg_from_stbcr3
+{
+ volatile uint8_t STBCR3; /* STBCR3 */
+ volatile uint8_t dummy1[3]; /* */
+};
+
+
+struct st_cpg_from_swrstcr1
+{
+ volatile uint8_t SWRSTCR1; /* SWRSTCR1 */
+ volatile uint8_t dummy1[3]; /* */
+};
+
+
+#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */
+
+
+/* Start of channnel array defines of CPG */
+
+/* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */
+/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
+#define CPG_FROM_SWRSTCR1_ARRAY_COUNT 3
+#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
+#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
+#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
+
+
+/* Channnel array defines of CPG_FROM_STBCR3_ARRAY */
+/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
+#define CPG_FROM_STBCR3_ARRAY_COUNT 10
+#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
+ &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
+#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
+#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
+#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
+#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
+#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
+#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
+#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
+#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
+#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
+
+
+/* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */
+/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
+#define CPG_FROM_SYSCR1_ARRAY_COUNT 3
+#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
+#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
+#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
+
+/* End of channnel array defines of CPG */
+
+
+#define CPGFRQCR CPG.FRQCR
+#define CPGFRQCR2 CPG.FRQCR2
+#define CPGCPUSTS CPG.CPUSTS
+#define CPGSTBCR1 CPG.STBCR1
+#define CPGSTBCR2 CPG.STBCR2
+#define CPGSTBREQ1 CPG.STBREQ1
+#define CPGSTBREQ2 CPG.STBREQ2
+#define CPGSTBACK1 CPG.STBACK1
+#define CPGSTBACK2 CPG.STBACK2
+#define CPGSYSCR1 CPG.SYSCR1
+#define CPGSYSCR2 CPG.SYSCR2
+#define CPGSYSCR3 CPG.SYSCR3
+#define CPGSTBCR3 CPG.STBCR3
+#define CPGSTBCR4 CPG.STBCR4
+#define CPGSTBCR5 CPG.STBCR5
+#define CPGSTBCR6 CPG.STBCR6
+#define CPGSTBCR7 CPG.STBCR7
+#define CPGSTBCR8 CPG.STBCR8
+#define CPGSTBCR9 CPG.STBCR9
+#define CPGSTBCR10 CPG.STBCR10
+#define CPGSTBCR11 CPG.STBCR11
+#define CPGSTBCR12 CPG.STBCR12
+#define CPGSWRSTCR1 CPG.SWRSTCR1
+#define CPGSWRSTCR2 CPG.SWRSTCR2
+#define CPGSWRSTCR3 CPG.SWRSTCR3
+#define CPGSTBCR13 CPG.STBCR13
+#define CPGRRAMKP CPG.RRAMKP
+#define CPGDSCTR CPG.DSCTR
+#define CPGDSSSR CPG.DSSSR
+#define CPGDSESR CPG.DSESR
+#define CPGDSFR CPG.DSFR
+#define CPGXTALCTR CPG.XTALCTR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,94 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : disc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef DISC_IODEFINE_H
+#define DISC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_disc
+{ /* DISC */
+ volatile uint32_t DOCMCR; /* DOCMCR */
+ volatile uint32_t DOCMSTR; /* DOCMSTR */
+ volatile uint32_t DOCMCLSTR; /* DOCMCLSTR */
+ volatile uint32_t DOCMIENR; /* DOCMIENR */
+ volatile uint8_t dummy1[4]; /* */
+ volatile uint32_t DOCMPMR; /* DOCMPMR */
+ volatile uint32_t DOCMECRCR; /* DOCMECRCR */
+ volatile uint32_t DOCMCCRCR; /* DOCMCCRCR */
+ volatile uint32_t DOCMSPXR; /* DOCMSPXR */
+ volatile uint32_t DOCMSPYR; /* DOCMSPYR */
+ volatile uint32_t DOCMSZXR; /* DOCMSZXR */
+ volatile uint32_t DOCMSZYR; /* DOCMSZYR */
+ volatile uint32_t DOCMCRCIR; /* DOCMCRCIR */
+};
+
+
+#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */
+#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */
+
+
+/* Start of channnel array defines of DISC */
+
+/* Channnel array defines of DISC */
+/*(Sample) value = DISC[ channel ]->DOCMCR; */
+#define DISC_COUNT 2
+#define DISC_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &DISC0, &DISC1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of DISC */
+
+
+#define DISC0DOCMCR DISC0.DOCMCR
+#define DISC0DOCMSTR DISC0.DOCMSTR
+#define DISC0DOCMCLSTR DISC0.DOCMCLSTR
+#define DISC0DOCMIENR DISC0.DOCMIENR
+#define DISC0DOCMPMR DISC0.DOCMPMR
+#define DISC0DOCMECRCR DISC0.DOCMECRCR
+#define DISC0DOCMCCRCR DISC0.DOCMCCRCR
+#define DISC0DOCMSPXR DISC0.DOCMSPXR
+#define DISC0DOCMSPYR DISC0.DOCMSPYR
+#define DISC0DOCMSZXR DISC0.DOCMSZXR
+#define DISC0DOCMSZYR DISC0.DOCMSZYR
+#define DISC0DOCMCRCIR DISC0.DOCMCRCIR
+#define DISC1DOCMCR DISC1.DOCMCR
+#define DISC1DOCMSTR DISC1.DOCMSTR
+#define DISC1DOCMCLSTR DISC1.DOCMCLSTR
+#define DISC1DOCMIENR DISC1.DOCMIENR
+#define DISC1DOCMPMR DISC1.DOCMPMR
+#define DISC1DOCMECRCR DISC1.DOCMECRCR
+#define DISC1DOCMCCRCR DISC1.DOCMCCRCR
+#define DISC1DOCMSPXR DISC1.DOCMSPXR
+#define DISC1DOCMSPYR DISC1.DOCMSPYR
+#define DISC1DOCMSZXR DISC1.DOCMSZXR
+#define DISC1DOCMSZYR DISC1.DOCMSZYR
+#define DISC1DOCMCRCIR DISC1.DOCMCRCIR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,734 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : dmac_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef DMAC_IODEFINE_H
+#define DMAC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_dmac
+{ /* DMAC */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_0; /* N0SA_0 */
+ volatile uint32_t N0DA_0; /* N0DA_0 */
+ volatile uint32_t N0TB_0; /* N0TB_0 */
+ volatile uint32_t N1SA_0; /* N1SA_0 */
+ volatile uint32_t N1DA_0; /* N1DA_0 */
+ volatile uint32_t N1TB_0; /* N1TB_0 */
+ volatile uint32_t CRSA_0; /* CRSA_0 */
+ volatile uint32_t CRDA_0; /* CRDA_0 */
+ volatile uint32_t CRTB_0; /* CRTB_0 */
+ volatile uint32_t CHSTAT_0; /* CHSTAT_0 */
+ volatile uint32_t CHCTRL_0; /* CHCTRL_0 */
+ volatile uint32_t CHCFG_0; /* CHCFG_0 */
+ volatile uint32_t CHITVL_0; /* CHITVL_0 */
+ volatile uint32_t CHEXT_0; /* CHEXT_0 */
+ volatile uint32_t NXLA_0; /* NXLA_0 */
+ volatile uint32_t CRLA_0; /* CRLA_0 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_1; /* N0SA_1 */
+ volatile uint32_t N0DA_1; /* N0DA_1 */
+ volatile uint32_t N0TB_1; /* N0TB_1 */
+ volatile uint32_t N1SA_1; /* N1SA_1 */
+ volatile uint32_t N1DA_1; /* N1DA_1 */
+ volatile uint32_t N1TB_1; /* N1TB_1 */
+ volatile uint32_t CRSA_1; /* CRSA_1 */
+ volatile uint32_t CRDA_1; /* CRDA_1 */
+ volatile uint32_t CRTB_1; /* CRTB_1 */
+ volatile uint32_t CHSTAT_1; /* CHSTAT_1 */
+ volatile uint32_t CHCTRL_1; /* CHCTRL_1 */
+ volatile uint32_t CHCFG_1; /* CHCFG_1 */
+ volatile uint32_t CHITVL_1; /* CHITVL_1 */
+ volatile uint32_t CHEXT_1; /* CHEXT_1 */
+ volatile uint32_t NXLA_1; /* NXLA_1 */
+ volatile uint32_t CRLA_1; /* CRLA_1 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_2; /* N0SA_2 */
+ volatile uint32_t N0DA_2; /* N0DA_2 */
+ volatile uint32_t N0TB_2; /* N0TB_2 */
+ volatile uint32_t N1SA_2; /* N1SA_2 */
+ volatile uint32_t N1DA_2; /* N1DA_2 */
+ volatile uint32_t N1TB_2; /* N1TB_2 */
+ volatile uint32_t CRSA_2; /* CRSA_2 */
+ volatile uint32_t CRDA_2; /* CRDA_2 */
+ volatile uint32_t CRTB_2; /* CRTB_2 */
+ volatile uint32_t CHSTAT_2; /* CHSTAT_2 */
+ volatile uint32_t CHCTRL_2; /* CHCTRL_2 */
+ volatile uint32_t CHCFG_2; /* CHCFG_2 */
+ volatile uint32_t CHITVL_2; /* CHITVL_2 */
+ volatile uint32_t CHEXT_2; /* CHEXT_2 */
+ volatile uint32_t NXLA_2; /* NXLA_2 */
+ volatile uint32_t CRLA_2; /* CRLA_2 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_3; /* N0SA_3 */
+ volatile uint32_t N0DA_3; /* N0DA_3 */
+ volatile uint32_t N0TB_3; /* N0TB_3 */
+ volatile uint32_t N1SA_3; /* N1SA_3 */
+ volatile uint32_t N1DA_3; /* N1DA_3 */
+ volatile uint32_t N1TB_3; /* N1TB_3 */
+ volatile uint32_t CRSA_3; /* CRSA_3 */
+ volatile uint32_t CRDA_3; /* CRDA_3 */
+ volatile uint32_t CRTB_3; /* CRTB_3 */
+ volatile uint32_t CHSTAT_3; /* CHSTAT_3 */
+ volatile uint32_t CHCTRL_3; /* CHCTRL_3 */
+ volatile uint32_t CHCFG_3; /* CHCFG_3 */
+ volatile uint32_t CHITVL_3; /* CHITVL_3 */
+ volatile uint32_t CHEXT_3; /* CHEXT_3 */
+ volatile uint32_t NXLA_3; /* NXLA_3 */
+ volatile uint32_t CRLA_3; /* CRLA_3 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_4; /* N0SA_4 */
+ volatile uint32_t N0DA_4; /* N0DA_4 */
+ volatile uint32_t N0TB_4; /* N0TB_4 */
+ volatile uint32_t N1SA_4; /* N1SA_4 */
+ volatile uint32_t N1DA_4; /* N1DA_4 */
+ volatile uint32_t N1TB_4; /* N1TB_4 */
+ volatile uint32_t CRSA_4; /* CRSA_4 */
+ volatile uint32_t CRDA_4; /* CRDA_4 */
+ volatile uint32_t CRTB_4; /* CRTB_4 */
+ volatile uint32_t CHSTAT_4; /* CHSTAT_4 */
+ volatile uint32_t CHCTRL_4; /* CHCTRL_4 */
+ volatile uint32_t CHCFG_4; /* CHCFG_4 */
+ volatile uint32_t CHITVL_4; /* CHITVL_4 */
+ volatile uint32_t CHEXT_4; /* CHEXT_4 */
+ volatile uint32_t NXLA_4; /* NXLA_4 */
+ volatile uint32_t CRLA_4; /* CRLA_4 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_5; /* N0SA_5 */
+ volatile uint32_t N0DA_5; /* N0DA_5 */
+ volatile uint32_t N0TB_5; /* N0TB_5 */
+ volatile uint32_t N1SA_5; /* N1SA_5 */
+ volatile uint32_t N1DA_5; /* N1DA_5 */
+ volatile uint32_t N1TB_5; /* N1TB_5 */
+ volatile uint32_t CRSA_5; /* CRSA_5 */
+ volatile uint32_t CRDA_5; /* CRDA_5 */
+ volatile uint32_t CRTB_5; /* CRTB_5 */
+ volatile uint32_t CHSTAT_5; /* CHSTAT_5 */
+ volatile uint32_t CHCTRL_5; /* CHCTRL_5 */
+ volatile uint32_t CHCFG_5; /* CHCFG_5 */
+ volatile uint32_t CHITVL_5; /* CHITVL_5 */
+ volatile uint32_t CHEXT_5; /* CHEXT_5 */
+ volatile uint32_t NXLA_5; /* NXLA_5 */
+ volatile uint32_t CRLA_5; /* CRLA_5 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_6; /* N0SA_6 */
+ volatile uint32_t N0DA_6; /* N0DA_6 */
+ volatile uint32_t N0TB_6; /* N0TB_6 */
+ volatile uint32_t N1SA_6; /* N1SA_6 */
+ volatile uint32_t N1DA_6; /* N1DA_6 */
+ volatile uint32_t N1TB_6; /* N1TB_6 */
+ volatile uint32_t CRSA_6; /* CRSA_6 */
+ volatile uint32_t CRDA_6; /* CRDA_6 */
+ volatile uint32_t CRTB_6; /* CRTB_6 */
+ volatile uint32_t CHSTAT_6; /* CHSTAT_6 */
+ volatile uint32_t CHCTRL_6; /* CHCTRL_6 */
+ volatile uint32_t CHCFG_6; /* CHCFG_6 */
+ volatile uint32_t CHITVL_6; /* CHITVL_6 */
+ volatile uint32_t CHEXT_6; /* CHEXT_6 */
+ volatile uint32_t NXLA_6; /* NXLA_6 */
+ volatile uint32_t CRLA_6; /* CRLA_6 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_7; /* N0SA_7 */
+ volatile uint32_t N0DA_7; /* N0DA_7 */
+ volatile uint32_t N0TB_7; /* N0TB_7 */
+ volatile uint32_t N1SA_7; /* N1SA_7 */
+ volatile uint32_t N1DA_7; /* N1DA_7 */
+ volatile uint32_t N1TB_7; /* N1TB_7 */
+ volatile uint32_t CRSA_7; /* CRSA_7 */
+ volatile uint32_t CRDA_7; /* CRDA_7 */
+ volatile uint32_t CRTB_7; /* CRTB_7 */
+ volatile uint32_t CHSTAT_7; /* CHSTAT_7 */
+ volatile uint32_t CHCTRL_7; /* CHCTRL_7 */
+ volatile uint32_t CHCFG_7; /* CHCFG_7 */
+ volatile uint32_t CHITVL_7; /* CHITVL_7 */
+ volatile uint32_t CHEXT_7; /* CHEXT_7 */
+ volatile uint32_t NXLA_7; /* NXLA_7 */
+ volatile uint32_t CRLA_7; /* CRLA_7 */
+/* end of struct st_dmac_n */
+ volatile uint8_t dummy187[256]; /* */
+/* start of struct st_dmaccommon_n */
+ volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */
+ volatile uint8_t dummy188[12]; /* */
+ volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */
+ volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */
+ volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */
+ volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */
+ volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */
+/* end of struct st_dmaccommon_n */
+ volatile uint8_t dummy189[220]; /* */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_8; /* N0SA_8 */
+ volatile uint32_t N0DA_8; /* N0DA_8 */
+ volatile uint32_t N0TB_8; /* N0TB_8 */
+ volatile uint32_t N1SA_8; /* N1SA_8 */
+ volatile uint32_t N1DA_8; /* N1DA_8 */
+ volatile uint32_t N1TB_8; /* N1TB_8 */
+ volatile uint32_t CRSA_8; /* CRSA_8 */
+ volatile uint32_t CRDA_8; /* CRDA_8 */
+ volatile uint32_t CRTB_8; /* CRTB_8 */
+ volatile uint32_t CHSTAT_8; /* CHSTAT_8 */
+ volatile uint32_t CHCTRL_8; /* CHCTRL_8 */
+ volatile uint32_t CHCFG_8; /* CHCFG_8 */
+ volatile uint32_t CHITVL_8; /* CHITVL_8 */
+ volatile uint32_t CHEXT_8; /* CHEXT_8 */
+ volatile uint32_t NXLA_8; /* NXLA_8 */
+ volatile uint32_t CRLA_8; /* CRLA_8 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_9; /* N0SA_9 */
+ volatile uint32_t N0DA_9; /* N0DA_9 */
+ volatile uint32_t N0TB_9; /* N0TB_9 */
+ volatile uint32_t N1SA_9; /* N1SA_9 */
+ volatile uint32_t N1DA_9; /* N1DA_9 */
+ volatile uint32_t N1TB_9; /* N1TB_9 */
+ volatile uint32_t CRSA_9; /* CRSA_9 */
+ volatile uint32_t CRDA_9; /* CRDA_9 */
+ volatile uint32_t CRTB_9; /* CRTB_9 */
+ volatile uint32_t CHSTAT_9; /* CHSTAT_9 */
+ volatile uint32_t CHCTRL_9; /* CHCTRL_9 */
+ volatile uint32_t CHCFG_9; /* CHCFG_9 */
+ volatile uint32_t CHITVL_9; /* CHITVL_9 */
+ volatile uint32_t CHEXT_9; /* CHEXT_9 */
+ volatile uint32_t NXLA_9; /* NXLA_9 */
+ volatile uint32_t CRLA_9; /* CRLA_9 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_10; /* N0SA_10 */
+ volatile uint32_t N0DA_10; /* N0DA_10 */
+ volatile uint32_t N0TB_10; /* N0TB_10 */
+ volatile uint32_t N1SA_10; /* N1SA_10 */
+ volatile uint32_t N1DA_10; /* N1DA_10 */
+ volatile uint32_t N1TB_10; /* N1TB_10 */
+ volatile uint32_t CRSA_10; /* CRSA_10 */
+ volatile uint32_t CRDA_10; /* CRDA_10 */
+ volatile uint32_t CRTB_10; /* CRTB_10 */
+ volatile uint32_t CHSTAT_10; /* CHSTAT_10 */
+ volatile uint32_t CHCTRL_10; /* CHCTRL_10 */
+ volatile uint32_t CHCFG_10; /* CHCFG_10 */
+ volatile uint32_t CHITVL_10; /* CHITVL_10 */
+ volatile uint32_t CHEXT_10; /* CHEXT_10 */
+ volatile uint32_t NXLA_10; /* NXLA_10 */
+ volatile uint32_t CRLA_10; /* CRLA_10 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_11; /* N0SA_11 */
+ volatile uint32_t N0DA_11; /* N0DA_11 */
+ volatile uint32_t N0TB_11; /* N0TB_11 */
+ volatile uint32_t N1SA_11; /* N1SA_11 */
+ volatile uint32_t N1DA_11; /* N1DA_11 */
+ volatile uint32_t N1TB_11; /* N1TB_11 */
+ volatile uint32_t CRSA_11; /* CRSA_11 */
+ volatile uint32_t CRDA_11; /* CRDA_11 */
+ volatile uint32_t CRTB_11; /* CRTB_11 */
+ volatile uint32_t CHSTAT_11; /* CHSTAT_11 */
+ volatile uint32_t CHCTRL_11; /* CHCTRL_11 */
+ volatile uint32_t CHCFG_11; /* CHCFG_11 */
+ volatile uint32_t CHITVL_11; /* CHITVL_11 */
+ volatile uint32_t CHEXT_11; /* CHEXT_11 */
+ volatile uint32_t NXLA_11; /* NXLA_11 */
+ volatile uint32_t CRLA_11; /* CRLA_11 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_12; /* N0SA_12 */
+ volatile uint32_t N0DA_12; /* N0DA_12 */
+ volatile uint32_t N0TB_12; /* N0TB_12 */
+ volatile uint32_t N1SA_12; /* N1SA_12 */
+ volatile uint32_t N1DA_12; /* N1DA_12 */
+ volatile uint32_t N1TB_12; /* N1TB_12 */
+ volatile uint32_t CRSA_12; /* CRSA_12 */
+ volatile uint32_t CRDA_12; /* CRDA_12 */
+ volatile uint32_t CRTB_12; /* CRTB_12 */
+ volatile uint32_t CHSTAT_12; /* CHSTAT_12 */
+ volatile uint32_t CHCTRL_12; /* CHCTRL_12 */
+ volatile uint32_t CHCFG_12; /* CHCFG_12 */
+ volatile uint32_t CHITVL_12; /* CHITVL_12 */
+ volatile uint32_t CHEXT_12; /* CHEXT_12 */
+ volatile uint32_t NXLA_12; /* NXLA_12 */
+ volatile uint32_t CRLA_12; /* CRLA_12 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_13; /* N0SA_13 */
+ volatile uint32_t N0DA_13; /* N0DA_13 */
+ volatile uint32_t N0TB_13; /* N0TB_13 */
+ volatile uint32_t N1SA_13; /* N1SA_13 */
+ volatile uint32_t N1DA_13; /* N1DA_13 */
+ volatile uint32_t N1TB_13; /* N1TB_13 */
+ volatile uint32_t CRSA_13; /* CRSA_13 */
+ volatile uint32_t CRDA_13; /* CRDA_13 */
+ volatile uint32_t CRTB_13; /* CRTB_13 */
+ volatile uint32_t CHSTAT_13; /* CHSTAT_13 */
+ volatile uint32_t CHCTRL_13; /* CHCTRL_13 */
+ volatile uint32_t CHCFG_13; /* CHCFG_13 */
+ volatile uint32_t CHITVL_13; /* CHITVL_13 */
+ volatile uint32_t CHEXT_13; /* CHEXT_13 */
+ volatile uint32_t NXLA_13; /* NXLA_13 */
+ volatile uint32_t CRLA_13; /* CRLA_13 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_14; /* N0SA_14 */
+ volatile uint32_t N0DA_14; /* N0DA_14 */
+ volatile uint32_t N0TB_14; /* N0TB_14 */
+ volatile uint32_t N1SA_14; /* N1SA_14 */
+ volatile uint32_t N1DA_14; /* N1DA_14 */
+ volatile uint32_t N1TB_14; /* N1TB_14 */
+ volatile uint32_t CRSA_14; /* CRSA_14 */
+ volatile uint32_t CRDA_14; /* CRDA_14 */
+ volatile uint32_t CRTB_14; /* CRTB_14 */
+ volatile uint32_t CHSTAT_14; /* CHSTAT_14 */
+ volatile uint32_t CHCTRL_14; /* CHCTRL_14 */
+ volatile uint32_t CHCFG_14; /* CHCFG_14 */
+ volatile uint32_t CHITVL_14; /* CHITVL_14 */
+ volatile uint32_t CHEXT_14; /* CHEXT_14 */
+ volatile uint32_t NXLA_14; /* NXLA_14 */
+ volatile uint32_t CRLA_14; /* CRLA_14 */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+ volatile uint32_t N0SA_15; /* N0SA_15 */
+ volatile uint32_t N0DA_15; /* N0DA_15 */
+ volatile uint32_t N0TB_15; /* N0TB_15 */
+ volatile uint32_t N1SA_15; /* N1SA_15 */
+ volatile uint32_t N1DA_15; /* N1DA_15 */
+ volatile uint32_t N1TB_15; /* N1TB_15 */
+ volatile uint32_t CRSA_15; /* CRSA_15 */
+ volatile uint32_t CRDA_15; /* CRDA_15 */
+ volatile uint32_t CRTB_15; /* CRTB_15 */
+ volatile uint32_t CHSTAT_15; /* CHSTAT_15 */
+ volatile uint32_t CHCTRL_15; /* CHCTRL_15 */
+ volatile uint32_t CHCFG_15; /* CHCFG_15 */
+ volatile uint32_t CHITVL_15; /* CHITVL_15 */
+ volatile uint32_t CHEXT_15; /* CHEXT_15 */
+ volatile uint32_t NXLA_15; /* NXLA_15 */
+ volatile uint32_t CRLA_15; /* CRLA_15 */
+/* end of struct st_dmac_n */
+ volatile uint8_t dummy190[256]; /* */
+/* start of struct st_dmaccommon_n */
+ volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */
+ volatile uint8_t dummy191[12]; /* */
+ volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */
+ volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */
+ volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */
+ volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */
+ volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */
+/* end of struct st_dmaccommon_n */
+ volatile uint8_t dummy192[350095580]; /* */
+ volatile uint32_t DMARS0; /* DMARS0 */
+ volatile uint32_t DMARS1; /* DMARS1 */
+ volatile uint32_t DMARS2; /* DMARS2 */
+ volatile uint32_t DMARS3; /* DMARS3 */
+ volatile uint32_t DMARS4; /* DMARS4 */
+ volatile uint32_t DMARS5; /* DMARS5 */
+ volatile uint32_t DMARS6; /* DMARS6 */
+ volatile uint32_t DMARS7; /* DMARS7 */
+};
+
+
+struct st_dmaccommon_n
+{
+ volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */
+ volatile uint8_t dummy1[12]; /* */
+ volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */
+ volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */
+ volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */
+ volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */
+ volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */
+};
+
+
+struct st_dmac_n
+{
+ volatile uint32_t N0SA_n; /* N0SA_n */
+ volatile uint32_t N0DA_n; /* N0DA_n */
+ volatile uint32_t N0TB_n; /* N0TB_n */
+ volatile uint32_t N1SA_n; /* N1SA_n */
+ volatile uint32_t N1DA_n; /* N1DA_n */
+ volatile uint32_t N1TB_n; /* N1TB_n */
+ volatile uint32_t CRSA_n; /* CRSA_n */
+ volatile uint32_t CRDA_n; /* CRDA_n */
+ volatile uint32_t CRTB_n; /* CRTB_n */
+ volatile uint32_t CHSTAT_n; /* CHSTAT_n */
+ volatile uint32_t CHCTRL_n; /* CHCTRL_n */
+ volatile uint32_t CHCFG_n; /* CHCFG_n */
+ volatile uint32_t CHITVL_n; /* CHITVL_n */
+ volatile uint32_t CHEXT_n; /* CHEXT_n */
+ volatile uint32_t NXLA_n; /* NXLA_n */
+ volatile uint32_t CRLA_n; /* CRLA_n */
+};
+
+
+#define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */
+
+
+/* Start of channnel array defines of DMAC */
+
+/* Channnel array defines of DMACn */
+/*(Sample) value = DMACn[ channel ]->N0SA_n; */
+#define DMACn_COUNT 16
+#define DMACn_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \
+ &DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC0 (*(struct st_dmac_n *)&DMAC.N0SA_0) /* DMAC0 */
+#define DMAC1 (*(struct st_dmac_n *)&DMAC.N0SA_1) /* DMAC1 */
+#define DMAC2 (*(struct st_dmac_n *)&DMAC.N0SA_2) /* DMAC2 */
+#define DMAC3 (*(struct st_dmac_n *)&DMAC.N0SA_3) /* DMAC3 */
+#define DMAC4 (*(struct st_dmac_n *)&DMAC.N0SA_4) /* DMAC4 */
+#define DMAC5 (*(struct st_dmac_n *)&DMAC.N0SA_5) /* DMAC5 */
+#define DMAC6 (*(struct st_dmac_n *)&DMAC.N0SA_6) /* DMAC6 */
+#define DMAC7 (*(struct st_dmac_n *)&DMAC.N0SA_7) /* DMAC7 */
+#define DMAC8 (*(struct st_dmac_n *)&DMAC.N0SA_8) /* DMAC8 */
+#define DMAC9 (*(struct st_dmac_n *)&DMAC.N0SA_9) /* DMAC9 */
+#define DMAC10 (*(struct st_dmac_n *)&DMAC.N0SA_10) /* DMAC10 */
+#define DMAC11 (*(struct st_dmac_n *)&DMAC.N0SA_11) /* DMAC11 */
+#define DMAC12 (*(struct st_dmac_n *)&DMAC.N0SA_12) /* DMAC12 */
+#define DMAC13 (*(struct st_dmac_n *)&DMAC.N0SA_13) /* DMAC13 */
+#define DMAC14 (*(struct st_dmac_n *)&DMAC.N0SA_14) /* DMAC14 */
+#define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */
+
+
+/* Channnel array defines of DMACnn */
+/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */
+#define DMACnn_COUNT 2
+#define DMACnn_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &DMAC07, &DMAC815 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */
+#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */
+
+
+/* Channnel array defines of DMACmm */
+/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
+struct st_dmars_mm
+{
+ uint32_t DMARS; /* DMARS */
+};
+#define DMACmm_COUNT 8
+#define DMACmm_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */
+#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */
+#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */
+#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */
+#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */
+#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */
+#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */
+#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */
+
+/* End of channnel array defines of DMAC */
+
+
+#define DMACN0SA_0 DMAC.N0SA_0
+#define DMACN0DA_0 DMAC.N0DA_0
+#define DMACN0TB_0 DMAC.N0TB_0
+#define DMACN1SA_0 DMAC.N1SA_0
+#define DMACN1DA_0 DMAC.N1DA_0
+#define DMACN1TB_0 DMAC.N1TB_0
+#define DMACCRSA_0 DMAC.CRSA_0
+#define DMACCRDA_0 DMAC.CRDA_0
+#define DMACCRTB_0 DMAC.CRTB_0
+#define DMACCHSTAT_0 DMAC.CHSTAT_0
+#define DMACCHCTRL_0 DMAC.CHCTRL_0
+#define DMACCHCFG_0 DMAC.CHCFG_0
+#define DMACCHITVL_0 DMAC.CHITVL_0
+#define DMACCHEXT_0 DMAC.CHEXT_0
+#define DMACNXLA_0 DMAC.NXLA_0
+#define DMACCRLA_0 DMAC.CRLA_0
+#define DMACN0SA_1 DMAC.N0SA_1
+#define DMACN0DA_1 DMAC.N0DA_1
+#define DMACN0TB_1 DMAC.N0TB_1
+#define DMACN1SA_1 DMAC.N1SA_1
+#define DMACN1DA_1 DMAC.N1DA_1
+#define DMACN1TB_1 DMAC.N1TB_1
+#define DMACCRSA_1 DMAC.CRSA_1
+#define DMACCRDA_1 DMAC.CRDA_1
+#define DMACCRTB_1 DMAC.CRTB_1
+#define DMACCHSTAT_1 DMAC.CHSTAT_1
+#define DMACCHCTRL_1 DMAC.CHCTRL_1
+#define DMACCHCFG_1 DMAC.CHCFG_1
+#define DMACCHITVL_1 DMAC.CHITVL_1
+#define DMACCHEXT_1 DMAC.CHEXT_1
+#define DMACNXLA_1 DMAC.NXLA_1
+#define DMACCRLA_1 DMAC.CRLA_1
+#define DMACN0SA_2 DMAC.N0SA_2
+#define DMACN0DA_2 DMAC.N0DA_2
+#define DMACN0TB_2 DMAC.N0TB_2
+#define DMACN1SA_2 DMAC.N1SA_2
+#define DMACN1DA_2 DMAC.N1DA_2
+#define DMACN1TB_2 DMAC.N1TB_2
+#define DMACCRSA_2 DMAC.CRSA_2
+#define DMACCRDA_2 DMAC.CRDA_2
+#define DMACCRTB_2 DMAC.CRTB_2
+#define DMACCHSTAT_2 DMAC.CHSTAT_2
+#define DMACCHCTRL_2 DMAC.CHCTRL_2
+#define DMACCHCFG_2 DMAC.CHCFG_2
+#define DMACCHITVL_2 DMAC.CHITVL_2
+#define DMACCHEXT_2 DMAC.CHEXT_2
+#define DMACNXLA_2 DMAC.NXLA_2
+#define DMACCRLA_2 DMAC.CRLA_2
+#define DMACN0SA_3 DMAC.N0SA_3
+#define DMACN0DA_3 DMAC.N0DA_3
+#define DMACN0TB_3 DMAC.N0TB_3
+#define DMACN1SA_3 DMAC.N1SA_3
+#define DMACN1DA_3 DMAC.N1DA_3
+#define DMACN1TB_3 DMAC.N1TB_3
+#define DMACCRSA_3 DMAC.CRSA_3
+#define DMACCRDA_3 DMAC.CRDA_3
+#define DMACCRTB_3 DMAC.CRTB_3
+#define DMACCHSTAT_3 DMAC.CHSTAT_3
+#define DMACCHCTRL_3 DMAC.CHCTRL_3
+#define DMACCHCFG_3 DMAC.CHCFG_3
+#define DMACCHITVL_3 DMAC.CHITVL_3
+#define DMACCHEXT_3 DMAC.CHEXT_3
+#define DMACNXLA_3 DMAC.NXLA_3
+#define DMACCRLA_3 DMAC.CRLA_3
+#define DMACN0SA_4 DMAC.N0SA_4
+#define DMACN0DA_4 DMAC.N0DA_4
+#define DMACN0TB_4 DMAC.N0TB_4
+#define DMACN1SA_4 DMAC.N1SA_4
+#define DMACN1DA_4 DMAC.N1DA_4
+#define DMACN1TB_4 DMAC.N1TB_4
+#define DMACCRSA_4 DMAC.CRSA_4
+#define DMACCRDA_4 DMAC.CRDA_4
+#define DMACCRTB_4 DMAC.CRTB_4
+#define DMACCHSTAT_4 DMAC.CHSTAT_4
+#define DMACCHCTRL_4 DMAC.CHCTRL_4
+#define DMACCHCFG_4 DMAC.CHCFG_4
+#define DMACCHITVL_4 DMAC.CHITVL_4
+#define DMACCHEXT_4 DMAC.CHEXT_4
+#define DMACNXLA_4 DMAC.NXLA_4
+#define DMACCRLA_4 DMAC.CRLA_4
+#define DMACN0SA_5 DMAC.N0SA_5
+#define DMACN0DA_5 DMAC.N0DA_5
+#define DMACN0TB_5 DMAC.N0TB_5
+#define DMACN1SA_5 DMAC.N1SA_5
+#define DMACN1DA_5 DMAC.N1DA_5
+#define DMACN1TB_5 DMAC.N1TB_5
+#define DMACCRSA_5 DMAC.CRSA_5
+#define DMACCRDA_5 DMAC.CRDA_5
+#define DMACCRTB_5 DMAC.CRTB_5
+#define DMACCHSTAT_5 DMAC.CHSTAT_5
+#define DMACCHCTRL_5 DMAC.CHCTRL_5
+#define DMACCHCFG_5 DMAC.CHCFG_5
+#define DMACCHITVL_5 DMAC.CHITVL_5
+#define DMACCHEXT_5 DMAC.CHEXT_5
+#define DMACNXLA_5 DMAC.NXLA_5
+#define DMACCRLA_5 DMAC.CRLA_5
+#define DMACN0SA_6 DMAC.N0SA_6
+#define DMACN0DA_6 DMAC.N0DA_6
+#define DMACN0TB_6 DMAC.N0TB_6
+#define DMACN1SA_6 DMAC.N1SA_6
+#define DMACN1DA_6 DMAC.N1DA_6
+#define DMACN1TB_6 DMAC.N1TB_6
+#define DMACCRSA_6 DMAC.CRSA_6
+#define DMACCRDA_6 DMAC.CRDA_6
+#define DMACCRTB_6 DMAC.CRTB_6
+#define DMACCHSTAT_6 DMAC.CHSTAT_6
+#define DMACCHCTRL_6 DMAC.CHCTRL_6
+#define DMACCHCFG_6 DMAC.CHCFG_6
+#define DMACCHITVL_6 DMAC.CHITVL_6
+#define DMACCHEXT_6 DMAC.CHEXT_6
+#define DMACNXLA_6 DMAC.NXLA_6
+#define DMACCRLA_6 DMAC.CRLA_6
+#define DMACN0SA_7 DMAC.N0SA_7
+#define DMACN0DA_7 DMAC.N0DA_7
+#define DMACN0TB_7 DMAC.N0TB_7
+#define DMACN1SA_7 DMAC.N1SA_7
+#define DMACN1DA_7 DMAC.N1DA_7
+#define DMACN1TB_7 DMAC.N1TB_7
+#define DMACCRSA_7 DMAC.CRSA_7
+#define DMACCRDA_7 DMAC.CRDA_7
+#define DMACCRTB_7 DMAC.CRTB_7
+#define DMACCHSTAT_7 DMAC.CHSTAT_7
+#define DMACCHCTRL_7 DMAC.CHCTRL_7
+#define DMACCHCFG_7 DMAC.CHCFG_7
+#define DMACCHITVL_7 DMAC.CHITVL_7
+#define DMACCHEXT_7 DMAC.CHEXT_7
+#define DMACNXLA_7 DMAC.NXLA_7
+#define DMACCRLA_7 DMAC.CRLA_7
+#define DMACDCTRL_0_7 DMAC.DCTRL_0_7
+#define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7
+#define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7
+#define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7
+#define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7
+#define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7
+#define DMACN0SA_8 DMAC.N0SA_8
+#define DMACN0DA_8 DMAC.N0DA_8
+#define DMACN0TB_8 DMAC.N0TB_8
+#define DMACN1SA_8 DMAC.N1SA_8
+#define DMACN1DA_8 DMAC.N1DA_8
+#define DMACN1TB_8 DMAC.N1TB_8
+#define DMACCRSA_8 DMAC.CRSA_8
+#define DMACCRDA_8 DMAC.CRDA_8
+#define DMACCRTB_8 DMAC.CRTB_8
+#define DMACCHSTAT_8 DMAC.CHSTAT_8
+#define DMACCHCTRL_8 DMAC.CHCTRL_8
+#define DMACCHCFG_8 DMAC.CHCFG_8
+#define DMACCHITVL_8 DMAC.CHITVL_8
+#define DMACCHEXT_8 DMAC.CHEXT_8
+#define DMACNXLA_8 DMAC.NXLA_8
+#define DMACCRLA_8 DMAC.CRLA_8
+#define DMACN0SA_9 DMAC.N0SA_9
+#define DMACN0DA_9 DMAC.N0DA_9
+#define DMACN0TB_9 DMAC.N0TB_9
+#define DMACN1SA_9 DMAC.N1SA_9
+#define DMACN1DA_9 DMAC.N1DA_9
+#define DMACN1TB_9 DMAC.N1TB_9
+#define DMACCRSA_9 DMAC.CRSA_9
+#define DMACCRDA_9 DMAC.CRDA_9
+#define DMACCRTB_9 DMAC.CRTB_9
+#define DMACCHSTAT_9 DMAC.CHSTAT_9
+#define DMACCHCTRL_9 DMAC.CHCTRL_9
+#define DMACCHCFG_9 DMAC.CHCFG_9
+#define DMACCHITVL_9 DMAC.CHITVL_9
+#define DMACCHEXT_9 DMAC.CHEXT_9
+#define DMACNXLA_9 DMAC.NXLA_9
+#define DMACCRLA_9 DMAC.CRLA_9
+#define DMACN0SA_10 DMAC.N0SA_10
+#define DMACN0DA_10 DMAC.N0DA_10
+#define DMACN0TB_10 DMAC.N0TB_10
+#define DMACN1SA_10 DMAC.N1SA_10
+#define DMACN1DA_10 DMAC.N1DA_10
+#define DMACN1TB_10 DMAC.N1TB_10
+#define DMACCRSA_10 DMAC.CRSA_10
+#define DMACCRDA_10 DMAC.CRDA_10
+#define DMACCRTB_10 DMAC.CRTB_10
+#define DMACCHSTAT_10 DMAC.CHSTAT_10
+#define DMACCHCTRL_10 DMAC.CHCTRL_10
+#define DMACCHCFG_10 DMAC.CHCFG_10
+#define DMACCHITVL_10 DMAC.CHITVL_10
+#define DMACCHEXT_10 DMAC.CHEXT_10
+#define DMACNXLA_10 DMAC.NXLA_10
+#define DMACCRLA_10 DMAC.CRLA_10
+#define DMACN0SA_11 DMAC.N0SA_11
+#define DMACN0DA_11 DMAC.N0DA_11
+#define DMACN0TB_11 DMAC.N0TB_11
+#define DMACN1SA_11 DMAC.N1SA_11
+#define DMACN1DA_11 DMAC.N1DA_11
+#define DMACN1TB_11 DMAC.N1TB_11
+#define DMACCRSA_11 DMAC.CRSA_11
+#define DMACCRDA_11 DMAC.CRDA_11
+#define DMACCRTB_11 DMAC.CRTB_11
+#define DMACCHSTAT_11 DMAC.CHSTAT_11
+#define DMACCHCTRL_11 DMAC.CHCTRL_11
+#define DMACCHCFG_11 DMAC.CHCFG_11
+#define DMACCHITVL_11 DMAC.CHITVL_11
+#define DMACCHEXT_11 DMAC.CHEXT_11
+#define DMACNXLA_11 DMAC.NXLA_11
+#define DMACCRLA_11 DMAC.CRLA_11
+#define DMACN0SA_12 DMAC.N0SA_12
+#define DMACN0DA_12 DMAC.N0DA_12
+#define DMACN0TB_12 DMAC.N0TB_12
+#define DMACN1SA_12 DMAC.N1SA_12
+#define DMACN1DA_12 DMAC.N1DA_12
+#define DMACN1TB_12 DMAC.N1TB_12
+#define DMACCRSA_12 DMAC.CRSA_12
+#define DMACCRDA_12 DMAC.CRDA_12
+#define DMACCRTB_12 DMAC.CRTB_12
+#define DMACCHSTAT_12 DMAC.CHSTAT_12
+#define DMACCHCTRL_12 DMAC.CHCTRL_12
+#define DMACCHCFG_12 DMAC.CHCFG_12
+#define DMACCHITVL_12 DMAC.CHITVL_12
+#define DMACCHEXT_12 DMAC.CHEXT_12
+#define DMACNXLA_12 DMAC.NXLA_12
+#define DMACCRLA_12 DMAC.CRLA_12
+#define DMACN0SA_13 DMAC.N0SA_13
+#define DMACN0DA_13 DMAC.N0DA_13
+#define DMACN0TB_13 DMAC.N0TB_13
+#define DMACN1SA_13 DMAC.N1SA_13
+#define DMACN1DA_13 DMAC.N1DA_13
+#define DMACN1TB_13 DMAC.N1TB_13
+#define DMACCRSA_13 DMAC.CRSA_13
+#define DMACCRDA_13 DMAC.CRDA_13
+#define DMACCRTB_13 DMAC.CRTB_13
+#define DMACCHSTAT_13 DMAC.CHSTAT_13
+#define DMACCHCTRL_13 DMAC.CHCTRL_13
+#define DMACCHCFG_13 DMAC.CHCFG_13
+#define DMACCHITVL_13 DMAC.CHITVL_13
+#define DMACCHEXT_13 DMAC.CHEXT_13
+#define DMACNXLA_13 DMAC.NXLA_13
+#define DMACCRLA_13 DMAC.CRLA_13
+#define DMACN0SA_14 DMAC.N0SA_14
+#define DMACN0DA_14 DMAC.N0DA_14
+#define DMACN0TB_14 DMAC.N0TB_14
+#define DMACN1SA_14 DMAC.N1SA_14
+#define DMACN1DA_14 DMAC.N1DA_14
+#define DMACN1TB_14 DMAC.N1TB_14
+#define DMACCRSA_14 DMAC.CRSA_14
+#define DMACCRDA_14 DMAC.CRDA_14
+#define DMACCRTB_14 DMAC.CRTB_14
+#define DMACCHSTAT_14 DMAC.CHSTAT_14
+#define DMACCHCTRL_14 DMAC.CHCTRL_14
+#define DMACCHCFG_14 DMAC.CHCFG_14
+#define DMACCHITVL_14 DMAC.CHITVL_14
+#define DMACCHEXT_14 DMAC.CHEXT_14
+#define DMACNXLA_14 DMAC.NXLA_14
+#define DMACCRLA_14 DMAC.CRLA_14
+#define DMACN0SA_15 DMAC.N0SA_15
+#define DMACN0DA_15 DMAC.N0DA_15
+#define DMACN0TB_15 DMAC.N0TB_15
+#define DMACN1SA_15 DMAC.N1SA_15
+#define DMACN1DA_15 DMAC.N1DA_15
+#define DMACN1TB_15 DMAC.N1TB_15
+#define DMACCRSA_15 DMAC.CRSA_15
+#define DMACCRDA_15 DMAC.CRDA_15
+#define DMACCRTB_15 DMAC.CRTB_15
+#define DMACCHSTAT_15 DMAC.CHSTAT_15
+#define DMACCHCTRL_15 DMAC.CHCTRL_15
+#define DMACCHCFG_15 DMAC.CHCFG_15
+#define DMACCHITVL_15 DMAC.CHITVL_15
+#define DMACCHEXT_15 DMAC.CHEXT_15
+#define DMACNXLA_15 DMAC.NXLA_15
+#define DMACCRLA_15 DMAC.CRLA_15
+#define DMACDCTRL_8_15 DMAC.DCTRL_8_15
+#define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15
+#define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15
+#define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15
+#define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15
+#define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15
+#define DMACDMARS0 DMAC.DMARS0
+#define DMACDMARS1 DMAC.DMARS1
+#define DMACDMARS2 DMAC.DMARS2
+#define DMACDMARS3 DMAC.DMARS3
+#define DMACDMARS4 DMAC.DMARS4
+#define DMACDMARS5 DMAC.DMARS5
+#define DMACDMARS6 DMAC.DMARS6
+#define DMACDMARS7 DMAC.DMARS7
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,392 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : dvdec_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef DVDEC_IODEFINE_H
+#define DVDEC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_dvdec
+{ /* DVDEC */
+ volatile uint16_t ADCCR1; /* ADCCR1 */
+ volatile uint8_t dummy1[4]; /* */
+#define DVDEC_TGCRn_COUNT 3
+ volatile uint16_t TGCR1; /* TGCR1 */
+ volatile uint16_t TGCR2; /* TGCR2 */
+ volatile uint16_t TGCR3; /* TGCR3 */
+ volatile uint8_t dummy2[6]; /* */
+#define DVDEC_SYNSCRn_COUNT 5
+ volatile uint16_t SYNSCR1; /* SYNSCR1 */
+ volatile uint16_t SYNSCR2; /* SYNSCR2 */
+ volatile uint16_t SYNSCR3; /* SYNSCR3 */
+ volatile uint16_t SYNSCR4; /* SYNSCR4 */
+ volatile uint16_t SYNSCR5; /* SYNSCR5 */
+#define DVDEC_HAFCCRn_COUNT 3
+ volatile uint16_t HAFCCR1; /* HAFCCR1 */
+ volatile uint16_t HAFCCR2; /* HAFCCR2 */
+ volatile uint16_t HAFCCR3; /* HAFCCR3 */
+ volatile uint16_t VCDWCR1; /* VCDWCR1 */
+ volatile uint8_t dummy3[4]; /* */
+#define DVDEC_DCPCRn_COUNT 8
+ volatile uint16_t DCPCR1; /* DCPCR1 */
+ volatile uint16_t DCPCR2; /* DCPCR2 */
+ volatile uint16_t DCPCR3; /* DCPCR3 */
+ volatile uint16_t DCPCR4; /* DCPCR4 */
+ volatile uint16_t DCPCR5; /* DCPCR5 */
+ volatile uint16_t DCPCR6; /* DCPCR6 */
+ volatile uint16_t DCPCR7; /* DCPCR7 */
+ volatile uint16_t DCPCR8; /* DCPCR8 */
+ volatile uint16_t NSDCR; /* NSDCR */
+ volatile uint16_t BTLCR; /* BTLCR */
+ volatile uint16_t BTGPCR; /* BTGPCR */
+#define DVDEC_ACCCRn_COUNT 3
+ volatile uint16_t ACCCR1; /* ACCCR1 */
+ volatile uint16_t ACCCR2; /* ACCCR2 */
+ volatile uint16_t ACCCR3; /* ACCCR3 */
+ volatile uint16_t TINTCR; /* TINTCR */
+ volatile uint16_t YCDCR; /* YCDCR */
+#define DVDEC_AGCCRn_COUNT 2
+ volatile uint16_t AGCCR1; /* AGCCR1 */
+ volatile uint16_t AGCCR2; /* AGCCR2 */
+ volatile uint16_t PKLIMITCR; /* PKLIMITCR */
+#define DVDEC_RGORCRn_COUNT 7
+ volatile uint16_t RGORCR1; /* RGORCR1 */
+ volatile uint16_t RGORCR2; /* RGORCR2 */
+ volatile uint16_t RGORCR3; /* RGORCR3 */
+ volatile uint16_t RGORCR4; /* RGORCR4 */
+ volatile uint16_t RGORCR5; /* RGORCR5 */
+ volatile uint16_t RGORCR6; /* RGORCR6 */
+ volatile uint16_t RGORCR7; /* RGORCR7 */
+ volatile uint8_t dummy4[24]; /* */
+ volatile uint16_t AFCPFCR; /* AFCPFCR */
+ volatile uint16_t RUPDCR; /* RUPDCR */
+ volatile uint16_t VSYNCSR; /* VSYNCSR */
+ volatile uint16_t HSYNCSR; /* HSYNCSR */
+#define DVDEC_DCPSRn_COUNT 2
+ volatile uint16_t DCPSR1; /* DCPSR1 */
+ volatile uint16_t DCPSR2; /* DCPSR2 */
+ volatile uint8_t dummy5[4]; /* */
+ volatile uint16_t NSDSR; /* NSDSR */
+#define DVDEC_CROMASRn_COUNT 2
+ volatile uint16_t CROMASR1; /* CROMASR1 */
+ volatile uint16_t CROMASR2; /* CROMASR2 */
+ volatile uint16_t SYNCSSR; /* SYNCSSR */
+#define DVDEC_AGCCSRn_COUNT 2
+ volatile uint16_t AGCCSR1; /* AGCCSR1 */
+ volatile uint16_t AGCCSR2; /* AGCCSR2 */
+ volatile uint8_t dummy6[108]; /* */
+#define DVDEC_YCSCRn_COUNT 7
+ volatile uint16_t YCSCR3; /* YCSCR3 */
+ volatile uint16_t YCSCR4; /* YCSCR4 */
+ volatile uint16_t YCSCR5; /* YCSCR5 */
+ volatile uint16_t YCSCR6; /* YCSCR6 */
+ volatile uint16_t YCSCR7; /* YCSCR7 */
+ volatile uint16_t YCSCR8; /* YCSCR8 */
+ volatile uint16_t YCSCR9; /* YCSCR9 */
+ volatile uint8_t dummy7[2]; /* */
+ volatile uint16_t YCSCR11; /* YCSCR11 */
+ volatile uint16_t YCSCR12; /* YCSCR12 */
+ volatile uint8_t dummy8[104]; /* */
+ volatile uint16_t DCPCR9; /* DCPCR9 */
+ volatile uint8_t dummy9[16]; /* */
+#define DVDEC_YCTWA_Fn_COUNT 9
+ volatile uint16_t YCTWA_F0; /* YCTWA_F0 */
+ volatile uint16_t YCTWA_F1; /* YCTWA_F1 */
+ volatile uint16_t YCTWA_F2; /* YCTWA_F2 */
+ volatile uint16_t YCTWA_F3; /* YCTWA_F3 */
+ volatile uint16_t YCTWA_F4; /* YCTWA_F4 */
+ volatile uint16_t YCTWA_F5; /* YCTWA_F5 */
+ volatile uint16_t YCTWA_F6; /* YCTWA_F6 */
+ volatile uint16_t YCTWA_F7; /* YCTWA_F7 */
+ volatile uint16_t YCTWA_F8; /* YCTWA_F8 */
+#define DVDEC_YCTWB_Fn_COUNT 9
+ volatile uint16_t YCTWB_F0; /* YCTWB_F0 */
+ volatile uint16_t YCTWB_F1; /* YCTWB_F1 */
+ volatile uint16_t YCTWB_F2; /* YCTWB_F2 */
+ volatile uint16_t YCTWB_F3; /* YCTWB_F3 */
+ volatile uint16_t YCTWB_F4; /* YCTWB_F4 */
+ volatile uint16_t YCTWB_F5; /* YCTWB_F5 */
+ volatile uint16_t YCTWB_F6; /* YCTWB_F6 */
+ volatile uint16_t YCTWB_F7; /* YCTWB_F7 */
+ volatile uint16_t YCTWB_F8; /* YCTWB_F8 */
+#define DVDEC_YCTNA_Fn_COUNT 9
+ volatile uint16_t YCTNA_F0; /* YCTNA_F0 */
+ volatile uint16_t YCTNA_F1; /* YCTNA_F1 */
+ volatile uint16_t YCTNA_F2; /* YCTNA_F2 */
+ volatile uint16_t YCTNA_F3; /* YCTNA_F3 */
+ volatile uint16_t YCTNA_F4; /* YCTNA_F4 */
+ volatile uint16_t YCTNA_F5; /* YCTNA_F5 */
+ volatile uint16_t YCTNA_F6; /* YCTNA_F6 */
+ volatile uint16_t YCTNA_F7; /* YCTNA_F7 */
+ volatile uint16_t YCTNA_F8; /* YCTNA_F8 */
+#define DVDEC_YCTNB_Fn_COUNT 9
+ volatile uint16_t YCTNB_F0; /* YCTNB_F0 */
+ volatile uint16_t YCTNB_F1; /* YCTNB_F1 */
+ volatile uint16_t YCTNB_F2; /* YCTNB_F2 */
+ volatile uint16_t YCTNB_F3; /* YCTNB_F3 */
+ volatile uint16_t YCTNB_F4; /* YCTNB_F4 */
+ volatile uint16_t YCTNB_F5; /* YCTNB_F5 */
+ volatile uint16_t YCTNB_F6; /* YCTNB_F6 */
+ volatile uint16_t YCTNB_F7; /* YCTNB_F7 */
+ volatile uint16_t YCTNB_F8; /* YCTNB_F8 */
+ volatile uint8_t dummy10[38]; /* */
+ volatile uint16_t YGAINCR; /* YGAINCR */
+ volatile uint16_t CBGAINCR; /* CBGAINCR */
+ volatile uint16_t CRGAINCR; /* CRGAINCR */
+ volatile uint8_t dummy11[122]; /* */
+ volatile uint16_t PGA_UPDATE; /* PGA_UPDATE */
+ volatile uint16_t PGACR; /* PGACR */
+ volatile uint16_t ADCCR2; /* ADCCR2 */
+};
+
+
+#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */
+#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */
+
+
+/* Start of channnel array defines of DVDEC */
+
+/* Channnel array defines of DVDEC */
+/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
+#define DVDEC_COUNT 2
+#define DVDEC_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &DVDEC0, &DVDEC1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of DVDEC */
+
+
+#define ADCCR1_1 DVDEC1.ADCCR1
+#define TGCR1_1 DVDEC1.TGCR1
+#define TGCR2_1 DVDEC1.TGCR2
+#define TGCR3_1 DVDEC1.TGCR3
+#define SYNSCR1_1 DVDEC1.SYNSCR1
+#define SYNSCR2_1 DVDEC1.SYNSCR2
+#define SYNSCR3_1 DVDEC1.SYNSCR3
+#define SYNSCR4_1 DVDEC1.SYNSCR4
+#define SYNSCR5_1 DVDEC1.SYNSCR5
+#define HAFCCR1_1 DVDEC1.HAFCCR1
+#define HAFCCR2_1 DVDEC1.HAFCCR2
+#define HAFCCR3_1 DVDEC1.HAFCCR3
+#define VCDWCR1_1 DVDEC1.VCDWCR1
+#define DCPCR1_1 DVDEC1.DCPCR1
+#define DCPCR2_1 DVDEC1.DCPCR2
+#define DCPCR3_1 DVDEC1.DCPCR3
+#define DCPCR4_1 DVDEC1.DCPCR4
+#define DCPCR5_1 DVDEC1.DCPCR5
+#define DCPCR6_1 DVDEC1.DCPCR6
+#define DCPCR7_1 DVDEC1.DCPCR7
+#define DCPCR8_1 DVDEC1.DCPCR8
+#define NSDCR_1 DVDEC1.NSDCR
+#define BTLCR_1 DVDEC1.BTLCR
+#define BTGPCR_1 DVDEC1.BTGPCR
+#define ACCCR1_1 DVDEC1.ACCCR1
+#define ACCCR2_1 DVDEC1.ACCCR2
+#define ACCCR3_1 DVDEC1.ACCCR3
+#define TINTCR_1 DVDEC1.TINTCR
+#define YCDCR_1 DVDEC1.YCDCR
+#define AGCCR1_1 DVDEC1.AGCCR1
+#define AGCCR2_1 DVDEC1.AGCCR2
+#define PKLIMITCR_1 DVDEC1.PKLIMITCR
+#define RGORCR1_1 DVDEC1.RGORCR1
+#define RGORCR2_1 DVDEC1.RGORCR2
+#define RGORCR3_1 DVDEC1.RGORCR3
+#define RGORCR4_1 DVDEC1.RGORCR4
+#define RGORCR5_1 DVDEC1.RGORCR5
+#define RGORCR6_1 DVDEC1.RGORCR6
+#define RGORCR7_1 DVDEC1.RGORCR7
+#define AFCPFCR_1 DVDEC1.AFCPFCR
+#define RUPDCR_1 DVDEC1.RUPDCR
+#define VSYNCSR_1 DVDEC1.VSYNCSR
+#define HSYNCSR_1 DVDEC1.HSYNCSR
+#define DCPSR1_1 DVDEC1.DCPSR1
+#define DCPSR2_1 DVDEC1.DCPSR2
+#define NSDSR_1 DVDEC1.NSDSR
+#define CROMASR1_1 DVDEC1.CROMASR1
+#define CROMASR2_1 DVDEC1.CROMASR2
+#define SYNCSSR_1 DVDEC1.SYNCSSR
+#define AGCCSR1_1 DVDEC1.AGCCSR1
+#define AGCCSR2_1 DVDEC1.AGCCSR2
+#define YCSCR3_1 DVDEC1.YCSCR3
+#define YCSCR4_1 DVDEC1.YCSCR4
+#define YCSCR5_1 DVDEC1.YCSCR5
+#define YCSCR6_1 DVDEC1.YCSCR6
+#define YCSCR7_1 DVDEC1.YCSCR7
+#define YCSCR8_1 DVDEC1.YCSCR8
+#define YCSCR9_1 DVDEC1.YCSCR9
+#define YCSCR11_1 DVDEC1.YCSCR11
+#define YCSCR12_1 DVDEC1.YCSCR12
+#define DCPCR9_1 DVDEC1.DCPCR9
+#define YCTWA_F0_1 DVDEC1.YCTWA_F0
+#define YCTWA_F1_1 DVDEC1.YCTWA_F1
+#define YCTWA_F2_1 DVDEC1.YCTWA_F2
+#define YCTWA_F3_1 DVDEC1.YCTWA_F3
+#define YCTWA_F4_1 DVDEC1.YCTWA_F4
+#define YCTWA_F5_1 DVDEC1.YCTWA_F5
+#define YCTWA_F6_1 DVDEC1.YCTWA_F6
+#define YCTWA_F7_1 DVDEC1.YCTWA_F7
+#define YCTWA_F8_1 DVDEC1.YCTWA_F8
+#define YCTWB_F0_1 DVDEC1.YCTWB_F0
+#define YCTWB_F1_1 DVDEC1.YCTWB_F1
+#define YCTWB_F2_1 DVDEC1.YCTWB_F2
+#define YCTWB_F3_1 DVDEC1.YCTWB_F3
+#define YCTWB_F4_1 DVDEC1.YCTWB_F4
+#define YCTWB_F5_1 DVDEC1.YCTWB_F5
+#define YCTWB_F6_1 DVDEC1.YCTWB_F6
+#define YCTWB_F7_1 DVDEC1.YCTWB_F7
+#define YCTWB_F8_1 DVDEC1.YCTWB_F8
+#define YCTNA_F0_1 DVDEC1.YCTNA_F0
+#define YCTNA_F1_1 DVDEC1.YCTNA_F1
+#define YCTNA_F2_1 DVDEC1.YCTNA_F2
+#define YCTNA_F3_1 DVDEC1.YCTNA_F3
+#define YCTNA_F4_1 DVDEC1.YCTNA_F4
+#define YCTNA_F5_1 DVDEC1.YCTNA_F5
+#define YCTNA_F6_1 DVDEC1.YCTNA_F6
+#define YCTNA_F7_1 DVDEC1.YCTNA_F7
+#define YCTNA_F8_1 DVDEC1.YCTNA_F8
+#define YCTNB_F0_1 DVDEC1.YCTNB_F0
+#define YCTNB_F1_1 DVDEC1.YCTNB_F1
+#define YCTNB_F2_1 DVDEC1.YCTNB_F2
+#define YCTNB_F3_1 DVDEC1.YCTNB_F3
+#define YCTNB_F4_1 DVDEC1.YCTNB_F4
+#define YCTNB_F5_1 DVDEC1.YCTNB_F5
+#define YCTNB_F6_1 DVDEC1.YCTNB_F6
+#define YCTNB_F7_1 DVDEC1.YCTNB_F7
+#define YCTNB_F8_1 DVDEC1.YCTNB_F8
+#define YGAINCR_1 DVDEC1.YGAINCR
+#define CBGAINCR_1 DVDEC1.CBGAINCR
+#define CRGAINCR_1 DVDEC1.CRGAINCR
+#define PGA_UPDATE_1 DVDEC1.PGA_UPDATE
+#define PGACR_1 DVDEC1.PGACR
+#define ADCCR2_1 DVDEC1.ADCCR2
+#define ADCCR1_0 DVDEC0.ADCCR1
+#define TGCR1_0 DVDEC0.TGCR1
+#define TGCR2_0 DVDEC0.TGCR2
+#define TGCR3_0 DVDEC0.TGCR3
+#define SYNSCR1_0 DVDEC0.SYNSCR1
+#define SYNSCR2_0 DVDEC0.SYNSCR2
+#define SYNSCR3_0 DVDEC0.SYNSCR3
+#define SYNSCR4_0 DVDEC0.SYNSCR4
+#define SYNSCR5_0 DVDEC0.SYNSCR5
+#define HAFCCR1_0 DVDEC0.HAFCCR1
+#define HAFCCR2_0 DVDEC0.HAFCCR2
+#define HAFCCR3_0 DVDEC0.HAFCCR3
+#define VCDWCR1_0 DVDEC0.VCDWCR1
+#define DCPCR1_0 DVDEC0.DCPCR1
+#define DCPCR2_0 DVDEC0.DCPCR2
+#define DCPCR3_0 DVDEC0.DCPCR3
+#define DCPCR4_0 DVDEC0.DCPCR4
+#define DCPCR5_0 DVDEC0.DCPCR5
+#define DCPCR6_0 DVDEC0.DCPCR6
+#define DCPCR7_0 DVDEC0.DCPCR7
+#define DCPCR8_0 DVDEC0.DCPCR8
+#define NSDCR_0 DVDEC0.NSDCR
+#define BTLCR_0 DVDEC0.BTLCR
+#define BTGPCR_0 DVDEC0.BTGPCR
+#define ACCCR1_0 DVDEC0.ACCCR1
+#define ACCCR2_0 DVDEC0.ACCCR2
+#define ACCCR3_0 DVDEC0.ACCCR3
+#define TINTCR_0 DVDEC0.TINTCR
+#define YCDCR_0 DVDEC0.YCDCR
+#define AGCCR1_0 DVDEC0.AGCCR1
+#define AGCCR2_0 DVDEC0.AGCCR2
+#define PKLIMITCR_0 DVDEC0.PKLIMITCR
+#define RGORCR1_0 DVDEC0.RGORCR1
+#define RGORCR2_0 DVDEC0.RGORCR2
+#define RGORCR3_0 DVDEC0.RGORCR3
+#define RGORCR4_0 DVDEC0.RGORCR4
+#define RGORCR5_0 DVDEC0.RGORCR5
+#define RGORCR6_0 DVDEC0.RGORCR6
+#define RGORCR7_0 DVDEC0.RGORCR7
+#define AFCPFCR_0 DVDEC0.AFCPFCR
+#define RUPDCR_0 DVDEC0.RUPDCR
+#define VSYNCSR_0 DVDEC0.VSYNCSR
+#define HSYNCSR_0 DVDEC0.HSYNCSR
+#define DCPSR1_0 DVDEC0.DCPSR1
+#define DCPSR2_0 DVDEC0.DCPSR2
+#define NSDSR_0 DVDEC0.NSDSR
+#define CROMASR1_0 DVDEC0.CROMASR1
+#define CROMASR2_0 DVDEC0.CROMASR2
+#define SYNCSSR_0 DVDEC0.SYNCSSR
+#define AGCCSR1_0 DVDEC0.AGCCSR1
+#define AGCCSR2_0 DVDEC0.AGCCSR2
+#define YCSCR3_0 DVDEC0.YCSCR3
+#define YCSCR4_0 DVDEC0.YCSCR4
+#define YCSCR5_0 DVDEC0.YCSCR5
+#define YCSCR6_0 DVDEC0.YCSCR6
+#define YCSCR7_0 DVDEC0.YCSCR7
+#define YCSCR8_0 DVDEC0.YCSCR8
+#define YCSCR9_0 DVDEC0.YCSCR9
+#define YCSCR11_0 DVDEC0.YCSCR11
+#define YCSCR12_0 DVDEC0.YCSCR12
+#define DCPCR9_0 DVDEC0.DCPCR9
+#define YCTWA_F0_0 DVDEC0.YCTWA_F0
+#define YCTWA_F1_0 DVDEC0.YCTWA_F1
+#define YCTWA_F2_0 DVDEC0.YCTWA_F2
+#define YCTWA_F3_0 DVDEC0.YCTWA_F3
+#define YCTWA_F4_0 DVDEC0.YCTWA_F4
+#define YCTWA_F5_0 DVDEC0.YCTWA_F5
+#define YCTWA_F6_0 DVDEC0.YCTWA_F6
+#define YCTWA_F7_0 DVDEC0.YCTWA_F7
+#define YCTWA_F8_0 DVDEC0.YCTWA_F8
+#define YCTWB_F0_0 DVDEC0.YCTWB_F0
+#define YCTWB_F1_0 DVDEC0.YCTWB_F1
+#define YCTWB_F2_0 DVDEC0.YCTWB_F2
+#define YCTWB_F3_0 DVDEC0.YCTWB_F3
+#define YCTWB_F4_0 DVDEC0.YCTWB_F4
+#define YCTWB_F5_0 DVDEC0.YCTWB_F5
+#define YCTWB_F6_0 DVDEC0.YCTWB_F6
+#define YCTWB_F7_0 DVDEC0.YCTWB_F7
+#define YCTWB_F8_0 DVDEC0.YCTWB_F8
+#define YCTNA_F0_0 DVDEC0.YCTNA_F0
+#define YCTNA_F1_0 DVDEC0.YCTNA_F1
+#define YCTNA_F2_0 DVDEC0.YCTNA_F2
+#define YCTNA_F3_0 DVDEC0.YCTNA_F3
+#define YCTNA_F4_0 DVDEC0.YCTNA_F4
+#define YCTNA_F5_0 DVDEC0.YCTNA_F5
+#define YCTNA_F6_0 DVDEC0.YCTNA_F6
+#define YCTNA_F7_0 DVDEC0.YCTNA_F7
+#define YCTNA_F8_0 DVDEC0.YCTNA_F8
+#define YCTNB_F0_0 DVDEC0.YCTNB_F0
+#define YCTNB_F1_0 DVDEC0.YCTNB_F1
+#define YCTNB_F2_0 DVDEC0.YCTNB_F2
+#define YCTNB_F3_0 DVDEC0.YCTNB_F3
+#define YCTNB_F4_0 DVDEC0.YCTNB_F4
+#define YCTNB_F5_0 DVDEC0.YCTNB_F5
+#define YCTNB_F6_0 DVDEC0.YCTNB_F6
+#define YCTNB_F7_0 DVDEC0.YCTNB_F7
+#define YCTNB_F8_0 DVDEC0.YCTNB_F8
+#define YGAINCR_0 DVDEC0.YGAINCR
+#define CBGAINCR_0 DVDEC0.CBGAINCR
+#define CRGAINCR_0 DVDEC0.CRGAINCR
+#define PGA_UPDATE_0 DVDEC0.PGA_UPDATE
+#define PGACR_0 DVDEC0.PGACR
+#define ADCCR2_0 DVDEC0.ADCCR2
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,428 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ether_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef ETHER_IODEFINE_H
+#define ETHER_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ether
+{ /* ETHER */
+ volatile uint32_t EDSR0; /* EDSR0 */
+ volatile uint8_t dummy207[12]; /* */
+ volatile uint32_t TDLAR0; /* TDLAR0 */
+ volatile uint32_t TDFAR0; /* TDFAR0 */
+ volatile uint32_t TDFXR0; /* TDFXR0 */
+ volatile uint32_t TDFFR0; /* TDFFR0 */
+ volatile uint8_t dummy208[16]; /* */
+ volatile uint32_t RDLAR0; /* RDLAR0 */
+ volatile uint32_t RDFAR0; /* RDFAR0 */
+ volatile uint32_t RDFXR0; /* RDFXR0 */
+ volatile uint32_t RDFFR0; /* RDFFR0 */
+ volatile uint8_t dummy209[960]; /* */
+ volatile uint32_t EDMR0; /* EDMR0 */
+ volatile uint8_t dummy210[4]; /* */
+ volatile uint32_t EDTRR0; /* EDTRR0 */
+ volatile uint8_t dummy211[4]; /* */
+ volatile uint32_t EDRRR0; /* EDRRR0 */
+ volatile uint8_t dummy212[20]; /* */
+ volatile uint32_t EESR0; /* EESR0 */
+ volatile uint8_t dummy213[4]; /* */
+ volatile uint32_t EESIPR0; /* EESIPR0 */
+ volatile uint8_t dummy214[4]; /* */
+ volatile uint32_t TRSCER0; /* TRSCER0 */
+ volatile uint8_t dummy215[4]; /* */
+ volatile uint32_t RMFCR0; /* RMFCR0 */
+ volatile uint8_t dummy216[4]; /* */
+ volatile uint32_t TFTR0; /* TFTR0 */
+ volatile uint8_t dummy217[4]; /* */
+ volatile uint32_t FDR0; /* FDR0 */
+ volatile uint8_t dummy218[4]; /* */
+ volatile uint32_t RMCR0; /* RMCR0 */
+ volatile uint8_t dummy219[4]; /* */
+ volatile uint32_t RPADIR0; /* RPADIR0 */
+ volatile uint8_t dummy220[4]; /* */
+ volatile uint32_t FCFTR0; /* FCFTR0 */
+ volatile uint8_t dummy221[120]; /* */
+ volatile uint32_t CSMR; /* CSMR */
+ volatile uint32_t CSSBM; /* CSSBM */
+ volatile uint32_t CSSMR; /* CSSMR */
+ volatile uint8_t dummy222[16]; /* */
+ volatile uint32_t ECMR0; /* ECMR0 */
+ volatile uint8_t dummy223[4]; /* */
+ volatile uint32_t RFLR0; /* RFLR0 */
+ volatile uint8_t dummy224[4]; /* */
+ volatile uint32_t ECSR0; /* ECSR0 */
+ volatile uint8_t dummy225[4]; /* */
+ volatile uint32_t ECSIPR0; /* ECSIPR0 */
+ volatile uint8_t dummy226[4]; /* */
+ volatile uint32_t PIR0; /* PIR0 */
+ volatile uint8_t dummy227[48]; /* */
+ volatile uint32_t APR0; /* APR0 */
+ volatile uint32_t MPR0; /* MPR0 */
+ volatile uint32_t PFTCR0; /* PFTCR0 */
+ volatile uint32_t PFRCR0; /* PFRCR0 */
+ volatile uint32_t TPAUSER0; /* TPAUSER0 */
+ volatile uint8_t dummy228[88]; /* */
+ volatile uint32_t MAHR0; /* MAHR0 */
+ volatile uint8_t dummy229[4]; /* */
+ volatile uint32_t MALR0; /* MALR0 */
+ volatile uint8_t dummy230[372]; /* */
+ volatile uint32_t CEFCR0; /* CEFCR0 */
+ volatile uint8_t dummy231[4]; /* */
+ volatile uint32_t FRECR0; /* FRECR0 */
+ volatile uint8_t dummy232[4]; /* */
+ volatile uint32_t TSFRCR0; /* TSFRCR0 */
+ volatile uint8_t dummy233[4]; /* */
+ volatile uint32_t TLFRCR0; /* TLFRCR0 */
+ volatile uint8_t dummy234[4]; /* */
+ volatile uint32_t RFCR0; /* RFCR0 */
+ volatile uint8_t dummy235[20]; /* */
+ volatile uint32_t MAFCR0; /* MAFCR0 */
+ volatile uint8_t dummy236[4228]; /* */
+ volatile uint32_t ARSTR; /* ARSTR */
+ volatile uint32_t TSU_CTRST; /* TSU_CTRST */
+ volatile uint8_t dummy237[80]; /* */
+ volatile uint32_t TSU_VTAG0; /* TSU_VTAG0 */
+ volatile uint8_t dummy238[4]; /* */
+ volatile uint32_t TSU_ADSBSY; /* TSU_ADSBSY */
+ volatile uint32_t TSU_TEN; /* TSU_TEN */
+ volatile uint8_t dummy239[24]; /* */
+ volatile uint32_t TXNLCR0; /* TXNLCR0 */
+ volatile uint32_t TXALCR0; /* TXALCR0 */
+ volatile uint32_t RXNLCR0; /* RXNLCR0 */
+ volatile uint32_t RXALCR0; /* RXALCR0 */
+ volatile uint8_t dummy240[112]; /* */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */
+ volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH1; /* TSU_ADRH1 */
+ volatile uint32_t TSU_ADRL1; /* TSU_ADRL1 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH2; /* TSU_ADRH2 */
+ volatile uint32_t TSU_ADRL2; /* TSU_ADRL2 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH3; /* TSU_ADRH3 */
+ volatile uint32_t TSU_ADRL3; /* TSU_ADRL3 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH4; /* TSU_ADRH4 */
+ volatile uint32_t TSU_ADRL4; /* TSU_ADRL4 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH5; /* TSU_ADRH5 */
+ volatile uint32_t TSU_ADRL5; /* TSU_ADRL5 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH6; /* TSU_ADRH6 */
+ volatile uint32_t TSU_ADRL6; /* TSU_ADRL6 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH7; /* TSU_ADRH7 */
+ volatile uint32_t TSU_ADRL7; /* TSU_ADRL7 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH8; /* TSU_ADRH8 */
+ volatile uint32_t TSU_ADRL8; /* TSU_ADRL8 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH9; /* TSU_ADRH9 */
+ volatile uint32_t TSU_ADRL9; /* TSU_ADRL9 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH10; /* TSU_ADRH10 */
+ volatile uint32_t TSU_ADRL10; /* TSU_ADRL10 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH11; /* TSU_ADRH11 */
+ volatile uint32_t TSU_ADRL11; /* TSU_ADRL11 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH12; /* TSU_ADRH12 */
+ volatile uint32_t TSU_ADRL12; /* TSU_ADRL12 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH13; /* TSU_ADRH13 */
+ volatile uint32_t TSU_ADRL13; /* TSU_ADRL13 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH14; /* TSU_ADRH14 */
+ volatile uint32_t TSU_ADRL14; /* TSU_ADRL14 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH15; /* TSU_ADRH15 */
+ volatile uint32_t TSU_ADRL15; /* TSU_ADRL15 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH16; /* TSU_ADRH16 */
+ volatile uint32_t TSU_ADRL16; /* TSU_ADRL16 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH17; /* TSU_ADRH17 */
+ volatile uint32_t TSU_ADRL17; /* TSU_ADRL17 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH18; /* TSU_ADRH18 */
+ volatile uint32_t TSU_ADRL18; /* TSU_ADRL18 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH19; /* TSU_ADRH19 */
+ volatile uint32_t TSU_ADRL19; /* TSU_ADRL19 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH20; /* TSU_ADRH20 */
+ volatile uint32_t TSU_ADRL20; /* TSU_ADRL20 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH21; /* TSU_ADRH21 */
+ volatile uint32_t TSU_ADRL21; /* TSU_ADRL21 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH22; /* TSU_ADRH22 */
+ volatile uint32_t TSU_ADRL22; /* TSU_ADRL22 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH23; /* TSU_ADRH23 */
+ volatile uint32_t TSU_ADRL23; /* TSU_ADRL23 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH24; /* TSU_ADRH24 */
+ volatile uint32_t TSU_ADRL24; /* TSU_ADRL24 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH25; /* TSU_ADRH25 */
+ volatile uint32_t TSU_ADRL25; /* TSU_ADRL25 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH26; /* TSU_ADRH26 */
+ volatile uint32_t TSU_ADRL26; /* TSU_ADRL26 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH27; /* TSU_ADRH27 */
+ volatile uint32_t TSU_ADRL27; /* TSU_ADRL27 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH28; /* TSU_ADRH28 */
+ volatile uint32_t TSU_ADRL28; /* TSU_ADRL28 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH29; /* TSU_ADRH29 */
+ volatile uint32_t TSU_ADRL29; /* TSU_ADRL29 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH30; /* TSU_ADRH30 */
+ volatile uint32_t TSU_ADRL30; /* TSU_ADRL30 */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+ volatile uint32_t TSU_ADRH31; /* TSU_ADRH31 */
+ volatile uint32_t TSU_ADRL31; /* TSU_ADRL31 */
+/* end of struct st_ether_from_tsu_adrh0 */
+};
+
+
+struct st_ether_from_tsu_adrh0
+{
+ volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */
+ volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */
+};
+
+
+#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */
+
+
+/* Start of channnel array defines of ETHER */
+
+/* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
+/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
+#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT 32
+#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ ÐER_FROM_TSU_ADRH0, ÐER_FROM_TSU_ADRH1, ÐER_FROM_TSU_ADRH2, ÐER_FROM_TSU_ADRH3, ÐER_FROM_TSU_ADRH4, ÐER_FROM_TSU_ADRH5, ÐER_FROM_TSU_ADRH6, ÐER_FROM_TSU_ADRH7, \
+ ÐER_FROM_TSU_ADRH8, ÐER_FROM_TSU_ADRH9, ÐER_FROM_TSU_ADRH10, ÐER_FROM_TSU_ADRH11, ÐER_FROM_TSU_ADRH12, ÐER_FROM_TSU_ADRH13, ÐER_FROM_TSU_ADRH14, ÐER_FROM_TSU_ADRH15, \
+ ÐER_FROM_TSU_ADRH16, ÐER_FROM_TSU_ADRH17, ÐER_FROM_TSU_ADRH18, ÐER_FROM_TSU_ADRH19, ÐER_FROM_TSU_ADRH20, ÐER_FROM_TSU_ADRH21, ÐER_FROM_TSU_ADRH22, ÐER_FROM_TSU_ADRH23, \
+ ÐER_FROM_TSU_ADRH24, ÐER_FROM_TSU_ADRH25, ÐER_FROM_TSU_ADRH26, ÐER_FROM_TSU_ADRH27, ÐER_FROM_TSU_ADRH28, ÐER_FROM_TSU_ADRH29, ÐER_FROM_TSU_ADRH30, ÐER_FROM_TSU_ADRH31 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
+#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
+#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
+#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
+#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
+#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
+#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
+#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
+#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
+#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
+#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
+#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
+#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
+#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
+#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
+#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
+#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
+#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
+#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
+#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
+#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
+#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
+#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
+#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
+#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
+#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
+#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
+#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
+#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
+#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
+#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
+#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
+
+/* End of channnel array defines of ETHER */
+
+
+#define ETHEREDSR0 ETHER.EDSR0
+#define ETHERTDLAR0 ETHER.TDLAR0
+#define ETHERTDFAR0 ETHER.TDFAR0
+#define ETHERTDFXR0 ETHER.TDFXR0
+#define ETHERTDFFR0 ETHER.TDFFR0
+#define ETHERRDLAR0 ETHER.RDLAR0
+#define ETHERRDFAR0 ETHER.RDFAR0
+#define ETHERRDFXR0 ETHER.RDFXR0
+#define ETHERRDFFR0 ETHER.RDFFR0
+#define ETHEREDMR0 ETHER.EDMR0
+#define ETHEREDTRR0 ETHER.EDTRR0
+#define ETHEREDRRR0 ETHER.EDRRR0
+#define ETHEREESR0 ETHER.EESR0
+#define ETHEREESIPR0 ETHER.EESIPR0
+#define ETHERTRSCER0 ETHER.TRSCER0
+#define ETHERRMFCR0 ETHER.RMFCR0
+#define ETHERTFTR0 ETHER.TFTR0
+#define ETHERFDR0 ETHER.FDR0
+#define ETHERRMCR0 ETHER.RMCR0
+#define ETHERRPADIR0 ETHER.RPADIR0
+#define ETHERFCFTR0 ETHER.FCFTR0
+#define ETHERCSMR ETHER.CSMR
+#define ETHERCSSBM ETHER.CSSBM
+#define ETHERCSSMR ETHER.CSSMR
+#define ETHERECMR0 ETHER.ECMR0
+#define ETHERRFLR0 ETHER.RFLR0
+#define ETHERECSR0 ETHER.ECSR0
+#define ETHERECSIPR0 ETHER.ECSIPR0
+#define ETHERPIR0 ETHER.PIR0
+#define ETHERAPR0 ETHER.APR0
+#define ETHERMPR0 ETHER.MPR0
+#define ETHERPFTCR0 ETHER.PFTCR0
+#define ETHERPFRCR0 ETHER.PFRCR0
+#define ETHERTPAUSER0 ETHER.TPAUSER0
+#define ETHERMAHR0 ETHER.MAHR0
+#define ETHERMALR0 ETHER.MALR0
+#define ETHERCEFCR0 ETHER.CEFCR0
+#define ETHERFRECR0 ETHER.FRECR0
+#define ETHERTSFRCR0 ETHER.TSFRCR0
+#define ETHERTLFRCR0 ETHER.TLFRCR0
+#define ETHERRFCR0 ETHER.RFCR0
+#define ETHERMAFCR0 ETHER.MAFCR0
+#define ETHERARSTR ETHER.ARSTR
+#define ETHERTSU_CTRST ETHER.TSU_CTRST
+#define ETHERTSU_VTAG0 ETHER.TSU_VTAG0
+#define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY
+#define ETHERTSU_TEN ETHER.TSU_TEN
+#define ETHERTXNLCR0 ETHER.TXNLCR0
+#define ETHERTXALCR0 ETHER.TXALCR0
+#define ETHERRXNLCR0 ETHER.RXNLCR0
+#define ETHERRXALCR0 ETHER.RXALCR0
+#define ETHERTSU_ADRH0 ETHER.TSU_ADRH0
+#define ETHERTSU_ADRL0 ETHER.TSU_ADRL0
+#define ETHERTSU_ADRH1 ETHER.TSU_ADRH1
+#define ETHERTSU_ADRL1 ETHER.TSU_ADRL1
+#define ETHERTSU_ADRH2 ETHER.TSU_ADRH2
+#define ETHERTSU_ADRL2 ETHER.TSU_ADRL2
+#define ETHERTSU_ADRH3 ETHER.TSU_ADRH3
+#define ETHERTSU_ADRL3 ETHER.TSU_ADRL3
+#define ETHERTSU_ADRH4 ETHER.TSU_ADRH4
+#define ETHERTSU_ADRL4 ETHER.TSU_ADRL4
+#define ETHERTSU_ADRH5 ETHER.TSU_ADRH5
+#define ETHERTSU_ADRL5 ETHER.TSU_ADRL5
+#define ETHERTSU_ADRH6 ETHER.TSU_ADRH6
+#define ETHERTSU_ADRL6 ETHER.TSU_ADRL6
+#define ETHERTSU_ADRH7 ETHER.TSU_ADRH7
+#define ETHERTSU_ADRL7 ETHER.TSU_ADRL7
+#define ETHERTSU_ADRH8 ETHER.TSU_ADRH8
+#define ETHERTSU_ADRL8 ETHER.TSU_ADRL8
+#define ETHERTSU_ADRH9 ETHER.TSU_ADRH9
+#define ETHERTSU_ADRL9 ETHER.TSU_ADRL9
+#define ETHERTSU_ADRH10 ETHER.TSU_ADRH10
+#define ETHERTSU_ADRL10 ETHER.TSU_ADRL10
+#define ETHERTSU_ADRH11 ETHER.TSU_ADRH11
+#define ETHERTSU_ADRL11 ETHER.TSU_ADRL11
+#define ETHERTSU_ADRH12 ETHER.TSU_ADRH12
+#define ETHERTSU_ADRL12 ETHER.TSU_ADRL12
+#define ETHERTSU_ADRH13 ETHER.TSU_ADRH13
+#define ETHERTSU_ADRL13 ETHER.TSU_ADRL13
+#define ETHERTSU_ADRH14 ETHER.TSU_ADRH14
+#define ETHERTSU_ADRL14 ETHER.TSU_ADRL14
+#define ETHERTSU_ADRH15 ETHER.TSU_ADRH15
+#define ETHERTSU_ADRL15 ETHER.TSU_ADRL15
+#define ETHERTSU_ADRH16 ETHER.TSU_ADRH16
+#define ETHERTSU_ADRL16 ETHER.TSU_ADRL16
+#define ETHERTSU_ADRH17 ETHER.TSU_ADRH17
+#define ETHERTSU_ADRL17 ETHER.TSU_ADRL17
+#define ETHERTSU_ADRH18 ETHER.TSU_ADRH18
+#define ETHERTSU_ADRL18 ETHER.TSU_ADRL18
+#define ETHERTSU_ADRH19 ETHER.TSU_ADRH19
+#define ETHERTSU_ADRL19 ETHER.TSU_ADRL19
+#define ETHERTSU_ADRH20 ETHER.TSU_ADRH20
+#define ETHERTSU_ADRL20 ETHER.TSU_ADRL20
+#define ETHERTSU_ADRH21 ETHER.TSU_ADRH21
+#define ETHERTSU_ADRL21 ETHER.TSU_ADRL21
+#define ETHERTSU_ADRH22 ETHER.TSU_ADRH22
+#define ETHERTSU_ADRL22 ETHER.TSU_ADRL22
+#define ETHERTSU_ADRH23 ETHER.TSU_ADRH23
+#define ETHERTSU_ADRL23 ETHER.TSU_ADRL23
+#define ETHERTSU_ADRH24 ETHER.TSU_ADRH24
+#define ETHERTSU_ADRL24 ETHER.TSU_ADRL24
+#define ETHERTSU_ADRH25 ETHER.TSU_ADRH25
+#define ETHERTSU_ADRL25 ETHER.TSU_ADRL25
+#define ETHERTSU_ADRH26 ETHER.TSU_ADRH26
+#define ETHERTSU_ADRL26 ETHER.TSU_ADRL26
+#define ETHERTSU_ADRH27 ETHER.TSU_ADRH27
+#define ETHERTSU_ADRL27 ETHER.TSU_ADRL27
+#define ETHERTSU_ADRH28 ETHER.TSU_ADRH28
+#define ETHERTSU_ADRL28 ETHER.TSU_ADRL28
+#define ETHERTSU_ADRH29 ETHER.TSU_ADRH29
+#define ETHERTSU_ADRL29 ETHER.TSU_ADRL29
+#define ETHERTSU_ADRH30 ETHER.TSU_ADRH30
+#define ETHERTSU_ADRL30 ETHER.TSU_ADRL30
+#define ETHERTSU_ADRH31 ETHER.TSU_ADRH31
+#define ETHERTSU_ADRL31 ETHER.TSU_ADRL31
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,73 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : flctl_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef FLCTL_IODEFINE_H
+#define FLCTL_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_flctl
+{ /* FLCTL */
+ volatile uint32_t FLCMNCR; /* FLCMNCR */
+ volatile uint32_t FLCMDCR; /* FLCMDCR */
+ volatile uint32_t FLCMCDR; /* FLCMCDR */
+ volatile uint32_t FLADR; /* FLADR */
+ volatile uint32_t FLDATAR; /* FLDATAR */
+ volatile uint32_t FLDTCNTR; /* FLDTCNTR */
+ volatile uint32_t FLINTDMACR; /* FLINTDMACR */
+ volatile uint32_t FLBSYTMR; /* FLBSYTMR */
+ volatile uint32_t FLBSYCNT; /* FLBSYCNT */
+ volatile uint8_t dummy555[8]; /* */
+ volatile uint8_t FLTRCR; /* FLTRCR */
+ volatile uint8_t dummy556[15]; /* */
+ volatile uint32_t FLADR2; /* FLADR2 */
+ volatile uint8_t dummy557[16]; /* */
+ volatile uint32_t FLDTFIFO; /* FLDTFIFO */
+ volatile uint8_t dummy558[12]; /* */
+ volatile uint32_t FLECFIFO; /* FLECFIFO */
+};
+
+
+#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */
+
+
+#define FLCTLFLCMNCR FLCTL.FLCMNCR
+#define FLCTLFLCMDCR FLCTL.FLCMDCR
+#define FLCTLFLCMCDR FLCTL.FLCMCDR
+#define FLCTLFLADR FLCTL.FLADR
+#define FLCTLFLDATAR FLCTL.FLDATAR
+#define FLCTLFLDTCNTR FLCTL.FLDTCNTR
+#define FLCTLFLINTDMACR FLCTL.FLINTDMACR
+#define FLCTLFLBSYTMR FLCTL.FLBSYTMR
+#define FLCTLFLBSYCNT FLCTL.FLBSYCNT
+#define FLCTLFLTRCR FLCTL.FLTRCR
+#define FLCTLFLADR2 FLCTL.FLADR2
+#define FLCTLFLDTFIFO FLCTL.FLDTFIFO
+#define FLCTLFLECFIFO FLCTL.FLECFIFO
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,1075 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : gpio_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef GPIO_IODEFINE_H
+#define GPIO_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_gpio
+{ /* GPIO */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P1; /* P1 */
+ volatile uint8_t dummy348[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P2; /* P2 */
+ volatile uint8_t dummy349[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P3; /* P3 */
+ volatile uint8_t dummy350[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P4; /* P4 */
+ volatile uint8_t dummy351[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P5; /* P5 */
+ volatile uint8_t dummy352[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P6; /* P6 */
+ volatile uint8_t dummy353[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P7; /* P7 */
+ volatile uint8_t dummy354[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P8; /* P8 */
+ volatile uint8_t dummy355[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P9; /* P9 */
+ volatile uint8_t dummy356[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P10; /* P10 */
+ volatile uint8_t dummy357[2]; /* */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+ volatile uint16_t P11; /* P11 */
+ volatile uint8_t dummy3580[2]; /* */
+/* end of struct st_gpio_from_p1 */
+ volatile uint8_t dummy3581[212]; /* */
+#define GPIO_PSRn_COUNT 11
+ volatile uint32_t PSR1; /* PSR1 */
+ volatile uint32_t PSR2; /* PSR2 */
+ volatile uint32_t PSR3; /* PSR3 */
+ volatile uint32_t PSR4; /* PSR4 */
+ volatile uint32_t PSR5; /* PSR5 */
+ volatile uint32_t PSR6; /* PSR6 */
+ volatile uint32_t PSR7; /* PSR7 */
+ volatile uint32_t PSR8; /* PSR8 */
+ volatile uint32_t PSR9; /* PSR9 */
+ volatile uint32_t PSR10; /* PSR10 */
+ volatile uint32_t PSR11; /* PSR11 */
+ volatile uint8_t dummy359[208]; /* */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR0; /* PPR0 */
+ volatile uint8_t dummy360[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR1; /* PPR1 */
+ volatile uint8_t dummy361[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR2; /* PPR2 */
+ volatile uint8_t dummy362[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR3; /* PPR3 */
+ volatile uint8_t dummy363[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR4; /* PPR4 */
+ volatile uint8_t dummy364[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR5; /* PPR5 */
+ volatile uint8_t dummy365[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR6; /* PPR6 */
+ volatile uint8_t dummy366[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR7; /* PPR7 */
+ volatile uint8_t dummy367[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR8; /* PPR8 */
+ volatile uint8_t dummy368[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR9; /* PPR9 */
+ volatile uint8_t dummy369[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR10; /* PPR10 */
+ volatile uint8_t dummy370[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+ volatile uint16_t PPR11; /* PPR11 */
+ volatile uint8_t dummy3710[2]; /* */
+/* end of struct st_gpio_from_ppr0 */
+ volatile uint8_t dummy3711[212]; /* */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM1; /* PM1 */
+ volatile uint8_t dummy372[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM2; /* PM2 */
+ volatile uint8_t dummy373[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM3; /* PM3 */
+ volatile uint8_t dummy374[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM4; /* PM4 */
+ volatile uint8_t dummy375[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM5; /* PM5 */
+ volatile uint8_t dummy376[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM6; /* PM6 */
+ volatile uint8_t dummy377[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM7; /* PM7 */
+ volatile uint8_t dummy378[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM8; /* PM8 */
+ volatile uint8_t dummy379[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM9; /* PM9 */
+ volatile uint8_t dummy380[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM10; /* PM10 */
+ volatile uint8_t dummy381[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+ volatile uint16_t PM11; /* PM11 */
+ volatile uint8_t dummy3820[2]; /* */
+/* end of struct st_gpio_from_pm1 */
+ volatile uint8_t dummy3821[208]; /* */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC0; /* PMC0 */
+ volatile uint8_t dummy383[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC1; /* PMC1 */
+ volatile uint8_t dummy384[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC2; /* PMC2 */
+ volatile uint8_t dummy385[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC3; /* PMC3 */
+ volatile uint8_t dummy386[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC4; /* PMC4 */
+ volatile uint8_t dummy387[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC5; /* PMC5 */
+ volatile uint8_t dummy388[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC6; /* PMC6 */
+ volatile uint8_t dummy389[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC7; /* PMC7 */
+ volatile uint8_t dummy390[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC8; /* PMC8 */
+ volatile uint8_t dummy391[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC9; /* PMC9 */
+ volatile uint8_t dummy392[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC10; /* PMC10 */
+ volatile uint8_t dummy393[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+ volatile uint16_t PMC11; /* PMC11 */
+ volatile uint8_t dummy3940[2]; /* */
+/* end of struct st_gpio_from_pmc0 */
+ volatile uint8_t dummy3941[212]; /* */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC1; /* PFC1 */
+ volatile uint8_t dummy395[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC2; /* PFC2 */
+ volatile uint8_t dummy396[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC3; /* PFC3 */
+ volatile uint8_t dummy397[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC4; /* PFC4 */
+ volatile uint8_t dummy398[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC5; /* PFC5 */
+ volatile uint8_t dummy399[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC6; /* PFC6 */
+ volatile uint8_t dummy400[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC7; /* PFC7 */
+ volatile uint8_t dummy401[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC8; /* PFC8 */
+ volatile uint8_t dummy402[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC9; /* PFC9 */
+ volatile uint8_t dummy403[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC10; /* PFC10 */
+ volatile uint8_t dummy404[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+ volatile uint16_t PFC11; /* PFC11 */
+ volatile uint8_t dummy4050[2]; /* */
+/* end of struct st_gpio_from_pfc1 */
+ volatile uint8_t dummy4051[212]; /* */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE1; /* PFCE1 */
+ volatile uint8_t dummy406[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE2; /* PFCE2 */
+ volatile uint8_t dummy407[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE3; /* PFCE3 */
+ volatile uint8_t dummy408[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE4; /* PFCE4 */
+ volatile uint8_t dummy409[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE5; /* PFCE5 */
+ volatile uint8_t dummy410[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE6; /* PFCE6 */
+ volatile uint8_t dummy411[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE7; /* PFCE7 */
+ volatile uint8_t dummy412[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE8; /* PFCE8 */
+ volatile uint8_t dummy413[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE9; /* PFCE9 */
+ volatile uint8_t dummy414[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE10; /* PFCE10 */
+ volatile uint8_t dummy415[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+ volatile uint16_t PFCE11; /* PFCE11 */
+ volatile uint8_t dummy4160[2]; /* */
+/* end of struct st_gpio_from_pfce1 */
+ volatile uint8_t dummy4161[212]; /* */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT1; /* PNOT1 */
+ volatile uint8_t dummy417[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT2; /* PNOT2 */
+ volatile uint8_t dummy418[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT3; /* PNOT3 */
+ volatile uint8_t dummy419[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT4; /* PNOT4 */
+ volatile uint8_t dummy420[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT5; /* PNOT5 */
+ volatile uint8_t dummy421[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT6; /* PNOT6 */
+ volatile uint8_t dummy422[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT7; /* PNOT7 */
+ volatile uint8_t dummy423[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT8; /* PNOT8 */
+ volatile uint8_t dummy424[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT9; /* PNOT9 */
+ volatile uint8_t dummy425[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT10; /* PNOT10 */
+ volatile uint8_t dummy426[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+ volatile uint16_t PNOT11; /* PNOT11 */
+ volatile uint8_t dummy4270[2]; /* */
+/* end of struct st_gpio_from_pnot1 */
+ volatile uint8_t dummy4271[212]; /* */
+#define GPIO_PMSRn_COUNT 11
+ volatile uint32_t PMSR1; /* PMSR1 */
+ volatile uint32_t PMSR2; /* PMSR2 */
+ volatile uint32_t PMSR3; /* PMSR3 */
+ volatile uint32_t PMSR4; /* PMSR4 */
+ volatile uint32_t PMSR5; /* PMSR5 */
+ volatile uint32_t PMSR6; /* PMSR6 */
+ volatile uint32_t PMSR7; /* PMSR7 */
+ volatile uint32_t PMSR8; /* PMSR8 */
+ volatile uint32_t PMSR9; /* PMSR9 */
+ volatile uint32_t PMSR10; /* PMSR10 */
+ volatile uint32_t PMSR11; /* PMSR11 */
+ volatile uint8_t dummy428[208]; /* */
+#define GPIO_PMCSRn_COUNT 12
+ volatile uint32_t PMCSR0; /* PMCSR0 */
+ volatile uint32_t PMCSR1; /* PMCSR1 */
+ volatile uint32_t PMCSR2; /* PMCSR2 */
+ volatile uint32_t PMCSR3; /* PMCSR3 */
+ volatile uint32_t PMCSR4; /* PMCSR4 */
+ volatile uint32_t PMCSR5; /* PMCSR5 */
+ volatile uint32_t PMCSR6; /* PMCSR6 */
+ volatile uint32_t PMCSR7; /* PMCSR7 */
+ volatile uint32_t PMCSR8; /* PMCSR8 */
+ volatile uint32_t PMCSR9; /* PMCSR9 */
+ volatile uint32_t PMCSR10; /* PMCSR10 */
+ volatile uint32_t PMCSR11; /* PMCSR11 */
+ volatile uint8_t dummy429[212]; /* */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE1; /* PFCAE1 */
+ volatile uint8_t dummy430[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE2; /* PFCAE2 */
+ volatile uint8_t dummy431[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE3; /* PFCAE3 */
+ volatile uint8_t dummy432[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE4; /* PFCAE4 */
+ volatile uint8_t dummy433[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE5; /* PFCAE5 */
+ volatile uint8_t dummy434[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE6; /* PFCAE6 */
+ volatile uint8_t dummy435[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE7; /* PFCAE7 */
+ volatile uint8_t dummy436[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE8; /* PFCAE8 */
+ volatile uint8_t dummy437[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE9; /* PFCAE9 */
+ volatile uint8_t dummy438[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE10; /* PFCAE10 */
+ volatile uint8_t dummy439[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+ volatile uint16_t PFCAE11; /* PFCAE11 */
+ volatile uint8_t dummy4400[2]; /* */
+/* end of struct st_gpio_from_pfcae1 */
+ volatile uint8_t dummy4401[464]; /* */
+ volatile uint32_t SNCR; /* SNCR */
+ volatile uint8_t dummy441[13308]; /* */
+ volatile uint16_t PIBC0; /* PIBC0 */
+ volatile uint8_t dummy442[2]; /* */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC1; /* PIBC1 */
+ volatile uint8_t dummy443[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC2; /* PIBC2 */
+ volatile uint8_t dummy444[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC3; /* PIBC3 */
+ volatile uint8_t dummy445[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC4; /* PIBC4 */
+ volatile uint8_t dummy446[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC5; /* PIBC5 */
+ volatile uint8_t dummy447[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC6; /* PIBC6 */
+ volatile uint8_t dummy448[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC7; /* PIBC7 */
+ volatile uint8_t dummy449[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC8; /* PIBC8 */
+ volatile uint8_t dummy450[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC9; /* PIBC9 */
+ volatile uint8_t dummy451[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC10; /* PIBC10 */
+ volatile uint8_t dummy452[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+ volatile uint16_t PIBC11; /* PIBC11 */
+ volatile uint8_t dummy4530[2]; /* */
+/* end of struct st_gpio_from_pibc1 */
+ volatile uint8_t dummy4531[212]; /* */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC1; /* PBDC1 */
+ volatile uint8_t dummy454[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC2; /* PBDC2 */
+ volatile uint8_t dummy455[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC3; /* PBDC3 */
+ volatile uint8_t dummy456[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC4; /* PBDC4 */
+ volatile uint8_t dummy457[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC5; /* PBDC5 */
+ volatile uint8_t dummy458[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC6; /* PBDC6 */
+ volatile uint8_t dummy459[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC7; /* PBDC7 */
+ volatile uint8_t dummy460[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC8; /* PBDC8 */
+ volatile uint8_t dummy461[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC9; /* PBDC9 */
+ volatile uint8_t dummy462[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC10; /* PBDC10 */
+ volatile uint8_t dummy463[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+ volatile uint16_t PBDC11; /* PBDC11 */
+ volatile uint8_t dummy4640[2]; /* */
+/* end of struct st_gpio_from_pbdc1 */
+ volatile uint8_t dummy4641[212]; /* */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC1; /* PIPC1 */
+ volatile uint8_t dummy465[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC2; /* PIPC2 */
+ volatile uint8_t dummy466[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC3; /* PIPC3 */
+ volatile uint8_t dummy467[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC4; /* PIPC4 */
+ volatile uint8_t dummy468[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC5; /* PIPC5 */
+ volatile uint8_t dummy469[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC6; /* PIPC6 */
+ volatile uint8_t dummy470[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC7; /* PIPC7 */
+ volatile uint8_t dummy471[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC8; /* PIPC8 */
+ volatile uint8_t dummy472[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC9; /* PIPC9 */
+ volatile uint8_t dummy473[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC10; /* PIPC10 */
+ volatile uint8_t dummy474[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+ volatile uint16_t PIPC11; /* PIPC11 */
+ volatile uint8_t dummy4750[2]; /* */
+/* end of struct st_gpio_from_pipc1 */
+ volatile uint8_t dummy4751[2288]; /* */
+ volatile uint16_t JPPR0; /* JPPR0 */
+ volatile uint8_t dummy476[30]; /* */
+ volatile uint16_t JPMC0; /* JPMC0 */
+ volatile uint8_t dummy477[78]; /* */
+ volatile uint32_t JPMCSR0; /* JPMCSR0 */
+ volatile uint8_t dummy478[876]; /* */
+ volatile uint16_t JPIBC0; /* JPIBC0 */
+};
+
+
+struct st_gpio_from_p1
+{
+ volatile uint16_t P1; /* P1 */
+ volatile uint8_t dummy1[3]; /* */
+};
+
+
+struct st_gpio_from_ppr0
+{
+ volatile uint16_t PPR0; /* PPR0 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pm1
+{
+ volatile uint16_t PM1; /* PM1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pmc0
+{
+ volatile uint16_t PMC0; /* PMC0 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pfc1
+{
+ volatile uint16_t PFC1; /* PFC1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pfce1
+{
+ volatile uint16_t PFCE1; /* PFCE1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pnot1
+{
+ volatile uint16_t PNOT1; /* PNOT1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pfcae1
+{
+ volatile uint16_t PFCAE1; /* PFCAE1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pibc1
+{
+ volatile uint16_t PIBC1; /* PIBC1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pbdc1
+{
+ volatile uint16_t PBDC1; /* PBDC1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+struct st_gpio_from_pipc1
+{
+ volatile uint16_t PIPC1; /* PIPC1 */
+ volatile uint8_t dummy1[2]; /* */
+};
+
+
+#define GPIO (*(struct st_gpio *)0xFCFE3004uL) /* GPIO */
+
+/* Start of channnel array defines of GPIO */
+
+/* Channnel array defines of GPIO_FROM_PIPC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */
+#define GPIO_FROM_PIPC1_ARRAY_COUNT 11
+#define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \
+ &GPIO_FROM_PIPC9, &GPIO_FROM_PIPC10, &GPIO_FROM_PIPC11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PIPC1 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC1) /* GPIO_FROM_PIPC1 */
+#define GPIO_FROM_PIPC2 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC2) /* GPIO_FROM_PIPC2 */
+#define GPIO_FROM_PIPC3 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC3) /* GPIO_FROM_PIPC3 */
+#define GPIO_FROM_PIPC4 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC4) /* GPIO_FROM_PIPC4 */
+#define GPIO_FROM_PIPC5 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC5) /* GPIO_FROM_PIPC5 */
+#define GPIO_FROM_PIPC6 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC6) /* GPIO_FROM_PIPC6 */
+#define GPIO_FROM_PIPC7 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC7) /* GPIO_FROM_PIPC7 */
+#define GPIO_FROM_PIPC8 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC8) /* GPIO_FROM_PIPC8 */
+#define GPIO_FROM_PIPC9 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC9) /* GPIO_FROM_PIPC9 */
+#define GPIO_FROM_PIPC10 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC10) /* GPIO_FROM_PIPC10 */
+#define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PBDC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */
+#define GPIO_FROM_PBDC1_ARRAY_COUNT 11
+#define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \
+ &GPIO_FROM_PBDC9, &GPIO_FROM_PBDC10, &GPIO_FROM_PBDC11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PBDC1 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC1) /* GPIO_FROM_PBDC1 */
+#define GPIO_FROM_PBDC2 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC2) /* GPIO_FROM_PBDC2 */
+#define GPIO_FROM_PBDC3 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC3) /* GPIO_FROM_PBDC3 */
+#define GPIO_FROM_PBDC4 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC4) /* GPIO_FROM_PBDC4 */
+#define GPIO_FROM_PBDC5 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC5) /* GPIO_FROM_PBDC5 */
+#define GPIO_FROM_PBDC6 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC6) /* GPIO_FROM_PBDC6 */
+#define GPIO_FROM_PBDC7 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC7) /* GPIO_FROM_PBDC7 */
+#define GPIO_FROM_PBDC8 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC8) /* GPIO_FROM_PBDC8 */
+#define GPIO_FROM_PBDC9 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC9) /* GPIO_FROM_PBDC9 */
+#define GPIO_FROM_PBDC10 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC10) /* GPIO_FROM_PBDC10 */
+#define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PIBC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */
+#define GPIO_FROM_PIBC1_ARRAY_COUNT 11
+#define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, &GPIO_FROM_PIBC8, \
+ &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */
+#define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */
+#define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */
+#define GPIO_FROM_PIBC4 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC4) /* GPIO_FROM_PIBC4 */
+#define GPIO_FROM_PIBC5 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC5) /* GPIO_FROM_PIBC5 */
+#define GPIO_FROM_PIBC6 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC6) /* GPIO_FROM_PIBC6 */
+#define GPIO_FROM_PIBC7 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC7) /* GPIO_FROM_PIBC7 */
+#define GPIO_FROM_PIBC8 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC8) /* GPIO_FROM_PIBC8 */
+#define GPIO_FROM_PIBC9 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC9) /* GPIO_FROM_PIBC9 */
+#define GPIO_FROM_PIBC10 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC10) /* GPIO_FROM_PIBC10 */
+#define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PFCAE1_ARRAY */
+/*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */
+#define GPIO_FROM_PFCAE1_ARRAY_COUNT 11
+#define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \
+ &GPIO_FROM_PFCAE9, &GPIO_FROM_PFCAE10, &GPIO_FROM_PFCAE11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PFCAE1 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE1) /* GPIO_FROM_PFCAE1 */
+#define GPIO_FROM_PFCAE2 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE2) /* GPIO_FROM_PFCAE2 */
+#define GPIO_FROM_PFCAE3 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE3) /* GPIO_FROM_PFCAE3 */
+#define GPIO_FROM_PFCAE4 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE4) /* GPIO_FROM_PFCAE4 */
+#define GPIO_FROM_PFCAE5 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE5) /* GPIO_FROM_PFCAE5 */
+#define GPIO_FROM_PFCAE6 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE6) /* GPIO_FROM_PFCAE6 */
+#define GPIO_FROM_PFCAE7 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE7) /* GPIO_FROM_PFCAE7 */
+#define GPIO_FROM_PFCAE8 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE8) /* GPIO_FROM_PFCAE8 */
+#define GPIO_FROM_PFCAE9 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE9) /* GPIO_FROM_PFCAE9 */
+#define GPIO_FROM_PFCAE10 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE10) /* GPIO_FROM_PFCAE10 */
+#define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */
+
+
+/* Channnel array defines of GPIO_FROM_PNOT1_ARRAY */
+/*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */
+#define GPIO_FROM_PNOT1_ARRAY_COUNT 11
+#define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \
+ &GPIO_FROM_PNOT9, &GPIO_FROM_PNOT10, &GPIO_FROM_PNOT11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PNOT1 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT1) /* GPIO_FROM_PNOT1 */
+#define GPIO_FROM_PNOT2 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT2) /* GPIO_FROM_PNOT2 */
+#define GPIO_FROM_PNOT3 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT3) /* GPIO_FROM_PNOT3 */
+#define GPIO_FROM_PNOT4 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT4) /* GPIO_FROM_PNOT4 */
+#define GPIO_FROM_PNOT5 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT5) /* GPIO_FROM_PNOT5 */
+#define GPIO_FROM_PNOT6 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT6) /* GPIO_FROM_PNOT6 */
+#define GPIO_FROM_PNOT7 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT7) /* GPIO_FROM_PNOT7 */
+#define GPIO_FROM_PNOT8 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT8) /* GPIO_FROM_PNOT8 */
+#define GPIO_FROM_PNOT9 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT9) /* GPIO_FROM_PNOT9 */
+#define GPIO_FROM_PNOT10 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT10) /* GPIO_FROM_PNOT10 */
+#define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */
+
+
+/* Channnel array defines of GPIO_FROM_PFCE1_ARRAY */
+/*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */
+#define GPIO_FROM_PFCE1_ARRAY_COUNT 11
+#define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \
+ &GPIO_FROM_PFCE9, &GPIO_FROM_PFCE10, &GPIO_FROM_PFCE11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PFCE1 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE1) /* GPIO_FROM_PFCE1 */
+#define GPIO_FROM_PFCE2 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE2) /* GPIO_FROM_PFCE2 */
+#define GPIO_FROM_PFCE3 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE3) /* GPIO_FROM_PFCE3 */
+#define GPIO_FROM_PFCE4 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE4) /* GPIO_FROM_PFCE4 */
+#define GPIO_FROM_PFCE5 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE5) /* GPIO_FROM_PFCE5 */
+#define GPIO_FROM_PFCE6 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE6) /* GPIO_FROM_PFCE6 */
+#define GPIO_FROM_PFCE7 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE7) /* GPIO_FROM_PFCE7 */
+#define GPIO_FROM_PFCE8 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE8) /* GPIO_FROM_PFCE8 */
+#define GPIO_FROM_PFCE9 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE9) /* GPIO_FROM_PFCE9 */
+#define GPIO_FROM_PFCE10 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE10) /* GPIO_FROM_PFCE10 */
+#define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */
+
+
+/* Channnel array defines of GPIO_FROM_PFC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */
+#define GPIO_FROM_PFC1_ARRAY_COUNT 11
+#define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \
+ &GPIO_FROM_PFC9, &GPIO_FROM_PFC10, &GPIO_FROM_PFC11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PFC1 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC1) /* GPIO_FROM_PFC1 */
+#define GPIO_FROM_PFC2 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC2) /* GPIO_FROM_PFC2 */
+#define GPIO_FROM_PFC3 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC3) /* GPIO_FROM_PFC3 */
+#define GPIO_FROM_PFC4 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC4) /* GPIO_FROM_PFC4 */
+#define GPIO_FROM_PFC5 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC5) /* GPIO_FROM_PFC5 */
+#define GPIO_FROM_PFC6 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC6) /* GPIO_FROM_PFC6 */
+#define GPIO_FROM_PFC7 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC7) /* GPIO_FROM_PFC7 */
+#define GPIO_FROM_PFC8 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC8) /* GPIO_FROM_PFC8 */
+#define GPIO_FROM_PFC9 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC9) /* GPIO_FROM_PFC9 */
+#define GPIO_FROM_PFC10 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC10) /* GPIO_FROM_PFC10 */
+#define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PMC0_ARRAY */
+/*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */
+#define GPIO_FROM_PMC0_ARRAY_COUNT 12
+#define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \
+ &GPIO_FROM_PMC8, &GPIO_FROM_PMC9, &GPIO_FROM_PMC10, &GPIO_FROM_PMC11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PMC0 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC0) /* GPIO_FROM_PMC0 */
+#define GPIO_FROM_PMC1 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC1) /* GPIO_FROM_PMC1 */
+#define GPIO_FROM_PMC2 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC2) /* GPIO_FROM_PMC2 */
+#define GPIO_FROM_PMC3 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC3) /* GPIO_FROM_PMC3 */
+#define GPIO_FROM_PMC4 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC4) /* GPIO_FROM_PMC4 */
+#define GPIO_FROM_PMC5 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC5) /* GPIO_FROM_PMC5 */
+#define GPIO_FROM_PMC6 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC6) /* GPIO_FROM_PMC6 */
+#define GPIO_FROM_PMC7 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC7) /* GPIO_FROM_PMC7 */
+#define GPIO_FROM_PMC8 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC8) /* GPIO_FROM_PMC8 */
+#define GPIO_FROM_PMC9 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC9) /* GPIO_FROM_PMC9 */
+#define GPIO_FROM_PMC10 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC10) /* GPIO_FROM_PMC10 */
+#define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PM1_ARRAY */
+/*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */
+#define GPIO_FROM_PM1_ARRAY_COUNT 11
+#define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \
+ &GPIO_FROM_PM9, &GPIO_FROM_PM10, &GPIO_FROM_PM11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PM1 (*(struct st_gpio_from_pm1 *)&GPIO.PM1) /* GPIO_FROM_PM1 */
+#define GPIO_FROM_PM2 (*(struct st_gpio_from_pm1 *)&GPIO.PM2) /* GPIO_FROM_PM2 */
+#define GPIO_FROM_PM3 (*(struct st_gpio_from_pm1 *)&GPIO.PM3) /* GPIO_FROM_PM3 */
+#define GPIO_FROM_PM4 (*(struct st_gpio_from_pm1 *)&GPIO.PM4) /* GPIO_FROM_PM4 */
+#define GPIO_FROM_PM5 (*(struct st_gpio_from_pm1 *)&GPIO.PM5) /* GPIO_FROM_PM5 */
+#define GPIO_FROM_PM6 (*(struct st_gpio_from_pm1 *)&GPIO.PM6) /* GPIO_FROM_PM6 */
+#define GPIO_FROM_PM7 (*(struct st_gpio_from_pm1 *)&GPIO.PM7) /* GPIO_FROM_PM7 */
+#define GPIO_FROM_PM8 (*(struct st_gpio_from_pm1 *)&GPIO.PM8) /* GPIO_FROM_PM8 */
+#define GPIO_FROM_PM9 (*(struct st_gpio_from_pm1 *)&GPIO.PM9) /* GPIO_FROM_PM9 */
+#define GPIO_FROM_PM10 (*(struct st_gpio_from_pm1 *)&GPIO.PM10) /* GPIO_FROM_PM10 */
+#define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11) /* GPIO_FROM_PM11 */
+
+
+/* Channnel array defines of GPIO_FROM_PPR0_ARRAY */
+/*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */
+#define GPIO_FROM_PPR0_ARRAY_COUNT 12
+#define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \
+ &GPIO_FROM_PPR8, &GPIO_FROM_PPR9, &GPIO_FROM_PPR10, &GPIO_FROM_PPR11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PPR0 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR0) /* GPIO_FROM_PPR0 */
+#define GPIO_FROM_PPR1 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR1) /* GPIO_FROM_PPR1 */
+#define GPIO_FROM_PPR2 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR2) /* GPIO_FROM_PPR2 */
+#define GPIO_FROM_PPR3 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR3) /* GPIO_FROM_PPR3 */
+#define GPIO_FROM_PPR4 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR4) /* GPIO_FROM_PPR4 */
+#define GPIO_FROM_PPR5 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR5) /* GPIO_FROM_PPR5 */
+#define GPIO_FROM_PPR6 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR6) /* GPIO_FROM_PPR6 */
+#define GPIO_FROM_PPR7 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR7) /* GPIO_FROM_PPR7 */
+#define GPIO_FROM_PPR8 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR8) /* GPIO_FROM_PPR8 */
+#define GPIO_FROM_PPR9 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR9) /* GPIO_FROM_PPR9 */
+#define GPIO_FROM_PPR10 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR10) /* GPIO_FROM_PPR10 */
+#define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */
+
+
+/* Channnel array defines of GPIO_FROM_P1_ARRAY */
+/*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */
+#define GPIO_FROM_P1_ARRAY_COUNT 11
+#define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \
+ &GPIO_FROM_P9, &GPIO_FROM_P10, &GPIO_FROM_P11 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_P1 (*(struct st_gpio_from_p1 *)&GPIO.P1) /* GPIO_FROM_P1 */
+#define GPIO_FROM_P2 (*(struct st_gpio_from_p1 *)&GPIO.P2) /* GPIO_FROM_P2 */
+#define GPIO_FROM_P3 (*(struct st_gpio_from_p1 *)&GPIO.P3) /* GPIO_FROM_P3 */
+#define GPIO_FROM_P4 (*(struct st_gpio_from_p1 *)&GPIO.P4) /* GPIO_FROM_P4 */
+#define GPIO_FROM_P5 (*(struct st_gpio_from_p1 *)&GPIO.P5) /* GPIO_FROM_P5 */
+#define GPIO_FROM_P6 (*(struct st_gpio_from_p1 *)&GPIO.P6) /* GPIO_FROM_P6 */
+#define GPIO_FROM_P7 (*(struct st_gpio_from_p1 *)&GPIO.P7) /* GPIO_FROM_P7 */
+#define GPIO_FROM_P8 (*(struct st_gpio_from_p1 *)&GPIO.P8) /* GPIO_FROM_P8 */
+#define GPIO_FROM_P9 (*(struct st_gpio_from_p1 *)&GPIO.P9) /* GPIO_FROM_P9 */
+#define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10) /* GPIO_FROM_P10 */
+#define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11) /* GPIO_FROM_P11 */
+
+/* End of channnel array defines of GPIO */
+
+
+#define GPIOP1 GPIO.P1
+#define GPIOP2 GPIO.P2
+#define GPIOP3 GPIO.P3
+#define GPIOP4 GPIO.P4
+#define GPIOP5 GPIO.P5
+#define GPIOP6 GPIO.P6
+#define GPIOP7 GPIO.P7
+#define GPIOP8 GPIO.P8
+#define GPIOP9 GPIO.P9
+#define GPIOP10 GPIO.P10
+#define GPIOP11 GPIO.P11
+#define GPIOPSR1 GPIO.PSR1
+#define GPIOPSR2 GPIO.PSR2
+#define GPIOPSR3 GPIO.PSR3
+#define GPIOPSR4 GPIO.PSR4
+#define GPIOPSR5 GPIO.PSR5
+#define GPIOPSR6 GPIO.PSR6
+#define GPIOPSR7 GPIO.PSR7
+#define GPIOPSR8 GPIO.PSR8
+#define GPIOPSR9 GPIO.PSR9
+#define GPIOPSR10 GPIO.PSR10
+#define GPIOPSR11 GPIO.PSR11
+#define GPIOPPR0 GPIO.PPR0
+#define GPIOPPR1 GPIO.PPR1
+#define GPIOPPR2 GPIO.PPR2
+#define GPIOPPR3 GPIO.PPR3
+#define GPIOPPR4 GPIO.PPR4
+#define GPIOPPR5 GPIO.PPR5
+#define GPIOPPR6 GPIO.PPR6
+#define GPIOPPR7 GPIO.PPR7
+#define GPIOPPR8 GPIO.PPR8
+#define GPIOPPR9 GPIO.PPR9
+#define GPIOPPR10 GPIO.PPR10
+#define GPIOPPR11 GPIO.PPR11
+#define GPIOPM1 GPIO.PM1
+#define GPIOPM2 GPIO.PM2
+#define GPIOPM3 GPIO.PM3
+#define GPIOPM4 GPIO.PM4
+#define GPIOPM5 GPIO.PM5
+#define GPIOPM6 GPIO.PM6
+#define GPIOPM7 GPIO.PM7
+#define GPIOPM8 GPIO.PM8
+#define GPIOPM9 GPIO.PM9
+#define GPIOPM10 GPIO.PM10
+#define GPIOPM11 GPIO.PM11
+#define GPIOPMC0 GPIO.PMC0
+#define GPIOPMC1 GPIO.PMC1
+#define GPIOPMC2 GPIO.PMC2
+#define GPIOPMC3 GPIO.PMC3
+#define GPIOPMC4 GPIO.PMC4
+#define GPIOPMC5 GPIO.PMC5
+#define GPIOPMC6 GPIO.PMC6
+#define GPIOPMC7 GPIO.PMC7
+#define GPIOPMC8 GPIO.PMC8
+#define GPIOPMC9 GPIO.PMC9
+#define GPIOPMC10 GPIO.PMC10
+#define GPIOPMC11 GPIO.PMC11
+#define GPIOPFC1 GPIO.PFC1
+#define GPIOPFC2 GPIO.PFC2
+#define GPIOPFC3 GPIO.PFC3
+#define GPIOPFC4 GPIO.PFC4
+#define GPIOPFC5 GPIO.PFC5
+#define GPIOPFC6 GPIO.PFC6
+#define GPIOPFC7 GPIO.PFC7
+#define GPIOPFC8 GPIO.PFC8
+#define GPIOPFC9 GPIO.PFC9
+#define GPIOPFC10 GPIO.PFC10
+#define GPIOPFC11 GPIO.PFC11
+#define GPIOPFCE1 GPIO.PFCE1
+#define GPIOPFCE2 GPIO.PFCE2
+#define GPIOPFCE3 GPIO.PFCE3
+#define GPIOPFCE4 GPIO.PFCE4
+#define GPIOPFCE5 GPIO.PFCE5
+#define GPIOPFCE6 GPIO.PFCE6
+#define GPIOPFCE7 GPIO.PFCE7
+#define GPIOPFCE8 GPIO.PFCE8
+#define GPIOPFCE9 GPIO.PFCE9
+#define GPIOPFCE10 GPIO.PFCE10
+#define GPIOPFCE11 GPIO.PFCE11
+#define GPIOPNOT1 GPIO.PNOT1
+#define GPIOPNOT2 GPIO.PNOT2
+#define GPIOPNOT3 GPIO.PNOT3
+#define GPIOPNOT4 GPIO.PNOT4
+#define GPIOPNOT5 GPIO.PNOT5
+#define GPIOPNOT6 GPIO.PNOT6
+#define GPIOPNOT7 GPIO.PNOT7
+#define GPIOPNOT8 GPIO.PNOT8
+#define GPIOPNOT9 GPIO.PNOT9
+#define GPIOPNOT10 GPIO.PNOT10
+#define GPIOPNOT11 GPIO.PNOT11
+#define GPIOPMSR1 GPIO.PMSR1
+#define GPIOPMSR2 GPIO.PMSR2
+#define GPIOPMSR3 GPIO.PMSR3
+#define GPIOPMSR4 GPIO.PMSR4
+#define GPIOPMSR5 GPIO.PMSR5
+#define GPIOPMSR6 GPIO.PMSR6
+#define GPIOPMSR7 GPIO.PMSR7
+#define GPIOPMSR8 GPIO.PMSR8
+#define GPIOPMSR9 GPIO.PMSR9
+#define GPIOPMSR10 GPIO.PMSR10
+#define GPIOPMSR11 GPIO.PMSR11
+#define GPIOPMCSR0 GPIO.PMCSR0
+#define GPIOPMCSR1 GPIO.PMCSR1
+#define GPIOPMCSR2 GPIO.PMCSR2
+#define GPIOPMCSR3 GPIO.PMCSR3
+#define GPIOPMCSR4 GPIO.PMCSR4
+#define GPIOPMCSR5 GPIO.PMCSR5
+#define GPIOPMCSR6 GPIO.PMCSR6
+#define GPIOPMCSR7 GPIO.PMCSR7
+#define GPIOPMCSR8 GPIO.PMCSR8
+#define GPIOPMCSR9 GPIO.PMCSR9
+#define GPIOPMCSR10 GPIO.PMCSR10
+#define GPIOPMCSR11 GPIO.PMCSR11
+#define GPIOPFCAE1 GPIO.PFCAE1
+#define GPIOPFCAE2 GPIO.PFCAE2
+#define GPIOPFCAE3 GPIO.PFCAE3
+#define GPIOPFCAE4 GPIO.PFCAE4
+#define GPIOPFCAE5 GPIO.PFCAE5
+#define GPIOPFCAE6 GPIO.PFCAE6
+#define GPIOPFCAE7 GPIO.PFCAE7
+#define GPIOPFCAE8 GPIO.PFCAE8
+#define GPIOPFCAE9 GPIO.PFCAE9
+#define GPIOPFCAE10 GPIO.PFCAE10
+#define GPIOPFCAE11 GPIO.PFCAE11
+#define GPIOSNCR GPIO.SNCR
+#define GPIOPIBC0 GPIO.PIBC0
+#define GPIOPIBC1 GPIO.PIBC1
+#define GPIOPIBC2 GPIO.PIBC2
+#define GPIOPIBC3 GPIO.PIBC3
+#define GPIOPIBC4 GPIO.PIBC4
+#define GPIOPIBC5 GPIO.PIBC5
+#define GPIOPIBC6 GPIO.PIBC6
+#define GPIOPIBC7 GPIO.PIBC7
+#define GPIOPIBC8 GPIO.PIBC8
+#define GPIOPIBC9 GPIO.PIBC9
+#define GPIOPIBC10 GPIO.PIBC10
+#define GPIOPIBC11 GPIO.PIBC11
+#define GPIOPBDC1 GPIO.PBDC1
+#define GPIOPBDC2 GPIO.PBDC2
+#define GPIOPBDC3 GPIO.PBDC3
+#define GPIOPBDC4 GPIO.PBDC4
+#define GPIOPBDC5 GPIO.PBDC5
+#define GPIOPBDC6 GPIO.PBDC6
+#define GPIOPBDC7 GPIO.PBDC7
+#define GPIOPBDC8 GPIO.PBDC8
+#define GPIOPBDC9 GPIO.PBDC9
+#define GPIOPBDC10 GPIO.PBDC10
+#define GPIOPBDC11 GPIO.PBDC11
+#define GPIOPIPC1 GPIO.PIPC1
+#define GPIOPIPC2 GPIO.PIPC2
+#define GPIOPIPC3 GPIO.PIPC3
+#define GPIOPIPC4 GPIO.PIPC4
+#define GPIOPIPC5 GPIO.PIPC5
+#define GPIOPIPC6 GPIO.PIPC6
+#define GPIOPIPC7 GPIO.PIPC7
+#define GPIOPIPC8 GPIO.PIPC8
+#define GPIOPIPC9 GPIO.PIPC9
+#define GPIOPIPC10 GPIO.PIPC10
+#define GPIOPIPC11 GPIO.PIPC11
+#define GPIOJPPR0 GPIO.JPPR0
+#define GPIOJPMC0 GPIO.JPMC0
+#define GPIOJPMCSR0 GPIO.JPMCSR0
+#define GPIOJPIBC0 GPIO.JPIBC0
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,120 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ieb_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef IEB_IODEFINE_H
+#define IEB_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ieb
+{ /* IEB */
+ volatile uint8_t B0BCR; /* B0BCR */
+ volatile uint8_t dummy495[3]; /* */
+ volatile uint8_t B0PSR; /* B0PSR */
+ volatile uint8_t dummy496[3]; /* */
+ volatile uint16_t B0UAR; /* B0UAR */
+ volatile uint8_t dummy497[2]; /* */
+ volatile uint16_t B0SAR; /* B0SAR */
+ volatile uint8_t dummy498[2]; /* */
+ volatile uint16_t B0PAR; /* B0PAR */
+ volatile uint8_t dummy499[2]; /* */
+ volatile uint16_t B0RSA; /* B0RSA */
+ volatile uint8_t dummy500[2]; /* */
+ volatile uint8_t B0CDR; /* B0CDR */
+ volatile uint8_t dummy501[3]; /* */
+ volatile uint8_t B0TCD; /* B0TCD */
+ volatile uint8_t dummy502[3]; /* */
+ volatile uint8_t B0RCD; /* B0RCD */
+ volatile uint8_t dummy503[3]; /* */
+ volatile uint8_t B0DLR; /* B0DLR */
+ volatile uint8_t dummy504[3]; /* */
+ volatile uint8_t B0TDL; /* B0TDL */
+ volatile uint8_t dummy505[3]; /* */
+ volatile uint8_t B0RDL; /* B0RDL */
+ volatile uint8_t dummy506[3]; /* */
+ volatile uint8_t B0CKS; /* B0CKS */
+ volatile uint8_t dummy507[3]; /* */
+ volatile uint8_t B0TMS; /* B0TMS */
+ volatile uint8_t dummy508[3]; /* */
+ volatile uint8_t B0PCR; /* B0PCR */
+ volatile uint8_t dummy509[3]; /* */
+ volatile uint16_t B0BSR; /* B0BSR */
+ volatile uint8_t dummy510[2]; /* */
+ volatile uint8_t B0SSR; /* B0SSR */
+ volatile uint8_t dummy511[3]; /* */
+ volatile uint8_t B0USR; /* B0USR */
+ volatile uint8_t dummy512[3]; /* */
+ volatile uint8_t B0ISR; /* B0ISR */
+ volatile uint8_t dummy513[3]; /* */
+ volatile uint8_t B0ESR; /* B0ESR */
+ volatile uint8_t dummy514[3]; /* */
+ volatile uint8_t B0FSR; /* B0FSR */
+ volatile uint8_t dummy515[3]; /* */
+ volatile uint8_t B0SCR; /* B0SCR */
+ volatile uint8_t dummy516[3]; /* */
+ volatile uint8_t B0CCR; /* B0CCR */
+ volatile uint8_t dummy517[3]; /* */
+ volatile uint8_t B0STC0; /* B0STC0 */
+ volatile uint8_t dummy518[3]; /* */
+ volatile uint8_t B0STC1; /* B0STC1 */
+ volatile uint8_t dummy519[3]; /* */
+ volatile uint8_t B0DR; /* B0DR */
+};
+
+
+#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */
+
+
+#define IEBB0BCR IEB.B0BCR
+#define IEBB0PSR IEB.B0PSR
+#define IEBB0UAR IEB.B0UAR
+#define IEBB0SAR IEB.B0SAR
+#define IEBB0PAR IEB.B0PAR
+#define IEBB0RSA IEB.B0RSA
+#define IEBB0CDR IEB.B0CDR
+#define IEBB0TCD IEB.B0TCD
+#define IEBB0RCD IEB.B0RCD
+#define IEBB0DLR IEB.B0DLR
+#define IEBB0TDL IEB.B0TDL
+#define IEBB0RDL IEB.B0RDL
+#define IEBB0CKS IEB.B0CKS
+#define IEBB0TMS IEB.B0TMS
+#define IEBB0PCR IEB.B0PCR
+#define IEBB0BSR IEB.B0BSR
+#define IEBB0SSR IEB.B0SSR
+#define IEBB0USR IEB.B0USR
+#define IEBB0ISR IEB.B0ISR
+#define IEBB0ESR IEB.B0ESR
+#define IEBB0FSR IEB.B0FSR
+#define IEBB0SCR IEB.B0SCR
+#define IEBB0CCR IEB.B0CCR
+#define IEBB0STC0 IEB.B0STC0
+#define IEBB0STC1 IEB.B0STC1
+#define IEBB0DR IEB.B0DR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,93 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : inb_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef INB_IODEFINE_H
+#define INB_IODEFINE_H
+
+struct st_inb
+{ /* INB */
+ volatile uint32_t RMPR; /* RMPR */
+#define INB_AXIBUSCTLn_COUNT 11
+ volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */
+ volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */
+ volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */
+ volatile uint32_t AXIBUSCTL3; /* AXIBUSCTL3 */
+ volatile uint32_t AXIBUSCTL4; /* AXIBUSCTL4 */
+ volatile uint32_t AXIBUSCTL5; /* AXIBUSCTL5 */
+ volatile uint32_t AXIBUSCTL6; /* AXIBUSCTL6 */
+ volatile uint32_t AXIBUSCTL7; /* AXIBUSCTL7 */
+ volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */
+ volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */
+ volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */
+#define INB_AXIRERRCTLn_COUNT 4
+ volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */
+ volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */
+ volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */
+ volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */
+#define INB_AXIRERRSTn_COUNT 4
+ volatile uint32_t AXIRERRST0; /* AXIRERRST0 */
+ volatile uint32_t AXIRERRST1; /* AXIRERRST1 */
+ volatile uint32_t AXIRERRST2; /* AXIRERRST2 */
+ volatile uint32_t AXIRERRST3; /* AXIRERRST3 */
+#define INB_AXIRERRCLRn_COUNT 4
+ volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */
+ volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */
+ volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */
+ volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */
+};
+
+
+#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */
+
+
+#define INBRMPR INB.RMPR
+#define INBAXIBUSCTL0 INB.AXIBUSCTL0
+#define INBAXIBUSCTL1 INB.AXIBUSCTL1
+#define INBAXIBUSCTL2 INB.AXIBUSCTL2
+#define INBAXIBUSCTL3 INB.AXIBUSCTL3
+#define INBAXIBUSCTL4 INB.AXIBUSCTL4
+#define INBAXIBUSCTL5 INB.AXIBUSCTL5
+#define INBAXIBUSCTL6 INB.AXIBUSCTL6
+#define INBAXIBUSCTL7 INB.AXIBUSCTL7
+#define INBAXIBUSCTL8 INB.AXIBUSCTL8
+#define INBAXIBUSCTL9 INB.AXIBUSCTL9
+#define INBAXIBUSCTL10 INB.AXIBUSCTL10
+#define INBAXIRERRCTL0 INB.AXIRERRCTL0
+#define INBAXIRERRCTL1 INB.AXIRERRCTL1
+#define INBAXIRERRCTL2 INB.AXIRERRCTL2
+#define INBAXIRERRCTL3 INB.AXIRERRCTL3
+#define INBAXIRERRST0 INB.AXIRERRST0
+#define INBAXIRERRST1 INB.AXIRERRST1
+#define INBAXIRERRST2 INB.AXIRERRST2
+#define INBAXIRERRST3 INB.AXIRERRST3
+#define INBAXIRERRCLR0 INB.AXIRERRCLR0
+#define INBAXIRERRCLR1 INB.AXIRERRCLR1
+#define INBAXIRERRCLR2 INB.AXIRERRCLR2
+#define INBAXIRERRCLR3 INB.AXIRERRCLR3
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,1027 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : intc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef INTC_IODEFINE_H
+#define INTC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_intc
+{ /* INTC */
+ volatile uint32_t ICDDCR; /* ICDDCR */
+ volatile uint32_t ICDICTR; /* ICDICTR */
+ volatile uint32_t ICDIIDR; /* ICDIIDR */
+ volatile uint8_t dummy193[116]; /* */
+#define INTC_ICDISR0_COUNT 19
+ volatile uint32_t ICDISR0; /* ICDISR0 */
+ volatile uint32_t ICDISR1; /* ICDISR1 */
+ volatile uint32_t ICDISR2; /* ICDISR2 */
+ volatile uint32_t ICDISR3; /* ICDISR3 */
+ volatile uint32_t ICDISR4; /* ICDISR4 */
+ volatile uint32_t ICDISR5; /* ICDISR5 */
+ volatile uint32_t ICDISR6; /* ICDISR6 */
+ volatile uint32_t ICDISR7; /* ICDISR7 */
+ volatile uint32_t ICDISR8; /* ICDISR8 */
+ volatile uint32_t ICDISR9; /* ICDISR9 */
+ volatile uint32_t ICDISR10; /* ICDISR10 */
+ volatile uint32_t ICDISR11; /* ICDISR11 */
+ volatile uint32_t ICDISR12; /* ICDISR12 */
+ volatile uint32_t ICDISR13; /* ICDISR13 */
+ volatile uint32_t ICDISR14; /* ICDISR14 */
+ volatile uint32_t ICDISR15; /* ICDISR15 */
+ volatile uint32_t ICDISR16; /* ICDISR16 */
+ volatile uint32_t ICDISR17; /* ICDISR17 */
+ volatile uint32_t ICDISR18; /* ICDISR18 */
+ volatile uint8_t dummy194[52]; /* */
+#define INTC_ICDISER0_COUNT 19
+ volatile uint32_t ICDISER0; /* ICDISER0 */
+ volatile uint32_t ICDISER1; /* ICDISER1 */
+ volatile uint32_t ICDISER2; /* ICDISER2 */
+ volatile uint32_t ICDISER3; /* ICDISER3 */
+ volatile uint32_t ICDISER4; /* ICDISER4 */
+ volatile uint32_t ICDISER5; /* ICDISER5 */
+ volatile uint32_t ICDISER6; /* ICDISER6 */
+ volatile uint32_t ICDISER7; /* ICDISER7 */
+ volatile uint32_t ICDISER8; /* ICDISER8 */
+ volatile uint32_t ICDISER9; /* ICDISER9 */
+ volatile uint32_t ICDISER10; /* ICDISER10 */
+ volatile uint32_t ICDISER11; /* ICDISER11 */
+ volatile uint32_t ICDISER12; /* ICDISER12 */
+ volatile uint32_t ICDISER13; /* ICDISER13 */
+ volatile uint32_t ICDISER14; /* ICDISER14 */
+ volatile uint32_t ICDISER15; /* ICDISER15 */
+ volatile uint32_t ICDISER16; /* ICDISER16 */
+ volatile uint32_t ICDISER17; /* ICDISER17 */
+ volatile uint32_t ICDISER18; /* ICDISER18 */
+ volatile uint8_t dummy195[52]; /* */
+#define INTC_ICDICER0_COUNT 19
+ volatile uint32_t ICDICER0; /* ICDICER0 */
+ volatile uint32_t ICDICER1; /* ICDICER1 */
+ volatile uint32_t ICDICER2; /* ICDICER2 */
+ volatile uint32_t ICDICER3; /* ICDICER3 */
+ volatile uint32_t ICDICER4; /* ICDICER4 */
+ volatile uint32_t ICDICER5; /* ICDICER5 */
+ volatile uint32_t ICDICER6; /* ICDICER6 */
+ volatile uint32_t ICDICER7; /* ICDICER7 */
+ volatile uint32_t ICDICER8; /* ICDICER8 */
+ volatile uint32_t ICDICER9; /* ICDICER9 */
+ volatile uint32_t ICDICER10; /* ICDICER10 */
+ volatile uint32_t ICDICER11; /* ICDICER11 */
+ volatile uint32_t ICDICER12; /* ICDICER12 */
+ volatile uint32_t ICDICER13; /* ICDICER13 */
+ volatile uint32_t ICDICER14; /* ICDICER14 */
+ volatile uint32_t ICDICER15; /* ICDICER15 */
+ volatile uint32_t ICDICER16; /* ICDICER16 */
+ volatile uint32_t ICDICER17; /* ICDICER17 */
+ volatile uint32_t ICDICER18; /* ICDICER18 */
+ volatile uint8_t dummy196[52]; /* */
+#define INTC_ICDISPR0_COUNT 19
+ volatile uint32_t ICDISPR0; /* ICDISPR0 */
+ volatile uint32_t ICDISPR1; /* ICDISPR1 */
+ volatile uint32_t ICDISPR2; /* ICDISPR2 */
+ volatile uint32_t ICDISPR3; /* ICDISPR3 */
+ volatile uint32_t ICDISPR4; /* ICDISPR4 */
+ volatile uint32_t ICDISPR5; /* ICDISPR5 */
+ volatile uint32_t ICDISPR6; /* ICDISPR6 */
+ volatile uint32_t ICDISPR7; /* ICDISPR7 */
+ volatile uint32_t ICDISPR8; /* ICDISPR8 */
+ volatile uint32_t ICDISPR9; /* ICDISPR9 */
+ volatile uint32_t ICDISPR10; /* ICDISPR10 */
+ volatile uint32_t ICDISPR11; /* ICDISPR11 */
+ volatile uint32_t ICDISPR12; /* ICDISPR12 */
+ volatile uint32_t ICDISPR13; /* ICDISPR13 */
+ volatile uint32_t ICDISPR14; /* ICDISPR14 */
+ volatile uint32_t ICDISPR15; /* ICDISPR15 */
+ volatile uint32_t ICDISPR16; /* ICDISPR16 */
+ volatile uint32_t ICDISPR17; /* ICDISPR17 */
+ volatile uint32_t ICDISPR18; /* ICDISPR18 */
+ volatile uint8_t dummy197[52]; /* */
+#define INTC_ICDICPR0_COUNT 19
+ volatile uint32_t ICDICPR0; /* ICDICPR0 */
+ volatile uint32_t ICDICPR1; /* ICDICPR1 */
+ volatile uint32_t ICDICPR2; /* ICDICPR2 */
+ volatile uint32_t ICDICPR3; /* ICDICPR3 */
+ volatile uint32_t ICDICPR4; /* ICDICPR4 */
+ volatile uint32_t ICDICPR5; /* ICDICPR5 */
+ volatile uint32_t ICDICPR6; /* ICDICPR6 */
+ volatile uint32_t ICDICPR7; /* ICDICPR7 */
+ volatile uint32_t ICDICPR8; /* ICDICPR8 */
+ volatile uint32_t ICDICPR9; /* ICDICPR9 */
+ volatile uint32_t ICDICPR10; /* ICDICPR10 */
+ volatile uint32_t ICDICPR11; /* ICDICPR11 */
+ volatile uint32_t ICDICPR12; /* ICDICPR12 */
+ volatile uint32_t ICDICPR13; /* ICDICPR13 */
+ volatile uint32_t ICDICPR14; /* ICDICPR14 */
+ volatile uint32_t ICDICPR15; /* ICDICPR15 */
+ volatile uint32_t ICDICPR16; /* ICDICPR16 */
+ volatile uint32_t ICDICPR17; /* ICDICPR17 */
+ volatile uint32_t ICDICPR18; /* ICDICPR18 */
+ volatile uint8_t dummy198[52]; /* */
+#define INTC_ICDABR0_COUNT 19
+ volatile uint32_t ICDABR0; /* ICDABR0 */
+ volatile uint32_t ICDABR1; /* ICDABR1 */
+ volatile uint32_t ICDABR2; /* ICDABR2 */
+ volatile uint32_t ICDABR3; /* ICDABR3 */
+ volatile uint32_t ICDABR4; /* ICDABR4 */
+ volatile uint32_t ICDABR5; /* ICDABR5 */
+ volatile uint32_t ICDABR6; /* ICDABR6 */
+ volatile uint32_t ICDABR7; /* ICDABR7 */
+ volatile uint32_t ICDABR8; /* ICDABR8 */
+ volatile uint32_t ICDABR9; /* ICDABR9 */
+ volatile uint32_t ICDABR10; /* ICDABR10 */
+ volatile uint32_t ICDABR11; /* ICDABR11 */
+ volatile uint32_t ICDABR12; /* ICDABR12 */
+ volatile uint32_t ICDABR13; /* ICDABR13 */
+ volatile uint32_t ICDABR14; /* ICDABR14 */
+ volatile uint32_t ICDABR15; /* ICDABR15 */
+ volatile uint32_t ICDABR16; /* ICDABR16 */
+ volatile uint32_t ICDABR17; /* ICDABR17 */
+ volatile uint32_t ICDABR18; /* ICDABR18 */
+ volatile uint8_t dummy199[180]; /* */
+#define INTC_ICDIPR0_COUNT 147
+ volatile uint32_t ICDIPR0; /* ICDIPR0 */
+ volatile uint32_t ICDIPR1; /* ICDIPR1 */
+ volatile uint32_t ICDIPR2; /* ICDIPR2 */
+ volatile uint32_t ICDIPR3; /* ICDIPR3 */
+ volatile uint32_t ICDIPR4; /* ICDIPR4 */
+ volatile uint32_t ICDIPR5; /* ICDIPR5 */
+ volatile uint32_t ICDIPR6; /* ICDIPR6 */
+ volatile uint32_t ICDIPR7; /* ICDIPR7 */
+ volatile uint32_t ICDIPR8; /* ICDIPR8 */
+ volatile uint32_t ICDIPR9; /* ICDIPR9 */
+ volatile uint32_t ICDIPR10; /* ICDIPR10 */
+ volatile uint32_t ICDIPR11; /* ICDIPR11 */
+ volatile uint32_t ICDIPR12; /* ICDIPR12 */
+ volatile uint32_t ICDIPR13; /* ICDIPR13 */
+ volatile uint32_t ICDIPR14; /* ICDIPR14 */
+ volatile uint32_t ICDIPR15; /* ICDIPR15 */
+ volatile uint32_t ICDIPR16; /* ICDIPR16 */
+ volatile uint32_t ICDIPR17; /* ICDIPR17 */
+ volatile uint32_t ICDIPR18; /* ICDIPR18 */
+ volatile uint32_t ICDIPR19; /* ICDIPR19 */
+ volatile uint32_t ICDIPR20; /* ICDIPR20 */
+ volatile uint32_t ICDIPR21; /* ICDIPR21 */
+ volatile uint32_t ICDIPR22; /* ICDIPR22 */
+ volatile uint32_t ICDIPR23; /* ICDIPR23 */
+ volatile uint32_t ICDIPR24; /* ICDIPR24 */
+ volatile uint32_t ICDIPR25; /* ICDIPR25 */
+ volatile uint32_t ICDIPR26; /* ICDIPR26 */
+ volatile uint32_t ICDIPR27; /* ICDIPR27 */
+ volatile uint32_t ICDIPR28; /* ICDIPR28 */
+ volatile uint32_t ICDIPR29; /* ICDIPR29 */
+ volatile uint32_t ICDIPR30; /* ICDIPR30 */
+ volatile uint32_t ICDIPR31; /* ICDIPR31 */
+ volatile uint32_t ICDIPR32; /* ICDIPR32 */
+ volatile uint32_t ICDIPR33; /* ICDIPR33 */
+ volatile uint32_t ICDIPR34; /* ICDIPR34 */
+ volatile uint32_t ICDIPR35; /* ICDIPR35 */
+ volatile uint32_t ICDIPR36; /* ICDIPR36 */
+ volatile uint32_t ICDIPR37; /* ICDIPR37 */
+ volatile uint32_t ICDIPR38; /* ICDIPR38 */
+ volatile uint32_t ICDIPR39; /* ICDIPR39 */
+ volatile uint32_t ICDIPR40; /* ICDIPR40 */
+ volatile uint32_t ICDIPR41; /* ICDIPR41 */
+ volatile uint32_t ICDIPR42; /* ICDIPR42 */
+ volatile uint32_t ICDIPR43; /* ICDIPR43 */
+ volatile uint32_t ICDIPR44; /* ICDIPR44 */
+ volatile uint32_t ICDIPR45; /* ICDIPR45 */
+ volatile uint32_t ICDIPR46; /* ICDIPR46 */
+ volatile uint32_t ICDIPR47; /* ICDIPR47 */
+ volatile uint32_t ICDIPR48; /* ICDIPR48 */
+ volatile uint32_t ICDIPR49; /* ICDIPR49 */
+ volatile uint32_t ICDIPR50; /* ICDIPR50 */
+ volatile uint32_t ICDIPR51; /* ICDIPR51 */
+ volatile uint32_t ICDIPR52; /* ICDIPR52 */
+ volatile uint32_t ICDIPR53; /* ICDIPR53 */
+ volatile uint32_t ICDIPR54; /* ICDIPR54 */
+ volatile uint32_t ICDIPR55; /* ICDIPR55 */
+ volatile uint32_t ICDIPR56; /* ICDIPR56 */
+ volatile uint32_t ICDIPR57; /* ICDIPR57 */
+ volatile uint32_t ICDIPR58; /* ICDIPR58 */
+ volatile uint32_t ICDIPR59; /* ICDIPR59 */
+ volatile uint32_t ICDIPR60; /* ICDIPR60 */
+ volatile uint32_t ICDIPR61; /* ICDIPR61 */
+ volatile uint32_t ICDIPR62; /* ICDIPR62 */
+ volatile uint32_t ICDIPR63; /* ICDIPR63 */
+ volatile uint32_t ICDIPR64; /* ICDIPR64 */
+ volatile uint32_t ICDIPR65; /* ICDIPR65 */
+ volatile uint32_t ICDIPR66; /* ICDIPR66 */
+ volatile uint32_t ICDIPR67; /* ICDIPR67 */
+ volatile uint32_t ICDIPR68; /* ICDIPR68 */
+ volatile uint32_t ICDIPR69; /* ICDIPR69 */
+ volatile uint32_t ICDIPR70; /* ICDIPR70 */
+ volatile uint32_t ICDIPR71; /* ICDIPR71 */
+ volatile uint32_t ICDIPR72; /* ICDIPR72 */
+ volatile uint32_t ICDIPR73; /* ICDIPR73 */
+ volatile uint32_t ICDIPR74; /* ICDIPR74 */
+ volatile uint32_t ICDIPR75; /* ICDIPR75 */
+ volatile uint32_t ICDIPR76; /* ICDIPR76 */
+ volatile uint32_t ICDIPR77; /* ICDIPR77 */
+ volatile uint32_t ICDIPR78; /* ICDIPR78 */
+ volatile uint32_t ICDIPR79; /* ICDIPR79 */
+ volatile uint32_t ICDIPR80; /* ICDIPR80 */
+ volatile uint32_t ICDIPR81; /* ICDIPR81 */
+ volatile uint32_t ICDIPR82; /* ICDIPR82 */
+ volatile uint32_t ICDIPR83; /* ICDIPR83 */
+ volatile uint32_t ICDIPR84; /* ICDIPR84 */
+ volatile uint32_t ICDIPR85; /* ICDIPR85 */
+ volatile uint32_t ICDIPR86; /* ICDIPR86 */
+ volatile uint32_t ICDIPR87; /* ICDIPR87 */
+ volatile uint32_t ICDIPR88; /* ICDIPR88 */
+ volatile uint32_t ICDIPR89; /* ICDIPR89 */
+ volatile uint32_t ICDIPR90; /* ICDIPR90 */
+ volatile uint32_t ICDIPR91; /* ICDIPR91 */
+ volatile uint32_t ICDIPR92; /* ICDIPR92 */
+ volatile uint32_t ICDIPR93; /* ICDIPR93 */
+ volatile uint32_t ICDIPR94; /* ICDIPR94 */
+ volatile uint32_t ICDIPR95; /* ICDIPR95 */
+ volatile uint32_t ICDIPR96; /* ICDIPR96 */
+ volatile uint32_t ICDIPR97; /* ICDIPR97 */
+ volatile uint32_t ICDIPR98; /* ICDIPR98 */
+ volatile uint32_t ICDIPR99; /* ICDIPR99 */
+ volatile uint32_t ICDIPR100; /* ICDIPR100 */
+ volatile uint32_t ICDIPR101; /* ICDIPR101 */
+ volatile uint32_t ICDIPR102; /* ICDIPR102 */
+ volatile uint32_t ICDIPR103; /* ICDIPR103 */
+ volatile uint32_t ICDIPR104; /* ICDIPR104 */
+ volatile uint32_t ICDIPR105; /* ICDIPR105 */
+ volatile uint32_t ICDIPR106; /* ICDIPR106 */
+ volatile uint32_t ICDIPR107; /* ICDIPR107 */
+ volatile uint32_t ICDIPR108; /* ICDIPR108 */
+ volatile uint32_t ICDIPR109; /* ICDIPR109 */
+ volatile uint32_t ICDIPR110; /* ICDIPR110 */
+ volatile uint32_t ICDIPR111; /* ICDIPR111 */
+ volatile uint32_t ICDIPR112; /* ICDIPR112 */
+ volatile uint32_t ICDIPR113; /* ICDIPR113 */
+ volatile uint32_t ICDIPR114; /* ICDIPR114 */
+ volatile uint32_t ICDIPR115; /* ICDIPR115 */
+ volatile uint32_t ICDIPR116; /* ICDIPR116 */
+ volatile uint32_t ICDIPR117; /* ICDIPR117 */
+ volatile uint32_t ICDIPR118; /* ICDIPR118 */
+ volatile uint32_t ICDIPR119; /* ICDIPR119 */
+ volatile uint32_t ICDIPR120; /* ICDIPR120 */
+ volatile uint32_t ICDIPR121; /* ICDIPR121 */
+ volatile uint32_t ICDIPR122; /* ICDIPR122 */
+ volatile uint32_t ICDIPR123; /* ICDIPR123 */
+ volatile uint32_t ICDIPR124; /* ICDIPR124 */
+ volatile uint32_t ICDIPR125; /* ICDIPR125 */
+ volatile uint32_t ICDIPR126; /* ICDIPR126 */
+ volatile uint32_t ICDIPR127; /* ICDIPR127 */
+ volatile uint32_t ICDIPR128; /* ICDIPR128 */
+ volatile uint32_t ICDIPR129; /* ICDIPR129 */
+ volatile uint32_t ICDIPR130; /* ICDIPR130 */
+ volatile uint32_t ICDIPR131; /* ICDIPR131 */
+ volatile uint32_t ICDIPR132; /* ICDIPR132 */
+ volatile uint32_t ICDIPR133; /* ICDIPR133 */
+ volatile uint32_t ICDIPR134; /* ICDIPR134 */
+ volatile uint32_t ICDIPR135; /* ICDIPR135 */
+ volatile uint32_t ICDIPR136; /* ICDIPR136 */
+ volatile uint32_t ICDIPR137; /* ICDIPR137 */
+ volatile uint32_t ICDIPR138; /* ICDIPR138 */
+ volatile uint32_t ICDIPR139; /* ICDIPR139 */
+ volatile uint32_t ICDIPR140; /* ICDIPR140 */
+ volatile uint32_t ICDIPR141; /* ICDIPR141 */
+ volatile uint32_t ICDIPR142; /* ICDIPR142 */
+ volatile uint32_t ICDIPR143; /* ICDIPR143 */
+ volatile uint32_t ICDIPR144; /* ICDIPR144 */
+ volatile uint32_t ICDIPR145; /* ICDIPR145 */
+ volatile uint32_t ICDIPR146; /* ICDIPR146 */
+ volatile uint8_t dummy200[436]; /* */
+#define INTC_ICDIPTR0_COUNT 147
+ volatile uint32_t ICDIPTR0; /* ICDIPTR0 */
+ volatile uint32_t ICDIPTR1; /* ICDIPTR1 */
+ volatile uint32_t ICDIPTR2; /* ICDIPTR2 */
+ volatile uint32_t ICDIPTR3; /* ICDIPTR3 */
+ volatile uint32_t ICDIPTR4; /* ICDIPTR4 */
+ volatile uint32_t ICDIPTR5; /* ICDIPTR5 */
+ volatile uint32_t ICDIPTR6; /* ICDIPTR6 */
+ volatile uint32_t ICDIPTR7; /* ICDIPTR7 */
+ volatile uint32_t ICDIPTR8; /* ICDIPTR8 */
+ volatile uint32_t ICDIPTR9; /* ICDIPTR9 */
+ volatile uint32_t ICDIPTR10; /* ICDIPTR10 */
+ volatile uint32_t ICDIPTR11; /* ICDIPTR11 */
+ volatile uint32_t ICDIPTR12; /* ICDIPTR12 */
+ volatile uint32_t ICDIPTR13; /* ICDIPTR13 */
+ volatile uint32_t ICDIPTR14; /* ICDIPTR14 */
+ volatile uint32_t ICDIPTR15; /* ICDIPTR15 */
+ volatile uint32_t ICDIPTR16; /* ICDIPTR16 */
+ volatile uint32_t ICDIPTR17; /* ICDIPTR17 */
+ volatile uint32_t ICDIPTR18; /* ICDIPTR18 */
+ volatile uint32_t ICDIPTR19; /* ICDIPTR19 */
+ volatile uint32_t ICDIPTR20; /* ICDIPTR20 */
+ volatile uint32_t ICDIPTR21; /* ICDIPTR21 */
+ volatile uint32_t ICDIPTR22; /* ICDIPTR22 */
+ volatile uint32_t ICDIPTR23; /* ICDIPTR23 */
+ volatile uint32_t ICDIPTR24; /* ICDIPTR24 */
+ volatile uint32_t ICDIPTR25; /* ICDIPTR25 */
+ volatile uint32_t ICDIPTR26; /* ICDIPTR26 */
+ volatile uint32_t ICDIPTR27; /* ICDIPTR27 */
+ volatile uint32_t ICDIPTR28; /* ICDIPTR28 */
+ volatile uint32_t ICDIPTR29; /* ICDIPTR29 */
+ volatile uint32_t ICDIPTR30; /* ICDIPTR30 */
+ volatile uint32_t ICDIPTR31; /* ICDIPTR31 */
+ volatile uint32_t ICDIPTR32; /* ICDIPTR32 */
+ volatile uint32_t ICDIPTR33; /* ICDIPTR33 */
+ volatile uint32_t ICDIPTR34; /* ICDIPTR34 */
+ volatile uint32_t ICDIPTR35; /* ICDIPTR35 */
+ volatile uint32_t ICDIPTR36; /* ICDIPTR36 */
+ volatile uint32_t ICDIPTR37; /* ICDIPTR37 */
+ volatile uint32_t ICDIPTR38; /* ICDIPTR38 */
+ volatile uint32_t ICDIPTR39; /* ICDIPTR39 */
+ volatile uint32_t ICDIPTR40; /* ICDIPTR40 */
+ volatile uint32_t ICDIPTR41; /* ICDIPTR41 */
+ volatile uint32_t ICDIPTR42; /* ICDIPTR42 */
+ volatile uint32_t ICDIPTR43; /* ICDIPTR43 */
+ volatile uint32_t ICDIPTR44; /* ICDIPTR44 */
+ volatile uint32_t ICDIPTR45; /* ICDIPTR45 */
+ volatile uint32_t ICDIPTR46; /* ICDIPTR46 */
+ volatile uint32_t ICDIPTR47; /* ICDIPTR47 */
+ volatile uint32_t ICDIPTR48; /* ICDIPTR48 */
+ volatile uint32_t ICDIPTR49; /* ICDIPTR49 */
+ volatile uint32_t ICDIPTR50; /* ICDIPTR50 */
+ volatile uint32_t ICDIPTR51; /* ICDIPTR51 */
+ volatile uint32_t ICDIPTR52; /* ICDIPTR52 */
+ volatile uint32_t ICDIPTR53; /* ICDIPTR53 */
+ volatile uint32_t ICDIPTR54; /* ICDIPTR54 */
+ volatile uint32_t ICDIPTR55; /* ICDIPTR55 */
+ volatile uint32_t ICDIPTR56; /* ICDIPTR56 */
+ volatile uint32_t ICDIPTR57; /* ICDIPTR57 */
+ volatile uint32_t ICDIPTR58; /* ICDIPTR58 */
+ volatile uint32_t ICDIPTR59; /* ICDIPTR59 */
+ volatile uint32_t ICDIPTR60; /* ICDIPTR60 */
+ volatile uint32_t ICDIPTR61; /* ICDIPTR61 */
+ volatile uint32_t ICDIPTR62; /* ICDIPTR62 */
+ volatile uint32_t ICDIPTR63; /* ICDIPTR63 */
+ volatile uint32_t ICDIPTR64; /* ICDIPTR64 */
+ volatile uint32_t ICDIPTR65; /* ICDIPTR65 */
+ volatile uint32_t ICDIPTR66; /* ICDIPTR66 */
+ volatile uint32_t ICDIPTR67; /* ICDIPTR67 */
+ volatile uint32_t ICDIPTR68; /* ICDIPTR68 */
+ volatile uint32_t ICDIPTR69; /* ICDIPTR69 */
+ volatile uint32_t ICDIPTR70; /* ICDIPTR70 */
+ volatile uint32_t ICDIPTR71; /* ICDIPTR71 */
+ volatile uint32_t ICDIPTR72; /* ICDIPTR72 */
+ volatile uint32_t ICDIPTR73; /* ICDIPTR73 */
+ volatile uint32_t ICDIPTR74; /* ICDIPTR74 */
+ volatile uint32_t ICDIPTR75; /* ICDIPTR75 */
+ volatile uint32_t ICDIPTR76; /* ICDIPTR76 */
+ volatile uint32_t ICDIPTR77; /* ICDIPTR77 */
+ volatile uint32_t ICDIPTR78; /* ICDIPTR78 */
+ volatile uint32_t ICDIPTR79; /* ICDIPTR79 */
+ volatile uint32_t ICDIPTR80; /* ICDIPTR80 */
+ volatile uint32_t ICDIPTR81; /* ICDIPTR81 */
+ volatile uint32_t ICDIPTR82; /* ICDIPTR82 */
+ volatile uint32_t ICDIPTR83; /* ICDIPTR83 */
+ volatile uint32_t ICDIPTR84; /* ICDIPTR84 */
+ volatile uint32_t ICDIPTR85; /* ICDIPTR85 */
+ volatile uint32_t ICDIPTR86; /* ICDIPTR86 */
+ volatile uint32_t ICDIPTR87; /* ICDIPTR87 */
+ volatile uint32_t ICDIPTR88; /* ICDIPTR88 */
+ volatile uint32_t ICDIPTR89; /* ICDIPTR89 */
+ volatile uint32_t ICDIPTR90; /* ICDIPTR90 */
+ volatile uint32_t ICDIPTR91; /* ICDIPTR91 */
+ volatile uint32_t ICDIPTR92; /* ICDIPTR92 */
+ volatile uint32_t ICDIPTR93; /* ICDIPTR93 */
+ volatile uint32_t ICDIPTR94; /* ICDIPTR94 */
+ volatile uint32_t ICDIPTR95; /* ICDIPTR95 */
+ volatile uint32_t ICDIPTR96; /* ICDIPTR96 */
+ volatile uint32_t ICDIPTR97; /* ICDIPTR97 */
+ volatile uint32_t ICDIPTR98; /* ICDIPTR98 */
+ volatile uint32_t ICDIPTR99; /* ICDIPTR99 */
+ volatile uint32_t ICDIPTR100; /* ICDIPTR100 */
+ volatile uint32_t ICDIPTR101; /* ICDIPTR101 */
+ volatile uint32_t ICDIPTR102; /* ICDIPTR102 */
+ volatile uint32_t ICDIPTR103; /* ICDIPTR103 */
+ volatile uint32_t ICDIPTR104; /* ICDIPTR104 */
+ volatile uint32_t ICDIPTR105; /* ICDIPTR105 */
+ volatile uint32_t ICDIPTR106; /* ICDIPTR106 */
+ volatile uint32_t ICDIPTR107; /* ICDIPTR107 */
+ volatile uint32_t ICDIPTR108; /* ICDIPTR108 */
+ volatile uint32_t ICDIPTR109; /* ICDIPTR109 */
+ volatile uint32_t ICDIPTR110; /* ICDIPTR110 */
+ volatile uint32_t ICDIPTR111; /* ICDIPTR111 */
+ volatile uint32_t ICDIPTR112; /* ICDIPTR112 */
+ volatile uint32_t ICDIPTR113; /* ICDIPTR113 */
+ volatile uint32_t ICDIPTR114; /* ICDIPTR114 */
+ volatile uint32_t ICDIPTR115; /* ICDIPTR115 */
+ volatile uint32_t ICDIPTR116; /* ICDIPTR116 */
+ volatile uint32_t ICDIPTR117; /* ICDIPTR117 */
+ volatile uint32_t ICDIPTR118; /* ICDIPTR118 */
+ volatile uint32_t ICDIPTR119; /* ICDIPTR119 */
+ volatile uint32_t ICDIPTR120; /* ICDIPTR120 */
+ volatile uint32_t ICDIPTR121; /* ICDIPTR121 */
+ volatile uint32_t ICDIPTR122; /* ICDIPTR122 */
+ volatile uint32_t ICDIPTR123; /* ICDIPTR123 */
+ volatile uint32_t ICDIPTR124; /* ICDIPTR124 */
+ volatile uint32_t ICDIPTR125; /* ICDIPTR125 */
+ volatile uint32_t ICDIPTR126; /* ICDIPTR126 */
+ volatile uint32_t ICDIPTR127; /* ICDIPTR127 */
+ volatile uint32_t ICDIPTR128; /* ICDIPTR128 */
+ volatile uint32_t ICDIPTR129; /* ICDIPTR129 */
+ volatile uint32_t ICDIPTR130; /* ICDIPTR130 */
+ volatile uint32_t ICDIPTR131; /* ICDIPTR131 */
+ volatile uint32_t ICDIPTR132; /* ICDIPTR132 */
+ volatile uint32_t ICDIPTR133; /* ICDIPTR133 */
+ volatile uint32_t ICDIPTR134; /* ICDIPTR134 */
+ volatile uint32_t ICDIPTR135; /* ICDIPTR135 */
+ volatile uint32_t ICDIPTR136; /* ICDIPTR136 */
+ volatile uint32_t ICDIPTR137; /* ICDIPTR137 */
+ volatile uint32_t ICDIPTR138; /* ICDIPTR138 */
+ volatile uint32_t ICDIPTR139; /* ICDIPTR139 */
+ volatile uint32_t ICDIPTR140; /* ICDIPTR140 */
+ volatile uint32_t ICDIPTR141; /* ICDIPTR141 */
+ volatile uint32_t ICDIPTR142; /* ICDIPTR142 */
+ volatile uint32_t ICDIPTR143; /* ICDIPTR143 */
+ volatile uint32_t ICDIPTR144; /* ICDIPTR144 */
+ volatile uint32_t ICDIPTR145; /* ICDIPTR145 */
+ volatile uint32_t ICDIPTR146; /* ICDIPTR146 */
+ volatile uint8_t dummy201[436]; /* */
+#define INTC_ICDICFR0_COUNT 37
+ volatile uint32_t ICDICFR0; /* ICDICFR0 */
+ volatile uint32_t ICDICFR1; /* ICDICFR1 */
+ volatile uint32_t ICDICFR2; /* ICDICFR2 */
+ volatile uint32_t ICDICFR3; /* ICDICFR3 */
+ volatile uint32_t ICDICFR4; /* ICDICFR4 */
+ volatile uint32_t ICDICFR5; /* ICDICFR5 */
+ volatile uint32_t ICDICFR6; /* ICDICFR6 */
+ volatile uint32_t ICDICFR7; /* ICDICFR7 */
+ volatile uint32_t ICDICFR8; /* ICDICFR8 */
+ volatile uint32_t ICDICFR9; /* ICDICFR9 */
+ volatile uint32_t ICDICFR10; /* ICDICFR10 */
+ volatile uint32_t ICDICFR11; /* ICDICFR11 */
+ volatile uint32_t ICDICFR12; /* ICDICFR12 */
+ volatile uint32_t ICDICFR13; /* ICDICFR13 */
+ volatile uint32_t ICDICFR14; /* ICDICFR14 */
+ volatile uint32_t ICDICFR15; /* ICDICFR15 */
+ volatile uint32_t ICDICFR16; /* ICDICFR16 */
+ volatile uint32_t ICDICFR17; /* ICDICFR17 */
+ volatile uint32_t ICDICFR18; /* ICDICFR18 */
+ volatile uint32_t ICDICFR19; /* ICDICFR19 */
+ volatile uint32_t ICDICFR20; /* ICDICFR20 */
+ volatile uint32_t ICDICFR21; /* ICDICFR21 */
+ volatile uint32_t ICDICFR22; /* ICDICFR22 */
+ volatile uint32_t ICDICFR23; /* ICDICFR23 */
+ volatile uint32_t ICDICFR24; /* ICDICFR24 */
+ volatile uint32_t ICDICFR25; /* ICDICFR25 */
+ volatile uint32_t ICDICFR26; /* ICDICFR26 */
+ volatile uint32_t ICDICFR27; /* ICDICFR27 */
+ volatile uint32_t ICDICFR28; /* ICDICFR28 */
+ volatile uint32_t ICDICFR29; /* ICDICFR29 */
+ volatile uint32_t ICDICFR30; /* ICDICFR30 */
+ volatile uint32_t ICDICFR31; /* ICDICFR31 */
+ volatile uint32_t ICDICFR32; /* ICDICFR32 */
+ volatile uint32_t ICDICFR33; /* ICDICFR33 */
+ volatile uint32_t ICDICFR34; /* ICDICFR34 */
+ volatile uint32_t ICDICFR35; /* ICDICFR35 */
+ volatile uint32_t ICDICFR36; /* ICDICFR36 */
+ volatile uint8_t dummy202[108]; /* */
+ volatile uint32_t PPI_STATUS; /* PPI_STATUS */
+#define INTC_SPI_STATUS0_COUNT 17
+ volatile uint32_t SPI_STATUS0; /* SPI_STATUS0 */
+ volatile uint32_t SPI_STATUS1; /* SPI_STATUS1 */
+ volatile uint32_t SPI_STATUS2; /* SPI_STATUS2 */
+ volatile uint32_t SPI_STATUS3; /* SPI_STATUS3 */
+ volatile uint32_t SPI_STATUS4; /* SPI_STATUS4 */
+ volatile uint32_t SPI_STATUS5; /* SPI_STATUS5 */
+ volatile uint32_t SPI_STATUS6; /* SPI_STATUS6 */
+ volatile uint32_t SPI_STATUS7; /* SPI_STATUS7 */
+ volatile uint32_t SPI_STATUS8; /* SPI_STATUS8 */
+ volatile uint32_t SPI_STATUS9; /* SPI_STATUS9 */
+ volatile uint32_t SPI_STATUS10; /* SPI_STATUS10 */
+ volatile uint32_t SPI_STATUS11; /* SPI_STATUS11 */
+ volatile uint32_t SPI_STATUS12; /* SPI_STATUS12 */
+ volatile uint32_t SPI_STATUS13; /* SPI_STATUS13 */
+ volatile uint32_t SPI_STATUS14; /* SPI_STATUS14 */
+ volatile uint32_t SPI_STATUS15; /* SPI_STATUS15 */
+ volatile uint32_t SPI_STATUS16; /* SPI_STATUS16 */
+ volatile uint8_t dummy203[440]; /* */
+ volatile uint32_t ICDSGIR; /* ICDSGIR */
+ volatile uint8_t dummy204[252]; /* */
+ volatile uint32_t ICCICR; /* ICCICR */
+ volatile uint32_t ICCPMR; /* ICCPMR */
+ volatile uint32_t ICCBPR; /* ICCBPR */
+ volatile uint32_t ICCIAR; /* ICCIAR */
+ volatile uint32_t ICCEOIR; /* ICCEOIR */
+ volatile uint32_t ICCRPR; /* ICCRPR */
+ volatile uint32_t ICCHPIR; /* ICCHPIR */
+ volatile uint32_t ICCABPR; /* ICCABPR */
+ volatile uint8_t dummy205[220]; /* */
+ volatile uint32_t ICCIIDR; /* ICCIIDR */
+ volatile uint8_t dummy206[350148352]; /* */
+ volatile uint16_t ICR0; /* ICR0 */
+ volatile uint16_t ICR1; /* ICR1 */
+ volatile uint16_t IRQRR; /* IRQRR */
+};
+
+
+#define INTC (*(struct st_intc *)0xE8201000uL) /* INTC */
+
+
+#define INTCICDDCR INTC.ICDDCR
+#define INTCICDICTR INTC.ICDICTR
+#define INTCICDIIDR INTC.ICDIIDR
+#define INTCICDISR0 INTC.ICDISR0
+#define INTCICDISR1 INTC.ICDISR1
+#define INTCICDISR2 INTC.ICDISR2
+#define INTCICDISR3 INTC.ICDISR3
+#define INTCICDISR4 INTC.ICDISR4
+#define INTCICDISR5 INTC.ICDISR5
+#define INTCICDISR6 INTC.ICDISR6
+#define INTCICDISR7 INTC.ICDISR7
+#define INTCICDISR8 INTC.ICDISR8
+#define INTCICDISR9 INTC.ICDISR9
+#define INTCICDISR10 INTC.ICDISR10
+#define INTCICDISR11 INTC.ICDISR11
+#define INTCICDISR12 INTC.ICDISR12
+#define INTCICDISR13 INTC.ICDISR13
+#define INTCICDISR14 INTC.ICDISR14
+#define INTCICDISR15 INTC.ICDISR15
+#define INTCICDISR16 INTC.ICDISR16
+#define INTCICDISR17 INTC.ICDISR17
+#define INTCICDISR18 INTC.ICDISR18
+#define INTCICDISER0 INTC.ICDISER0
+#define INTCICDISER1 INTC.ICDISER1
+#define INTCICDISER2 INTC.ICDISER2
+#define INTCICDISER3 INTC.ICDISER3
+#define INTCICDISER4 INTC.ICDISER4
+#define INTCICDISER5 INTC.ICDISER5
+#define INTCICDISER6 INTC.ICDISER6
+#define INTCICDISER7 INTC.ICDISER7
+#define INTCICDISER8 INTC.ICDISER8
+#define INTCICDISER9 INTC.ICDISER9
+#define INTCICDISER10 INTC.ICDISER10
+#define INTCICDISER11 INTC.ICDISER11
+#define INTCICDISER12 INTC.ICDISER12
+#define INTCICDISER13 INTC.ICDISER13
+#define INTCICDISER14 INTC.ICDISER14
+#define INTCICDISER15 INTC.ICDISER15
+#define INTCICDISER16 INTC.ICDISER16
+#define INTCICDISER17 INTC.ICDISER17
+#define INTCICDISER18 INTC.ICDISER18
+#define INTCICDICER0 INTC.ICDICER0
+#define INTCICDICER1 INTC.ICDICER1
+#define INTCICDICER2 INTC.ICDICER2
+#define INTCICDICER3 INTC.ICDICER3
+#define INTCICDICER4 INTC.ICDICER4
+#define INTCICDICER5 INTC.ICDICER5
+#define INTCICDICER6 INTC.ICDICER6
+#define INTCICDICER7 INTC.ICDICER7
+#define INTCICDICER8 INTC.ICDICER8
+#define INTCICDICER9 INTC.ICDICER9
+#define INTCICDICER10 INTC.ICDICER10
+#define INTCICDICER11 INTC.ICDICER11
+#define INTCICDICER12 INTC.ICDICER12
+#define INTCICDICER13 INTC.ICDICER13
+#define INTCICDICER14 INTC.ICDICER14
+#define INTCICDICER15 INTC.ICDICER15
+#define INTCICDICER16 INTC.ICDICER16
+#define INTCICDICER17 INTC.ICDICER17
+#define INTCICDICER18 INTC.ICDICER18
+#define INTCICDISPR0 INTC.ICDISPR0
+#define INTCICDISPR1 INTC.ICDISPR1
+#define INTCICDISPR2 INTC.ICDISPR2
+#define INTCICDISPR3 INTC.ICDISPR3
+#define INTCICDISPR4 INTC.ICDISPR4
+#define INTCICDISPR5 INTC.ICDISPR5
+#define INTCICDISPR6 INTC.ICDISPR6
+#define INTCICDISPR7 INTC.ICDISPR7
+#define INTCICDISPR8 INTC.ICDISPR8
+#define INTCICDISPR9 INTC.ICDISPR9
+#define INTCICDISPR10 INTC.ICDISPR10
+#define INTCICDISPR11 INTC.ICDISPR11
+#define INTCICDISPR12 INTC.ICDISPR12
+#define INTCICDISPR13 INTC.ICDISPR13
+#define INTCICDISPR14 INTC.ICDISPR14
+#define INTCICDISPR15 INTC.ICDISPR15
+#define INTCICDISPR16 INTC.ICDISPR16
+#define INTCICDISPR17 INTC.ICDISPR17
+#define INTCICDISPR18 INTC.ICDISPR18
+#define INTCICDICPR0 INTC.ICDICPR0
+#define INTCICDICPR1 INTC.ICDICPR1
+#define INTCICDICPR2 INTC.ICDICPR2
+#define INTCICDICPR3 INTC.ICDICPR3
+#define INTCICDICPR4 INTC.ICDICPR4
+#define INTCICDICPR5 INTC.ICDICPR5
+#define INTCICDICPR6 INTC.ICDICPR6
+#define INTCICDICPR7 INTC.ICDICPR7
+#define INTCICDICPR8 INTC.ICDICPR8
+#define INTCICDICPR9 INTC.ICDICPR9
+#define INTCICDICPR10 INTC.ICDICPR10
+#define INTCICDICPR11 INTC.ICDICPR11
+#define INTCICDICPR12 INTC.ICDICPR12
+#define INTCICDICPR13 INTC.ICDICPR13
+#define INTCICDICPR14 INTC.ICDICPR14
+#define INTCICDICPR15 INTC.ICDICPR15
+#define INTCICDICPR16 INTC.ICDICPR16
+#define INTCICDICPR17 INTC.ICDICPR17
+#define INTCICDICPR18 INTC.ICDICPR18
+#define INTCICDABR0 INTC.ICDABR0
+#define INTCICDABR1 INTC.ICDABR1
+#define INTCICDABR2 INTC.ICDABR2
+#define INTCICDABR3 INTC.ICDABR3
+#define INTCICDABR4 INTC.ICDABR4
+#define INTCICDABR5 INTC.ICDABR5
+#define INTCICDABR6 INTC.ICDABR6
+#define INTCICDABR7 INTC.ICDABR7
+#define INTCICDABR8 INTC.ICDABR8
+#define INTCICDABR9 INTC.ICDABR9
+#define INTCICDABR10 INTC.ICDABR10
+#define INTCICDABR11 INTC.ICDABR11
+#define INTCICDABR12 INTC.ICDABR12
+#define INTCICDABR13 INTC.ICDABR13
+#define INTCICDABR14 INTC.ICDABR14
+#define INTCICDABR15 INTC.ICDABR15
+#define INTCICDABR16 INTC.ICDABR16
+#define INTCICDABR17 INTC.ICDABR17
+#define INTCICDABR18 INTC.ICDABR18
+#define INTCICDIPR0 INTC.ICDIPR0
+#define INTCICDIPR1 INTC.ICDIPR1
+#define INTCICDIPR2 INTC.ICDIPR2
+#define INTCICDIPR3 INTC.ICDIPR3
+#define INTCICDIPR4 INTC.ICDIPR4
+#define INTCICDIPR5 INTC.ICDIPR5
+#define INTCICDIPR6 INTC.ICDIPR6
+#define INTCICDIPR7 INTC.ICDIPR7
+#define INTCICDIPR8 INTC.ICDIPR8
+#define INTCICDIPR9 INTC.ICDIPR9
+#define INTCICDIPR10 INTC.ICDIPR10
+#define INTCICDIPR11 INTC.ICDIPR11
+#define INTCICDIPR12 INTC.ICDIPR12
+#define INTCICDIPR13 INTC.ICDIPR13
+#define INTCICDIPR14 INTC.ICDIPR14
+#define INTCICDIPR15 INTC.ICDIPR15
+#define INTCICDIPR16 INTC.ICDIPR16
+#define INTCICDIPR17 INTC.ICDIPR17
+#define INTCICDIPR18 INTC.ICDIPR18
+#define INTCICDIPR19 INTC.ICDIPR19
+#define INTCICDIPR20 INTC.ICDIPR20
+#define INTCICDIPR21 INTC.ICDIPR21
+#define INTCICDIPR22 INTC.ICDIPR22
+#define INTCICDIPR23 INTC.ICDIPR23
+#define INTCICDIPR24 INTC.ICDIPR24
+#define INTCICDIPR25 INTC.ICDIPR25
+#define INTCICDIPR26 INTC.ICDIPR26
+#define INTCICDIPR27 INTC.ICDIPR27
+#define INTCICDIPR28 INTC.ICDIPR28
+#define INTCICDIPR29 INTC.ICDIPR29
+#define INTCICDIPR30 INTC.ICDIPR30
+#define INTCICDIPR31 INTC.ICDIPR31
+#define INTCICDIPR32 INTC.ICDIPR32
+#define INTCICDIPR33 INTC.ICDIPR33
+#define INTCICDIPR34 INTC.ICDIPR34
+#define INTCICDIPR35 INTC.ICDIPR35
+#define INTCICDIPR36 INTC.ICDIPR36
+#define INTCICDIPR37 INTC.ICDIPR37
+#define INTCICDIPR38 INTC.ICDIPR38
+#define INTCICDIPR39 INTC.ICDIPR39
+#define INTCICDIPR40 INTC.ICDIPR40
+#define INTCICDIPR41 INTC.ICDIPR41
+#define INTCICDIPR42 INTC.ICDIPR42
+#define INTCICDIPR43 INTC.ICDIPR43
+#define INTCICDIPR44 INTC.ICDIPR44
+#define INTCICDIPR45 INTC.ICDIPR45
+#define INTCICDIPR46 INTC.ICDIPR46
+#define INTCICDIPR47 INTC.ICDIPR47
+#define INTCICDIPR48 INTC.ICDIPR48
+#define INTCICDIPR49 INTC.ICDIPR49
+#define INTCICDIPR50 INTC.ICDIPR50
+#define INTCICDIPR51 INTC.ICDIPR51
+#define INTCICDIPR52 INTC.ICDIPR52
+#define INTCICDIPR53 INTC.ICDIPR53
+#define INTCICDIPR54 INTC.ICDIPR54
+#define INTCICDIPR55 INTC.ICDIPR55
+#define INTCICDIPR56 INTC.ICDIPR56
+#define INTCICDIPR57 INTC.ICDIPR57
+#define INTCICDIPR58 INTC.ICDIPR58
+#define INTCICDIPR59 INTC.ICDIPR59
+#define INTCICDIPR60 INTC.ICDIPR60
+#define INTCICDIPR61 INTC.ICDIPR61
+#define INTCICDIPR62 INTC.ICDIPR62
+#define INTCICDIPR63 INTC.ICDIPR63
+#define INTCICDIPR64 INTC.ICDIPR64
+#define INTCICDIPR65 INTC.ICDIPR65
+#define INTCICDIPR66 INTC.ICDIPR66
+#define INTCICDIPR67 INTC.ICDIPR67
+#define INTCICDIPR68 INTC.ICDIPR68
+#define INTCICDIPR69 INTC.ICDIPR69
+#define INTCICDIPR70 INTC.ICDIPR70
+#define INTCICDIPR71 INTC.ICDIPR71
+#define INTCICDIPR72 INTC.ICDIPR72
+#define INTCICDIPR73 INTC.ICDIPR73
+#define INTCICDIPR74 INTC.ICDIPR74
+#define INTCICDIPR75 INTC.ICDIPR75
+#define INTCICDIPR76 INTC.ICDIPR76
+#define INTCICDIPR77 INTC.ICDIPR77
+#define INTCICDIPR78 INTC.ICDIPR78
+#define INTCICDIPR79 INTC.ICDIPR79
+#define INTCICDIPR80 INTC.ICDIPR80
+#define INTCICDIPR81 INTC.ICDIPR81
+#define INTCICDIPR82 INTC.ICDIPR82
+#define INTCICDIPR83 INTC.ICDIPR83
+#define INTCICDIPR84 INTC.ICDIPR84
+#define INTCICDIPR85 INTC.ICDIPR85
+#define INTCICDIPR86 INTC.ICDIPR86
+#define INTCICDIPR87 INTC.ICDIPR87
+#define INTCICDIPR88 INTC.ICDIPR88
+#define INTCICDIPR89 INTC.ICDIPR89
+#define INTCICDIPR90 INTC.ICDIPR90
+#define INTCICDIPR91 INTC.ICDIPR91
+#define INTCICDIPR92 INTC.ICDIPR92
+#define INTCICDIPR93 INTC.ICDIPR93
+#define INTCICDIPR94 INTC.ICDIPR94
+#define INTCICDIPR95 INTC.ICDIPR95
+#define INTCICDIPR96 INTC.ICDIPR96
+#define INTCICDIPR97 INTC.ICDIPR97
+#define INTCICDIPR98 INTC.ICDIPR98
+#define INTCICDIPR99 INTC.ICDIPR99
+#define INTCICDIPR100 INTC.ICDIPR100
+#define INTCICDIPR101 INTC.ICDIPR101
+#define INTCICDIPR102 INTC.ICDIPR102
+#define INTCICDIPR103 INTC.ICDIPR103
+#define INTCICDIPR104 INTC.ICDIPR104
+#define INTCICDIPR105 INTC.ICDIPR105
+#define INTCICDIPR106 INTC.ICDIPR106
+#define INTCICDIPR107 INTC.ICDIPR107
+#define INTCICDIPR108 INTC.ICDIPR108
+#define INTCICDIPR109 INTC.ICDIPR109
+#define INTCICDIPR110 INTC.ICDIPR110
+#define INTCICDIPR111 INTC.ICDIPR111
+#define INTCICDIPR112 INTC.ICDIPR112
+#define INTCICDIPR113 INTC.ICDIPR113
+#define INTCICDIPR114 INTC.ICDIPR114
+#define INTCICDIPR115 INTC.ICDIPR115
+#define INTCICDIPR116 INTC.ICDIPR116
+#define INTCICDIPR117 INTC.ICDIPR117
+#define INTCICDIPR118 INTC.ICDIPR118
+#define INTCICDIPR119 INTC.ICDIPR119
+#define INTCICDIPR120 INTC.ICDIPR120
+#define INTCICDIPR121 INTC.ICDIPR121
+#define INTCICDIPR122 INTC.ICDIPR122
+#define INTCICDIPR123 INTC.ICDIPR123
+#define INTCICDIPR124 INTC.ICDIPR124
+#define INTCICDIPR125 INTC.ICDIPR125
+#define INTCICDIPR126 INTC.ICDIPR126
+#define INTCICDIPR127 INTC.ICDIPR127
+#define INTCICDIPR128 INTC.ICDIPR128
+#define INTCICDIPR129 INTC.ICDIPR129
+#define INTCICDIPR130 INTC.ICDIPR130
+#define INTCICDIPR131 INTC.ICDIPR131
+#define INTCICDIPR132 INTC.ICDIPR132
+#define INTCICDIPR133 INTC.ICDIPR133
+#define INTCICDIPR134 INTC.ICDIPR134
+#define INTCICDIPR135 INTC.ICDIPR135
+#define INTCICDIPR136 INTC.ICDIPR136
+#define INTCICDIPR137 INTC.ICDIPR137
+#define INTCICDIPR138 INTC.ICDIPR138
+#define INTCICDIPR139 INTC.ICDIPR139
+#define INTCICDIPR140 INTC.ICDIPR140
+#define INTCICDIPR141 INTC.ICDIPR141
+#define INTCICDIPR142 INTC.ICDIPR142
+#define INTCICDIPR143 INTC.ICDIPR143
+#define INTCICDIPR144 INTC.ICDIPR144
+#define INTCICDIPR145 INTC.ICDIPR145
+#define INTCICDIPR146 INTC.ICDIPR146
+#define INTCICDIPTR0 INTC.ICDIPTR0
+#define INTCICDIPTR1 INTC.ICDIPTR1
+#define INTCICDIPTR2 INTC.ICDIPTR2
+#define INTCICDIPTR3 INTC.ICDIPTR3
+#define INTCICDIPTR4 INTC.ICDIPTR4
+#define INTCICDIPTR5 INTC.ICDIPTR5
+#define INTCICDIPTR6 INTC.ICDIPTR6
+#define INTCICDIPTR7 INTC.ICDIPTR7
+#define INTCICDIPTR8 INTC.ICDIPTR8
+#define INTCICDIPTR9 INTC.ICDIPTR9
+#define INTCICDIPTR10 INTC.ICDIPTR10
+#define INTCICDIPTR11 INTC.ICDIPTR11
+#define INTCICDIPTR12 INTC.ICDIPTR12
+#define INTCICDIPTR13 INTC.ICDIPTR13
+#define INTCICDIPTR14 INTC.ICDIPTR14
+#define INTCICDIPTR15 INTC.ICDIPTR15
+#define INTCICDIPTR16 INTC.ICDIPTR16
+#define INTCICDIPTR17 INTC.ICDIPTR17
+#define INTCICDIPTR18 INTC.ICDIPTR18
+#define INTCICDIPTR19 INTC.ICDIPTR19
+#define INTCICDIPTR20 INTC.ICDIPTR20
+#define INTCICDIPTR21 INTC.ICDIPTR21
+#define INTCICDIPTR22 INTC.ICDIPTR22
+#define INTCICDIPTR23 INTC.ICDIPTR23
+#define INTCICDIPTR24 INTC.ICDIPTR24
+#define INTCICDIPTR25 INTC.ICDIPTR25
+#define INTCICDIPTR26 INTC.ICDIPTR26
+#define INTCICDIPTR27 INTC.ICDIPTR27
+#define INTCICDIPTR28 INTC.ICDIPTR28
+#define INTCICDIPTR29 INTC.ICDIPTR29
+#define INTCICDIPTR30 INTC.ICDIPTR30
+#define INTCICDIPTR31 INTC.ICDIPTR31
+#define INTCICDIPTR32 INTC.ICDIPTR32
+#define INTCICDIPTR33 INTC.ICDIPTR33
+#define INTCICDIPTR34 INTC.ICDIPTR34
+#define INTCICDIPTR35 INTC.ICDIPTR35
+#define INTCICDIPTR36 INTC.ICDIPTR36
+#define INTCICDIPTR37 INTC.ICDIPTR37
+#define INTCICDIPTR38 INTC.ICDIPTR38
+#define INTCICDIPTR39 INTC.ICDIPTR39
+#define INTCICDIPTR40 INTC.ICDIPTR40
+#define INTCICDIPTR41 INTC.ICDIPTR41
+#define INTCICDIPTR42 INTC.ICDIPTR42
+#define INTCICDIPTR43 INTC.ICDIPTR43
+#define INTCICDIPTR44 INTC.ICDIPTR44
+#define INTCICDIPTR45 INTC.ICDIPTR45
+#define INTCICDIPTR46 INTC.ICDIPTR46
+#define INTCICDIPTR47 INTC.ICDIPTR47
+#define INTCICDIPTR48 INTC.ICDIPTR48
+#define INTCICDIPTR49 INTC.ICDIPTR49
+#define INTCICDIPTR50 INTC.ICDIPTR50
+#define INTCICDIPTR51 INTC.ICDIPTR51
+#define INTCICDIPTR52 INTC.ICDIPTR52
+#define INTCICDIPTR53 INTC.ICDIPTR53
+#define INTCICDIPTR54 INTC.ICDIPTR54
+#define INTCICDIPTR55 INTC.ICDIPTR55
+#define INTCICDIPTR56 INTC.ICDIPTR56
+#define INTCICDIPTR57 INTC.ICDIPTR57
+#define INTCICDIPTR58 INTC.ICDIPTR58
+#define INTCICDIPTR59 INTC.ICDIPTR59
+#define INTCICDIPTR60 INTC.ICDIPTR60
+#define INTCICDIPTR61 INTC.ICDIPTR61
+#define INTCICDIPTR62 INTC.ICDIPTR62
+#define INTCICDIPTR63 INTC.ICDIPTR63
+#define INTCICDIPTR64 INTC.ICDIPTR64
+#define INTCICDIPTR65 INTC.ICDIPTR65
+#define INTCICDIPTR66 INTC.ICDIPTR66
+#define INTCICDIPTR67 INTC.ICDIPTR67
+#define INTCICDIPTR68 INTC.ICDIPTR68
+#define INTCICDIPTR69 INTC.ICDIPTR69
+#define INTCICDIPTR70 INTC.ICDIPTR70
+#define INTCICDIPTR71 INTC.ICDIPTR71
+#define INTCICDIPTR72 INTC.ICDIPTR72
+#define INTCICDIPTR73 INTC.ICDIPTR73
+#define INTCICDIPTR74 INTC.ICDIPTR74
+#define INTCICDIPTR75 INTC.ICDIPTR75
+#define INTCICDIPTR76 INTC.ICDIPTR76
+#define INTCICDIPTR77 INTC.ICDIPTR77
+#define INTCICDIPTR78 INTC.ICDIPTR78
+#define INTCICDIPTR79 INTC.ICDIPTR79
+#define INTCICDIPTR80 INTC.ICDIPTR80
+#define INTCICDIPTR81 INTC.ICDIPTR81
+#define INTCICDIPTR82 INTC.ICDIPTR82
+#define INTCICDIPTR83 INTC.ICDIPTR83
+#define INTCICDIPTR84 INTC.ICDIPTR84
+#define INTCICDIPTR85 INTC.ICDIPTR85
+#define INTCICDIPTR86 INTC.ICDIPTR86
+#define INTCICDIPTR87 INTC.ICDIPTR87
+#define INTCICDIPTR88 INTC.ICDIPTR88
+#define INTCICDIPTR89 INTC.ICDIPTR89
+#define INTCICDIPTR90 INTC.ICDIPTR90
+#define INTCICDIPTR91 INTC.ICDIPTR91
+#define INTCICDIPTR92 INTC.ICDIPTR92
+#define INTCICDIPTR93 INTC.ICDIPTR93
+#define INTCICDIPTR94 INTC.ICDIPTR94
+#define INTCICDIPTR95 INTC.ICDIPTR95
+#define INTCICDIPTR96 INTC.ICDIPTR96
+#define INTCICDIPTR97 INTC.ICDIPTR97
+#define INTCICDIPTR98 INTC.ICDIPTR98
+#define INTCICDIPTR99 INTC.ICDIPTR99
+#define INTCICDIPTR100 INTC.ICDIPTR100
+#define INTCICDIPTR101 INTC.ICDIPTR101
+#define INTCICDIPTR102 INTC.ICDIPTR102
+#define INTCICDIPTR103 INTC.ICDIPTR103
+#define INTCICDIPTR104 INTC.ICDIPTR104
+#define INTCICDIPTR105 INTC.ICDIPTR105
+#define INTCICDIPTR106 INTC.ICDIPTR106
+#define INTCICDIPTR107 INTC.ICDIPTR107
+#define INTCICDIPTR108 INTC.ICDIPTR108
+#define INTCICDIPTR109 INTC.ICDIPTR109
+#define INTCICDIPTR110 INTC.ICDIPTR110
+#define INTCICDIPTR111 INTC.ICDIPTR111
+#define INTCICDIPTR112 INTC.ICDIPTR112
+#define INTCICDIPTR113 INTC.ICDIPTR113
+#define INTCICDIPTR114 INTC.ICDIPTR114
+#define INTCICDIPTR115 INTC.ICDIPTR115
+#define INTCICDIPTR116 INTC.ICDIPTR116
+#define INTCICDIPTR117 INTC.ICDIPTR117
+#define INTCICDIPTR118 INTC.ICDIPTR118
+#define INTCICDIPTR119 INTC.ICDIPTR119
+#define INTCICDIPTR120 INTC.ICDIPTR120
+#define INTCICDIPTR121 INTC.ICDIPTR121
+#define INTCICDIPTR122 INTC.ICDIPTR122
+#define INTCICDIPTR123 INTC.ICDIPTR123
+#define INTCICDIPTR124 INTC.ICDIPTR124
+#define INTCICDIPTR125 INTC.ICDIPTR125
+#define INTCICDIPTR126 INTC.ICDIPTR126
+#define INTCICDIPTR127 INTC.ICDIPTR127
+#define INTCICDIPTR128 INTC.ICDIPTR128
+#define INTCICDIPTR129 INTC.ICDIPTR129
+#define INTCICDIPTR130 INTC.ICDIPTR130
+#define INTCICDIPTR131 INTC.ICDIPTR131
+#define INTCICDIPTR132 INTC.ICDIPTR132
+#define INTCICDIPTR133 INTC.ICDIPTR133
+#define INTCICDIPTR134 INTC.ICDIPTR134
+#define INTCICDIPTR135 INTC.ICDIPTR135
+#define INTCICDIPTR136 INTC.ICDIPTR136
+#define INTCICDIPTR137 INTC.ICDIPTR137
+#define INTCICDIPTR138 INTC.ICDIPTR138
+#define INTCICDIPTR139 INTC.ICDIPTR139
+#define INTCICDIPTR140 INTC.ICDIPTR140
+#define INTCICDIPTR141 INTC.ICDIPTR141
+#define INTCICDIPTR142 INTC.ICDIPTR142
+#define INTCICDIPTR143 INTC.ICDIPTR143
+#define INTCICDIPTR144 INTC.ICDIPTR144
+#define INTCICDIPTR145 INTC.ICDIPTR145
+#define INTCICDIPTR146 INTC.ICDIPTR146
+#define INTCICDICFR0 INTC.ICDICFR0
+#define INTCICDICFR1 INTC.ICDICFR1
+#define INTCICDICFR2 INTC.ICDICFR2
+#define INTCICDICFR3 INTC.ICDICFR3
+#define INTCICDICFR4 INTC.ICDICFR4
+#define INTCICDICFR5 INTC.ICDICFR5
+#define INTCICDICFR6 INTC.ICDICFR6
+#define INTCICDICFR7 INTC.ICDICFR7
+#define INTCICDICFR8 INTC.ICDICFR8
+#define INTCICDICFR9 INTC.ICDICFR9
+#define INTCICDICFR10 INTC.ICDICFR10
+#define INTCICDICFR11 INTC.ICDICFR11
+#define INTCICDICFR12 INTC.ICDICFR12
+#define INTCICDICFR13 INTC.ICDICFR13
+#define INTCICDICFR14 INTC.ICDICFR14
+#define INTCICDICFR15 INTC.ICDICFR15
+#define INTCICDICFR16 INTC.ICDICFR16
+#define INTCICDICFR17 INTC.ICDICFR17
+#define INTCICDICFR18 INTC.ICDICFR18
+#define INTCICDICFR19 INTC.ICDICFR19
+#define INTCICDICFR20 INTC.ICDICFR20
+#define INTCICDICFR21 INTC.ICDICFR21
+#define INTCICDICFR22 INTC.ICDICFR22
+#define INTCICDICFR23 INTC.ICDICFR23
+#define INTCICDICFR24 INTC.ICDICFR24
+#define INTCICDICFR25 INTC.ICDICFR25
+#define INTCICDICFR26 INTC.ICDICFR26
+#define INTCICDICFR27 INTC.ICDICFR27
+#define INTCICDICFR28 INTC.ICDICFR28
+#define INTCICDICFR29 INTC.ICDICFR29
+#define INTCICDICFR30 INTC.ICDICFR30
+#define INTCICDICFR31 INTC.ICDICFR31
+#define INTCICDICFR32 INTC.ICDICFR32
+#define INTCICDICFR33 INTC.ICDICFR33
+#define INTCICDICFR34 INTC.ICDICFR34
+#define INTCICDICFR35 INTC.ICDICFR35
+#define INTCICDICFR36 INTC.ICDICFR36
+#define INTCPPI_STATUS INTC.PPI_STATUS
+#define INTCSPI_STATUS0 INTC.SPI_STATUS0
+#define INTCSPI_STATUS1 INTC.SPI_STATUS1
+#define INTCSPI_STATUS2 INTC.SPI_STATUS2
+#define INTCSPI_STATUS3 INTC.SPI_STATUS3
+#define INTCSPI_STATUS4 INTC.SPI_STATUS4
+#define INTCSPI_STATUS5 INTC.SPI_STATUS5
+#define INTCSPI_STATUS6 INTC.SPI_STATUS6
+#define INTCSPI_STATUS7 INTC.SPI_STATUS7
+#define INTCSPI_STATUS8 INTC.SPI_STATUS8
+#define INTCSPI_STATUS9 INTC.SPI_STATUS9
+#define INTCSPI_STATUS10 INTC.SPI_STATUS10
+#define INTCSPI_STATUS11 INTC.SPI_STATUS11
+#define INTCSPI_STATUS12 INTC.SPI_STATUS12
+#define INTCSPI_STATUS13 INTC.SPI_STATUS13
+#define INTCSPI_STATUS14 INTC.SPI_STATUS14
+#define INTCSPI_STATUS15 INTC.SPI_STATUS15
+#define INTCSPI_STATUS16 INTC.SPI_STATUS16
+#define INTCICDSGIR INTC.ICDSGIR
+#define INTCICCICR INTC.ICCICR
+#define INTCICCPMR INTC.ICCPMR
+#define INTCICCBPR INTC.ICCBPR
+#define INTCICCIAR INTC.ICCIAR
+#define INTCICCEOIR INTC.ICCEOIR
+#define INTCICCRPR INTC.ICCRPR
+#define INTCICCHPIR INTC.ICCHPIR
+#define INTCICCABPR INTC.ICCABPR
+#define INTCICCIIDR INTC.ICCIIDR
+#define INTCICR0 INTC.ICR0
+#define INTCICR1 INTC.ICR1
+#define INTCIRQRR INTC.IRQRR
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,43 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : irda_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef IRDA_IODEFINE_H
+#define IRDA_IODEFINE_H
+
+struct st_irda
+{ /* IRDA */
+ volatile uint8_t IRCR; /* IRCR */
+};
+
+
+#define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */
+
+
+#define IRDAIRCR IRDA.IRCR
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,170 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : jcu_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef JCU_IODEFINE_H
+#define JCU_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_jcu
+{ /* JCU */
+ volatile uint8_t JCMOD; /* JCMOD */
+ volatile uint8_t JCCMD; /* JCCMD */
+ volatile uint8_t dummy145[1]; /* */
+ volatile uint8_t JCQTN; /* JCQTN */
+ volatile uint8_t JCHTN; /* JCHTN */
+ volatile uint8_t JCDRIU; /* JCDRIU */
+ volatile uint8_t JCDRID; /* JCDRID */
+ volatile uint8_t JCVSZU; /* JCVSZU */
+ volatile uint8_t JCVSZD; /* JCVSZD */
+ volatile uint8_t JCHSZU; /* JCHSZU */
+ volatile uint8_t JCHSZD; /* JCHSZD */
+ volatile uint8_t JCDTCU; /* JCDTCU */
+ volatile uint8_t JCDTCM; /* JCDTCM */
+ volatile uint8_t JCDTCD; /* JCDTCD */
+ volatile uint8_t JINTE0; /* JINTE0 */
+ volatile uint8_t JINTS0; /* JINTS0 */
+ volatile uint8_t JCDERR; /* JCDERR */
+ volatile uint8_t JCRST; /* JCRST */
+ volatile uint8_t dummy146[46]; /* */
+ volatile uint32_t JIFECNT; /* JIFECNT */
+ volatile uint32_t JIFESA; /* JIFESA */
+ volatile uint32_t JIFESOFST; /* JIFESOFST */
+ volatile uint32_t JIFEDA; /* JIFEDA */
+ volatile uint32_t JIFESLC; /* JIFESLC */
+ volatile uint32_t JIFEDDC; /* JIFEDDC */
+ volatile uint32_t JIFDCNT; /* JIFDCNT */
+ volatile uint32_t JIFDSA; /* JIFDSA */
+ volatile uint32_t JIFDDOFST; /* JIFDDOFST */
+ volatile uint32_t JIFDDA; /* JIFDDA */
+ volatile uint32_t JIFDSDC; /* JIFDSDC */
+ volatile uint32_t JIFDDLC; /* JIFDDLC */
+ volatile uint32_t JIFDADT; /* JIFDADT */
+ volatile uint8_t dummy147[24]; /* */
+ volatile uint32_t JINTE1; /* JINTE1 */
+ volatile uint32_t JINTS1; /* JINTS1 */
+ volatile uint32_t JIFESVSZ; /* JIFESVSZ */
+ volatile uint32_t JIFESHSZ; /* JIFESHSZ */
+ volatile uint8_t dummy148[100]; /* */
+/* start of struct st_jcu_from_jcqtbl0 */
+ volatile uint8_t JCQTBL0; /* JCQTBL0 */
+ volatile uint8_t dummy149[63]; /* */
+/* end of struct st_jcu_from_jcqtbl0 */
+/* start of struct st_jcu_from_jcqtbl0 */
+ volatile uint8_t JCQTBL1; /* JCQTBL1 */
+ volatile uint8_t dummy150[63]; /* */
+/* end of struct st_jcu_from_jcqtbl0 */
+/* start of struct st_jcu_from_jcqtbl0 */
+ volatile uint8_t JCQTBL2; /* JCQTBL2 */
+ volatile uint8_t dummy151[63]; /* */
+/* end of struct st_jcu_from_jcqtbl0 */
+/* start of struct st_jcu_from_jcqtbl0 */
+ volatile uint8_t JCQTBL3; /* JCQTBL3 */
+ volatile uint8_t dummy152[63]; /* */
+/* end of struct st_jcu_from_jcqtbl0 */
+ volatile uint8_t JCHTBD0; /* JCHTBD0 */
+ volatile uint8_t dummy153[31]; /* */
+ volatile uint8_t JCHTBA0; /* JCHTBA0 */
+ volatile uint8_t dummy154[223]; /* */
+ volatile uint8_t JCHTBD1; /* JCHTBD1 */
+ volatile uint8_t dummy155[31]; /* */
+ volatile uint8_t JCHTBA1; /* JCHTBA1 */
+};
+
+
+struct st_jcu_from_jcqtbl0
+{
+ volatile uint8_t JCQTBL0; /* JCQTBL0 */
+ volatile uint8_t dummy1[63]; /* */
+};
+
+
+#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */
+
+
+/* Start of channnel array defines of JCU */
+
+/* Channnel array defines of JCU_JCQTBL0 */
+/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
+#define JCU_JCQTBL0_COUNT 4
+#define JCU_JCQTBL0_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
+#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
+#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
+#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
+
+/* End of channnel array defines of JCU */
+
+
+#define JCUJCMOD JCU.JCMOD
+#define JCUJCCMD JCU.JCCMD
+#define JCUJCQTN JCU.JCQTN
+#define JCUJCHTN JCU.JCHTN
+#define JCUJCDRIU JCU.JCDRIU
+#define JCUJCDRID JCU.JCDRID
+#define JCUJCVSZU JCU.JCVSZU
+#define JCUJCVSZD JCU.JCVSZD
+#define JCUJCHSZU JCU.JCHSZU
+#define JCUJCHSZD JCU.JCHSZD
+#define JCUJCDTCU JCU.JCDTCU
+#define JCUJCDTCM JCU.JCDTCM
+#define JCUJCDTCD JCU.JCDTCD
+#define JCUJINTE0 JCU.JINTE0
+#define JCUJINTS0 JCU.JINTS0
+#define JCUJCDERR JCU.JCDERR
+#define JCUJCRST JCU.JCRST
+#define JCUJIFECNT JCU.JIFECNT
+#define JCUJIFESA JCU.JIFESA
+#define JCUJIFESOFST JCU.JIFESOFST
+#define JCUJIFEDA JCU.JIFEDA
+#define JCUJIFESLC JCU.JIFESLC
+#define JCUJIFEDDC JCU.JIFEDDC
+#define JCUJIFDCNT JCU.JIFDCNT
+#define JCUJIFDSA JCU.JIFDSA
+#define JCUJIFDDOFST JCU.JIFDDOFST
+#define JCUJIFDDA JCU.JIFDDA
+#define JCUJIFDSDC JCU.JIFDSDC
+#define JCUJIFDDLC JCU.JIFDDLC
+#define JCUJIFDADT JCU.JIFDADT
+#define JCUJINTE1 JCU.JINTE1
+#define JCUJINTS1 JCU.JINTS1
+#define JCUJIFESVSZ JCU.JIFESVSZ
+#define JCUJIFESHSZ JCU.JIFESHSZ
+#define JCUJCQTBL0 JCU.JCQTBL0
+#define JCUJCQTBL1 JCU.JCQTBL1
+#define JCUJCQTBL2 JCU.JCQTBL2
+#define JCUJCQTBL3 JCU.JCQTBL3
+#define JCUJCHTBD0 JCU.JCHTBD0
+#define JCUJCHTBA0 JCU.JCHTBA0
+#define JCUJCHTBD1 JCU.JCHTBD1
+#define JCUJCHTBA1 JCU.JCHTBA1
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,196 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : l2c_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef L2C_IODEFINE_H
+#define L2C_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_l2c
+{ /* L2C */
+ volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */
+ volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */
+ volatile uint8_t dummy8[248]; /* */
+ volatile uint32_t REG1_CONTROL; /* REG1_CONTROL */
+ volatile uint32_t REG1_AUX_CONTROL; /* REG1_AUX_CONTROL */
+ volatile uint32_t REG1_TAG_RAM_CONTROL; /* REG1_TAG_RAM_CONTROL */
+ volatile uint32_t REG1_DATA_RAM_CONTROL; /* REG1_DATA_RAM_CONTROL */
+ volatile uint8_t dummy9[240]; /* */
+ volatile uint32_t REG2_EV_COUNTER_CTRL; /* REG2_EV_COUNTER_CTRL */
+ volatile uint32_t REG2_EV_COUNTER1_CFG; /* REG2_EV_COUNTER1_CFG */
+ volatile uint32_t REG2_EV_COUNTER0_CFG; /* REG2_EV_COUNTER0_CFG */
+ volatile uint32_t REG2_EV_COUNTER1; /* REG2_EV_COUNTER1 */
+ volatile uint32_t REG2_EV_COUNTER0; /* REG2_EV_COUNTER0 */
+ volatile uint32_t REG2_INT_MASK; /* REG2_INT_MASK */
+ volatile uint32_t REG2_INT_MASK_STATUS; /* REG2_INT_MASK_STATUS */
+ volatile uint32_t REG2_INT_RAW_STATUS; /* REG2_INT_RAW_STATUS */
+ volatile uint32_t REG2_INT_CLEAR; /* REG2_INT_CLEAR */
+ volatile uint8_t dummy10[1292]; /* */
+ volatile uint32_t REG7_CACHE_SYNC; /* REG7_CACHE_SYNC */
+ volatile uint8_t dummy11[60]; /* */
+ volatile uint32_t REG7_INV_PA; /* REG7_INV_PA */
+ volatile uint8_t dummy12[8]; /* */
+ volatile uint32_t REG7_INV_WAY; /* REG7_INV_WAY */
+ volatile uint8_t dummy13[48]; /* */
+ volatile uint32_t REG7_CLEAN_PA; /* REG7_CLEAN_PA */
+ volatile uint8_t dummy14[4]; /* */
+ volatile uint32_t REG7_CLEAN_INDEX; /* REG7_CLEAN_INDEX */
+ volatile uint32_t REG7_CLEAN_WAY; /* REG7_CLEAN_WAY */
+ volatile uint8_t dummy15[48]; /* */
+ volatile uint32_t REG7_CLEAN_INV_PA; /* REG7_CLEAN_INV_PA */
+ volatile uint8_t dummy16[4]; /* */
+ volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */
+ volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */
+ volatile uint8_t dummy17[256]; /* */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
+ volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */
+ volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */
+ volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */
+ volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */
+ volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */
+ volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */
+ volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */
+ volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+ volatile uint8_t dummy18[16]; /* */
+ volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */
+ volatile uint32_t REG9_UNLOCK_WAY; /* REG9_UNLOCK_WAY */
+ volatile uint8_t dummy19[680]; /* */
+ volatile uint32_t REG12_ADDR_FILTERING_START; /* REG12_ADDR_FILTERING_START */
+ volatile uint32_t REG12_ADDR_FILTERING_END; /* REG12_ADDR_FILTERING_END */
+ volatile uint8_t dummy20[824]; /* */
+ volatile uint32_t REG15_DEBUG_CTRL; /* REG15_DEBUG_CTRL */
+ volatile uint8_t dummy21[28]; /* */
+ volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */
+ volatile uint8_t dummy22[28]; /* */
+ volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */
+};
+
+
+struct st_l2c_from_reg9_d_lockdown0
+{
+ volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
+ volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
+};
+
+
+#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */
+
+
+/* Start of channnel array defines of L2C */
+
+/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
+/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
+#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT 8
+#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
+#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
+#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
+#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
+#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
+#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
+#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
+#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
+
+/* End of channnel array defines of L2C */
+
+
+#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID
+#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE
+#define L2CREG1_CONTROL L2C.REG1_CONTROL
+#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL
+#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL
+#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL
+#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL
+#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG
+#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG
+#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1
+#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0
+#define L2CREG2_INT_MASK L2C.REG2_INT_MASK
+#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS
+#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS
+#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR
+#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC
+#define L2CREG7_INV_PA L2C.REG7_INV_PA
+#define L2CREG7_INV_WAY L2C.REG7_INV_WAY
+#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA
+#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX
+#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY
+#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA
+#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX
+#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY
+#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0
+#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0
+#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1
+#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1
+#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2
+#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2
+#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3
+#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3
+#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4
+#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4
+#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5
+#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5
+#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6
+#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6
+#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7
+#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7
+#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN
+#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY
+#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START
+#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END
+#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL
+#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL
+#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,175 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : lin_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef LIN_IODEFINE_H
+#define LIN_IODEFINE_H
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_lin
+{ /* LIN */
+ volatile uint8_t dummy1[1]; /* */
+ volatile uint8_t RLN3nLWBR; /* RLN3nLWBR */
+ union iodefine_reg16_8_t RLN3nLBRP01; /* RLN3nLBRP01 */
+
+ volatile uint8_t RLN3nLSTC; /* RLN3nLSTC */
+ volatile uint8_t dummy2[3]; /* */
+ volatile uint8_t RLN3nLMD; /* RLN3nLMD */
+ volatile uint8_t RLN3nLBFC; /* RLN3nLBFC */
+ volatile uint8_t RLN3nLSC; /* RLN3nLSC */
+ volatile uint8_t RLN3nLWUP; /* RLN3nLWUP */
+ volatile uint8_t RLN3nLIE; /* RLN3nLIE */
+ volatile uint8_t RLN3nLEDE; /* RLN3nLEDE */
+ volatile uint8_t RLN3nLCUC; /* RLN3nLCUC */
+ volatile uint8_t dummy3[1]; /* */
+ volatile uint8_t RLN3nLTRC; /* RLN3nLTRC */
+ volatile uint8_t RLN3nLMST; /* RLN3nLMST */
+ volatile uint8_t RLN3nLST; /* RLN3nLST */
+ volatile uint8_t RLN3nLEST; /* RLN3nLEST */
+ volatile uint8_t RLN3nLDFC; /* RLN3nLDFC */
+ volatile uint8_t RLN3nLIDB; /* RLN3nLIDB */
+ volatile uint8_t RLN3nLCBR; /* RLN3nLCBR */
+ volatile uint8_t RLN3nLUDB0; /* RLN3nLUDB0 */
+#define LIN_LDBn_COUNT 8
+ volatile uint8_t RLN3nLDBR1; /* RLN3nLDBR1 */
+ volatile uint8_t RLN3nLDBR2; /* RLN3nLDBR2 */
+ volatile uint8_t RLN3nLDBR3; /* RLN3nLDBR3 */
+ volatile uint8_t RLN3nLDBR4; /* RLN3nLDBR4 */
+ volatile uint8_t RLN3nLDBR5; /* RLN3nLDBR5 */
+ volatile uint8_t RLN3nLDBR6; /* RLN3nLDBR6 */
+ volatile uint8_t RLN3nLDBR7; /* RLN3nLDBR7 */
+ volatile uint8_t RLN3nLDBR8; /* RLN3nLDBR8 */
+ volatile uint8_t RLN3nLUOER; /* RLN3nLUOER */
+ volatile uint8_t RLN3nLUOR1; /* RLN3nLUOR1 */
+ volatile uint8_t dummy4[2]; /* */
+ union iodefine_reg16_8_t RLN3nLUTDR; /* RLN3nLUTDR */
+ union iodefine_reg16_8_t RLN3nLURDR; /* RLN3nLURDR */
+ union iodefine_reg16_8_t RLN3nLUWTDR; /* RLN3nLUWTDR */
+
+};
+
+
+#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */
+#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */
+
+
+/* Start of channnel array defines of LIN */
+
+/* Channnel array defines of LIN */
+/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
+#define LIN_COUNT 2
+#define LIN_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &LIN0, &LIN1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of LIN */
+
+
+#define LIN0RLN30LWBR LIN0.RLN3nLWBR
+#define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16
+#define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L]
+#define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H]
+#define LIN0RLN30LSTC LIN0.RLN3nLSTC
+#define LIN0RLN30LMD LIN0.RLN3nLMD
+#define LIN0RLN30LBFC LIN0.RLN3nLBFC
+#define LIN0RLN30LSC LIN0.RLN3nLSC
+#define LIN0RLN30LWUP LIN0.RLN3nLWUP
+#define LIN0RLN30LIE LIN0.RLN3nLIE
+#define LIN0RLN30LEDE LIN0.RLN3nLEDE
+#define LIN0RLN30LCUC LIN0.RLN3nLCUC
+#define LIN0RLN30LTRC LIN0.RLN3nLTRC
+#define LIN0RLN30LMST LIN0.RLN3nLMST
+#define LIN0RLN30LST LIN0.RLN3nLST
+#define LIN0RLN30LEST LIN0.RLN3nLEST
+#define LIN0RLN30LDFC LIN0.RLN3nLDFC
+#define LIN0RLN30LIDB LIN0.RLN3nLIDB
+#define LIN0RLN30LCBR LIN0.RLN3nLCBR
+#define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0
+#define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1
+#define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2
+#define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3
+#define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4
+#define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5
+#define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6
+#define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7
+#define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8
+#define LIN0RLN30LUOER LIN0.RLN3nLUOER
+#define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1
+#define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16
+#define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L]
+#define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H]
+#define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16
+#define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L]
+#define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H]
+#define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16
+#define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L]
+#define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H]
+#define LIN1RLN31LWBR LIN1.RLN3nLWBR
+#define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16
+#define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L]
+#define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H]
+#define LIN1RLN31LSTC LIN1.RLN3nLSTC
+#define LIN1RLN31LMD LIN1.RLN3nLMD
+#define LIN1RLN31LBFC LIN1.RLN3nLBFC
+#define LIN1RLN31LSC LIN1.RLN3nLSC
+#define LIN1RLN31LWUP LIN1.RLN3nLWUP
+#define LIN1RLN31LIE LIN1.RLN3nLIE
+#define LIN1RLN31LEDE LIN1.RLN3nLEDE
+#define LIN1RLN31LCUC LIN1.RLN3nLCUC
+#define LIN1RLN31LTRC LIN1.RLN3nLTRC
+#define LIN1RLN31LMST LIN1.RLN3nLMST
+#define LIN1RLN31LST LIN1.RLN3nLST
+#define LIN1RLN31LEST LIN1.RLN3nLEST
+#define LIN1RLN31LDFC LIN1.RLN3nLDFC
+#define LIN1RLN31LIDB LIN1.RLN3nLIDB
+#define LIN1RLN31LCBR LIN1.RLN3nLCBR
+#define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0
+#define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1
+#define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2
+#define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3
+#define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4
+#define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5
+#define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6
+#define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7
+#define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8
+#define LIN1RLN31LUOER LIN1.RLN3nLUOER
+#define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1
+#define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16
+#define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L]
+#define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H]
+#define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16
+#define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L]
+#define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H]
+#define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16
+#define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L]
+#define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H]
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,55 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : lvds_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.01a)
+******************************************************************************/
+#ifndef LVDS_IODEFINE_H
+#define LVDS_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_lvds
+{ /* LVDS */
+ volatile uint32_t LVDS_UPDATE; /* LVDS_UPDATE */
+ volatile uint32_t LVDSFCL; /* LVDSFCL */
+ volatile uint8_t dummy608[24]; /* */
+ volatile uint32_t LCLKSELR; /* LCLKSELR */
+ volatile uint32_t LPLLSETR; /* LPLLSETR */
+ volatile uint8_t dummy609[4]; /* */
+ volatile uint32_t LPHYACC; /* LPHYACC */
+};
+
+
+#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */
+
+
+#define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE
+#define LVDSLVDSFCL LVDS.LVDSFCL
+#define LVDSLCLKSELR LVDS.LCLKSELR
+#define LVDSLPLLSETR LVDS.LPLLSETR
+#define LVDSLPHYACC LVDS.LPHYACC
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,499 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mlb_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef MLB_IODEFINE_H
+#define MLB_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_mlb
+{ /* MLB */
+ volatile uint32_t DCCR; /* DCCR */
+ volatile uint32_t SSCR; /* SSCR */
+ volatile uint32_t SDCR; /* SDCR */
+ volatile uint32_t SMCR; /* SMCR */
+ volatile uint8_t dummy156[12]; /* */
+ volatile uint32_t VCCR; /* VCCR */
+ volatile uint32_t SBCR; /* SBCR */
+ volatile uint32_t ABCR; /* ABCR */
+ volatile uint32_t CBCR; /* CBCR */
+ volatile uint32_t IBCR; /* IBCR */
+ volatile uint32_t CICR; /* CICR */
+ volatile uint8_t dummy157[12]; /* */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR0; /* CECR0 */
+ volatile uint32_t CSCR0; /* CSCR0 */
+ volatile uint32_t CCBCR0; /* CCBCR0 */
+ volatile uint32_t CNBCR0; /* CNBCR0 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR1; /* CECR1 */
+ volatile uint32_t CSCR1; /* CSCR1 */
+ volatile uint32_t CCBCR1; /* CCBCR1 */
+ volatile uint32_t CNBCR1; /* CNBCR1 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR2; /* CECR2 */
+ volatile uint32_t CSCR2; /* CSCR2 */
+ volatile uint32_t CCBCR2; /* CCBCR2 */
+ volatile uint32_t CNBCR2; /* CNBCR2 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR3; /* CECR3 */
+ volatile uint32_t CSCR3; /* CSCR3 */
+ volatile uint32_t CCBCR3; /* CCBCR3 */
+ volatile uint32_t CNBCR3; /* CNBCR3 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR4; /* CECR4 */
+ volatile uint32_t CSCR4; /* CSCR4 */
+ volatile uint32_t CCBCR4; /* CCBCR4 */
+ volatile uint32_t CNBCR4; /* CNBCR4 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR5; /* CECR5 */
+ volatile uint32_t CSCR5; /* CSCR5 */
+ volatile uint32_t CCBCR5; /* CCBCR5 */
+ volatile uint32_t CNBCR5; /* CNBCR5 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR6; /* CECR6 */
+ volatile uint32_t CSCR6; /* CSCR6 */
+ volatile uint32_t CCBCR6; /* CCBCR6 */
+ volatile uint32_t CNBCR6; /* CNBCR6 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR7; /* CECR7 */
+ volatile uint32_t CSCR7; /* CSCR7 */
+ volatile uint32_t CCBCR7; /* CCBCR7 */
+ volatile uint32_t CNBCR7; /* CNBCR7 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR8; /* CECR8 */
+ volatile uint32_t CSCR8; /* CSCR8 */
+ volatile uint32_t CCBCR8; /* CCBCR8 */
+ volatile uint32_t CNBCR8; /* CNBCR8 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR9; /* CECR9 */
+ volatile uint32_t CSCR9; /* CSCR9 */
+ volatile uint32_t CCBCR9; /* CCBCR9 */
+ volatile uint32_t CNBCR9; /* CNBCR9 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR10; /* CECR10 */
+ volatile uint32_t CSCR10; /* CSCR10 */
+ volatile uint32_t CCBCR10; /* CCBCR10 */
+ volatile uint32_t CNBCR10; /* CNBCR10 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR11; /* CECR11 */
+ volatile uint32_t CSCR11; /* CSCR11 */
+ volatile uint32_t CCBCR11; /* CCBCR11 */
+ volatile uint32_t CNBCR11; /* CNBCR11 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR12; /* CECR12 */
+ volatile uint32_t CSCR12; /* CSCR12 */
+ volatile uint32_t CCBCR12; /* CCBCR12 */
+ volatile uint32_t CNBCR12; /* CNBCR12 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR13; /* CECR13 */
+ volatile uint32_t CSCR13; /* CSCR13 */
+ volatile uint32_t CCBCR13; /* CCBCR13 */
+ volatile uint32_t CNBCR13; /* CNBCR13 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR14; /* CECR14 */
+ volatile uint32_t CSCR14; /* CSCR14 */
+ volatile uint32_t CCBCR14; /* CCBCR14 */
+ volatile uint32_t CNBCR14; /* CNBCR14 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR15; /* CECR15 */
+ volatile uint32_t CSCR15; /* CSCR15 */
+ volatile uint32_t CCBCR15; /* CCBCR15 */
+ volatile uint32_t CNBCR15; /* CNBCR15 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR16; /* CECR16 */
+ volatile uint32_t CSCR16; /* CSCR16 */
+ volatile uint32_t CCBCR16; /* CCBCR16 */
+ volatile uint32_t CNBCR16; /* CNBCR16 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR17; /* CECR17 */
+ volatile uint32_t CSCR17; /* CSCR17 */
+ volatile uint32_t CCBCR17; /* CCBCR17 */
+ volatile uint32_t CNBCR17; /* CNBCR17 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR18; /* CECR18 */
+ volatile uint32_t CSCR18; /* CSCR18 */
+ volatile uint32_t CCBCR18; /* CCBCR18 */
+ volatile uint32_t CNBCR18; /* CNBCR18 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR19; /* CECR19 */
+ volatile uint32_t CSCR19; /* CSCR19 */
+ volatile uint32_t CCBCR19; /* CCBCR19 */
+ volatile uint32_t CNBCR19; /* CNBCR19 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR20; /* CECR20 */
+ volatile uint32_t CSCR20; /* CSCR20 */
+ volatile uint32_t CCBCR20; /* CCBCR20 */
+ volatile uint32_t CNBCR20; /* CNBCR20 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR21; /* CECR21 */
+ volatile uint32_t CSCR21; /* CSCR21 */
+ volatile uint32_t CCBCR21; /* CCBCR21 */
+ volatile uint32_t CNBCR21; /* CNBCR21 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR22; /* CECR22 */
+ volatile uint32_t CSCR22; /* CSCR22 */
+ volatile uint32_t CCBCR22; /* CCBCR22 */
+ volatile uint32_t CNBCR22; /* CNBCR22 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR23; /* CECR23 */
+ volatile uint32_t CSCR23; /* CSCR23 */
+ volatile uint32_t CCBCR23; /* CCBCR23 */
+ volatile uint32_t CNBCR23; /* CNBCR23 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR24; /* CECR24 */
+ volatile uint32_t CSCR24; /* CSCR24 */
+ volatile uint32_t CCBCR24; /* CCBCR24 */
+ volatile uint32_t CNBCR24; /* CNBCR24 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR25; /* CECR25 */
+ volatile uint32_t CSCR25; /* CSCR25 */
+ volatile uint32_t CCBCR25; /* CCBCR25 */
+ volatile uint32_t CNBCR25; /* CNBCR25 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR26; /* CECR26 */
+ volatile uint32_t CSCR26; /* CSCR26 */
+ volatile uint32_t CCBCR26; /* CCBCR26 */
+ volatile uint32_t CNBCR26; /* CNBCR26 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR27; /* CECR27 */
+ volatile uint32_t CSCR27; /* CSCR27 */
+ volatile uint32_t CCBCR27; /* CCBCR27 */
+ volatile uint32_t CNBCR27; /* CNBCR27 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR28; /* CECR28 */
+ volatile uint32_t CSCR28; /* CSCR28 */
+ volatile uint32_t CCBCR28; /* CCBCR28 */
+ volatile uint32_t CNBCR28; /* CNBCR28 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR29; /* CECR29 */
+ volatile uint32_t CSCR29; /* CSCR29 */
+ volatile uint32_t CCBCR29; /* CCBCR29 */
+ volatile uint32_t CNBCR29; /* CNBCR29 */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+ volatile uint32_t CECR30; /* CECR30 */
+ volatile uint32_t CSCR30; /* CSCR30 */
+ volatile uint32_t CCBCR30; /* CCBCR30 */
+ volatile uint32_t CNBCR30; /* CNBCR30 */
+/* end of struct st_mlb_from_cecr0 */
+ volatile uint8_t dummy158[80]; /* */
+#define MLB_LCBCR0_COUNT 31
+ volatile uint32_t LCBCR0; /* LCBCR0 */
+ volatile uint32_t LCBCR1; /* LCBCR1 */
+ volatile uint32_t LCBCR2; /* LCBCR2 */
+ volatile uint32_t LCBCR3; /* LCBCR3 */
+ volatile uint32_t LCBCR4; /* LCBCR4 */
+ volatile uint32_t LCBCR5; /* LCBCR5 */
+ volatile uint32_t LCBCR6; /* LCBCR6 */
+ volatile uint32_t LCBCR7; /* LCBCR7 */
+ volatile uint32_t LCBCR8; /* LCBCR8 */
+ volatile uint32_t LCBCR9; /* LCBCR9 */
+ volatile uint32_t LCBCR10; /* LCBCR10 */
+ volatile uint32_t LCBCR11; /* LCBCR11 */
+ volatile uint32_t LCBCR12; /* LCBCR12 */
+ volatile uint32_t LCBCR13; /* LCBCR13 */
+ volatile uint32_t LCBCR14; /* LCBCR14 */
+ volatile uint32_t LCBCR15; /* LCBCR15 */
+ volatile uint32_t LCBCR16; /* LCBCR16 */
+ volatile uint32_t LCBCR17; /* LCBCR17 */
+ volatile uint32_t LCBCR18; /* LCBCR18 */
+ volatile uint32_t LCBCR19; /* LCBCR19 */
+ volatile uint32_t LCBCR20; /* LCBCR20 */
+ volatile uint32_t LCBCR21; /* LCBCR21 */
+ volatile uint32_t LCBCR22; /* LCBCR22 */
+ volatile uint32_t LCBCR23; /* LCBCR23 */
+ volatile uint32_t LCBCR24; /* LCBCR24 */
+ volatile uint32_t LCBCR25; /* LCBCR25 */
+ volatile uint32_t LCBCR26; /* LCBCR26 */
+ volatile uint32_t LCBCR27; /* LCBCR27 */
+ volatile uint32_t LCBCR28; /* LCBCR28 */
+ volatile uint32_t LCBCR29; /* LCBCR29 */
+ volatile uint32_t LCBCR30; /* LCBCR30 */
+};
+
+
+struct st_mlb_from_cecr0
+{
+ volatile uint32_t CECR0; /* CECR0 */
+ volatile uint32_t CSCR0; /* CSCR0 */
+ volatile uint32_t CCBCR0; /* CCBCR0 */
+ volatile uint32_t CNBCR0; /* CNBCR0 */
+};
+
+
+#define MLB (*(struct st_mlb *)0xE8034000uL) /* MLB */
+
+
+/* Start of channnel array defines of MLB */
+
+/* Channnel array defines of MLB_FROM_CECR0_ARRAY */
+/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */
+#define MLB_FROM_CECR0_ARRAY_COUNT 31
+#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \
+ &MLB_FROM_CECR8, &MLB_FROM_CECR9, &MLB_FROM_CECR10, &MLB_FROM_CECR11, &MLB_FROM_CECR12, &MLB_FROM_CECR13, &MLB_FROM_CECR14, &MLB_FROM_CECR15, \
+ &MLB_FROM_CECR16, &MLB_FROM_CECR17, &MLB_FROM_CECR18, &MLB_FROM_CECR19, &MLB_FROM_CECR20, &MLB_FROM_CECR21, &MLB_FROM_CECR22, &MLB_FROM_CECR23, \
+ &MLB_FROM_CECR24, &MLB_FROM_CECR25, &MLB_FROM_CECR26, &MLB_FROM_CECR27, &MLB_FROM_CECR28, &MLB_FROM_CECR29, &MLB_FROM_CECR30 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define MLB_FROM_CECR0 (*(struct st_mlb_from_cecr0 *)&MLB.CECR0) /* MLB_FROM_CECR0 */
+#define MLB_FROM_CECR1 (*(struct st_mlb_from_cecr0 *)&MLB.CECR1) /* MLB_FROM_CECR1 */
+#define MLB_FROM_CECR2 (*(struct st_mlb_from_cecr0 *)&MLB.CECR2) /* MLB_FROM_CECR2 */
+#define MLB_FROM_CECR3 (*(struct st_mlb_from_cecr0 *)&MLB.CECR3) /* MLB_FROM_CECR3 */
+#define MLB_FROM_CECR4 (*(struct st_mlb_from_cecr0 *)&MLB.CECR4) /* MLB_FROM_CECR4 */
+#define MLB_FROM_CECR5 (*(struct st_mlb_from_cecr0 *)&MLB.CECR5) /* MLB_FROM_CECR5 */
+#define MLB_FROM_CECR6 (*(struct st_mlb_from_cecr0 *)&MLB.CECR6) /* MLB_FROM_CECR6 */
+#define MLB_FROM_CECR7 (*(struct st_mlb_from_cecr0 *)&MLB.CECR7) /* MLB_FROM_CECR7 */
+#define MLB_FROM_CECR8 (*(struct st_mlb_from_cecr0 *)&MLB.CECR8) /* MLB_FROM_CECR8 */
+#define MLB_FROM_CECR9 (*(struct st_mlb_from_cecr0 *)&MLB.CECR9) /* MLB_FROM_CECR9 */
+#define MLB_FROM_CECR10 (*(struct st_mlb_from_cecr0 *)&MLB.CECR10) /* MLB_FROM_CECR10 */
+#define MLB_FROM_CECR11 (*(struct st_mlb_from_cecr0 *)&MLB.CECR11) /* MLB_FROM_CECR11 */
+#define MLB_FROM_CECR12 (*(struct st_mlb_from_cecr0 *)&MLB.CECR12) /* MLB_FROM_CECR12 */
+#define MLB_FROM_CECR13 (*(struct st_mlb_from_cecr0 *)&MLB.CECR13) /* MLB_FROM_CECR13 */
+#define MLB_FROM_CECR14 (*(struct st_mlb_from_cecr0 *)&MLB.CECR14) /* MLB_FROM_CECR14 */
+#define MLB_FROM_CECR15 (*(struct st_mlb_from_cecr0 *)&MLB.CECR15) /* MLB_FROM_CECR15 */
+#define MLB_FROM_CECR16 (*(struct st_mlb_from_cecr0 *)&MLB.CECR16) /* MLB_FROM_CECR16 */
+#define MLB_FROM_CECR17 (*(struct st_mlb_from_cecr0 *)&MLB.CECR17) /* MLB_FROM_CECR17 */
+#define MLB_FROM_CECR18 (*(struct st_mlb_from_cecr0 *)&MLB.CECR18) /* MLB_FROM_CECR18 */
+#define MLB_FROM_CECR19 (*(struct st_mlb_from_cecr0 *)&MLB.CECR19) /* MLB_FROM_CECR19 */
+#define MLB_FROM_CECR20 (*(struct st_mlb_from_cecr0 *)&MLB.CECR20) /* MLB_FROM_CECR20 */
+#define MLB_FROM_CECR21 (*(struct st_mlb_from_cecr0 *)&MLB.CECR21) /* MLB_FROM_CECR21 */
+#define MLB_FROM_CECR22 (*(struct st_mlb_from_cecr0 *)&MLB.CECR22) /* MLB_FROM_CECR22 */
+#define MLB_FROM_CECR23 (*(struct st_mlb_from_cecr0 *)&MLB.CECR23) /* MLB_FROM_CECR23 */
+#define MLB_FROM_CECR24 (*(struct st_mlb_from_cecr0 *)&MLB.CECR24) /* MLB_FROM_CECR24 */
+#define MLB_FROM_CECR25 (*(struct st_mlb_from_cecr0 *)&MLB.CECR25) /* MLB_FROM_CECR25 */
+#define MLB_FROM_CECR26 (*(struct st_mlb_from_cecr0 *)&MLB.CECR26) /* MLB_FROM_CECR26 */
+#define MLB_FROM_CECR27 (*(struct st_mlb_from_cecr0 *)&MLB.CECR27) /* MLB_FROM_CECR27 */
+#define MLB_FROM_CECR28 (*(struct st_mlb_from_cecr0 *)&MLB.CECR28) /* MLB_FROM_CECR28 */
+#define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */
+#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */
+
+/* End of channnel array defines of MLB */
+
+
+#define MLBDCCR MLB.DCCR
+#define MLBSSCR MLB.SSCR
+#define MLBSDCR MLB.SDCR
+#define MLBSMCR MLB.SMCR
+#define MLBVCCR MLB.VCCR
+#define MLBSBCR MLB.SBCR
+#define MLBABCR MLB.ABCR
+#define MLBCBCR MLB.CBCR
+#define MLBIBCR MLB.IBCR
+#define MLBCICR MLB.CICR
+#define MLBCECR0 MLB.CECR0
+#define MLBCSCR0 MLB.CSCR0
+#define MLBCCBCR0 MLB.CCBCR0
+#define MLBCNBCR0 MLB.CNBCR0
+#define MLBCECR1 MLB.CECR1
+#define MLBCSCR1 MLB.CSCR1
+#define MLBCCBCR1 MLB.CCBCR1
+#define MLBCNBCR1 MLB.CNBCR1
+#define MLBCECR2 MLB.CECR2
+#define MLBCSCR2 MLB.CSCR2
+#define MLBCCBCR2 MLB.CCBCR2
+#define MLBCNBCR2 MLB.CNBCR2
+#define MLBCECR3 MLB.CECR3
+#define MLBCSCR3 MLB.CSCR3
+#define MLBCCBCR3 MLB.CCBCR3
+#define MLBCNBCR3 MLB.CNBCR3
+#define MLBCECR4 MLB.CECR4
+#define MLBCSCR4 MLB.CSCR4
+#define MLBCCBCR4 MLB.CCBCR4
+#define MLBCNBCR4 MLB.CNBCR4
+#define MLBCECR5 MLB.CECR5
+#define MLBCSCR5 MLB.CSCR5
+#define MLBCCBCR5 MLB.CCBCR5
+#define MLBCNBCR5 MLB.CNBCR5
+#define MLBCECR6 MLB.CECR6
+#define MLBCSCR6 MLB.CSCR6
+#define MLBCCBCR6 MLB.CCBCR6
+#define MLBCNBCR6 MLB.CNBCR6
+#define MLBCECR7 MLB.CECR7
+#define MLBCSCR7 MLB.CSCR7
+#define MLBCCBCR7 MLB.CCBCR7
+#define MLBCNBCR7 MLB.CNBCR7
+#define MLBCECR8 MLB.CECR8
+#define MLBCSCR8 MLB.CSCR8
+#define MLBCCBCR8 MLB.CCBCR8
+#define MLBCNBCR8 MLB.CNBCR8
+#define MLBCECR9 MLB.CECR9
+#define MLBCSCR9 MLB.CSCR9
+#define MLBCCBCR9 MLB.CCBCR9
+#define MLBCNBCR9 MLB.CNBCR9
+#define MLBCECR10 MLB.CECR10
+#define MLBCSCR10 MLB.CSCR10
+#define MLBCCBCR10 MLB.CCBCR10
+#define MLBCNBCR10 MLB.CNBCR10
+#define MLBCECR11 MLB.CECR11
+#define MLBCSCR11 MLB.CSCR11
+#define MLBCCBCR11 MLB.CCBCR11
+#define MLBCNBCR11 MLB.CNBCR11
+#define MLBCECR12 MLB.CECR12
+#define MLBCSCR12 MLB.CSCR12
+#define MLBCCBCR12 MLB.CCBCR12
+#define MLBCNBCR12 MLB.CNBCR12
+#define MLBCECR13 MLB.CECR13
+#define MLBCSCR13 MLB.CSCR13
+#define MLBCCBCR13 MLB.CCBCR13
+#define MLBCNBCR13 MLB.CNBCR13
+#define MLBCECR14 MLB.CECR14
+#define MLBCSCR14 MLB.CSCR14
+#define MLBCCBCR14 MLB.CCBCR14
+#define MLBCNBCR14 MLB.CNBCR14
+#define MLBCECR15 MLB.CECR15
+#define MLBCSCR15 MLB.CSCR15
+#define MLBCCBCR15 MLB.CCBCR15
+#define MLBCNBCR15 MLB.CNBCR15
+#define MLBCECR16 MLB.CECR16
+#define MLBCSCR16 MLB.CSCR16
+#define MLBCCBCR16 MLB.CCBCR16
+#define MLBCNBCR16 MLB.CNBCR16
+#define MLBCECR17 MLB.CECR17
+#define MLBCSCR17 MLB.CSCR17
+#define MLBCCBCR17 MLB.CCBCR17
+#define MLBCNBCR17 MLB.CNBCR17
+#define MLBCECR18 MLB.CECR18
+#define MLBCSCR18 MLB.CSCR18
+#define MLBCCBCR18 MLB.CCBCR18
+#define MLBCNBCR18 MLB.CNBCR18
+#define MLBCECR19 MLB.CECR19
+#define MLBCSCR19 MLB.CSCR19
+#define MLBCCBCR19 MLB.CCBCR19
+#define MLBCNBCR19 MLB.CNBCR19
+#define MLBCECR20 MLB.CECR20
+#define MLBCSCR20 MLB.CSCR20
+#define MLBCCBCR20 MLB.CCBCR20
+#define MLBCNBCR20 MLB.CNBCR20
+#define MLBCECR21 MLB.CECR21
+#define MLBCSCR21 MLB.CSCR21
+#define MLBCCBCR21 MLB.CCBCR21
+#define MLBCNBCR21 MLB.CNBCR21
+#define MLBCECR22 MLB.CECR22
+#define MLBCSCR22 MLB.CSCR22
+#define MLBCCBCR22 MLB.CCBCR22
+#define MLBCNBCR22 MLB.CNBCR22
+#define MLBCECR23 MLB.CECR23
+#define MLBCSCR23 MLB.CSCR23
+#define MLBCCBCR23 MLB.CCBCR23
+#define MLBCNBCR23 MLB.CNBCR23
+#define MLBCECR24 MLB.CECR24
+#define MLBCSCR24 MLB.CSCR24
+#define MLBCCBCR24 MLB.CCBCR24
+#define MLBCNBCR24 MLB.CNBCR24
+#define MLBCECR25 MLB.CECR25
+#define MLBCSCR25 MLB.CSCR25
+#define MLBCCBCR25 MLB.CCBCR25
+#define MLBCNBCR25 MLB.CNBCR25
+#define MLBCECR26 MLB.CECR26
+#define MLBCSCR26 MLB.CSCR26
+#define MLBCCBCR26 MLB.CCBCR26
+#define MLBCNBCR26 MLB.CNBCR26
+#define MLBCECR27 MLB.CECR27
+#define MLBCSCR27 MLB.CSCR27
+#define MLBCCBCR27 MLB.CCBCR27
+#define MLBCNBCR27 MLB.CNBCR27
+#define MLBCECR28 MLB.CECR28
+#define MLBCSCR28 MLB.CSCR28
+#define MLBCCBCR28 MLB.CCBCR28
+#define MLBCNBCR28 MLB.CNBCR28
+#define MLBCECR29 MLB.CECR29
+#define MLBCSCR29 MLB.CSCR29
+#define MLBCCBCR29 MLB.CCBCR29
+#define MLBCNBCR29 MLB.CNBCR29
+#define MLBCECR30 MLB.CECR30
+#define MLBCSCR30 MLB.CSCR30
+#define MLBCCBCR30 MLB.CCBCR30
+#define MLBCNBCR30 MLB.CNBCR30
+#define MLBLCBCR0 MLB.LCBCR0
+#define MLBLCBCR1 MLB.LCBCR1
+#define MLBLCBCR2 MLB.LCBCR2
+#define MLBLCBCR3 MLB.LCBCR3
+#define MLBLCBCR4 MLB.LCBCR4
+#define MLBLCBCR5 MLB.LCBCR5
+#define MLBLCBCR6 MLB.LCBCR6
+#define MLBLCBCR7 MLB.LCBCR7
+#define MLBLCBCR8 MLB.LCBCR8
+#define MLBLCBCR9 MLB.LCBCR9
+#define MLBLCBCR10 MLB.LCBCR10
+#define MLBLCBCR11 MLB.LCBCR11
+#define MLBLCBCR12 MLB.LCBCR12
+#define MLBLCBCR13 MLB.LCBCR13
+#define MLBLCBCR14 MLB.LCBCR14
+#define MLBLCBCR15 MLB.LCBCR15
+#define MLBLCBCR16 MLB.LCBCR16
+#define MLBLCBCR17 MLB.LCBCR17
+#define MLBLCBCR18 MLB.LCBCR18
+#define MLBLCBCR19 MLB.LCBCR19
+#define MLBLCBCR20 MLB.LCBCR20
+#define MLBLCBCR21 MLB.LCBCR21
+#define MLBLCBCR22 MLB.LCBCR22
+#define MLBLCBCR23 MLB.LCBCR23
+#define MLBLCBCR24 MLB.LCBCR24
+#define MLBLCBCR25 MLB.LCBCR25
+#define MLBLCBCR26 MLB.LCBCR26
+#define MLBLCBCR27 MLB.LCBCR27
+#define MLBLCBCR28 MLB.LCBCR28
+#define MLBLCBCR29 MLB.LCBCR29
+#define MLBLCBCR30 MLB.LCBCR30
+/* <-SEC M1.10.1 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,93 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mmc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef MMC_IODEFINE_H
+#define MMC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_mmc
+{ /* MMC */
+ volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */
+ volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */
+ volatile uint8_t dummy182[4]; /* */
+ volatile uint32_t CE_ARG; /* CE_ARG */
+ volatile uint32_t CE_ARG_CMD12; /* CE_ARG_CMD12 */
+ volatile uint32_t CE_CMD_CTRL; /* CE_CMD_CTRL */
+ volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */
+ volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */
+ volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */
+#define MMC_CE_RESPn_COUNT 4
+ volatile uint32_t CE_RESP3; /* CE_RESP3 */
+ volatile uint32_t CE_RESP2; /* CE_RESP2 */
+ volatile uint32_t CE_RESP1; /* CE_RESP1 */
+ volatile uint32_t CE_RESP0; /* CE_RESP0 */
+ volatile uint32_t CE_RESP_CMD12; /* CE_RESP_CMD12 */
+ volatile uint32_t CE_DATA; /* CE_DATA */
+ volatile uint8_t dummy183[8]; /* */
+ volatile uint32_t CE_INT; /* CE_INT */
+ volatile uint32_t CE_INT_EN; /* CE_INT_EN */
+ volatile uint32_t CE_HOST_STS1; /* CE_HOST_STS1 */
+ volatile uint32_t CE_HOST_STS2; /* CE_HOST_STS2 */
+ volatile uint8_t dummy184[12]; /* */
+ volatile uint32_t CE_DMA_MODE; /* CE_DMA_MODE */
+ volatile uint8_t dummy185[16]; /* */
+ volatile uint32_t CE_DETECT; /* CE_DETECT */
+ volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */
+ volatile uint8_t dummy186[4]; /* */
+ volatile uint32_t CE_VERSION; /* CE_VERSION */
+};
+
+
+#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */
+
+
+#define MMCCE_CMD_SETH MMC.CE_CMD_SETH
+#define MMCCE_CMD_SETL MMC.CE_CMD_SETL
+#define MMCCE_ARG MMC.CE_ARG
+#define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12
+#define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL
+#define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET
+#define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL
+#define MMCCE_BUF_ACC MMC.CE_BUF_ACC
+#define MMCCE_RESP3 MMC.CE_RESP3
+#define MMCCE_RESP2 MMC.CE_RESP2
+#define MMCCE_RESP1 MMC.CE_RESP1
+#define MMCCE_RESP0 MMC.CE_RESP0
+#define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12
+#define MMCCE_DATA MMC.CE_DATA
+#define MMCCE_INT MMC.CE_INT
+#define MMCCE_INT_EN MMC.CE_INT_EN
+#define MMCCE_HOST_STS1 MMC.CE_HOST_STS1
+#define MMCCE_HOST_STS2 MMC.CE_HOST_STS2
+#define MMCCE_DMA_MODE MMC.CE_DMA_MODE
+#define MMCCE_DETECT MMC.CE_DETECT
+#define MMCCE_ADD_MODE MMC.CE_ADD_MODE
+#define MMCCE_VERSION MMC.CE_VERSION
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,218 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mtu2_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef MTU2_IODEFINE_H
+#define MTU2_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_mtu2
+{ /* MTU2 */
+ volatile uint8_t TCR_2; /* TCR_2 */
+ volatile uint8_t TMDR_2; /* TMDR_2 */
+ volatile uint8_t TIOR_2; /* TIOR_2 */
+ volatile uint8_t dummy520[1]; /* */
+ volatile uint8_t TIER_2; /* TIER_2 */
+ volatile uint8_t TSR_2; /* TSR_2 */
+ volatile uint16_t TCNT_2; /* TCNT_2 */
+ volatile uint16_t TGRA_2; /* TGRA_2 */
+ volatile uint16_t TGRB_2; /* TGRB_2 */
+ volatile uint8_t dummy521[500]; /* */
+ volatile uint8_t TCR_3; /* TCR_3 */
+ volatile uint8_t TCR_4; /* TCR_4 */
+ volatile uint8_t TMDR_3; /* TMDR_3 */
+ volatile uint8_t TMDR_4; /* TMDR_4 */
+ volatile uint8_t TIORH_3; /* TIORH_3 */
+ volatile uint8_t TIORL_3; /* TIORL_3 */
+ volatile uint8_t TIORH_4; /* TIORH_4 */
+ volatile uint8_t TIORL_4; /* TIORL_4 */
+ volatile uint8_t TIER_3; /* TIER_3 */
+ volatile uint8_t TIER_4; /* TIER_4 */
+ volatile uint8_t TOER; /* TOER */
+ volatile uint8_t dummy522[2]; /* */
+ volatile uint8_t TGCR; /* TGCR */
+ volatile uint8_t TOCR1; /* TOCR1 */
+ volatile uint8_t TOCR2; /* TOCR2 */
+ volatile uint16_t TCNT_3; /* TCNT_3 */
+ volatile uint16_t TCNT_4; /* TCNT_4 */
+ volatile uint16_t TCDR; /* TCDR */
+ volatile uint16_t TDDR; /* TDDR */
+ volatile uint16_t TGRA_3; /* TGRA_3 */
+ volatile uint16_t TGRB_3; /* TGRB_3 */
+ volatile uint16_t TGRA_4; /* TGRA_4 */
+ volatile uint16_t TGRB_4; /* TGRB_4 */
+ volatile uint16_t TCNTS; /* TCNTS */
+ volatile uint16_t TCBR; /* TCBR */
+ volatile uint16_t TGRC_3; /* TGRC_3 */
+ volatile uint16_t TGRD_3; /* TGRD_3 */
+ volatile uint16_t TGRC_4; /* TGRC_4 */
+ volatile uint16_t TGRD_4; /* TGRD_4 */
+ volatile uint8_t TSR_3; /* TSR_3 */
+ volatile uint8_t TSR_4; /* TSR_4 */
+ volatile uint8_t dummy523[2]; /* */
+ volatile uint8_t TITCR; /* TITCR */
+ volatile uint8_t TITCNT; /* TITCNT */
+ volatile uint8_t TBTER; /* TBTER */
+ volatile uint8_t dummy524[1]; /* */
+ volatile uint8_t TDER; /* TDER */
+ volatile uint8_t dummy525[1]; /* */
+ volatile uint8_t TOLBR; /* TOLBR */
+ volatile uint8_t dummy526[1]; /* */
+ volatile uint8_t TBTM_3; /* TBTM_3 */
+ volatile uint8_t TBTM_4; /* TBTM_4 */
+ volatile uint8_t dummy527[6]; /* */
+ volatile uint16_t TADCR; /* TADCR */
+ volatile uint8_t dummy528[2]; /* */
+ volatile uint16_t TADCORA_4; /* TADCORA_4 */
+ volatile uint16_t TADCORB_4; /* TADCORB_4 */
+ volatile uint16_t TADCOBRA_4; /* TADCOBRA_4 */
+ volatile uint16_t TADCOBRB_4; /* TADCOBRB_4 */
+ volatile uint8_t dummy529[20]; /* */
+ volatile uint8_t TWCR; /* TWCR */
+ volatile uint8_t dummy530[31]; /* */
+ volatile uint8_t TSTR; /* TSTR */
+ volatile uint8_t TSYR; /* TSYR */
+ volatile uint8_t dummy531[2]; /* */
+ volatile uint8_t TRWER; /* TRWER */
+ volatile uint8_t dummy532[123]; /* */
+ volatile uint8_t TCR_0; /* TCR_0 */
+ volatile uint8_t TMDR_0; /* TMDR_0 */
+ volatile uint8_t TIORH_0; /* TIORH_0 */
+ volatile uint8_t TIORL_0; /* TIORL_0 */
+ volatile uint8_t TIER_0; /* TIER_0 */
+ volatile uint8_t TSR_0; /* TSR_0 */
+ volatile uint16_t TCNT_0; /* TCNT_0 */
+ volatile uint16_t TGRA_0; /* TGRA_0 */
+ volatile uint16_t TGRB_0; /* TGRB_0 */
+ volatile uint16_t TGRC_0; /* TGRC_0 */
+ volatile uint16_t TGRD_0; /* TGRD_0 */
+ volatile uint8_t dummy533[16]; /* */
+ volatile uint16_t TGRE_0; /* TGRE_0 */
+ volatile uint16_t TGRF_0; /* TGRF_0 */
+ volatile uint8_t TIER2_0; /* TIER2_0 */
+ volatile uint8_t TSR2_0; /* TSR2_0 */
+ volatile uint8_t TBTM_0; /* TBTM_0 */
+ volatile uint8_t dummy534[89]; /* */
+ volatile uint8_t TCR_1; /* TCR_1 */
+ volatile uint8_t TMDR_1; /* TMDR_1 */
+ volatile uint8_t TIOR_1; /* TIOR_1 */
+ volatile uint8_t dummy535[1]; /* */
+ volatile uint8_t TIER_1; /* TIER_1 */
+ volatile uint8_t TSR_1; /* TSR_1 */
+ volatile uint16_t TCNT_1; /* TCNT_1 */
+ volatile uint16_t TGRA_1; /* TGRA_1 */
+ volatile uint16_t TGRB_1; /* TGRB_1 */
+ volatile uint8_t dummy536[4]; /* */
+ volatile uint8_t TICCR; /* TICCR */
+};
+
+
+#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */
+
+
+#define MTU2TCR_2 MTU2.TCR_2
+#define MTU2TMDR_2 MTU2.TMDR_2
+#define MTU2TIOR_2 MTU2.TIOR_2
+#define MTU2TIER_2 MTU2.TIER_2
+#define MTU2TSR_2 MTU2.TSR_2
+#define MTU2TCNT_2 MTU2.TCNT_2
+#define MTU2TGRA_2 MTU2.TGRA_2
+#define MTU2TGRB_2 MTU2.TGRB_2
+#define MTU2TCR_3 MTU2.TCR_3
+#define MTU2TCR_4 MTU2.TCR_4
+#define MTU2TMDR_3 MTU2.TMDR_3
+#define MTU2TMDR_4 MTU2.TMDR_4
+#define MTU2TIORH_3 MTU2.TIORH_3
+#define MTU2TIORL_3 MTU2.TIORL_3
+#define MTU2TIORH_4 MTU2.TIORH_4
+#define MTU2TIORL_4 MTU2.TIORL_4
+#define MTU2TIER_3 MTU2.TIER_3
+#define MTU2TIER_4 MTU2.TIER_4
+#define MTU2TOER MTU2.TOER
+#define MTU2TGCR MTU2.TGCR
+#define MTU2TOCR1 MTU2.TOCR1
+#define MTU2TOCR2 MTU2.TOCR2
+#define MTU2TCNT_3 MTU2.TCNT_3
+#define MTU2TCNT_4 MTU2.TCNT_4
+#define MTU2TCDR MTU2.TCDR
+#define MTU2TDDR MTU2.TDDR
+#define MTU2TGRA_3 MTU2.TGRA_3
+#define MTU2TGRB_3 MTU2.TGRB_3
+#define MTU2TGRA_4 MTU2.TGRA_4
+#define MTU2TGRB_4 MTU2.TGRB_4
+#define MTU2TCNTS MTU2.TCNTS
+#define MTU2TCBR MTU2.TCBR
+#define MTU2TGRC_3 MTU2.TGRC_3
+#define MTU2TGRD_3 MTU2.TGRD_3
+#define MTU2TGRC_4 MTU2.TGRC_4
+#define MTU2TGRD_4 MTU2.TGRD_4
+#define MTU2TSR_3 MTU2.TSR_3
+#define MTU2TSR_4 MTU2.TSR_4
+#define MTU2TITCR MTU2.TITCR
+#define MTU2TITCNT MTU2.TITCNT
+#define MTU2TBTER MTU2.TBTER
+#define MTU2TDER MTU2.TDER
+#define MTU2TOLBR MTU2.TOLBR
+#define MTU2TBTM_3 MTU2.TBTM_3
+#define MTU2TBTM_4 MTU2.TBTM_4
+#define MTU2TADCR MTU2.TADCR
+#define MTU2TADCORA_4 MTU2.TADCORA_4
+#define MTU2TADCORB_4 MTU2.TADCORB_4
+#define MTU2TADCOBRA_4 MTU2.TADCOBRA_4
+#define MTU2TADCOBRB_4 MTU2.TADCOBRB_4
+#define MTU2TWCR MTU2.TWCR
+#define MTU2TSTR MTU2.TSTR
+#define MTU2TSYR MTU2.TSYR
+#define MTU2TRWER MTU2.TRWER
+#define MTU2TCR_0 MTU2.TCR_0
+#define MTU2TMDR_0 MTU2.TMDR_0
+#define MTU2TIORH_0 MTU2.TIORH_0
+#define MTU2TIORL_0 MTU2.TIORL_0
+#define MTU2TIER_0 MTU2.TIER_0
+#define MTU2TSR_0 MTU2.TSR_0
+#define MTU2TCNT_0 MTU2.TCNT_0
+#define MTU2TGRA_0 MTU2.TGRA_0
+#define MTU2TGRB_0 MTU2.TGRB_0
+#define MTU2TGRC_0 MTU2.TGRC_0
+#define MTU2TGRD_0 MTU2.TGRD_0
+#define MTU2TGRE_0 MTU2.TGRE_0
+#define MTU2TGRF_0 MTU2.TGRF_0
+#define MTU2TIER2_0 MTU2.TIER2_0
+#define MTU2TSR2_0 MTU2.TSR2_0
+#define MTU2TBTM_0 MTU2.TBTM_0
+#define MTU2TCR_1 MTU2.TCR_1
+#define MTU2TMDR_1 MTU2.TMDR_1
+#define MTU2TIOR_1 MTU2.TIOR_1
+#define MTU2TIER_1 MTU2.TIER_1
+#define MTU2TSR_1 MTU2.TSR_1
+#define MTU2TCNT_1 MTU2.TCNT_1
+#define MTU2TGRA_1 MTU2.TGRA_1
+#define MTU2TGRB_1 MTU2.TGRB_1
+#define MTU2TICCR MTU2.TICCR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,79 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ostm_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef OSTM_IODEFINE_H
+#define OSTM_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ostm
+{ /* OSTM */
+ volatile uint32_t OSTMnCMP; /* OSTMnCMP */
+ volatile uint32_t OSTMnCNT; /* OSTMnCNT */
+ volatile uint8_t dummy1[8]; /* */
+ volatile uint8_t OSTMnTE; /* OSTMnTE */
+ volatile uint8_t dummy2[3]; /* */
+ volatile uint8_t OSTMnTS; /* OSTMnTS */
+ volatile uint8_t dummy3[3]; /* */
+ volatile uint8_t OSTMnTT; /* OSTMnTT */
+ volatile uint8_t dummy4[7]; /* */
+ volatile uint8_t OSTMnCTL; /* OSTMnCTL */
+};
+
+
+#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */
+#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */
+
+
+/* Start of channnel array defines of OSTM */
+
+/* Channnel array defines of OSTM */
+/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
+#define OSTM_COUNT 2
+#define OSTM_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &OSTM0, &OSTM1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of OSTM */
+
+
+#define OSTM0CMP OSTM0.OSTMnCMP
+#define OSTM0CNT OSTM0.OSTMnCNT
+#define OSTM0TE OSTM0.OSTMnTE
+#define OSTM0TS OSTM0.OSTMnTS
+#define OSTM0TT OSTM0.OSTMnTT
+#define OSTM0CTL OSTM0.OSTMnCTL
+#define OSTM1CMP OSTM1.OSTMnCMP
+#define OSTM1CNT OSTM1.OSTMnCNT
+#define OSTM1TE OSTM1.OSTMnTE
+#define OSTM1TS OSTM1.OSTMnTS
+#define OSTM1TT OSTM1.OSTMnTT
+#define OSTM1CTL OSTM1.OSTMnCTL
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,151 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : pfv_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef PFV_IODEFINE_H
+#define PFV_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_pfv
+{ /* PFV */
+ volatile uint32_t PFVCR; /* PFVCR */
+ volatile uint32_t PFVICR; /* PFVICR */
+ volatile uint32_t PFVISR; /* PFVISR */
+ volatile uint8_t dummy1[20]; /* */
+#define PFVID_COUNT 8
+ volatile uint32_t PFVID0; /* PFVID0 */
+ volatile uint32_t PFVID1; /* PFVID1 */
+ volatile uint32_t PFVID2; /* PFVID2 */
+ volatile uint32_t PFVID3; /* PFVID3 */
+ volatile uint32_t PFVID4; /* PFVID4 */
+ volatile uint32_t PFVID5; /* PFVID5 */
+ volatile uint32_t PFVID6; /* PFVID6 */
+ volatile uint32_t PFVID7; /* PFVID7 */
+#define PFVOD_COUNT 8
+ volatile uint32_t PFVOD0; /* PFVOD0 */
+ volatile uint32_t PFVOD1; /* PFVOD1 */
+ volatile uint32_t PFVOD2; /* PFVOD2 */
+ volatile uint32_t PFVOD3; /* PFVOD3 */
+ volatile uint32_t PFVOD4; /* PFVOD4 */
+ volatile uint32_t PFVOD5; /* PFVOD5 */
+ volatile uint32_t PFVOD6; /* PFVOD6 */
+ volatile uint32_t PFVOD7; /* PFVOD7 */
+ volatile uint8_t dummy2[4]; /* */
+ volatile uint32_t PFVIFSR; /* PFVIFSR */
+ volatile uint32_t PFVOFSR; /* PFVOFSR */
+ volatile uint32_t PFVACR; /* PFVACR */
+ volatile uint32_t PFV_MTX_MODE; /* PFV_MTX_MODE */
+ volatile uint32_t PFV_MTX_YG_ADJ0; /* PFV_MTX_YG_ADJ0 */
+ volatile uint32_t PFV_MTX_YG_ADJ1; /* PFV_MTX_YG_ADJ1 */
+ volatile uint32_t PFV_MTX_CBB_ADJ0; /* PFV_MTX_CBB_ADJ0 */
+ volatile uint32_t PFV_MTX_CBB_ADJ1; /* PFV_MTX_CBB_ADJ1 */
+ volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */
+ volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */
+ volatile uint32_t PFVSZR; /* PFVSZR */
+};
+
+
+#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */
+#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */
+
+
+/* Start of channnel array defines of PFV */
+
+/* Channnel array defines of PFV */
+/*(Sample) value = PFV[ channel ]->PFVCR; */
+#define PFV_COUNT 2
+#define PFV_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &PFV0, &PFV1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of PFV */
+
+
+#define PFV0PFVCR PFV0.PFVCR
+#define PFV0PFVICR PFV0.PFVICR
+#define PFV0PFVISR PFV0.PFVISR
+#define PFV0PFVID0 PFV0.PFVID0
+#define PFV0PFVID1 PFV0.PFVID1
+#define PFV0PFVID2 PFV0.PFVID2
+#define PFV0PFVID3 PFV0.PFVID3
+#define PFV0PFVID4 PFV0.PFVID4
+#define PFV0PFVID5 PFV0.PFVID5
+#define PFV0PFVID6 PFV0.PFVID6
+#define PFV0PFVID7 PFV0.PFVID7
+#define PFV0PFVOD0 PFV0.PFVOD0
+#define PFV0PFVOD1 PFV0.PFVOD1
+#define PFV0PFVOD2 PFV0.PFVOD2
+#define PFV0PFVOD3 PFV0.PFVOD3
+#define PFV0PFVOD4 PFV0.PFVOD4
+#define PFV0PFVOD5 PFV0.PFVOD5
+#define PFV0PFVOD6 PFV0.PFVOD6
+#define PFV0PFVOD7 PFV0.PFVOD7
+#define PFV0PFVIFSR PFV0.PFVIFSR
+#define PFV0PFVOFSR PFV0.PFVOFSR
+#define PFV0PFVACR PFV0.PFVACR
+#define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE
+#define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0
+#define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1
+#define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0
+#define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1
+#define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0
+#define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1
+#define PFV0PFVSZR PFV0.PFVSZR
+#define PFV1PFVCR PFV1.PFVCR
+#define PFV1PFVICR PFV1.PFVICR
+#define PFV1PFVISR PFV1.PFVISR
+#define PFV1PFVID0 PFV1.PFVID0
+#define PFV1PFVID1 PFV1.PFVID1
+#define PFV1PFVID2 PFV1.PFVID2
+#define PFV1PFVID3 PFV1.PFVID3
+#define PFV1PFVID4 PFV1.PFVID4
+#define PFV1PFVID5 PFV1.PFVID5
+#define PFV1PFVID6 PFV1.PFVID6
+#define PFV1PFVID7 PFV1.PFVID7
+#define PFV1PFVOD0 PFV1.PFVOD0
+#define PFV1PFVOD1 PFV1.PFVOD1
+#define PFV1PFVOD2 PFV1.PFVOD2
+#define PFV1PFVOD3 PFV1.PFVOD3
+#define PFV1PFVOD4 PFV1.PFVOD4
+#define PFV1PFVOD5 PFV1.PFVOD5
+#define PFV1PFVOD6 PFV1.PFVOD6
+#define PFV1PFVOD7 PFV1.PFVOD7
+#define PFV1PFVIFSR PFV1.PFVIFSR
+#define PFV1PFVOFSR PFV1.PFVOFSR
+#define PFV1PFVACR PFV1.PFVACR
+#define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE
+#define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0
+#define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1
+#define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0
+#define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1
+#define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0
+#define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1
+#define PFV1PFVSZR PFV1.PFVSZR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,136 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : pwm_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef PWM_IODEFINE_H
+#define PWM_IODEFINE_H
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+union reg16_8_t
+{
+ volatile uint16_t UINT16; /* 16-bit Access */
+ volatile uint8_t UINT8[2]; /* 8-bit Access */
+};
+
+struct st_pwm
+{ /* PWM */
+ volatile uint8_t dummy559[2]; /* */
+ union reg16_8_t PWBTCR; /* PWBTCR */
+
+ volatile uint8_t dummy560[216]; /* */
+
+/* start of struct st_pwm_common */
+ union reg16_8_t PWCR_1; /* PWCR_1 */
+
+ volatile uint8_t dummy561[2]; /* */
+ union reg16_8_t PWPR_1; /* PWPR_1 */
+
+ volatile uint16_t PWCYR_1; /* PWCYR_1 */
+ volatile uint16_t PWBFR_1A; /* PWBFR_1A */
+ volatile uint16_t PWBFR_1C; /* PWBFR_1C */
+ volatile uint16_t PWBFR_1E; /* PWBFR_1E */
+ volatile uint16_t PWBFR_1G; /* PWBFR_1G */
+/* end of struct st_pwm_common */
+
+/* start of struct st_pwm_common */
+ union reg16_8_t PWCR_2; /* PWCR_2 */
+
+ volatile uint8_t dummy562[2]; /* */
+ union reg16_8_t PWPR_2; /* PWPR_2 */
+
+ volatile uint16_t PWCYR_2; /* PWCYR_2 */
+ volatile uint16_t PWBFR_2A; /* PWBFR_2A */
+ volatile uint16_t PWBFR_2C; /* PWBFR_2C */
+ volatile uint16_t PWBFR_2E; /* PWBFR_2E */
+ volatile uint16_t PWBFR_2G; /* PWBFR_2G */
+/* end of struct st_pwm_common */
+};
+
+
+struct st_pwm_common
+{
+ union reg16_8_t PWCR_1; /* PWCR_1 */
+
+ volatile uint8_t dummy572[2]; /* */
+ union reg16_8_t PWPR_1; /* PWPR_1 */
+
+ volatile uint16_t PWCYR_1; /* PWCYR_1 */
+ volatile uint16_t PWBFR_1A; /* PWBFR_1A */
+ volatile uint16_t PWBFR_1C; /* PWBFR_1C */
+ volatile uint16_t PWBFR_1E; /* PWBFR_1E */
+ volatile uint16_t PWBFR_1G; /* PWBFR_1G */
+};
+
+
+#define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */
+
+
+/* Start of channnel array defines of PWM */
+
+/* Channnel array defines of PWMn */
+/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */
+#define PWMn_COUNT 2
+#define PWMn_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &PWM1, &PWM2 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */
+#define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */
+
+/* End of channnel array defines of PWM */
+
+
+#define PWMPWBTCR PWM.PWBTCR.UINT16
+#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0]
+#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1]
+#define PWMPWCR_1 PWM.PWCR_1.UINT16
+#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0]
+#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1]
+#define PWMPWPR_1 PWM.PWPR_1.UINT16
+#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0]
+#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1]
+#define PWMPWCYR_1 PWM.PWCYR_1
+#define PWMPWBFR_1A PWM.PWBFR_1A
+#define PWMPWBFR_1C PWM.PWBFR_1C
+#define PWMPWBFR_1E PWM.PWBFR_1E
+#define PWMPWBFR_1G PWM.PWBFR_1G
+#define PWMPWCR_2 PWM.PWCR_2.UINT16
+#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0]
+#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1]
+#define PWMPWPR_2 PWM.PWPR_2.UINT16
+#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0]
+#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1]
+#define PWMPWCYR_2 PWM.PWCYR_2
+#define PWMPWBFR_2A PWM.PWBFR_2A
+#define PWMPWBFR_2C PWM.PWBFR_2C
+#define PWMPWBFR_2E PWM.PWBFR_2E
+#define PWMPWBFR_2G PWM.PWBFR_2G
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,557 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : riic_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef RIIC_IODEFINE_H
+#define RIIC_IODEFINE_H
+
+#include "reg32_t.h"
+
+struct st_riic
+{ /* RIIC */
+#define RIICnCRm_COUNT 2
+ union reg32_t RIICnCR1; /* RIICnCR1 */
+ union reg32_t RIICnCR2; /* RIICnCR2 */
+#define RIICnMRm_COUNT 3
+ union reg32_t RIICnMR1; /* RIICnMR1 */
+ union reg32_t RIICnMR2; /* RIICnMR2 */
+ union reg32_t RIICnMR3; /* RIICnMR3 */
+ union reg32_t RIICnFER; /* RIICnFER */
+ union reg32_t RIICnSER; /* RIICnSER */
+ union reg32_t RIICnIER; /* RIICnIER */
+#define RIICnSRm_COUNT 2
+ union reg32_t RIICnSR1; /* RIICnSR1 */
+ union reg32_t RIICnSR2; /* RIICnSR2 */
+#define RIICnSARm_COUNT 3
+ union reg32_t RIICnSAR0; /* RIICnSAR0 */
+ union reg32_t RIICnSAR1; /* RIICnSAR1 */
+ union reg32_t RIICnSAR2; /* RIICnSAR2 */
+ union reg32_t RIICnBRL; /* RIICnBRL */
+ union reg32_t RIICnBRH; /* RIICnBRH */
+ union reg32_t RIICnDRT; /* RIICnDRT */
+ union reg32_t RIICnDRR; /* RIICnDRR */
+
+};
+
+
+#define RIIC0 (*(struct st_riic *)0xFCFEE000uL) /* RIIC0 */
+#define RIIC1 (*(struct st_riic *)0xFCFEE400uL) /* RIIC1 */
+#define RIIC2 (*(struct st_riic *)0xFCFEE800uL) /* RIIC2 */
+#define RIIC3 (*(struct st_riic *)0xFCFEEC00uL) /* RIIC3 */
+
+
+/* Start of channnel array defines of RIIC */
+
+/* Channnel array defines of RIIC */
+/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */
+#define RIIC_COUNT 4
+#define RIIC_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RIIC0, &RIIC1, &RIIC2, &RIIC3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of RIIC */
+
+
+#define RIIC0CR1 RIIC0.RIICnCR1.UINT32
+#define RIIC0CR1L RIIC0.RIICnCR1.UINT16[L]
+#define RIIC0CR1LL RIIC0.RIICnCR1.UINT8[LL]
+#define RIIC0CR1LH RIIC0.RIICnCR1.UINT8[LH]
+#define RIIC0CR1H RIIC0.RIICnCR1.UINT16[H]
+#define RIIC0CR1HL RIIC0.RIICnCR1.UINT8[HL]
+#define RIIC0CR1HH RIIC0.RIICnCR1.UINT8[HH]
+#define RIIC0CR2 RIIC0.RIICnCR2.UINT32
+#define RIIC0CR2L RIIC0.RIICnCR2.UINT16[L]
+#define RIIC0CR2LL RIIC0.RIICnCR2.UINT8[LL]
+#define RIIC0CR2LH RIIC0.RIICnCR2.UINT8[LH]
+#define RIIC0CR2H RIIC0.RIICnCR2.UINT16[H]
+#define RIIC0CR2HL RIIC0.RIICnCR2.UINT8[HL]
+#define RIIC0CR2HH RIIC0.RIICnCR2.UINT8[HH]
+#define RIIC0MR1 RIIC0.RIICnMR1.UINT32
+#define RIIC0MR1L RIIC0.RIICnMR1.UINT16[L]
+#define RIIC0MR1LL RIIC0.RIICnMR1.UINT8[LL]
+#define RIIC0MR1LH RIIC0.RIICnMR1.UINT8[LH]
+#define RIIC0MR1H RIIC0.RIICnMR1.UINT16[H]
+#define RIIC0MR1HL RIIC0.RIICnMR1.UINT8[HL]
+#define RIIC0MR1HH RIIC0.RIICnMR1.UINT8[HH]
+#define RIIC0MR2 RIIC0.RIICnMR2.UINT32
+#define RIIC0MR2L RIIC0.RIICnMR2.UINT16[L]
+#define RIIC0MR2LL RIIC0.RIICnMR2.UINT8[LL]
+#define RIIC0MR2LH RIIC0.RIICnMR2.UINT8[LH]
+#define RIIC0MR2H RIIC0.RIICnMR2.UINT16[H]
+#define RIIC0MR2HL RIIC0.RIICnMR2.UINT8[HL]
+#define RIIC0MR2HH RIIC0.RIICnMR2.UINT8[HH]
+#define RIIC0MR3 RIIC0.RIICnMR3.UINT32
+#define RIIC0MR3L RIIC0.RIICnMR3.UINT16[L]
+#define RIIC0MR3LL RIIC0.RIICnMR3.UINT8[LL]
+#define RIIC0MR3LH RIIC0.RIICnMR3.UINT8[LH]
+#define RIIC0MR3H RIIC0.RIICnMR3.UINT16[H]
+#define RIIC0MR3HL RIIC0.RIICnMR3.UINT8[HL]
+#define RIIC0MR3HH RIIC0.RIICnMR3.UINT8[HH]
+#define RIIC0FER RIIC0.RIICnFER.UINT32
+#define RIIC0FERL RIIC0.RIICnFER.UINT16[L]
+#define RIIC0FERLL RIIC0.RIICnFER.UINT8[LL]
+#define RIIC0FERLH RIIC0.RIICnFER.UINT8[LH]
+#define RIIC0FERH RIIC0.RIICnFER.UINT16[H]
+#define RIIC0FERHL RIIC0.RIICnFER.UINT8[HL]
+#define RIIC0FERHH RIIC0.RIICnFER.UINT8[HH]
+#define RIIC0SER RIIC0.RIICnSER.UINT32
+#define RIIC0SERL RIIC0.RIICnSER.UINT16[L]
+#define RIIC0SERLL RIIC0.RIICnSER.UINT8[LL]
+#define RIIC0SERLH RIIC0.RIICnSER.UINT8[LH]
+#define RIIC0SERH RIIC0.RIICnSER.UINT16[H]
+#define RIIC0SERHL RIIC0.RIICnSER.UINT8[HL]
+#define RIIC0SERHH RIIC0.RIICnSER.UINT8[HH]
+#define RIIC0IER RIIC0.RIICnIER.UINT32
+#define RIIC0IERL RIIC0.RIICnIER.UINT16[L]
+#define RIIC0IERLL RIIC0.RIICnIER.UINT8[LL]
+#define RIIC0IERLH RIIC0.RIICnIER.UINT8[LH]
+#define RIIC0IERH RIIC0.RIICnIER.UINT16[H]
+#define RIIC0IERHL RIIC0.RIICnIER.UINT8[HL]
+#define RIIC0IERHH RIIC0.RIICnIER.UINT8[HH]
+#define RIIC0SR1 RIIC0.RIICnSR1.UINT32
+#define RIIC0SR1L RIIC0.RIICnSR1.UINT16[L]
+#define RIIC0SR1LL RIIC0.RIICnSR1.UINT8[LL]
+#define RIIC0SR1LH RIIC0.RIICnSR1.UINT8[LH]
+#define RIIC0SR1H RIIC0.RIICnSR1.UINT16[H]
+#define RIIC0SR1HL RIIC0.RIICnSR1.UINT8[HL]
+#define RIIC0SR1HH RIIC0.RIICnSR1.UINT8[HH]
+#define RIIC0SR2 RIIC0.RIICnSR2.UINT32
+#define RIIC0SR2L RIIC0.RIICnSR2.UINT16[L]
+#define RIIC0SR2LL RIIC0.RIICnSR2.UINT8[LL]
+#define RIIC0SR2LH RIIC0.RIICnSR2.UINT8[LH]
+#define RIIC0SR2H RIIC0.RIICnSR2.UINT16[H]
+#define RIIC0SR2HL RIIC0.RIICnSR2.UINT8[HL]
+#define RIIC0SR2HH RIIC0.RIICnSR2.UINT8[HH]
+#define RIIC0SAR0 RIIC0.RIICnSAR0.UINT32
+#define RIIC0SAR0L RIIC0.RIICnSAR0.UINT16[L]
+#define RIIC0SAR0LL RIIC0.RIICnSAR0.UINT8[LL]
+#define RIIC0SAR0LH RIIC0.RIICnSAR0.UINT8[LH]
+#define RIIC0SAR0H RIIC0.RIICnSAR0.UINT16[H]
+#define RIIC0SAR0HL RIIC0.RIICnSAR0.UINT8[HL]
+#define RIIC0SAR0HH RIIC0.RIICnSAR0.UINT8[HH]
+#define RIIC0SAR1 RIIC0.RIICnSAR1.UINT32
+#define RIIC0SAR1L RIIC0.RIICnSAR1.UINT16[L]
+#define RIIC0SAR1LL RIIC0.RIICnSAR1.UINT8[LL]
+#define RIIC0SAR1LH RIIC0.RIICnSAR1.UINT8[LH]
+#define RIIC0SAR1H RIIC0.RIICnSAR1.UINT16[H]
+#define RIIC0SAR1HL RIIC0.RIICnSAR1.UINT8[HL]
+#define RIIC0SAR1HH RIIC0.RIICnSAR1.UINT8[HH]
+#define RIIC0SAR2 RIIC0.RIICnSAR2.UINT32
+#define RIIC0SAR2L RIIC0.RIICnSAR2.UINT16[L]
+#define RIIC0SAR2LL RIIC0.RIICnSAR2.UINT8[LL]
+#define RIIC0SAR2LH RIIC0.RIICnSAR2.UINT8[LH]
+#define RIIC0SAR2H RIIC0.RIICnSAR2.UINT16[H]
+#define RIIC0SAR2HL RIIC0.RIICnSAR2.UINT8[HL]
+#define RIIC0SAR2HH RIIC0.RIICnSAR2.UINT8[HH]
+#define RIIC0BRL RIIC0.RIICnBRL.UINT32
+#define RIIC0BRLL RIIC0.RIICnBRL.UINT16[L]
+#define RIIC0BRLLL RIIC0.RIICnBRL.UINT8[LL]
+#define RIIC0BRLLH RIIC0.RIICnBRL.UINT8[LH]
+#define RIIC0BRLH RIIC0.RIICnBRL.UINT16[H]
+#define RIIC0BRLHL RIIC0.RIICnBRL.UINT8[HL]
+#define RIIC0BRLHH RIIC0.RIICnBRL.UINT8[HH]
+#define RIIC0BRH RIIC0.RIICnBRH.UINT32
+#define RIIC0BRHL RIIC0.RIICnBRH.UINT16[L]
+#define RIIC0BRHLL RIIC0.RIICnBRH.UINT8[LL]
+#define RIIC0BRHLH RIIC0.RIICnBRH.UINT8[LH]
+#define RIIC0BRHH RIIC0.RIICnBRH.UINT16[H]
+#define RIIC0BRHHL RIIC0.RIICnBRH.UINT8[HL]
+#define RIIC0BRHHH RIIC0.RIICnBRH.UINT8[HH]
+#define RIIC0DRT RIIC0.RIICnDRT.UINT32
+#define RIIC0DRTL RIIC0.RIICnDRT.UINT16[L]
+#define RIIC0DRTLL RIIC0.RIICnDRT.UINT8[LL]
+#define RIIC0DRTLH RIIC0.RIICnDRT.UINT8[LH]
+#define RIIC0DRTH RIIC0.RIICnDRT.UINT16[H]
+#define RIIC0DRTHL RIIC0.RIICnDRT.UINT8[HL]
+#define RIIC0DRTHH RIIC0.RIICnDRT.UINT8[HH]
+#define RIIC0DRR RIIC0.RIICnDRR.UINT32
+#define RIIC0DRRL RIIC0.RIICnDRR.UINT16[L]
+#define RIIC0DRRLL RIIC0.RIICnDRR.UINT8[LL]
+#define RIIC0DRRLH RIIC0.RIICnDRR.UINT8[LH]
+#define RIIC0DRRH RIIC0.RIICnDRR.UINT16[H]
+#define RIIC0DRRHL RIIC0.RIICnDRR.UINT8[HL]
+#define RIIC0DRRHH RIIC0.RIICnDRR.UINT8[HH]
+#define RIIC1CR1 RIIC1.RIICnCR1.UINT32
+#define RIIC1CR1L RIIC1.RIICnCR1.UINT16[L]
+#define RIIC1CR1LL RIIC1.RIICnCR1.UINT8[LL]
+#define RIIC1CR1LH RIIC1.RIICnCR1.UINT8[LH]
+#define RIIC1CR1H RIIC1.RIICnCR1.UINT16[H]
+#define RIIC1CR1HL RIIC1.RIICnCR1.UINT8[HL]
+#define RIIC1CR1HH RIIC1.RIICnCR1.UINT8[HH]
+#define RIIC1CR2 RIIC1.RIICnCR2.UINT32
+#define RIIC1CR2L RIIC1.RIICnCR2.UINT16[L]
+#define RIIC1CR2LL RIIC1.RIICnCR2.UINT8[LL]
+#define RIIC1CR2LH RIIC1.RIICnCR2.UINT8[LH]
+#define RIIC1CR2H RIIC1.RIICnCR2.UINT16[H]
+#define RIIC1CR2HL RIIC1.RIICnCR2.UINT8[HL]
+#define RIIC1CR2HH RIIC1.RIICnCR2.UINT8[HH]
+#define RIIC1MR1 RIIC1.RIICnMR1.UINT32
+#define RIIC1MR1L RIIC1.RIICnMR1.UINT16[L]
+#define RIIC1MR1LL RIIC1.RIICnMR1.UINT8[LL]
+#define RIIC1MR1LH RIIC1.RIICnMR1.UINT8[LH]
+#define RIIC1MR1H RIIC1.RIICnMR1.UINT16[H]
+#define RIIC1MR1HL RIIC1.RIICnMR1.UINT8[HL]
+#define RIIC1MR1HH RIIC1.RIICnMR1.UINT8[HH]
+#define RIIC1MR2 RIIC1.RIICnMR2.UINT32
+#define RIIC1MR2L RIIC1.RIICnMR2.UINT16[L]
+#define RIIC1MR2LL RIIC1.RIICnMR2.UINT8[LL]
+#define RIIC1MR2LH RIIC1.RIICnMR2.UINT8[LH]
+#define RIIC1MR2H RIIC1.RIICnMR2.UINT16[H]
+#define RIIC1MR2HL RIIC1.RIICnMR2.UINT8[HL]
+#define RIIC1MR2HH RIIC1.RIICnMR2.UINT8[HH]
+#define RIIC1MR3 RIIC1.RIICnMR3.UINT32
+#define RIIC1MR3L RIIC1.RIICnMR3.UINT16[L]
+#define RIIC1MR3LL RIIC1.RIICnMR3.UINT8[LL]
+#define RIIC1MR3LH RIIC1.RIICnMR3.UINT8[LH]
+#define RIIC1MR3H RIIC1.RIICnMR3.UINT16[H]
+#define RIIC1MR3HL RIIC1.RIICnMR3.UINT8[HL]
+#define RIIC1MR3HH RIIC1.RIICnMR3.UINT8[HH]
+#define RIIC1FER RIIC1.RIICnFER.UINT32
+#define RIIC1FERL RIIC1.RIICnFER.UINT16[L]
+#define RIIC1FERLL RIIC1.RIICnFER.UINT8[LL]
+#define RIIC1FERLH RIIC1.RIICnFER.UINT8[LH]
+#define RIIC1FERH RIIC1.RIICnFER.UINT16[H]
+#define RIIC1FERHL RIIC1.RIICnFER.UINT8[HL]
+#define RIIC1FERHH RIIC1.RIICnFER.UINT8[HH]
+#define RIIC1SER RIIC1.RIICnSER.UINT32
+#define RIIC1SERL RIIC1.RIICnSER.UINT16[L]
+#define RIIC1SERLL RIIC1.RIICnSER.UINT8[LL]
+#define RIIC1SERLH RIIC1.RIICnSER.UINT8[LH]
+#define RIIC1SERH RIIC1.RIICnSER.UINT16[H]
+#define RIIC1SERHL RIIC1.RIICnSER.UINT8[HL]
+#define RIIC1SERHH RIIC1.RIICnSER.UINT8[HH]
+#define RIIC1IER RIIC1.RIICnIER.UINT32
+#define RIIC1IERL RIIC1.RIICnIER.UINT16[L]
+#define RIIC1IERLL RIIC1.RIICnIER.UINT8[LL]
+#define RIIC1IERLH RIIC1.RIICnIER.UINT8[LH]
+#define RIIC1IERH RIIC1.RIICnIER.UINT16[H]
+#define RIIC1IERHL RIIC1.RIICnIER.UINT8[HL]
+#define RIIC1IERHH RIIC1.RIICnIER.UINT8[HH]
+#define RIIC1SR1 RIIC1.RIICnSR1.UINT32
+#define RIIC1SR1L RIIC1.RIICnSR1.UINT16[L]
+#define RIIC1SR1LL RIIC1.RIICnSR1.UINT8[LL]
+#define RIIC1SR1LH RIIC1.RIICnSR1.UINT8[LH]
+#define RIIC1SR1H RIIC1.RIICnSR1.UINT16[H]
+#define RIIC1SR1HL RIIC1.RIICnSR1.UINT8[HL]
+#define RIIC1SR1HH RIIC1.RIICnSR1.UINT8[HH]
+#define RIIC1SR2 RIIC1.RIICnSR2.UINT32
+#define RIIC1SR2L RIIC1.RIICnSR2.UINT16[L]
+#define RIIC1SR2LL RIIC1.RIICnSR2.UINT8[LL]
+#define RIIC1SR2LH RIIC1.RIICnSR2.UINT8[LH]
+#define RIIC1SR2H RIIC1.RIICnSR2.UINT16[H]
+#define RIIC1SR2HL RIIC1.RIICnSR2.UINT8[HL]
+#define RIIC1SR2HH RIIC1.RIICnSR2.UINT8[HH]
+#define RIIC1SAR0 RIIC1.RIICnSAR0.UINT32
+#define RIIC1SAR0L RIIC1.RIICnSAR0.UINT16[L]
+#define RIIC1SAR0LL RIIC1.RIICnSAR0.UINT8[LL]
+#define RIIC1SAR0LH RIIC1.RIICnSAR0.UINT8[LH]
+#define RIIC1SAR0H RIIC1.RIICnSAR0.UINT16[H]
+#define RIIC1SAR0HL RIIC1.RIICnSAR0.UINT8[HL]
+#define RIIC1SAR0HH RIIC1.RIICnSAR0.UINT8[HH]
+#define RIIC1SAR1 RIIC1.RIICnSAR1.UINT32
+#define RIIC1SAR1L RIIC1.RIICnSAR1.UINT16[L]
+#define RIIC1SAR1LL RIIC1.RIICnSAR1.UINT8[LL]
+#define RIIC1SAR1LH RIIC1.RIICnSAR1.UINT8[LH]
+#define RIIC1SAR1H RIIC1.RIICnSAR1.UINT16[H]
+#define RIIC1SAR1HL RIIC1.RIICnSAR1.UINT8[HL]
+#define RIIC1SAR1HH RIIC1.RIICnSAR1.UINT8[HH]
+#define RIIC1SAR2 RIIC1.RIICnSAR2.UINT32
+#define RIIC1SAR2L RIIC1.RIICnSAR2.UINT16[L]
+#define RIIC1SAR2LL RIIC1.RIICnSAR2.UINT8[LL]
+#define RIIC1SAR2LH RIIC1.RIICnSAR2.UINT8[LH]
+#define RIIC1SAR2H RIIC1.RIICnSAR2.UINT16[H]
+#define RIIC1SAR2HL RIIC1.RIICnSAR2.UINT8[HL]
+#define RIIC1SAR2HH RIIC1.RIICnSAR2.UINT8[HH]
+#define RIIC1BRL RIIC1.RIICnBRL.UINT32
+#define RIIC1BRLL RIIC1.RIICnBRL.UINT16[L]
+#define RIIC1BRLLL RIIC1.RIICnBRL.UINT8[LL]
+#define RIIC1BRLLH RIIC1.RIICnBRL.UINT8[LH]
+#define RIIC1BRLH RIIC1.RIICnBRL.UINT16[H]
+#define RIIC1BRLHL RIIC1.RIICnBRL.UINT8[HL]
+#define RIIC1BRLHH RIIC1.RIICnBRL.UINT8[HH]
+#define RIIC1BRH RIIC1.RIICnBRH.UINT32
+#define RIIC1BRHL RIIC1.RIICnBRH.UINT16[L]
+#define RIIC1BRHLL RIIC1.RIICnBRH.UINT8[LL]
+#define RIIC1BRHLH RIIC1.RIICnBRH.UINT8[LH]
+#define RIIC1BRHH RIIC1.RIICnBRH.UINT16[H]
+#define RIIC1BRHHL RIIC1.RIICnBRH.UINT8[HL]
+#define RIIC1BRHHH RIIC1.RIICnBRH.UINT8[HH]
+#define RIIC1DRT RIIC1.RIICnDRT.UINT32
+#define RIIC1DRTL RIIC1.RIICnDRT.UINT16[L]
+#define RIIC1DRTLL RIIC1.RIICnDRT.UINT8[LL]
+#define RIIC1DRTLH RIIC1.RIICnDRT.UINT8[LH]
+#define RIIC1DRTH RIIC1.RIICnDRT.UINT16[H]
+#define RIIC1DRTHL RIIC1.RIICnDRT.UINT8[HL]
+#define RIIC1DRTHH RIIC1.RIICnDRT.UINT8[HH]
+#define RIIC1DRR RIIC1.RIICnDRR.UINT32
+#define RIIC1DRRL RIIC1.RIICnDRR.UINT16[L]
+#define RIIC1DRRLL RIIC1.RIICnDRR.UINT8[LL]
+#define RIIC1DRRLH RIIC1.RIICnDRR.UINT8[LH]
+#define RIIC1DRRH RIIC1.RIICnDRR.UINT16[H]
+#define RIIC1DRRHL RIIC1.RIICnDRR.UINT8[HL]
+#define RIIC1DRRHH RIIC1.RIICnDRR.UINT8[HH]
+#define RIIC2CR1 RIIC2.RIICnCR1.UINT32
+#define RIIC2CR1L RIIC2.RIICnCR1.UINT16[L]
+#define RIIC2CR1LL RIIC2.RIICnCR1.UINT8[LL]
+#define RIIC2CR1LH RIIC2.RIICnCR1.UINT8[LH]
+#define RIIC2CR1H RIIC2.RIICnCR1.UINT16[H]
+#define RIIC2CR1HL RIIC2.RIICnCR1.UINT8[HL]
+#define RIIC2CR1HH RIIC2.RIICnCR1.UINT8[HH]
+#define RIIC2CR2 RIIC2.RIICnCR2.UINT32
+#define RIIC2CR2L RIIC2.RIICnCR2.UINT16[L]
+#define RIIC2CR2LL RIIC2.RIICnCR2.UINT8[LL]
+#define RIIC2CR2LH RIIC2.RIICnCR2.UINT8[LH]
+#define RIIC2CR2H RIIC2.RIICnCR2.UINT16[H]
+#define RIIC2CR2HL RIIC2.RIICnCR2.UINT8[HL]
+#define RIIC2CR2HH RIIC2.RIICnCR2.UINT8[HH]
+#define RIIC2MR1 RIIC2.RIICnMR1.UINT32
+#define RIIC2MR1L RIIC2.RIICnMR1.UINT16[L]
+#define RIIC2MR1LL RIIC2.RIICnMR1.UINT8[LL]
+#define RIIC2MR1LH RIIC2.RIICnMR1.UINT8[LH]
+#define RIIC2MR1H RIIC2.RIICnMR1.UINT16[H]
+#define RIIC2MR1HL RIIC2.RIICnMR1.UINT8[HL]
+#define RIIC2MR1HH RIIC2.RIICnMR1.UINT8[HH]
+#define RIIC2MR2 RIIC2.RIICnMR2.UINT32
+#define RIIC2MR2L RIIC2.RIICnMR2.UINT16[L]
+#define RIIC2MR2LL RIIC2.RIICnMR2.UINT8[LL]
+#define RIIC2MR2LH RIIC2.RIICnMR2.UINT8[LH]
+#define RIIC2MR2H RIIC2.RIICnMR2.UINT16[H]
+#define RIIC2MR2HL RIIC2.RIICnMR2.UINT8[HL]
+#define RIIC2MR2HH RIIC2.RIICnMR2.UINT8[HH]
+#define RIIC2MR3 RIIC2.RIICnMR3.UINT32
+#define RIIC2MR3L RIIC2.RIICnMR3.UINT16[L]
+#define RIIC2MR3LL RIIC2.RIICnMR3.UINT8[LL]
+#define RIIC2MR3LH RIIC2.RIICnMR3.UINT8[LH]
+#define RIIC2MR3H RIIC2.RIICnMR3.UINT16[H]
+#define RIIC2MR3HL RIIC2.RIICnMR3.UINT8[HL]
+#define RIIC2MR3HH RIIC2.RIICnMR3.UINT8[HH]
+#define RIIC2FER RIIC2.RIICnFER.UINT32
+#define RIIC2FERL RIIC2.RIICnFER.UINT16[L]
+#define RIIC2FERLL RIIC2.RIICnFER.UINT8[LL]
+#define RIIC2FERLH RIIC2.RIICnFER.UINT8[LH]
+#define RIIC2FERH RIIC2.RIICnFER.UINT16[H]
+#define RIIC2FERHL RIIC2.RIICnFER.UINT8[HL]
+#define RIIC2FERHH RIIC2.RIICnFER.UINT8[HH]
+#define RIIC2SER RIIC2.RIICnSER.UINT32
+#define RIIC2SERL RIIC2.RIICnSER.UINT16[L]
+#define RIIC2SERLL RIIC2.RIICnSER.UINT8[LL]
+#define RIIC2SERLH RIIC2.RIICnSER.UINT8[LH]
+#define RIIC2SERH RIIC2.RIICnSER.UINT16[H]
+#define RIIC2SERHL RIIC2.RIICnSER.UINT8[HL]
+#define RIIC2SERHH RIIC2.RIICnSER.UINT8[HH]
+#define RIIC2IER RIIC2.RIICnIER.UINT32
+#define RIIC2IERL RIIC2.RIICnIER.UINT16[L]
+#define RIIC2IERLL RIIC2.RIICnIER.UINT8[LL]
+#define RIIC2IERLH RIIC2.RIICnIER.UINT8[LH]
+#define RIIC2IERH RIIC2.RIICnIER.UINT16[H]
+#define RIIC2IERHL RIIC2.RIICnIER.UINT8[HL]
+#define RIIC2IERHH RIIC2.RIICnIER.UINT8[HH]
+#define RIIC2SR1 RIIC2.RIICnSR1.UINT32
+#define RIIC2SR1L RIIC2.RIICnSR1.UINT16[L]
+#define RIIC2SR1LL RIIC2.RIICnSR1.UINT8[LL]
+#define RIIC2SR1LH RIIC2.RIICnSR1.UINT8[LH]
+#define RIIC2SR1H RIIC2.RIICnSR1.UINT16[H]
+#define RIIC2SR1HL RIIC2.RIICnSR1.UINT8[HL]
+#define RIIC2SR1HH RIIC2.RIICnSR1.UINT8[HH]
+#define RIIC2SR2 RIIC2.RIICnSR2.UINT32
+#define RIIC2SR2L RIIC2.RIICnSR2.UINT16[L]
+#define RIIC2SR2LL RIIC2.RIICnSR2.UINT8[LL]
+#define RIIC2SR2LH RIIC2.RIICnSR2.UINT8[LH]
+#define RIIC2SR2H RIIC2.RIICnSR2.UINT16[H]
+#define RIIC2SR2HL RIIC2.RIICnSR2.UINT8[HL]
+#define RIIC2SR2HH RIIC2.RIICnSR2.UINT8[HH]
+#define RIIC2SAR0 RIIC2.RIICnSAR0.UINT32
+#define RIIC2SAR0L RIIC2.RIICnSAR0.UINT16[L]
+#define RIIC2SAR0LL RIIC2.RIICnSAR0.UINT8[LL]
+#define RIIC2SAR0LH RIIC2.RIICnSAR0.UINT8[LH]
+#define RIIC2SAR0H RIIC2.RIICnSAR0.UINT16[H]
+#define RIIC2SAR0HL RIIC2.RIICnSAR0.UINT8[HL]
+#define RIIC2SAR0HH RIIC2.RIICnSAR0.UINT8[HH]
+#define RIIC2SAR1 RIIC2.RIICnSAR1.UINT32
+#define RIIC2SAR1L RIIC2.RIICnSAR1.UINT16[L]
+#define RIIC2SAR1LL RIIC2.RIICnSAR1.UINT8[LL]
+#define RIIC2SAR1LH RIIC2.RIICnSAR1.UINT8[LH]
+#define RIIC2SAR1H RIIC2.RIICnSAR1.UINT16[H]
+#define RIIC2SAR1HL RIIC2.RIICnSAR1.UINT8[HL]
+#define RIIC2SAR1HH RIIC2.RIICnSAR1.UINT8[HH]
+#define RIIC2SAR2 RIIC2.RIICnSAR2.UINT32
+#define RIIC2SAR2L RIIC2.RIICnSAR2.UINT16[L]
+#define RIIC2SAR2LL RIIC2.RIICnSAR2.UINT8[LL]
+#define RIIC2SAR2LH RIIC2.RIICnSAR2.UINT8[LH]
+#define RIIC2SAR2H RIIC2.RIICnSAR2.UINT16[H]
+#define RIIC2SAR2HL RIIC2.RIICnSAR2.UINT8[HL]
+#define RIIC2SAR2HH RIIC2.RIICnSAR2.UINT8[HH]
+#define RIIC2BRL RIIC2.RIICnBRL.UINT32
+#define RIIC2BRLL RIIC2.RIICnBRL.UINT16[L]
+#define RIIC2BRLLL RIIC2.RIICnBRL.UINT8[LL]
+#define RIIC2BRLLH RIIC2.RIICnBRL.UINT8[LH]
+#define RIIC2BRLH RIIC2.RIICnBRL.UINT16[H]
+#define RIIC2BRLHL RIIC2.RIICnBRL.UINT8[HL]
+#define RIIC2BRLHH RIIC2.RIICnBRL.UINT8[HH]
+#define RIIC2BRH RIIC2.RIICnBRH.UINT32
+#define RIIC2BRHL RIIC2.RIICnBRH.UINT16[L]
+#define RIIC2BRHLL RIIC2.RIICnBRH.UINT8[LL]
+#define RIIC2BRHLH RIIC2.RIICnBRH.UINT8[LH]
+#define RIIC2BRHH RIIC2.RIICnBRH.UINT16[H]
+#define RIIC2BRHHL RIIC2.RIICnBRH.UINT8[HL]
+#define RIIC2BRHHH RIIC2.RIICnBRH.UINT8[HH]
+#define RIIC2DRT RIIC2.RIICnDRT.UINT32
+#define RIIC2DRTL RIIC2.RIICnDRT.UINT16[L]
+#define RIIC2DRTLL RIIC2.RIICnDRT.UINT8[LL]
+#define RIIC2DRTLH RIIC2.RIICnDRT.UINT8[LH]
+#define RIIC2DRTH RIIC2.RIICnDRT.UINT16[H]
+#define RIIC2DRTHL RIIC2.RIICnDRT.UINT8[HL]
+#define RIIC2DRTHH RIIC2.RIICnDRT.UINT8[HH]
+#define RIIC2DRR RIIC2.RIICnDRR.UINT32
+#define RIIC2DRRL RIIC2.RIICnDRR.UINT16[L]
+#define RIIC2DRRLL RIIC2.RIICnDRR.UINT8[LL]
+#define RIIC2DRRLH RIIC2.RIICnDRR.UINT8[LH]
+#define RIIC2DRRH RIIC2.RIICnDRR.UINT16[H]
+#define RIIC2DRRHL RIIC2.RIICnDRR.UINT8[HL]
+#define RIIC2DRRHH RIIC2.RIICnDRR.UINT8[HH]
+#define RIIC3CR1 RIIC3.RIICnCR1.UINT32
+#define RIIC3CR1L RIIC3.RIICnCR1.UINT16[L]
+#define RIIC3CR1LL RIIC3.RIICnCR1.UINT8[LL]
+#define RIIC3CR1LH RIIC3.RIICnCR1.UINT8[LH]
+#define RIIC3CR1H RIIC3.RIICnCR1.UINT16[H]
+#define RIIC3CR1HL RIIC3.RIICnCR1.UINT8[HL]
+#define RIIC3CR1HH RIIC3.RIICnCR1.UINT8[HH]
+#define RIIC3CR2 RIIC3.RIICnCR2.UINT32
+#define RIIC3CR2L RIIC3.RIICnCR2.UINT16[L]
+#define RIIC3CR2LL RIIC3.RIICnCR2.UINT8[LL]
+#define RIIC3CR2LH RIIC3.RIICnCR2.UINT8[LH]
+#define RIIC3CR2H RIIC3.RIICnCR2.UINT16[H]
+#define RIIC3CR2HL RIIC3.RIICnCR2.UINT8[HL]
+#define RIIC3CR2HH RIIC3.RIICnCR2.UINT8[HH]
+#define RIIC3MR1 RIIC3.RIICnMR1.UINT32
+#define RIIC3MR1L RIIC3.RIICnMR1.UINT16[L]
+#define RIIC3MR1LL RIIC3.RIICnMR1.UINT8[LL]
+#define RIIC3MR1LH RIIC3.RIICnMR1.UINT8[LH]
+#define RIIC3MR1H RIIC3.RIICnMR1.UINT16[H]
+#define RIIC3MR1HL RIIC3.RIICnMR1.UINT8[HL]
+#define RIIC3MR1HH RIIC3.RIICnMR1.UINT8[HH]
+#define RIIC3MR2 RIIC3.RIICnMR2.UINT32
+#define RIIC3MR2L RIIC3.RIICnMR2.UINT16[L]
+#define RIIC3MR2LL RIIC3.RIICnMR2.UINT8[LL]
+#define RIIC3MR2LH RIIC3.RIICnMR2.UINT8[LH]
+#define RIIC3MR2H RIIC3.RIICnMR2.UINT16[H]
+#define RIIC3MR2HL RIIC3.RIICnMR2.UINT8[HL]
+#define RIIC3MR2HH RIIC3.RIICnMR2.UINT8[HH]
+#define RIIC3MR3 RIIC3.RIICnMR3.UINT32
+#define RIIC3MR3L RIIC3.RIICnMR3.UINT16[L]
+#define RIIC3MR3LL RIIC3.RIICnMR3.UINT8[LL]
+#define RIIC3MR3LH RIIC3.RIICnMR3.UINT8[LH]
+#define RIIC3MR3H RIIC3.RIICnMR3.UINT16[H]
+#define RIIC3MR3HL RIIC3.RIICnMR3.UINT8[HL]
+#define RIIC3MR3HH RIIC3.RIICnMR3.UINT8[HH]
+#define RIIC3FER RIIC3.RIICnFER.UINT32
+#define RIIC3FERL RIIC3.RIICnFER.UINT16[L]
+#define RIIC3FERLL RIIC3.RIICnFER.UINT8[LL]
+#define RIIC3FERLH RIIC3.RIICnFER.UINT8[LH]
+#define RIIC3FERH RIIC3.RIICnFER.UINT16[H]
+#define RIIC3FERHL RIIC3.RIICnFER.UINT8[HL]
+#define RIIC3FERHH RIIC3.RIICnFER.UINT8[HH]
+#define RIIC3SER RIIC3.RIICnSER.UINT32
+#define RIIC3SERL RIIC3.RIICnSER.UINT16[L]
+#define RIIC3SERLL RIIC3.RIICnSER.UINT8[LL]
+#define RIIC3SERLH RIIC3.RIICnSER.UINT8[LH]
+#define RIIC3SERH RIIC3.RIICnSER.UINT16[H]
+#define RIIC3SERHL RIIC3.RIICnSER.UINT8[HL]
+#define RIIC3SERHH RIIC3.RIICnSER.UINT8[HH]
+#define RIIC3IER RIIC3.RIICnIER.UINT32
+#define RIIC3IERL RIIC3.RIICnIER.UINT16[L]
+#define RIIC3IERLL RIIC3.RIICnIER.UINT8[LL]
+#define RIIC3IERLH RIIC3.RIICnIER.UINT8[LH]
+#define RIIC3IERH RIIC3.RIICnIER.UINT16[H]
+#define RIIC3IERHL RIIC3.RIICnIER.UINT8[HL]
+#define RIIC3IERHH RIIC3.RIICnIER.UINT8[HH]
+#define RIIC3SR1 RIIC3.RIICnSR1.UINT32
+#define RIIC3SR1L RIIC3.RIICnSR1.UINT16[L]
+#define RIIC3SR1LL RIIC3.RIICnSR1.UINT8[LL]
+#define RIIC3SR1LH RIIC3.RIICnSR1.UINT8[LH]
+#define RIIC3SR1H RIIC3.RIICnSR1.UINT16[H]
+#define RIIC3SR1HL RIIC3.RIICnSR1.UINT8[HL]
+#define RIIC3SR1HH RIIC3.RIICnSR1.UINT8[HH]
+#define RIIC3SR2 RIIC3.RIICnSR2.UINT32
+#define RIIC3SR2L RIIC3.RIICnSR2.UINT16[L]
+#define RIIC3SR2LL RIIC3.RIICnSR2.UINT8[LL]
+#define RIIC3SR2LH RIIC3.RIICnSR2.UINT8[LH]
+#define RIIC3SR2H RIIC3.RIICnSR2.UINT16[H]
+#define RIIC3SR2HL RIIC3.RIICnSR2.UINT8[HL]
+#define RIIC3SR2HH RIIC3.RIICnSR2.UINT8[HH]
+#define RIIC3SAR0 RIIC3.RIICnSAR0.UINT32
+#define RIIC3SAR0L RIIC3.RIICnSAR0.UINT16[L]
+#define RIIC3SAR0LL RIIC3.RIICnSAR0.UINT8[LL]
+#define RIIC3SAR0LH RIIC3.RIICnSAR0.UINT8[LH]
+#define RIIC3SAR0H RIIC3.RIICnSAR0.UINT16[H]
+#define RIIC3SAR0HL RIIC3.RIICnSAR0.UINT8[HL]
+#define RIIC3SAR0HH RIIC3.RIICnSAR0.UINT8[HH]
+#define RIIC3SAR1 RIIC3.RIICnSAR1.UINT32
+#define RIIC3SAR1L RIIC3.RIICnSAR1.UINT16[L]
+#define RIIC3SAR1LL RIIC3.RIICnSAR1.UINT8[LL]
+#define RIIC3SAR1LH RIIC3.RIICnSAR1.UINT8[LH]
+#define RIIC3SAR1H RIIC3.RIICnSAR1.UINT16[H]
+#define RIIC3SAR1HL RIIC3.RIICnSAR1.UINT8[HL]
+#define RIIC3SAR1HH RIIC3.RIICnSAR1.UINT8[HH]
+#define RIIC3SAR2 RIIC3.RIICnSAR2.UINT32
+#define RIIC3SAR2L RIIC3.RIICnSAR2.UINT16[L]
+#define RIIC3SAR2LL RIIC3.RIICnSAR2.UINT8[LL]
+#define RIIC3SAR2LH RIIC3.RIICnSAR2.UINT8[LH]
+#define RIIC3SAR2H RIIC3.RIICnSAR2.UINT16[H]
+#define RIIC3SAR2HL RIIC3.RIICnSAR2.UINT8[HL]
+#define RIIC3SAR2HH RIIC3.RIICnSAR2.UINT8[HH]
+#define RIIC3BRL RIIC3.RIICnBRL.UINT32
+#define RIIC3BRLL RIIC3.RIICnBRL.UINT16[L]
+#define RIIC3BRLLL RIIC3.RIICnBRL.UINT8[LL]
+#define RIIC3BRLLH RIIC3.RIICnBRL.UINT8[LH]
+#define RIIC3BRLH RIIC3.RIICnBRL.UINT16[H]
+#define RIIC3BRLHL RIIC3.RIICnBRL.UINT8[HL]
+#define RIIC3BRLHH RIIC3.RIICnBRL.UINT8[HH]
+#define RIIC3BRH RIIC3.RIICnBRH.UINT32
+#define RIIC3BRHL RIIC3.RIICnBRH.UINT16[L]
+#define RIIC3BRHLL RIIC3.RIICnBRH.UINT8[LL]
+#define RIIC3BRHLH RIIC3.RIICnBRH.UINT8[LH]
+#define RIIC3BRHH RIIC3.RIICnBRH.UINT16[H]
+#define RIIC3BRHHL RIIC3.RIICnBRH.UINT8[HL]
+#define RIIC3BRHHH RIIC3.RIICnBRH.UINT8[HH]
+#define RIIC3DRT RIIC3.RIICnDRT.UINT32
+#define RIIC3DRTL RIIC3.RIICnDRT.UINT16[L]
+#define RIIC3DRTLL RIIC3.RIICnDRT.UINT8[LL]
+#define RIIC3DRTLH RIIC3.RIICnDRT.UINT8[LH]
+#define RIIC3DRTH RIIC3.RIICnDRT.UINT16[H]
+#define RIIC3DRTHL RIIC3.RIICnDRT.UINT8[HL]
+#define RIIC3DRTHH RIIC3.RIICnDRT.UINT8[HH]
+#define RIIC3DRR RIIC3.RIICnDRR.UINT32
+#define RIIC3DRRL RIIC3.RIICnDRR.UINT16[L]
+#define RIIC3DRRLL RIIC3.RIICnDRR.UINT8[LL]
+#define RIIC3DRRLH RIIC3.RIICnDRR.UINT8[LH]
+#define RIIC3DRRH RIIC3.RIICnDRR.UINT16[H]
+#define RIIC3DRRHL RIIC3.RIICnDRR.UINT8[HL]
+#define RIIC3DRRHH RIIC3.RIICnDRR.UINT8[HH]
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,167 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : romdec_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef ROMDEC_IODEFINE_H
+#define ROMDEC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_romdec
+{ /* ROMDEC */
+ volatile uint8_t CROMEN; /* CROMEN */
+ volatile uint8_t CROMSY0; /* CROMSY0 */
+#define ROMDEC_CROMCTL0_COUNT 2
+ volatile uint8_t CROMCTL0; /* CROMCTL0 */
+ volatile uint8_t CROMCTL1; /* CROMCTL1 */
+ volatile uint8_t dummy23[1]; /* */
+ volatile uint8_t CROMCTL3; /* CROMCTL3 */
+ volatile uint8_t CROMCTL4; /* CROMCTL4 */
+ volatile uint8_t CROMCTL5; /* CROMCTL5 */
+#define ROMDEC_CROMST0_COUNT 2
+ volatile uint8_t CROMST0; /* CROMST0 */
+ volatile uint8_t CROMST1; /* CROMST1 */
+ volatile uint8_t dummy24[1]; /* */
+ volatile uint8_t CROMST3; /* CROMST3 */
+ volatile uint8_t CROMST4; /* CROMST4 */
+ volatile uint8_t CROMST5; /* CROMST5 */
+ volatile uint8_t CROMST6; /* CROMST6 */
+ volatile uint8_t dummy25[5]; /* */
+#define ROMDEC_CBUFST0_COUNT 3
+ volatile uint8_t CBUFST0; /* CBUFST0 */
+ volatile uint8_t CBUFST1; /* CBUFST1 */
+ volatile uint8_t CBUFST2; /* CBUFST2 */
+ volatile uint8_t dummy26[1]; /* */
+#define ROMDEC_HEAD00_COUNT 4
+ volatile uint8_t HEAD00; /* HEAD00 */
+ volatile uint8_t HEAD01; /* HEAD01 */
+ volatile uint8_t HEAD02; /* HEAD02 */
+ volatile uint8_t HEAD03; /* HEAD03 */
+#define ROMDEC_SHEAD00_COUNT 8
+ volatile uint8_t SHEAD00; /* SHEAD00 */
+ volatile uint8_t SHEAD01; /* SHEAD01 */
+ volatile uint8_t SHEAD02; /* SHEAD02 */
+ volatile uint8_t SHEAD03; /* SHEAD03 */
+ volatile uint8_t SHEAD04; /* SHEAD04 */
+ volatile uint8_t SHEAD05; /* SHEAD05 */
+ volatile uint8_t SHEAD06; /* SHEAD06 */
+ volatile uint8_t SHEAD07; /* SHEAD07 */
+#define ROMDEC_HEAD20_COUNT 4
+ volatile uint8_t HEAD20; /* HEAD20 */
+ volatile uint8_t HEAD21; /* HEAD21 */
+ volatile uint8_t HEAD22; /* HEAD22 */
+ volatile uint8_t HEAD23; /* HEAD23 */
+#define ROMDEC_SHEAD20_COUNT 8
+ volatile uint8_t SHEAD20; /* SHEAD20 */
+ volatile uint8_t SHEAD21; /* SHEAD21 */
+ volatile uint8_t SHEAD22; /* SHEAD22 */
+ volatile uint8_t SHEAD23; /* SHEAD23 */
+ volatile uint8_t SHEAD24; /* SHEAD24 */
+ volatile uint8_t SHEAD25; /* SHEAD25 */
+ volatile uint8_t SHEAD26; /* SHEAD26 */
+ volatile uint8_t SHEAD27; /* SHEAD27 */
+ volatile uint8_t dummy27[16]; /* */
+#define ROMDEC_CBUFCTL0_COUNT 4
+ volatile uint8_t CBUFCTL0; /* CBUFCTL0 */
+ volatile uint8_t CBUFCTL1; /* CBUFCTL1 */
+ volatile uint8_t CBUFCTL2; /* CBUFCTL2 */
+ volatile uint8_t CBUFCTL3; /* CBUFCTL3 */
+ volatile uint8_t dummy28[1]; /* */
+ volatile uint8_t CROMST0M; /* CROMST0M */
+ volatile uint8_t dummy29[186]; /* */
+ volatile uint8_t ROMDECRST; /* ROMDECRST */
+ volatile uint8_t RSTSTAT; /* RSTSTAT */
+ volatile uint8_t SSI; /* SSI */
+ volatile uint8_t dummy30[5]; /* */
+ volatile uint8_t INTHOLD; /* INTHOLD */
+ volatile uint8_t INHINT; /* INHINT */
+ volatile uint8_t dummy31[246]; /* */
+#define ROMDEC_STRMDIN0_COUNT 2
+ volatile uint16_t STRMDIN0; /* STRMDIN0 */
+ volatile uint16_t STRMDIN2; /* STRMDIN2 */
+ volatile uint16_t STRMDOUT0; /* STRMDOUT0 */
+};
+
+
+#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */
+
+
+#define ROMDECCROMEN ROMDEC.CROMEN
+#define ROMDECCROMSY0 ROMDEC.CROMSY0
+#define ROMDECCROMCTL0 ROMDEC.CROMCTL0
+#define ROMDECCROMCTL1 ROMDEC.CROMCTL1
+#define ROMDECCROMCTL3 ROMDEC.CROMCTL3
+#define ROMDECCROMCTL4 ROMDEC.CROMCTL4
+#define ROMDECCROMCTL5 ROMDEC.CROMCTL5
+#define ROMDECCROMST0 ROMDEC.CROMST0
+#define ROMDECCROMST1 ROMDEC.CROMST1
+#define ROMDECCROMST3 ROMDEC.CROMST3
+#define ROMDECCROMST4 ROMDEC.CROMST4
+#define ROMDECCROMST5 ROMDEC.CROMST5
+#define ROMDECCROMST6 ROMDEC.CROMST6
+#define ROMDECCBUFST0 ROMDEC.CBUFST0
+#define ROMDECCBUFST1 ROMDEC.CBUFST1
+#define ROMDECCBUFST2 ROMDEC.CBUFST2
+#define ROMDECHEAD00 ROMDEC.HEAD00
+#define ROMDECHEAD01 ROMDEC.HEAD01
+#define ROMDECHEAD02 ROMDEC.HEAD02
+#define ROMDECHEAD03 ROMDEC.HEAD03
+#define ROMDECSHEAD00 ROMDEC.SHEAD00
+#define ROMDECSHEAD01 ROMDEC.SHEAD01
+#define ROMDECSHEAD02 ROMDEC.SHEAD02
+#define ROMDECSHEAD03 ROMDEC.SHEAD03
+#define ROMDECSHEAD04 ROMDEC.SHEAD04
+#define ROMDECSHEAD05 ROMDEC.SHEAD05
+#define ROMDECSHEAD06 ROMDEC.SHEAD06
+#define ROMDECSHEAD07 ROMDEC.SHEAD07
+#define ROMDECHEAD20 ROMDEC.HEAD20
+#define ROMDECHEAD21 ROMDEC.HEAD21
+#define ROMDECHEAD22 ROMDEC.HEAD22
+#define ROMDECHEAD23 ROMDEC.HEAD23
+#define ROMDECSHEAD20 ROMDEC.SHEAD20
+#define ROMDECSHEAD21 ROMDEC.SHEAD21
+#define ROMDECSHEAD22 ROMDEC.SHEAD22
+#define ROMDECSHEAD23 ROMDEC.SHEAD23
+#define ROMDECSHEAD24 ROMDEC.SHEAD24
+#define ROMDECSHEAD25 ROMDEC.SHEAD25
+#define ROMDECSHEAD26 ROMDEC.SHEAD26
+#define ROMDECSHEAD27 ROMDEC.SHEAD27
+#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0
+#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1
+#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2
+#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3
+#define ROMDECCROMST0M ROMDEC.CROMST0M
+#define ROMDECROMDECRST ROMDEC.ROMDECRST
+#define ROMDECRSTSTAT ROMDEC.RSTSTAT
+#define ROMDECSSI ROMDEC.SSI
+#define ROMDECINTHOLD ROMDEC.INTHOLD
+#define ROMDECINHINT ROMDEC.INHINT
+#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0
+#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2
+#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,9039 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rscan0_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef RSCAN0_IODEFINE_H
+#define RSCAN0_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_rscan0
+{ /* RSCAN0 */
+/* start of struct st_rscan_from_rscan0cncfg */
+ union iodefine_reg32_t C0CFG; /* C0CFG */
+ union iodefine_reg32_t C0CTR; /* C0CTR */
+ union iodefine_reg32_t C0STS; /* C0STS */
+ union iodefine_reg32_t C0ERFL; /* C0ERFL */
+/* end of struct st_rscan_from_rscan0cncfg */
+
+/* start of struct st_rscan_from_rscan0cncfg */
+ union iodefine_reg32_t C1CFG; /* C1CFG */
+ union iodefine_reg32_t C1CTR; /* C1CTR */
+ union iodefine_reg32_t C1STS; /* C1STS */
+ union iodefine_reg32_t C1ERFL; /* C1ERFL */
+/* end of struct st_rscan_from_rscan0cncfg */
+
+/* start of struct st_rscan_from_rscan0cncfg */
+ union iodefine_reg32_t C2CFG; /* C2CFG */
+ union iodefine_reg32_t C2CTR; /* C2CTR */
+ union iodefine_reg32_t C2STS; /* C2STS */
+ union iodefine_reg32_t C2ERFL; /* C2ERFL */
+/* end of struct st_rscan_from_rscan0cncfg */
+
+/* start of struct st_rscan_from_rscan0cncfg */
+ union iodefine_reg32_t C3CFG; /* C3CFG */
+ union iodefine_reg32_t C3CTR; /* C3CTR */
+ union iodefine_reg32_t C3STS; /* C3STS */
+ union iodefine_reg32_t C3ERFL; /* C3ERFL */
+/* end of struct st_rscan_from_rscan0cncfg */
+
+/* start of struct st_rscan_from_rscan0cncfg */
+ union iodefine_reg32_t C4CFG; /* C4CFG */
+ union iodefine_reg32_t C4CTR; /* C4CTR */
+ union iodefine_reg32_t C4STS; /* C4STS */
+ union iodefine_reg32_t C4ERFL; /* C4ERFL */
+/* end of struct st_rscan_from_rscan0cncfg */
+
+ volatile uint8_t dummy159[52]; /* */
+ union iodefine_reg32_t GCFG; /* GCFG */
+ union iodefine_reg32_t GCTR; /* GCTR */
+ union iodefine_reg32_t GSTS; /* GSTS */
+ union iodefine_reg32_t GERFL; /* GERFL */
+ union iodefine_reg32_16_t GTSC; /* GTSC */
+ union iodefine_reg32_t GAFLECTR; /* GAFLECTR */
+#define RSCAN0_GAFLCFG0_COUNT 2
+ union iodefine_reg32_t GAFLCFG0; /* GAFLCFG0 */
+ union iodefine_reg32_t GAFLCFG1; /* GAFLCFG1 */
+ union iodefine_reg32_t RMNB; /* RMNB */
+#define RSCAN0_RMND0_COUNT 3
+ union iodefine_reg32_t RMND0; /* RMND0 */
+ union iodefine_reg32_t RMND1; /* RMND1 */
+ union iodefine_reg32_t RMND2; /* RMND2 */
+
+ volatile uint8_t dummy160[4]; /* */
+#define RSCAN0_RFCC0_COUNT 8
+ union iodefine_reg32_t RFCC0; /* RFCC0 */
+ union iodefine_reg32_t RFCC1; /* RFCC1 */
+ union iodefine_reg32_t RFCC2; /* RFCC2 */
+ union iodefine_reg32_t RFCC3; /* RFCC3 */
+ union iodefine_reg32_t RFCC4; /* RFCC4 */
+ union iodefine_reg32_t RFCC5; /* RFCC5 */
+ union iodefine_reg32_t RFCC6; /* RFCC6 */
+ union iodefine_reg32_t RFCC7; /* RFCC7 */
+#define RSCAN0_RFSTS0_COUNT 8
+ union iodefine_reg32_t RFSTS0; /* RFSTS0 */
+ union iodefine_reg32_t RFSTS1; /* RFSTS1 */
+ union iodefine_reg32_t RFSTS2; /* RFSTS2 */
+ union iodefine_reg32_t RFSTS3; /* RFSTS3 */
+ union iodefine_reg32_t RFSTS4; /* RFSTS4 */
+ union iodefine_reg32_t RFSTS5; /* RFSTS5 */
+ union iodefine_reg32_t RFSTS6; /* RFSTS6 */
+ union iodefine_reg32_t RFSTS7; /* RFSTS7 */
+#define RSCAN0_RFPCTR0_COUNT 8
+ union iodefine_reg32_t RFPCTR0; /* RFPCTR0 */
+ union iodefine_reg32_t RFPCTR1; /* RFPCTR1 */
+ union iodefine_reg32_t RFPCTR2; /* RFPCTR2 */
+ union iodefine_reg32_t RFPCTR3; /* RFPCTR3 */
+ union iodefine_reg32_t RFPCTR4; /* RFPCTR4 */
+ union iodefine_reg32_t RFPCTR5; /* RFPCTR5 */
+ union iodefine_reg32_t RFPCTR6; /* RFPCTR6 */
+ union iodefine_reg32_t RFPCTR7; /* RFPCTR7 */
+#define RSCAN0_CFCC0_COUNT 15
+ union iodefine_reg32_t CFCC0; /* CFCC0 */
+ union iodefine_reg32_t CFCC1; /* CFCC1 */
+ union iodefine_reg32_t CFCC2; /* CFCC2 */
+ union iodefine_reg32_t CFCC3; /* CFCC3 */
+ union iodefine_reg32_t CFCC4; /* CFCC4 */
+ union iodefine_reg32_t CFCC5; /* CFCC5 */
+ union iodefine_reg32_t CFCC6; /* CFCC6 */
+ union iodefine_reg32_t CFCC7; /* CFCC7 */
+ union iodefine_reg32_t CFCC8; /* CFCC8 */
+ union iodefine_reg32_t CFCC9; /* CFCC9 */
+ union iodefine_reg32_t CFCC10; /* CFCC10 */
+ union iodefine_reg32_t CFCC11; /* CFCC11 */
+ union iodefine_reg32_t CFCC12; /* CFCC12 */
+ union iodefine_reg32_t CFCC13; /* CFCC13 */
+ union iodefine_reg32_t CFCC14; /* CFCC14 */
+
+ volatile uint8_t dummy161[36]; /* */
+#define RSCAN0_CFSTS0_COUNT 15
+ union iodefine_reg32_t CFSTS0; /* CFSTS0 */
+ union iodefine_reg32_t CFSTS1; /* CFSTS1 */
+ union iodefine_reg32_t CFSTS2; /* CFSTS2 */
+ union iodefine_reg32_t CFSTS3; /* CFSTS3 */
+ union iodefine_reg32_t CFSTS4; /* CFSTS4 */
+ union iodefine_reg32_t CFSTS5; /* CFSTS5 */
+ union iodefine_reg32_t CFSTS6; /* CFSTS6 */
+ union iodefine_reg32_t CFSTS7; /* CFSTS7 */
+ union iodefine_reg32_t CFSTS8; /* CFSTS8 */
+ union iodefine_reg32_t CFSTS9; /* CFSTS9 */
+ union iodefine_reg32_t CFSTS10; /* CFSTS10 */
+ union iodefine_reg32_t CFSTS11; /* CFSTS11 */
+ union iodefine_reg32_t CFSTS12; /* CFSTS12 */
+ union iodefine_reg32_t CFSTS13; /* CFSTS13 */
+ union iodefine_reg32_t CFSTS14; /* CFSTS14 */
+
+ volatile uint8_t dummy162[36]; /* */
+#define RSCAN0_CFPCTR0_COUNT 15
+ union iodefine_reg32_t CFPCTR0; /* CFPCTR0 */
+ union iodefine_reg32_t CFPCTR1; /* CFPCTR1 */
+ union iodefine_reg32_t CFPCTR2; /* CFPCTR2 */
+ union iodefine_reg32_t CFPCTR3; /* CFPCTR3 */
+ union iodefine_reg32_t CFPCTR4; /* CFPCTR4 */
+ union iodefine_reg32_t CFPCTR5; /* CFPCTR5 */
+ union iodefine_reg32_t CFPCTR6; /* CFPCTR6 */
+ union iodefine_reg32_t CFPCTR7; /* CFPCTR7 */
+ union iodefine_reg32_t CFPCTR8; /* CFPCTR8 */
+ union iodefine_reg32_t CFPCTR9; /* CFPCTR9 */
+ union iodefine_reg32_t CFPCTR10; /* CFPCTR10 */
+ union iodefine_reg32_t CFPCTR11; /* CFPCTR11 */
+ union iodefine_reg32_t CFPCTR12; /* CFPCTR12 */
+ union iodefine_reg32_t CFPCTR13; /* CFPCTR13 */
+ union iodefine_reg32_t CFPCTR14; /* CFPCTR14 */
+
+ volatile uint8_t dummy163[36]; /* */
+ union iodefine_reg32_t FESTS; /* FESTS */
+ union iodefine_reg32_t FFSTS; /* FFSTS */
+ union iodefine_reg32_t FMSTS; /* FMSTS */
+ union iodefine_reg32_t RFISTS; /* RFISTS */
+ union iodefine_reg32_t CFRISTS; /* CFRISTS */
+ union iodefine_reg32_t CFTISTS; /* CFTISTS */
+
+#define RSCAN0_TMC0_COUNT 80
+ volatile uint8_t TMC0; /* TMC0 */
+ volatile uint8_t TMC1; /* TMC1 */
+ volatile uint8_t TMC2; /* TMC2 */
+ volatile uint8_t TMC3; /* TMC3 */
+ volatile uint8_t TMC4; /* TMC4 */
+ volatile uint8_t TMC5; /* TMC5 */
+ volatile uint8_t TMC6; /* TMC6 */
+ volatile uint8_t TMC7; /* TMC7 */
+ volatile uint8_t TMC8; /* TMC8 */
+ volatile uint8_t TMC9; /* TMC9 */
+ volatile uint8_t TMC10; /* TMC10 */
+ volatile uint8_t TMC11; /* TMC11 */
+ volatile uint8_t TMC12; /* TMC12 */
+ volatile uint8_t TMC13; /* TMC13 */
+ volatile uint8_t TMC14; /* TMC14 */
+ volatile uint8_t TMC15; /* TMC15 */
+ volatile uint8_t TMC16; /* TMC16 */
+ volatile uint8_t TMC17; /* TMC17 */
+ volatile uint8_t TMC18; /* TMC18 */
+ volatile uint8_t TMC19; /* TMC19 */
+ volatile uint8_t TMC20; /* TMC20 */
+ volatile uint8_t TMC21; /* TMC21 */
+ volatile uint8_t TMC22; /* TMC22 */
+ volatile uint8_t TMC23; /* TMC23 */
+ volatile uint8_t TMC24; /* TMC24 */
+ volatile uint8_t TMC25; /* TMC25 */
+ volatile uint8_t TMC26; /* TMC26 */
+ volatile uint8_t TMC27; /* TMC27 */
+ volatile uint8_t TMC28; /* TMC28 */
+ volatile uint8_t TMC29; /* TMC29 */
+ volatile uint8_t TMC30; /* TMC30 */
+ volatile uint8_t TMC31; /* TMC31 */
+ volatile uint8_t TMC32; /* TMC32 */
+ volatile uint8_t TMC33; /* TMC33 */
+ volatile uint8_t TMC34; /* TMC34 */
+ volatile uint8_t TMC35; /* TMC35 */
+ volatile uint8_t TMC36; /* TMC36 */
+ volatile uint8_t TMC37; /* TMC37 */
+ volatile uint8_t TMC38; /* TMC38 */
+ volatile uint8_t TMC39; /* TMC39 */
+ volatile uint8_t TMC40; /* TMC40 */
+ volatile uint8_t TMC41; /* TMC41 */
+ volatile uint8_t TMC42; /* TMC42 */
+ volatile uint8_t TMC43; /* TMC43 */
+ volatile uint8_t TMC44; /* TMC44 */
+ volatile uint8_t TMC45; /* TMC45 */
+ volatile uint8_t TMC46; /* TMC46 */
+ volatile uint8_t TMC47; /* TMC47 */
+ volatile uint8_t TMC48; /* TMC48 */
+ volatile uint8_t TMC49; /* TMC49 */
+ volatile uint8_t TMC50; /* TMC50 */
+ volatile uint8_t TMC51; /* TMC51 */
+ volatile uint8_t TMC52; /* TMC52 */
+ volatile uint8_t TMC53; /* TMC53 */
+ volatile uint8_t TMC54; /* TMC54 */
+ volatile uint8_t TMC55; /* TMC55 */
+ volatile uint8_t TMC56; /* TMC56 */
+ volatile uint8_t TMC57; /* TMC57 */
+ volatile uint8_t TMC58; /* TMC58 */
+ volatile uint8_t TMC59; /* TMC59 */
+ volatile uint8_t TMC60; /* TMC60 */
+ volatile uint8_t TMC61; /* TMC61 */
+ volatile uint8_t TMC62; /* TMC62 */
+ volatile uint8_t TMC63; /* TMC63 */
+ volatile uint8_t TMC64; /* TMC64 */
+ volatile uint8_t TMC65; /* TMC65 */
+ volatile uint8_t TMC66; /* TMC66 */
+ volatile uint8_t TMC67; /* TMC67 */
+ volatile uint8_t TMC68; /* TMC68 */
+ volatile uint8_t TMC69; /* TMC69 */
+ volatile uint8_t TMC70; /* TMC70 */
+ volatile uint8_t TMC71; /* TMC71 */
+ volatile uint8_t TMC72; /* TMC72 */
+ volatile uint8_t TMC73; /* TMC73 */
+ volatile uint8_t TMC74; /* TMC74 */
+ volatile uint8_t TMC75; /* TMC75 */
+ volatile uint8_t TMC76; /* TMC76 */
+ volatile uint8_t TMC77; /* TMC77 */
+ volatile uint8_t TMC78; /* TMC78 */
+ volatile uint8_t TMC79; /* TMC79 */
+ volatile uint8_t dummy164[48]; /* */
+#define RSCAN0_TMSTS0_COUNT 80
+ volatile uint8_t TMSTS0; /* TMSTS0 */
+ volatile uint8_t TMSTS1; /* TMSTS1 */
+ volatile uint8_t TMSTS2; /* TMSTS2 */
+ volatile uint8_t TMSTS3; /* TMSTS3 */
+ volatile uint8_t TMSTS4; /* TMSTS4 */
+ volatile uint8_t TMSTS5; /* TMSTS5 */
+ volatile uint8_t TMSTS6; /* TMSTS6 */
+ volatile uint8_t TMSTS7; /* TMSTS7 */
+ volatile uint8_t TMSTS8; /* TMSTS8 */
+ volatile uint8_t TMSTS9; /* TMSTS9 */
+ volatile uint8_t TMSTS10; /* TMSTS10 */
+ volatile uint8_t TMSTS11; /* TMSTS11 */
+ volatile uint8_t TMSTS12; /* TMSTS12 */
+ volatile uint8_t TMSTS13; /* TMSTS13 */
+ volatile uint8_t TMSTS14; /* TMSTS14 */
+ volatile uint8_t TMSTS15; /* TMSTS15 */
+ volatile uint8_t TMSTS16; /* TMSTS16 */
+ volatile uint8_t TMSTS17; /* TMSTS17 */
+ volatile uint8_t TMSTS18; /* TMSTS18 */
+ volatile uint8_t TMSTS19; /* TMSTS19 */
+ volatile uint8_t TMSTS20; /* TMSTS20 */
+ volatile uint8_t TMSTS21; /* TMSTS21 */
+ volatile uint8_t TMSTS22; /* TMSTS22 */
+ volatile uint8_t TMSTS23; /* TMSTS23 */
+ volatile uint8_t TMSTS24; /* TMSTS24 */
+ volatile uint8_t TMSTS25; /* TMSTS25 */
+ volatile uint8_t TMSTS26; /* TMSTS26 */
+ volatile uint8_t TMSTS27; /* TMSTS27 */
+ volatile uint8_t TMSTS28; /* TMSTS28 */
+ volatile uint8_t TMSTS29; /* TMSTS29 */
+ volatile uint8_t TMSTS30; /* TMSTS30 */
+ volatile uint8_t TMSTS31; /* TMSTS31 */
+ volatile uint8_t TMSTS32; /* TMSTS32 */
+ volatile uint8_t TMSTS33; /* TMSTS33 */
+ volatile uint8_t TMSTS34; /* TMSTS34 */
+ volatile uint8_t TMSTS35; /* TMSTS35 */
+ volatile uint8_t TMSTS36; /* TMSTS36 */
+ volatile uint8_t TMSTS37; /* TMSTS37 */
+ volatile uint8_t TMSTS38; /* TMSTS38 */
+ volatile uint8_t TMSTS39; /* TMSTS39 */
+ volatile uint8_t TMSTS40; /* TMSTS40 */
+ volatile uint8_t TMSTS41; /* TMSTS41 */
+ volatile uint8_t TMSTS42; /* TMSTS42 */
+ volatile uint8_t TMSTS43; /* TMSTS43 */
+ volatile uint8_t TMSTS44; /* TMSTS44 */
+ volatile uint8_t TMSTS45; /* TMSTS45 */
+ volatile uint8_t TMSTS46; /* TMSTS46 */
+ volatile uint8_t TMSTS47; /* TMSTS47 */
+ volatile uint8_t TMSTS48; /* TMSTS48 */
+ volatile uint8_t TMSTS49; /* TMSTS49 */
+ volatile uint8_t TMSTS50; /* TMSTS50 */
+ volatile uint8_t TMSTS51; /* TMSTS51 */
+ volatile uint8_t TMSTS52; /* TMSTS52 */
+ volatile uint8_t TMSTS53; /* TMSTS53 */
+ volatile uint8_t TMSTS54; /* TMSTS54 */
+ volatile uint8_t TMSTS55; /* TMSTS55 */
+ volatile uint8_t TMSTS56; /* TMSTS56 */
+ volatile uint8_t TMSTS57; /* TMSTS57 */
+ volatile uint8_t TMSTS58; /* TMSTS58 */
+ volatile uint8_t TMSTS59; /* TMSTS59 */
+ volatile uint8_t TMSTS60; /* TMSTS60 */
+ volatile uint8_t TMSTS61; /* TMSTS61 */
+ volatile uint8_t TMSTS62; /* TMSTS62 */
+ volatile uint8_t TMSTS63; /* TMSTS63 */
+ volatile uint8_t TMSTS64; /* TMSTS64 */
+ volatile uint8_t TMSTS65; /* TMSTS65 */
+ volatile uint8_t TMSTS66; /* TMSTS66 */
+ volatile uint8_t TMSTS67; /* TMSTS67 */
+ volatile uint8_t TMSTS68; /* TMSTS68 */
+ volatile uint8_t TMSTS69; /* TMSTS69 */
+ volatile uint8_t TMSTS70; /* TMSTS70 */
+ volatile uint8_t TMSTS71; /* TMSTS71 */
+ volatile uint8_t TMSTS72; /* TMSTS72 */
+ volatile uint8_t TMSTS73; /* TMSTS73 */
+ volatile uint8_t TMSTS74; /* TMSTS74 */
+ volatile uint8_t TMSTS75; /* TMSTS75 */
+ volatile uint8_t TMSTS76; /* TMSTS76 */
+ volatile uint8_t TMSTS77; /* TMSTS77 */
+ volatile uint8_t TMSTS78; /* TMSTS78 */
+ volatile uint8_t TMSTS79; /* TMSTS79 */
+ volatile uint8_t dummy165[48]; /* */
+#define RSCAN0_TMTRSTS0_COUNT 3
+ union iodefine_reg32_t TMTRSTS0; /* TMTRSTS0 */
+ union iodefine_reg32_t TMTRSTS1; /* TMTRSTS1 */
+ union iodefine_reg32_t TMTRSTS2; /* TMTRSTS2 */
+
+ volatile uint8_t dummy166[4]; /* */
+#define RSCAN0_TMTARSTS0_COUNT 3
+ union iodefine_reg32_t TMTARSTS0; /* TMTARSTS0 */
+ union iodefine_reg32_t TMTARSTS1; /* TMTARSTS1 */
+ union iodefine_reg32_t TMTARSTS2; /* TMTARSTS2 */
+
+ volatile uint8_t dummy167[4]; /* */
+#define RSCAN0_TMTCSTS0_COUNT 3
+ union iodefine_reg32_t TMTCSTS0; /* TMTCSTS0 */
+ union iodefine_reg32_t TMTCSTS1; /* TMTCSTS1 */
+ union iodefine_reg32_t TMTCSTS2; /* TMTCSTS2 */
+
+ volatile uint8_t dummy168[4]; /* */
+#define RSCAN0_TMTASTS0_COUNT 3
+ union iodefine_reg32_t TMTASTS0; /* TMTASTS0 */
+ union iodefine_reg32_t TMTASTS1; /* TMTASTS1 */
+ union iodefine_reg32_t TMTASTS2; /* TMTASTS2 */
+
+ volatile uint8_t dummy169[4]; /* */
+#define RSCAN0_TMIEC0_COUNT 3
+ union iodefine_reg32_t TMIEC0; /* TMIEC0 */
+ union iodefine_reg32_t TMIEC1; /* TMIEC1 */
+ union iodefine_reg32_t TMIEC2; /* TMIEC2 */
+
+ volatile uint8_t dummy170[4]; /* */
+#define RSCAN0_TXQCC0_COUNT 5
+ union iodefine_reg32_t TXQCC0; /* TXQCC0 */
+ union iodefine_reg32_t TXQCC1; /* TXQCC1 */
+ union iodefine_reg32_t TXQCC2; /* TXQCC2 */
+ union iodefine_reg32_t TXQCC3; /* TXQCC3 */
+ union iodefine_reg32_t TXQCC4; /* TXQCC4 */
+
+ volatile uint8_t dummy171[12]; /* */
+#define RSCAN0_TXQSTS0_COUNT 5
+ union iodefine_reg32_t TXQSTS0; /* TXQSTS0 */
+ union iodefine_reg32_t TXQSTS1; /* TXQSTS1 */
+ union iodefine_reg32_t TXQSTS2; /* TXQSTS2 */
+ union iodefine_reg32_t TXQSTS3; /* TXQSTS3 */
+ union iodefine_reg32_t TXQSTS4; /* TXQSTS4 */
+
+ volatile uint8_t dummy172[12]; /* */
+#define RSCAN0_TXQPCTR0_COUNT 5
+ union iodefine_reg32_t TXQPCTR0; /* TXQPCTR0 */
+ union iodefine_reg32_t TXQPCTR1; /* TXQPCTR1 */
+ union iodefine_reg32_t TXQPCTR2; /* TXQPCTR2 */
+ union iodefine_reg32_t TXQPCTR3; /* TXQPCTR3 */
+ union iodefine_reg32_t TXQPCTR4; /* TXQPCTR4 */
+
+ volatile uint8_t dummy173[12]; /* */
+#define RSCAN0_THLCC0_COUNT 5
+ union iodefine_reg32_t THLCC0; /* THLCC0 */
+ union iodefine_reg32_t THLCC1; /* THLCC1 */
+ union iodefine_reg32_t THLCC2; /* THLCC2 */
+ union iodefine_reg32_t THLCC3; /* THLCC3 */
+ union iodefine_reg32_t THLCC4; /* THLCC4 */
+
+ volatile uint8_t dummy174[12]; /* */
+#define RSCAN0_THLSTS0_COUNT 5
+ union iodefine_reg32_t THLSTS0; /* THLSTS0 */
+ union iodefine_reg32_t THLSTS1; /* THLSTS1 */
+ union iodefine_reg32_t THLSTS2; /* THLSTS2 */
+ union iodefine_reg32_t THLSTS3; /* THLSTS3 */
+ union iodefine_reg32_t THLSTS4; /* THLSTS4 */
+
+ volatile uint8_t dummy175[12]; /* */
+#define RSCAN0_THLPCTR0_COUNT 5
+ union iodefine_reg32_t THLPCTR0; /* THLPCTR0 */
+ union iodefine_reg32_t THLPCTR1; /* THLPCTR1 */
+ union iodefine_reg32_t THLPCTR2; /* THLPCTR2 */
+ union iodefine_reg32_t THLPCTR3; /* THLPCTR3 */
+ union iodefine_reg32_t THLPCTR4; /* THLPCTR4 */
+
+ volatile uint8_t dummy176[12]; /* */
+#define RSCAN0_GTINTSTS0_COUNT 2
+ union iodefine_reg32_t GTINTSTS0; /* GTINTSTS0 */
+ union iodefine_reg32_t GTINTSTS1; /* GTINTSTS1 */
+ union iodefine_reg32_t GTSTCFG; /* GTSTCFG */
+ union iodefine_reg32_t GTSTCTR; /* GTSTCTR */
+
+ volatile uint8_t dummy177[12]; /* */
+ union iodefine_reg32_16_t GLOCKK; /* GLOCKK */
+
+ volatile uint8_t dummy178[128]; /* */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID0; /* GAFLID0 */
+ union iodefine_reg32_t GAFLM0; /* GAFLM0 */
+ union iodefine_reg32_t GAFLP00; /* GAFLP00 */
+ union iodefine_reg32_t GAFLP10; /* GAFLP10 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID1; /* GAFLID1 */
+ union iodefine_reg32_t GAFLM1; /* GAFLM1 */
+ union iodefine_reg32_t GAFLP01; /* GAFLP01 */
+ union iodefine_reg32_t GAFLP11; /* GAFLP11 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID2; /* GAFLID2 */
+ union iodefine_reg32_t GAFLM2; /* GAFLM2 */
+ union iodefine_reg32_t GAFLP02; /* GAFLP02 */
+ union iodefine_reg32_t GAFLP12; /* GAFLP12 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID3; /* GAFLID3 */
+ union iodefine_reg32_t GAFLM3; /* GAFLM3 */
+ union iodefine_reg32_t GAFLP03; /* GAFLP03 */
+ union iodefine_reg32_t GAFLP13; /* GAFLP13 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID4; /* GAFLID4 */
+ union iodefine_reg32_t GAFLM4; /* GAFLM4 */
+ union iodefine_reg32_t GAFLP04; /* GAFLP04 */
+ union iodefine_reg32_t GAFLP14; /* GAFLP14 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID5; /* GAFLID5 */
+ union iodefine_reg32_t GAFLM5; /* GAFLM5 */
+ union iodefine_reg32_t GAFLP05; /* GAFLP05 */
+ union iodefine_reg32_t GAFLP15; /* GAFLP15 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID6; /* GAFLID6 */
+ union iodefine_reg32_t GAFLM6; /* GAFLM6 */
+ union iodefine_reg32_t GAFLP06; /* GAFLP06 */
+ union iodefine_reg32_t GAFLP16; /* GAFLP16 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID7; /* GAFLID7 */
+ union iodefine_reg32_t GAFLM7; /* GAFLM7 */
+ union iodefine_reg32_t GAFLP07; /* GAFLP07 */
+ union iodefine_reg32_t GAFLP17; /* GAFLP17 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID8; /* GAFLID8 */
+ union iodefine_reg32_t GAFLM8; /* GAFLM8 */
+ union iodefine_reg32_t GAFLP08; /* GAFLP08 */
+ union iodefine_reg32_t GAFLP18; /* GAFLP18 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID9; /* GAFLID9 */
+ union iodefine_reg32_t GAFLM9; /* GAFLM9 */
+ union iodefine_reg32_t GAFLP09; /* GAFLP09 */
+ union iodefine_reg32_t GAFLP19; /* GAFLP19 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID10; /* GAFLID10 */
+ union iodefine_reg32_t GAFLM10; /* GAFLM10 */
+ union iodefine_reg32_t GAFLP010; /* GAFLP010 */
+ union iodefine_reg32_t GAFLP110; /* GAFLP110 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID11; /* GAFLID11 */
+ union iodefine_reg32_t GAFLM11; /* GAFLM11 */
+ union iodefine_reg32_t GAFLP011; /* GAFLP011 */
+ union iodefine_reg32_t GAFLP111; /* GAFLP111 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID12; /* GAFLID12 */
+ union iodefine_reg32_t GAFLM12; /* GAFLM12 */
+ union iodefine_reg32_t GAFLP012; /* GAFLP012 */
+ union iodefine_reg32_t GAFLP112; /* GAFLP112 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID13; /* GAFLID13 */
+ union iodefine_reg32_t GAFLM13; /* GAFLM13 */
+ union iodefine_reg32_t GAFLP013; /* GAFLP013 */
+ union iodefine_reg32_t GAFLP113; /* GAFLP113 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID14; /* GAFLID14 */
+ union iodefine_reg32_t GAFLM14; /* GAFLM14 */
+ union iodefine_reg32_t GAFLP014; /* GAFLP014 */
+ union iodefine_reg32_t GAFLP114; /* GAFLP114 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0gaflidj */
+ union iodefine_reg32_t GAFLID15; /* GAFLID15 */
+ union iodefine_reg32_t GAFLM15; /* GAFLM15 */
+ union iodefine_reg32_t GAFLP015; /* GAFLP015 */
+ union iodefine_reg32_t GAFLP115; /* GAFLP115 */
+/* end of struct st_rscan_from_rscan0gaflidj */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID0; /* RMID0 */
+ union iodefine_reg32_t RMPTR0; /* RMPTR0 */
+ union iodefine_reg32_t RMDF00; /* RMDF00 */
+ union iodefine_reg32_t RMDF10; /* RMDF10 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID1; /* RMID1 */
+ union iodefine_reg32_t RMPTR1; /* RMPTR1 */
+ union iodefine_reg32_t RMDF01; /* RMDF01 */
+ union iodefine_reg32_t RMDF11; /* RMDF11 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID2; /* RMID2 */
+ union iodefine_reg32_t RMPTR2; /* RMPTR2 */
+ union iodefine_reg32_t RMDF02; /* RMDF02 */
+ union iodefine_reg32_t RMDF12; /* RMDF12 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID3; /* RMID3 */
+ union iodefine_reg32_t RMPTR3; /* RMPTR3 */
+ union iodefine_reg32_t RMDF03; /* RMDF03 */
+ union iodefine_reg32_t RMDF13; /* RMDF13 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID4; /* RMID4 */
+ union iodefine_reg32_t RMPTR4; /* RMPTR4 */
+ union iodefine_reg32_t RMDF04; /* RMDF04 */
+ union iodefine_reg32_t RMDF14; /* RMDF14 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID5; /* RMID5 */
+ union iodefine_reg32_t RMPTR5; /* RMPTR5 */
+ union iodefine_reg32_t RMDF05; /* RMDF05 */
+ union iodefine_reg32_t RMDF15; /* RMDF15 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID6; /* RMID6 */
+ union iodefine_reg32_t RMPTR6; /* RMPTR6 */
+ union iodefine_reg32_t RMDF06; /* RMDF06 */
+ union iodefine_reg32_t RMDF16; /* RMDF16 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID7; /* RMID7 */
+ union iodefine_reg32_t RMPTR7; /* RMPTR7 */
+ union iodefine_reg32_t RMDF07; /* RMDF07 */
+ union iodefine_reg32_t RMDF17; /* RMDF17 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID8; /* RMID8 */
+ union iodefine_reg32_t RMPTR8; /* RMPTR8 */
+ union iodefine_reg32_t RMDF08; /* RMDF08 */
+ union iodefine_reg32_t RMDF18; /* RMDF18 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID9; /* RMID9 */
+ union iodefine_reg32_t RMPTR9; /* RMPTR9 */
+ union iodefine_reg32_t RMDF09; /* RMDF09 */
+ union iodefine_reg32_t RMDF19; /* RMDF19 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID10; /* RMID10 */
+ union iodefine_reg32_t RMPTR10; /* RMPTR10 */
+ union iodefine_reg32_t RMDF010; /* RMDF010 */
+ union iodefine_reg32_t RMDF110; /* RMDF110 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID11; /* RMID11 */
+ union iodefine_reg32_t RMPTR11; /* RMPTR11 */
+ union iodefine_reg32_t RMDF011; /* RMDF011 */
+ union iodefine_reg32_t RMDF111; /* RMDF111 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID12; /* RMID12 */
+ union iodefine_reg32_t RMPTR12; /* RMPTR12 */
+ union iodefine_reg32_t RMDF012; /* RMDF012 */
+ union iodefine_reg32_t RMDF112; /* RMDF112 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID13; /* RMID13 */
+ union iodefine_reg32_t RMPTR13; /* RMPTR13 */
+ union iodefine_reg32_t RMDF013; /* RMDF013 */
+ union iodefine_reg32_t RMDF113; /* RMDF113 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID14; /* RMID14 */
+ union iodefine_reg32_t RMPTR14; /* RMPTR14 */
+ union iodefine_reg32_t RMDF014; /* RMDF014 */
+ union iodefine_reg32_t RMDF114; /* RMDF114 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID15; /* RMID15 */
+ union iodefine_reg32_t RMPTR15; /* RMPTR15 */
+ union iodefine_reg32_t RMDF015; /* RMDF015 */
+ union iodefine_reg32_t RMDF115; /* RMDF115 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID16; /* RMID16 */
+ union iodefine_reg32_t RMPTR16; /* RMPTR16 */
+ union iodefine_reg32_t RMDF016; /* RMDF016 */
+ union iodefine_reg32_t RMDF116; /* RMDF116 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID17; /* RMID17 */
+ union iodefine_reg32_t RMPTR17; /* RMPTR17 */
+ union iodefine_reg32_t RMDF017; /* RMDF017 */
+ union iodefine_reg32_t RMDF117; /* RMDF117 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID18; /* RMID18 */
+ union iodefine_reg32_t RMPTR18; /* RMPTR18 */
+ union iodefine_reg32_t RMDF018; /* RMDF018 */
+ union iodefine_reg32_t RMDF118; /* RMDF118 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID19; /* RMID19 */
+ union iodefine_reg32_t RMPTR19; /* RMPTR19 */
+ union iodefine_reg32_t RMDF019; /* RMDF019 */
+ union iodefine_reg32_t RMDF119; /* RMDF119 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID20; /* RMID20 */
+ union iodefine_reg32_t RMPTR20; /* RMPTR20 */
+ union iodefine_reg32_t RMDF020; /* RMDF020 */
+ union iodefine_reg32_t RMDF120; /* RMDF120 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID21; /* RMID21 */
+ union iodefine_reg32_t RMPTR21; /* RMPTR21 */
+ union iodefine_reg32_t RMDF021; /* RMDF021 */
+ union iodefine_reg32_t RMDF121; /* RMDF121 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID22; /* RMID22 */
+ union iodefine_reg32_t RMPTR22; /* RMPTR22 */
+ union iodefine_reg32_t RMDF022; /* RMDF022 */
+ union iodefine_reg32_t RMDF122; /* RMDF122 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID23; /* RMID23 */
+ union iodefine_reg32_t RMPTR23; /* RMPTR23 */
+ union iodefine_reg32_t RMDF023; /* RMDF023 */
+ union iodefine_reg32_t RMDF123; /* RMDF123 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID24; /* RMID24 */
+ union iodefine_reg32_t RMPTR24; /* RMPTR24 */
+ union iodefine_reg32_t RMDF024; /* RMDF024 */
+ union iodefine_reg32_t RMDF124; /* RMDF124 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID25; /* RMID25 */
+ union iodefine_reg32_t RMPTR25; /* RMPTR25 */
+ union iodefine_reg32_t RMDF025; /* RMDF025 */
+ union iodefine_reg32_t RMDF125; /* RMDF125 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID26; /* RMID26 */
+ union iodefine_reg32_t RMPTR26; /* RMPTR26 */
+ union iodefine_reg32_t RMDF026; /* RMDF026 */
+ union iodefine_reg32_t RMDF126; /* RMDF126 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID27; /* RMID27 */
+ union iodefine_reg32_t RMPTR27; /* RMPTR27 */
+ union iodefine_reg32_t RMDF027; /* RMDF027 */
+ union iodefine_reg32_t RMDF127; /* RMDF127 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID28; /* RMID28 */
+ union iodefine_reg32_t RMPTR28; /* RMPTR28 */
+ union iodefine_reg32_t RMDF028; /* RMDF028 */
+ union iodefine_reg32_t RMDF128; /* RMDF128 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID29; /* RMID29 */
+ union iodefine_reg32_t RMPTR29; /* RMPTR29 */
+ union iodefine_reg32_t RMDF029; /* RMDF029 */
+ union iodefine_reg32_t RMDF129; /* RMDF129 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID30; /* RMID30 */
+ union iodefine_reg32_t RMPTR30; /* RMPTR30 */
+ union iodefine_reg32_t RMDF030; /* RMDF030 */
+ union iodefine_reg32_t RMDF130; /* RMDF130 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID31; /* RMID31 */
+ union iodefine_reg32_t RMPTR31; /* RMPTR31 */
+ union iodefine_reg32_t RMDF031; /* RMDF031 */
+ union iodefine_reg32_t RMDF131; /* RMDF131 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID32; /* RMID32 */
+ union iodefine_reg32_t RMPTR32; /* RMPTR32 */
+ union iodefine_reg32_t RMDF032; /* RMDF032 */
+ union iodefine_reg32_t RMDF132; /* RMDF132 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID33; /* RMID33 */
+ union iodefine_reg32_t RMPTR33; /* RMPTR33 */
+ union iodefine_reg32_t RMDF033; /* RMDF033 */
+ union iodefine_reg32_t RMDF133; /* RMDF133 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID34; /* RMID34 */
+ union iodefine_reg32_t RMPTR34; /* RMPTR34 */
+ union iodefine_reg32_t RMDF034; /* RMDF034 */
+ union iodefine_reg32_t RMDF134; /* RMDF134 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID35; /* RMID35 */
+ union iodefine_reg32_t RMPTR35; /* RMPTR35 */
+ union iodefine_reg32_t RMDF035; /* RMDF035 */
+ union iodefine_reg32_t RMDF135; /* RMDF135 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID36; /* RMID36 */
+ union iodefine_reg32_t RMPTR36; /* RMPTR36 */
+ union iodefine_reg32_t RMDF036; /* RMDF036 */
+ union iodefine_reg32_t RMDF136; /* RMDF136 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID37; /* RMID37 */
+ union iodefine_reg32_t RMPTR37; /* RMPTR37 */
+ union iodefine_reg32_t RMDF037; /* RMDF037 */
+ union iodefine_reg32_t RMDF137; /* RMDF137 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID38; /* RMID38 */
+ union iodefine_reg32_t RMPTR38; /* RMPTR38 */
+ union iodefine_reg32_t RMDF038; /* RMDF038 */
+ union iodefine_reg32_t RMDF138; /* RMDF138 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID39; /* RMID39 */
+ union iodefine_reg32_t RMPTR39; /* RMPTR39 */
+ union iodefine_reg32_t RMDF039; /* RMDF039 */
+ union iodefine_reg32_t RMDF139; /* RMDF139 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID40; /* RMID40 */
+ union iodefine_reg32_t RMPTR40; /* RMPTR40 */
+ union iodefine_reg32_t RMDF040; /* RMDF040 */
+ union iodefine_reg32_t RMDF140; /* RMDF140 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID41; /* RMID41 */
+ union iodefine_reg32_t RMPTR41; /* RMPTR41 */
+ union iodefine_reg32_t RMDF041; /* RMDF041 */
+ union iodefine_reg32_t RMDF141; /* RMDF141 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID42; /* RMID42 */
+ union iodefine_reg32_t RMPTR42; /* RMPTR42 */
+ union iodefine_reg32_t RMDF042; /* RMDF042 */
+ union iodefine_reg32_t RMDF142; /* RMDF142 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID43; /* RMID43 */
+ union iodefine_reg32_t RMPTR43; /* RMPTR43 */
+ union iodefine_reg32_t RMDF043; /* RMDF043 */
+ union iodefine_reg32_t RMDF143; /* RMDF143 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID44; /* RMID44 */
+ union iodefine_reg32_t RMPTR44; /* RMPTR44 */
+ union iodefine_reg32_t RMDF044; /* RMDF044 */
+ union iodefine_reg32_t RMDF144; /* RMDF144 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID45; /* RMID45 */
+ union iodefine_reg32_t RMPTR45; /* RMPTR45 */
+ union iodefine_reg32_t RMDF045; /* RMDF045 */
+ union iodefine_reg32_t RMDF145; /* RMDF145 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID46; /* RMID46 */
+ union iodefine_reg32_t RMPTR46; /* RMPTR46 */
+ union iodefine_reg32_t RMDF046; /* RMDF046 */
+ union iodefine_reg32_t RMDF146; /* RMDF146 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID47; /* RMID47 */
+ union iodefine_reg32_t RMPTR47; /* RMPTR47 */
+ union iodefine_reg32_t RMDF047; /* RMDF047 */
+ union iodefine_reg32_t RMDF147; /* RMDF147 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID48; /* RMID48 */
+ union iodefine_reg32_t RMPTR48; /* RMPTR48 */
+ union iodefine_reg32_t RMDF048; /* RMDF048 */
+ union iodefine_reg32_t RMDF148; /* RMDF148 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID49; /* RMID49 */
+ union iodefine_reg32_t RMPTR49; /* RMPTR49 */
+ union iodefine_reg32_t RMDF049; /* RMDF049 */
+ union iodefine_reg32_t RMDF149; /* RMDF149 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID50; /* RMID50 */
+ union iodefine_reg32_t RMPTR50; /* RMPTR50 */
+ union iodefine_reg32_t RMDF050; /* RMDF050 */
+ union iodefine_reg32_t RMDF150; /* RMDF150 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID51; /* RMID51 */
+ union iodefine_reg32_t RMPTR51; /* RMPTR51 */
+ union iodefine_reg32_t RMDF051; /* RMDF051 */
+ union iodefine_reg32_t RMDF151; /* RMDF151 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID52; /* RMID52 */
+ union iodefine_reg32_t RMPTR52; /* RMPTR52 */
+ union iodefine_reg32_t RMDF052; /* RMDF052 */
+ union iodefine_reg32_t RMDF152; /* RMDF152 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID53; /* RMID53 */
+ union iodefine_reg32_t RMPTR53; /* RMPTR53 */
+ union iodefine_reg32_t RMDF053; /* RMDF053 */
+ union iodefine_reg32_t RMDF153; /* RMDF153 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID54; /* RMID54 */
+ union iodefine_reg32_t RMPTR54; /* RMPTR54 */
+ union iodefine_reg32_t RMDF054; /* RMDF054 */
+ union iodefine_reg32_t RMDF154; /* RMDF154 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID55; /* RMID55 */
+ union iodefine_reg32_t RMPTR55; /* RMPTR55 */
+ union iodefine_reg32_t RMDF055; /* RMDF055 */
+ union iodefine_reg32_t RMDF155; /* RMDF155 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID56; /* RMID56 */
+ union iodefine_reg32_t RMPTR56; /* RMPTR56 */
+ union iodefine_reg32_t RMDF056; /* RMDF056 */
+ union iodefine_reg32_t RMDF156; /* RMDF156 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID57; /* RMID57 */
+ union iodefine_reg32_t RMPTR57; /* RMPTR57 */
+ union iodefine_reg32_t RMDF057; /* RMDF057 */
+ union iodefine_reg32_t RMDF157; /* RMDF157 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID58; /* RMID58 */
+ union iodefine_reg32_t RMPTR58; /* RMPTR58 */
+ union iodefine_reg32_t RMDF058; /* RMDF058 */
+ union iodefine_reg32_t RMDF158; /* RMDF158 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID59; /* RMID59 */
+ union iodefine_reg32_t RMPTR59; /* RMPTR59 */
+ union iodefine_reg32_t RMDF059; /* RMDF059 */
+ union iodefine_reg32_t RMDF159; /* RMDF159 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID60; /* RMID60 */
+ union iodefine_reg32_t RMPTR60; /* RMPTR60 */
+ union iodefine_reg32_t RMDF060; /* RMDF060 */
+ union iodefine_reg32_t RMDF160; /* RMDF160 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID61; /* RMID61 */
+ union iodefine_reg32_t RMPTR61; /* RMPTR61 */
+ union iodefine_reg32_t RMDF061; /* RMDF061 */
+ union iodefine_reg32_t RMDF161; /* RMDF161 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID62; /* RMID62 */
+ union iodefine_reg32_t RMPTR62; /* RMPTR62 */
+ union iodefine_reg32_t RMDF062; /* RMDF062 */
+ union iodefine_reg32_t RMDF162; /* RMDF162 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID63; /* RMID63 */
+ union iodefine_reg32_t RMPTR63; /* RMPTR63 */
+ union iodefine_reg32_t RMDF063; /* RMDF063 */
+ union iodefine_reg32_t RMDF163; /* RMDF163 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID64; /* RMID64 */
+ union iodefine_reg32_t RMPTR64; /* RMPTR64 */
+ union iodefine_reg32_t RMDF064; /* RMDF064 */
+ union iodefine_reg32_t RMDF164; /* RMDF164 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID65; /* RMID65 */
+ union iodefine_reg32_t RMPTR65; /* RMPTR65 */
+ union iodefine_reg32_t RMDF065; /* RMDF065 */
+ union iodefine_reg32_t RMDF165; /* RMDF165 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID66; /* RMID66 */
+ union iodefine_reg32_t RMPTR66; /* RMPTR66 */
+ union iodefine_reg32_t RMDF066; /* RMDF066 */
+ union iodefine_reg32_t RMDF166; /* RMDF166 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID67; /* RMID67 */
+ union iodefine_reg32_t RMPTR67; /* RMPTR67 */
+ union iodefine_reg32_t RMDF067; /* RMDF067 */
+ union iodefine_reg32_t RMDF167; /* RMDF167 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID68; /* RMID68 */
+ union iodefine_reg32_t RMPTR68; /* RMPTR68 */
+ union iodefine_reg32_t RMDF068; /* RMDF068 */
+ union iodefine_reg32_t RMDF168; /* RMDF168 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID69; /* RMID69 */
+ union iodefine_reg32_t RMPTR69; /* RMPTR69 */
+ union iodefine_reg32_t RMDF069; /* RMDF069 */
+ union iodefine_reg32_t RMDF169; /* RMDF169 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID70; /* RMID70 */
+ union iodefine_reg32_t RMPTR70; /* RMPTR70 */
+ union iodefine_reg32_t RMDF070; /* RMDF070 */
+ union iodefine_reg32_t RMDF170; /* RMDF170 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID71; /* RMID71 */
+ union iodefine_reg32_t RMPTR71; /* RMPTR71 */
+ union iodefine_reg32_t RMDF071; /* RMDF071 */
+ union iodefine_reg32_t RMDF171; /* RMDF171 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID72; /* RMID72 */
+ union iodefine_reg32_t RMPTR72; /* RMPTR72 */
+ union iodefine_reg32_t RMDF072; /* RMDF072 */
+ union iodefine_reg32_t RMDF172; /* RMDF172 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID73; /* RMID73 */
+ union iodefine_reg32_t RMPTR73; /* RMPTR73 */
+ union iodefine_reg32_t RMDF073; /* RMDF073 */
+ union iodefine_reg32_t RMDF173; /* RMDF173 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID74; /* RMID74 */
+ union iodefine_reg32_t RMPTR74; /* RMPTR74 */
+ union iodefine_reg32_t RMDF074; /* RMDF074 */
+ union iodefine_reg32_t RMDF174; /* RMDF174 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID75; /* RMID75 */
+ union iodefine_reg32_t RMPTR75; /* RMPTR75 */
+ union iodefine_reg32_t RMDF075; /* RMDF075 */
+ union iodefine_reg32_t RMDF175; /* RMDF175 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID76; /* RMID76 */
+ union iodefine_reg32_t RMPTR76; /* RMPTR76 */
+ union iodefine_reg32_t RMDF076; /* RMDF076 */
+ union iodefine_reg32_t RMDF176; /* RMDF176 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID77; /* RMID77 */
+ union iodefine_reg32_t RMPTR77; /* RMPTR77 */
+ union iodefine_reg32_t RMDF077; /* RMDF077 */
+ union iodefine_reg32_t RMDF177; /* RMDF177 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID78; /* RMID78 */
+ union iodefine_reg32_t RMPTR78; /* RMPTR78 */
+ union iodefine_reg32_t RMDF078; /* RMDF078 */
+ union iodefine_reg32_t RMDF178; /* RMDF178 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+/* start of struct st_rscan_from_rscan0rmidp */
+ union iodefine_reg32_t RMID79; /* RMID79 */
+ union iodefine_reg32_t RMPTR79; /* RMPTR79 */
+ union iodefine_reg32_t RMDF079; /* RMDF079 */
+ union iodefine_reg32_t RMDF179; /* RMDF179 */
+/* end of struct st_rscan_from_rscan0rmidp */
+
+ volatile uint8_t dummy179[768]; /* */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID0; /* RFID0 */
+ union iodefine_reg32_t RFPTR0; /* RFPTR0 */
+ union iodefine_reg32_t RFDF00; /* RFDF00 */
+ union iodefine_reg32_t RFDF10; /* RFDF10 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID1; /* RFID1 */
+ union iodefine_reg32_t RFPTR1; /* RFPTR1 */
+ union iodefine_reg32_t RFDF01; /* RFDF01 */
+ union iodefine_reg32_t RFDF11; /* RFDF11 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID2; /* RFID2 */
+ union iodefine_reg32_t RFPTR2; /* RFPTR2 */
+ union iodefine_reg32_t RFDF02; /* RFDF02 */
+ union iodefine_reg32_t RFDF12; /* RFDF12 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID3; /* RFID3 */
+ union iodefine_reg32_t RFPTR3; /* RFPTR3 */
+ union iodefine_reg32_t RFDF03; /* RFDF03 */
+ union iodefine_reg32_t RFDF13; /* RFDF13 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID4; /* RFID4 */
+ union iodefine_reg32_t RFPTR4; /* RFPTR4 */
+ union iodefine_reg32_t RFDF04; /* RFDF04 */
+ union iodefine_reg32_t RFDF14; /* RFDF14 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID5; /* RFID5 */
+ union iodefine_reg32_t RFPTR5; /* RFPTR5 */
+ union iodefine_reg32_t RFDF05; /* RFDF05 */
+ union iodefine_reg32_t RFDF15; /* RFDF15 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID6; /* RFID6 */
+ union iodefine_reg32_t RFPTR6; /* RFPTR6 */
+ union iodefine_reg32_t RFDF06; /* RFDF06 */
+ union iodefine_reg32_t RFDF16; /* RFDF16 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0rfidm */
+ union iodefine_reg32_t RFID7; /* RFID7 */
+ union iodefine_reg32_t RFPTR7; /* RFPTR7 */
+ union iodefine_reg32_t RFDF07; /* RFDF07 */
+ union iodefine_reg32_t RFDF17; /* RFDF17 */
+/* end of struct st_rscan_from_rscan0rfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID0; /* CFID0 */
+ union iodefine_reg32_t CFPTR0; /* CFPTR0 */
+ union iodefine_reg32_t CFDF00; /* CFDF00 */
+ union iodefine_reg32_t CFDF10; /* CFDF10 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID1; /* CFID1 */
+ union iodefine_reg32_t CFPTR1; /* CFPTR1 */
+ union iodefine_reg32_t CFDF01; /* CFDF01 */
+ union iodefine_reg32_t CFDF11; /* CFDF11 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID2; /* CFID2 */
+ union iodefine_reg32_t CFPTR2; /* CFPTR2 */
+ union iodefine_reg32_t CFDF02; /* CFDF02 */
+ union iodefine_reg32_t CFDF12; /* CFDF12 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID3; /* CFID3 */
+ union iodefine_reg32_t CFPTR3; /* CFPTR3 */
+ union iodefine_reg32_t CFDF03; /* CFDF03 */
+ union iodefine_reg32_t CFDF13; /* CFDF13 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID4; /* CFID4 */
+ union iodefine_reg32_t CFPTR4; /* CFPTR4 */
+ union iodefine_reg32_t CFDF04; /* CFDF04 */
+ union iodefine_reg32_t CFDF14; /* CFDF14 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID5; /* CFID5 */
+ union iodefine_reg32_t CFPTR5; /* CFPTR5 */
+ union iodefine_reg32_t CFDF05; /* CFDF05 */
+ union iodefine_reg32_t CFDF15; /* CFDF15 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID6; /* CFID6 */
+ union iodefine_reg32_t CFPTR6; /* CFPTR6 */
+ union iodefine_reg32_t CFDF06; /* CFDF06 */
+ union iodefine_reg32_t CFDF16; /* CFDF16 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID7; /* CFID7 */
+ union iodefine_reg32_t CFPTR7; /* CFPTR7 */
+ union iodefine_reg32_t CFDF07; /* CFDF07 */
+ union iodefine_reg32_t CFDF17; /* CFDF17 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID8; /* CFID8 */
+ union iodefine_reg32_t CFPTR8; /* CFPTR8 */
+ union iodefine_reg32_t CFDF08; /* CFDF08 */
+ union iodefine_reg32_t CFDF18; /* CFDF18 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID9; /* CFID9 */
+ union iodefine_reg32_t CFPTR9; /* CFPTR9 */
+ union iodefine_reg32_t CFDF09; /* CFDF09 */
+ union iodefine_reg32_t CFDF19; /* CFDF19 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID10; /* CFID10 */
+ union iodefine_reg32_t CFPTR10; /* CFPTR10 */
+ union iodefine_reg32_t CFDF010; /* CFDF010 */
+ union iodefine_reg32_t CFDF110; /* CFDF110 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID11; /* CFID11 */
+ union iodefine_reg32_t CFPTR11; /* CFPTR11 */
+ union iodefine_reg32_t CFDF011; /* CFDF011 */
+ union iodefine_reg32_t CFDF111; /* CFDF111 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID12; /* CFID12 */
+ union iodefine_reg32_t CFPTR12; /* CFPTR12 */
+ union iodefine_reg32_t CFDF012; /* CFDF012 */
+ union iodefine_reg32_t CFDF112; /* CFDF112 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID13; /* CFID13 */
+ union iodefine_reg32_t CFPTR13; /* CFPTR13 */
+ union iodefine_reg32_t CFDF013; /* CFDF013 */
+ union iodefine_reg32_t CFDF113; /* CFDF113 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+/* start of struct st_rscan_from_rscan0cfidm */
+ union iodefine_reg32_t CFID14; /* CFID14 */
+ union iodefine_reg32_t CFPTR14; /* CFPTR14 */
+ union iodefine_reg32_t CFDF014; /* CFDF014 */
+ union iodefine_reg32_t CFDF114; /* CFDF114 */
+/* end of struct st_rscan_from_rscan0cfidm */
+
+ volatile uint8_t dummy180[144]; /* */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID0; /* TMID0 */
+ union iodefine_reg32_t TMPTR0; /* TMPTR0 */
+ union iodefine_reg32_t TMDF00; /* TMDF00 */
+ union iodefine_reg32_t TMDF10; /* TMDF10 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID1; /* TMID1 */
+ union iodefine_reg32_t TMPTR1; /* TMPTR1 */
+ union iodefine_reg32_t TMDF01; /* TMDF01 */
+ union iodefine_reg32_t TMDF11; /* TMDF11 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID2; /* TMID2 */
+ union iodefine_reg32_t TMPTR2; /* TMPTR2 */
+ union iodefine_reg32_t TMDF02; /* TMDF02 */
+ union iodefine_reg32_t TMDF12; /* TMDF12 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID3; /* TMID3 */
+ union iodefine_reg32_t TMPTR3; /* TMPTR3 */
+ union iodefine_reg32_t TMDF03; /* TMDF03 */
+ union iodefine_reg32_t TMDF13; /* TMDF13 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID4; /* TMID4 */
+ union iodefine_reg32_t TMPTR4; /* TMPTR4 */
+ union iodefine_reg32_t TMDF04; /* TMDF04 */
+ union iodefine_reg32_t TMDF14; /* TMDF14 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID5; /* TMID5 */
+ union iodefine_reg32_t TMPTR5; /* TMPTR5 */
+ union iodefine_reg32_t TMDF05; /* TMDF05 */
+ union iodefine_reg32_t TMDF15; /* TMDF15 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID6; /* TMID6 */
+ union iodefine_reg32_t TMPTR6; /* TMPTR6 */
+ union iodefine_reg32_t TMDF06; /* TMDF06 */
+ union iodefine_reg32_t TMDF16; /* TMDF16 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID7; /* TMID7 */
+ union iodefine_reg32_t TMPTR7; /* TMPTR7 */
+ union iodefine_reg32_t TMDF07; /* TMDF07 */
+ union iodefine_reg32_t TMDF17; /* TMDF17 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID8; /* TMID8 */
+ union iodefine_reg32_t TMPTR8; /* TMPTR8 */
+ union iodefine_reg32_t TMDF08; /* TMDF08 */
+ union iodefine_reg32_t TMDF18; /* TMDF18 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID9; /* TMID9 */
+ union iodefine_reg32_t TMPTR9; /* TMPTR9 */
+ union iodefine_reg32_t TMDF09; /* TMDF09 */
+ union iodefine_reg32_t TMDF19; /* TMDF19 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID10; /* TMID10 */
+ union iodefine_reg32_t TMPTR10; /* TMPTR10 */
+ union iodefine_reg32_t TMDF010; /* TMDF010 */
+ union iodefine_reg32_t TMDF110; /* TMDF110 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID11; /* TMID11 */
+ union iodefine_reg32_t TMPTR11; /* TMPTR11 */
+ union iodefine_reg32_t TMDF011; /* TMDF011 */
+ union iodefine_reg32_t TMDF111; /* TMDF111 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID12; /* TMID12 */
+ union iodefine_reg32_t TMPTR12; /* TMPTR12 */
+ union iodefine_reg32_t TMDF012; /* TMDF012 */
+ union iodefine_reg32_t TMDF112; /* TMDF112 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID13; /* TMID13 */
+ union iodefine_reg32_t TMPTR13; /* TMPTR13 */
+ union iodefine_reg32_t TMDF013; /* TMDF013 */
+ union iodefine_reg32_t TMDF113; /* TMDF113 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID14; /* TMID14 */
+ union iodefine_reg32_t TMPTR14; /* TMPTR14 */
+ union iodefine_reg32_t TMDF014; /* TMDF014 */
+ union iodefine_reg32_t TMDF114; /* TMDF114 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID15; /* TMID15 */
+ union iodefine_reg32_t TMPTR15; /* TMPTR15 */
+ union iodefine_reg32_t TMDF015; /* TMDF015 */
+ union iodefine_reg32_t TMDF115; /* TMDF115 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID16; /* TMID16 */
+ union iodefine_reg32_t TMPTR16; /* TMPTR16 */
+ union iodefine_reg32_t TMDF016; /* TMDF016 */
+ union iodefine_reg32_t TMDF116; /* TMDF116 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID17; /* TMID17 */
+ union iodefine_reg32_t TMPTR17; /* TMPTR17 */
+ union iodefine_reg32_t TMDF017; /* TMDF017 */
+ union iodefine_reg32_t TMDF117; /* TMDF117 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID18; /* TMID18 */
+ union iodefine_reg32_t TMPTR18; /* TMPTR18 */
+ union iodefine_reg32_t TMDF018; /* TMDF018 */
+ union iodefine_reg32_t TMDF118; /* TMDF118 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID19; /* TMID19 */
+ union iodefine_reg32_t TMPTR19; /* TMPTR19 */
+ union iodefine_reg32_t TMDF019; /* TMDF019 */
+ union iodefine_reg32_t TMDF119; /* TMDF119 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID20; /* TMID20 */
+ union iodefine_reg32_t TMPTR20; /* TMPTR20 */
+ union iodefine_reg32_t TMDF020; /* TMDF020 */
+ union iodefine_reg32_t TMDF120; /* TMDF120 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID21; /* TMID21 */
+ union iodefine_reg32_t TMPTR21; /* TMPTR21 */
+ union iodefine_reg32_t TMDF021; /* TMDF021 */
+ union iodefine_reg32_t TMDF121; /* TMDF121 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID22; /* TMID22 */
+ union iodefine_reg32_t TMPTR22; /* TMPTR22 */
+ union iodefine_reg32_t TMDF022; /* TMDF022 */
+ union iodefine_reg32_t TMDF122; /* TMDF122 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID23; /* TMID23 */
+ union iodefine_reg32_t TMPTR23; /* TMPTR23 */
+ union iodefine_reg32_t TMDF023; /* TMDF023 */
+ union iodefine_reg32_t TMDF123; /* TMDF123 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID24; /* TMID24 */
+ union iodefine_reg32_t TMPTR24; /* TMPTR24 */
+ union iodefine_reg32_t TMDF024; /* TMDF024 */
+ union iodefine_reg32_t TMDF124; /* TMDF124 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID25; /* TMID25 */
+ union iodefine_reg32_t TMPTR25; /* TMPTR25 */
+ union iodefine_reg32_t TMDF025; /* TMDF025 */
+ union iodefine_reg32_t TMDF125; /* TMDF125 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID26; /* TMID26 */
+ union iodefine_reg32_t TMPTR26; /* TMPTR26 */
+ union iodefine_reg32_t TMDF026; /* TMDF026 */
+ union iodefine_reg32_t TMDF126; /* TMDF126 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID27; /* TMID27 */
+ union iodefine_reg32_t TMPTR27; /* TMPTR27 */
+ union iodefine_reg32_t TMDF027; /* TMDF027 */
+ union iodefine_reg32_t TMDF127; /* TMDF127 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID28; /* TMID28 */
+ union iodefine_reg32_t TMPTR28; /* TMPTR28 */
+ union iodefine_reg32_t TMDF028; /* TMDF028 */
+ union iodefine_reg32_t TMDF128; /* TMDF128 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID29; /* TMID29 */
+ union iodefine_reg32_t TMPTR29; /* TMPTR29 */
+ union iodefine_reg32_t TMDF029; /* TMDF029 */
+ union iodefine_reg32_t TMDF129; /* TMDF129 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID30; /* TMID30 */
+ union iodefine_reg32_t TMPTR30; /* TMPTR30 */
+ union iodefine_reg32_t TMDF030; /* TMDF030 */
+ union iodefine_reg32_t TMDF130; /* TMDF130 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID31; /* TMID31 */
+ union iodefine_reg32_t TMPTR31; /* TMPTR31 */
+ union iodefine_reg32_t TMDF031; /* TMDF031 */
+ union iodefine_reg32_t TMDF131; /* TMDF131 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID32; /* TMID32 */
+ union iodefine_reg32_t TMPTR32; /* TMPTR32 */
+ union iodefine_reg32_t TMDF032; /* TMDF032 */
+ union iodefine_reg32_t TMDF132; /* TMDF132 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID33; /* TMID33 */
+ union iodefine_reg32_t TMPTR33; /* TMPTR33 */
+ union iodefine_reg32_t TMDF033; /* TMDF033 */
+ union iodefine_reg32_t TMDF133; /* TMDF133 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID34; /* TMID34 */
+ union iodefine_reg32_t TMPTR34; /* TMPTR34 */
+ union iodefine_reg32_t TMDF034; /* TMDF034 */
+ union iodefine_reg32_t TMDF134; /* TMDF134 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID35; /* TMID35 */
+ union iodefine_reg32_t TMPTR35; /* TMPTR35 */
+ union iodefine_reg32_t TMDF035; /* TMDF035 */
+ union iodefine_reg32_t TMDF135; /* TMDF135 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID36; /* TMID36 */
+ union iodefine_reg32_t TMPTR36; /* TMPTR36 */
+ union iodefine_reg32_t TMDF036; /* TMDF036 */
+ union iodefine_reg32_t TMDF136; /* TMDF136 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID37; /* TMID37 */
+ union iodefine_reg32_t TMPTR37; /* TMPTR37 */
+ union iodefine_reg32_t TMDF037; /* TMDF037 */
+ union iodefine_reg32_t TMDF137; /* TMDF137 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID38; /* TMID38 */
+ union iodefine_reg32_t TMPTR38; /* TMPTR38 */
+ union iodefine_reg32_t TMDF038; /* TMDF038 */
+ union iodefine_reg32_t TMDF138; /* TMDF138 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID39; /* TMID39 */
+ union iodefine_reg32_t TMPTR39; /* TMPTR39 */
+ union iodefine_reg32_t TMDF039; /* TMDF039 */
+ union iodefine_reg32_t TMDF139; /* TMDF139 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID40; /* TMID40 */
+ union iodefine_reg32_t TMPTR40; /* TMPTR40 */
+ union iodefine_reg32_t TMDF040; /* TMDF040 */
+ union iodefine_reg32_t TMDF140; /* TMDF140 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID41; /* TMID41 */
+ union iodefine_reg32_t TMPTR41; /* TMPTR41 */
+ union iodefine_reg32_t TMDF041; /* TMDF041 */
+ union iodefine_reg32_t TMDF141; /* TMDF141 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID42; /* TMID42 */
+ union iodefine_reg32_t TMPTR42; /* TMPTR42 */
+ union iodefine_reg32_t TMDF042; /* TMDF042 */
+ union iodefine_reg32_t TMDF142; /* TMDF142 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID43; /* TMID43 */
+ union iodefine_reg32_t TMPTR43; /* TMPTR43 */
+ union iodefine_reg32_t TMDF043; /* TMDF043 */
+ union iodefine_reg32_t TMDF143; /* TMDF143 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID44; /* TMID44 */
+ union iodefine_reg32_t TMPTR44; /* TMPTR44 */
+ union iodefine_reg32_t TMDF044; /* TMDF044 */
+ union iodefine_reg32_t TMDF144; /* TMDF144 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID45; /* TMID45 */
+ union iodefine_reg32_t TMPTR45; /* TMPTR45 */
+ union iodefine_reg32_t TMDF045; /* TMDF045 */
+ union iodefine_reg32_t TMDF145; /* TMDF145 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID46; /* TMID46 */
+ union iodefine_reg32_t TMPTR46; /* TMPTR46 */
+ union iodefine_reg32_t TMDF046; /* TMDF046 */
+ union iodefine_reg32_t TMDF146; /* TMDF146 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID47; /* TMID47 */
+ union iodefine_reg32_t TMPTR47; /* TMPTR47 */
+ union iodefine_reg32_t TMDF047; /* TMDF047 */
+ union iodefine_reg32_t TMDF147; /* TMDF147 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID48; /* TMID48 */
+ union iodefine_reg32_t TMPTR48; /* TMPTR48 */
+ union iodefine_reg32_t TMDF048; /* TMDF048 */
+ union iodefine_reg32_t TMDF148; /* TMDF148 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID49; /* TMID49 */
+ union iodefine_reg32_t TMPTR49; /* TMPTR49 */
+ union iodefine_reg32_t TMDF049; /* TMDF049 */
+ union iodefine_reg32_t TMDF149; /* TMDF149 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID50; /* TMID50 */
+ union iodefine_reg32_t TMPTR50; /* TMPTR50 */
+ union iodefine_reg32_t TMDF050; /* TMDF050 */
+ union iodefine_reg32_t TMDF150; /* TMDF150 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID51; /* TMID51 */
+ union iodefine_reg32_t TMPTR51; /* TMPTR51 */
+ union iodefine_reg32_t TMDF051; /* TMDF051 */
+ union iodefine_reg32_t TMDF151; /* TMDF151 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID52; /* TMID52 */
+ union iodefine_reg32_t TMPTR52; /* TMPTR52 */
+ union iodefine_reg32_t TMDF052; /* TMDF052 */
+ union iodefine_reg32_t TMDF152; /* TMDF152 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID53; /* TMID53 */
+ union iodefine_reg32_t TMPTR53; /* TMPTR53 */
+ union iodefine_reg32_t TMDF053; /* TMDF053 */
+ union iodefine_reg32_t TMDF153; /* TMDF153 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID54; /* TMID54 */
+ union iodefine_reg32_t TMPTR54; /* TMPTR54 */
+ union iodefine_reg32_t TMDF054; /* TMDF054 */
+ union iodefine_reg32_t TMDF154; /* TMDF154 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID55; /* TMID55 */
+ union iodefine_reg32_t TMPTR55; /* TMPTR55 */
+ union iodefine_reg32_t TMDF055; /* TMDF055 */
+ union iodefine_reg32_t TMDF155; /* TMDF155 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID56; /* TMID56 */
+ union iodefine_reg32_t TMPTR56; /* TMPTR56 */
+ union iodefine_reg32_t TMDF056; /* TMDF056 */
+ union iodefine_reg32_t TMDF156; /* TMDF156 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID57; /* TMID57 */
+ union iodefine_reg32_t TMPTR57; /* TMPTR57 */
+ union iodefine_reg32_t TMDF057; /* TMDF057 */
+ union iodefine_reg32_t TMDF157; /* TMDF157 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID58; /* TMID58 */
+ union iodefine_reg32_t TMPTR58; /* TMPTR58 */
+ union iodefine_reg32_t TMDF058; /* TMDF058 */
+ union iodefine_reg32_t TMDF158; /* TMDF158 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID59; /* TMID59 */
+ union iodefine_reg32_t TMPTR59; /* TMPTR59 */
+ union iodefine_reg32_t TMDF059; /* TMDF059 */
+ union iodefine_reg32_t TMDF159; /* TMDF159 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID60; /* TMID60 */
+ union iodefine_reg32_t TMPTR60; /* TMPTR60 */
+ union iodefine_reg32_t TMDF060; /* TMDF060 */
+ union iodefine_reg32_t TMDF160; /* TMDF160 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID61; /* TMID61 */
+ union iodefine_reg32_t TMPTR61; /* TMPTR61 */
+ union iodefine_reg32_t TMDF061; /* TMDF061 */
+ union iodefine_reg32_t TMDF161; /* TMDF161 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID62; /* TMID62 */
+ union iodefine_reg32_t TMPTR62; /* TMPTR62 */
+ union iodefine_reg32_t TMDF062; /* TMDF062 */
+ union iodefine_reg32_t TMDF162; /* TMDF162 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID63; /* TMID63 */
+ union iodefine_reg32_t TMPTR63; /* TMPTR63 */
+ union iodefine_reg32_t TMDF063; /* TMDF063 */
+ union iodefine_reg32_t TMDF163; /* TMDF163 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID64; /* TMID64 */
+ union iodefine_reg32_t TMPTR64; /* TMPTR64 */
+ union iodefine_reg32_t TMDF064; /* TMDF064 */
+ union iodefine_reg32_t TMDF164; /* TMDF164 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID65; /* TMID65 */
+ union iodefine_reg32_t TMPTR65; /* TMPTR65 */
+ union iodefine_reg32_t TMDF065; /* TMDF065 */
+ union iodefine_reg32_t TMDF165; /* TMDF165 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID66; /* TMID66 */
+ union iodefine_reg32_t TMPTR66; /* TMPTR66 */
+ union iodefine_reg32_t TMDF066; /* TMDF066 */
+ union iodefine_reg32_t TMDF166; /* TMDF166 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID67; /* TMID67 */
+ union iodefine_reg32_t TMPTR67; /* TMPTR67 */
+ union iodefine_reg32_t TMDF067; /* TMDF067 */
+ union iodefine_reg32_t TMDF167; /* TMDF167 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID68; /* TMID68 */
+ union iodefine_reg32_t TMPTR68; /* TMPTR68 */
+ union iodefine_reg32_t TMDF068; /* TMDF068 */
+ union iodefine_reg32_t TMDF168; /* TMDF168 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID69; /* TMID69 */
+ union iodefine_reg32_t TMPTR69; /* TMPTR69 */
+ union iodefine_reg32_t TMDF069; /* TMDF069 */
+ union iodefine_reg32_t TMDF169; /* TMDF169 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID70; /* TMID70 */
+ union iodefine_reg32_t TMPTR70; /* TMPTR70 */
+ union iodefine_reg32_t TMDF070; /* TMDF070 */
+ union iodefine_reg32_t TMDF170; /* TMDF170 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID71; /* TMID71 */
+ union iodefine_reg32_t TMPTR71; /* TMPTR71 */
+ union iodefine_reg32_t TMDF071; /* TMDF071 */
+ union iodefine_reg32_t TMDF171; /* TMDF171 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID72; /* TMID72 */
+ union iodefine_reg32_t TMPTR72; /* TMPTR72 */
+ union iodefine_reg32_t TMDF072; /* TMDF072 */
+ union iodefine_reg32_t TMDF172; /* TMDF172 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID73; /* TMID73 */
+ union iodefine_reg32_t TMPTR73; /* TMPTR73 */
+ union iodefine_reg32_t TMDF073; /* TMDF073 */
+ union iodefine_reg32_t TMDF173; /* TMDF173 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID74; /* TMID74 */
+ union iodefine_reg32_t TMPTR74; /* TMPTR74 */
+ union iodefine_reg32_t TMDF074; /* TMDF074 */
+ union iodefine_reg32_t TMDF174; /* TMDF174 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID75; /* TMID75 */
+ union iodefine_reg32_t TMPTR75; /* TMPTR75 */
+ union iodefine_reg32_t TMDF075; /* TMDF075 */
+ union iodefine_reg32_t TMDF175; /* TMDF175 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID76; /* TMID76 */
+ union iodefine_reg32_t TMPTR76; /* TMPTR76 */
+ union iodefine_reg32_t TMDF076; /* TMDF076 */
+ union iodefine_reg32_t TMDF176; /* TMDF176 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID77; /* TMID77 */
+ union iodefine_reg32_t TMPTR77; /* TMPTR77 */
+ union iodefine_reg32_t TMDF077; /* TMDF077 */
+ union iodefine_reg32_t TMDF177; /* TMDF177 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID78; /* TMID78 */
+ union iodefine_reg32_t TMPTR78; /* TMPTR78 */
+ union iodefine_reg32_t TMDF078; /* TMDF078 */
+ union iodefine_reg32_t TMDF178; /* TMDF178 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+/* start of struct st_rscan_from_rscan0tmidp */
+ union iodefine_reg32_t TMID79; /* TMID79 */
+ union iodefine_reg32_t TMPTR79; /* TMPTR79 */
+ union iodefine_reg32_t TMDF079; /* TMDF079 */
+ union iodefine_reg32_t TMDF179; /* TMDF179 */
+/* end of struct st_rscan_from_rscan0tmidp */
+
+ volatile uint8_t dummy181[768]; /* */
+#define RSCAN0_THLACC0_COUNT 5
+ union iodefine_reg32_t THLACC0; /* THLACC0 */
+ union iodefine_reg32_t THLACC1; /* THLACC1 */
+ union iodefine_reg32_t THLACC2; /* THLACC2 */
+ union iodefine_reg32_t THLACC3; /* THLACC3 */
+ union iodefine_reg32_t THLACC4; /* THLACC4 */
+
+};
+
+
+struct st_rscan_from_rscan0cncfg
+{
+ union iodefine_reg32_t CnCFG; /* CnCFG */
+ union iodefine_reg32_t CnCTR; /* CnCTR */
+ union iodefine_reg32_t CnSTS; /* CnSTS */
+ union iodefine_reg32_t CnERFL; /* CnERFL */
+};
+
+
+struct st_rscan_from_rscan0gaflidj
+{
+ union iodefine_reg32_t GAFLIDj; /* GAFLIDj */
+ union iodefine_reg32_t GAFLMj; /* GAFLMj */
+ union iodefine_reg32_t GAFLP0j; /* GAFLP0j */
+ union iodefine_reg32_t GAFLP1j; /* GAFLP1j */
+};
+
+
+struct st_rscan_from_rscan0rmidp
+{
+ union iodefine_reg32_t RMIDp; /* RMIDp */
+ union iodefine_reg32_t RMPTRp; /* RMPTRp */
+ union iodefine_reg32_t RMDF0p; /* RMDF0p */
+ union iodefine_reg32_t RMDF1p; /* RMDF1p */
+};
+
+
+struct st_rscan_from_rscan0rfidm
+{
+ union iodefine_reg32_t RFIDm; /* RFIDm */
+ union iodefine_reg32_t RFPTRm; /* RFPTRm */
+ union iodefine_reg32_t RFDF0m; /* RFDF0m */
+ union iodefine_reg32_t RFDF1m; /* RFDF1m */
+};
+
+
+struct st_rscan_from_rscan0tmidp
+{
+ union iodefine_reg32_t TMIDp; /* TMIDp */
+ union iodefine_reg32_t TMPTRp; /* TMPTRp */
+ union iodefine_reg32_t TMDF0p; /* TMDF0p */
+ union iodefine_reg32_t TMDF1p; /* TMDF1p */
+};
+
+
+struct st_rscan_from_rscan0cfidm
+{
+ union iodefine_reg32_t CFIDm; /* CFIDm */
+ union iodefine_reg32_t CFPTRm; /* CFPTRm */
+ union iodefine_reg32_t CFDF0m; /* CFDF0m */
+ union iodefine_reg32_t CFDF1m; /* CFDF1m */
+};
+
+
+#define RSCAN0 (*(struct st_rscan0 *)0xE803A000uL) /* RSCAN0 */
+
+
+/* Start of channnel array defines of RSCAN0 */
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0CFIDm */
+/*(Sample) value = RSCAN_FROM_RSCAN0CFIDm[ channel ]->CFIDm.UINT32; */
+#define RSCAN_FROM_RSCAN0CFIDm_COUNT 15
+#define RSCAN_FROM_RSCAN0CFIDm_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \
+ &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0CFID0 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID0) /* RSCAN_FROM_RSCAN0CFID0 */
+#define RSCAN_FROM_RSCAN0CFID1 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID1) /* RSCAN_FROM_RSCAN0CFID1 */
+#define RSCAN_FROM_RSCAN0CFID2 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID2) /* RSCAN_FROM_RSCAN0CFID2 */
+#define RSCAN_FROM_RSCAN0CFID3 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID3) /* RSCAN_FROM_RSCAN0CFID3 */
+#define RSCAN_FROM_RSCAN0CFID4 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID4) /* RSCAN_FROM_RSCAN0CFID4 */
+#define RSCAN_FROM_RSCAN0CFID5 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID5) /* RSCAN_FROM_RSCAN0CFID5 */
+#define RSCAN_FROM_RSCAN0CFID6 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID6) /* RSCAN_FROM_RSCAN0CFID6 */
+#define RSCAN_FROM_RSCAN0CFID7 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID7) /* RSCAN_FROM_RSCAN0CFID7 */
+#define RSCAN_FROM_RSCAN0CFID8 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID8) /* RSCAN_FROM_RSCAN0CFID8 */
+#define RSCAN_FROM_RSCAN0CFID9 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID9) /* RSCAN_FROM_RSCAN0CFID9 */
+#define RSCAN_FROM_RSCAN0CFID10 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID10) /* RSCAN_FROM_RSCAN0CFID10 */
+#define RSCAN_FROM_RSCAN0CFID11 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID11) /* RSCAN_FROM_RSCAN0CFID11 */
+#define RSCAN_FROM_RSCAN0CFID12 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID12) /* RSCAN_FROM_RSCAN0CFID12 */
+#define RSCAN_FROM_RSCAN0CFID13 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID13) /* RSCAN_FROM_RSCAN0CFID13 */
+#define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0TMIDp */
+/*(Sample) value = RSCAN_FROM_RSCAN0TMIDp[ channel ]->TMIDp.UINT32; */
+#define RSCAN_FROM_RSCAN0TMIDp_COUNT 80
+#define RSCAN_FROM_RSCAN0TMIDp_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \
+ &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \
+ &RSCAN_FROM_RSCAN0TMID16, &RSCAN_FROM_RSCAN0TMID17, &RSCAN_FROM_RSCAN0TMID18, &RSCAN_FROM_RSCAN0TMID19, &RSCAN_FROM_RSCAN0TMID20, &RSCAN_FROM_RSCAN0TMID21, &RSCAN_FROM_RSCAN0TMID22, &RSCAN_FROM_RSCAN0TMID23, \
+ &RSCAN_FROM_RSCAN0TMID24, &RSCAN_FROM_RSCAN0TMID25, &RSCAN_FROM_RSCAN0TMID26, &RSCAN_FROM_RSCAN0TMID27, &RSCAN_FROM_RSCAN0TMID28, &RSCAN_FROM_RSCAN0TMID29, &RSCAN_FROM_RSCAN0TMID30, &RSCAN_FROM_RSCAN0TMID31, \
+ &RSCAN_FROM_RSCAN0TMID32, &RSCAN_FROM_RSCAN0TMID33, &RSCAN_FROM_RSCAN0TMID34, &RSCAN_FROM_RSCAN0TMID35, &RSCAN_FROM_RSCAN0TMID36, &RSCAN_FROM_RSCAN0TMID37, &RSCAN_FROM_RSCAN0TMID38, &RSCAN_FROM_RSCAN0TMID39, \
+ &RSCAN_FROM_RSCAN0TMID40, &RSCAN_FROM_RSCAN0TMID41, &RSCAN_FROM_RSCAN0TMID42, &RSCAN_FROM_RSCAN0TMID43, &RSCAN_FROM_RSCAN0TMID44, &RSCAN_FROM_RSCAN0TMID45, &RSCAN_FROM_RSCAN0TMID46, &RSCAN_FROM_RSCAN0TMID47, \
+ &RSCAN_FROM_RSCAN0TMID48, &RSCAN_FROM_RSCAN0TMID49, &RSCAN_FROM_RSCAN0TMID50, &RSCAN_FROM_RSCAN0TMID51, &RSCAN_FROM_RSCAN0TMID52, &RSCAN_FROM_RSCAN0TMID53, &RSCAN_FROM_RSCAN0TMID54, &RSCAN_FROM_RSCAN0TMID55, \
+ &RSCAN_FROM_RSCAN0TMID56, &RSCAN_FROM_RSCAN0TMID57, &RSCAN_FROM_RSCAN0TMID58, &RSCAN_FROM_RSCAN0TMID59, &RSCAN_FROM_RSCAN0TMID60, &RSCAN_FROM_RSCAN0TMID61, &RSCAN_FROM_RSCAN0TMID62, &RSCAN_FROM_RSCAN0TMID63, \
+ &RSCAN_FROM_RSCAN0TMID64, &RSCAN_FROM_RSCAN0TMID65, &RSCAN_FROM_RSCAN0TMID66, &RSCAN_FROM_RSCAN0TMID67, &RSCAN_FROM_RSCAN0TMID68, &RSCAN_FROM_RSCAN0TMID69, &RSCAN_FROM_RSCAN0TMID70, &RSCAN_FROM_RSCAN0TMID71, \
+ &RSCAN_FROM_RSCAN0TMID72, &RSCAN_FROM_RSCAN0TMID73, &RSCAN_FROM_RSCAN0TMID74, &RSCAN_FROM_RSCAN0TMID75, &RSCAN_FROM_RSCAN0TMID76, &RSCAN_FROM_RSCAN0TMID77, &RSCAN_FROM_RSCAN0TMID78, &RSCAN_FROM_RSCAN0TMID79 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0TMID0 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID0) /* RSCAN_FROM_RSCAN0TMID0 */
+#define RSCAN_FROM_RSCAN0TMID1 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID1) /* RSCAN_FROM_RSCAN0TMID1 */
+#define RSCAN_FROM_RSCAN0TMID2 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID2) /* RSCAN_FROM_RSCAN0TMID2 */
+#define RSCAN_FROM_RSCAN0TMID3 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID3) /* RSCAN_FROM_RSCAN0TMID3 */
+#define RSCAN_FROM_RSCAN0TMID4 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID4) /* RSCAN_FROM_RSCAN0TMID4 */
+#define RSCAN_FROM_RSCAN0TMID5 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID5) /* RSCAN_FROM_RSCAN0TMID5 */
+#define RSCAN_FROM_RSCAN0TMID6 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID6) /* RSCAN_FROM_RSCAN0TMID6 */
+#define RSCAN_FROM_RSCAN0TMID7 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID7) /* RSCAN_FROM_RSCAN0TMID7 */
+#define RSCAN_FROM_RSCAN0TMID8 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID8) /* RSCAN_FROM_RSCAN0TMID8 */
+#define RSCAN_FROM_RSCAN0TMID9 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID9) /* RSCAN_FROM_RSCAN0TMID9 */
+#define RSCAN_FROM_RSCAN0TMID10 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID10) /* RSCAN_FROM_RSCAN0TMID10 */
+#define RSCAN_FROM_RSCAN0TMID11 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID11) /* RSCAN_FROM_RSCAN0TMID11 */
+#define RSCAN_FROM_RSCAN0TMID12 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID12) /* RSCAN_FROM_RSCAN0TMID12 */
+#define RSCAN_FROM_RSCAN0TMID13 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID13) /* RSCAN_FROM_RSCAN0TMID13 */
+#define RSCAN_FROM_RSCAN0TMID14 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID14) /* RSCAN_FROM_RSCAN0TMID14 */
+#define RSCAN_FROM_RSCAN0TMID15 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID15) /* RSCAN_FROM_RSCAN0TMID15 */
+#define RSCAN_FROM_RSCAN0TMID16 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID16) /* RSCAN_FROM_RSCAN0TMID16 */
+#define RSCAN_FROM_RSCAN0TMID17 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID17) /* RSCAN_FROM_RSCAN0TMID17 */
+#define RSCAN_FROM_RSCAN0TMID18 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID18) /* RSCAN_FROM_RSCAN0TMID18 */
+#define RSCAN_FROM_RSCAN0TMID19 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID19) /* RSCAN_FROM_RSCAN0TMID19 */
+#define RSCAN_FROM_RSCAN0TMID20 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID20) /* RSCAN_FROM_RSCAN0TMID20 */
+#define RSCAN_FROM_RSCAN0TMID21 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID21) /* RSCAN_FROM_RSCAN0TMID21 */
+#define RSCAN_FROM_RSCAN0TMID22 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID22) /* RSCAN_FROM_RSCAN0TMID22 */
+#define RSCAN_FROM_RSCAN0TMID23 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID23) /* RSCAN_FROM_RSCAN0TMID23 */
+#define RSCAN_FROM_RSCAN0TMID24 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID24) /* RSCAN_FROM_RSCAN0TMID24 */
+#define RSCAN_FROM_RSCAN0TMID25 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID25) /* RSCAN_FROM_RSCAN0TMID25 */
+#define RSCAN_FROM_RSCAN0TMID26 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID26) /* RSCAN_FROM_RSCAN0TMID26 */
+#define RSCAN_FROM_RSCAN0TMID27 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID27) /* RSCAN_FROM_RSCAN0TMID27 */
+#define RSCAN_FROM_RSCAN0TMID28 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID28) /* RSCAN_FROM_RSCAN0TMID28 */
+#define RSCAN_FROM_RSCAN0TMID29 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID29) /* RSCAN_FROM_RSCAN0TMID29 */
+#define RSCAN_FROM_RSCAN0TMID30 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID30) /* RSCAN_FROM_RSCAN0TMID30 */
+#define RSCAN_FROM_RSCAN0TMID31 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID31) /* RSCAN_FROM_RSCAN0TMID31 */
+#define RSCAN_FROM_RSCAN0TMID32 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID32) /* RSCAN_FROM_RSCAN0TMID32 */
+#define RSCAN_FROM_RSCAN0TMID33 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID33) /* RSCAN_FROM_RSCAN0TMID33 */
+#define RSCAN_FROM_RSCAN0TMID34 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID34) /* RSCAN_FROM_RSCAN0TMID34 */
+#define RSCAN_FROM_RSCAN0TMID35 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID35) /* RSCAN_FROM_RSCAN0TMID35 */
+#define RSCAN_FROM_RSCAN0TMID36 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID36) /* RSCAN_FROM_RSCAN0TMID36 */
+#define RSCAN_FROM_RSCAN0TMID37 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID37) /* RSCAN_FROM_RSCAN0TMID37 */
+#define RSCAN_FROM_RSCAN0TMID38 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID38) /* RSCAN_FROM_RSCAN0TMID38 */
+#define RSCAN_FROM_RSCAN0TMID39 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID39) /* RSCAN_FROM_RSCAN0TMID39 */
+#define RSCAN_FROM_RSCAN0TMID40 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID40) /* RSCAN_FROM_RSCAN0TMID40 */
+#define RSCAN_FROM_RSCAN0TMID41 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID41) /* RSCAN_FROM_RSCAN0TMID41 */
+#define RSCAN_FROM_RSCAN0TMID42 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID42) /* RSCAN_FROM_RSCAN0TMID42 */
+#define RSCAN_FROM_RSCAN0TMID43 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID43) /* RSCAN_FROM_RSCAN0TMID43 */
+#define RSCAN_FROM_RSCAN0TMID44 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID44) /* RSCAN_FROM_RSCAN0TMID44 */
+#define RSCAN_FROM_RSCAN0TMID45 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID45) /* RSCAN_FROM_RSCAN0TMID45 */
+#define RSCAN_FROM_RSCAN0TMID46 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID46) /* RSCAN_FROM_RSCAN0TMID46 */
+#define RSCAN_FROM_RSCAN0TMID47 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID47) /* RSCAN_FROM_RSCAN0TMID47 */
+#define RSCAN_FROM_RSCAN0TMID48 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID48) /* RSCAN_FROM_RSCAN0TMID48 */
+#define RSCAN_FROM_RSCAN0TMID49 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID49) /* RSCAN_FROM_RSCAN0TMID49 */
+#define RSCAN_FROM_RSCAN0TMID50 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID50) /* RSCAN_FROM_RSCAN0TMID50 */
+#define RSCAN_FROM_RSCAN0TMID51 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID51) /* RSCAN_FROM_RSCAN0TMID51 */
+#define RSCAN_FROM_RSCAN0TMID52 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID52) /* RSCAN_FROM_RSCAN0TMID52 */
+#define RSCAN_FROM_RSCAN0TMID53 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID53) /* RSCAN_FROM_RSCAN0TMID53 */
+#define RSCAN_FROM_RSCAN0TMID54 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID54) /* RSCAN_FROM_RSCAN0TMID54 */
+#define RSCAN_FROM_RSCAN0TMID55 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID55) /* RSCAN_FROM_RSCAN0TMID55 */
+#define RSCAN_FROM_RSCAN0TMID56 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID56) /* RSCAN_FROM_RSCAN0TMID56 */
+#define RSCAN_FROM_RSCAN0TMID57 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID57) /* RSCAN_FROM_RSCAN0TMID57 */
+#define RSCAN_FROM_RSCAN0TMID58 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID58) /* RSCAN_FROM_RSCAN0TMID58 */
+#define RSCAN_FROM_RSCAN0TMID59 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID59) /* RSCAN_FROM_RSCAN0TMID59 */
+#define RSCAN_FROM_RSCAN0TMID60 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID60) /* RSCAN_FROM_RSCAN0TMID60 */
+#define RSCAN_FROM_RSCAN0TMID61 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID61) /* RSCAN_FROM_RSCAN0TMID61 */
+#define RSCAN_FROM_RSCAN0TMID62 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID62) /* RSCAN_FROM_RSCAN0TMID62 */
+#define RSCAN_FROM_RSCAN0TMID63 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID63) /* RSCAN_FROM_RSCAN0TMID63 */
+#define RSCAN_FROM_RSCAN0TMID64 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID64) /* RSCAN_FROM_RSCAN0TMID64 */
+#define RSCAN_FROM_RSCAN0TMID65 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID65) /* RSCAN_FROM_RSCAN0TMID65 */
+#define RSCAN_FROM_RSCAN0TMID66 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID66) /* RSCAN_FROM_RSCAN0TMID66 */
+#define RSCAN_FROM_RSCAN0TMID67 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID67) /* RSCAN_FROM_RSCAN0TMID67 */
+#define RSCAN_FROM_RSCAN0TMID68 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID68) /* RSCAN_FROM_RSCAN0TMID68 */
+#define RSCAN_FROM_RSCAN0TMID69 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID69) /* RSCAN_FROM_RSCAN0TMID69 */
+#define RSCAN_FROM_RSCAN0TMID70 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID70) /* RSCAN_FROM_RSCAN0TMID70 */
+#define RSCAN_FROM_RSCAN0TMID71 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID71) /* RSCAN_FROM_RSCAN0TMID71 */
+#define RSCAN_FROM_RSCAN0TMID72 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID72) /* RSCAN_FROM_RSCAN0TMID72 */
+#define RSCAN_FROM_RSCAN0TMID73 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID73) /* RSCAN_FROM_RSCAN0TMID73 */
+#define RSCAN_FROM_RSCAN0TMID74 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID74) /* RSCAN_FROM_RSCAN0TMID74 */
+#define RSCAN_FROM_RSCAN0TMID75 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID75) /* RSCAN_FROM_RSCAN0TMID75 */
+#define RSCAN_FROM_RSCAN0TMID76 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID76) /* RSCAN_FROM_RSCAN0TMID76 */
+#define RSCAN_FROM_RSCAN0TMID77 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID77) /* RSCAN_FROM_RSCAN0TMID77 */
+#define RSCAN_FROM_RSCAN0TMID78 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID78) /* RSCAN_FROM_RSCAN0TMID78 */
+#define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0RFIDm */
+/*(Sample) value = RSCAN_FROM_RSCAN0RFIDm[ channel ]->RFIDm.UINT32; */
+#define RSCAN_FROM_RSCAN0RFIDm_COUNT 8
+#define RSCAN_FROM_RSCAN0RFIDm_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0RFID0 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID0) /* RSCAN_FROM_RSCAN0RFID0 */
+#define RSCAN_FROM_RSCAN0RFID1 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID1) /* RSCAN_FROM_RSCAN0RFID1 */
+#define RSCAN_FROM_RSCAN0RFID2 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID2) /* RSCAN_FROM_RSCAN0RFID2 */
+#define RSCAN_FROM_RSCAN0RFID3 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID3) /* RSCAN_FROM_RSCAN0RFID3 */
+#define RSCAN_FROM_RSCAN0RFID4 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID4) /* RSCAN_FROM_RSCAN0RFID4 */
+#define RSCAN_FROM_RSCAN0RFID5 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID5) /* RSCAN_FROM_RSCAN0RFID5 */
+#define RSCAN_FROM_RSCAN0RFID6 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID6) /* RSCAN_FROM_RSCAN0RFID6 */
+#define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0RMIDp */
+/*(Sample) value = RSCAN_FROM_RSCAN0RMIDp[ channel ]->RMIDp.UINT32; */
+#define RSCAN_FROM_RSCAN0RMIDp_COUNT 80
+#define RSCAN_FROM_RSCAN0RMIDp_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \
+ &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \
+ &RSCAN_FROM_RSCAN0RMID16, &RSCAN_FROM_RSCAN0RMID17, &RSCAN_FROM_RSCAN0RMID18, &RSCAN_FROM_RSCAN0RMID19, &RSCAN_FROM_RSCAN0RMID20, &RSCAN_FROM_RSCAN0RMID21, &RSCAN_FROM_RSCAN0RMID22, &RSCAN_FROM_RSCAN0RMID23, \
+ &RSCAN_FROM_RSCAN0RMID24, &RSCAN_FROM_RSCAN0RMID25, &RSCAN_FROM_RSCAN0RMID26, &RSCAN_FROM_RSCAN0RMID27, &RSCAN_FROM_RSCAN0RMID28, &RSCAN_FROM_RSCAN0RMID29, &RSCAN_FROM_RSCAN0RMID30, &RSCAN_FROM_RSCAN0RMID31, \
+ &RSCAN_FROM_RSCAN0RMID32, &RSCAN_FROM_RSCAN0RMID33, &RSCAN_FROM_RSCAN0RMID34, &RSCAN_FROM_RSCAN0RMID35, &RSCAN_FROM_RSCAN0RMID36, &RSCAN_FROM_RSCAN0RMID37, &RSCAN_FROM_RSCAN0RMID38, &RSCAN_FROM_RSCAN0RMID39, \
+ &RSCAN_FROM_RSCAN0RMID40, &RSCAN_FROM_RSCAN0RMID41, &RSCAN_FROM_RSCAN0RMID42, &RSCAN_FROM_RSCAN0RMID43, &RSCAN_FROM_RSCAN0RMID44, &RSCAN_FROM_RSCAN0RMID45, &RSCAN_FROM_RSCAN0RMID46, &RSCAN_FROM_RSCAN0RMID47, \
+ &RSCAN_FROM_RSCAN0RMID48, &RSCAN_FROM_RSCAN0RMID49, &RSCAN_FROM_RSCAN0RMID50, &RSCAN_FROM_RSCAN0RMID51, &RSCAN_FROM_RSCAN0RMID52, &RSCAN_FROM_RSCAN0RMID53, &RSCAN_FROM_RSCAN0RMID54, &RSCAN_FROM_RSCAN0RMID55, \
+ &RSCAN_FROM_RSCAN0RMID56, &RSCAN_FROM_RSCAN0RMID57, &RSCAN_FROM_RSCAN0RMID58, &RSCAN_FROM_RSCAN0RMID59, &RSCAN_FROM_RSCAN0RMID60, &RSCAN_FROM_RSCAN0RMID61, &RSCAN_FROM_RSCAN0RMID62, &RSCAN_FROM_RSCAN0RMID63, \
+ &RSCAN_FROM_RSCAN0RMID64, &RSCAN_FROM_RSCAN0RMID65, &RSCAN_FROM_RSCAN0RMID66, &RSCAN_FROM_RSCAN0RMID67, &RSCAN_FROM_RSCAN0RMID68, &RSCAN_FROM_RSCAN0RMID69, &RSCAN_FROM_RSCAN0RMID70, &RSCAN_FROM_RSCAN0RMID71, \
+ &RSCAN_FROM_RSCAN0RMID72, &RSCAN_FROM_RSCAN0RMID73, &RSCAN_FROM_RSCAN0RMID74, &RSCAN_FROM_RSCAN0RMID75, &RSCAN_FROM_RSCAN0RMID76, &RSCAN_FROM_RSCAN0RMID77, &RSCAN_FROM_RSCAN0RMID78, &RSCAN_FROM_RSCAN0RMID79 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0RMID0 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID0) /* RSCAN_FROM_RSCAN0RMID0 */
+#define RSCAN_FROM_RSCAN0RMID1 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID1) /* RSCAN_FROM_RSCAN0RMID1 */
+#define RSCAN_FROM_RSCAN0RMID2 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID2) /* RSCAN_FROM_RSCAN0RMID2 */
+#define RSCAN_FROM_RSCAN0RMID3 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID3) /* RSCAN_FROM_RSCAN0RMID3 */
+#define RSCAN_FROM_RSCAN0RMID4 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID4) /* RSCAN_FROM_RSCAN0RMID4 */
+#define RSCAN_FROM_RSCAN0RMID5 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID5) /* RSCAN_FROM_RSCAN0RMID5 */
+#define RSCAN_FROM_RSCAN0RMID6 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID6) /* RSCAN_FROM_RSCAN0RMID6 */
+#define RSCAN_FROM_RSCAN0RMID7 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID7) /* RSCAN_FROM_RSCAN0RMID7 */
+#define RSCAN_FROM_RSCAN0RMID8 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID8) /* RSCAN_FROM_RSCAN0RMID8 */
+#define RSCAN_FROM_RSCAN0RMID9 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID9) /* RSCAN_FROM_RSCAN0RMID9 */
+#define RSCAN_FROM_RSCAN0RMID10 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID10) /* RSCAN_FROM_RSCAN0RMID10 */
+#define RSCAN_FROM_RSCAN0RMID11 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID11) /* RSCAN_FROM_RSCAN0RMID11 */
+#define RSCAN_FROM_RSCAN0RMID12 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID12) /* RSCAN_FROM_RSCAN0RMID12 */
+#define RSCAN_FROM_RSCAN0RMID13 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID13) /* RSCAN_FROM_RSCAN0RMID13 */
+#define RSCAN_FROM_RSCAN0RMID14 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID14) /* RSCAN_FROM_RSCAN0RMID14 */
+#define RSCAN_FROM_RSCAN0RMID15 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID15) /* RSCAN_FROM_RSCAN0RMID15 */
+#define RSCAN_FROM_RSCAN0RMID16 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID16) /* RSCAN_FROM_RSCAN0RMID16 */
+#define RSCAN_FROM_RSCAN0RMID17 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID17) /* RSCAN_FROM_RSCAN0RMID17 */
+#define RSCAN_FROM_RSCAN0RMID18 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID18) /* RSCAN_FROM_RSCAN0RMID18 */
+#define RSCAN_FROM_RSCAN0RMID19 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID19) /* RSCAN_FROM_RSCAN0RMID19 */
+#define RSCAN_FROM_RSCAN0RMID20 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID20) /* RSCAN_FROM_RSCAN0RMID20 */
+#define RSCAN_FROM_RSCAN0RMID21 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID21) /* RSCAN_FROM_RSCAN0RMID21 */
+#define RSCAN_FROM_RSCAN0RMID22 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID22) /* RSCAN_FROM_RSCAN0RMID22 */
+#define RSCAN_FROM_RSCAN0RMID23 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID23) /* RSCAN_FROM_RSCAN0RMID23 */
+#define RSCAN_FROM_RSCAN0RMID24 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID24) /* RSCAN_FROM_RSCAN0RMID24 */
+#define RSCAN_FROM_RSCAN0RMID25 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID25) /* RSCAN_FROM_RSCAN0RMID25 */
+#define RSCAN_FROM_RSCAN0RMID26 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID26) /* RSCAN_FROM_RSCAN0RMID26 */
+#define RSCAN_FROM_RSCAN0RMID27 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID27) /* RSCAN_FROM_RSCAN0RMID27 */
+#define RSCAN_FROM_RSCAN0RMID28 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID28) /* RSCAN_FROM_RSCAN0RMID28 */
+#define RSCAN_FROM_RSCAN0RMID29 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID29) /* RSCAN_FROM_RSCAN0RMID29 */
+#define RSCAN_FROM_RSCAN0RMID30 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID30) /* RSCAN_FROM_RSCAN0RMID30 */
+#define RSCAN_FROM_RSCAN0RMID31 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID31) /* RSCAN_FROM_RSCAN0RMID31 */
+#define RSCAN_FROM_RSCAN0RMID32 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID32) /* RSCAN_FROM_RSCAN0RMID32 */
+#define RSCAN_FROM_RSCAN0RMID33 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID33) /* RSCAN_FROM_RSCAN0RMID33 */
+#define RSCAN_FROM_RSCAN0RMID34 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID34) /* RSCAN_FROM_RSCAN0RMID34 */
+#define RSCAN_FROM_RSCAN0RMID35 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID35) /* RSCAN_FROM_RSCAN0RMID35 */
+#define RSCAN_FROM_RSCAN0RMID36 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID36) /* RSCAN_FROM_RSCAN0RMID36 */
+#define RSCAN_FROM_RSCAN0RMID37 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID37) /* RSCAN_FROM_RSCAN0RMID37 */
+#define RSCAN_FROM_RSCAN0RMID38 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID38) /* RSCAN_FROM_RSCAN0RMID38 */
+#define RSCAN_FROM_RSCAN0RMID39 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID39) /* RSCAN_FROM_RSCAN0RMID39 */
+#define RSCAN_FROM_RSCAN0RMID40 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID40) /* RSCAN_FROM_RSCAN0RMID40 */
+#define RSCAN_FROM_RSCAN0RMID41 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID41) /* RSCAN_FROM_RSCAN0RMID41 */
+#define RSCAN_FROM_RSCAN0RMID42 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID42) /* RSCAN_FROM_RSCAN0RMID42 */
+#define RSCAN_FROM_RSCAN0RMID43 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID43) /* RSCAN_FROM_RSCAN0RMID43 */
+#define RSCAN_FROM_RSCAN0RMID44 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID44) /* RSCAN_FROM_RSCAN0RMID44 */
+#define RSCAN_FROM_RSCAN0RMID45 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID45) /* RSCAN_FROM_RSCAN0RMID45 */
+#define RSCAN_FROM_RSCAN0RMID46 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID46) /* RSCAN_FROM_RSCAN0RMID46 */
+#define RSCAN_FROM_RSCAN0RMID47 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID47) /* RSCAN_FROM_RSCAN0RMID47 */
+#define RSCAN_FROM_RSCAN0RMID48 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID48) /* RSCAN_FROM_RSCAN0RMID48 */
+#define RSCAN_FROM_RSCAN0RMID49 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID49) /* RSCAN_FROM_RSCAN0RMID49 */
+#define RSCAN_FROM_RSCAN0RMID50 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID50) /* RSCAN_FROM_RSCAN0RMID50 */
+#define RSCAN_FROM_RSCAN0RMID51 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID51) /* RSCAN_FROM_RSCAN0RMID51 */
+#define RSCAN_FROM_RSCAN0RMID52 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID52) /* RSCAN_FROM_RSCAN0RMID52 */
+#define RSCAN_FROM_RSCAN0RMID53 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID53) /* RSCAN_FROM_RSCAN0RMID53 */
+#define RSCAN_FROM_RSCAN0RMID54 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID54) /* RSCAN_FROM_RSCAN0RMID54 */
+#define RSCAN_FROM_RSCAN0RMID55 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID55) /* RSCAN_FROM_RSCAN0RMID55 */
+#define RSCAN_FROM_RSCAN0RMID56 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID56) /* RSCAN_FROM_RSCAN0RMID56 */
+#define RSCAN_FROM_RSCAN0RMID57 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID57) /* RSCAN_FROM_RSCAN0RMID57 */
+#define RSCAN_FROM_RSCAN0RMID58 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID58) /* RSCAN_FROM_RSCAN0RMID58 */
+#define RSCAN_FROM_RSCAN0RMID59 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID59) /* RSCAN_FROM_RSCAN0RMID59 */
+#define RSCAN_FROM_RSCAN0RMID60 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID60) /* RSCAN_FROM_RSCAN0RMID60 */
+#define RSCAN_FROM_RSCAN0RMID61 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID61) /* RSCAN_FROM_RSCAN0RMID61 */
+#define RSCAN_FROM_RSCAN0RMID62 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID62) /* RSCAN_FROM_RSCAN0RMID62 */
+#define RSCAN_FROM_RSCAN0RMID63 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID63) /* RSCAN_FROM_RSCAN0RMID63 */
+#define RSCAN_FROM_RSCAN0RMID64 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID64) /* RSCAN_FROM_RSCAN0RMID64 */
+#define RSCAN_FROM_RSCAN0RMID65 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID65) /* RSCAN_FROM_RSCAN0RMID65 */
+#define RSCAN_FROM_RSCAN0RMID66 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID66) /* RSCAN_FROM_RSCAN0RMID66 */
+#define RSCAN_FROM_RSCAN0RMID67 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID67) /* RSCAN_FROM_RSCAN0RMID67 */
+#define RSCAN_FROM_RSCAN0RMID68 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID68) /* RSCAN_FROM_RSCAN0RMID68 */
+#define RSCAN_FROM_RSCAN0RMID69 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID69) /* RSCAN_FROM_RSCAN0RMID69 */
+#define RSCAN_FROM_RSCAN0RMID70 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID70) /* RSCAN_FROM_RSCAN0RMID70 */
+#define RSCAN_FROM_RSCAN0RMID71 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID71) /* RSCAN_FROM_RSCAN0RMID71 */
+#define RSCAN_FROM_RSCAN0RMID72 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID72) /* RSCAN_FROM_RSCAN0RMID72 */
+#define RSCAN_FROM_RSCAN0RMID73 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID73) /* RSCAN_FROM_RSCAN0RMID73 */
+#define RSCAN_FROM_RSCAN0RMID74 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID74) /* RSCAN_FROM_RSCAN0RMID74 */
+#define RSCAN_FROM_RSCAN0RMID75 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID75) /* RSCAN_FROM_RSCAN0RMID75 */
+#define RSCAN_FROM_RSCAN0RMID76 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID76) /* RSCAN_FROM_RSCAN0RMID76 */
+#define RSCAN_FROM_RSCAN0RMID77 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID77) /* RSCAN_FROM_RSCAN0RMID77 */
+#define RSCAN_FROM_RSCAN0RMID78 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID78) /* RSCAN_FROM_RSCAN0RMID78 */
+#define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0GAFLIDj */
+/*(Sample) value = RSCAN_FROM_RSCAN0GAFLIDj[ channel ]->GAFLIDj.UINT32; */
+#define RSCAN_FROM_RSCAN0GAFLIDj_COUNT 16
+#define RSCAN_FROM_RSCAN0GAFLIDj_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \
+ &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0GAFLID0 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID0) /* RSCAN_FROM_RSCAN0GAFLID0 */
+#define RSCAN_FROM_RSCAN0GAFLID1 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID1) /* RSCAN_FROM_RSCAN0GAFLID1 */
+#define RSCAN_FROM_RSCAN0GAFLID2 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID2) /* RSCAN_FROM_RSCAN0GAFLID2 */
+#define RSCAN_FROM_RSCAN0GAFLID3 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID3) /* RSCAN_FROM_RSCAN0GAFLID3 */
+#define RSCAN_FROM_RSCAN0GAFLID4 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID4) /* RSCAN_FROM_RSCAN0GAFLID4 */
+#define RSCAN_FROM_RSCAN0GAFLID5 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID5) /* RSCAN_FROM_RSCAN0GAFLID5 */
+#define RSCAN_FROM_RSCAN0GAFLID6 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID6) /* RSCAN_FROM_RSCAN0GAFLID6 */
+#define RSCAN_FROM_RSCAN0GAFLID7 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID7) /* RSCAN_FROM_RSCAN0GAFLID7 */
+#define RSCAN_FROM_RSCAN0GAFLID8 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID8) /* RSCAN_FROM_RSCAN0GAFLID8 */
+#define RSCAN_FROM_RSCAN0GAFLID9 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID9) /* RSCAN_FROM_RSCAN0GAFLID9 */
+#define RSCAN_FROM_RSCAN0GAFLID10 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID10) /* RSCAN_FROM_RSCAN0GAFLID10 */
+#define RSCAN_FROM_RSCAN0GAFLID11 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID11) /* RSCAN_FROM_RSCAN0GAFLID11 */
+#define RSCAN_FROM_RSCAN0GAFLID12 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID12) /* RSCAN_FROM_RSCAN0GAFLID12 */
+#define RSCAN_FROM_RSCAN0GAFLID13 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID13) /* RSCAN_FROM_RSCAN0GAFLID13 */
+#define RSCAN_FROM_RSCAN0GAFLID14 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID14) /* RSCAN_FROM_RSCAN0GAFLID14 */
+#define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0CnCFG */
+/*(Sample) value = RSCAN_FROM_RSCAN0CnCFG[ channel ]->CnCFG.UINT32; */
+#define RSCAN_FROM_RSCAN0CnCFG_COUNT 5
+#define RSCAN_FROM_RSCAN0CnCFG_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0C0CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C0CFG) /* RSCAN_FROM_RSCAN0C0CFG */
+#define RSCAN_FROM_RSCAN0C1CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C1CFG) /* RSCAN_FROM_RSCAN0C1CFG */
+#define RSCAN_FROM_RSCAN0C2CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C2CFG) /* RSCAN_FROM_RSCAN0C2CFG */
+#define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */
+#define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */
+
+/* End of channnel array defines of RSCAN0 */
+
+
+#define RSCAN0C0CFG RSCAN0.C0CFG.UINT32
+#define RSCAN0C0CFGL RSCAN0.C0CFG.UINT16[L]
+#define RSCAN0C0CFGLL RSCAN0.C0CFG.UINT8[LL]
+#define RSCAN0C0CFGLH RSCAN0.C0CFG.UINT8[LH]
+#define RSCAN0C0CFGH RSCAN0.C0CFG.UINT16[H]
+#define RSCAN0C0CFGHL RSCAN0.C0CFG.UINT8[HL]
+#define RSCAN0C0CFGHH RSCAN0.C0CFG.UINT8[HH]
+#define RSCAN0C0CTR RSCAN0.C0CTR.UINT32
+#define RSCAN0C0CTRL RSCAN0.C0CTR.UINT16[L]
+#define RSCAN0C0CTRLL RSCAN0.C0CTR.UINT8[LL]
+#define RSCAN0C0CTRLH RSCAN0.C0CTR.UINT8[LH]
+#define RSCAN0C0CTRH RSCAN0.C0CTR.UINT16[H]
+#define RSCAN0C0CTRHL RSCAN0.C0CTR.UINT8[HL]
+#define RSCAN0C0CTRHH RSCAN0.C0CTR.UINT8[HH]
+#define RSCAN0C0STS RSCAN0.C0STS.UINT32
+#define RSCAN0C0STSL RSCAN0.C0STS.UINT16[L]
+#define RSCAN0C0STSLL RSCAN0.C0STS.UINT8[LL]
+#define RSCAN0C0STSLH RSCAN0.C0STS.UINT8[LH]
+#define RSCAN0C0STSH RSCAN0.C0STS.UINT16[H]
+#define RSCAN0C0STSHL RSCAN0.C0STS.UINT8[HL]
+#define RSCAN0C0STSHH RSCAN0.C0STS.UINT8[HH]
+#define RSCAN0C0ERFL RSCAN0.C0ERFL.UINT32
+#define RSCAN0C0ERFLL RSCAN0.C0ERFL.UINT16[L]
+#define RSCAN0C0ERFLLL RSCAN0.C0ERFL.UINT8[LL]
+#define RSCAN0C0ERFLLH RSCAN0.C0ERFL.UINT8[LH]
+#define RSCAN0C0ERFLH RSCAN0.C0ERFL.UINT16[H]
+#define RSCAN0C0ERFLHL RSCAN0.C0ERFL.UINT8[HL]
+#define RSCAN0C0ERFLHH RSCAN0.C0ERFL.UINT8[HH]
+#define RSCAN0C1CFG RSCAN0.C1CFG.UINT32
+#define RSCAN0C1CFGL RSCAN0.C1CFG.UINT16[L]
+#define RSCAN0C1CFGLL RSCAN0.C1CFG.UINT8[LL]
+#define RSCAN0C1CFGLH RSCAN0.C1CFG.UINT8[LH]
+#define RSCAN0C1CFGH RSCAN0.C1CFG.UINT16[H]
+#define RSCAN0C1CFGHL RSCAN0.C1CFG.UINT8[HL]
+#define RSCAN0C1CFGHH RSCAN0.C1CFG.UINT8[HH]
+#define RSCAN0C1CTR RSCAN0.C1CTR.UINT32
+#define RSCAN0C1CTRL RSCAN0.C1CTR.UINT16[L]
+#define RSCAN0C1CTRLL RSCAN0.C1CTR.UINT8[LL]
+#define RSCAN0C1CTRLH RSCAN0.C1CTR.UINT8[LH]
+#define RSCAN0C1CTRH RSCAN0.C1CTR.UINT16[H]
+#define RSCAN0C1CTRHL RSCAN0.C1CTR.UINT8[HL]
+#define RSCAN0C1CTRHH RSCAN0.C1CTR.UINT8[HH]
+#define RSCAN0C1STS RSCAN0.C1STS.UINT32
+#define RSCAN0C1STSL RSCAN0.C1STS.UINT16[L]
+#define RSCAN0C1STSLL RSCAN0.C1STS.UINT8[LL]
+#define RSCAN0C1STSLH RSCAN0.C1STS.UINT8[LH]
+#define RSCAN0C1STSH RSCAN0.C1STS.UINT16[H]
+#define RSCAN0C1STSHL RSCAN0.C1STS.UINT8[HL]
+#define RSCAN0C1STSHH RSCAN0.C1STS.UINT8[HH]
+#define RSCAN0C1ERFL RSCAN0.C1ERFL.UINT32
+#define RSCAN0C1ERFLL RSCAN0.C1ERFL.UINT16[L]
+#define RSCAN0C1ERFLLL RSCAN0.C1ERFL.UINT8[LL]
+#define RSCAN0C1ERFLLH RSCAN0.C1ERFL.UINT8[LH]
+#define RSCAN0C1ERFLH RSCAN0.C1ERFL.UINT16[H]
+#define RSCAN0C1ERFLHL RSCAN0.C1ERFL.UINT8[HL]
+#define RSCAN0C1ERFLHH RSCAN0.C1ERFL.UINT8[HH]
+#define RSCAN0C2CFG RSCAN0.C2CFG.UINT32
+#define RSCAN0C2CFGL RSCAN0.C2CFG.UINT16[L]
+#define RSCAN0C2CFGLL RSCAN0.C2CFG.UINT8[LL]
+#define RSCAN0C2CFGLH RSCAN0.C2CFG.UINT8[LH]
+#define RSCAN0C2CFGH RSCAN0.C2CFG.UINT16[H]
+#define RSCAN0C2CFGHL RSCAN0.C2CFG.UINT8[HL]
+#define RSCAN0C2CFGHH RSCAN0.C2CFG.UINT8[HH]
+#define RSCAN0C2CTR RSCAN0.C2CTR.UINT32
+#define RSCAN0C2CTRL RSCAN0.C2CTR.UINT16[L]
+#define RSCAN0C2CTRLL RSCAN0.C2CTR.UINT8[LL]
+#define RSCAN0C2CTRLH RSCAN0.C2CTR.UINT8[LH]
+#define RSCAN0C2CTRH RSCAN0.C2CTR.UINT16[H]
+#define RSCAN0C2CTRHL RSCAN0.C2CTR.UINT8[HL]
+#define RSCAN0C2CTRHH RSCAN0.C2CTR.UINT8[HH]
+#define RSCAN0C2STS RSCAN0.C2STS.UINT32
+#define RSCAN0C2STSL RSCAN0.C2STS.UINT16[L]
+#define RSCAN0C2STSLL RSCAN0.C2STS.UINT8[LL]
+#define RSCAN0C2STSLH RSCAN0.C2STS.UINT8[LH]
+#define RSCAN0C2STSH RSCAN0.C2STS.UINT16[H]
+#define RSCAN0C2STSHL RSCAN0.C2STS.UINT8[HL]
+#define RSCAN0C2STSHH RSCAN0.C2STS.UINT8[HH]
+#define RSCAN0C2ERFL RSCAN0.C2ERFL.UINT32
+#define RSCAN0C2ERFLL RSCAN0.C2ERFL.UINT16[L]
+#define RSCAN0C2ERFLLL RSCAN0.C2ERFL.UINT8[LL]
+#define RSCAN0C2ERFLLH RSCAN0.C2ERFL.UINT8[LH]
+#define RSCAN0C2ERFLH RSCAN0.C2ERFL.UINT16[H]
+#define RSCAN0C2ERFLHL RSCAN0.C2ERFL.UINT8[HL]
+#define RSCAN0C2ERFLHH RSCAN0.C2ERFL.UINT8[HH]
+#define RSCAN0C3CFG RSCAN0.C3CFG.UINT32
+#define RSCAN0C3CFGL RSCAN0.C3CFG.UINT16[L]
+#define RSCAN0C3CFGLL RSCAN0.C3CFG.UINT8[LL]
+#define RSCAN0C3CFGLH RSCAN0.C3CFG.UINT8[LH]
+#define RSCAN0C3CFGH RSCAN0.C3CFG.UINT16[H]
+#define RSCAN0C3CFGHL RSCAN0.C3CFG.UINT8[HL]
+#define RSCAN0C3CFGHH RSCAN0.C3CFG.UINT8[HH]
+#define RSCAN0C3CTR RSCAN0.C3CTR.UINT32
+#define RSCAN0C3CTRL RSCAN0.C3CTR.UINT16[L]
+#define RSCAN0C3CTRLL RSCAN0.C3CTR.UINT8[LL]
+#define RSCAN0C3CTRLH RSCAN0.C3CTR.UINT8[LH]
+#define RSCAN0C3CTRH RSCAN0.C3CTR.UINT16[H]
+#define RSCAN0C3CTRHL RSCAN0.C3CTR.UINT8[HL]
+#define RSCAN0C3CTRHH RSCAN0.C3CTR.UINT8[HH]
+#define RSCAN0C3STS RSCAN0.C3STS.UINT32
+#define RSCAN0C3STSL RSCAN0.C3STS.UINT16[L]
+#define RSCAN0C3STSLL RSCAN0.C3STS.UINT8[LL]
+#define RSCAN0C3STSLH RSCAN0.C3STS.UINT8[LH]
+#define RSCAN0C3STSH RSCAN0.C3STS.UINT16[H]
+#define RSCAN0C3STSHL RSCAN0.C3STS.UINT8[HL]
+#define RSCAN0C3STSHH RSCAN0.C3STS.UINT8[HH]
+#define RSCAN0C3ERFL RSCAN0.C3ERFL.UINT32
+#define RSCAN0C3ERFLL RSCAN0.C3ERFL.UINT16[L]
+#define RSCAN0C3ERFLLL RSCAN0.C3ERFL.UINT8[LL]
+#define RSCAN0C3ERFLLH RSCAN0.C3ERFL.UINT8[LH]
+#define RSCAN0C3ERFLH RSCAN0.C3ERFL.UINT16[H]
+#define RSCAN0C3ERFLHL RSCAN0.C3ERFL.UINT8[HL]
+#define RSCAN0C3ERFLHH RSCAN0.C3ERFL.UINT8[HH]
+#define RSCAN0C4CFG RSCAN0.C4CFG.UINT32
+#define RSCAN0C4CFGL RSCAN0.C4CFG.UINT16[L]
+#define RSCAN0C4CFGLL RSCAN0.C4CFG.UINT8[LL]
+#define RSCAN0C4CFGLH RSCAN0.C4CFG.UINT8[LH]
+#define RSCAN0C4CFGH RSCAN0.C4CFG.UINT16[H]
+#define RSCAN0C4CFGHL RSCAN0.C4CFG.UINT8[HL]
+#define RSCAN0C4CFGHH RSCAN0.C4CFG.UINT8[HH]
+#define RSCAN0C4CTR RSCAN0.C4CTR.UINT32
+#define RSCAN0C4CTRL RSCAN0.C4CTR.UINT16[L]
+#define RSCAN0C4CTRLL RSCAN0.C4CTR.UINT8[LL]
+#define RSCAN0C4CTRLH RSCAN0.C4CTR.UINT8[LH]
+#define RSCAN0C4CTRH RSCAN0.C4CTR.UINT16[H]
+#define RSCAN0C4CTRHL RSCAN0.C4CTR.UINT8[HL]
+#define RSCAN0C4CTRHH RSCAN0.C4CTR.UINT8[HH]
+#define RSCAN0C4STS RSCAN0.C4STS.UINT32
+#define RSCAN0C4STSL RSCAN0.C4STS.UINT16[L]
+#define RSCAN0C4STSLL RSCAN0.C4STS.UINT8[LL]
+#define RSCAN0C4STSLH RSCAN0.C4STS.UINT8[LH]
+#define RSCAN0C4STSH RSCAN0.C4STS.UINT16[H]
+#define RSCAN0C4STSHL RSCAN0.C4STS.UINT8[HL]
+#define RSCAN0C4STSHH RSCAN0.C4STS.UINT8[HH]
+#define RSCAN0C4ERFL RSCAN0.C4ERFL.UINT32
+#define RSCAN0C4ERFLL RSCAN0.C4ERFL.UINT16[L]
+#define RSCAN0C4ERFLLL RSCAN0.C4ERFL.UINT8[LL]
+#define RSCAN0C4ERFLLH RSCAN0.C4ERFL.UINT8[LH]
+#define RSCAN0C4ERFLH RSCAN0.C4ERFL.UINT16[H]
+#define RSCAN0C4ERFLHL RSCAN0.C4ERFL.UINT8[HL]
+#define RSCAN0C4ERFLHH RSCAN0.C4ERFL.UINT8[HH]
+#define RSCAN0GCFG RSCAN0.GCFG.UINT32
+#define RSCAN0GCFGL RSCAN0.GCFG.UINT16[L]
+#define RSCAN0GCFGLL RSCAN0.GCFG.UINT8[LL]
+#define RSCAN0GCFGLH RSCAN0.GCFG.UINT8[LH]
+#define RSCAN0GCFGH RSCAN0.GCFG.UINT16[H]
+#define RSCAN0GCFGHL RSCAN0.GCFG.UINT8[HL]
+#define RSCAN0GCFGHH RSCAN0.GCFG.UINT8[HH]
+#define RSCAN0GCTR RSCAN0.GCTR.UINT32
+#define RSCAN0GCTRL RSCAN0.GCTR.UINT16[L]
+#define RSCAN0GCTRLL RSCAN0.GCTR.UINT8[LL]
+#define RSCAN0GCTRLH RSCAN0.GCTR.UINT8[LH]
+#define RSCAN0GCTRH RSCAN0.GCTR.UINT16[H]
+#define RSCAN0GCTRHL RSCAN0.GCTR.UINT8[HL]
+#define RSCAN0GCTRHH RSCAN0.GCTR.UINT8[HH]
+#define RSCAN0GSTS RSCAN0.GSTS.UINT32
+#define RSCAN0GSTSL RSCAN0.GSTS.UINT16[L]
+#define RSCAN0GSTSLL RSCAN0.GSTS.UINT8[LL]
+#define RSCAN0GSTSLH RSCAN0.GSTS.UINT8[LH]
+#define RSCAN0GSTSH RSCAN0.GSTS.UINT16[H]
+#define RSCAN0GSTSHL RSCAN0.GSTS.UINT8[HL]
+#define RSCAN0GSTSHH RSCAN0.GSTS.UINT8[HH]
+#define RSCAN0GERFL RSCAN0.GERFL.UINT32
+#define RSCAN0GERFLL RSCAN0.GERFL.UINT16[L]
+#define RSCAN0GERFLLL RSCAN0.GERFL.UINT8[LL]
+#define RSCAN0GERFLLH RSCAN0.GERFL.UINT8[LH]
+#define RSCAN0GERFLH RSCAN0.GERFL.UINT16[H]
+#define RSCAN0GERFLHL RSCAN0.GERFL.UINT8[HL]
+#define RSCAN0GERFLHH RSCAN0.GERFL.UINT8[HH]
+#define RSCAN0GTSC RSCAN0.GTSC.UINT32
+#define RSCAN0GTSCL RSCAN0.GTSC.UINT16[L]
+#define RSCAN0GTSCH RSCAN0.GTSC.UINT16[H]
+#define RSCAN0GAFLECTR RSCAN0.GAFLECTR.UINT32
+#define RSCAN0GAFLECTRL RSCAN0.GAFLECTR.UINT16[L]
+#define RSCAN0GAFLECTRLL RSCAN0.GAFLECTR.UINT8[LL]
+#define RSCAN0GAFLECTRLH RSCAN0.GAFLECTR.UINT8[LH]
+#define RSCAN0GAFLECTRH RSCAN0.GAFLECTR.UINT16[H]
+#define RSCAN0GAFLECTRHL RSCAN0.GAFLECTR.UINT8[HL]
+#define RSCAN0GAFLECTRHH RSCAN0.GAFLECTR.UINT8[HH]
+#define RSCAN0GAFLCFG0 RSCAN0.GAFLCFG0.UINT32
+#define RSCAN0GAFLCFG0L RSCAN0.GAFLCFG0.UINT16[L]
+#define RSCAN0GAFLCFG0LL RSCAN0.GAFLCFG0.UINT8[LL]
+#define RSCAN0GAFLCFG0LH RSCAN0.GAFLCFG0.UINT8[LH]
+#define RSCAN0GAFLCFG0H RSCAN0.GAFLCFG0.UINT16[H]
+#define RSCAN0GAFLCFG0HL RSCAN0.GAFLCFG0.UINT8[HL]
+#define RSCAN0GAFLCFG0HH RSCAN0.GAFLCFG0.UINT8[HH]
+#define RSCAN0GAFLCFG1 RSCAN0.GAFLCFG1.UINT32
+#define RSCAN0GAFLCFG1L RSCAN0.GAFLCFG1.UINT16[L]
+#define RSCAN0GAFLCFG1LL RSCAN0.GAFLCFG1.UINT8[LL]
+#define RSCAN0GAFLCFG1LH RSCAN0.GAFLCFG1.UINT8[LH]
+#define RSCAN0GAFLCFG1H RSCAN0.GAFLCFG1.UINT16[H]
+#define RSCAN0GAFLCFG1HL RSCAN0.GAFLCFG1.UINT8[HL]
+#define RSCAN0GAFLCFG1HH RSCAN0.GAFLCFG1.UINT8[HH]
+#define RSCAN0RMNB RSCAN0.RMNB.UINT32
+#define RSCAN0RMNBL RSCAN0.RMNB.UINT16[L]
+#define RSCAN0RMNBLL RSCAN0.RMNB.UINT8[LL]
+#define RSCAN0RMNBLH RSCAN0.RMNB.UINT8[LH]
+#define RSCAN0RMNBH RSCAN0.RMNB.UINT16[H]
+#define RSCAN0RMNBHL RSCAN0.RMNB.UINT8[HL]
+#define RSCAN0RMNBHH RSCAN0.RMNB.UINT8[HH]
+#define RSCAN0RMND0 RSCAN0.RMND0.UINT32
+#define RSCAN0RMND0L RSCAN0.RMND0.UINT16[L]
+#define RSCAN0RMND0LL RSCAN0.RMND0.UINT8[LL]
+#define RSCAN0RMND0LH RSCAN0.RMND0.UINT8[LH]
+#define RSCAN0RMND0H RSCAN0.RMND0.UINT16[H]
+#define RSCAN0RMND0HL RSCAN0.RMND0.UINT8[HL]
+#define RSCAN0RMND0HH RSCAN0.RMND0.UINT8[HH]
+#define RSCAN0RMND1 RSCAN0.RMND1.UINT32
+#define RSCAN0RMND1L RSCAN0.RMND1.UINT16[L]
+#define RSCAN0RMND1LL RSCAN0.RMND1.UINT8[LL]
+#define RSCAN0RMND1LH RSCAN0.RMND1.UINT8[LH]
+#define RSCAN0RMND1H RSCAN0.RMND1.UINT16[H]
+#define RSCAN0RMND1HL RSCAN0.RMND1.UINT8[HL]
+#define RSCAN0RMND1HH RSCAN0.RMND1.UINT8[HH]
+#define RSCAN0RMND2 RSCAN0.RMND2.UINT32
+#define RSCAN0RMND2L RSCAN0.RMND2.UINT16[L]
+#define RSCAN0RMND2LL RSCAN0.RMND2.UINT8[LL]
+#define RSCAN0RMND2LH RSCAN0.RMND2.UINT8[LH]
+#define RSCAN0RMND2H RSCAN0.RMND2.UINT16[H]
+#define RSCAN0RMND2HL RSCAN0.RMND2.UINT8[HL]
+#define RSCAN0RMND2HH RSCAN0.RMND2.UINT8[HH]
+#define RSCAN0RFCC0 RSCAN0.RFCC0.UINT32
+#define RSCAN0RFCC0L RSCAN0.RFCC0.UINT16[L]
+#define RSCAN0RFCC0LL RSCAN0.RFCC0.UINT8[LL]
+#define RSCAN0RFCC0LH RSCAN0.RFCC0.UINT8[LH]
+#define RSCAN0RFCC0H RSCAN0.RFCC0.UINT16[H]
+#define RSCAN0RFCC0HL RSCAN0.RFCC0.UINT8[HL]
+#define RSCAN0RFCC0HH RSCAN0.RFCC0.UINT8[HH]
+#define RSCAN0RFCC1 RSCAN0.RFCC1.UINT32
+#define RSCAN0RFCC1L RSCAN0.RFCC1.UINT16[L]
+#define RSCAN0RFCC1LL RSCAN0.RFCC1.UINT8[LL]
+#define RSCAN0RFCC1LH RSCAN0.RFCC1.UINT8[LH]
+#define RSCAN0RFCC1H RSCAN0.RFCC1.UINT16[H]
+#define RSCAN0RFCC1HL RSCAN0.RFCC1.UINT8[HL]
+#define RSCAN0RFCC1HH RSCAN0.RFCC1.UINT8[HH]
+#define RSCAN0RFCC2 RSCAN0.RFCC2.UINT32
+#define RSCAN0RFCC2L RSCAN0.RFCC2.UINT16[L]
+#define RSCAN0RFCC2LL RSCAN0.RFCC2.UINT8[LL]
+#define RSCAN0RFCC2LH RSCAN0.RFCC2.UINT8[LH]
+#define RSCAN0RFCC2H RSCAN0.RFCC2.UINT16[H]
+#define RSCAN0RFCC2HL RSCAN0.RFCC2.UINT8[HL]
+#define RSCAN0RFCC2HH RSCAN0.RFCC2.UINT8[HH]
+#define RSCAN0RFCC3 RSCAN0.RFCC3.UINT32
+#define RSCAN0RFCC3L RSCAN0.RFCC3.UINT16[L]
+#define RSCAN0RFCC3LL RSCAN0.RFCC3.UINT8[LL]
+#define RSCAN0RFCC3LH RSCAN0.RFCC3.UINT8[LH]
+#define RSCAN0RFCC3H RSCAN0.RFCC3.UINT16[H]
+#define RSCAN0RFCC3HL RSCAN0.RFCC3.UINT8[HL]
+#define RSCAN0RFCC3HH RSCAN0.RFCC3.UINT8[HH]
+#define RSCAN0RFCC4 RSCAN0.RFCC4.UINT32
+#define RSCAN0RFCC4L RSCAN0.RFCC4.UINT16[L]
+#define RSCAN0RFCC4LL RSCAN0.RFCC4.UINT8[LL]
+#define RSCAN0RFCC4LH RSCAN0.RFCC4.UINT8[LH]
+#define RSCAN0RFCC4H RSCAN0.RFCC4.UINT16[H]
+#define RSCAN0RFCC4HL RSCAN0.RFCC4.UINT8[HL]
+#define RSCAN0RFCC4HH RSCAN0.RFCC4.UINT8[HH]
+#define RSCAN0RFCC5 RSCAN0.RFCC5.UINT32
+#define RSCAN0RFCC5L RSCAN0.RFCC5.UINT16[L]
+#define RSCAN0RFCC5LL RSCAN0.RFCC5.UINT8[LL]
+#define RSCAN0RFCC5LH RSCAN0.RFCC5.UINT8[LH]
+#define RSCAN0RFCC5H RSCAN0.RFCC5.UINT16[H]
+#define RSCAN0RFCC5HL RSCAN0.RFCC5.UINT8[HL]
+#define RSCAN0RFCC5HH RSCAN0.RFCC5.UINT8[HH]
+#define RSCAN0RFCC6 RSCAN0.RFCC6.UINT32
+#define RSCAN0RFCC6L RSCAN0.RFCC6.UINT16[L]
+#define RSCAN0RFCC6LL RSCAN0.RFCC6.UINT8[LL]
+#define RSCAN0RFCC6LH RSCAN0.RFCC6.UINT8[LH]
+#define RSCAN0RFCC6H RSCAN0.RFCC6.UINT16[H]
+#define RSCAN0RFCC6HL RSCAN0.RFCC6.UINT8[HL]
+#define RSCAN0RFCC6HH RSCAN0.RFCC6.UINT8[HH]
+#define RSCAN0RFCC7 RSCAN0.RFCC7.UINT32
+#define RSCAN0RFCC7L RSCAN0.RFCC7.UINT16[L]
+#define RSCAN0RFCC7LL RSCAN0.RFCC7.UINT8[LL]
+#define RSCAN0RFCC7LH RSCAN0.RFCC7.UINT8[LH]
+#define RSCAN0RFCC7H RSCAN0.RFCC7.UINT16[H]
+#define RSCAN0RFCC7HL RSCAN0.RFCC7.UINT8[HL]
+#define RSCAN0RFCC7HH RSCAN0.RFCC7.UINT8[HH]
+#define RSCAN0RFSTS0 RSCAN0.RFSTS0.UINT32
+#define RSCAN0RFSTS0L RSCAN0.RFSTS0.UINT16[L]
+#define RSCAN0RFSTS0LL RSCAN0.RFSTS0.UINT8[LL]
+#define RSCAN0RFSTS0LH RSCAN0.RFSTS0.UINT8[LH]
+#define RSCAN0RFSTS0H RSCAN0.RFSTS0.UINT16[H]
+#define RSCAN0RFSTS0HL RSCAN0.RFSTS0.UINT8[HL]
+#define RSCAN0RFSTS0HH RSCAN0.RFSTS0.UINT8[HH]
+#define RSCAN0RFSTS1 RSCAN0.RFSTS1.UINT32
+#define RSCAN0RFSTS1L RSCAN0.RFSTS1.UINT16[L]
+#define RSCAN0RFSTS1LL RSCAN0.RFSTS1.UINT8[LL]
+#define RSCAN0RFSTS1LH RSCAN0.RFSTS1.UINT8[LH]
+#define RSCAN0RFSTS1H RSCAN0.RFSTS1.UINT16[H]
+#define RSCAN0RFSTS1HL RSCAN0.RFSTS1.UINT8[HL]
+#define RSCAN0RFSTS1HH RSCAN0.RFSTS1.UINT8[HH]
+#define RSCAN0RFSTS2 RSCAN0.RFSTS2.UINT32
+#define RSCAN0RFSTS2L RSCAN0.RFSTS2.UINT16[L]
+#define RSCAN0RFSTS2LL RSCAN0.RFSTS2.UINT8[LL]
+#define RSCAN0RFSTS2LH RSCAN0.RFSTS2.UINT8[LH]
+#define RSCAN0RFSTS2H RSCAN0.RFSTS2.UINT16[H]
+#define RSCAN0RFSTS2HL RSCAN0.RFSTS2.UINT8[HL]
+#define RSCAN0RFSTS2HH RSCAN0.RFSTS2.UINT8[HH]
+#define RSCAN0RFSTS3 RSCAN0.RFSTS3.UINT32
+#define RSCAN0RFSTS3L RSCAN0.RFSTS3.UINT16[L]
+#define RSCAN0RFSTS3LL RSCAN0.RFSTS3.UINT8[LL]
+#define RSCAN0RFSTS3LH RSCAN0.RFSTS3.UINT8[LH]
+#define RSCAN0RFSTS3H RSCAN0.RFSTS3.UINT16[H]
+#define RSCAN0RFSTS3HL RSCAN0.RFSTS3.UINT8[HL]
+#define RSCAN0RFSTS3HH RSCAN0.RFSTS3.UINT8[HH]
+#define RSCAN0RFSTS4 RSCAN0.RFSTS4.UINT32
+#define RSCAN0RFSTS4L RSCAN0.RFSTS4.UINT16[L]
+#define RSCAN0RFSTS4LL RSCAN0.RFSTS4.UINT8[LL]
+#define RSCAN0RFSTS4LH RSCAN0.RFSTS4.UINT8[LH]
+#define RSCAN0RFSTS4H RSCAN0.RFSTS4.UINT16[H]
+#define RSCAN0RFSTS4HL RSCAN0.RFSTS4.UINT8[HL]
+#define RSCAN0RFSTS4HH RSCAN0.RFSTS4.UINT8[HH]
+#define RSCAN0RFSTS5 RSCAN0.RFSTS5.UINT32
+#define RSCAN0RFSTS5L RSCAN0.RFSTS5.UINT16[L]
+#define RSCAN0RFSTS5LL RSCAN0.RFSTS5.UINT8[LL]
+#define RSCAN0RFSTS5LH RSCAN0.RFSTS5.UINT8[LH]
+#define RSCAN0RFSTS5H RSCAN0.RFSTS5.UINT16[H]
+#define RSCAN0RFSTS5HL RSCAN0.RFSTS5.UINT8[HL]
+#define RSCAN0RFSTS5HH RSCAN0.RFSTS5.UINT8[HH]
+#define RSCAN0RFSTS6 RSCAN0.RFSTS6.UINT32
+#define RSCAN0RFSTS6L RSCAN0.RFSTS6.UINT16[L]
+#define RSCAN0RFSTS6LL RSCAN0.RFSTS6.UINT8[LL]
+#define RSCAN0RFSTS6LH RSCAN0.RFSTS6.UINT8[LH]
+#define RSCAN0RFSTS6H RSCAN0.RFSTS6.UINT16[H]
+#define RSCAN0RFSTS6HL RSCAN0.RFSTS6.UINT8[HL]
+#define RSCAN0RFSTS6HH RSCAN0.RFSTS6.UINT8[HH]
+#define RSCAN0RFSTS7 RSCAN0.RFSTS7.UINT32
+#define RSCAN0RFSTS7L RSCAN0.RFSTS7.UINT16[L]
+#define RSCAN0RFSTS7LL RSCAN0.RFSTS7.UINT8[LL]
+#define RSCAN0RFSTS7LH RSCAN0.RFSTS7.UINT8[LH]
+#define RSCAN0RFSTS7H RSCAN0.RFSTS7.UINT16[H]
+#define RSCAN0RFSTS7HL RSCAN0.RFSTS7.UINT8[HL]
+#define RSCAN0RFSTS7HH RSCAN0.RFSTS7.UINT8[HH]
+#define RSCAN0RFPCTR0 RSCAN0.RFPCTR0.UINT32
+#define RSCAN0RFPCTR0L RSCAN0.RFPCTR0.UINT16[L]
+#define RSCAN0RFPCTR0LL RSCAN0.RFPCTR0.UINT8[LL]
+#define RSCAN0RFPCTR0LH RSCAN0.RFPCTR0.UINT8[LH]
+#define RSCAN0RFPCTR0H RSCAN0.RFPCTR0.UINT16[H]
+#define RSCAN0RFPCTR0HL RSCAN0.RFPCTR0.UINT8[HL]
+#define RSCAN0RFPCTR0HH RSCAN0.RFPCTR0.UINT8[HH]
+#define RSCAN0RFPCTR1 RSCAN0.RFPCTR1.UINT32
+#define RSCAN0RFPCTR1L RSCAN0.RFPCTR1.UINT16[L]
+#define RSCAN0RFPCTR1LL RSCAN0.RFPCTR1.UINT8[LL]
+#define RSCAN0RFPCTR1LH RSCAN0.RFPCTR1.UINT8[LH]
+#define RSCAN0RFPCTR1H RSCAN0.RFPCTR1.UINT16[H]
+#define RSCAN0RFPCTR1HL RSCAN0.RFPCTR1.UINT8[HL]
+#define RSCAN0RFPCTR1HH RSCAN0.RFPCTR1.UINT8[HH]
+#define RSCAN0RFPCTR2 RSCAN0.RFPCTR2.UINT32
+#define RSCAN0RFPCTR2L RSCAN0.RFPCTR2.UINT16[L]
+#define RSCAN0RFPCTR2LL RSCAN0.RFPCTR2.UINT8[LL]
+#define RSCAN0RFPCTR2LH RSCAN0.RFPCTR2.UINT8[LH]
+#define RSCAN0RFPCTR2H RSCAN0.RFPCTR2.UINT16[H]
+#define RSCAN0RFPCTR2HL RSCAN0.RFPCTR2.UINT8[HL]
+#define RSCAN0RFPCTR2HH RSCAN0.RFPCTR2.UINT8[HH]
+#define RSCAN0RFPCTR3 RSCAN0.RFPCTR3.UINT32
+#define RSCAN0RFPCTR3L RSCAN0.RFPCTR3.UINT16[L]
+#define RSCAN0RFPCTR3LL RSCAN0.RFPCTR3.UINT8[LL]
+#define RSCAN0RFPCTR3LH RSCAN0.RFPCTR3.UINT8[LH]
+#define RSCAN0RFPCTR3H RSCAN0.RFPCTR3.UINT16[H]
+#define RSCAN0RFPCTR3HL RSCAN0.RFPCTR3.UINT8[HL]
+#define RSCAN0RFPCTR3HH RSCAN0.RFPCTR3.UINT8[HH]
+#define RSCAN0RFPCTR4 RSCAN0.RFPCTR4.UINT32
+#define RSCAN0RFPCTR4L RSCAN0.RFPCTR4.UINT16[L]
+#define RSCAN0RFPCTR4LL RSCAN0.RFPCTR4.UINT8[LL]
+#define RSCAN0RFPCTR4LH RSCAN0.RFPCTR4.UINT8[LH]
+#define RSCAN0RFPCTR4H RSCAN0.RFPCTR4.UINT16[H]
+#define RSCAN0RFPCTR4HL RSCAN0.RFPCTR4.UINT8[HL]
+#define RSCAN0RFPCTR4HH RSCAN0.RFPCTR4.UINT8[HH]
+#define RSCAN0RFPCTR5 RSCAN0.RFPCTR5.UINT32
+#define RSCAN0RFPCTR5L RSCAN0.RFPCTR5.UINT16[L]
+#define RSCAN0RFPCTR5LL RSCAN0.RFPCTR5.UINT8[LL]
+#define RSCAN0RFPCTR5LH RSCAN0.RFPCTR5.UINT8[LH]
+#define RSCAN0RFPCTR5H RSCAN0.RFPCTR5.UINT16[H]
+#define RSCAN0RFPCTR5HL RSCAN0.RFPCTR5.UINT8[HL]
+#define RSCAN0RFPCTR5HH RSCAN0.RFPCTR5.UINT8[HH]
+#define RSCAN0RFPCTR6 RSCAN0.RFPCTR6.UINT32
+#define RSCAN0RFPCTR6L RSCAN0.RFPCTR6.UINT16[L]
+#define RSCAN0RFPCTR6LL RSCAN0.RFPCTR6.UINT8[LL]
+#define RSCAN0RFPCTR6LH RSCAN0.RFPCTR6.UINT8[LH]
+#define RSCAN0RFPCTR6H RSCAN0.RFPCTR6.UINT16[H]
+#define RSCAN0RFPCTR6HL RSCAN0.RFPCTR6.UINT8[HL]
+#define RSCAN0RFPCTR6HH RSCAN0.RFPCTR6.UINT8[HH]
+#define RSCAN0RFPCTR7 RSCAN0.RFPCTR7.UINT32
+#define RSCAN0RFPCTR7L RSCAN0.RFPCTR7.UINT16[L]
+#define RSCAN0RFPCTR7LL RSCAN0.RFPCTR7.UINT8[LL]
+#define RSCAN0RFPCTR7LH RSCAN0.RFPCTR7.UINT8[LH]
+#define RSCAN0RFPCTR7H RSCAN0.RFPCTR7.UINT16[H]
+#define RSCAN0RFPCTR7HL RSCAN0.RFPCTR7.UINT8[HL]
+#define RSCAN0RFPCTR7HH RSCAN0.RFPCTR7.UINT8[HH]
+#define RSCAN0CFCC0 RSCAN0.CFCC0.UINT32
+#define RSCAN0CFCC0L RSCAN0.CFCC0.UINT16[L]
+#define RSCAN0CFCC0LL RSCAN0.CFCC0.UINT8[LL]
+#define RSCAN0CFCC0LH RSCAN0.CFCC0.UINT8[LH]
+#define RSCAN0CFCC0H RSCAN0.CFCC0.UINT16[H]
+#define RSCAN0CFCC0HL RSCAN0.CFCC0.UINT8[HL]
+#define RSCAN0CFCC0HH RSCAN0.CFCC0.UINT8[HH]
+#define RSCAN0CFCC1 RSCAN0.CFCC1.UINT32
+#define RSCAN0CFCC1L RSCAN0.CFCC1.UINT16[L]
+#define RSCAN0CFCC1LL RSCAN0.CFCC1.UINT8[LL]
+#define RSCAN0CFCC1LH RSCAN0.CFCC1.UINT8[LH]
+#define RSCAN0CFCC1H RSCAN0.CFCC1.UINT16[H]
+#define RSCAN0CFCC1HL RSCAN0.CFCC1.UINT8[HL]
+#define RSCAN0CFCC1HH RSCAN0.CFCC1.UINT8[HH]
+#define RSCAN0CFCC2 RSCAN0.CFCC2.UINT32
+#define RSCAN0CFCC2L RSCAN0.CFCC2.UINT16[L]
+#define RSCAN0CFCC2LL RSCAN0.CFCC2.UINT8[LL]
+#define RSCAN0CFCC2LH RSCAN0.CFCC2.UINT8[LH]
+#define RSCAN0CFCC2H RSCAN0.CFCC2.UINT16[H]
+#define RSCAN0CFCC2HL RSCAN0.CFCC2.UINT8[HL]
+#define RSCAN0CFCC2HH RSCAN0.CFCC2.UINT8[HH]
+#define RSCAN0CFCC3 RSCAN0.CFCC3.UINT32
+#define RSCAN0CFCC3L RSCAN0.CFCC3.UINT16[L]
+#define RSCAN0CFCC3LL RSCAN0.CFCC3.UINT8[LL]
+#define RSCAN0CFCC3LH RSCAN0.CFCC3.UINT8[LH]
+#define RSCAN0CFCC3H RSCAN0.CFCC3.UINT16[H]
+#define RSCAN0CFCC3HL RSCAN0.CFCC3.UINT8[HL]
+#define RSCAN0CFCC3HH RSCAN0.CFCC3.UINT8[HH]
+#define RSCAN0CFCC4 RSCAN0.CFCC4.UINT32
+#define RSCAN0CFCC4L RSCAN0.CFCC4.UINT16[L]
+#define RSCAN0CFCC4LL RSCAN0.CFCC4.UINT8[LL]
+#define RSCAN0CFCC4LH RSCAN0.CFCC4.UINT8[LH]
+#define RSCAN0CFCC4H RSCAN0.CFCC4.UINT16[H]
+#define RSCAN0CFCC4HL RSCAN0.CFCC4.UINT8[HL]
+#define RSCAN0CFCC4HH RSCAN0.CFCC4.UINT8[HH]
+#define RSCAN0CFCC5 RSCAN0.CFCC5.UINT32
+#define RSCAN0CFCC5L RSCAN0.CFCC5.UINT16[L]
+#define RSCAN0CFCC5LL RSCAN0.CFCC5.UINT8[LL]
+#define RSCAN0CFCC5LH RSCAN0.CFCC5.UINT8[LH]
+#define RSCAN0CFCC5H RSCAN0.CFCC5.UINT16[H]
+#define RSCAN0CFCC5HL RSCAN0.CFCC5.UINT8[HL]
+#define RSCAN0CFCC5HH RSCAN0.CFCC5.UINT8[HH]
+#define RSCAN0CFCC6 RSCAN0.CFCC6.UINT32
+#define RSCAN0CFCC6L RSCAN0.CFCC6.UINT16[L]
+#define RSCAN0CFCC6LL RSCAN0.CFCC6.UINT8[LL]
+#define RSCAN0CFCC6LH RSCAN0.CFCC6.UINT8[LH]
+#define RSCAN0CFCC6H RSCAN0.CFCC6.UINT16[H]
+#define RSCAN0CFCC6HL RSCAN0.CFCC6.UINT8[HL]
+#define RSCAN0CFCC6HH RSCAN0.CFCC6.UINT8[HH]
+#define RSCAN0CFCC7 RSCAN0.CFCC7.UINT32
+#define RSCAN0CFCC7L RSCAN0.CFCC7.UINT16[L]
+#define RSCAN0CFCC7LL RSCAN0.CFCC7.UINT8[LL]
+#define RSCAN0CFCC7LH RSCAN0.CFCC7.UINT8[LH]
+#define RSCAN0CFCC7H RSCAN0.CFCC7.UINT16[H]
+#define RSCAN0CFCC7HL RSCAN0.CFCC7.UINT8[HL]
+#define RSCAN0CFCC7HH RSCAN0.CFCC7.UINT8[HH]
+#define RSCAN0CFCC8 RSCAN0.CFCC8.UINT32
+#define RSCAN0CFCC8L RSCAN0.CFCC8.UINT16[L]
+#define RSCAN0CFCC8LL RSCAN0.CFCC8.UINT8[LL]
+#define RSCAN0CFCC8LH RSCAN0.CFCC8.UINT8[LH]
+#define RSCAN0CFCC8H RSCAN0.CFCC8.UINT16[H]
+#define RSCAN0CFCC8HL RSCAN0.CFCC8.UINT8[HL]
+#define RSCAN0CFCC8HH RSCAN0.CFCC8.UINT8[HH]
+#define RSCAN0CFCC9 RSCAN0.CFCC9.UINT32
+#define RSCAN0CFCC9L RSCAN0.CFCC9.UINT16[L]
+#define RSCAN0CFCC9LL RSCAN0.CFCC9.UINT8[LL]
+#define RSCAN0CFCC9LH RSCAN0.CFCC9.UINT8[LH]
+#define RSCAN0CFCC9H RSCAN0.CFCC9.UINT16[H]
+#define RSCAN0CFCC9HL RSCAN0.CFCC9.UINT8[HL]
+#define RSCAN0CFCC9HH RSCAN0.CFCC9.UINT8[HH]
+#define RSCAN0CFCC10 RSCAN0.CFCC10.UINT32
+#define RSCAN0CFCC10L RSCAN0.CFCC10.UINT16[L]
+#define RSCAN0CFCC10LL RSCAN0.CFCC10.UINT8[LL]
+#define RSCAN0CFCC10LH RSCAN0.CFCC10.UINT8[LH]
+#define RSCAN0CFCC10H RSCAN0.CFCC10.UINT16[H]
+#define RSCAN0CFCC10HL RSCAN0.CFCC10.UINT8[HL]
+#define RSCAN0CFCC10HH RSCAN0.CFCC10.UINT8[HH]
+#define RSCAN0CFCC11 RSCAN0.CFCC11.UINT32
+#define RSCAN0CFCC11L RSCAN0.CFCC11.UINT16[L]
+#define RSCAN0CFCC11LL RSCAN0.CFCC11.UINT8[LL]
+#define RSCAN0CFCC11LH RSCAN0.CFCC11.UINT8[LH]
+#define RSCAN0CFCC11H RSCAN0.CFCC11.UINT16[H]
+#define RSCAN0CFCC11HL RSCAN0.CFCC11.UINT8[HL]
+#define RSCAN0CFCC11HH RSCAN0.CFCC11.UINT8[HH]
+#define RSCAN0CFCC12 RSCAN0.CFCC12.UINT32
+#define RSCAN0CFCC12L RSCAN0.CFCC12.UINT16[L]
+#define RSCAN0CFCC12LL RSCAN0.CFCC12.UINT8[LL]
+#define RSCAN0CFCC12LH RSCAN0.CFCC12.UINT8[LH]
+#define RSCAN0CFCC12H RSCAN0.CFCC12.UINT16[H]
+#define RSCAN0CFCC12HL RSCAN0.CFCC12.UINT8[HL]
+#define RSCAN0CFCC12HH RSCAN0.CFCC12.UINT8[HH]
+#define RSCAN0CFCC13 RSCAN0.CFCC13.UINT32
+#define RSCAN0CFCC13L RSCAN0.CFCC13.UINT16[L]
+#define RSCAN0CFCC13LL RSCAN0.CFCC13.UINT8[LL]
+#define RSCAN0CFCC13LH RSCAN0.CFCC13.UINT8[LH]
+#define RSCAN0CFCC13H RSCAN0.CFCC13.UINT16[H]
+#define RSCAN0CFCC13HL RSCAN0.CFCC13.UINT8[HL]
+#define RSCAN0CFCC13HH RSCAN0.CFCC13.UINT8[HH]
+#define RSCAN0CFCC14 RSCAN0.CFCC14.UINT32
+#define RSCAN0CFCC14L RSCAN0.CFCC14.UINT16[L]
+#define RSCAN0CFCC14LL RSCAN0.CFCC14.UINT8[LL]
+#define RSCAN0CFCC14LH RSCAN0.CFCC14.UINT8[LH]
+#define RSCAN0CFCC14H RSCAN0.CFCC14.UINT16[H]
+#define RSCAN0CFCC14HL RSCAN0.CFCC14.UINT8[HL]
+#define RSCAN0CFCC14HH RSCAN0.CFCC14.UINT8[HH]
+#define RSCAN0CFSTS0 RSCAN0.CFSTS0.UINT32
+#define RSCAN0CFSTS0L RSCAN0.CFSTS0.UINT16[L]
+#define RSCAN0CFSTS0LL RSCAN0.CFSTS0.UINT8[LL]
+#define RSCAN0CFSTS0LH RSCAN0.CFSTS0.UINT8[LH]
+#define RSCAN0CFSTS0H RSCAN0.CFSTS0.UINT16[H]
+#define RSCAN0CFSTS0HL RSCAN0.CFSTS0.UINT8[HL]
+#define RSCAN0CFSTS0HH RSCAN0.CFSTS0.UINT8[HH]
+#define RSCAN0CFSTS1 RSCAN0.CFSTS1.UINT32
+#define RSCAN0CFSTS1L RSCAN0.CFSTS1.UINT16[L]
+#define RSCAN0CFSTS1LL RSCAN0.CFSTS1.UINT8[LL]
+#define RSCAN0CFSTS1LH RSCAN0.CFSTS1.UINT8[LH]
+#define RSCAN0CFSTS1H RSCAN0.CFSTS1.UINT16[H]
+#define RSCAN0CFSTS1HL RSCAN0.CFSTS1.UINT8[HL]
+#define RSCAN0CFSTS1HH RSCAN0.CFSTS1.UINT8[HH]
+#define RSCAN0CFSTS2 RSCAN0.CFSTS2.UINT32
+#define RSCAN0CFSTS2L RSCAN0.CFSTS2.UINT16[L]
+#define RSCAN0CFSTS2LL RSCAN0.CFSTS2.UINT8[LL]
+#define RSCAN0CFSTS2LH RSCAN0.CFSTS2.UINT8[LH]
+#define RSCAN0CFSTS2H RSCAN0.CFSTS2.UINT16[H]
+#define RSCAN0CFSTS2HL RSCAN0.CFSTS2.UINT8[HL]
+#define RSCAN0CFSTS2HH RSCAN0.CFSTS2.UINT8[HH]
+#define RSCAN0CFSTS3 RSCAN0.CFSTS3.UINT32
+#define RSCAN0CFSTS3L RSCAN0.CFSTS3.UINT16[L]
+#define RSCAN0CFSTS3LL RSCAN0.CFSTS3.UINT8[LL]
+#define RSCAN0CFSTS3LH RSCAN0.CFSTS3.UINT8[LH]
+#define RSCAN0CFSTS3H RSCAN0.CFSTS3.UINT16[H]
+#define RSCAN0CFSTS3HL RSCAN0.CFSTS3.UINT8[HL]
+#define RSCAN0CFSTS3HH RSCAN0.CFSTS3.UINT8[HH]
+#define RSCAN0CFSTS4 RSCAN0.CFSTS4.UINT32
+#define RSCAN0CFSTS4L RSCAN0.CFSTS4.UINT16[L]
+#define RSCAN0CFSTS4LL RSCAN0.CFSTS4.UINT8[LL]
+#define RSCAN0CFSTS4LH RSCAN0.CFSTS4.UINT8[LH]
+#define RSCAN0CFSTS4H RSCAN0.CFSTS4.UINT16[H]
+#define RSCAN0CFSTS4HL RSCAN0.CFSTS4.UINT8[HL]
+#define RSCAN0CFSTS4HH RSCAN0.CFSTS4.UINT8[HH]
+#define RSCAN0CFSTS5 RSCAN0.CFSTS5.UINT32
+#define RSCAN0CFSTS5L RSCAN0.CFSTS5.UINT16[L]
+#define RSCAN0CFSTS5LL RSCAN0.CFSTS5.UINT8[LL]
+#define RSCAN0CFSTS5LH RSCAN0.CFSTS5.UINT8[LH]
+#define RSCAN0CFSTS5H RSCAN0.CFSTS5.UINT16[H]
+#define RSCAN0CFSTS5HL RSCAN0.CFSTS5.UINT8[HL]
+#define RSCAN0CFSTS5HH RSCAN0.CFSTS5.UINT8[HH]
+#define RSCAN0CFSTS6 RSCAN0.CFSTS6.UINT32
+#define RSCAN0CFSTS6L RSCAN0.CFSTS6.UINT16[L]
+#define RSCAN0CFSTS6LL RSCAN0.CFSTS6.UINT8[LL]
+#define RSCAN0CFSTS6LH RSCAN0.CFSTS6.UINT8[LH]
+#define RSCAN0CFSTS6H RSCAN0.CFSTS6.UINT16[H]
+#define RSCAN0CFSTS6HL RSCAN0.CFSTS6.UINT8[HL]
+#define RSCAN0CFSTS6HH RSCAN0.CFSTS6.UINT8[HH]
+#define RSCAN0CFSTS7 RSCAN0.CFSTS7.UINT32
+#define RSCAN0CFSTS7L RSCAN0.CFSTS7.UINT16[L]
+#define RSCAN0CFSTS7LL RSCAN0.CFSTS7.UINT8[LL]
+#define RSCAN0CFSTS7LH RSCAN0.CFSTS7.UINT8[LH]
+#define RSCAN0CFSTS7H RSCAN0.CFSTS7.UINT16[H]
+#define RSCAN0CFSTS7HL RSCAN0.CFSTS7.UINT8[HL]
+#define RSCAN0CFSTS7HH RSCAN0.CFSTS7.UINT8[HH]
+#define RSCAN0CFSTS8 RSCAN0.CFSTS8.UINT32
+#define RSCAN0CFSTS8L RSCAN0.CFSTS8.UINT16[L]
+#define RSCAN0CFSTS8LL RSCAN0.CFSTS8.UINT8[LL]
+#define RSCAN0CFSTS8LH RSCAN0.CFSTS8.UINT8[LH]
+#define RSCAN0CFSTS8H RSCAN0.CFSTS8.UINT16[H]
+#define RSCAN0CFSTS8HL RSCAN0.CFSTS8.UINT8[HL]
+#define RSCAN0CFSTS8HH RSCAN0.CFSTS8.UINT8[HH]
+#define RSCAN0CFSTS9 RSCAN0.CFSTS9.UINT32
+#define RSCAN0CFSTS9L RSCAN0.CFSTS9.UINT16[L]
+#define RSCAN0CFSTS9LL RSCAN0.CFSTS9.UINT8[LL]
+#define RSCAN0CFSTS9LH RSCAN0.CFSTS9.UINT8[LH]
+#define RSCAN0CFSTS9H RSCAN0.CFSTS9.UINT16[H]
+#define RSCAN0CFSTS9HL RSCAN0.CFSTS9.UINT8[HL]
+#define RSCAN0CFSTS9HH RSCAN0.CFSTS9.UINT8[HH]
+#define RSCAN0CFSTS10 RSCAN0.CFSTS10.UINT32
+#define RSCAN0CFSTS10L RSCAN0.CFSTS10.UINT16[L]
+#define RSCAN0CFSTS10LL RSCAN0.CFSTS10.UINT8[LL]
+#define RSCAN0CFSTS10LH RSCAN0.CFSTS10.UINT8[LH]
+#define RSCAN0CFSTS10H RSCAN0.CFSTS10.UINT16[H]
+#define RSCAN0CFSTS10HL RSCAN0.CFSTS10.UINT8[HL]
+#define RSCAN0CFSTS10HH RSCAN0.CFSTS10.UINT8[HH]
+#define RSCAN0CFSTS11 RSCAN0.CFSTS11.UINT32
+#define RSCAN0CFSTS11L RSCAN0.CFSTS11.UINT16[L]
+#define RSCAN0CFSTS11LL RSCAN0.CFSTS11.UINT8[LL]
+#define RSCAN0CFSTS11LH RSCAN0.CFSTS11.UINT8[LH]
+#define RSCAN0CFSTS11H RSCAN0.CFSTS11.UINT16[H]
+#define RSCAN0CFSTS11HL RSCAN0.CFSTS11.UINT8[HL]
+#define RSCAN0CFSTS11HH RSCAN0.CFSTS11.UINT8[HH]
+#define RSCAN0CFSTS12 RSCAN0.CFSTS12.UINT32
+#define RSCAN0CFSTS12L RSCAN0.CFSTS12.UINT16[L]
+#define RSCAN0CFSTS12LL RSCAN0.CFSTS12.UINT8[LL]
+#define RSCAN0CFSTS12LH RSCAN0.CFSTS12.UINT8[LH]
+#define RSCAN0CFSTS12H RSCAN0.CFSTS12.UINT16[H]
+#define RSCAN0CFSTS12HL RSCAN0.CFSTS12.UINT8[HL]
+#define RSCAN0CFSTS12HH RSCAN0.CFSTS12.UINT8[HH]
+#define RSCAN0CFSTS13 RSCAN0.CFSTS13.UINT32
+#define RSCAN0CFSTS13L RSCAN0.CFSTS13.UINT16[L]
+#define RSCAN0CFSTS13LL RSCAN0.CFSTS13.UINT8[LL]
+#define RSCAN0CFSTS13LH RSCAN0.CFSTS13.UINT8[LH]
+#define RSCAN0CFSTS13H RSCAN0.CFSTS13.UINT16[H]
+#define RSCAN0CFSTS13HL RSCAN0.CFSTS13.UINT8[HL]
+#define RSCAN0CFSTS13HH RSCAN0.CFSTS13.UINT8[HH]
+#define RSCAN0CFSTS14 RSCAN0.CFSTS14.UINT32
+#define RSCAN0CFSTS14L RSCAN0.CFSTS14.UINT16[L]
+#define RSCAN0CFSTS14LL RSCAN0.CFSTS14.UINT8[LL]
+#define RSCAN0CFSTS14LH RSCAN0.CFSTS14.UINT8[LH]
+#define RSCAN0CFSTS14H RSCAN0.CFSTS14.UINT16[H]
+#define RSCAN0CFSTS14HL RSCAN0.CFSTS14.UINT8[HL]
+#define RSCAN0CFSTS14HH RSCAN0.CFSTS14.UINT8[HH]
+#define RSCAN0CFPCTR0 RSCAN0.CFPCTR0.UINT32
+#define RSCAN0CFPCTR0L RSCAN0.CFPCTR0.UINT16[L]
+#define RSCAN0CFPCTR0LL RSCAN0.CFPCTR0.UINT8[LL]
+#define RSCAN0CFPCTR0LH RSCAN0.CFPCTR0.UINT8[LH]
+#define RSCAN0CFPCTR0H RSCAN0.CFPCTR0.UINT16[H]
+#define RSCAN0CFPCTR0HL RSCAN0.CFPCTR0.UINT8[HL]
+#define RSCAN0CFPCTR0HH RSCAN0.CFPCTR0.UINT8[HH]
+#define RSCAN0CFPCTR1 RSCAN0.CFPCTR1.UINT32
+#define RSCAN0CFPCTR1L RSCAN0.CFPCTR1.UINT16[L]
+#define RSCAN0CFPCTR1LL RSCAN0.CFPCTR1.UINT8[LL]
+#define RSCAN0CFPCTR1LH RSCAN0.CFPCTR1.UINT8[LH]
+#define RSCAN0CFPCTR1H RSCAN0.CFPCTR1.UINT16[H]
+#define RSCAN0CFPCTR1HL RSCAN0.CFPCTR1.UINT8[HL]
+#define RSCAN0CFPCTR1HH RSCAN0.CFPCTR1.UINT8[HH]
+#define RSCAN0CFPCTR2 RSCAN0.CFPCTR2.UINT32
+#define RSCAN0CFPCTR2L RSCAN0.CFPCTR2.UINT16[L]
+#define RSCAN0CFPCTR2LL RSCAN0.CFPCTR2.UINT8[LL]
+#define RSCAN0CFPCTR2LH RSCAN0.CFPCTR2.UINT8[LH]
+#define RSCAN0CFPCTR2H RSCAN0.CFPCTR2.UINT16[H]
+#define RSCAN0CFPCTR2HL RSCAN0.CFPCTR2.UINT8[HL]
+#define RSCAN0CFPCTR2HH RSCAN0.CFPCTR2.UINT8[HH]
+#define RSCAN0CFPCTR3 RSCAN0.CFPCTR3.UINT32
+#define RSCAN0CFPCTR3L RSCAN0.CFPCTR3.UINT16[L]
+#define RSCAN0CFPCTR3LL RSCAN0.CFPCTR3.UINT8[LL]
+#define RSCAN0CFPCTR3LH RSCAN0.CFPCTR3.UINT8[LH]
+#define RSCAN0CFPCTR3H RSCAN0.CFPCTR3.UINT16[H]
+#define RSCAN0CFPCTR3HL RSCAN0.CFPCTR3.UINT8[HL]
+#define RSCAN0CFPCTR3HH RSCAN0.CFPCTR3.UINT8[HH]
+#define RSCAN0CFPCTR4 RSCAN0.CFPCTR4.UINT32
+#define RSCAN0CFPCTR4L RSCAN0.CFPCTR4.UINT16[L]
+#define RSCAN0CFPCTR4LL RSCAN0.CFPCTR4.UINT8[LL]
+#define RSCAN0CFPCTR4LH RSCAN0.CFPCTR4.UINT8[LH]
+#define RSCAN0CFPCTR4H RSCAN0.CFPCTR4.UINT16[H]
+#define RSCAN0CFPCTR4HL RSCAN0.CFPCTR4.UINT8[HL]
+#define RSCAN0CFPCTR4HH RSCAN0.CFPCTR4.UINT8[HH]
+#define RSCAN0CFPCTR5 RSCAN0.CFPCTR5.UINT32
+#define RSCAN0CFPCTR5L RSCAN0.CFPCTR5.UINT16[L]
+#define RSCAN0CFPCTR5LL RSCAN0.CFPCTR5.UINT8[LL]
+#define RSCAN0CFPCTR5LH RSCAN0.CFPCTR5.UINT8[LH]
+#define RSCAN0CFPCTR5H RSCAN0.CFPCTR5.UINT16[H]
+#define RSCAN0CFPCTR5HL RSCAN0.CFPCTR5.UINT8[HL]
+#define RSCAN0CFPCTR5HH RSCAN0.CFPCTR5.UINT8[HH]
+#define RSCAN0CFPCTR6 RSCAN0.CFPCTR6.UINT32
+#define RSCAN0CFPCTR6L RSCAN0.CFPCTR6.UINT16[L]
+#define RSCAN0CFPCTR6LL RSCAN0.CFPCTR6.UINT8[LL]
+#define RSCAN0CFPCTR6LH RSCAN0.CFPCTR6.UINT8[LH]
+#define RSCAN0CFPCTR6H RSCAN0.CFPCTR6.UINT16[H]
+#define RSCAN0CFPCTR6HL RSCAN0.CFPCTR6.UINT8[HL]
+#define RSCAN0CFPCTR6HH RSCAN0.CFPCTR6.UINT8[HH]
+#define RSCAN0CFPCTR7 RSCAN0.CFPCTR7.UINT32
+#define RSCAN0CFPCTR7L RSCAN0.CFPCTR7.UINT16[L]
+#define RSCAN0CFPCTR7LL RSCAN0.CFPCTR7.UINT8[LL]
+#define RSCAN0CFPCTR7LH RSCAN0.CFPCTR7.UINT8[LH]
+#define RSCAN0CFPCTR7H RSCAN0.CFPCTR7.UINT16[H]
+#define RSCAN0CFPCTR7HL RSCAN0.CFPCTR7.UINT8[HL]
+#define RSCAN0CFPCTR7HH RSCAN0.CFPCTR7.UINT8[HH]
+#define RSCAN0CFPCTR8 RSCAN0.CFPCTR8.UINT32
+#define RSCAN0CFPCTR8L RSCAN0.CFPCTR8.UINT16[L]
+#define RSCAN0CFPCTR8LL RSCAN0.CFPCTR8.UINT8[LL]
+#define RSCAN0CFPCTR8LH RSCAN0.CFPCTR8.UINT8[LH]
+#define RSCAN0CFPCTR8H RSCAN0.CFPCTR8.UINT16[H]
+#define RSCAN0CFPCTR8HL RSCAN0.CFPCTR8.UINT8[HL]
+#define RSCAN0CFPCTR8HH RSCAN0.CFPCTR8.UINT8[HH]
+#define RSCAN0CFPCTR9 RSCAN0.CFPCTR9.UINT32
+#define RSCAN0CFPCTR9L RSCAN0.CFPCTR9.UINT16[L]
+#define RSCAN0CFPCTR9LL RSCAN0.CFPCTR9.UINT8[LL]
+#define RSCAN0CFPCTR9LH RSCAN0.CFPCTR9.UINT8[LH]
+#define RSCAN0CFPCTR9H RSCAN0.CFPCTR9.UINT16[H]
+#define RSCAN0CFPCTR9HL RSCAN0.CFPCTR9.UINT8[HL]
+#define RSCAN0CFPCTR9HH RSCAN0.CFPCTR9.UINT8[HH]
+#define RSCAN0CFPCTR10 RSCAN0.CFPCTR10.UINT32
+#define RSCAN0CFPCTR10L RSCAN0.CFPCTR10.UINT16[L]
+#define RSCAN0CFPCTR10LL RSCAN0.CFPCTR10.UINT8[LL]
+#define RSCAN0CFPCTR10LH RSCAN0.CFPCTR10.UINT8[LH]
+#define RSCAN0CFPCTR10H RSCAN0.CFPCTR10.UINT16[H]
+#define RSCAN0CFPCTR10HL RSCAN0.CFPCTR10.UINT8[HL]
+#define RSCAN0CFPCTR10HH RSCAN0.CFPCTR10.UINT8[HH]
+#define RSCAN0CFPCTR11 RSCAN0.CFPCTR11.UINT32
+#define RSCAN0CFPCTR11L RSCAN0.CFPCTR11.UINT16[L]
+#define RSCAN0CFPCTR11LL RSCAN0.CFPCTR11.UINT8[LL]
+#define RSCAN0CFPCTR11LH RSCAN0.CFPCTR11.UINT8[LH]
+#define RSCAN0CFPCTR11H RSCAN0.CFPCTR11.UINT16[H]
+#define RSCAN0CFPCTR11HL RSCAN0.CFPCTR11.UINT8[HL]
+#define RSCAN0CFPCTR11HH RSCAN0.CFPCTR11.UINT8[HH]
+#define RSCAN0CFPCTR12 RSCAN0.CFPCTR12.UINT32
+#define RSCAN0CFPCTR12L RSCAN0.CFPCTR12.UINT16[L]
+#define RSCAN0CFPCTR12LL RSCAN0.CFPCTR12.UINT8[LL]
+#define RSCAN0CFPCTR12LH RSCAN0.CFPCTR12.UINT8[LH]
+#define RSCAN0CFPCTR12H RSCAN0.CFPCTR12.UINT16[H]
+#define RSCAN0CFPCTR12HL RSCAN0.CFPCTR12.UINT8[HL]
+#define RSCAN0CFPCTR12HH RSCAN0.CFPCTR12.UINT8[HH]
+#define RSCAN0CFPCTR13 RSCAN0.CFPCTR13.UINT32
+#define RSCAN0CFPCTR13L RSCAN0.CFPCTR13.UINT16[L]
+#define RSCAN0CFPCTR13LL RSCAN0.CFPCTR13.UINT8[LL]
+#define RSCAN0CFPCTR13LH RSCAN0.CFPCTR13.UINT8[LH]
+#define RSCAN0CFPCTR13H RSCAN0.CFPCTR13.UINT16[H]
+#define RSCAN0CFPCTR13HL RSCAN0.CFPCTR13.UINT8[HL]
+#define RSCAN0CFPCTR13HH RSCAN0.CFPCTR13.UINT8[HH]
+#define RSCAN0CFPCTR14 RSCAN0.CFPCTR14.UINT32
+#define RSCAN0CFPCTR14L RSCAN0.CFPCTR14.UINT16[L]
+#define RSCAN0CFPCTR14LL RSCAN0.CFPCTR14.UINT8[LL]
+#define RSCAN0CFPCTR14LH RSCAN0.CFPCTR14.UINT8[LH]
+#define RSCAN0CFPCTR14H RSCAN0.CFPCTR14.UINT16[H]
+#define RSCAN0CFPCTR14HL RSCAN0.CFPCTR14.UINT8[HL]
+#define RSCAN0CFPCTR14HH RSCAN0.CFPCTR14.UINT8[HH]
+#define RSCAN0FESTS RSCAN0.FESTS.UINT32
+#define RSCAN0FESTSL RSCAN0.FESTS.UINT16[L]
+#define RSCAN0FESTSLL RSCAN0.FESTS.UINT8[LL]
+#define RSCAN0FESTSLH RSCAN0.FESTS.UINT8[LH]
+#define RSCAN0FESTSH RSCAN0.FESTS.UINT16[H]
+#define RSCAN0FESTSHL RSCAN0.FESTS.UINT8[HL]
+#define RSCAN0FESTSHH RSCAN0.FESTS.UINT8[HH]
+#define RSCAN0FFSTS RSCAN0.FFSTS.UINT32
+#define RSCAN0FFSTSL RSCAN0.FFSTS.UINT16[L]
+#define RSCAN0FFSTSLL RSCAN0.FFSTS.UINT8[LL]
+#define RSCAN0FFSTSLH RSCAN0.FFSTS.UINT8[LH]
+#define RSCAN0FFSTSH RSCAN0.FFSTS.UINT16[H]
+#define RSCAN0FFSTSHL RSCAN0.FFSTS.UINT8[HL]
+#define RSCAN0FFSTSHH RSCAN0.FFSTS.UINT8[HH]
+#define RSCAN0FMSTS RSCAN0.FMSTS.UINT32
+#define RSCAN0FMSTSL RSCAN0.FMSTS.UINT16[L]
+#define RSCAN0FMSTSLL RSCAN0.FMSTS.UINT8[LL]
+#define RSCAN0FMSTSLH RSCAN0.FMSTS.UINT8[LH]
+#define RSCAN0FMSTSH RSCAN0.FMSTS.UINT16[H]
+#define RSCAN0FMSTSHL RSCAN0.FMSTS.UINT8[HL]
+#define RSCAN0FMSTSHH RSCAN0.FMSTS.UINT8[HH]
+#define RSCAN0RFISTS RSCAN0.RFISTS.UINT32
+#define RSCAN0RFISTSL RSCAN0.RFISTS.UINT16[L]
+#define RSCAN0RFISTSLL RSCAN0.RFISTS.UINT8[LL]
+#define RSCAN0RFISTSLH RSCAN0.RFISTS.UINT8[LH]
+#define RSCAN0RFISTSH RSCAN0.RFISTS.UINT16[H]
+#define RSCAN0RFISTSHL RSCAN0.RFISTS.UINT8[HL]
+#define RSCAN0RFISTSHH RSCAN0.RFISTS.UINT8[HH]
+#define RSCAN0CFRISTS RSCAN0.CFRISTS.UINT32
+#define RSCAN0CFRISTSL RSCAN0.CFRISTS.UINT16[L]
+#define RSCAN0CFRISTSLL RSCAN0.CFRISTS.UINT8[LL]
+#define RSCAN0CFRISTSLH RSCAN0.CFRISTS.UINT8[LH]
+#define RSCAN0CFRISTSH RSCAN0.CFRISTS.UINT16[H]
+#define RSCAN0CFRISTSHL RSCAN0.CFRISTS.UINT8[HL]
+#define RSCAN0CFRISTSHH RSCAN0.CFRISTS.UINT8[HH]
+#define RSCAN0CFTISTS RSCAN0.CFTISTS.UINT32
+#define RSCAN0CFTISTSL RSCAN0.CFTISTS.UINT16[L]
+#define RSCAN0CFTISTSLL RSCAN0.CFTISTS.UINT8[LL]
+#define RSCAN0CFTISTSLH RSCAN0.CFTISTS.UINT8[LH]
+#define RSCAN0CFTISTSH RSCAN0.CFTISTS.UINT16[H]
+#define RSCAN0CFTISTSHL RSCAN0.CFTISTS.UINT8[HL]
+#define RSCAN0CFTISTSHH RSCAN0.CFTISTS.UINT8[HH]
+#define RSCAN0TMC0 RSCAN0.TMC0
+#define RSCAN0TMC1 RSCAN0.TMC1
+#define RSCAN0TMC2 RSCAN0.TMC2
+#define RSCAN0TMC3 RSCAN0.TMC3
+#define RSCAN0TMC4 RSCAN0.TMC4
+#define RSCAN0TMC5 RSCAN0.TMC5
+#define RSCAN0TMC6 RSCAN0.TMC6
+#define RSCAN0TMC7 RSCAN0.TMC7
+#define RSCAN0TMC8 RSCAN0.TMC8
+#define RSCAN0TMC9 RSCAN0.TMC9
+#define RSCAN0TMC10 RSCAN0.TMC10
+#define RSCAN0TMC11 RSCAN0.TMC11
+#define RSCAN0TMC12 RSCAN0.TMC12
+#define RSCAN0TMC13 RSCAN0.TMC13
+#define RSCAN0TMC14 RSCAN0.TMC14
+#define RSCAN0TMC15 RSCAN0.TMC15
+#define RSCAN0TMC16 RSCAN0.TMC16
+#define RSCAN0TMC17 RSCAN0.TMC17
+#define RSCAN0TMC18 RSCAN0.TMC18
+#define RSCAN0TMC19 RSCAN0.TMC19
+#define RSCAN0TMC20 RSCAN0.TMC20
+#define RSCAN0TMC21 RSCAN0.TMC21
+#define RSCAN0TMC22 RSCAN0.TMC22
+#define RSCAN0TMC23 RSCAN0.TMC23
+#define RSCAN0TMC24 RSCAN0.TMC24
+#define RSCAN0TMC25 RSCAN0.TMC25
+#define RSCAN0TMC26 RSCAN0.TMC26
+#define RSCAN0TMC27 RSCAN0.TMC27
+#define RSCAN0TMC28 RSCAN0.TMC28
+#define RSCAN0TMC29 RSCAN0.TMC29
+#define RSCAN0TMC30 RSCAN0.TMC30
+#define RSCAN0TMC31 RSCAN0.TMC31
+#define RSCAN0TMC32 RSCAN0.TMC32
+#define RSCAN0TMC33 RSCAN0.TMC33
+#define RSCAN0TMC34 RSCAN0.TMC34
+#define RSCAN0TMC35 RSCAN0.TMC35
+#define RSCAN0TMC36 RSCAN0.TMC36
+#define RSCAN0TMC37 RSCAN0.TMC37
+#define RSCAN0TMC38 RSCAN0.TMC38
+#define RSCAN0TMC39 RSCAN0.TMC39
+#define RSCAN0TMC40 RSCAN0.TMC40
+#define RSCAN0TMC41 RSCAN0.TMC41
+#define RSCAN0TMC42 RSCAN0.TMC42
+#define RSCAN0TMC43 RSCAN0.TMC43
+#define RSCAN0TMC44 RSCAN0.TMC44
+#define RSCAN0TMC45 RSCAN0.TMC45
+#define RSCAN0TMC46 RSCAN0.TMC46
+#define RSCAN0TMC47 RSCAN0.TMC47
+#define RSCAN0TMC48 RSCAN0.TMC48
+#define RSCAN0TMC49 RSCAN0.TMC49
+#define RSCAN0TMC50 RSCAN0.TMC50
+#define RSCAN0TMC51 RSCAN0.TMC51
+#define RSCAN0TMC52 RSCAN0.TMC52
+#define RSCAN0TMC53 RSCAN0.TMC53
+#define RSCAN0TMC54 RSCAN0.TMC54
+#define RSCAN0TMC55 RSCAN0.TMC55
+#define RSCAN0TMC56 RSCAN0.TMC56
+#define RSCAN0TMC57 RSCAN0.TMC57
+#define RSCAN0TMC58 RSCAN0.TMC58
+#define RSCAN0TMC59 RSCAN0.TMC59
+#define RSCAN0TMC60 RSCAN0.TMC60
+#define RSCAN0TMC61 RSCAN0.TMC61
+#define RSCAN0TMC62 RSCAN0.TMC62
+#define RSCAN0TMC63 RSCAN0.TMC63
+#define RSCAN0TMC64 RSCAN0.TMC64
+#define RSCAN0TMC65 RSCAN0.TMC65
+#define RSCAN0TMC66 RSCAN0.TMC66
+#define RSCAN0TMC67 RSCAN0.TMC67
+#define RSCAN0TMC68 RSCAN0.TMC68
+#define RSCAN0TMC69 RSCAN0.TMC69
+#define RSCAN0TMC70 RSCAN0.TMC70
+#define RSCAN0TMC71 RSCAN0.TMC71
+#define RSCAN0TMC72 RSCAN0.TMC72
+#define RSCAN0TMC73 RSCAN0.TMC73
+#define RSCAN0TMC74 RSCAN0.TMC74
+#define RSCAN0TMC75 RSCAN0.TMC75
+#define RSCAN0TMC76 RSCAN0.TMC76
+#define RSCAN0TMC77 RSCAN0.TMC77
+#define RSCAN0TMC78 RSCAN0.TMC78
+#define RSCAN0TMC79 RSCAN0.TMC79
+#define RSCAN0TMSTS0 RSCAN0.TMSTS0
+#define RSCAN0TMSTS1 RSCAN0.TMSTS1
+#define RSCAN0TMSTS2 RSCAN0.TMSTS2
+#define RSCAN0TMSTS3 RSCAN0.TMSTS3
+#define RSCAN0TMSTS4 RSCAN0.TMSTS4
+#define RSCAN0TMSTS5 RSCAN0.TMSTS5
+#define RSCAN0TMSTS6 RSCAN0.TMSTS6
+#define RSCAN0TMSTS7 RSCAN0.TMSTS7
+#define RSCAN0TMSTS8 RSCAN0.TMSTS8
+#define RSCAN0TMSTS9 RSCAN0.TMSTS9
+#define RSCAN0TMSTS10 RSCAN0.TMSTS10
+#define RSCAN0TMSTS11 RSCAN0.TMSTS11
+#define RSCAN0TMSTS12 RSCAN0.TMSTS12
+#define RSCAN0TMSTS13 RSCAN0.TMSTS13
+#define RSCAN0TMSTS14 RSCAN0.TMSTS14
+#define RSCAN0TMSTS15 RSCAN0.TMSTS15
+#define RSCAN0TMSTS16 RSCAN0.TMSTS16
+#define RSCAN0TMSTS17 RSCAN0.TMSTS17
+#define RSCAN0TMSTS18 RSCAN0.TMSTS18
+#define RSCAN0TMSTS19 RSCAN0.TMSTS19
+#define RSCAN0TMSTS20 RSCAN0.TMSTS20
+#define RSCAN0TMSTS21 RSCAN0.TMSTS21
+#define RSCAN0TMSTS22 RSCAN0.TMSTS22
+#define RSCAN0TMSTS23 RSCAN0.TMSTS23
+#define RSCAN0TMSTS24 RSCAN0.TMSTS24
+#define RSCAN0TMSTS25 RSCAN0.TMSTS25
+#define RSCAN0TMSTS26 RSCAN0.TMSTS26
+#define RSCAN0TMSTS27 RSCAN0.TMSTS27
+#define RSCAN0TMSTS28 RSCAN0.TMSTS28
+#define RSCAN0TMSTS29 RSCAN0.TMSTS29
+#define RSCAN0TMSTS30 RSCAN0.TMSTS30
+#define RSCAN0TMSTS31 RSCAN0.TMSTS31
+#define RSCAN0TMSTS32 RSCAN0.TMSTS32
+#define RSCAN0TMSTS33 RSCAN0.TMSTS33
+#define RSCAN0TMSTS34 RSCAN0.TMSTS34
+#define RSCAN0TMSTS35 RSCAN0.TMSTS35
+#define RSCAN0TMSTS36 RSCAN0.TMSTS36
+#define RSCAN0TMSTS37 RSCAN0.TMSTS37
+#define RSCAN0TMSTS38 RSCAN0.TMSTS38
+#define RSCAN0TMSTS39 RSCAN0.TMSTS39
+#define RSCAN0TMSTS40 RSCAN0.TMSTS40
+#define RSCAN0TMSTS41 RSCAN0.TMSTS41
+#define RSCAN0TMSTS42 RSCAN0.TMSTS42
+#define RSCAN0TMSTS43 RSCAN0.TMSTS43
+#define RSCAN0TMSTS44 RSCAN0.TMSTS44
+#define RSCAN0TMSTS45 RSCAN0.TMSTS45
+#define RSCAN0TMSTS46 RSCAN0.TMSTS46
+#define RSCAN0TMSTS47 RSCAN0.TMSTS47
+#define RSCAN0TMSTS48 RSCAN0.TMSTS48
+#define RSCAN0TMSTS49 RSCAN0.TMSTS49
+#define RSCAN0TMSTS50 RSCAN0.TMSTS50
+#define RSCAN0TMSTS51 RSCAN0.TMSTS51
+#define RSCAN0TMSTS52 RSCAN0.TMSTS52
+#define RSCAN0TMSTS53 RSCAN0.TMSTS53
+#define RSCAN0TMSTS54 RSCAN0.TMSTS54
+#define RSCAN0TMSTS55 RSCAN0.TMSTS55
+#define RSCAN0TMSTS56 RSCAN0.TMSTS56
+#define RSCAN0TMSTS57 RSCAN0.TMSTS57
+#define RSCAN0TMSTS58 RSCAN0.TMSTS58
+#define RSCAN0TMSTS59 RSCAN0.TMSTS59
+#define RSCAN0TMSTS60 RSCAN0.TMSTS60
+#define RSCAN0TMSTS61 RSCAN0.TMSTS61
+#define RSCAN0TMSTS62 RSCAN0.TMSTS62
+#define RSCAN0TMSTS63 RSCAN0.TMSTS63
+#define RSCAN0TMSTS64 RSCAN0.TMSTS64
+#define RSCAN0TMSTS65 RSCAN0.TMSTS65
+#define RSCAN0TMSTS66 RSCAN0.TMSTS66
+#define RSCAN0TMSTS67 RSCAN0.TMSTS67
+#define RSCAN0TMSTS68 RSCAN0.TMSTS68
+#define RSCAN0TMSTS69 RSCAN0.TMSTS69
+#define RSCAN0TMSTS70 RSCAN0.TMSTS70
+#define RSCAN0TMSTS71 RSCAN0.TMSTS71
+#define RSCAN0TMSTS72 RSCAN0.TMSTS72
+#define RSCAN0TMSTS73 RSCAN0.TMSTS73
+#define RSCAN0TMSTS74 RSCAN0.TMSTS74
+#define RSCAN0TMSTS75 RSCAN0.TMSTS75
+#define RSCAN0TMSTS76 RSCAN0.TMSTS76
+#define RSCAN0TMSTS77 RSCAN0.TMSTS77
+#define RSCAN0TMSTS78 RSCAN0.TMSTS78
+#define RSCAN0TMSTS79 RSCAN0.TMSTS79
+#define RSCAN0TMTRSTS0 RSCAN0.TMTRSTS0.UINT32
+#define RSCAN0TMTRSTS0L RSCAN0.TMTRSTS0.UINT16[L]
+#define RSCAN0TMTRSTS0LL RSCAN0.TMTRSTS0.UINT8[LL]
+#define RSCAN0TMTRSTS0LH RSCAN0.TMTRSTS0.UINT8[LH]
+#define RSCAN0TMTRSTS0H RSCAN0.TMTRSTS0.UINT16[H]
+#define RSCAN0TMTRSTS0HL RSCAN0.TMTRSTS0.UINT8[HL]
+#define RSCAN0TMTRSTS0HH RSCAN0.TMTRSTS0.UINT8[HH]
+#define RSCAN0TMTRSTS1 RSCAN0.TMTRSTS1.UINT32
+#define RSCAN0TMTRSTS1L RSCAN0.TMTRSTS1.UINT16[L]
+#define RSCAN0TMTRSTS1LL RSCAN0.TMTRSTS1.UINT8[LL]
+#define RSCAN0TMTRSTS1LH RSCAN0.TMTRSTS1.UINT8[LH]
+#define RSCAN0TMTRSTS1H RSCAN0.TMTRSTS1.UINT16[H]
+#define RSCAN0TMTRSTS1HL RSCAN0.TMTRSTS1.UINT8[HL]
+#define RSCAN0TMTRSTS1HH RSCAN0.TMTRSTS1.UINT8[HH]
+#define RSCAN0TMTRSTS2 RSCAN0.TMTRSTS2.UINT32
+#define RSCAN0TMTRSTS2L RSCAN0.TMTRSTS2.UINT16[L]
+#define RSCAN0TMTRSTS2LL RSCAN0.TMTRSTS2.UINT8[LL]
+#define RSCAN0TMTRSTS2LH RSCAN0.TMTRSTS2.UINT8[LH]
+#define RSCAN0TMTRSTS2H RSCAN0.TMTRSTS2.UINT16[H]
+#define RSCAN0TMTRSTS2HL RSCAN0.TMTRSTS2.UINT8[HL]
+#define RSCAN0TMTRSTS2HH RSCAN0.TMTRSTS2.UINT8[HH]
+#define RSCAN0TMTARSTS0 RSCAN0.TMTARSTS0.UINT32
+#define RSCAN0TMTARSTS0L RSCAN0.TMTARSTS0.UINT16[L]
+#define RSCAN0TMTARSTS0LL RSCAN0.TMTARSTS0.UINT8[LL]
+#define RSCAN0TMTARSTS0LH RSCAN0.TMTARSTS0.UINT8[LH]
+#define RSCAN0TMTARSTS0H RSCAN0.TMTARSTS0.UINT16[H]
+#define RSCAN0TMTARSTS0HL RSCAN0.TMTARSTS0.UINT8[HL]
+#define RSCAN0TMTARSTS0HH RSCAN0.TMTARSTS0.UINT8[HH]
+#define RSCAN0TMTARSTS1 RSCAN0.TMTARSTS1.UINT32
+#define RSCAN0TMTARSTS1L RSCAN0.TMTARSTS1.UINT16[L]
+#define RSCAN0TMTARSTS1LL RSCAN0.TMTARSTS1.UINT8[LL]
+#define RSCAN0TMTARSTS1LH RSCAN0.TMTARSTS1.UINT8[LH]
+#define RSCAN0TMTARSTS1H RSCAN0.TMTARSTS1.UINT16[H]
+#define RSCAN0TMTARSTS1HL RSCAN0.TMTARSTS1.UINT8[HL]
+#define RSCAN0TMTARSTS1HH RSCAN0.TMTARSTS1.UINT8[HH]
+#define RSCAN0TMTARSTS2 RSCAN0.TMTARSTS2.UINT32
+#define RSCAN0TMTARSTS2L RSCAN0.TMTARSTS2.UINT16[L]
+#define RSCAN0TMTARSTS2LL RSCAN0.TMTARSTS2.UINT8[LL]
+#define RSCAN0TMTARSTS2LH RSCAN0.TMTARSTS2.UINT8[LH]
+#define RSCAN0TMTARSTS2H RSCAN0.TMTARSTS2.UINT16[H]
+#define RSCAN0TMTARSTS2HL RSCAN0.TMTARSTS2.UINT8[HL]
+#define RSCAN0TMTARSTS2HH RSCAN0.TMTARSTS2.UINT8[HH]
+#define RSCAN0TMTCSTS0 RSCAN0.TMTCSTS0.UINT32
+#define RSCAN0TMTCSTS0L RSCAN0.TMTCSTS0.UINT16[L]
+#define RSCAN0TMTCSTS0LL RSCAN0.TMTCSTS0.UINT8[LL]
+#define RSCAN0TMTCSTS0LH RSCAN0.TMTCSTS0.UINT8[LH]
+#define RSCAN0TMTCSTS0H RSCAN0.TMTCSTS0.UINT16[H]
+#define RSCAN0TMTCSTS0HL RSCAN0.TMTCSTS0.UINT8[HL]
+#define RSCAN0TMTCSTS0HH RSCAN0.TMTCSTS0.UINT8[HH]
+#define RSCAN0TMTCSTS1 RSCAN0.TMTCSTS1.UINT32
+#define RSCAN0TMTCSTS1L RSCAN0.TMTCSTS1.UINT16[L]
+#define RSCAN0TMTCSTS1LL RSCAN0.TMTCSTS1.UINT8[LL]
+#define RSCAN0TMTCSTS1LH RSCAN0.TMTCSTS1.UINT8[LH]
+#define RSCAN0TMTCSTS1H RSCAN0.TMTCSTS1.UINT16[H]
+#define RSCAN0TMTCSTS1HL RSCAN0.TMTCSTS1.UINT8[HL]
+#define RSCAN0TMTCSTS1HH RSCAN0.TMTCSTS1.UINT8[HH]
+#define RSCAN0TMTCSTS2 RSCAN0.TMTCSTS2.UINT32
+#define RSCAN0TMTCSTS2L RSCAN0.TMTCSTS2.UINT16[L]
+#define RSCAN0TMTCSTS2LL RSCAN0.TMTCSTS2.UINT8[LL]
+#define RSCAN0TMTCSTS2LH RSCAN0.TMTCSTS2.UINT8[LH]
+#define RSCAN0TMTCSTS2H RSCAN0.TMTCSTS2.UINT16[H]
+#define RSCAN0TMTCSTS2HL RSCAN0.TMTCSTS2.UINT8[HL]
+#define RSCAN0TMTCSTS2HH RSCAN0.TMTCSTS2.UINT8[HH]
+#define RSCAN0TMTASTS0 RSCAN0.TMTASTS0.UINT32
+#define RSCAN0TMTASTS0L RSCAN0.TMTASTS0.UINT16[L]
+#define RSCAN0TMTASTS0LL RSCAN0.TMTASTS0.UINT8[LL]
+#define RSCAN0TMTASTS0LH RSCAN0.TMTASTS0.UINT8[LH]
+#define RSCAN0TMTASTS0H RSCAN0.TMTASTS0.UINT16[H]
+#define RSCAN0TMTASTS0HL RSCAN0.TMTASTS0.UINT8[HL]
+#define RSCAN0TMTASTS0HH RSCAN0.TMTASTS0.UINT8[HH]
+#define RSCAN0TMTASTS1 RSCAN0.TMTASTS1.UINT32
+#define RSCAN0TMTASTS1L RSCAN0.TMTASTS1.UINT16[L]
+#define RSCAN0TMTASTS1LL RSCAN0.TMTASTS1.UINT8[LL]
+#define RSCAN0TMTASTS1LH RSCAN0.TMTASTS1.UINT8[LH]
+#define RSCAN0TMTASTS1H RSCAN0.TMTASTS1.UINT16[H]
+#define RSCAN0TMTASTS1HL RSCAN0.TMTASTS1.UINT8[HL]
+#define RSCAN0TMTASTS1HH RSCAN0.TMTASTS1.UINT8[HH]
+#define RSCAN0TMTASTS2 RSCAN0.TMTASTS2.UINT32
+#define RSCAN0TMTASTS2L RSCAN0.TMTASTS2.UINT16[L]
+#define RSCAN0TMTASTS2LL RSCAN0.TMTASTS2.UINT8[LL]
+#define RSCAN0TMTASTS2LH RSCAN0.TMTASTS2.UINT8[LH]
+#define RSCAN0TMTASTS2H RSCAN0.TMTASTS2.UINT16[H]
+#define RSCAN0TMTASTS2HL RSCAN0.TMTASTS2.UINT8[HL]
+#define RSCAN0TMTASTS2HH RSCAN0.TMTASTS2.UINT8[HH]
+#define RSCAN0TMIEC0 RSCAN0.TMIEC0.UINT32
+#define RSCAN0TMIEC0L RSCAN0.TMIEC0.UINT16[L]
+#define RSCAN0TMIEC0LL RSCAN0.TMIEC0.UINT8[LL]
+#define RSCAN0TMIEC0LH RSCAN0.TMIEC0.UINT8[LH]
+#define RSCAN0TMIEC0H RSCAN0.TMIEC0.UINT16[H]
+#define RSCAN0TMIEC0HL RSCAN0.TMIEC0.UINT8[HL]
+#define RSCAN0TMIEC0HH RSCAN0.TMIEC0.UINT8[HH]
+#define RSCAN0TMIEC1 RSCAN0.TMIEC1.UINT32
+#define RSCAN0TMIEC1L RSCAN0.TMIEC1.UINT16[L]
+#define RSCAN0TMIEC1LL RSCAN0.TMIEC1.UINT8[LL]
+#define RSCAN0TMIEC1LH RSCAN0.TMIEC1.UINT8[LH]
+#define RSCAN0TMIEC1H RSCAN0.TMIEC1.UINT16[H]
+#define RSCAN0TMIEC1HL RSCAN0.TMIEC1.UINT8[HL]
+#define RSCAN0TMIEC1HH RSCAN0.TMIEC1.UINT8[HH]
+#define RSCAN0TMIEC2 RSCAN0.TMIEC2.UINT32
+#define RSCAN0TMIEC2L RSCAN0.TMIEC2.UINT16[L]
+#define RSCAN0TMIEC2LL RSCAN0.TMIEC2.UINT8[LL]
+#define RSCAN0TMIEC2LH RSCAN0.TMIEC2.UINT8[LH]
+#define RSCAN0TMIEC2H RSCAN0.TMIEC2.UINT16[H]
+#define RSCAN0TMIEC2HL RSCAN0.TMIEC2.UINT8[HL]
+#define RSCAN0TMIEC2HH RSCAN0.TMIEC2.UINT8[HH]
+#define RSCAN0TXQCC0 RSCAN0.TXQCC0.UINT32
+#define RSCAN0TXQCC0L RSCAN0.TXQCC0.UINT16[L]
+#define RSCAN0TXQCC0LL RSCAN0.TXQCC0.UINT8[LL]
+#define RSCAN0TXQCC0LH RSCAN0.TXQCC0.UINT8[LH]
+#define RSCAN0TXQCC0H RSCAN0.TXQCC0.UINT16[H]
+#define RSCAN0TXQCC0HL RSCAN0.TXQCC0.UINT8[HL]
+#define RSCAN0TXQCC0HH RSCAN0.TXQCC0.UINT8[HH]
+#define RSCAN0TXQCC1 RSCAN0.TXQCC1.UINT32
+#define RSCAN0TXQCC1L RSCAN0.TXQCC1.UINT16[L]
+#define RSCAN0TXQCC1LL RSCAN0.TXQCC1.UINT8[LL]
+#define RSCAN0TXQCC1LH RSCAN0.TXQCC1.UINT8[LH]
+#define RSCAN0TXQCC1H RSCAN0.TXQCC1.UINT16[H]
+#define RSCAN0TXQCC1HL RSCAN0.TXQCC1.UINT8[HL]
+#define RSCAN0TXQCC1HH RSCAN0.TXQCC1.UINT8[HH]
+#define RSCAN0TXQCC2 RSCAN0.TXQCC2.UINT32
+#define RSCAN0TXQCC2L RSCAN0.TXQCC2.UINT16[L]
+#define RSCAN0TXQCC2LL RSCAN0.TXQCC2.UINT8[LL]
+#define RSCAN0TXQCC2LH RSCAN0.TXQCC2.UINT8[LH]
+#define RSCAN0TXQCC2H RSCAN0.TXQCC2.UINT16[H]
+#define RSCAN0TXQCC2HL RSCAN0.TXQCC2.UINT8[HL]
+#define RSCAN0TXQCC2HH RSCAN0.TXQCC2.UINT8[HH]
+#define RSCAN0TXQCC3 RSCAN0.TXQCC3.UINT32
+#define RSCAN0TXQCC3L RSCAN0.TXQCC3.UINT16[L]
+#define RSCAN0TXQCC3LL RSCAN0.TXQCC3.UINT8[LL]
+#define RSCAN0TXQCC3LH RSCAN0.TXQCC3.UINT8[LH]
+#define RSCAN0TXQCC3H RSCAN0.TXQCC3.UINT16[H]
+#define RSCAN0TXQCC3HL RSCAN0.TXQCC3.UINT8[HL]
+#define RSCAN0TXQCC3HH RSCAN0.TXQCC3.UINT8[HH]
+#define RSCAN0TXQCC4 RSCAN0.TXQCC4.UINT32
+#define RSCAN0TXQCC4L RSCAN0.TXQCC4.UINT16[L]
+#define RSCAN0TXQCC4LL RSCAN0.TXQCC4.UINT8[LL]
+#define RSCAN0TXQCC4LH RSCAN0.TXQCC4.UINT8[LH]
+#define RSCAN0TXQCC4H RSCAN0.TXQCC4.UINT16[H]
+#define RSCAN0TXQCC4HL RSCAN0.TXQCC4.UINT8[HL]
+#define RSCAN0TXQCC4HH RSCAN0.TXQCC4.UINT8[HH]
+#define RSCAN0TXQSTS0 RSCAN0.TXQSTS0.UINT32
+#define RSCAN0TXQSTS0L RSCAN0.TXQSTS0.UINT16[L]
+#define RSCAN0TXQSTS0LL RSCAN0.TXQSTS0.UINT8[LL]
+#define RSCAN0TXQSTS0LH RSCAN0.TXQSTS0.UINT8[LH]
+#define RSCAN0TXQSTS0H RSCAN0.TXQSTS0.UINT16[H]
+#define RSCAN0TXQSTS0HL RSCAN0.TXQSTS0.UINT8[HL]
+#define RSCAN0TXQSTS0HH RSCAN0.TXQSTS0.UINT8[HH]
+#define RSCAN0TXQSTS1 RSCAN0.TXQSTS1.UINT32
+#define RSCAN0TXQSTS1L RSCAN0.TXQSTS1.UINT16[L]
+#define RSCAN0TXQSTS1LL RSCAN0.TXQSTS1.UINT8[LL]
+#define RSCAN0TXQSTS1LH RSCAN0.TXQSTS1.UINT8[LH]
+#define RSCAN0TXQSTS1H RSCAN0.TXQSTS1.UINT16[H]
+#define RSCAN0TXQSTS1HL RSCAN0.TXQSTS1.UINT8[HL]
+#define RSCAN0TXQSTS1HH RSCAN0.TXQSTS1.UINT8[HH]
+#define RSCAN0TXQSTS2 RSCAN0.TXQSTS2.UINT32
+#define RSCAN0TXQSTS2L RSCAN0.TXQSTS2.UINT16[L]
+#define RSCAN0TXQSTS2LL RSCAN0.TXQSTS2.UINT8[LL]
+#define RSCAN0TXQSTS2LH RSCAN0.TXQSTS2.UINT8[LH]
+#define RSCAN0TXQSTS2H RSCAN0.TXQSTS2.UINT16[H]
+#define RSCAN0TXQSTS2HL RSCAN0.TXQSTS2.UINT8[HL]
+#define RSCAN0TXQSTS2HH RSCAN0.TXQSTS2.UINT8[HH]
+#define RSCAN0TXQSTS3 RSCAN0.TXQSTS3.UINT32
+#define RSCAN0TXQSTS3L RSCAN0.TXQSTS3.UINT16[L]
+#define RSCAN0TXQSTS3LL RSCAN0.TXQSTS3.UINT8[LL]
+#define RSCAN0TXQSTS3LH RSCAN0.TXQSTS3.UINT8[LH]
+#define RSCAN0TXQSTS3H RSCAN0.TXQSTS3.UINT16[H]
+#define RSCAN0TXQSTS3HL RSCAN0.TXQSTS3.UINT8[HL]
+#define RSCAN0TXQSTS3HH RSCAN0.TXQSTS3.UINT8[HH]
+#define RSCAN0TXQSTS4 RSCAN0.TXQSTS4.UINT32
+#define RSCAN0TXQSTS4L RSCAN0.TXQSTS4.UINT16[L]
+#define RSCAN0TXQSTS4LL RSCAN0.TXQSTS4.UINT8[LL]
+#define RSCAN0TXQSTS4LH RSCAN0.TXQSTS4.UINT8[LH]
+#define RSCAN0TXQSTS4H RSCAN0.TXQSTS4.UINT16[H]
+#define RSCAN0TXQSTS4HL RSCAN0.TXQSTS4.UINT8[HL]
+#define RSCAN0TXQSTS4HH RSCAN0.TXQSTS4.UINT8[HH]
+#define RSCAN0TXQPCTR0 RSCAN0.TXQPCTR0.UINT32
+#define RSCAN0TXQPCTR0L RSCAN0.TXQPCTR0.UINT16[L]
+#define RSCAN0TXQPCTR0LL RSCAN0.TXQPCTR0.UINT8[LL]
+#define RSCAN0TXQPCTR0LH RSCAN0.TXQPCTR0.UINT8[LH]
+#define RSCAN0TXQPCTR0H RSCAN0.TXQPCTR0.UINT16[H]
+#define RSCAN0TXQPCTR0HL RSCAN0.TXQPCTR0.UINT8[HL]
+#define RSCAN0TXQPCTR0HH RSCAN0.TXQPCTR0.UINT8[HH]
+#define RSCAN0TXQPCTR1 RSCAN0.TXQPCTR1.UINT32
+#define RSCAN0TXQPCTR1L RSCAN0.TXQPCTR1.UINT16[L]
+#define RSCAN0TXQPCTR1LL RSCAN0.TXQPCTR1.UINT8[LL]
+#define RSCAN0TXQPCTR1LH RSCAN0.TXQPCTR1.UINT8[LH]
+#define RSCAN0TXQPCTR1H RSCAN0.TXQPCTR1.UINT16[H]
+#define RSCAN0TXQPCTR1HL RSCAN0.TXQPCTR1.UINT8[HL]
+#define RSCAN0TXQPCTR1HH RSCAN0.TXQPCTR1.UINT8[HH]
+#define RSCAN0TXQPCTR2 RSCAN0.TXQPCTR2.UINT32
+#define RSCAN0TXQPCTR2L RSCAN0.TXQPCTR2.UINT16[L]
+#define RSCAN0TXQPCTR2LL RSCAN0.TXQPCTR2.UINT8[LL]
+#define RSCAN0TXQPCTR2LH RSCAN0.TXQPCTR2.UINT8[LH]
+#define RSCAN0TXQPCTR2H RSCAN0.TXQPCTR2.UINT16[H]
+#define RSCAN0TXQPCTR2HL RSCAN0.TXQPCTR2.UINT8[HL]
+#define RSCAN0TXQPCTR2HH RSCAN0.TXQPCTR2.UINT8[HH]
+#define RSCAN0TXQPCTR3 RSCAN0.TXQPCTR3.UINT32
+#define RSCAN0TXQPCTR3L RSCAN0.TXQPCTR3.UINT16[L]
+#define RSCAN0TXQPCTR3LL RSCAN0.TXQPCTR3.UINT8[LL]
+#define RSCAN0TXQPCTR3LH RSCAN0.TXQPCTR3.UINT8[LH]
+#define RSCAN0TXQPCTR3H RSCAN0.TXQPCTR3.UINT16[H]
+#define RSCAN0TXQPCTR3HL RSCAN0.TXQPCTR3.UINT8[HL]
+#define RSCAN0TXQPCTR3HH RSCAN0.TXQPCTR3.UINT8[HH]
+#define RSCAN0TXQPCTR4 RSCAN0.TXQPCTR4.UINT32
+#define RSCAN0TXQPCTR4L RSCAN0.TXQPCTR4.UINT16[L]
+#define RSCAN0TXQPCTR4LL RSCAN0.TXQPCTR4.UINT8[LL]
+#define RSCAN0TXQPCTR4LH RSCAN0.TXQPCTR4.UINT8[LH]
+#define RSCAN0TXQPCTR4H RSCAN0.TXQPCTR4.UINT16[H]
+#define RSCAN0TXQPCTR4HL RSCAN0.TXQPCTR4.UINT8[HL]
+#define RSCAN0TXQPCTR4HH RSCAN0.TXQPCTR4.UINT8[HH]
+#define RSCAN0THLCC0 RSCAN0.THLCC0.UINT32
+#define RSCAN0THLCC0L RSCAN0.THLCC0.UINT16[L]
+#define RSCAN0THLCC0LL RSCAN0.THLCC0.UINT8[LL]
+#define RSCAN0THLCC0LH RSCAN0.THLCC0.UINT8[LH]
+#define RSCAN0THLCC0H RSCAN0.THLCC0.UINT16[H]
+#define RSCAN0THLCC0HL RSCAN0.THLCC0.UINT8[HL]
+#define RSCAN0THLCC0HH RSCAN0.THLCC0.UINT8[HH]
+#define RSCAN0THLCC1 RSCAN0.THLCC1.UINT32
+#define RSCAN0THLCC1L RSCAN0.THLCC1.UINT16[L]
+#define RSCAN0THLCC1LL RSCAN0.THLCC1.UINT8[LL]
+#define RSCAN0THLCC1LH RSCAN0.THLCC1.UINT8[LH]
+#define RSCAN0THLCC1H RSCAN0.THLCC1.UINT16[H]
+#define RSCAN0THLCC1HL RSCAN0.THLCC1.UINT8[HL]
+#define RSCAN0THLCC1HH RSCAN0.THLCC1.UINT8[HH]
+#define RSCAN0THLCC2 RSCAN0.THLCC2.UINT32
+#define RSCAN0THLCC2L RSCAN0.THLCC2.UINT16[L]
+#define RSCAN0THLCC2LL RSCAN0.THLCC2.UINT8[LL]
+#define RSCAN0THLCC2LH RSCAN0.THLCC2.UINT8[LH]
+#define RSCAN0THLCC2H RSCAN0.THLCC2.UINT16[H]
+#define RSCAN0THLCC2HL RSCAN0.THLCC2.UINT8[HL]
+#define RSCAN0THLCC2HH RSCAN0.THLCC2.UINT8[HH]
+#define RSCAN0THLCC3 RSCAN0.THLCC3.UINT32
+#define RSCAN0THLCC3L RSCAN0.THLCC3.UINT16[L]
+#define RSCAN0THLCC3LL RSCAN0.THLCC3.UINT8[LL]
+#define RSCAN0THLCC3LH RSCAN0.THLCC3.UINT8[LH]
+#define RSCAN0THLCC3H RSCAN0.THLCC3.UINT16[H]
+#define RSCAN0THLCC3HL RSCAN0.THLCC3.UINT8[HL]
+#define RSCAN0THLCC3HH RSCAN0.THLCC3.UINT8[HH]
+#define RSCAN0THLCC4 RSCAN0.THLCC4.UINT32
+#define RSCAN0THLCC4L RSCAN0.THLCC4.UINT16[L]
+#define RSCAN0THLCC4LL RSCAN0.THLCC4.UINT8[LL]
+#define RSCAN0THLCC4LH RSCAN0.THLCC4.UINT8[LH]
+#define RSCAN0THLCC4H RSCAN0.THLCC4.UINT16[H]
+#define RSCAN0THLCC4HL RSCAN0.THLCC4.UINT8[HL]
+#define RSCAN0THLCC4HH RSCAN0.THLCC4.UINT8[HH]
+#define RSCAN0THLSTS0 RSCAN0.THLSTS0.UINT32
+#define RSCAN0THLSTS0L RSCAN0.THLSTS0.UINT16[L]
+#define RSCAN0THLSTS0LL RSCAN0.THLSTS0.UINT8[LL]
+#define RSCAN0THLSTS0LH RSCAN0.THLSTS0.UINT8[LH]
+#define RSCAN0THLSTS0H RSCAN0.THLSTS0.UINT16[H]
+#define RSCAN0THLSTS0HL RSCAN0.THLSTS0.UINT8[HL]
+#define RSCAN0THLSTS0HH RSCAN0.THLSTS0.UINT8[HH]
+#define RSCAN0THLSTS1 RSCAN0.THLSTS1.UINT32
+#define RSCAN0THLSTS1L RSCAN0.THLSTS1.UINT16[L]
+#define RSCAN0THLSTS1LL RSCAN0.THLSTS1.UINT8[LL]
+#define RSCAN0THLSTS1LH RSCAN0.THLSTS1.UINT8[LH]
+#define RSCAN0THLSTS1H RSCAN0.THLSTS1.UINT16[H]
+#define RSCAN0THLSTS1HL RSCAN0.THLSTS1.UINT8[HL]
+#define RSCAN0THLSTS1HH RSCAN0.THLSTS1.UINT8[HH]
+#define RSCAN0THLSTS2 RSCAN0.THLSTS2.UINT32
+#define RSCAN0THLSTS2L RSCAN0.THLSTS2.UINT16[L]
+#define RSCAN0THLSTS2LL RSCAN0.THLSTS2.UINT8[LL]
+#define RSCAN0THLSTS2LH RSCAN0.THLSTS2.UINT8[LH]
+#define RSCAN0THLSTS2H RSCAN0.THLSTS2.UINT16[H]
+#define RSCAN0THLSTS2HL RSCAN0.THLSTS2.UINT8[HL]
+#define RSCAN0THLSTS2HH RSCAN0.THLSTS2.UINT8[HH]
+#define RSCAN0THLSTS3 RSCAN0.THLSTS3.UINT32
+#define RSCAN0THLSTS3L RSCAN0.THLSTS3.UINT16[L]
+#define RSCAN0THLSTS3LL RSCAN0.THLSTS3.UINT8[LL]
+#define RSCAN0THLSTS3LH RSCAN0.THLSTS3.UINT8[LH]
+#define RSCAN0THLSTS3H RSCAN0.THLSTS3.UINT16[H]
+#define RSCAN0THLSTS3HL RSCAN0.THLSTS3.UINT8[HL]
+#define RSCAN0THLSTS3HH RSCAN0.THLSTS3.UINT8[HH]
+#define RSCAN0THLSTS4 RSCAN0.THLSTS4.UINT32
+#define RSCAN0THLSTS4L RSCAN0.THLSTS4.UINT16[L]
+#define RSCAN0THLSTS4LL RSCAN0.THLSTS4.UINT8[LL]
+#define RSCAN0THLSTS4LH RSCAN0.THLSTS4.UINT8[LH]
+#define RSCAN0THLSTS4H RSCAN0.THLSTS4.UINT16[H]
+#define RSCAN0THLSTS4HL RSCAN0.THLSTS4.UINT8[HL]
+#define RSCAN0THLSTS4HH RSCAN0.THLSTS4.UINT8[HH]
+#define RSCAN0THLPCTR0 RSCAN0.THLPCTR0.UINT32
+#define RSCAN0THLPCTR0L RSCAN0.THLPCTR0.UINT16[L]
+#define RSCAN0THLPCTR0LL RSCAN0.THLPCTR0.UINT8[LL]
+#define RSCAN0THLPCTR0LH RSCAN0.THLPCTR0.UINT8[LH]
+#define RSCAN0THLPCTR0H RSCAN0.THLPCTR0.UINT16[H]
+#define RSCAN0THLPCTR0HL RSCAN0.THLPCTR0.UINT8[HL]
+#define RSCAN0THLPCTR0HH RSCAN0.THLPCTR0.UINT8[HH]
+#define RSCAN0THLPCTR1 RSCAN0.THLPCTR1.UINT32
+#define RSCAN0THLPCTR1L RSCAN0.THLPCTR1.UINT16[L]
+#define RSCAN0THLPCTR1LL RSCAN0.THLPCTR1.UINT8[LL]
+#define RSCAN0THLPCTR1LH RSCAN0.THLPCTR1.UINT8[LH]
+#define RSCAN0THLPCTR1H RSCAN0.THLPCTR1.UINT16[H]
+#define RSCAN0THLPCTR1HL RSCAN0.THLPCTR1.UINT8[HL]
+#define RSCAN0THLPCTR1HH RSCAN0.THLPCTR1.UINT8[HH]
+#define RSCAN0THLPCTR2 RSCAN0.THLPCTR2.UINT32
+#define RSCAN0THLPCTR2L RSCAN0.THLPCTR2.UINT16[L]
+#define RSCAN0THLPCTR2LL RSCAN0.THLPCTR2.UINT8[LL]
+#define RSCAN0THLPCTR2LH RSCAN0.THLPCTR2.UINT8[LH]
+#define RSCAN0THLPCTR2H RSCAN0.THLPCTR2.UINT16[H]
+#define RSCAN0THLPCTR2HL RSCAN0.THLPCTR2.UINT8[HL]
+#define RSCAN0THLPCTR2HH RSCAN0.THLPCTR2.UINT8[HH]
+#define RSCAN0THLPCTR3 RSCAN0.THLPCTR3.UINT32
+#define RSCAN0THLPCTR3L RSCAN0.THLPCTR3.UINT16[L]
+#define RSCAN0THLPCTR3LL RSCAN0.THLPCTR3.UINT8[LL]
+#define RSCAN0THLPCTR3LH RSCAN0.THLPCTR3.UINT8[LH]
+#define RSCAN0THLPCTR3H RSCAN0.THLPCTR3.UINT16[H]
+#define RSCAN0THLPCTR3HL RSCAN0.THLPCTR3.UINT8[HL]
+#define RSCAN0THLPCTR3HH RSCAN0.THLPCTR3.UINT8[HH]
+#define RSCAN0THLPCTR4 RSCAN0.THLPCTR4.UINT32
+#define RSCAN0THLPCTR4L RSCAN0.THLPCTR4.UINT16[L]
+#define RSCAN0THLPCTR4LL RSCAN0.THLPCTR4.UINT8[LL]
+#define RSCAN0THLPCTR4LH RSCAN0.THLPCTR4.UINT8[LH]
+#define RSCAN0THLPCTR4H RSCAN0.THLPCTR4.UINT16[H]
+#define RSCAN0THLPCTR4HL RSCAN0.THLPCTR4.UINT8[HL]
+#define RSCAN0THLPCTR4HH RSCAN0.THLPCTR4.UINT8[HH]
+#define RSCAN0GTINTSTS0 RSCAN0.GTINTSTS0.UINT32
+#define RSCAN0GTINTSTS0L RSCAN0.GTINTSTS0.UINT16[L]
+#define RSCAN0GTINTSTS0LL RSCAN0.GTINTSTS0.UINT8[LL]
+#define RSCAN0GTINTSTS0LH RSCAN0.GTINTSTS0.UINT8[LH]
+#define RSCAN0GTINTSTS0H RSCAN0.GTINTSTS0.UINT16[H]
+#define RSCAN0GTINTSTS0HL RSCAN0.GTINTSTS0.UINT8[HL]
+#define RSCAN0GTINTSTS0HH RSCAN0.GTINTSTS0.UINT8[HH]
+#define RSCAN0GTINTSTS1 RSCAN0.GTINTSTS1.UINT32
+#define RSCAN0GTINTSTS1L RSCAN0.GTINTSTS1.UINT16[L]
+#define RSCAN0GTINTSTS1LL RSCAN0.GTINTSTS1.UINT8[LL]
+#define RSCAN0GTINTSTS1LH RSCAN0.GTINTSTS1.UINT8[LH]
+#define RSCAN0GTINTSTS1H RSCAN0.GTINTSTS1.UINT16[H]
+#define RSCAN0GTINTSTS1HL RSCAN0.GTINTSTS1.UINT8[HL]
+#define RSCAN0GTINTSTS1HH RSCAN0.GTINTSTS1.UINT8[HH]
+#define RSCAN0GTSTCFG RSCAN0.GTSTCFG.UINT32
+#define RSCAN0GTSTCFGL RSCAN0.GTSTCFG.UINT16[L]
+#define RSCAN0GTSTCFGLL RSCAN0.GTSTCFG.UINT8[LL]
+#define RSCAN0GTSTCFGLH RSCAN0.GTSTCFG.UINT8[LH]
+#define RSCAN0GTSTCFGH RSCAN0.GTSTCFG.UINT16[H]
+#define RSCAN0GTSTCFGHL RSCAN0.GTSTCFG.UINT8[HL]
+#define RSCAN0GTSTCFGHH RSCAN0.GTSTCFG.UINT8[HH]
+#define RSCAN0GTSTCTR RSCAN0.GTSTCTR.UINT32
+#define RSCAN0GTSTCTRL RSCAN0.GTSTCTR.UINT16[L]
+#define RSCAN0GTSTCTRLL RSCAN0.GTSTCTR.UINT8[LL]
+#define RSCAN0GTSTCTRLH RSCAN0.GTSTCTR.UINT8[LH]
+#define RSCAN0GTSTCTRH RSCAN0.GTSTCTR.UINT16[H]
+#define RSCAN0GTSTCTRHL RSCAN0.GTSTCTR.UINT8[HL]
+#define RSCAN0GTSTCTRHH RSCAN0.GTSTCTR.UINT8[HH]
+#define RSCAN0GLOCKK RSCAN0.GLOCKK.UINT32
+#define RSCAN0GLOCKKL RSCAN0.GLOCKK.UINT16[L]
+#define RSCAN0GLOCKKH RSCAN0.GLOCKK.UINT16[H]
+#define RSCAN0GAFLID0 RSCAN0.GAFLID0.UINT32
+#define RSCAN0GAFLID0L RSCAN0.GAFLID0.UINT16[L]
+#define RSCAN0GAFLID0LL RSCAN0.GAFLID0.UINT8[LL]
+#define RSCAN0GAFLID0LH RSCAN0.GAFLID0.UINT8[LH]
+#define RSCAN0GAFLID0H RSCAN0.GAFLID0.UINT16[H]
+#define RSCAN0GAFLID0HL RSCAN0.GAFLID0.UINT8[HL]
+#define RSCAN0GAFLID0HH RSCAN0.GAFLID0.UINT8[HH]
+#define RSCAN0GAFLM0 RSCAN0.GAFLM0.UINT32
+#define RSCAN0GAFLM0L RSCAN0.GAFLM0.UINT16[L]
+#define RSCAN0GAFLM0LL RSCAN0.GAFLM0.UINT8[LL]
+#define RSCAN0GAFLM0LH RSCAN0.GAFLM0.UINT8[LH]
+#define RSCAN0GAFLM0H RSCAN0.GAFLM0.UINT16[H]
+#define RSCAN0GAFLM0HL RSCAN0.GAFLM0.UINT8[HL]
+#define RSCAN0GAFLM0HH RSCAN0.GAFLM0.UINT8[HH]
+#define RSCAN0GAFLP00 RSCAN0.GAFLP00.UINT32
+#define RSCAN0GAFLP00L RSCAN0.GAFLP00.UINT16[L]
+#define RSCAN0GAFLP00LL RSCAN0.GAFLP00.UINT8[LL]
+#define RSCAN0GAFLP00LH RSCAN0.GAFLP00.UINT8[LH]
+#define RSCAN0GAFLP00H RSCAN0.GAFLP00.UINT16[H]
+#define RSCAN0GAFLP00HL RSCAN0.GAFLP00.UINT8[HL]
+#define RSCAN0GAFLP00HH RSCAN0.GAFLP00.UINT8[HH]
+#define RSCAN0GAFLP10 RSCAN0.GAFLP10.UINT32
+#define RSCAN0GAFLP10L RSCAN0.GAFLP10.UINT16[L]
+#define RSCAN0GAFLP10LL RSCAN0.GAFLP10.UINT8[LL]
+#define RSCAN0GAFLP10LH RSCAN0.GAFLP10.UINT8[LH]
+#define RSCAN0GAFLP10H RSCAN0.GAFLP10.UINT16[H]
+#define RSCAN0GAFLP10HL RSCAN0.GAFLP10.UINT8[HL]
+#define RSCAN0GAFLP10HH RSCAN0.GAFLP10.UINT8[HH]
+#define RSCAN0GAFLID1 RSCAN0.GAFLID1.UINT32
+#define RSCAN0GAFLID1L RSCAN0.GAFLID1.UINT16[L]
+#define RSCAN0GAFLID1LL RSCAN0.GAFLID1.UINT8[LL]
+#define RSCAN0GAFLID1LH RSCAN0.GAFLID1.UINT8[LH]
+#define RSCAN0GAFLID1H RSCAN0.GAFLID1.UINT16[H]
+#define RSCAN0GAFLID1HL RSCAN0.GAFLID1.UINT8[HL]
+#define RSCAN0GAFLID1HH RSCAN0.GAFLID1.UINT8[HH]
+#define RSCAN0GAFLM1 RSCAN0.GAFLM1.UINT32
+#define RSCAN0GAFLM1L RSCAN0.GAFLM1.UINT16[L]
+#define RSCAN0GAFLM1LL RSCAN0.GAFLM1.UINT8[LL]
+#define RSCAN0GAFLM1LH RSCAN0.GAFLM1.UINT8[LH]
+#define RSCAN0GAFLM1H RSCAN0.GAFLM1.UINT16[H]
+#define RSCAN0GAFLM1HL RSCAN0.GAFLM1.UINT8[HL]
+#define RSCAN0GAFLM1HH RSCAN0.GAFLM1.UINT8[HH]
+#define RSCAN0GAFLP01 RSCAN0.GAFLP01.UINT32
+#define RSCAN0GAFLP01L RSCAN0.GAFLP01.UINT16[L]
+#define RSCAN0GAFLP01LL RSCAN0.GAFLP01.UINT8[LL]
+#define RSCAN0GAFLP01LH RSCAN0.GAFLP01.UINT8[LH]
+#define RSCAN0GAFLP01H RSCAN0.GAFLP01.UINT16[H]
+#define RSCAN0GAFLP01HL RSCAN0.GAFLP01.UINT8[HL]
+#define RSCAN0GAFLP01HH RSCAN0.GAFLP01.UINT8[HH]
+#define RSCAN0GAFLP11 RSCAN0.GAFLP11.UINT32
+#define RSCAN0GAFLP11L RSCAN0.GAFLP11.UINT16[L]
+#define RSCAN0GAFLP11LL RSCAN0.GAFLP11.UINT8[LL]
+#define RSCAN0GAFLP11LH RSCAN0.GAFLP11.UINT8[LH]
+#define RSCAN0GAFLP11H RSCAN0.GAFLP11.UINT16[H]
+#define RSCAN0GAFLP11HL RSCAN0.GAFLP11.UINT8[HL]
+#define RSCAN0GAFLP11HH RSCAN0.GAFLP11.UINT8[HH]
+#define RSCAN0GAFLID2 RSCAN0.GAFLID2.UINT32
+#define RSCAN0GAFLID2L RSCAN0.GAFLID2.UINT16[L]
+#define RSCAN0GAFLID2LL RSCAN0.GAFLID2.UINT8[LL]
+#define RSCAN0GAFLID2LH RSCAN0.GAFLID2.UINT8[LH]
+#define RSCAN0GAFLID2H RSCAN0.GAFLID2.UINT16[H]
+#define RSCAN0GAFLID2HL RSCAN0.GAFLID2.UINT8[HL]
+#define RSCAN0GAFLID2HH RSCAN0.GAFLID2.UINT8[HH]
+#define RSCAN0GAFLM2 RSCAN0.GAFLM2.UINT32
+#define RSCAN0GAFLM2L RSCAN0.GAFLM2.UINT16[L]
+#define RSCAN0GAFLM2LL RSCAN0.GAFLM2.UINT8[LL]
+#define RSCAN0GAFLM2LH RSCAN0.GAFLM2.UINT8[LH]
+#define RSCAN0GAFLM2H RSCAN0.GAFLM2.UINT16[H]
+#define RSCAN0GAFLM2HL RSCAN0.GAFLM2.UINT8[HL]
+#define RSCAN0GAFLM2HH RSCAN0.GAFLM2.UINT8[HH]
+#define RSCAN0GAFLP02 RSCAN0.GAFLP02.UINT32
+#define RSCAN0GAFLP02L RSCAN0.GAFLP02.UINT16[L]
+#define RSCAN0GAFLP02LL RSCAN0.GAFLP02.UINT8[LL]
+#define RSCAN0GAFLP02LH RSCAN0.GAFLP02.UINT8[LH]
+#define RSCAN0GAFLP02H RSCAN0.GAFLP02.UINT16[H]
+#define RSCAN0GAFLP02HL RSCAN0.GAFLP02.UINT8[HL]
+#define RSCAN0GAFLP02HH RSCAN0.GAFLP02.UINT8[HH]
+#define RSCAN0GAFLP12 RSCAN0.GAFLP12.UINT32
+#define RSCAN0GAFLP12L RSCAN0.GAFLP12.UINT16[L]
+#define RSCAN0GAFLP12LL RSCAN0.GAFLP12.UINT8[LL]
+#define RSCAN0GAFLP12LH RSCAN0.GAFLP12.UINT8[LH]
+#define RSCAN0GAFLP12H RSCAN0.GAFLP12.UINT16[H]
+#define RSCAN0GAFLP12HL RSCAN0.GAFLP12.UINT8[HL]
+#define RSCAN0GAFLP12HH RSCAN0.GAFLP12.UINT8[HH]
+#define RSCAN0GAFLID3 RSCAN0.GAFLID3.UINT32
+#define RSCAN0GAFLID3L RSCAN0.GAFLID3.UINT16[L]
+#define RSCAN0GAFLID3LL RSCAN0.GAFLID3.UINT8[LL]
+#define RSCAN0GAFLID3LH RSCAN0.GAFLID3.UINT8[LH]
+#define RSCAN0GAFLID3H RSCAN0.GAFLID3.UINT16[H]
+#define RSCAN0GAFLID3HL RSCAN0.GAFLID3.UINT8[HL]
+#define RSCAN0GAFLID3HH RSCAN0.GAFLID3.UINT8[HH]
+#define RSCAN0GAFLM3 RSCAN0.GAFLM3.UINT32
+#define RSCAN0GAFLM3L RSCAN0.GAFLM3.UINT16[L]
+#define RSCAN0GAFLM3LL RSCAN0.GAFLM3.UINT8[LL]
+#define RSCAN0GAFLM3LH RSCAN0.GAFLM3.UINT8[LH]
+#define RSCAN0GAFLM3H RSCAN0.GAFLM3.UINT16[H]
+#define RSCAN0GAFLM3HL RSCAN0.GAFLM3.UINT8[HL]
+#define RSCAN0GAFLM3HH RSCAN0.GAFLM3.UINT8[HH]
+#define RSCAN0GAFLP03 RSCAN0.GAFLP03.UINT32
+#define RSCAN0GAFLP03L RSCAN0.GAFLP03.UINT16[L]
+#define RSCAN0GAFLP03LL RSCAN0.GAFLP03.UINT8[LL]
+#define RSCAN0GAFLP03LH RSCAN0.GAFLP03.UINT8[LH]
+#define RSCAN0GAFLP03H RSCAN0.GAFLP03.UINT16[H]
+#define RSCAN0GAFLP03HL RSCAN0.GAFLP03.UINT8[HL]
+#define RSCAN0GAFLP03HH RSCAN0.GAFLP03.UINT8[HH]
+#define RSCAN0GAFLP13 RSCAN0.GAFLP13.UINT32
+#define RSCAN0GAFLP13L RSCAN0.GAFLP13.UINT16[L]
+#define RSCAN0GAFLP13LL RSCAN0.GAFLP13.UINT8[LL]
+#define RSCAN0GAFLP13LH RSCAN0.GAFLP13.UINT8[LH]
+#define RSCAN0GAFLP13H RSCAN0.GAFLP13.UINT16[H]
+#define RSCAN0GAFLP13HL RSCAN0.GAFLP13.UINT8[HL]
+#define RSCAN0GAFLP13HH RSCAN0.GAFLP13.UINT8[HH]
+#define RSCAN0GAFLID4 RSCAN0.GAFLID4.UINT32
+#define RSCAN0GAFLID4L RSCAN0.GAFLID4.UINT16[L]
+#define RSCAN0GAFLID4LL RSCAN0.GAFLID4.UINT8[LL]
+#define RSCAN0GAFLID4LH RSCAN0.GAFLID4.UINT8[LH]
+#define RSCAN0GAFLID4H RSCAN0.GAFLID4.UINT16[H]
+#define RSCAN0GAFLID4HL RSCAN0.GAFLID4.UINT8[HL]
+#define RSCAN0GAFLID4HH RSCAN0.GAFLID4.UINT8[HH]
+#define RSCAN0GAFLM4 RSCAN0.GAFLM4.UINT32
+#define RSCAN0GAFLM4L RSCAN0.GAFLM4.UINT16[L]
+#define RSCAN0GAFLM4LL RSCAN0.GAFLM4.UINT8[LL]
+#define RSCAN0GAFLM4LH RSCAN0.GAFLM4.UINT8[LH]
+#define RSCAN0GAFLM4H RSCAN0.GAFLM4.UINT16[H]
+#define RSCAN0GAFLM4HL RSCAN0.GAFLM4.UINT8[HL]
+#define RSCAN0GAFLM4HH RSCAN0.GAFLM4.UINT8[HH]
+#define RSCAN0GAFLP04 RSCAN0.GAFLP04.UINT32
+#define RSCAN0GAFLP04L RSCAN0.GAFLP04.UINT16[L]
+#define RSCAN0GAFLP04LL RSCAN0.GAFLP04.UINT8[LL]
+#define RSCAN0GAFLP04LH RSCAN0.GAFLP04.UINT8[LH]
+#define RSCAN0GAFLP04H RSCAN0.GAFLP04.UINT16[H]
+#define RSCAN0GAFLP04HL RSCAN0.GAFLP04.UINT8[HL]
+#define RSCAN0GAFLP04HH RSCAN0.GAFLP04.UINT8[HH]
+#define RSCAN0GAFLP14 RSCAN0.GAFLP14.UINT32
+#define RSCAN0GAFLP14L RSCAN0.GAFLP14.UINT16[L]
+#define RSCAN0GAFLP14LL RSCAN0.GAFLP14.UINT8[LL]
+#define RSCAN0GAFLP14LH RSCAN0.GAFLP14.UINT8[LH]
+#define RSCAN0GAFLP14H RSCAN0.GAFLP14.UINT16[H]
+#define RSCAN0GAFLP14HL RSCAN0.GAFLP14.UINT8[HL]
+#define RSCAN0GAFLP14HH RSCAN0.GAFLP14.UINT8[HH]
+#define RSCAN0GAFLID5 RSCAN0.GAFLID5.UINT32
+#define RSCAN0GAFLID5L RSCAN0.GAFLID5.UINT16[L]
+#define RSCAN0GAFLID5LL RSCAN0.GAFLID5.UINT8[LL]
+#define RSCAN0GAFLID5LH RSCAN0.GAFLID5.UINT8[LH]
+#define RSCAN0GAFLID5H RSCAN0.GAFLID5.UINT16[H]
+#define RSCAN0GAFLID5HL RSCAN0.GAFLID5.UINT8[HL]
+#define RSCAN0GAFLID5HH RSCAN0.GAFLID5.UINT8[HH]
+#define RSCAN0GAFLM5 RSCAN0.GAFLM5.UINT32
+#define RSCAN0GAFLM5L RSCAN0.GAFLM5.UINT16[L]
+#define RSCAN0GAFLM5LL RSCAN0.GAFLM5.UINT8[LL]
+#define RSCAN0GAFLM5LH RSCAN0.GAFLM5.UINT8[LH]
+#define RSCAN0GAFLM5H RSCAN0.GAFLM5.UINT16[H]
+#define RSCAN0GAFLM5HL RSCAN0.GAFLM5.UINT8[HL]
+#define RSCAN0GAFLM5HH RSCAN0.GAFLM5.UINT8[HH]
+#define RSCAN0GAFLP05 RSCAN0.GAFLP05.UINT32
+#define RSCAN0GAFLP05L RSCAN0.GAFLP05.UINT16[L]
+#define RSCAN0GAFLP05LL RSCAN0.GAFLP05.UINT8[LL]
+#define RSCAN0GAFLP05LH RSCAN0.GAFLP05.UINT8[LH]
+#define RSCAN0GAFLP05H RSCAN0.GAFLP05.UINT16[H]
+#define RSCAN0GAFLP05HL RSCAN0.GAFLP05.UINT8[HL]
+#define RSCAN0GAFLP05HH RSCAN0.GAFLP05.UINT8[HH]
+#define RSCAN0GAFLP15 RSCAN0.GAFLP15.UINT32
+#define RSCAN0GAFLP15L RSCAN0.GAFLP15.UINT16[L]
+#define RSCAN0GAFLP15LL RSCAN0.GAFLP15.UINT8[LL]
+#define RSCAN0GAFLP15LH RSCAN0.GAFLP15.UINT8[LH]
+#define RSCAN0GAFLP15H RSCAN0.GAFLP15.UINT16[H]
+#define RSCAN0GAFLP15HL RSCAN0.GAFLP15.UINT8[HL]
+#define RSCAN0GAFLP15HH RSCAN0.GAFLP15.UINT8[HH]
+#define RSCAN0GAFLID6 RSCAN0.GAFLID6.UINT32
+#define RSCAN0GAFLID6L RSCAN0.GAFLID6.UINT16[L]
+#define RSCAN0GAFLID6LL RSCAN0.GAFLID6.UINT8[LL]
+#define RSCAN0GAFLID6LH RSCAN0.GAFLID6.UINT8[LH]
+#define RSCAN0GAFLID6H RSCAN0.GAFLID6.UINT16[H]
+#define RSCAN0GAFLID6HL RSCAN0.GAFLID6.UINT8[HL]
+#define RSCAN0GAFLID6HH RSCAN0.GAFLID6.UINT8[HH]
+#define RSCAN0GAFLM6 RSCAN0.GAFLM6.UINT32
+#define RSCAN0GAFLM6L RSCAN0.GAFLM6.UINT16[L]
+#define RSCAN0GAFLM6LL RSCAN0.GAFLM6.UINT8[LL]
+#define RSCAN0GAFLM6LH RSCAN0.GAFLM6.UINT8[LH]
+#define RSCAN0GAFLM6H RSCAN0.GAFLM6.UINT16[H]
+#define RSCAN0GAFLM6HL RSCAN0.GAFLM6.UINT8[HL]
+#define RSCAN0GAFLM6HH RSCAN0.GAFLM6.UINT8[HH]
+#define RSCAN0GAFLP06 RSCAN0.GAFLP06.UINT32
+#define RSCAN0GAFLP06L RSCAN0.GAFLP06.UINT16[L]
+#define RSCAN0GAFLP06LL RSCAN0.GAFLP06.UINT8[LL]
+#define RSCAN0GAFLP06LH RSCAN0.GAFLP06.UINT8[LH]
+#define RSCAN0GAFLP06H RSCAN0.GAFLP06.UINT16[H]
+#define RSCAN0GAFLP06HL RSCAN0.GAFLP06.UINT8[HL]
+#define RSCAN0GAFLP06HH RSCAN0.GAFLP06.UINT8[HH]
+#define RSCAN0GAFLP16 RSCAN0.GAFLP16.UINT32
+#define RSCAN0GAFLP16L RSCAN0.GAFLP16.UINT16[L]
+#define RSCAN0GAFLP16LL RSCAN0.GAFLP16.UINT8[LL]
+#define RSCAN0GAFLP16LH RSCAN0.GAFLP16.UINT8[LH]
+#define RSCAN0GAFLP16H RSCAN0.GAFLP16.UINT16[H]
+#define RSCAN0GAFLP16HL RSCAN0.GAFLP16.UINT8[HL]
+#define RSCAN0GAFLP16HH RSCAN0.GAFLP16.UINT8[HH]
+#define RSCAN0GAFLID7 RSCAN0.GAFLID7.UINT32
+#define RSCAN0GAFLID7L RSCAN0.GAFLID7.UINT16[L]
+#define RSCAN0GAFLID7LL RSCAN0.GAFLID7.UINT8[LL]
+#define RSCAN0GAFLID7LH RSCAN0.GAFLID7.UINT8[LH]
+#define RSCAN0GAFLID7H RSCAN0.GAFLID7.UINT16[H]
+#define RSCAN0GAFLID7HL RSCAN0.GAFLID7.UINT8[HL]
+#define RSCAN0GAFLID7HH RSCAN0.GAFLID7.UINT8[HH]
+#define RSCAN0GAFLM7 RSCAN0.GAFLM7.UINT32
+#define RSCAN0GAFLM7L RSCAN0.GAFLM7.UINT16[L]
+#define RSCAN0GAFLM7LL RSCAN0.GAFLM7.UINT8[LL]
+#define RSCAN0GAFLM7LH RSCAN0.GAFLM7.UINT8[LH]
+#define RSCAN0GAFLM7H RSCAN0.GAFLM7.UINT16[H]
+#define RSCAN0GAFLM7HL RSCAN0.GAFLM7.UINT8[HL]
+#define RSCAN0GAFLM7HH RSCAN0.GAFLM7.UINT8[HH]
+#define RSCAN0GAFLP07 RSCAN0.GAFLP07.UINT32
+#define RSCAN0GAFLP07L RSCAN0.GAFLP07.UINT16[L]
+#define RSCAN0GAFLP07LL RSCAN0.GAFLP07.UINT8[LL]
+#define RSCAN0GAFLP07LH RSCAN0.GAFLP07.UINT8[LH]
+#define RSCAN0GAFLP07H RSCAN0.GAFLP07.UINT16[H]
+#define RSCAN0GAFLP07HL RSCAN0.GAFLP07.UINT8[HL]
+#define RSCAN0GAFLP07HH RSCAN0.GAFLP07.UINT8[HH]
+#define RSCAN0GAFLP17 RSCAN0.GAFLP17.UINT32
+#define RSCAN0GAFLP17L RSCAN0.GAFLP17.UINT16[L]
+#define RSCAN0GAFLP17LL RSCAN0.GAFLP17.UINT8[LL]
+#define RSCAN0GAFLP17LH RSCAN0.GAFLP17.UINT8[LH]
+#define RSCAN0GAFLP17H RSCAN0.GAFLP17.UINT16[H]
+#define RSCAN0GAFLP17HL RSCAN0.GAFLP17.UINT8[HL]
+#define RSCAN0GAFLP17HH RSCAN0.GAFLP17.UINT8[HH]
+#define RSCAN0GAFLID8 RSCAN0.GAFLID8.UINT32
+#define RSCAN0GAFLID8L RSCAN0.GAFLID8.UINT16[L]
+#define RSCAN0GAFLID8LL RSCAN0.GAFLID8.UINT8[LL]
+#define RSCAN0GAFLID8LH RSCAN0.GAFLID8.UINT8[LH]
+#define RSCAN0GAFLID8H RSCAN0.GAFLID8.UINT16[H]
+#define RSCAN0GAFLID8HL RSCAN0.GAFLID8.UINT8[HL]
+#define RSCAN0GAFLID8HH RSCAN0.GAFLID8.UINT8[HH]
+#define RSCAN0GAFLM8 RSCAN0.GAFLM8.UINT32
+#define RSCAN0GAFLM8L RSCAN0.GAFLM8.UINT16[L]
+#define RSCAN0GAFLM8LL RSCAN0.GAFLM8.UINT8[LL]
+#define RSCAN0GAFLM8LH RSCAN0.GAFLM8.UINT8[LH]
+#define RSCAN0GAFLM8H RSCAN0.GAFLM8.UINT16[H]
+#define RSCAN0GAFLM8HL RSCAN0.GAFLM8.UINT8[HL]
+#define RSCAN0GAFLM8HH RSCAN0.GAFLM8.UINT8[HH]
+#define RSCAN0GAFLP08 RSCAN0.GAFLP08.UINT32
+#define RSCAN0GAFLP08L RSCAN0.GAFLP08.UINT16[L]
+#define RSCAN0GAFLP08LL RSCAN0.GAFLP08.UINT8[LL]
+#define RSCAN0GAFLP08LH RSCAN0.GAFLP08.UINT8[LH]
+#define RSCAN0GAFLP08H RSCAN0.GAFLP08.UINT16[H]
+#define RSCAN0GAFLP08HL RSCAN0.GAFLP08.UINT8[HL]
+#define RSCAN0GAFLP08HH RSCAN0.GAFLP08.UINT8[HH]
+#define RSCAN0GAFLP18 RSCAN0.GAFLP18.UINT32
+#define RSCAN0GAFLP18L RSCAN0.GAFLP18.UINT16[L]
+#define RSCAN0GAFLP18LL RSCAN0.GAFLP18.UINT8[LL]
+#define RSCAN0GAFLP18LH RSCAN0.GAFLP18.UINT8[LH]
+#define RSCAN0GAFLP18H RSCAN0.GAFLP18.UINT16[H]
+#define RSCAN0GAFLP18HL RSCAN0.GAFLP18.UINT8[HL]
+#define RSCAN0GAFLP18HH RSCAN0.GAFLP18.UINT8[HH]
+#define RSCAN0GAFLID9 RSCAN0.GAFLID9.UINT32
+#define RSCAN0GAFLID9L RSCAN0.GAFLID9.UINT16[L]
+#define RSCAN0GAFLID9LL RSCAN0.GAFLID9.UINT8[LL]
+#define RSCAN0GAFLID9LH RSCAN0.GAFLID9.UINT8[LH]
+#define RSCAN0GAFLID9H RSCAN0.GAFLID9.UINT16[H]
+#define RSCAN0GAFLID9HL RSCAN0.GAFLID9.UINT8[HL]
+#define RSCAN0GAFLID9HH RSCAN0.GAFLID9.UINT8[HH]
+#define RSCAN0GAFLM9 RSCAN0.GAFLM9.UINT32
+#define RSCAN0GAFLM9L RSCAN0.GAFLM9.UINT16[L]
+#define RSCAN0GAFLM9LL RSCAN0.GAFLM9.UINT8[LL]
+#define RSCAN0GAFLM9LH RSCAN0.GAFLM9.UINT8[LH]
+#define RSCAN0GAFLM9H RSCAN0.GAFLM9.UINT16[H]
+#define RSCAN0GAFLM9HL RSCAN0.GAFLM9.UINT8[HL]
+#define RSCAN0GAFLM9HH RSCAN0.GAFLM9.UINT8[HH]
+#define RSCAN0GAFLP09 RSCAN0.GAFLP09.UINT32
+#define RSCAN0GAFLP09L RSCAN0.GAFLP09.UINT16[L]
+#define RSCAN0GAFLP09LL RSCAN0.GAFLP09.UINT8[LL]
+#define RSCAN0GAFLP09LH RSCAN0.GAFLP09.UINT8[LH]
+#define RSCAN0GAFLP09H RSCAN0.GAFLP09.UINT16[H]
+#define RSCAN0GAFLP09HL RSCAN0.GAFLP09.UINT8[HL]
+#define RSCAN0GAFLP09HH RSCAN0.GAFLP09.UINT8[HH]
+#define RSCAN0GAFLP19 RSCAN0.GAFLP19.UINT32
+#define RSCAN0GAFLP19L RSCAN0.GAFLP19.UINT16[L]
+#define RSCAN0GAFLP19LL RSCAN0.GAFLP19.UINT8[LL]
+#define RSCAN0GAFLP19LH RSCAN0.GAFLP19.UINT8[LH]
+#define RSCAN0GAFLP19H RSCAN0.GAFLP19.UINT16[H]
+#define RSCAN0GAFLP19HL RSCAN0.GAFLP19.UINT8[HL]
+#define RSCAN0GAFLP19HH RSCAN0.GAFLP19.UINT8[HH]
+#define RSCAN0GAFLID10 RSCAN0.GAFLID10.UINT32
+#define RSCAN0GAFLID10L RSCAN0.GAFLID10.UINT16[L]
+#define RSCAN0GAFLID10LL RSCAN0.GAFLID10.UINT8[LL]
+#define RSCAN0GAFLID10LH RSCAN0.GAFLID10.UINT8[LH]
+#define RSCAN0GAFLID10H RSCAN0.GAFLID10.UINT16[H]
+#define RSCAN0GAFLID10HL RSCAN0.GAFLID10.UINT8[HL]
+#define RSCAN0GAFLID10HH RSCAN0.GAFLID10.UINT8[HH]
+#define RSCAN0GAFLM10 RSCAN0.GAFLM10.UINT32
+#define RSCAN0GAFLM10L RSCAN0.GAFLM10.UINT16[L]
+#define RSCAN0GAFLM10LL RSCAN0.GAFLM10.UINT8[LL]
+#define RSCAN0GAFLM10LH RSCAN0.GAFLM10.UINT8[LH]
+#define RSCAN0GAFLM10H RSCAN0.GAFLM10.UINT16[H]
+#define RSCAN0GAFLM10HL RSCAN0.GAFLM10.UINT8[HL]
+#define RSCAN0GAFLM10HH RSCAN0.GAFLM10.UINT8[HH]
+#define RSCAN0GAFLP010 RSCAN0.GAFLP010.UINT32
+#define RSCAN0GAFLP010L RSCAN0.GAFLP010.UINT16[L]
+#define RSCAN0GAFLP010LL RSCAN0.GAFLP010.UINT8[LL]
+#define RSCAN0GAFLP010LH RSCAN0.GAFLP010.UINT8[LH]
+#define RSCAN0GAFLP010H RSCAN0.GAFLP010.UINT16[H]
+#define RSCAN0GAFLP010HL RSCAN0.GAFLP010.UINT8[HL]
+#define RSCAN0GAFLP010HH RSCAN0.GAFLP010.UINT8[HH]
+#define RSCAN0GAFLP110 RSCAN0.GAFLP110.UINT32
+#define RSCAN0GAFLP110L RSCAN0.GAFLP110.UINT16[L]
+#define RSCAN0GAFLP110LL RSCAN0.GAFLP110.UINT8[LL]
+#define RSCAN0GAFLP110LH RSCAN0.GAFLP110.UINT8[LH]
+#define RSCAN0GAFLP110H RSCAN0.GAFLP110.UINT16[H]
+#define RSCAN0GAFLP110HL RSCAN0.GAFLP110.UINT8[HL]
+#define RSCAN0GAFLP110HH RSCAN0.GAFLP110.UINT8[HH]
+#define RSCAN0GAFLID11 RSCAN0.GAFLID11.UINT32
+#define RSCAN0GAFLID11L RSCAN0.GAFLID11.UINT16[L]
+#define RSCAN0GAFLID11LL RSCAN0.GAFLID11.UINT8[LL]
+#define RSCAN0GAFLID11LH RSCAN0.GAFLID11.UINT8[LH]
+#define RSCAN0GAFLID11H RSCAN0.GAFLID11.UINT16[H]
+#define RSCAN0GAFLID11HL RSCAN0.GAFLID11.UINT8[HL]
+#define RSCAN0GAFLID11HH RSCAN0.GAFLID11.UINT8[HH]
+#define RSCAN0GAFLM11 RSCAN0.GAFLM11.UINT32
+#define RSCAN0GAFLM11L RSCAN0.GAFLM11.UINT16[L]
+#define RSCAN0GAFLM11LL RSCAN0.GAFLM11.UINT8[LL]
+#define RSCAN0GAFLM11LH RSCAN0.GAFLM11.UINT8[LH]
+#define RSCAN0GAFLM11H RSCAN0.GAFLM11.UINT16[H]
+#define RSCAN0GAFLM11HL RSCAN0.GAFLM11.UINT8[HL]
+#define RSCAN0GAFLM11HH RSCAN0.GAFLM11.UINT8[HH]
+#define RSCAN0GAFLP011 RSCAN0.GAFLP011.UINT32
+#define RSCAN0GAFLP011L RSCAN0.GAFLP011.UINT16[L]
+#define RSCAN0GAFLP011LL RSCAN0.GAFLP011.UINT8[LL]
+#define RSCAN0GAFLP011LH RSCAN0.GAFLP011.UINT8[LH]
+#define RSCAN0GAFLP011H RSCAN0.GAFLP011.UINT16[H]
+#define RSCAN0GAFLP011HL RSCAN0.GAFLP011.UINT8[HL]
+#define RSCAN0GAFLP011HH RSCAN0.GAFLP011.UINT8[HH]
+#define RSCAN0GAFLP111 RSCAN0.GAFLP111.UINT32
+#define RSCAN0GAFLP111L RSCAN0.GAFLP111.UINT16[L]
+#define RSCAN0GAFLP111LL RSCAN0.GAFLP111.UINT8[LL]
+#define RSCAN0GAFLP111LH RSCAN0.GAFLP111.UINT8[LH]
+#define RSCAN0GAFLP111H RSCAN0.GAFLP111.UINT16[H]
+#define RSCAN0GAFLP111HL RSCAN0.GAFLP111.UINT8[HL]
+#define RSCAN0GAFLP111HH RSCAN0.GAFLP111.UINT8[HH]
+#define RSCAN0GAFLID12 RSCAN0.GAFLID12.UINT32
+#define RSCAN0GAFLID12L RSCAN0.GAFLID12.UINT16[L]
+#define RSCAN0GAFLID12LL RSCAN0.GAFLID12.UINT8[LL]
+#define RSCAN0GAFLID12LH RSCAN0.GAFLID12.UINT8[LH]
+#define RSCAN0GAFLID12H RSCAN0.GAFLID12.UINT16[H]
+#define RSCAN0GAFLID12HL RSCAN0.GAFLID12.UINT8[HL]
+#define RSCAN0GAFLID12HH RSCAN0.GAFLID12.UINT8[HH]
+#define RSCAN0GAFLM12 RSCAN0.GAFLM12.UINT32
+#define RSCAN0GAFLM12L RSCAN0.GAFLM12.UINT16[L]
+#define RSCAN0GAFLM12LL RSCAN0.GAFLM12.UINT8[LL]
+#define RSCAN0GAFLM12LH RSCAN0.GAFLM12.UINT8[LH]
+#define RSCAN0GAFLM12H RSCAN0.GAFLM12.UINT16[H]
+#define RSCAN0GAFLM12HL RSCAN0.GAFLM12.UINT8[HL]
+#define RSCAN0GAFLM12HH RSCAN0.GAFLM12.UINT8[HH]
+#define RSCAN0GAFLP012 RSCAN0.GAFLP012.UINT32
+#define RSCAN0GAFLP012L RSCAN0.GAFLP012.UINT16[L]
+#define RSCAN0GAFLP012LL RSCAN0.GAFLP012.UINT8[LL]
+#define RSCAN0GAFLP012LH RSCAN0.GAFLP012.UINT8[LH]
+#define RSCAN0GAFLP012H RSCAN0.GAFLP012.UINT16[H]
+#define RSCAN0GAFLP012HL RSCAN0.GAFLP012.UINT8[HL]
+#define RSCAN0GAFLP012HH RSCAN0.GAFLP012.UINT8[HH]
+#define RSCAN0GAFLP112 RSCAN0.GAFLP112.UINT32
+#define RSCAN0GAFLP112L RSCAN0.GAFLP112.UINT16[L]
+#define RSCAN0GAFLP112LL RSCAN0.GAFLP112.UINT8[LL]
+#define RSCAN0GAFLP112LH RSCAN0.GAFLP112.UINT8[LH]
+#define RSCAN0GAFLP112H RSCAN0.GAFLP112.UINT16[H]
+#define RSCAN0GAFLP112HL RSCAN0.GAFLP112.UINT8[HL]
+#define RSCAN0GAFLP112HH RSCAN0.GAFLP112.UINT8[HH]
+#define RSCAN0GAFLID13 RSCAN0.GAFLID13.UINT32
+#define RSCAN0GAFLID13L RSCAN0.GAFLID13.UINT16[L]
+#define RSCAN0GAFLID13LL RSCAN0.GAFLID13.UINT8[LL]
+#define RSCAN0GAFLID13LH RSCAN0.GAFLID13.UINT8[LH]
+#define RSCAN0GAFLID13H RSCAN0.GAFLID13.UINT16[H]
+#define RSCAN0GAFLID13HL RSCAN0.GAFLID13.UINT8[HL]
+#define RSCAN0GAFLID13HH RSCAN0.GAFLID13.UINT8[HH]
+#define RSCAN0GAFLM13 RSCAN0.GAFLM13.UINT32
+#define RSCAN0GAFLM13L RSCAN0.GAFLM13.UINT16[L]
+#define RSCAN0GAFLM13LL RSCAN0.GAFLM13.UINT8[LL]
+#define RSCAN0GAFLM13LH RSCAN0.GAFLM13.UINT8[LH]
+#define RSCAN0GAFLM13H RSCAN0.GAFLM13.UINT16[H]
+#define RSCAN0GAFLM13HL RSCAN0.GAFLM13.UINT8[HL]
+#define RSCAN0GAFLM13HH RSCAN0.GAFLM13.UINT8[HH]
+#define RSCAN0GAFLP013 RSCAN0.GAFLP013.UINT32
+#define RSCAN0GAFLP013L RSCAN0.GAFLP013.UINT16[L]
+#define RSCAN0GAFLP013LL RSCAN0.GAFLP013.UINT8[LL]
+#define RSCAN0GAFLP013LH RSCAN0.GAFLP013.UINT8[LH]
+#define RSCAN0GAFLP013H RSCAN0.GAFLP013.UINT16[H]
+#define RSCAN0GAFLP013HL RSCAN0.GAFLP013.UINT8[HL]
+#define RSCAN0GAFLP013HH RSCAN0.GAFLP013.UINT8[HH]
+#define RSCAN0GAFLP113 RSCAN0.GAFLP113.UINT32
+#define RSCAN0GAFLP113L RSCAN0.GAFLP113.UINT16[L]
+#define RSCAN0GAFLP113LL RSCAN0.GAFLP113.UINT8[LL]
+#define RSCAN0GAFLP113LH RSCAN0.GAFLP113.UINT8[LH]
+#define RSCAN0GAFLP113H RSCAN0.GAFLP113.UINT16[H]
+#define RSCAN0GAFLP113HL RSCAN0.GAFLP113.UINT8[HL]
+#define RSCAN0GAFLP113HH RSCAN0.GAFLP113.UINT8[HH]
+#define RSCAN0GAFLID14 RSCAN0.GAFLID14.UINT32
+#define RSCAN0GAFLID14L RSCAN0.GAFLID14.UINT16[L]
+#define RSCAN0GAFLID14LL RSCAN0.GAFLID14.UINT8[LL]
+#define RSCAN0GAFLID14LH RSCAN0.GAFLID14.UINT8[LH]
+#define RSCAN0GAFLID14H RSCAN0.GAFLID14.UINT16[H]
+#define RSCAN0GAFLID14HL RSCAN0.GAFLID14.UINT8[HL]
+#define RSCAN0GAFLID14HH RSCAN0.GAFLID14.UINT8[HH]
+#define RSCAN0GAFLM14 RSCAN0.GAFLM14.UINT32
+#define RSCAN0GAFLM14L RSCAN0.GAFLM14.UINT16[L]
+#define RSCAN0GAFLM14LL RSCAN0.GAFLM14.UINT8[LL]
+#define RSCAN0GAFLM14LH RSCAN0.GAFLM14.UINT8[LH]
+#define RSCAN0GAFLM14H RSCAN0.GAFLM14.UINT16[H]
+#define RSCAN0GAFLM14HL RSCAN0.GAFLM14.UINT8[HL]
+#define RSCAN0GAFLM14HH RSCAN0.GAFLM14.UINT8[HH]
+#define RSCAN0GAFLP014 RSCAN0.GAFLP014.UINT32
+#define RSCAN0GAFLP014L RSCAN0.GAFLP014.UINT16[L]
+#define RSCAN0GAFLP014LL RSCAN0.GAFLP014.UINT8[LL]
+#define RSCAN0GAFLP014LH RSCAN0.GAFLP014.UINT8[LH]
+#define RSCAN0GAFLP014H RSCAN0.GAFLP014.UINT16[H]
+#define RSCAN0GAFLP014HL RSCAN0.GAFLP014.UINT8[HL]
+#define RSCAN0GAFLP014HH RSCAN0.GAFLP014.UINT8[HH]
+#define RSCAN0GAFLP114 RSCAN0.GAFLP114.UINT32
+#define RSCAN0GAFLP114L RSCAN0.GAFLP114.UINT16[L]
+#define RSCAN0GAFLP114LL RSCAN0.GAFLP114.UINT8[LL]
+#define RSCAN0GAFLP114LH RSCAN0.GAFLP114.UINT8[LH]
+#define RSCAN0GAFLP114H RSCAN0.GAFLP114.UINT16[H]
+#define RSCAN0GAFLP114HL RSCAN0.GAFLP114.UINT8[HL]
+#define RSCAN0GAFLP114HH RSCAN0.GAFLP114.UINT8[HH]
+#define RSCAN0GAFLID15 RSCAN0.GAFLID15.UINT32
+#define RSCAN0GAFLID15L RSCAN0.GAFLID15.UINT16[L]
+#define RSCAN0GAFLID15LL RSCAN0.GAFLID15.UINT8[LL]
+#define RSCAN0GAFLID15LH RSCAN0.GAFLID15.UINT8[LH]
+#define RSCAN0GAFLID15H RSCAN0.GAFLID15.UINT16[H]
+#define RSCAN0GAFLID15HL RSCAN0.GAFLID15.UINT8[HL]
+#define RSCAN0GAFLID15HH RSCAN0.GAFLID15.UINT8[HH]
+#define RSCAN0GAFLM15 RSCAN0.GAFLM15.UINT32
+#define RSCAN0GAFLM15L RSCAN0.GAFLM15.UINT16[L]
+#define RSCAN0GAFLM15LL RSCAN0.GAFLM15.UINT8[LL]
+#define RSCAN0GAFLM15LH RSCAN0.GAFLM15.UINT8[LH]
+#define RSCAN0GAFLM15H RSCAN0.GAFLM15.UINT16[H]
+#define RSCAN0GAFLM15HL RSCAN0.GAFLM15.UINT8[HL]
+#define RSCAN0GAFLM15HH RSCAN0.GAFLM15.UINT8[HH]
+#define RSCAN0GAFLP015 RSCAN0.GAFLP015.UINT32
+#define RSCAN0GAFLP015L RSCAN0.GAFLP015.UINT16[L]
+#define RSCAN0GAFLP015LL RSCAN0.GAFLP015.UINT8[LL]
+#define RSCAN0GAFLP015LH RSCAN0.GAFLP015.UINT8[LH]
+#define RSCAN0GAFLP015H RSCAN0.GAFLP015.UINT16[H]
+#define RSCAN0GAFLP015HL RSCAN0.GAFLP015.UINT8[HL]
+#define RSCAN0GAFLP015HH RSCAN0.GAFLP015.UINT8[HH]
+#define RSCAN0GAFLP115 RSCAN0.GAFLP115.UINT32
+#define RSCAN0GAFLP115L RSCAN0.GAFLP115.UINT16[L]
+#define RSCAN0GAFLP115LL RSCAN0.GAFLP115.UINT8[LL]
+#define RSCAN0GAFLP115LH RSCAN0.GAFLP115.UINT8[LH]
+#define RSCAN0GAFLP115H RSCAN0.GAFLP115.UINT16[H]
+#define RSCAN0GAFLP115HL RSCAN0.GAFLP115.UINT8[HL]
+#define RSCAN0GAFLP115HH RSCAN0.GAFLP115.UINT8[HH]
+#define RSCAN0RMID0 RSCAN0.RMID0.UINT32
+#define RSCAN0RMID0L RSCAN0.RMID0.UINT16[L]
+#define RSCAN0RMID0LL RSCAN0.RMID0.UINT8[LL]
+#define RSCAN0RMID0LH RSCAN0.RMID0.UINT8[LH]
+#define RSCAN0RMID0H RSCAN0.RMID0.UINT16[H]
+#define RSCAN0RMID0HL RSCAN0.RMID0.UINT8[HL]
+#define RSCAN0RMID0HH RSCAN0.RMID0.UINT8[HH]
+#define RSCAN0RMPTR0 RSCAN0.RMPTR0.UINT32
+#define RSCAN0RMPTR0L RSCAN0.RMPTR0.UINT16[L]
+#define RSCAN0RMPTR0LL RSCAN0.RMPTR0.UINT8[LL]
+#define RSCAN0RMPTR0LH RSCAN0.RMPTR0.UINT8[LH]
+#define RSCAN0RMPTR0H RSCAN0.RMPTR0.UINT16[H]
+#define RSCAN0RMPTR0HL RSCAN0.RMPTR0.UINT8[HL]
+#define RSCAN0RMPTR0HH RSCAN0.RMPTR0.UINT8[HH]
+#define RSCAN0RMDF00 RSCAN0.RMDF00.UINT32
+#define RSCAN0RMDF00L RSCAN0.RMDF00.UINT16[L]
+#define RSCAN0RMDF00LL RSCAN0.RMDF00.UINT8[LL]
+#define RSCAN0RMDF00LH RSCAN0.RMDF00.UINT8[LH]
+#define RSCAN0RMDF00H RSCAN0.RMDF00.UINT16[H]
+#define RSCAN0RMDF00HL RSCAN0.RMDF00.UINT8[HL]
+#define RSCAN0RMDF00HH RSCAN0.RMDF00.UINT8[HH]
+#define RSCAN0RMDF10 RSCAN0.RMDF10.UINT32
+#define RSCAN0RMDF10L RSCAN0.RMDF10.UINT16[L]
+#define RSCAN0RMDF10LL RSCAN0.RMDF10.UINT8[LL]
+#define RSCAN0RMDF10LH RSCAN0.RMDF10.UINT8[LH]
+#define RSCAN0RMDF10H RSCAN0.RMDF10.UINT16[H]
+#define RSCAN0RMDF10HL RSCAN0.RMDF10.UINT8[HL]
+#define RSCAN0RMDF10HH RSCAN0.RMDF10.UINT8[HH]
+#define RSCAN0RMID1 RSCAN0.RMID1.UINT32
+#define RSCAN0RMID1L RSCAN0.RMID1.UINT16[L]
+#define RSCAN0RMID1LL RSCAN0.RMID1.UINT8[LL]
+#define RSCAN0RMID1LH RSCAN0.RMID1.UINT8[LH]
+#define RSCAN0RMID1H RSCAN0.RMID1.UINT16[H]
+#define RSCAN0RMID1HL RSCAN0.RMID1.UINT8[HL]
+#define RSCAN0RMID1HH RSCAN0.RMID1.UINT8[HH]
+#define RSCAN0RMPTR1 RSCAN0.RMPTR1.UINT32
+#define RSCAN0RMPTR1L RSCAN0.RMPTR1.UINT16[L]
+#define RSCAN0RMPTR1LL RSCAN0.RMPTR1.UINT8[LL]
+#define RSCAN0RMPTR1LH RSCAN0.RMPTR1.UINT8[LH]
+#define RSCAN0RMPTR1H RSCAN0.RMPTR1.UINT16[H]
+#define RSCAN0RMPTR1HL RSCAN0.RMPTR1.UINT8[HL]
+#define RSCAN0RMPTR1HH RSCAN0.RMPTR1.UINT8[HH]
+#define RSCAN0RMDF01 RSCAN0.RMDF01.UINT32
+#define RSCAN0RMDF01L RSCAN0.RMDF01.UINT16[L]
+#define RSCAN0RMDF01LL RSCAN0.RMDF01.UINT8[LL]
+#define RSCAN0RMDF01LH RSCAN0.RMDF01.UINT8[LH]
+#define RSCAN0RMDF01H RSCAN0.RMDF01.UINT16[H]
+#define RSCAN0RMDF01HL RSCAN0.RMDF01.UINT8[HL]
+#define RSCAN0RMDF01HH RSCAN0.RMDF01.UINT8[HH]
+#define RSCAN0RMDF11 RSCAN0.RMDF11.UINT32
+#define RSCAN0RMDF11L RSCAN0.RMDF11.UINT16[L]
+#define RSCAN0RMDF11LL RSCAN0.RMDF11.UINT8[LL]
+#define RSCAN0RMDF11LH RSCAN0.RMDF11.UINT8[LH]
+#define RSCAN0RMDF11H RSCAN0.RMDF11.UINT16[H]
+#define RSCAN0RMDF11HL RSCAN0.RMDF11.UINT8[HL]
+#define RSCAN0RMDF11HH RSCAN0.RMDF11.UINT8[HH]
+#define RSCAN0RMID2 RSCAN0.RMID2.UINT32
+#define RSCAN0RMID2L RSCAN0.RMID2.UINT16[L]
+#define RSCAN0RMID2LL RSCAN0.RMID2.UINT8[LL]
+#define RSCAN0RMID2LH RSCAN0.RMID2.UINT8[LH]
+#define RSCAN0RMID2H RSCAN0.RMID2.UINT16[H]
+#define RSCAN0RMID2HL RSCAN0.RMID2.UINT8[HL]
+#define RSCAN0RMID2HH RSCAN0.RMID2.UINT8[HH]
+#define RSCAN0RMPTR2 RSCAN0.RMPTR2.UINT32
+#define RSCAN0RMPTR2L RSCAN0.RMPTR2.UINT16[L]
+#define RSCAN0RMPTR2LL RSCAN0.RMPTR2.UINT8[LL]
+#define RSCAN0RMPTR2LH RSCAN0.RMPTR2.UINT8[LH]
+#define RSCAN0RMPTR2H RSCAN0.RMPTR2.UINT16[H]
+#define RSCAN0RMPTR2HL RSCAN0.RMPTR2.UINT8[HL]
+#define RSCAN0RMPTR2HH RSCAN0.RMPTR2.UINT8[HH]
+#define RSCAN0RMDF02 RSCAN0.RMDF02.UINT32
+#define RSCAN0RMDF02L RSCAN0.RMDF02.UINT16[L]
+#define RSCAN0RMDF02LL RSCAN0.RMDF02.UINT8[LL]
+#define RSCAN0RMDF02LH RSCAN0.RMDF02.UINT8[LH]
+#define RSCAN0RMDF02H RSCAN0.RMDF02.UINT16[H]
+#define RSCAN0RMDF02HL RSCAN0.RMDF02.UINT8[HL]
+#define RSCAN0RMDF02HH RSCAN0.RMDF02.UINT8[HH]
+#define RSCAN0RMDF12 RSCAN0.RMDF12.UINT32
+#define RSCAN0RMDF12L RSCAN0.RMDF12.UINT16[L]
+#define RSCAN0RMDF12LL RSCAN0.RMDF12.UINT8[LL]
+#define RSCAN0RMDF12LH RSCAN0.RMDF12.UINT8[LH]
+#define RSCAN0RMDF12H RSCAN0.RMDF12.UINT16[H]
+#define RSCAN0RMDF12HL RSCAN0.RMDF12.UINT8[HL]
+#define RSCAN0RMDF12HH RSCAN0.RMDF12.UINT8[HH]
+#define RSCAN0RMID3 RSCAN0.RMID3.UINT32
+#define RSCAN0RMID3L RSCAN0.RMID3.UINT16[L]
+#define RSCAN0RMID3LL RSCAN0.RMID3.UINT8[LL]
+#define RSCAN0RMID3LH RSCAN0.RMID3.UINT8[LH]
+#define RSCAN0RMID3H RSCAN0.RMID3.UINT16[H]
+#define RSCAN0RMID3HL RSCAN0.RMID3.UINT8[HL]
+#define RSCAN0RMID3HH RSCAN0.RMID3.UINT8[HH]
+#define RSCAN0RMPTR3 RSCAN0.RMPTR3.UINT32
+#define RSCAN0RMPTR3L RSCAN0.RMPTR3.UINT16[L]
+#define RSCAN0RMPTR3LL RSCAN0.RMPTR3.UINT8[LL]
+#define RSCAN0RMPTR3LH RSCAN0.RMPTR3.UINT8[LH]
+#define RSCAN0RMPTR3H RSCAN0.RMPTR3.UINT16[H]
+#define RSCAN0RMPTR3HL RSCAN0.RMPTR3.UINT8[HL]
+#define RSCAN0RMPTR3HH RSCAN0.RMPTR3.UINT8[HH]
+#define RSCAN0RMDF03 RSCAN0.RMDF03.UINT32
+#define RSCAN0RMDF03L RSCAN0.RMDF03.UINT16[L]
+#define RSCAN0RMDF03LL RSCAN0.RMDF03.UINT8[LL]
+#define RSCAN0RMDF03LH RSCAN0.RMDF03.UINT8[LH]
+#define RSCAN0RMDF03H RSCAN0.RMDF03.UINT16[H]
+#define RSCAN0RMDF03HL RSCAN0.RMDF03.UINT8[HL]
+#define RSCAN0RMDF03HH RSCAN0.RMDF03.UINT8[HH]
+#define RSCAN0RMDF13 RSCAN0.RMDF13.UINT32
+#define RSCAN0RMDF13L RSCAN0.RMDF13.UINT16[L]
+#define RSCAN0RMDF13LL RSCAN0.RMDF13.UINT8[LL]
+#define RSCAN0RMDF13LH RSCAN0.RMDF13.UINT8[LH]
+#define RSCAN0RMDF13H RSCAN0.RMDF13.UINT16[H]
+#define RSCAN0RMDF13HL RSCAN0.RMDF13.UINT8[HL]
+#define RSCAN0RMDF13HH RSCAN0.RMDF13.UINT8[HH]
+#define RSCAN0RMID4 RSCAN0.RMID4.UINT32
+#define RSCAN0RMID4L RSCAN0.RMID4.UINT16[L]
+#define RSCAN0RMID4LL RSCAN0.RMID4.UINT8[LL]
+#define RSCAN0RMID4LH RSCAN0.RMID4.UINT8[LH]
+#define RSCAN0RMID4H RSCAN0.RMID4.UINT16[H]
+#define RSCAN0RMID4HL RSCAN0.RMID4.UINT8[HL]
+#define RSCAN0RMID4HH RSCAN0.RMID4.UINT8[HH]
+#define RSCAN0RMPTR4 RSCAN0.RMPTR4.UINT32
+#define RSCAN0RMPTR4L RSCAN0.RMPTR4.UINT16[L]
+#define RSCAN0RMPTR4LL RSCAN0.RMPTR4.UINT8[LL]
+#define RSCAN0RMPTR4LH RSCAN0.RMPTR4.UINT8[LH]
+#define RSCAN0RMPTR4H RSCAN0.RMPTR4.UINT16[H]
+#define RSCAN0RMPTR4HL RSCAN0.RMPTR4.UINT8[HL]
+#define RSCAN0RMPTR4HH RSCAN0.RMPTR4.UINT8[HH]
+#define RSCAN0RMDF04 RSCAN0.RMDF04.UINT32
+#define RSCAN0RMDF04L RSCAN0.RMDF04.UINT16[L]
+#define RSCAN0RMDF04LL RSCAN0.RMDF04.UINT8[LL]
+#define RSCAN0RMDF04LH RSCAN0.RMDF04.UINT8[LH]
+#define RSCAN0RMDF04H RSCAN0.RMDF04.UINT16[H]
+#define RSCAN0RMDF04HL RSCAN0.RMDF04.UINT8[HL]
+#define RSCAN0RMDF04HH RSCAN0.RMDF04.UINT8[HH]
+#define RSCAN0RMDF14 RSCAN0.RMDF14.UINT32
+#define RSCAN0RMDF14L RSCAN0.RMDF14.UINT16[L]
+#define RSCAN0RMDF14LL RSCAN0.RMDF14.UINT8[LL]
+#define RSCAN0RMDF14LH RSCAN0.RMDF14.UINT8[LH]
+#define RSCAN0RMDF14H RSCAN0.RMDF14.UINT16[H]
+#define RSCAN0RMDF14HL RSCAN0.RMDF14.UINT8[HL]
+#define RSCAN0RMDF14HH RSCAN0.RMDF14.UINT8[HH]
+#define RSCAN0RMID5 RSCAN0.RMID5.UINT32
+#define RSCAN0RMID5L RSCAN0.RMID5.UINT16[L]
+#define RSCAN0RMID5LL RSCAN0.RMID5.UINT8[LL]
+#define RSCAN0RMID5LH RSCAN0.RMID5.UINT8[LH]
+#define RSCAN0RMID5H RSCAN0.RMID5.UINT16[H]
+#define RSCAN0RMID5HL RSCAN0.RMID5.UINT8[HL]
+#define RSCAN0RMID5HH RSCAN0.RMID5.UINT8[HH]
+#define RSCAN0RMPTR5 RSCAN0.RMPTR5.UINT32
+#define RSCAN0RMPTR5L RSCAN0.RMPTR5.UINT16[L]
+#define RSCAN0RMPTR5LL RSCAN0.RMPTR5.UINT8[LL]
+#define RSCAN0RMPTR5LH RSCAN0.RMPTR5.UINT8[LH]
+#define RSCAN0RMPTR5H RSCAN0.RMPTR5.UINT16[H]
+#define RSCAN0RMPTR5HL RSCAN0.RMPTR5.UINT8[HL]
+#define RSCAN0RMPTR5HH RSCAN0.RMPTR5.UINT8[HH]
+#define RSCAN0RMDF05 RSCAN0.RMDF05.UINT32
+#define RSCAN0RMDF05L RSCAN0.RMDF05.UINT16[L]
+#define RSCAN0RMDF05LL RSCAN0.RMDF05.UINT8[LL]
+#define RSCAN0RMDF05LH RSCAN0.RMDF05.UINT8[LH]
+#define RSCAN0RMDF05H RSCAN0.RMDF05.UINT16[H]
+#define RSCAN0RMDF05HL RSCAN0.RMDF05.UINT8[HL]
+#define RSCAN0RMDF05HH RSCAN0.RMDF05.UINT8[HH]
+#define RSCAN0RMDF15 RSCAN0.RMDF15.UINT32
+#define RSCAN0RMDF15L RSCAN0.RMDF15.UINT16[L]
+#define RSCAN0RMDF15LL RSCAN0.RMDF15.UINT8[LL]
+#define RSCAN0RMDF15LH RSCAN0.RMDF15.UINT8[LH]
+#define RSCAN0RMDF15H RSCAN0.RMDF15.UINT16[H]
+#define RSCAN0RMDF15HL RSCAN0.RMDF15.UINT8[HL]
+#define RSCAN0RMDF15HH RSCAN0.RMDF15.UINT8[HH]
+#define RSCAN0RMID6 RSCAN0.RMID6.UINT32
+#define RSCAN0RMID6L RSCAN0.RMID6.UINT16[L]
+#define RSCAN0RMID6LL RSCAN0.RMID6.UINT8[LL]
+#define RSCAN0RMID6LH RSCAN0.RMID6.UINT8[LH]
+#define RSCAN0RMID6H RSCAN0.RMID6.UINT16[H]
+#define RSCAN0RMID6HL RSCAN0.RMID6.UINT8[HL]
+#define RSCAN0RMID6HH RSCAN0.RMID6.UINT8[HH]
+#define RSCAN0RMPTR6 RSCAN0.RMPTR6.UINT32
+#define RSCAN0RMPTR6L RSCAN0.RMPTR6.UINT16[L]
+#define RSCAN0RMPTR6LL RSCAN0.RMPTR6.UINT8[LL]
+#define RSCAN0RMPTR6LH RSCAN0.RMPTR6.UINT8[LH]
+#define RSCAN0RMPTR6H RSCAN0.RMPTR6.UINT16[H]
+#define RSCAN0RMPTR6HL RSCAN0.RMPTR6.UINT8[HL]
+#define RSCAN0RMPTR6HH RSCAN0.RMPTR6.UINT8[HH]
+#define RSCAN0RMDF06 RSCAN0.RMDF06.UINT32
+#define RSCAN0RMDF06L RSCAN0.RMDF06.UINT16[L]
+#define RSCAN0RMDF06LL RSCAN0.RMDF06.UINT8[LL]
+#define RSCAN0RMDF06LH RSCAN0.RMDF06.UINT8[LH]
+#define RSCAN0RMDF06H RSCAN0.RMDF06.UINT16[H]
+#define RSCAN0RMDF06HL RSCAN0.RMDF06.UINT8[HL]
+#define RSCAN0RMDF06HH RSCAN0.RMDF06.UINT8[HH]
+#define RSCAN0RMDF16 RSCAN0.RMDF16.UINT32
+#define RSCAN0RMDF16L RSCAN0.RMDF16.UINT16[L]
+#define RSCAN0RMDF16LL RSCAN0.RMDF16.UINT8[LL]
+#define RSCAN0RMDF16LH RSCAN0.RMDF16.UINT8[LH]
+#define RSCAN0RMDF16H RSCAN0.RMDF16.UINT16[H]
+#define RSCAN0RMDF16HL RSCAN0.RMDF16.UINT8[HL]
+#define RSCAN0RMDF16HH RSCAN0.RMDF16.UINT8[HH]
+#define RSCAN0RMID7 RSCAN0.RMID7.UINT32
+#define RSCAN0RMID7L RSCAN0.RMID7.UINT16[L]
+#define RSCAN0RMID7LL RSCAN0.RMID7.UINT8[LL]
+#define RSCAN0RMID7LH RSCAN0.RMID7.UINT8[LH]
+#define RSCAN0RMID7H RSCAN0.RMID7.UINT16[H]
+#define RSCAN0RMID7HL RSCAN0.RMID7.UINT8[HL]
+#define RSCAN0RMID7HH RSCAN0.RMID7.UINT8[HH]
+#define RSCAN0RMPTR7 RSCAN0.RMPTR7.UINT32
+#define RSCAN0RMPTR7L RSCAN0.RMPTR7.UINT16[L]
+#define RSCAN0RMPTR7LL RSCAN0.RMPTR7.UINT8[LL]
+#define RSCAN0RMPTR7LH RSCAN0.RMPTR7.UINT8[LH]
+#define RSCAN0RMPTR7H RSCAN0.RMPTR7.UINT16[H]
+#define RSCAN0RMPTR7HL RSCAN0.RMPTR7.UINT8[HL]
+#define RSCAN0RMPTR7HH RSCAN0.RMPTR7.UINT8[HH]
+#define RSCAN0RMDF07 RSCAN0.RMDF07.UINT32
+#define RSCAN0RMDF07L RSCAN0.RMDF07.UINT16[L]
+#define RSCAN0RMDF07LL RSCAN0.RMDF07.UINT8[LL]
+#define RSCAN0RMDF07LH RSCAN0.RMDF07.UINT8[LH]
+#define RSCAN0RMDF07H RSCAN0.RMDF07.UINT16[H]
+#define RSCAN0RMDF07HL RSCAN0.RMDF07.UINT8[HL]
+#define RSCAN0RMDF07HH RSCAN0.RMDF07.UINT8[HH]
+#define RSCAN0RMDF17 RSCAN0.RMDF17.UINT32
+#define RSCAN0RMDF17L RSCAN0.RMDF17.UINT16[L]
+#define RSCAN0RMDF17LL RSCAN0.RMDF17.UINT8[LL]
+#define RSCAN0RMDF17LH RSCAN0.RMDF17.UINT8[LH]
+#define RSCAN0RMDF17H RSCAN0.RMDF17.UINT16[H]
+#define RSCAN0RMDF17HL RSCAN0.RMDF17.UINT8[HL]
+#define RSCAN0RMDF17HH RSCAN0.RMDF17.UINT8[HH]
+#define RSCAN0RMID8 RSCAN0.RMID8.UINT32
+#define RSCAN0RMID8L RSCAN0.RMID8.UINT16[L]
+#define RSCAN0RMID8LL RSCAN0.RMID8.UINT8[LL]
+#define RSCAN0RMID8LH RSCAN0.RMID8.UINT8[LH]
+#define RSCAN0RMID8H RSCAN0.RMID8.UINT16[H]
+#define RSCAN0RMID8HL RSCAN0.RMID8.UINT8[HL]
+#define RSCAN0RMID8HH RSCAN0.RMID8.UINT8[HH]
+#define RSCAN0RMPTR8 RSCAN0.RMPTR8.UINT32
+#define RSCAN0RMPTR8L RSCAN0.RMPTR8.UINT16[L]
+#define RSCAN0RMPTR8LL RSCAN0.RMPTR8.UINT8[LL]
+#define RSCAN0RMPTR8LH RSCAN0.RMPTR8.UINT8[LH]
+#define RSCAN0RMPTR8H RSCAN0.RMPTR8.UINT16[H]
+#define RSCAN0RMPTR8HL RSCAN0.RMPTR8.UINT8[HL]
+#define RSCAN0RMPTR8HH RSCAN0.RMPTR8.UINT8[HH]
+#define RSCAN0RMDF08 RSCAN0.RMDF08.UINT32
+#define RSCAN0RMDF08L RSCAN0.RMDF08.UINT16[L]
+#define RSCAN0RMDF08LL RSCAN0.RMDF08.UINT8[LL]
+#define RSCAN0RMDF08LH RSCAN0.RMDF08.UINT8[LH]
+#define RSCAN0RMDF08H RSCAN0.RMDF08.UINT16[H]
+#define RSCAN0RMDF08HL RSCAN0.RMDF08.UINT8[HL]
+#define RSCAN0RMDF08HH RSCAN0.RMDF08.UINT8[HH]
+#define RSCAN0RMDF18 RSCAN0.RMDF18.UINT32
+#define RSCAN0RMDF18L RSCAN0.RMDF18.UINT16[L]
+#define RSCAN0RMDF18LL RSCAN0.RMDF18.UINT8[LL]
+#define RSCAN0RMDF18LH RSCAN0.RMDF18.UINT8[LH]
+#define RSCAN0RMDF18H RSCAN0.RMDF18.UINT16[H]
+#define RSCAN0RMDF18HL RSCAN0.RMDF18.UINT8[HL]
+#define RSCAN0RMDF18HH RSCAN0.RMDF18.UINT8[HH]
+#define RSCAN0RMID9 RSCAN0.RMID9.UINT32
+#define RSCAN0RMID9L RSCAN0.RMID9.UINT16[L]
+#define RSCAN0RMID9LL RSCAN0.RMID9.UINT8[LL]
+#define RSCAN0RMID9LH RSCAN0.RMID9.UINT8[LH]
+#define RSCAN0RMID9H RSCAN0.RMID9.UINT16[H]
+#define RSCAN0RMID9HL RSCAN0.RMID9.UINT8[HL]
+#define RSCAN0RMID9HH RSCAN0.RMID9.UINT8[HH]
+#define RSCAN0RMPTR9 RSCAN0.RMPTR9.UINT32
+#define RSCAN0RMPTR9L RSCAN0.RMPTR9.UINT16[L]
+#define RSCAN0RMPTR9LL RSCAN0.RMPTR9.UINT8[LL]
+#define RSCAN0RMPTR9LH RSCAN0.RMPTR9.UINT8[LH]
+#define RSCAN0RMPTR9H RSCAN0.RMPTR9.UINT16[H]
+#define RSCAN0RMPTR9HL RSCAN0.RMPTR9.UINT8[HL]
+#define RSCAN0RMPTR9HH RSCAN0.RMPTR9.UINT8[HH]
+#define RSCAN0RMDF09 RSCAN0.RMDF09.UINT32
+#define RSCAN0RMDF09L RSCAN0.RMDF09.UINT16[L]
+#define RSCAN0RMDF09LL RSCAN0.RMDF09.UINT8[LL]
+#define RSCAN0RMDF09LH RSCAN0.RMDF09.UINT8[LH]
+#define RSCAN0RMDF09H RSCAN0.RMDF09.UINT16[H]
+#define RSCAN0RMDF09HL RSCAN0.RMDF09.UINT8[HL]
+#define RSCAN0RMDF09HH RSCAN0.RMDF09.UINT8[HH]
+#define RSCAN0RMDF19 RSCAN0.RMDF19.UINT32
+#define RSCAN0RMDF19L RSCAN0.RMDF19.UINT16[L]
+#define RSCAN0RMDF19LL RSCAN0.RMDF19.UINT8[LL]
+#define RSCAN0RMDF19LH RSCAN0.RMDF19.UINT8[LH]
+#define RSCAN0RMDF19H RSCAN0.RMDF19.UINT16[H]
+#define RSCAN0RMDF19HL RSCAN0.RMDF19.UINT8[HL]
+#define RSCAN0RMDF19HH RSCAN0.RMDF19.UINT8[HH]
+#define RSCAN0RMID10 RSCAN0.RMID10.UINT32
+#define RSCAN0RMID10L RSCAN0.RMID10.UINT16[L]
+#define RSCAN0RMID10LL RSCAN0.RMID10.UINT8[LL]
+#define RSCAN0RMID10LH RSCAN0.RMID10.UINT8[LH]
+#define RSCAN0RMID10H RSCAN0.RMID10.UINT16[H]
+#define RSCAN0RMID10HL RSCAN0.RMID10.UINT8[HL]
+#define RSCAN0RMID10HH RSCAN0.RMID10.UINT8[HH]
+#define RSCAN0RMPTR10 RSCAN0.RMPTR10.UINT32
+#define RSCAN0RMPTR10L RSCAN0.RMPTR10.UINT16[L]
+#define RSCAN0RMPTR10LL RSCAN0.RMPTR10.UINT8[LL]
+#define RSCAN0RMPTR10LH RSCAN0.RMPTR10.UINT8[LH]
+#define RSCAN0RMPTR10H RSCAN0.RMPTR10.UINT16[H]
+#define RSCAN0RMPTR10HL RSCAN0.RMPTR10.UINT8[HL]
+#define RSCAN0RMPTR10HH RSCAN0.RMPTR10.UINT8[HH]
+#define RSCAN0RMDF010 RSCAN0.RMDF010.UINT32
+#define RSCAN0RMDF010L RSCAN0.RMDF010.UINT16[L]
+#define RSCAN0RMDF010LL RSCAN0.RMDF010.UINT8[LL]
+#define RSCAN0RMDF010LH RSCAN0.RMDF010.UINT8[LH]
+#define RSCAN0RMDF010H RSCAN0.RMDF010.UINT16[H]
+#define RSCAN0RMDF010HL RSCAN0.RMDF010.UINT8[HL]
+#define RSCAN0RMDF010HH RSCAN0.RMDF010.UINT8[HH]
+#define RSCAN0RMDF110 RSCAN0.RMDF110.UINT32
+#define RSCAN0RMDF110L RSCAN0.RMDF110.UINT16[L]
+#define RSCAN0RMDF110LL RSCAN0.RMDF110.UINT8[LL]
+#define RSCAN0RMDF110LH RSCAN0.RMDF110.UINT8[LH]
+#define RSCAN0RMDF110H RSCAN0.RMDF110.UINT16[H]
+#define RSCAN0RMDF110HL RSCAN0.RMDF110.UINT8[HL]
+#define RSCAN0RMDF110HH RSCAN0.RMDF110.UINT8[HH]
+#define RSCAN0RMID11 RSCAN0.RMID11.UINT32
+#define RSCAN0RMID11L RSCAN0.RMID11.UINT16[L]
+#define RSCAN0RMID11LL RSCAN0.RMID11.UINT8[LL]
+#define RSCAN0RMID11LH RSCAN0.RMID11.UINT8[LH]
+#define RSCAN0RMID11H RSCAN0.RMID11.UINT16[H]
+#define RSCAN0RMID11HL RSCAN0.RMID11.UINT8[HL]
+#define RSCAN0RMID11HH RSCAN0.RMID11.UINT8[HH]
+#define RSCAN0RMPTR11 RSCAN0.RMPTR11.UINT32
+#define RSCAN0RMPTR11L RSCAN0.RMPTR11.UINT16[L]
+#define RSCAN0RMPTR11LL RSCAN0.RMPTR11.UINT8[LL]
+#define RSCAN0RMPTR11LH RSCAN0.RMPTR11.UINT8[LH]
+#define RSCAN0RMPTR11H RSCAN0.RMPTR11.UINT16[H]
+#define RSCAN0RMPTR11HL RSCAN0.RMPTR11.UINT8[HL]
+#define RSCAN0RMPTR11HH RSCAN0.RMPTR11.UINT8[HH]
+#define RSCAN0RMDF011 RSCAN0.RMDF011.UINT32
+#define RSCAN0RMDF011L RSCAN0.RMDF011.UINT16[L]
+#define RSCAN0RMDF011LL RSCAN0.RMDF011.UINT8[LL]
+#define RSCAN0RMDF011LH RSCAN0.RMDF011.UINT8[LH]
+#define RSCAN0RMDF011H RSCAN0.RMDF011.UINT16[H]
+#define RSCAN0RMDF011HL RSCAN0.RMDF011.UINT8[HL]
+#define RSCAN0RMDF011HH RSCAN0.RMDF011.UINT8[HH]
+#define RSCAN0RMDF111 RSCAN0.RMDF111.UINT32
+#define RSCAN0RMDF111L RSCAN0.RMDF111.UINT16[L]
+#define RSCAN0RMDF111LL RSCAN0.RMDF111.UINT8[LL]
+#define RSCAN0RMDF111LH RSCAN0.RMDF111.UINT8[LH]
+#define RSCAN0RMDF111H RSCAN0.RMDF111.UINT16[H]
+#define RSCAN0RMDF111HL RSCAN0.RMDF111.UINT8[HL]
+#define RSCAN0RMDF111HH RSCAN0.RMDF111.UINT8[HH]
+#define RSCAN0RMID12 RSCAN0.RMID12.UINT32
+#define RSCAN0RMID12L RSCAN0.RMID12.UINT16[L]
+#define RSCAN0RMID12LL RSCAN0.RMID12.UINT8[LL]
+#define RSCAN0RMID12LH RSCAN0.RMID12.UINT8[LH]
+#define RSCAN0RMID12H RSCAN0.RMID12.UINT16[H]
+#define RSCAN0RMID12HL RSCAN0.RMID12.UINT8[HL]
+#define RSCAN0RMID12HH RSCAN0.RMID12.UINT8[HH]
+#define RSCAN0RMPTR12 RSCAN0.RMPTR12.UINT32
+#define RSCAN0RMPTR12L RSCAN0.RMPTR12.UINT16[L]
+#define RSCAN0RMPTR12LL RSCAN0.RMPTR12.UINT8[LL]
+#define RSCAN0RMPTR12LH RSCAN0.RMPTR12.UINT8[LH]
+#define RSCAN0RMPTR12H RSCAN0.RMPTR12.UINT16[H]
+#define RSCAN0RMPTR12HL RSCAN0.RMPTR12.UINT8[HL]
+#define RSCAN0RMPTR12HH RSCAN0.RMPTR12.UINT8[HH]
+#define RSCAN0RMDF012 RSCAN0.RMDF012.UINT32
+#define RSCAN0RMDF012L RSCAN0.RMDF012.UINT16[L]
+#define RSCAN0RMDF012LL RSCAN0.RMDF012.UINT8[LL]
+#define RSCAN0RMDF012LH RSCAN0.RMDF012.UINT8[LH]
+#define RSCAN0RMDF012H RSCAN0.RMDF012.UINT16[H]
+#define RSCAN0RMDF012HL RSCAN0.RMDF012.UINT8[HL]
+#define RSCAN0RMDF012HH RSCAN0.RMDF012.UINT8[HH]
+#define RSCAN0RMDF112 RSCAN0.RMDF112.UINT32
+#define RSCAN0RMDF112L RSCAN0.RMDF112.UINT16[L]
+#define RSCAN0RMDF112LL RSCAN0.RMDF112.UINT8[LL]
+#define RSCAN0RMDF112LH RSCAN0.RMDF112.UINT8[LH]
+#define RSCAN0RMDF112H RSCAN0.RMDF112.UINT16[H]
+#define RSCAN0RMDF112HL RSCAN0.RMDF112.UINT8[HL]
+#define RSCAN0RMDF112HH RSCAN0.RMDF112.UINT8[HH]
+#define RSCAN0RMID13 RSCAN0.RMID13.UINT32
+#define RSCAN0RMID13L RSCAN0.RMID13.UINT16[L]
+#define RSCAN0RMID13LL RSCAN0.RMID13.UINT8[LL]
+#define RSCAN0RMID13LH RSCAN0.RMID13.UINT8[LH]
+#define RSCAN0RMID13H RSCAN0.RMID13.UINT16[H]
+#define RSCAN0RMID13HL RSCAN0.RMID13.UINT8[HL]
+#define RSCAN0RMID13HH RSCAN0.RMID13.UINT8[HH]
+#define RSCAN0RMPTR13 RSCAN0.RMPTR13.UINT32
+#define RSCAN0RMPTR13L RSCAN0.RMPTR13.UINT16[L]
+#define RSCAN0RMPTR13LL RSCAN0.RMPTR13.UINT8[LL]
+#define RSCAN0RMPTR13LH RSCAN0.RMPTR13.UINT8[LH]
+#define RSCAN0RMPTR13H RSCAN0.RMPTR13.UINT16[H]
+#define RSCAN0RMPTR13HL RSCAN0.RMPTR13.UINT8[HL]
+#define RSCAN0RMPTR13HH RSCAN0.RMPTR13.UINT8[HH]
+#define RSCAN0RMDF013 RSCAN0.RMDF013.UINT32
+#define RSCAN0RMDF013L RSCAN0.RMDF013.UINT16[L]
+#define RSCAN0RMDF013LL RSCAN0.RMDF013.UINT8[LL]
+#define RSCAN0RMDF013LH RSCAN0.RMDF013.UINT8[LH]
+#define RSCAN0RMDF013H RSCAN0.RMDF013.UINT16[H]
+#define RSCAN0RMDF013HL RSCAN0.RMDF013.UINT8[HL]
+#define RSCAN0RMDF013HH RSCAN0.RMDF013.UINT8[HH]
+#define RSCAN0RMDF113 RSCAN0.RMDF113.UINT32
+#define RSCAN0RMDF113L RSCAN0.RMDF113.UINT16[L]
+#define RSCAN0RMDF113LL RSCAN0.RMDF113.UINT8[LL]
+#define RSCAN0RMDF113LH RSCAN0.RMDF113.UINT8[LH]
+#define RSCAN0RMDF113H RSCAN0.RMDF113.UINT16[H]
+#define RSCAN0RMDF113HL RSCAN0.RMDF113.UINT8[HL]
+#define RSCAN0RMDF113HH RSCAN0.RMDF113.UINT8[HH]
+#define RSCAN0RMID14 RSCAN0.RMID14.UINT32
+#define RSCAN0RMID14L RSCAN0.RMID14.UINT16[L]
+#define RSCAN0RMID14LL RSCAN0.RMID14.UINT8[LL]
+#define RSCAN0RMID14LH RSCAN0.RMID14.UINT8[LH]
+#define RSCAN0RMID14H RSCAN0.RMID14.UINT16[H]
+#define RSCAN0RMID14HL RSCAN0.RMID14.UINT8[HL]
+#define RSCAN0RMID14HH RSCAN0.RMID14.UINT8[HH]
+#define RSCAN0RMPTR14 RSCAN0.RMPTR14.UINT32
+#define RSCAN0RMPTR14L RSCAN0.RMPTR14.UINT16[L]
+#define RSCAN0RMPTR14LL RSCAN0.RMPTR14.UINT8[LL]
+#define RSCAN0RMPTR14LH RSCAN0.RMPTR14.UINT8[LH]
+#define RSCAN0RMPTR14H RSCAN0.RMPTR14.UINT16[H]
+#define RSCAN0RMPTR14HL RSCAN0.RMPTR14.UINT8[HL]
+#define RSCAN0RMPTR14HH RSCAN0.RMPTR14.UINT8[HH]
+#define RSCAN0RMDF014 RSCAN0.RMDF014.UINT32
+#define RSCAN0RMDF014L RSCAN0.RMDF014.UINT16[L]
+#define RSCAN0RMDF014LL RSCAN0.RMDF014.UINT8[LL]
+#define RSCAN0RMDF014LH RSCAN0.RMDF014.UINT8[LH]
+#define RSCAN0RMDF014H RSCAN0.RMDF014.UINT16[H]
+#define RSCAN0RMDF014HL RSCAN0.RMDF014.UINT8[HL]
+#define RSCAN0RMDF014HH RSCAN0.RMDF014.UINT8[HH]
+#define RSCAN0RMDF114 RSCAN0.RMDF114.UINT32
+#define RSCAN0RMDF114L RSCAN0.RMDF114.UINT16[L]
+#define RSCAN0RMDF114LL RSCAN0.RMDF114.UINT8[LL]
+#define RSCAN0RMDF114LH RSCAN0.RMDF114.UINT8[LH]
+#define RSCAN0RMDF114H RSCAN0.RMDF114.UINT16[H]
+#define RSCAN0RMDF114HL RSCAN0.RMDF114.UINT8[HL]
+#define RSCAN0RMDF114HH RSCAN0.RMDF114.UINT8[HH]
+#define RSCAN0RMID15 RSCAN0.RMID15.UINT32
+#define RSCAN0RMID15L RSCAN0.RMID15.UINT16[L]
+#define RSCAN0RMID15LL RSCAN0.RMID15.UINT8[LL]
+#define RSCAN0RMID15LH RSCAN0.RMID15.UINT8[LH]
+#define RSCAN0RMID15H RSCAN0.RMID15.UINT16[H]
+#define RSCAN0RMID15HL RSCAN0.RMID15.UINT8[HL]
+#define RSCAN0RMID15HH RSCAN0.RMID15.UINT8[HH]
+#define RSCAN0RMPTR15 RSCAN0.RMPTR15.UINT32
+#define RSCAN0RMPTR15L RSCAN0.RMPTR15.UINT16[L]
+#define RSCAN0RMPTR15LL RSCAN0.RMPTR15.UINT8[LL]
+#define RSCAN0RMPTR15LH RSCAN0.RMPTR15.UINT8[LH]
+#define RSCAN0RMPTR15H RSCAN0.RMPTR15.UINT16[H]
+#define RSCAN0RMPTR15HL RSCAN0.RMPTR15.UINT8[HL]
+#define RSCAN0RMPTR15HH RSCAN0.RMPTR15.UINT8[HH]
+#define RSCAN0RMDF015 RSCAN0.RMDF015.UINT32
+#define RSCAN0RMDF015L RSCAN0.RMDF015.UINT16[L]
+#define RSCAN0RMDF015LL RSCAN0.RMDF015.UINT8[LL]
+#define RSCAN0RMDF015LH RSCAN0.RMDF015.UINT8[LH]
+#define RSCAN0RMDF015H RSCAN0.RMDF015.UINT16[H]
+#define RSCAN0RMDF015HL RSCAN0.RMDF015.UINT8[HL]
+#define RSCAN0RMDF015HH RSCAN0.RMDF015.UINT8[HH]
+#define RSCAN0RMDF115 RSCAN0.RMDF115.UINT32
+#define RSCAN0RMDF115L RSCAN0.RMDF115.UINT16[L]
+#define RSCAN0RMDF115LL RSCAN0.RMDF115.UINT8[LL]
+#define RSCAN0RMDF115LH RSCAN0.RMDF115.UINT8[LH]
+#define RSCAN0RMDF115H RSCAN0.RMDF115.UINT16[H]
+#define RSCAN0RMDF115HL RSCAN0.RMDF115.UINT8[HL]
+#define RSCAN0RMDF115HH RSCAN0.RMDF115.UINT8[HH]
+#define RSCAN0RMID16 RSCAN0.RMID16.UINT32
+#define RSCAN0RMID16L RSCAN0.RMID16.UINT16[L]
+#define RSCAN0RMID16LL RSCAN0.RMID16.UINT8[LL]
+#define RSCAN0RMID16LH RSCAN0.RMID16.UINT8[LH]
+#define RSCAN0RMID16H RSCAN0.RMID16.UINT16[H]
+#define RSCAN0RMID16HL RSCAN0.RMID16.UINT8[HL]
+#define RSCAN0RMID16HH RSCAN0.RMID16.UINT8[HH]
+#define RSCAN0RMPTR16 RSCAN0.RMPTR16.UINT32
+#define RSCAN0RMPTR16L RSCAN0.RMPTR16.UINT16[L]
+#define RSCAN0RMPTR16LL RSCAN0.RMPTR16.UINT8[LL]
+#define RSCAN0RMPTR16LH RSCAN0.RMPTR16.UINT8[LH]
+#define RSCAN0RMPTR16H RSCAN0.RMPTR16.UINT16[H]
+#define RSCAN0RMPTR16HL RSCAN0.RMPTR16.UINT8[HL]
+#define RSCAN0RMPTR16HH RSCAN0.RMPTR16.UINT8[HH]
+#define RSCAN0RMDF016 RSCAN0.RMDF016.UINT32
+#define RSCAN0RMDF016L RSCAN0.RMDF016.UINT16[L]
+#define RSCAN0RMDF016LL RSCAN0.RMDF016.UINT8[LL]
+#define RSCAN0RMDF016LH RSCAN0.RMDF016.UINT8[LH]
+#define RSCAN0RMDF016H RSCAN0.RMDF016.UINT16[H]
+#define RSCAN0RMDF016HL RSCAN0.RMDF016.UINT8[HL]
+#define RSCAN0RMDF016HH RSCAN0.RMDF016.UINT8[HH]
+#define RSCAN0RMDF116 RSCAN0.RMDF116.UINT32
+#define RSCAN0RMDF116L RSCAN0.RMDF116.UINT16[L]
+#define RSCAN0RMDF116LL RSCAN0.RMDF116.UINT8[LL]
+#define RSCAN0RMDF116LH RSCAN0.RMDF116.UINT8[LH]
+#define RSCAN0RMDF116H RSCAN0.RMDF116.UINT16[H]
+#define RSCAN0RMDF116HL RSCAN0.RMDF116.UINT8[HL]
+#define RSCAN0RMDF116HH RSCAN0.RMDF116.UINT8[HH]
+#define RSCAN0RMID17 RSCAN0.RMID17.UINT32
+#define RSCAN0RMID17L RSCAN0.RMID17.UINT16[L]
+#define RSCAN0RMID17LL RSCAN0.RMID17.UINT8[LL]
+#define RSCAN0RMID17LH RSCAN0.RMID17.UINT8[LH]
+#define RSCAN0RMID17H RSCAN0.RMID17.UINT16[H]
+#define RSCAN0RMID17HL RSCAN0.RMID17.UINT8[HL]
+#define RSCAN0RMID17HH RSCAN0.RMID17.UINT8[HH]
+#define RSCAN0RMPTR17 RSCAN0.RMPTR17.UINT32
+#define RSCAN0RMPTR17L RSCAN0.RMPTR17.UINT16[L]
+#define RSCAN0RMPTR17LL RSCAN0.RMPTR17.UINT8[LL]
+#define RSCAN0RMPTR17LH RSCAN0.RMPTR17.UINT8[LH]
+#define RSCAN0RMPTR17H RSCAN0.RMPTR17.UINT16[H]
+#define RSCAN0RMPTR17HL RSCAN0.RMPTR17.UINT8[HL]
+#define RSCAN0RMPTR17HH RSCAN0.RMPTR17.UINT8[HH]
+#define RSCAN0RMDF017 RSCAN0.RMDF017.UINT32
+#define RSCAN0RMDF017L RSCAN0.RMDF017.UINT16[L]
+#define RSCAN0RMDF017LL RSCAN0.RMDF017.UINT8[LL]
+#define RSCAN0RMDF017LH RSCAN0.RMDF017.UINT8[LH]
+#define RSCAN0RMDF017H RSCAN0.RMDF017.UINT16[H]
+#define RSCAN0RMDF017HL RSCAN0.RMDF017.UINT8[HL]
+#define RSCAN0RMDF017HH RSCAN0.RMDF017.UINT8[HH]
+#define RSCAN0RMDF117 RSCAN0.RMDF117.UINT32
+#define RSCAN0RMDF117L RSCAN0.RMDF117.UINT16[L]
+#define RSCAN0RMDF117LL RSCAN0.RMDF117.UINT8[LL]
+#define RSCAN0RMDF117LH RSCAN0.RMDF117.UINT8[LH]
+#define RSCAN0RMDF117H RSCAN0.RMDF117.UINT16[H]
+#define RSCAN0RMDF117HL RSCAN0.RMDF117.UINT8[HL]
+#define RSCAN0RMDF117HH RSCAN0.RMDF117.UINT8[HH]
+#define RSCAN0RMID18 RSCAN0.RMID18.UINT32
+#define RSCAN0RMID18L RSCAN0.RMID18.UINT16[L]
+#define RSCAN0RMID18LL RSCAN0.RMID18.UINT8[LL]
+#define RSCAN0RMID18LH RSCAN0.RMID18.UINT8[LH]
+#define RSCAN0RMID18H RSCAN0.RMID18.UINT16[H]
+#define RSCAN0RMID18HL RSCAN0.RMID18.UINT8[HL]
+#define RSCAN0RMID18HH RSCAN0.RMID18.UINT8[HH]
+#define RSCAN0RMPTR18 RSCAN0.RMPTR18.UINT32
+#define RSCAN0RMPTR18L RSCAN0.RMPTR18.UINT16[L]
+#define RSCAN0RMPTR18LL RSCAN0.RMPTR18.UINT8[LL]
+#define RSCAN0RMPTR18LH RSCAN0.RMPTR18.UINT8[LH]
+#define RSCAN0RMPTR18H RSCAN0.RMPTR18.UINT16[H]
+#define RSCAN0RMPTR18HL RSCAN0.RMPTR18.UINT8[HL]
+#define RSCAN0RMPTR18HH RSCAN0.RMPTR18.UINT8[HH]
+#define RSCAN0RMDF018 RSCAN0.RMDF018.UINT32
+#define RSCAN0RMDF018L RSCAN0.RMDF018.UINT16[L]
+#define RSCAN0RMDF018LL RSCAN0.RMDF018.UINT8[LL]
+#define RSCAN0RMDF018LH RSCAN0.RMDF018.UINT8[LH]
+#define RSCAN0RMDF018H RSCAN0.RMDF018.UINT16[H]
+#define RSCAN0RMDF018HL RSCAN0.RMDF018.UINT8[HL]
+#define RSCAN0RMDF018HH RSCAN0.RMDF018.UINT8[HH]
+#define RSCAN0RMDF118 RSCAN0.RMDF118.UINT32
+#define RSCAN0RMDF118L RSCAN0.RMDF118.UINT16[L]
+#define RSCAN0RMDF118LL RSCAN0.RMDF118.UINT8[LL]
+#define RSCAN0RMDF118LH RSCAN0.RMDF118.UINT8[LH]
+#define RSCAN0RMDF118H RSCAN0.RMDF118.UINT16[H]
+#define RSCAN0RMDF118HL RSCAN0.RMDF118.UINT8[HL]
+#define RSCAN0RMDF118HH RSCAN0.RMDF118.UINT8[HH]
+#define RSCAN0RMID19 RSCAN0.RMID19.UINT32
+#define RSCAN0RMID19L RSCAN0.RMID19.UINT16[L]
+#define RSCAN0RMID19LL RSCAN0.RMID19.UINT8[LL]
+#define RSCAN0RMID19LH RSCAN0.RMID19.UINT8[LH]
+#define RSCAN0RMID19H RSCAN0.RMID19.UINT16[H]
+#define RSCAN0RMID19HL RSCAN0.RMID19.UINT8[HL]
+#define RSCAN0RMID19HH RSCAN0.RMID19.UINT8[HH]
+#define RSCAN0RMPTR19 RSCAN0.RMPTR19.UINT32
+#define RSCAN0RMPTR19L RSCAN0.RMPTR19.UINT16[L]
+#define RSCAN0RMPTR19LL RSCAN0.RMPTR19.UINT8[LL]
+#define RSCAN0RMPTR19LH RSCAN0.RMPTR19.UINT8[LH]
+#define RSCAN0RMPTR19H RSCAN0.RMPTR19.UINT16[H]
+#define RSCAN0RMPTR19HL RSCAN0.RMPTR19.UINT8[HL]
+#define RSCAN0RMPTR19HH RSCAN0.RMPTR19.UINT8[HH]
+#define RSCAN0RMDF019 RSCAN0.RMDF019.UINT32
+#define RSCAN0RMDF019L RSCAN0.RMDF019.UINT16[L]
+#define RSCAN0RMDF019LL RSCAN0.RMDF019.UINT8[LL]
+#define RSCAN0RMDF019LH RSCAN0.RMDF019.UINT8[LH]
+#define RSCAN0RMDF019H RSCAN0.RMDF019.UINT16[H]
+#define RSCAN0RMDF019HL RSCAN0.RMDF019.UINT8[HL]
+#define RSCAN0RMDF019HH RSCAN0.RMDF019.UINT8[HH]
+#define RSCAN0RMDF119 RSCAN0.RMDF119.UINT32
+#define RSCAN0RMDF119L RSCAN0.RMDF119.UINT16[L]
+#define RSCAN0RMDF119LL RSCAN0.RMDF119.UINT8[LL]
+#define RSCAN0RMDF119LH RSCAN0.RMDF119.UINT8[LH]
+#define RSCAN0RMDF119H RSCAN0.RMDF119.UINT16[H]
+#define RSCAN0RMDF119HL RSCAN0.RMDF119.UINT8[HL]
+#define RSCAN0RMDF119HH RSCAN0.RMDF119.UINT8[HH]
+#define RSCAN0RMID20 RSCAN0.RMID20.UINT32
+#define RSCAN0RMID20L RSCAN0.RMID20.UINT16[L]
+#define RSCAN0RMID20LL RSCAN0.RMID20.UINT8[LL]
+#define RSCAN0RMID20LH RSCAN0.RMID20.UINT8[LH]
+#define RSCAN0RMID20H RSCAN0.RMID20.UINT16[H]
+#define RSCAN0RMID20HL RSCAN0.RMID20.UINT8[HL]
+#define RSCAN0RMID20HH RSCAN0.RMID20.UINT8[HH]
+#define RSCAN0RMPTR20 RSCAN0.RMPTR20.UINT32
+#define RSCAN0RMPTR20L RSCAN0.RMPTR20.UINT16[L]
+#define RSCAN0RMPTR20LL RSCAN0.RMPTR20.UINT8[LL]
+#define RSCAN0RMPTR20LH RSCAN0.RMPTR20.UINT8[LH]
+#define RSCAN0RMPTR20H RSCAN0.RMPTR20.UINT16[H]
+#define RSCAN0RMPTR20HL RSCAN0.RMPTR20.UINT8[HL]
+#define RSCAN0RMPTR20HH RSCAN0.RMPTR20.UINT8[HH]
+#define RSCAN0RMDF020 RSCAN0.RMDF020.UINT32
+#define RSCAN0RMDF020L RSCAN0.RMDF020.UINT16[L]
+#define RSCAN0RMDF020LL RSCAN0.RMDF020.UINT8[LL]
+#define RSCAN0RMDF020LH RSCAN0.RMDF020.UINT8[LH]
+#define RSCAN0RMDF020H RSCAN0.RMDF020.UINT16[H]
+#define RSCAN0RMDF020HL RSCAN0.RMDF020.UINT8[HL]
+#define RSCAN0RMDF020HH RSCAN0.RMDF020.UINT8[HH]
+#define RSCAN0RMDF120 RSCAN0.RMDF120.UINT32
+#define RSCAN0RMDF120L RSCAN0.RMDF120.UINT16[L]
+#define RSCAN0RMDF120LL RSCAN0.RMDF120.UINT8[LL]
+#define RSCAN0RMDF120LH RSCAN0.RMDF120.UINT8[LH]
+#define RSCAN0RMDF120H RSCAN0.RMDF120.UINT16[H]
+#define RSCAN0RMDF120HL RSCAN0.RMDF120.UINT8[HL]
+#define RSCAN0RMDF120HH RSCAN0.RMDF120.UINT8[HH]
+#define RSCAN0RMID21 RSCAN0.RMID21.UINT32
+#define RSCAN0RMID21L RSCAN0.RMID21.UINT16[L]
+#define RSCAN0RMID21LL RSCAN0.RMID21.UINT8[LL]
+#define RSCAN0RMID21LH RSCAN0.RMID21.UINT8[LH]
+#define RSCAN0RMID21H RSCAN0.RMID21.UINT16[H]
+#define RSCAN0RMID21HL RSCAN0.RMID21.UINT8[HL]
+#define RSCAN0RMID21HH RSCAN0.RMID21.UINT8[HH]
+#define RSCAN0RMPTR21 RSCAN0.RMPTR21.UINT32
+#define RSCAN0RMPTR21L RSCAN0.RMPTR21.UINT16[L]
+#define RSCAN0RMPTR21LL RSCAN0.RMPTR21.UINT8[LL]
+#define RSCAN0RMPTR21LH RSCAN0.RMPTR21.UINT8[LH]
+#define RSCAN0RMPTR21H RSCAN0.RMPTR21.UINT16[H]
+#define RSCAN0RMPTR21HL RSCAN0.RMPTR21.UINT8[HL]
+#define RSCAN0RMPTR21HH RSCAN0.RMPTR21.UINT8[HH]
+#define RSCAN0RMDF021 RSCAN0.RMDF021.UINT32
+#define RSCAN0RMDF021L RSCAN0.RMDF021.UINT16[L]
+#define RSCAN0RMDF021LL RSCAN0.RMDF021.UINT8[LL]
+#define RSCAN0RMDF021LH RSCAN0.RMDF021.UINT8[LH]
+#define RSCAN0RMDF021H RSCAN0.RMDF021.UINT16[H]
+#define RSCAN0RMDF021HL RSCAN0.RMDF021.UINT8[HL]
+#define RSCAN0RMDF021HH RSCAN0.RMDF021.UINT8[HH]
+#define RSCAN0RMDF121 RSCAN0.RMDF121.UINT32
+#define RSCAN0RMDF121L RSCAN0.RMDF121.UINT16[L]
+#define RSCAN0RMDF121LL RSCAN0.RMDF121.UINT8[LL]
+#define RSCAN0RMDF121LH RSCAN0.RMDF121.UINT8[LH]
+#define RSCAN0RMDF121H RSCAN0.RMDF121.UINT16[H]
+#define RSCAN0RMDF121HL RSCAN0.RMDF121.UINT8[HL]
+#define RSCAN0RMDF121HH RSCAN0.RMDF121.UINT8[HH]
+#define RSCAN0RMID22 RSCAN0.RMID22.UINT32
+#define RSCAN0RMID22L RSCAN0.RMID22.UINT16[L]
+#define RSCAN0RMID22LL RSCAN0.RMID22.UINT8[LL]
+#define RSCAN0RMID22LH RSCAN0.RMID22.UINT8[LH]
+#define RSCAN0RMID22H RSCAN0.RMID22.UINT16[H]
+#define RSCAN0RMID22HL RSCAN0.RMID22.UINT8[HL]
+#define RSCAN0RMID22HH RSCAN0.RMID22.UINT8[HH]
+#define RSCAN0RMPTR22 RSCAN0.RMPTR22.UINT32
+#define RSCAN0RMPTR22L RSCAN0.RMPTR22.UINT16[L]
+#define RSCAN0RMPTR22LL RSCAN0.RMPTR22.UINT8[LL]
+#define RSCAN0RMPTR22LH RSCAN0.RMPTR22.UINT8[LH]
+#define RSCAN0RMPTR22H RSCAN0.RMPTR22.UINT16[H]
+#define RSCAN0RMPTR22HL RSCAN0.RMPTR22.UINT8[HL]
+#define RSCAN0RMPTR22HH RSCAN0.RMPTR22.UINT8[HH]
+#define RSCAN0RMDF022 RSCAN0.RMDF022.UINT32
+#define RSCAN0RMDF022L RSCAN0.RMDF022.UINT16[L]
+#define RSCAN0RMDF022LL RSCAN0.RMDF022.UINT8[LL]
+#define RSCAN0RMDF022LH RSCAN0.RMDF022.UINT8[LH]
+#define RSCAN0RMDF022H RSCAN0.RMDF022.UINT16[H]
+#define RSCAN0RMDF022HL RSCAN0.RMDF022.UINT8[HL]
+#define RSCAN0RMDF022HH RSCAN0.RMDF022.UINT8[HH]
+#define RSCAN0RMDF122 RSCAN0.RMDF122.UINT32
+#define RSCAN0RMDF122L RSCAN0.RMDF122.UINT16[L]
+#define RSCAN0RMDF122LL RSCAN0.RMDF122.UINT8[LL]
+#define RSCAN0RMDF122LH RSCAN0.RMDF122.UINT8[LH]
+#define RSCAN0RMDF122H RSCAN0.RMDF122.UINT16[H]
+#define RSCAN0RMDF122HL RSCAN0.RMDF122.UINT8[HL]
+#define RSCAN0RMDF122HH RSCAN0.RMDF122.UINT8[HH]
+#define RSCAN0RMID23 RSCAN0.RMID23.UINT32
+#define RSCAN0RMID23L RSCAN0.RMID23.UINT16[L]
+#define RSCAN0RMID23LL RSCAN0.RMID23.UINT8[LL]
+#define RSCAN0RMID23LH RSCAN0.RMID23.UINT8[LH]
+#define RSCAN0RMID23H RSCAN0.RMID23.UINT16[H]
+#define RSCAN0RMID23HL RSCAN0.RMID23.UINT8[HL]
+#define RSCAN0RMID23HH RSCAN0.RMID23.UINT8[HH]
+#define RSCAN0RMPTR23 RSCAN0.RMPTR23.UINT32
+#define RSCAN0RMPTR23L RSCAN0.RMPTR23.UINT16[L]
+#define RSCAN0RMPTR23LL RSCAN0.RMPTR23.UINT8[LL]
+#define RSCAN0RMPTR23LH RSCAN0.RMPTR23.UINT8[LH]
+#define RSCAN0RMPTR23H RSCAN0.RMPTR23.UINT16[H]
+#define RSCAN0RMPTR23HL RSCAN0.RMPTR23.UINT8[HL]
+#define RSCAN0RMPTR23HH RSCAN0.RMPTR23.UINT8[HH]
+#define RSCAN0RMDF023 RSCAN0.RMDF023.UINT32
+#define RSCAN0RMDF023L RSCAN0.RMDF023.UINT16[L]
+#define RSCAN0RMDF023LL RSCAN0.RMDF023.UINT8[LL]
+#define RSCAN0RMDF023LH RSCAN0.RMDF023.UINT8[LH]
+#define RSCAN0RMDF023H RSCAN0.RMDF023.UINT16[H]
+#define RSCAN0RMDF023HL RSCAN0.RMDF023.UINT8[HL]
+#define RSCAN0RMDF023HH RSCAN0.RMDF023.UINT8[HH]
+#define RSCAN0RMDF123 RSCAN0.RMDF123.UINT32
+#define RSCAN0RMDF123L RSCAN0.RMDF123.UINT16[L]
+#define RSCAN0RMDF123LL RSCAN0.RMDF123.UINT8[LL]
+#define RSCAN0RMDF123LH RSCAN0.RMDF123.UINT8[LH]
+#define RSCAN0RMDF123H RSCAN0.RMDF123.UINT16[H]
+#define RSCAN0RMDF123HL RSCAN0.RMDF123.UINT8[HL]
+#define RSCAN0RMDF123HH RSCAN0.RMDF123.UINT8[HH]
+#define RSCAN0RMID24 RSCAN0.RMID24.UINT32
+#define RSCAN0RMID24L RSCAN0.RMID24.UINT16[L]
+#define RSCAN0RMID24LL RSCAN0.RMID24.UINT8[LL]
+#define RSCAN0RMID24LH RSCAN0.RMID24.UINT8[LH]
+#define RSCAN0RMID24H RSCAN0.RMID24.UINT16[H]
+#define RSCAN0RMID24HL RSCAN0.RMID24.UINT8[HL]
+#define RSCAN0RMID24HH RSCAN0.RMID24.UINT8[HH]
+#define RSCAN0RMPTR24 RSCAN0.RMPTR24.UINT32
+#define RSCAN0RMPTR24L RSCAN0.RMPTR24.UINT16[L]
+#define RSCAN0RMPTR24LL RSCAN0.RMPTR24.UINT8[LL]
+#define RSCAN0RMPTR24LH RSCAN0.RMPTR24.UINT8[LH]
+#define RSCAN0RMPTR24H RSCAN0.RMPTR24.UINT16[H]
+#define RSCAN0RMPTR24HL RSCAN0.RMPTR24.UINT8[HL]
+#define RSCAN0RMPTR24HH RSCAN0.RMPTR24.UINT8[HH]
+#define RSCAN0RMDF024 RSCAN0.RMDF024.UINT32
+#define RSCAN0RMDF024L RSCAN0.RMDF024.UINT16[L]
+#define RSCAN0RMDF024LL RSCAN0.RMDF024.UINT8[LL]
+#define RSCAN0RMDF024LH RSCAN0.RMDF024.UINT8[LH]
+#define RSCAN0RMDF024H RSCAN0.RMDF024.UINT16[H]
+#define RSCAN0RMDF024HL RSCAN0.RMDF024.UINT8[HL]
+#define RSCAN0RMDF024HH RSCAN0.RMDF024.UINT8[HH]
+#define RSCAN0RMDF124 RSCAN0.RMDF124.UINT32
+#define RSCAN0RMDF124L RSCAN0.RMDF124.UINT16[L]
+#define RSCAN0RMDF124LL RSCAN0.RMDF124.UINT8[LL]
+#define RSCAN0RMDF124LH RSCAN0.RMDF124.UINT8[LH]
+#define RSCAN0RMDF124H RSCAN0.RMDF124.UINT16[H]
+#define RSCAN0RMDF124HL RSCAN0.RMDF124.UINT8[HL]
+#define RSCAN0RMDF124HH RSCAN0.RMDF124.UINT8[HH]
+#define RSCAN0RMID25 RSCAN0.RMID25.UINT32
+#define RSCAN0RMID25L RSCAN0.RMID25.UINT16[L]
+#define RSCAN0RMID25LL RSCAN0.RMID25.UINT8[LL]
+#define RSCAN0RMID25LH RSCAN0.RMID25.UINT8[LH]
+#define RSCAN0RMID25H RSCAN0.RMID25.UINT16[H]
+#define RSCAN0RMID25HL RSCAN0.RMID25.UINT8[HL]
+#define RSCAN0RMID25HH RSCAN0.RMID25.UINT8[HH]
+#define RSCAN0RMPTR25 RSCAN0.RMPTR25.UINT32
+#define RSCAN0RMPTR25L RSCAN0.RMPTR25.UINT16[L]
+#define RSCAN0RMPTR25LL RSCAN0.RMPTR25.UINT8[LL]
+#define RSCAN0RMPTR25LH RSCAN0.RMPTR25.UINT8[LH]
+#define RSCAN0RMPTR25H RSCAN0.RMPTR25.UINT16[H]
+#define RSCAN0RMPTR25HL RSCAN0.RMPTR25.UINT8[HL]
+#define RSCAN0RMPTR25HH RSCAN0.RMPTR25.UINT8[HH]
+#define RSCAN0RMDF025 RSCAN0.RMDF025.UINT32
+#define RSCAN0RMDF025L RSCAN0.RMDF025.UINT16[L]
+#define RSCAN0RMDF025LL RSCAN0.RMDF025.UINT8[LL]
+#define RSCAN0RMDF025LH RSCAN0.RMDF025.UINT8[LH]
+#define RSCAN0RMDF025H RSCAN0.RMDF025.UINT16[H]
+#define RSCAN0RMDF025HL RSCAN0.RMDF025.UINT8[HL]
+#define RSCAN0RMDF025HH RSCAN0.RMDF025.UINT8[HH]
+#define RSCAN0RMDF125 RSCAN0.RMDF125.UINT32
+#define RSCAN0RMDF125L RSCAN0.RMDF125.UINT16[L]
+#define RSCAN0RMDF125LL RSCAN0.RMDF125.UINT8[LL]
+#define RSCAN0RMDF125LH RSCAN0.RMDF125.UINT8[LH]
+#define RSCAN0RMDF125H RSCAN0.RMDF125.UINT16[H]
+#define RSCAN0RMDF125HL RSCAN0.RMDF125.UINT8[HL]
+#define RSCAN0RMDF125HH RSCAN0.RMDF125.UINT8[HH]
+#define RSCAN0RMID26 RSCAN0.RMID26.UINT32
+#define RSCAN0RMID26L RSCAN0.RMID26.UINT16[L]
+#define RSCAN0RMID26LL RSCAN0.RMID26.UINT8[LL]
+#define RSCAN0RMID26LH RSCAN0.RMID26.UINT8[LH]
+#define RSCAN0RMID26H RSCAN0.RMID26.UINT16[H]
+#define RSCAN0RMID26HL RSCAN0.RMID26.UINT8[HL]
+#define RSCAN0RMID26HH RSCAN0.RMID26.UINT8[HH]
+#define RSCAN0RMPTR26 RSCAN0.RMPTR26.UINT32
+#define RSCAN0RMPTR26L RSCAN0.RMPTR26.UINT16[L]
+#define RSCAN0RMPTR26LL RSCAN0.RMPTR26.UINT8[LL]
+#define RSCAN0RMPTR26LH RSCAN0.RMPTR26.UINT8[LH]
+#define RSCAN0RMPTR26H RSCAN0.RMPTR26.UINT16[H]
+#define RSCAN0RMPTR26HL RSCAN0.RMPTR26.UINT8[HL]
+#define RSCAN0RMPTR26HH RSCAN0.RMPTR26.UINT8[HH]
+#define RSCAN0RMDF026 RSCAN0.RMDF026.UINT32
+#define RSCAN0RMDF026L RSCAN0.RMDF026.UINT16[L]
+#define RSCAN0RMDF026LL RSCAN0.RMDF026.UINT8[LL]
+#define RSCAN0RMDF026LH RSCAN0.RMDF026.UINT8[LH]
+#define RSCAN0RMDF026H RSCAN0.RMDF026.UINT16[H]
+#define RSCAN0RMDF026HL RSCAN0.RMDF026.UINT8[HL]
+#define RSCAN0RMDF026HH RSCAN0.RMDF026.UINT8[HH]
+#define RSCAN0RMDF126 RSCAN0.RMDF126.UINT32
+#define RSCAN0RMDF126L RSCAN0.RMDF126.UINT16[L]
+#define RSCAN0RMDF126LL RSCAN0.RMDF126.UINT8[LL]
+#define RSCAN0RMDF126LH RSCAN0.RMDF126.UINT8[LH]
+#define RSCAN0RMDF126H RSCAN0.RMDF126.UINT16[H]
+#define RSCAN0RMDF126HL RSCAN0.RMDF126.UINT8[HL]
+#define RSCAN0RMDF126HH RSCAN0.RMDF126.UINT8[HH]
+#define RSCAN0RMID27 RSCAN0.RMID27.UINT32
+#define RSCAN0RMID27L RSCAN0.RMID27.UINT16[L]
+#define RSCAN0RMID27LL RSCAN0.RMID27.UINT8[LL]
+#define RSCAN0RMID27LH RSCAN0.RMID27.UINT8[LH]
+#define RSCAN0RMID27H RSCAN0.RMID27.UINT16[H]
+#define RSCAN0RMID27HL RSCAN0.RMID27.UINT8[HL]
+#define RSCAN0RMID27HH RSCAN0.RMID27.UINT8[HH]
+#define RSCAN0RMPTR27 RSCAN0.RMPTR27.UINT32
+#define RSCAN0RMPTR27L RSCAN0.RMPTR27.UINT16[L]
+#define RSCAN0RMPTR27LL RSCAN0.RMPTR27.UINT8[LL]
+#define RSCAN0RMPTR27LH RSCAN0.RMPTR27.UINT8[LH]
+#define RSCAN0RMPTR27H RSCAN0.RMPTR27.UINT16[H]
+#define RSCAN0RMPTR27HL RSCAN0.RMPTR27.UINT8[HL]
+#define RSCAN0RMPTR27HH RSCAN0.RMPTR27.UINT8[HH]
+#define RSCAN0RMDF027 RSCAN0.RMDF027.UINT32
+#define RSCAN0RMDF027L RSCAN0.RMDF027.UINT16[L]
+#define RSCAN0RMDF027LL RSCAN0.RMDF027.UINT8[LL]
+#define RSCAN0RMDF027LH RSCAN0.RMDF027.UINT8[LH]
+#define RSCAN0RMDF027H RSCAN0.RMDF027.UINT16[H]
+#define RSCAN0RMDF027HL RSCAN0.RMDF027.UINT8[HL]
+#define RSCAN0RMDF027HH RSCAN0.RMDF027.UINT8[HH]
+#define RSCAN0RMDF127 RSCAN0.RMDF127.UINT32
+#define RSCAN0RMDF127L RSCAN0.RMDF127.UINT16[L]
+#define RSCAN0RMDF127LL RSCAN0.RMDF127.UINT8[LL]
+#define RSCAN0RMDF127LH RSCAN0.RMDF127.UINT8[LH]
+#define RSCAN0RMDF127H RSCAN0.RMDF127.UINT16[H]
+#define RSCAN0RMDF127HL RSCAN0.RMDF127.UINT8[HL]
+#define RSCAN0RMDF127HH RSCAN0.RMDF127.UINT8[HH]
+#define RSCAN0RMID28 RSCAN0.RMID28.UINT32
+#define RSCAN0RMID28L RSCAN0.RMID28.UINT16[L]
+#define RSCAN0RMID28LL RSCAN0.RMID28.UINT8[LL]
+#define RSCAN0RMID28LH RSCAN0.RMID28.UINT8[LH]
+#define RSCAN0RMID28H RSCAN0.RMID28.UINT16[H]
+#define RSCAN0RMID28HL RSCAN0.RMID28.UINT8[HL]
+#define RSCAN0RMID28HH RSCAN0.RMID28.UINT8[HH]
+#define RSCAN0RMPTR28 RSCAN0.RMPTR28.UINT32
+#define RSCAN0RMPTR28L RSCAN0.RMPTR28.UINT16[L]
+#define RSCAN0RMPTR28LL RSCAN0.RMPTR28.UINT8[LL]
+#define RSCAN0RMPTR28LH RSCAN0.RMPTR28.UINT8[LH]
+#define RSCAN0RMPTR28H RSCAN0.RMPTR28.UINT16[H]
+#define RSCAN0RMPTR28HL RSCAN0.RMPTR28.UINT8[HL]
+#define RSCAN0RMPTR28HH RSCAN0.RMPTR28.UINT8[HH]
+#define RSCAN0RMDF028 RSCAN0.RMDF028.UINT32
+#define RSCAN0RMDF028L RSCAN0.RMDF028.UINT16[L]
+#define RSCAN0RMDF028LL RSCAN0.RMDF028.UINT8[LL]
+#define RSCAN0RMDF028LH RSCAN0.RMDF028.UINT8[LH]
+#define RSCAN0RMDF028H RSCAN0.RMDF028.UINT16[H]
+#define RSCAN0RMDF028HL RSCAN0.RMDF028.UINT8[HL]
+#define RSCAN0RMDF028HH RSCAN0.RMDF028.UINT8[HH]
+#define RSCAN0RMDF128 RSCAN0.RMDF128.UINT32
+#define RSCAN0RMDF128L RSCAN0.RMDF128.UINT16[L]
+#define RSCAN0RMDF128LL RSCAN0.RMDF128.UINT8[LL]
+#define RSCAN0RMDF128LH RSCAN0.RMDF128.UINT8[LH]
+#define RSCAN0RMDF128H RSCAN0.RMDF128.UINT16[H]
+#define RSCAN0RMDF128HL RSCAN0.RMDF128.UINT8[HL]
+#define RSCAN0RMDF128HH RSCAN0.RMDF128.UINT8[HH]
+#define RSCAN0RMID29 RSCAN0.RMID29.UINT32
+#define RSCAN0RMID29L RSCAN0.RMID29.UINT16[L]
+#define RSCAN0RMID29LL RSCAN0.RMID29.UINT8[LL]
+#define RSCAN0RMID29LH RSCAN0.RMID29.UINT8[LH]
+#define RSCAN0RMID29H RSCAN0.RMID29.UINT16[H]
+#define RSCAN0RMID29HL RSCAN0.RMID29.UINT8[HL]
+#define RSCAN0RMID29HH RSCAN0.RMID29.UINT8[HH]
+#define RSCAN0RMPTR29 RSCAN0.RMPTR29.UINT32
+#define RSCAN0RMPTR29L RSCAN0.RMPTR29.UINT16[L]
+#define RSCAN0RMPTR29LL RSCAN0.RMPTR29.UINT8[LL]
+#define RSCAN0RMPTR29LH RSCAN0.RMPTR29.UINT8[LH]
+#define RSCAN0RMPTR29H RSCAN0.RMPTR29.UINT16[H]
+#define RSCAN0RMPTR29HL RSCAN0.RMPTR29.UINT8[HL]
+#define RSCAN0RMPTR29HH RSCAN0.RMPTR29.UINT8[HH]
+#define RSCAN0RMDF029 RSCAN0.RMDF029.UINT32
+#define RSCAN0RMDF029L RSCAN0.RMDF029.UINT16[L]
+#define RSCAN0RMDF029LL RSCAN0.RMDF029.UINT8[LL]
+#define RSCAN0RMDF029LH RSCAN0.RMDF029.UINT8[LH]
+#define RSCAN0RMDF029H RSCAN0.RMDF029.UINT16[H]
+#define RSCAN0RMDF029HL RSCAN0.RMDF029.UINT8[HL]
+#define RSCAN0RMDF029HH RSCAN0.RMDF029.UINT8[HH]
+#define RSCAN0RMDF129 RSCAN0.RMDF129.UINT32
+#define RSCAN0RMDF129L RSCAN0.RMDF129.UINT16[L]
+#define RSCAN0RMDF129LL RSCAN0.RMDF129.UINT8[LL]
+#define RSCAN0RMDF129LH RSCAN0.RMDF129.UINT8[LH]
+#define RSCAN0RMDF129H RSCAN0.RMDF129.UINT16[H]
+#define RSCAN0RMDF129HL RSCAN0.RMDF129.UINT8[HL]
+#define RSCAN0RMDF129HH RSCAN0.RMDF129.UINT8[HH]
+#define RSCAN0RMID30 RSCAN0.RMID30.UINT32
+#define RSCAN0RMID30L RSCAN0.RMID30.UINT16[L]
+#define RSCAN0RMID30LL RSCAN0.RMID30.UINT8[LL]
+#define RSCAN0RMID30LH RSCAN0.RMID30.UINT8[LH]
+#define RSCAN0RMID30H RSCAN0.RMID30.UINT16[H]
+#define RSCAN0RMID30HL RSCAN0.RMID30.UINT8[HL]
+#define RSCAN0RMID30HH RSCAN0.RMID30.UINT8[HH]
+#define RSCAN0RMPTR30 RSCAN0.RMPTR30.UINT32
+#define RSCAN0RMPTR30L RSCAN0.RMPTR30.UINT16[L]
+#define RSCAN0RMPTR30LL RSCAN0.RMPTR30.UINT8[LL]
+#define RSCAN0RMPTR30LH RSCAN0.RMPTR30.UINT8[LH]
+#define RSCAN0RMPTR30H RSCAN0.RMPTR30.UINT16[H]
+#define RSCAN0RMPTR30HL RSCAN0.RMPTR30.UINT8[HL]
+#define RSCAN0RMPTR30HH RSCAN0.RMPTR30.UINT8[HH]
+#define RSCAN0RMDF030 RSCAN0.RMDF030.UINT32
+#define RSCAN0RMDF030L RSCAN0.RMDF030.UINT16[L]
+#define RSCAN0RMDF030LL RSCAN0.RMDF030.UINT8[LL]
+#define RSCAN0RMDF030LH RSCAN0.RMDF030.UINT8[LH]
+#define RSCAN0RMDF030H RSCAN0.RMDF030.UINT16[H]
+#define RSCAN0RMDF030HL RSCAN0.RMDF030.UINT8[HL]
+#define RSCAN0RMDF030HH RSCAN0.RMDF030.UINT8[HH]
+#define RSCAN0RMDF130 RSCAN0.RMDF130.UINT32
+#define RSCAN0RMDF130L RSCAN0.RMDF130.UINT16[L]
+#define RSCAN0RMDF130LL RSCAN0.RMDF130.UINT8[LL]
+#define RSCAN0RMDF130LH RSCAN0.RMDF130.UINT8[LH]
+#define RSCAN0RMDF130H RSCAN0.RMDF130.UINT16[H]
+#define RSCAN0RMDF130HL RSCAN0.RMDF130.UINT8[HL]
+#define RSCAN0RMDF130HH RSCAN0.RMDF130.UINT8[HH]
+#define RSCAN0RMID31 RSCAN0.RMID31.UINT32
+#define RSCAN0RMID31L RSCAN0.RMID31.UINT16[L]
+#define RSCAN0RMID31LL RSCAN0.RMID31.UINT8[LL]
+#define RSCAN0RMID31LH RSCAN0.RMID31.UINT8[LH]
+#define RSCAN0RMID31H RSCAN0.RMID31.UINT16[H]
+#define RSCAN0RMID31HL RSCAN0.RMID31.UINT8[HL]
+#define RSCAN0RMID31HH RSCAN0.RMID31.UINT8[HH]
+#define RSCAN0RMPTR31 RSCAN0.RMPTR31.UINT32
+#define RSCAN0RMPTR31L RSCAN0.RMPTR31.UINT16[L]
+#define RSCAN0RMPTR31LL RSCAN0.RMPTR31.UINT8[LL]
+#define RSCAN0RMPTR31LH RSCAN0.RMPTR31.UINT8[LH]
+#define RSCAN0RMPTR31H RSCAN0.RMPTR31.UINT16[H]
+#define RSCAN0RMPTR31HL RSCAN0.RMPTR31.UINT8[HL]
+#define RSCAN0RMPTR31HH RSCAN0.RMPTR31.UINT8[HH]
+#define RSCAN0RMDF031 RSCAN0.RMDF031.UINT32
+#define RSCAN0RMDF031L RSCAN0.RMDF031.UINT16[L]
+#define RSCAN0RMDF031LL RSCAN0.RMDF031.UINT8[LL]
+#define RSCAN0RMDF031LH RSCAN0.RMDF031.UINT8[LH]
+#define RSCAN0RMDF031H RSCAN0.RMDF031.UINT16[H]
+#define RSCAN0RMDF031HL RSCAN0.RMDF031.UINT8[HL]
+#define RSCAN0RMDF031HH RSCAN0.RMDF031.UINT8[HH]
+#define RSCAN0RMDF131 RSCAN0.RMDF131.UINT32
+#define RSCAN0RMDF131L RSCAN0.RMDF131.UINT16[L]
+#define RSCAN0RMDF131LL RSCAN0.RMDF131.UINT8[LL]
+#define RSCAN0RMDF131LH RSCAN0.RMDF131.UINT8[LH]
+#define RSCAN0RMDF131H RSCAN0.RMDF131.UINT16[H]
+#define RSCAN0RMDF131HL RSCAN0.RMDF131.UINT8[HL]
+#define RSCAN0RMDF131HH RSCAN0.RMDF131.UINT8[HH]
+#define RSCAN0RMID32 RSCAN0.RMID32.UINT32
+#define RSCAN0RMID32L RSCAN0.RMID32.UINT16[L]
+#define RSCAN0RMID32LL RSCAN0.RMID32.UINT8[LL]
+#define RSCAN0RMID32LH RSCAN0.RMID32.UINT8[LH]
+#define RSCAN0RMID32H RSCAN0.RMID32.UINT16[H]
+#define RSCAN0RMID32HL RSCAN0.RMID32.UINT8[HL]
+#define RSCAN0RMID32HH RSCAN0.RMID32.UINT8[HH]
+#define RSCAN0RMPTR32 RSCAN0.RMPTR32.UINT32
+#define RSCAN0RMPTR32L RSCAN0.RMPTR32.UINT16[L]
+#define RSCAN0RMPTR32LL RSCAN0.RMPTR32.UINT8[LL]
+#define RSCAN0RMPTR32LH RSCAN0.RMPTR32.UINT8[LH]
+#define RSCAN0RMPTR32H RSCAN0.RMPTR32.UINT16[H]
+#define RSCAN0RMPTR32HL RSCAN0.RMPTR32.UINT8[HL]
+#define RSCAN0RMPTR32HH RSCAN0.RMPTR32.UINT8[HH]
+#define RSCAN0RMDF032 RSCAN0.RMDF032.UINT32
+#define RSCAN0RMDF032L RSCAN0.RMDF032.UINT16[L]
+#define RSCAN0RMDF032LL RSCAN0.RMDF032.UINT8[LL]
+#define RSCAN0RMDF032LH RSCAN0.RMDF032.UINT8[LH]
+#define RSCAN0RMDF032H RSCAN0.RMDF032.UINT16[H]
+#define RSCAN0RMDF032HL RSCAN0.RMDF032.UINT8[HL]
+#define RSCAN0RMDF032HH RSCAN0.RMDF032.UINT8[HH]
+#define RSCAN0RMDF132 RSCAN0.RMDF132.UINT32
+#define RSCAN0RMDF132L RSCAN0.RMDF132.UINT16[L]
+#define RSCAN0RMDF132LL RSCAN0.RMDF132.UINT8[LL]
+#define RSCAN0RMDF132LH RSCAN0.RMDF132.UINT8[LH]
+#define RSCAN0RMDF132H RSCAN0.RMDF132.UINT16[H]
+#define RSCAN0RMDF132HL RSCAN0.RMDF132.UINT8[HL]
+#define RSCAN0RMDF132HH RSCAN0.RMDF132.UINT8[HH]
+#define RSCAN0RMID33 RSCAN0.RMID33.UINT32
+#define RSCAN0RMID33L RSCAN0.RMID33.UINT16[L]
+#define RSCAN0RMID33LL RSCAN0.RMID33.UINT8[LL]
+#define RSCAN0RMID33LH RSCAN0.RMID33.UINT8[LH]
+#define RSCAN0RMID33H RSCAN0.RMID33.UINT16[H]
+#define RSCAN0RMID33HL RSCAN0.RMID33.UINT8[HL]
+#define RSCAN0RMID33HH RSCAN0.RMID33.UINT8[HH]
+#define RSCAN0RMPTR33 RSCAN0.RMPTR33.UINT32
+#define RSCAN0RMPTR33L RSCAN0.RMPTR33.UINT16[L]
+#define RSCAN0RMPTR33LL RSCAN0.RMPTR33.UINT8[LL]
+#define RSCAN0RMPTR33LH RSCAN0.RMPTR33.UINT8[LH]
+#define RSCAN0RMPTR33H RSCAN0.RMPTR33.UINT16[H]
+#define RSCAN0RMPTR33HL RSCAN0.RMPTR33.UINT8[HL]
+#define RSCAN0RMPTR33HH RSCAN0.RMPTR33.UINT8[HH]
+#define RSCAN0RMDF033 RSCAN0.RMDF033.UINT32
+#define RSCAN0RMDF033L RSCAN0.RMDF033.UINT16[L]
+#define RSCAN0RMDF033LL RSCAN0.RMDF033.UINT8[LL]
+#define RSCAN0RMDF033LH RSCAN0.RMDF033.UINT8[LH]
+#define RSCAN0RMDF033H RSCAN0.RMDF033.UINT16[H]
+#define RSCAN0RMDF033HL RSCAN0.RMDF033.UINT8[HL]
+#define RSCAN0RMDF033HH RSCAN0.RMDF033.UINT8[HH]
+#define RSCAN0RMDF133 RSCAN0.RMDF133.UINT32
+#define RSCAN0RMDF133L RSCAN0.RMDF133.UINT16[L]
+#define RSCAN0RMDF133LL RSCAN0.RMDF133.UINT8[LL]
+#define RSCAN0RMDF133LH RSCAN0.RMDF133.UINT8[LH]
+#define RSCAN0RMDF133H RSCAN0.RMDF133.UINT16[H]
+#define RSCAN0RMDF133HL RSCAN0.RMDF133.UINT8[HL]
+#define RSCAN0RMDF133HH RSCAN0.RMDF133.UINT8[HH]
+#define RSCAN0RMID34 RSCAN0.RMID34.UINT32
+#define RSCAN0RMID34L RSCAN0.RMID34.UINT16[L]
+#define RSCAN0RMID34LL RSCAN0.RMID34.UINT8[LL]
+#define RSCAN0RMID34LH RSCAN0.RMID34.UINT8[LH]
+#define RSCAN0RMID34H RSCAN0.RMID34.UINT16[H]
+#define RSCAN0RMID34HL RSCAN0.RMID34.UINT8[HL]
+#define RSCAN0RMID34HH RSCAN0.RMID34.UINT8[HH]
+#define RSCAN0RMPTR34 RSCAN0.RMPTR34.UINT32
+#define RSCAN0RMPTR34L RSCAN0.RMPTR34.UINT16[L]
+#define RSCAN0RMPTR34LL RSCAN0.RMPTR34.UINT8[LL]
+#define RSCAN0RMPTR34LH RSCAN0.RMPTR34.UINT8[LH]
+#define RSCAN0RMPTR34H RSCAN0.RMPTR34.UINT16[H]
+#define RSCAN0RMPTR34HL RSCAN0.RMPTR34.UINT8[HL]
+#define RSCAN0RMPTR34HH RSCAN0.RMPTR34.UINT8[HH]
+#define RSCAN0RMDF034 RSCAN0.RMDF034.UINT32
+#define RSCAN0RMDF034L RSCAN0.RMDF034.UINT16[L]
+#define RSCAN0RMDF034LL RSCAN0.RMDF034.UINT8[LL]
+#define RSCAN0RMDF034LH RSCAN0.RMDF034.UINT8[LH]
+#define RSCAN0RMDF034H RSCAN0.RMDF034.UINT16[H]
+#define RSCAN0RMDF034HL RSCAN0.RMDF034.UINT8[HL]
+#define RSCAN0RMDF034HH RSCAN0.RMDF034.UINT8[HH]
+#define RSCAN0RMDF134 RSCAN0.RMDF134.UINT32
+#define RSCAN0RMDF134L RSCAN0.RMDF134.UINT16[L]
+#define RSCAN0RMDF134LL RSCAN0.RMDF134.UINT8[LL]
+#define RSCAN0RMDF134LH RSCAN0.RMDF134.UINT8[LH]
+#define RSCAN0RMDF134H RSCAN0.RMDF134.UINT16[H]
+#define RSCAN0RMDF134HL RSCAN0.RMDF134.UINT8[HL]
+#define RSCAN0RMDF134HH RSCAN0.RMDF134.UINT8[HH]
+#define RSCAN0RMID35 RSCAN0.RMID35.UINT32
+#define RSCAN0RMID35L RSCAN0.RMID35.UINT16[L]
+#define RSCAN0RMID35LL RSCAN0.RMID35.UINT8[LL]
+#define RSCAN0RMID35LH RSCAN0.RMID35.UINT8[LH]
+#define RSCAN0RMID35H RSCAN0.RMID35.UINT16[H]
+#define RSCAN0RMID35HL RSCAN0.RMID35.UINT8[HL]
+#define RSCAN0RMID35HH RSCAN0.RMID35.UINT8[HH]
+#define RSCAN0RMPTR35 RSCAN0.RMPTR35.UINT32
+#define RSCAN0RMPTR35L RSCAN0.RMPTR35.UINT16[L]
+#define RSCAN0RMPTR35LL RSCAN0.RMPTR35.UINT8[LL]
+#define RSCAN0RMPTR35LH RSCAN0.RMPTR35.UINT8[LH]
+#define RSCAN0RMPTR35H RSCAN0.RMPTR35.UINT16[H]
+#define RSCAN0RMPTR35HL RSCAN0.RMPTR35.UINT8[HL]
+#define RSCAN0RMPTR35HH RSCAN0.RMPTR35.UINT8[HH]
+#define RSCAN0RMDF035 RSCAN0.RMDF035.UINT32
+#define RSCAN0RMDF035L RSCAN0.RMDF035.UINT16[L]
+#define RSCAN0RMDF035LL RSCAN0.RMDF035.UINT8[LL]
+#define RSCAN0RMDF035LH RSCAN0.RMDF035.UINT8[LH]
+#define RSCAN0RMDF035H RSCAN0.RMDF035.UINT16[H]
+#define RSCAN0RMDF035HL RSCAN0.RMDF035.UINT8[HL]
+#define RSCAN0RMDF035HH RSCAN0.RMDF035.UINT8[HH]
+#define RSCAN0RMDF135 RSCAN0.RMDF135.UINT32
+#define RSCAN0RMDF135L RSCAN0.RMDF135.UINT16[L]
+#define RSCAN0RMDF135LL RSCAN0.RMDF135.UINT8[LL]
+#define RSCAN0RMDF135LH RSCAN0.RMDF135.UINT8[LH]
+#define RSCAN0RMDF135H RSCAN0.RMDF135.UINT16[H]
+#define RSCAN0RMDF135HL RSCAN0.RMDF135.UINT8[HL]
+#define RSCAN0RMDF135HH RSCAN0.RMDF135.UINT8[HH]
+#define RSCAN0RMID36 RSCAN0.RMID36.UINT32
+#define RSCAN0RMID36L RSCAN0.RMID36.UINT16[L]
+#define RSCAN0RMID36LL RSCAN0.RMID36.UINT8[LL]
+#define RSCAN0RMID36LH RSCAN0.RMID36.UINT8[LH]
+#define RSCAN0RMID36H RSCAN0.RMID36.UINT16[H]
+#define RSCAN0RMID36HL RSCAN0.RMID36.UINT8[HL]
+#define RSCAN0RMID36HH RSCAN0.RMID36.UINT8[HH]
+#define RSCAN0RMPTR36 RSCAN0.RMPTR36.UINT32
+#define RSCAN0RMPTR36L RSCAN0.RMPTR36.UINT16[L]
+#define RSCAN0RMPTR36LL RSCAN0.RMPTR36.UINT8[LL]
+#define RSCAN0RMPTR36LH RSCAN0.RMPTR36.UINT8[LH]
+#define RSCAN0RMPTR36H RSCAN0.RMPTR36.UINT16[H]
+#define RSCAN0RMPTR36HL RSCAN0.RMPTR36.UINT8[HL]
+#define RSCAN0RMPTR36HH RSCAN0.RMPTR36.UINT8[HH]
+#define RSCAN0RMDF036 RSCAN0.RMDF036.UINT32
+#define RSCAN0RMDF036L RSCAN0.RMDF036.UINT16[L]
+#define RSCAN0RMDF036LL RSCAN0.RMDF036.UINT8[LL]
+#define RSCAN0RMDF036LH RSCAN0.RMDF036.UINT8[LH]
+#define RSCAN0RMDF036H RSCAN0.RMDF036.UINT16[H]
+#define RSCAN0RMDF036HL RSCAN0.RMDF036.UINT8[HL]
+#define RSCAN0RMDF036HH RSCAN0.RMDF036.UINT8[HH]
+#define RSCAN0RMDF136 RSCAN0.RMDF136.UINT32
+#define RSCAN0RMDF136L RSCAN0.RMDF136.UINT16[L]
+#define RSCAN0RMDF136LL RSCAN0.RMDF136.UINT8[LL]
+#define RSCAN0RMDF136LH RSCAN0.RMDF136.UINT8[LH]
+#define RSCAN0RMDF136H RSCAN0.RMDF136.UINT16[H]
+#define RSCAN0RMDF136HL RSCAN0.RMDF136.UINT8[HL]
+#define RSCAN0RMDF136HH RSCAN0.RMDF136.UINT8[HH]
+#define RSCAN0RMID37 RSCAN0.RMID37.UINT32
+#define RSCAN0RMID37L RSCAN0.RMID37.UINT16[L]
+#define RSCAN0RMID37LL RSCAN0.RMID37.UINT8[LL]
+#define RSCAN0RMID37LH RSCAN0.RMID37.UINT8[LH]
+#define RSCAN0RMID37H RSCAN0.RMID37.UINT16[H]
+#define RSCAN0RMID37HL RSCAN0.RMID37.UINT8[HL]
+#define RSCAN0RMID37HH RSCAN0.RMID37.UINT8[HH]
+#define RSCAN0RMPTR37 RSCAN0.RMPTR37.UINT32
+#define RSCAN0RMPTR37L RSCAN0.RMPTR37.UINT16[L]
+#define RSCAN0RMPTR37LL RSCAN0.RMPTR37.UINT8[LL]
+#define RSCAN0RMPTR37LH RSCAN0.RMPTR37.UINT8[LH]
+#define RSCAN0RMPTR37H RSCAN0.RMPTR37.UINT16[H]
+#define RSCAN0RMPTR37HL RSCAN0.RMPTR37.UINT8[HL]
+#define RSCAN0RMPTR37HH RSCAN0.RMPTR37.UINT8[HH]
+#define RSCAN0RMDF037 RSCAN0.RMDF037.UINT32
+#define RSCAN0RMDF037L RSCAN0.RMDF037.UINT16[L]
+#define RSCAN0RMDF037LL RSCAN0.RMDF037.UINT8[LL]
+#define RSCAN0RMDF037LH RSCAN0.RMDF037.UINT8[LH]
+#define RSCAN0RMDF037H RSCAN0.RMDF037.UINT16[H]
+#define RSCAN0RMDF037HL RSCAN0.RMDF037.UINT8[HL]
+#define RSCAN0RMDF037HH RSCAN0.RMDF037.UINT8[HH]
+#define RSCAN0RMDF137 RSCAN0.RMDF137.UINT32
+#define RSCAN0RMDF137L RSCAN0.RMDF137.UINT16[L]
+#define RSCAN0RMDF137LL RSCAN0.RMDF137.UINT8[LL]
+#define RSCAN0RMDF137LH RSCAN0.RMDF137.UINT8[LH]
+#define RSCAN0RMDF137H RSCAN0.RMDF137.UINT16[H]
+#define RSCAN0RMDF137HL RSCAN0.RMDF137.UINT8[HL]
+#define RSCAN0RMDF137HH RSCAN0.RMDF137.UINT8[HH]
+#define RSCAN0RMID38 RSCAN0.RMID38.UINT32
+#define RSCAN0RMID38L RSCAN0.RMID38.UINT16[L]
+#define RSCAN0RMID38LL RSCAN0.RMID38.UINT8[LL]
+#define RSCAN0RMID38LH RSCAN0.RMID38.UINT8[LH]
+#define RSCAN0RMID38H RSCAN0.RMID38.UINT16[H]
+#define RSCAN0RMID38HL RSCAN0.RMID38.UINT8[HL]
+#define RSCAN0RMID38HH RSCAN0.RMID38.UINT8[HH]
+#define RSCAN0RMPTR38 RSCAN0.RMPTR38.UINT32
+#define RSCAN0RMPTR38L RSCAN0.RMPTR38.UINT16[L]
+#define RSCAN0RMPTR38LL RSCAN0.RMPTR38.UINT8[LL]
+#define RSCAN0RMPTR38LH RSCAN0.RMPTR38.UINT8[LH]
+#define RSCAN0RMPTR38H RSCAN0.RMPTR38.UINT16[H]
+#define RSCAN0RMPTR38HL RSCAN0.RMPTR38.UINT8[HL]
+#define RSCAN0RMPTR38HH RSCAN0.RMPTR38.UINT8[HH]
+#define RSCAN0RMDF038 RSCAN0.RMDF038.UINT32
+#define RSCAN0RMDF038L RSCAN0.RMDF038.UINT16[L]
+#define RSCAN0RMDF038LL RSCAN0.RMDF038.UINT8[LL]
+#define RSCAN0RMDF038LH RSCAN0.RMDF038.UINT8[LH]
+#define RSCAN0RMDF038H RSCAN0.RMDF038.UINT16[H]
+#define RSCAN0RMDF038HL RSCAN0.RMDF038.UINT8[HL]
+#define RSCAN0RMDF038HH RSCAN0.RMDF038.UINT8[HH]
+#define RSCAN0RMDF138 RSCAN0.RMDF138.UINT32
+#define RSCAN0RMDF138L RSCAN0.RMDF138.UINT16[L]
+#define RSCAN0RMDF138LL RSCAN0.RMDF138.UINT8[LL]
+#define RSCAN0RMDF138LH RSCAN0.RMDF138.UINT8[LH]
+#define RSCAN0RMDF138H RSCAN0.RMDF138.UINT16[H]
+#define RSCAN0RMDF138HL RSCAN0.RMDF138.UINT8[HL]
+#define RSCAN0RMDF138HH RSCAN0.RMDF138.UINT8[HH]
+#define RSCAN0RMID39 RSCAN0.RMID39.UINT32
+#define RSCAN0RMID39L RSCAN0.RMID39.UINT16[L]
+#define RSCAN0RMID39LL RSCAN0.RMID39.UINT8[LL]
+#define RSCAN0RMID39LH RSCAN0.RMID39.UINT8[LH]
+#define RSCAN0RMID39H RSCAN0.RMID39.UINT16[H]
+#define RSCAN0RMID39HL RSCAN0.RMID39.UINT8[HL]
+#define RSCAN0RMID39HH RSCAN0.RMID39.UINT8[HH]
+#define RSCAN0RMPTR39 RSCAN0.RMPTR39.UINT32
+#define RSCAN0RMPTR39L RSCAN0.RMPTR39.UINT16[L]
+#define RSCAN0RMPTR39LL RSCAN0.RMPTR39.UINT8[LL]
+#define RSCAN0RMPTR39LH RSCAN0.RMPTR39.UINT8[LH]
+#define RSCAN0RMPTR39H RSCAN0.RMPTR39.UINT16[H]
+#define RSCAN0RMPTR39HL RSCAN0.RMPTR39.UINT8[HL]
+#define RSCAN0RMPTR39HH RSCAN0.RMPTR39.UINT8[HH]
+#define RSCAN0RMDF039 RSCAN0.RMDF039.UINT32
+#define RSCAN0RMDF039L RSCAN0.RMDF039.UINT16[L]
+#define RSCAN0RMDF039LL RSCAN0.RMDF039.UINT8[LL]
+#define RSCAN0RMDF039LH RSCAN0.RMDF039.UINT8[LH]
+#define RSCAN0RMDF039H RSCAN0.RMDF039.UINT16[H]
+#define RSCAN0RMDF039HL RSCAN0.RMDF039.UINT8[HL]
+#define RSCAN0RMDF039HH RSCAN0.RMDF039.UINT8[HH]
+#define RSCAN0RMDF139 RSCAN0.RMDF139.UINT32
+#define RSCAN0RMDF139L RSCAN0.RMDF139.UINT16[L]
+#define RSCAN0RMDF139LL RSCAN0.RMDF139.UINT8[LL]
+#define RSCAN0RMDF139LH RSCAN0.RMDF139.UINT8[LH]
+#define RSCAN0RMDF139H RSCAN0.RMDF139.UINT16[H]
+#define RSCAN0RMDF139HL RSCAN0.RMDF139.UINT8[HL]
+#define RSCAN0RMDF139HH RSCAN0.RMDF139.UINT8[HH]
+#define RSCAN0RMID40 RSCAN0.RMID40.UINT32
+#define RSCAN0RMID40L RSCAN0.RMID40.UINT16[L]
+#define RSCAN0RMID40LL RSCAN0.RMID40.UINT8[LL]
+#define RSCAN0RMID40LH RSCAN0.RMID40.UINT8[LH]
+#define RSCAN0RMID40H RSCAN0.RMID40.UINT16[H]
+#define RSCAN0RMID40HL RSCAN0.RMID40.UINT8[HL]
+#define RSCAN0RMID40HH RSCAN0.RMID40.UINT8[HH]
+#define RSCAN0RMPTR40 RSCAN0.RMPTR40.UINT32
+#define RSCAN0RMPTR40L RSCAN0.RMPTR40.UINT16[L]
+#define RSCAN0RMPTR40LL RSCAN0.RMPTR40.UINT8[LL]
+#define RSCAN0RMPTR40LH RSCAN0.RMPTR40.UINT8[LH]
+#define RSCAN0RMPTR40H RSCAN0.RMPTR40.UINT16[H]
+#define RSCAN0RMPTR40HL RSCAN0.RMPTR40.UINT8[HL]
+#define RSCAN0RMPTR40HH RSCAN0.RMPTR40.UINT8[HH]
+#define RSCAN0RMDF040 RSCAN0.RMDF040.UINT32
+#define RSCAN0RMDF040L RSCAN0.RMDF040.UINT16[L]
+#define RSCAN0RMDF040LL RSCAN0.RMDF040.UINT8[LL]
+#define RSCAN0RMDF040LH RSCAN0.RMDF040.UINT8[LH]
+#define RSCAN0RMDF040H RSCAN0.RMDF040.UINT16[H]
+#define RSCAN0RMDF040HL RSCAN0.RMDF040.UINT8[HL]
+#define RSCAN0RMDF040HH RSCAN0.RMDF040.UINT8[HH]
+#define RSCAN0RMDF140 RSCAN0.RMDF140.UINT32
+#define RSCAN0RMDF140L RSCAN0.RMDF140.UINT16[L]
+#define RSCAN0RMDF140LL RSCAN0.RMDF140.UINT8[LL]
+#define RSCAN0RMDF140LH RSCAN0.RMDF140.UINT8[LH]
+#define RSCAN0RMDF140H RSCAN0.RMDF140.UINT16[H]
+#define RSCAN0RMDF140HL RSCAN0.RMDF140.UINT8[HL]
+#define RSCAN0RMDF140HH RSCAN0.RMDF140.UINT8[HH]
+#define RSCAN0RMID41 RSCAN0.RMID41.UINT32
+#define RSCAN0RMID41L RSCAN0.RMID41.UINT16[L]
+#define RSCAN0RMID41LL RSCAN0.RMID41.UINT8[LL]
+#define RSCAN0RMID41LH RSCAN0.RMID41.UINT8[LH]
+#define RSCAN0RMID41H RSCAN0.RMID41.UINT16[H]
+#define RSCAN0RMID41HL RSCAN0.RMID41.UINT8[HL]
+#define RSCAN0RMID41HH RSCAN0.RMID41.UINT8[HH]
+#define RSCAN0RMPTR41 RSCAN0.RMPTR41.UINT32
+#define RSCAN0RMPTR41L RSCAN0.RMPTR41.UINT16[L]
+#define RSCAN0RMPTR41LL RSCAN0.RMPTR41.UINT8[LL]
+#define RSCAN0RMPTR41LH RSCAN0.RMPTR41.UINT8[LH]
+#define RSCAN0RMPTR41H RSCAN0.RMPTR41.UINT16[H]
+#define RSCAN0RMPTR41HL RSCAN0.RMPTR41.UINT8[HL]
+#define RSCAN0RMPTR41HH RSCAN0.RMPTR41.UINT8[HH]
+#define RSCAN0RMDF041 RSCAN0.RMDF041.UINT32
+#define RSCAN0RMDF041L RSCAN0.RMDF041.UINT16[L]
+#define RSCAN0RMDF041LL RSCAN0.RMDF041.UINT8[LL]
+#define RSCAN0RMDF041LH RSCAN0.RMDF041.UINT8[LH]
+#define RSCAN0RMDF041H RSCAN0.RMDF041.UINT16[H]
+#define RSCAN0RMDF041HL RSCAN0.RMDF041.UINT8[HL]
+#define RSCAN0RMDF041HH RSCAN0.RMDF041.UINT8[HH]
+#define RSCAN0RMDF141 RSCAN0.RMDF141.UINT32
+#define RSCAN0RMDF141L RSCAN0.RMDF141.UINT16[L]
+#define RSCAN0RMDF141LL RSCAN0.RMDF141.UINT8[LL]
+#define RSCAN0RMDF141LH RSCAN0.RMDF141.UINT8[LH]
+#define RSCAN0RMDF141H RSCAN0.RMDF141.UINT16[H]
+#define RSCAN0RMDF141HL RSCAN0.RMDF141.UINT8[HL]
+#define RSCAN0RMDF141HH RSCAN0.RMDF141.UINT8[HH]
+#define RSCAN0RMID42 RSCAN0.RMID42.UINT32
+#define RSCAN0RMID42L RSCAN0.RMID42.UINT16[L]
+#define RSCAN0RMID42LL RSCAN0.RMID42.UINT8[LL]
+#define RSCAN0RMID42LH RSCAN0.RMID42.UINT8[LH]
+#define RSCAN0RMID42H RSCAN0.RMID42.UINT16[H]
+#define RSCAN0RMID42HL RSCAN0.RMID42.UINT8[HL]
+#define RSCAN0RMID42HH RSCAN0.RMID42.UINT8[HH]
+#define RSCAN0RMPTR42 RSCAN0.RMPTR42.UINT32
+#define RSCAN0RMPTR42L RSCAN0.RMPTR42.UINT16[L]
+#define RSCAN0RMPTR42LL RSCAN0.RMPTR42.UINT8[LL]
+#define RSCAN0RMPTR42LH RSCAN0.RMPTR42.UINT8[LH]
+#define RSCAN0RMPTR42H RSCAN0.RMPTR42.UINT16[H]
+#define RSCAN0RMPTR42HL RSCAN0.RMPTR42.UINT8[HL]
+#define RSCAN0RMPTR42HH RSCAN0.RMPTR42.UINT8[HH]
+#define RSCAN0RMDF042 RSCAN0.RMDF042.UINT32
+#define RSCAN0RMDF042L RSCAN0.RMDF042.UINT16[L]
+#define RSCAN0RMDF042LL RSCAN0.RMDF042.UINT8[LL]
+#define RSCAN0RMDF042LH RSCAN0.RMDF042.UINT8[LH]
+#define RSCAN0RMDF042H RSCAN0.RMDF042.UINT16[H]
+#define RSCAN0RMDF042HL RSCAN0.RMDF042.UINT8[HL]
+#define RSCAN0RMDF042HH RSCAN0.RMDF042.UINT8[HH]
+#define RSCAN0RMDF142 RSCAN0.RMDF142.UINT32
+#define RSCAN0RMDF142L RSCAN0.RMDF142.UINT16[L]
+#define RSCAN0RMDF142LL RSCAN0.RMDF142.UINT8[LL]
+#define RSCAN0RMDF142LH RSCAN0.RMDF142.UINT8[LH]
+#define RSCAN0RMDF142H RSCAN0.RMDF142.UINT16[H]
+#define RSCAN0RMDF142HL RSCAN0.RMDF142.UINT8[HL]
+#define RSCAN0RMDF142HH RSCAN0.RMDF142.UINT8[HH]
+#define RSCAN0RMID43 RSCAN0.RMID43.UINT32
+#define RSCAN0RMID43L RSCAN0.RMID43.UINT16[L]
+#define RSCAN0RMID43LL RSCAN0.RMID43.UINT8[LL]
+#define RSCAN0RMID43LH RSCAN0.RMID43.UINT8[LH]
+#define RSCAN0RMID43H RSCAN0.RMID43.UINT16[H]
+#define RSCAN0RMID43HL RSCAN0.RMID43.UINT8[HL]
+#define RSCAN0RMID43HH RSCAN0.RMID43.UINT8[HH]
+#define RSCAN0RMPTR43 RSCAN0.RMPTR43.UINT32
+#define RSCAN0RMPTR43L RSCAN0.RMPTR43.UINT16[L]
+#define RSCAN0RMPTR43LL RSCAN0.RMPTR43.UINT8[LL]
+#define RSCAN0RMPTR43LH RSCAN0.RMPTR43.UINT8[LH]
+#define RSCAN0RMPTR43H RSCAN0.RMPTR43.UINT16[H]
+#define RSCAN0RMPTR43HL RSCAN0.RMPTR43.UINT8[HL]
+#define RSCAN0RMPTR43HH RSCAN0.RMPTR43.UINT8[HH]
+#define RSCAN0RMDF043 RSCAN0.RMDF043.UINT32
+#define RSCAN0RMDF043L RSCAN0.RMDF043.UINT16[L]
+#define RSCAN0RMDF043LL RSCAN0.RMDF043.UINT8[LL]
+#define RSCAN0RMDF043LH RSCAN0.RMDF043.UINT8[LH]
+#define RSCAN0RMDF043H RSCAN0.RMDF043.UINT16[H]
+#define RSCAN0RMDF043HL RSCAN0.RMDF043.UINT8[HL]
+#define RSCAN0RMDF043HH RSCAN0.RMDF043.UINT8[HH]
+#define RSCAN0RMDF143 RSCAN0.RMDF143.UINT32
+#define RSCAN0RMDF143L RSCAN0.RMDF143.UINT16[L]
+#define RSCAN0RMDF143LL RSCAN0.RMDF143.UINT8[LL]
+#define RSCAN0RMDF143LH RSCAN0.RMDF143.UINT8[LH]
+#define RSCAN0RMDF143H RSCAN0.RMDF143.UINT16[H]
+#define RSCAN0RMDF143HL RSCAN0.RMDF143.UINT8[HL]
+#define RSCAN0RMDF143HH RSCAN0.RMDF143.UINT8[HH]
+#define RSCAN0RMID44 RSCAN0.RMID44.UINT32
+#define RSCAN0RMID44L RSCAN0.RMID44.UINT16[L]
+#define RSCAN0RMID44LL RSCAN0.RMID44.UINT8[LL]
+#define RSCAN0RMID44LH RSCAN0.RMID44.UINT8[LH]
+#define RSCAN0RMID44H RSCAN0.RMID44.UINT16[H]
+#define RSCAN0RMID44HL RSCAN0.RMID44.UINT8[HL]
+#define RSCAN0RMID44HH RSCAN0.RMID44.UINT8[HH]
+#define RSCAN0RMPTR44 RSCAN0.RMPTR44.UINT32
+#define RSCAN0RMPTR44L RSCAN0.RMPTR44.UINT16[L]
+#define RSCAN0RMPTR44LL RSCAN0.RMPTR44.UINT8[LL]
+#define RSCAN0RMPTR44LH RSCAN0.RMPTR44.UINT8[LH]
+#define RSCAN0RMPTR44H RSCAN0.RMPTR44.UINT16[H]
+#define RSCAN0RMPTR44HL RSCAN0.RMPTR44.UINT8[HL]
+#define RSCAN0RMPTR44HH RSCAN0.RMPTR44.UINT8[HH]
+#define RSCAN0RMDF044 RSCAN0.RMDF044.UINT32
+#define RSCAN0RMDF044L RSCAN0.RMDF044.UINT16[L]
+#define RSCAN0RMDF044LL RSCAN0.RMDF044.UINT8[LL]
+#define RSCAN0RMDF044LH RSCAN0.RMDF044.UINT8[LH]
+#define RSCAN0RMDF044H RSCAN0.RMDF044.UINT16[H]
+#define RSCAN0RMDF044HL RSCAN0.RMDF044.UINT8[HL]
+#define RSCAN0RMDF044HH RSCAN0.RMDF044.UINT8[HH]
+#define RSCAN0RMDF144 RSCAN0.RMDF144.UINT32
+#define RSCAN0RMDF144L RSCAN0.RMDF144.UINT16[L]
+#define RSCAN0RMDF144LL RSCAN0.RMDF144.UINT8[LL]
+#define RSCAN0RMDF144LH RSCAN0.RMDF144.UINT8[LH]
+#define RSCAN0RMDF144H RSCAN0.RMDF144.UINT16[H]
+#define RSCAN0RMDF144HL RSCAN0.RMDF144.UINT8[HL]
+#define RSCAN0RMDF144HH RSCAN0.RMDF144.UINT8[HH]
+#define RSCAN0RMID45 RSCAN0.RMID45.UINT32
+#define RSCAN0RMID45L RSCAN0.RMID45.UINT16[L]
+#define RSCAN0RMID45LL RSCAN0.RMID45.UINT8[LL]
+#define RSCAN0RMID45LH RSCAN0.RMID45.UINT8[LH]
+#define RSCAN0RMID45H RSCAN0.RMID45.UINT16[H]
+#define RSCAN0RMID45HL RSCAN0.RMID45.UINT8[HL]
+#define RSCAN0RMID45HH RSCAN0.RMID45.UINT8[HH]
+#define RSCAN0RMPTR45 RSCAN0.RMPTR45.UINT32
+#define RSCAN0RMPTR45L RSCAN0.RMPTR45.UINT16[L]
+#define RSCAN0RMPTR45LL RSCAN0.RMPTR45.UINT8[LL]
+#define RSCAN0RMPTR45LH RSCAN0.RMPTR45.UINT8[LH]
+#define RSCAN0RMPTR45H RSCAN0.RMPTR45.UINT16[H]
+#define RSCAN0RMPTR45HL RSCAN0.RMPTR45.UINT8[HL]
+#define RSCAN0RMPTR45HH RSCAN0.RMPTR45.UINT8[HH]
+#define RSCAN0RMDF045 RSCAN0.RMDF045.UINT32
+#define RSCAN0RMDF045L RSCAN0.RMDF045.UINT16[L]
+#define RSCAN0RMDF045LL RSCAN0.RMDF045.UINT8[LL]
+#define RSCAN0RMDF045LH RSCAN0.RMDF045.UINT8[LH]
+#define RSCAN0RMDF045H RSCAN0.RMDF045.UINT16[H]
+#define RSCAN0RMDF045HL RSCAN0.RMDF045.UINT8[HL]
+#define RSCAN0RMDF045HH RSCAN0.RMDF045.UINT8[HH]
+#define RSCAN0RMDF145 RSCAN0.RMDF145.UINT32
+#define RSCAN0RMDF145L RSCAN0.RMDF145.UINT16[L]
+#define RSCAN0RMDF145LL RSCAN0.RMDF145.UINT8[LL]
+#define RSCAN0RMDF145LH RSCAN0.RMDF145.UINT8[LH]
+#define RSCAN0RMDF145H RSCAN0.RMDF145.UINT16[H]
+#define RSCAN0RMDF145HL RSCAN0.RMDF145.UINT8[HL]
+#define RSCAN0RMDF145HH RSCAN0.RMDF145.UINT8[HH]
+#define RSCAN0RMID46 RSCAN0.RMID46.UINT32
+#define RSCAN0RMID46L RSCAN0.RMID46.UINT16[L]
+#define RSCAN0RMID46LL RSCAN0.RMID46.UINT8[LL]
+#define RSCAN0RMID46LH RSCAN0.RMID46.UINT8[LH]
+#define RSCAN0RMID46H RSCAN0.RMID46.UINT16[H]
+#define RSCAN0RMID46HL RSCAN0.RMID46.UINT8[HL]
+#define RSCAN0RMID46HH RSCAN0.RMID46.UINT8[HH]
+#define RSCAN0RMPTR46 RSCAN0.RMPTR46.UINT32
+#define RSCAN0RMPTR46L RSCAN0.RMPTR46.UINT16[L]
+#define RSCAN0RMPTR46LL RSCAN0.RMPTR46.UINT8[LL]
+#define RSCAN0RMPTR46LH RSCAN0.RMPTR46.UINT8[LH]
+#define RSCAN0RMPTR46H RSCAN0.RMPTR46.UINT16[H]
+#define RSCAN0RMPTR46HL RSCAN0.RMPTR46.UINT8[HL]
+#define RSCAN0RMPTR46HH RSCAN0.RMPTR46.UINT8[HH]
+#define RSCAN0RMDF046 RSCAN0.RMDF046.UINT32
+#define RSCAN0RMDF046L RSCAN0.RMDF046.UINT16[L]
+#define RSCAN0RMDF046LL RSCAN0.RMDF046.UINT8[LL]
+#define RSCAN0RMDF046LH RSCAN0.RMDF046.UINT8[LH]
+#define RSCAN0RMDF046H RSCAN0.RMDF046.UINT16[H]
+#define RSCAN0RMDF046HL RSCAN0.RMDF046.UINT8[HL]
+#define RSCAN0RMDF046HH RSCAN0.RMDF046.UINT8[HH]
+#define RSCAN0RMDF146 RSCAN0.RMDF146.UINT32
+#define RSCAN0RMDF146L RSCAN0.RMDF146.UINT16[L]
+#define RSCAN0RMDF146LL RSCAN0.RMDF146.UINT8[LL]
+#define RSCAN0RMDF146LH RSCAN0.RMDF146.UINT8[LH]
+#define RSCAN0RMDF146H RSCAN0.RMDF146.UINT16[H]
+#define RSCAN0RMDF146HL RSCAN0.RMDF146.UINT8[HL]
+#define RSCAN0RMDF146HH RSCAN0.RMDF146.UINT8[HH]
+#define RSCAN0RMID47 RSCAN0.RMID47.UINT32
+#define RSCAN0RMID47L RSCAN0.RMID47.UINT16[L]
+#define RSCAN0RMID47LL RSCAN0.RMID47.UINT8[LL]
+#define RSCAN0RMID47LH RSCAN0.RMID47.UINT8[LH]
+#define RSCAN0RMID47H RSCAN0.RMID47.UINT16[H]
+#define RSCAN0RMID47HL RSCAN0.RMID47.UINT8[HL]
+#define RSCAN0RMID47HH RSCAN0.RMID47.UINT8[HH]
+#define RSCAN0RMPTR47 RSCAN0.RMPTR47.UINT32
+#define RSCAN0RMPTR47L RSCAN0.RMPTR47.UINT16[L]
+#define RSCAN0RMPTR47LL RSCAN0.RMPTR47.UINT8[LL]
+#define RSCAN0RMPTR47LH RSCAN0.RMPTR47.UINT8[LH]
+#define RSCAN0RMPTR47H RSCAN0.RMPTR47.UINT16[H]
+#define RSCAN0RMPTR47HL RSCAN0.RMPTR47.UINT8[HL]
+#define RSCAN0RMPTR47HH RSCAN0.RMPTR47.UINT8[HH]
+#define RSCAN0RMDF047 RSCAN0.RMDF047.UINT32
+#define RSCAN0RMDF047L RSCAN0.RMDF047.UINT16[L]
+#define RSCAN0RMDF047LL RSCAN0.RMDF047.UINT8[LL]
+#define RSCAN0RMDF047LH RSCAN0.RMDF047.UINT8[LH]
+#define RSCAN0RMDF047H RSCAN0.RMDF047.UINT16[H]
+#define RSCAN0RMDF047HL RSCAN0.RMDF047.UINT8[HL]
+#define RSCAN0RMDF047HH RSCAN0.RMDF047.UINT8[HH]
+#define RSCAN0RMDF147 RSCAN0.RMDF147.UINT32
+#define RSCAN0RMDF147L RSCAN0.RMDF147.UINT16[L]
+#define RSCAN0RMDF147LL RSCAN0.RMDF147.UINT8[LL]
+#define RSCAN0RMDF147LH RSCAN0.RMDF147.UINT8[LH]
+#define RSCAN0RMDF147H RSCAN0.RMDF147.UINT16[H]
+#define RSCAN0RMDF147HL RSCAN0.RMDF147.UINT8[HL]
+#define RSCAN0RMDF147HH RSCAN0.RMDF147.UINT8[HH]
+#define RSCAN0RMID48 RSCAN0.RMID48.UINT32
+#define RSCAN0RMID48L RSCAN0.RMID48.UINT16[L]
+#define RSCAN0RMID48LL RSCAN0.RMID48.UINT8[LL]
+#define RSCAN0RMID48LH RSCAN0.RMID48.UINT8[LH]
+#define RSCAN0RMID48H RSCAN0.RMID48.UINT16[H]
+#define RSCAN0RMID48HL RSCAN0.RMID48.UINT8[HL]
+#define RSCAN0RMID48HH RSCAN0.RMID48.UINT8[HH]
+#define RSCAN0RMPTR48 RSCAN0.RMPTR48.UINT32
+#define RSCAN0RMPTR48L RSCAN0.RMPTR48.UINT16[L]
+#define RSCAN0RMPTR48LL RSCAN0.RMPTR48.UINT8[LL]
+#define RSCAN0RMPTR48LH RSCAN0.RMPTR48.UINT8[LH]
+#define RSCAN0RMPTR48H RSCAN0.RMPTR48.UINT16[H]
+#define RSCAN0RMPTR48HL RSCAN0.RMPTR48.UINT8[HL]
+#define RSCAN0RMPTR48HH RSCAN0.RMPTR48.UINT8[HH]
+#define RSCAN0RMDF048 RSCAN0.RMDF048.UINT32
+#define RSCAN0RMDF048L RSCAN0.RMDF048.UINT16[L]
+#define RSCAN0RMDF048LL RSCAN0.RMDF048.UINT8[LL]
+#define RSCAN0RMDF048LH RSCAN0.RMDF048.UINT8[LH]
+#define RSCAN0RMDF048H RSCAN0.RMDF048.UINT16[H]
+#define RSCAN0RMDF048HL RSCAN0.RMDF048.UINT8[HL]
+#define RSCAN0RMDF048HH RSCAN0.RMDF048.UINT8[HH]
+#define RSCAN0RMDF148 RSCAN0.RMDF148.UINT32
+#define RSCAN0RMDF148L RSCAN0.RMDF148.UINT16[L]
+#define RSCAN0RMDF148LL RSCAN0.RMDF148.UINT8[LL]
+#define RSCAN0RMDF148LH RSCAN0.RMDF148.UINT8[LH]
+#define RSCAN0RMDF148H RSCAN0.RMDF148.UINT16[H]
+#define RSCAN0RMDF148HL RSCAN0.RMDF148.UINT8[HL]
+#define RSCAN0RMDF148HH RSCAN0.RMDF148.UINT8[HH]
+#define RSCAN0RMID49 RSCAN0.RMID49.UINT32
+#define RSCAN0RMID49L RSCAN0.RMID49.UINT16[L]
+#define RSCAN0RMID49LL RSCAN0.RMID49.UINT8[LL]
+#define RSCAN0RMID49LH RSCAN0.RMID49.UINT8[LH]
+#define RSCAN0RMID49H RSCAN0.RMID49.UINT16[H]
+#define RSCAN0RMID49HL RSCAN0.RMID49.UINT8[HL]
+#define RSCAN0RMID49HH RSCAN0.RMID49.UINT8[HH]
+#define RSCAN0RMPTR49 RSCAN0.RMPTR49.UINT32
+#define RSCAN0RMPTR49L RSCAN0.RMPTR49.UINT16[L]
+#define RSCAN0RMPTR49LL RSCAN0.RMPTR49.UINT8[LL]
+#define RSCAN0RMPTR49LH RSCAN0.RMPTR49.UINT8[LH]
+#define RSCAN0RMPTR49H RSCAN0.RMPTR49.UINT16[H]
+#define RSCAN0RMPTR49HL RSCAN0.RMPTR49.UINT8[HL]
+#define RSCAN0RMPTR49HH RSCAN0.RMPTR49.UINT8[HH]
+#define RSCAN0RMDF049 RSCAN0.RMDF049.UINT32
+#define RSCAN0RMDF049L RSCAN0.RMDF049.UINT16[L]
+#define RSCAN0RMDF049LL RSCAN0.RMDF049.UINT8[LL]
+#define RSCAN0RMDF049LH RSCAN0.RMDF049.UINT8[LH]
+#define RSCAN0RMDF049H RSCAN0.RMDF049.UINT16[H]
+#define RSCAN0RMDF049HL RSCAN0.RMDF049.UINT8[HL]
+#define RSCAN0RMDF049HH RSCAN0.RMDF049.UINT8[HH]
+#define RSCAN0RMDF149 RSCAN0.RMDF149.UINT32
+#define RSCAN0RMDF149L RSCAN0.RMDF149.UINT16[L]
+#define RSCAN0RMDF149LL RSCAN0.RMDF149.UINT8[LL]
+#define RSCAN0RMDF149LH RSCAN0.RMDF149.UINT8[LH]
+#define RSCAN0RMDF149H RSCAN0.RMDF149.UINT16[H]
+#define RSCAN0RMDF149HL RSCAN0.RMDF149.UINT8[HL]
+#define RSCAN0RMDF149HH RSCAN0.RMDF149.UINT8[HH]
+#define RSCAN0RMID50 RSCAN0.RMID50.UINT32
+#define RSCAN0RMID50L RSCAN0.RMID50.UINT16[L]
+#define RSCAN0RMID50LL RSCAN0.RMID50.UINT8[LL]
+#define RSCAN0RMID50LH RSCAN0.RMID50.UINT8[LH]
+#define RSCAN0RMID50H RSCAN0.RMID50.UINT16[H]
+#define RSCAN0RMID50HL RSCAN0.RMID50.UINT8[HL]
+#define RSCAN0RMID50HH RSCAN0.RMID50.UINT8[HH]
+#define RSCAN0RMPTR50 RSCAN0.RMPTR50.UINT32
+#define RSCAN0RMPTR50L RSCAN0.RMPTR50.UINT16[L]
+#define RSCAN0RMPTR50LL RSCAN0.RMPTR50.UINT8[LL]
+#define RSCAN0RMPTR50LH RSCAN0.RMPTR50.UINT8[LH]
+#define RSCAN0RMPTR50H RSCAN0.RMPTR50.UINT16[H]
+#define RSCAN0RMPTR50HL RSCAN0.RMPTR50.UINT8[HL]
+#define RSCAN0RMPTR50HH RSCAN0.RMPTR50.UINT8[HH]
+#define RSCAN0RMDF050 RSCAN0.RMDF050.UINT32
+#define RSCAN0RMDF050L RSCAN0.RMDF050.UINT16[L]
+#define RSCAN0RMDF050LL RSCAN0.RMDF050.UINT8[LL]
+#define RSCAN0RMDF050LH RSCAN0.RMDF050.UINT8[LH]
+#define RSCAN0RMDF050H RSCAN0.RMDF050.UINT16[H]
+#define RSCAN0RMDF050HL RSCAN0.RMDF050.UINT8[HL]
+#define RSCAN0RMDF050HH RSCAN0.RMDF050.UINT8[HH]
+#define RSCAN0RMDF150 RSCAN0.RMDF150.UINT32
+#define RSCAN0RMDF150L RSCAN0.RMDF150.UINT16[L]
+#define RSCAN0RMDF150LL RSCAN0.RMDF150.UINT8[LL]
+#define RSCAN0RMDF150LH RSCAN0.RMDF150.UINT8[LH]
+#define RSCAN0RMDF150H RSCAN0.RMDF150.UINT16[H]
+#define RSCAN0RMDF150HL RSCAN0.RMDF150.UINT8[HL]
+#define RSCAN0RMDF150HH RSCAN0.RMDF150.UINT8[HH]
+#define RSCAN0RMID51 RSCAN0.RMID51.UINT32
+#define RSCAN0RMID51L RSCAN0.RMID51.UINT16[L]
+#define RSCAN0RMID51LL RSCAN0.RMID51.UINT8[LL]
+#define RSCAN0RMID51LH RSCAN0.RMID51.UINT8[LH]
+#define RSCAN0RMID51H RSCAN0.RMID51.UINT16[H]
+#define RSCAN0RMID51HL RSCAN0.RMID51.UINT8[HL]
+#define RSCAN0RMID51HH RSCAN0.RMID51.UINT8[HH]
+#define RSCAN0RMPTR51 RSCAN0.RMPTR51.UINT32
+#define RSCAN0RMPTR51L RSCAN0.RMPTR51.UINT16[L]
+#define RSCAN0RMPTR51LL RSCAN0.RMPTR51.UINT8[LL]
+#define RSCAN0RMPTR51LH RSCAN0.RMPTR51.UINT8[LH]
+#define RSCAN0RMPTR51H RSCAN0.RMPTR51.UINT16[H]
+#define RSCAN0RMPTR51HL RSCAN0.RMPTR51.UINT8[HL]
+#define RSCAN0RMPTR51HH RSCAN0.RMPTR51.UINT8[HH]
+#define RSCAN0RMDF051 RSCAN0.RMDF051.UINT32
+#define RSCAN0RMDF051L RSCAN0.RMDF051.UINT16[L]
+#define RSCAN0RMDF051LL RSCAN0.RMDF051.UINT8[LL]
+#define RSCAN0RMDF051LH RSCAN0.RMDF051.UINT8[LH]
+#define RSCAN0RMDF051H RSCAN0.RMDF051.UINT16[H]
+#define RSCAN0RMDF051HL RSCAN0.RMDF051.UINT8[HL]
+#define RSCAN0RMDF051HH RSCAN0.RMDF051.UINT8[HH]
+#define RSCAN0RMDF151 RSCAN0.RMDF151.UINT32
+#define RSCAN0RMDF151L RSCAN0.RMDF151.UINT16[L]
+#define RSCAN0RMDF151LL RSCAN0.RMDF151.UINT8[LL]
+#define RSCAN0RMDF151LH RSCAN0.RMDF151.UINT8[LH]
+#define RSCAN0RMDF151H RSCAN0.RMDF151.UINT16[H]
+#define RSCAN0RMDF151HL RSCAN0.RMDF151.UINT8[HL]
+#define RSCAN0RMDF151HH RSCAN0.RMDF151.UINT8[HH]
+#define RSCAN0RMID52 RSCAN0.RMID52.UINT32
+#define RSCAN0RMID52L RSCAN0.RMID52.UINT16[L]
+#define RSCAN0RMID52LL RSCAN0.RMID52.UINT8[LL]
+#define RSCAN0RMID52LH RSCAN0.RMID52.UINT8[LH]
+#define RSCAN0RMID52H RSCAN0.RMID52.UINT16[H]
+#define RSCAN0RMID52HL RSCAN0.RMID52.UINT8[HL]
+#define RSCAN0RMID52HH RSCAN0.RMID52.UINT8[HH]
+#define RSCAN0RMPTR52 RSCAN0.RMPTR52.UINT32
+#define RSCAN0RMPTR52L RSCAN0.RMPTR52.UINT16[L]
+#define RSCAN0RMPTR52LL RSCAN0.RMPTR52.UINT8[LL]
+#define RSCAN0RMPTR52LH RSCAN0.RMPTR52.UINT8[LH]
+#define RSCAN0RMPTR52H RSCAN0.RMPTR52.UINT16[H]
+#define RSCAN0RMPTR52HL RSCAN0.RMPTR52.UINT8[HL]
+#define RSCAN0RMPTR52HH RSCAN0.RMPTR52.UINT8[HH]
+#define RSCAN0RMDF052 RSCAN0.RMDF052.UINT32
+#define RSCAN0RMDF052L RSCAN0.RMDF052.UINT16[L]
+#define RSCAN0RMDF052LL RSCAN0.RMDF052.UINT8[LL]
+#define RSCAN0RMDF052LH RSCAN0.RMDF052.UINT8[LH]
+#define RSCAN0RMDF052H RSCAN0.RMDF052.UINT16[H]
+#define RSCAN0RMDF052HL RSCAN0.RMDF052.UINT8[HL]
+#define RSCAN0RMDF052HH RSCAN0.RMDF052.UINT8[HH]
+#define RSCAN0RMDF152 RSCAN0.RMDF152.UINT32
+#define RSCAN0RMDF152L RSCAN0.RMDF152.UINT16[L]
+#define RSCAN0RMDF152LL RSCAN0.RMDF152.UINT8[LL]
+#define RSCAN0RMDF152LH RSCAN0.RMDF152.UINT8[LH]
+#define RSCAN0RMDF152H RSCAN0.RMDF152.UINT16[H]
+#define RSCAN0RMDF152HL RSCAN0.RMDF152.UINT8[HL]
+#define RSCAN0RMDF152HH RSCAN0.RMDF152.UINT8[HH]
+#define RSCAN0RMID53 RSCAN0.RMID53.UINT32
+#define RSCAN0RMID53L RSCAN0.RMID53.UINT16[L]
+#define RSCAN0RMID53LL RSCAN0.RMID53.UINT8[LL]
+#define RSCAN0RMID53LH RSCAN0.RMID53.UINT8[LH]
+#define RSCAN0RMID53H RSCAN0.RMID53.UINT16[H]
+#define RSCAN0RMID53HL RSCAN0.RMID53.UINT8[HL]
+#define RSCAN0RMID53HH RSCAN0.RMID53.UINT8[HH]
+#define RSCAN0RMPTR53 RSCAN0.RMPTR53.UINT32
+#define RSCAN0RMPTR53L RSCAN0.RMPTR53.UINT16[L]
+#define RSCAN0RMPTR53LL RSCAN0.RMPTR53.UINT8[LL]
+#define RSCAN0RMPTR53LH RSCAN0.RMPTR53.UINT8[LH]
+#define RSCAN0RMPTR53H RSCAN0.RMPTR53.UINT16[H]
+#define RSCAN0RMPTR53HL RSCAN0.RMPTR53.UINT8[HL]
+#define RSCAN0RMPTR53HH RSCAN0.RMPTR53.UINT8[HH]
+#define RSCAN0RMDF053 RSCAN0.RMDF053.UINT32
+#define RSCAN0RMDF053L RSCAN0.RMDF053.UINT16[L]
+#define RSCAN0RMDF053LL RSCAN0.RMDF053.UINT8[LL]
+#define RSCAN0RMDF053LH RSCAN0.RMDF053.UINT8[LH]
+#define RSCAN0RMDF053H RSCAN0.RMDF053.UINT16[H]
+#define RSCAN0RMDF053HL RSCAN0.RMDF053.UINT8[HL]
+#define RSCAN0RMDF053HH RSCAN0.RMDF053.UINT8[HH]
+#define RSCAN0RMDF153 RSCAN0.RMDF153.UINT32
+#define RSCAN0RMDF153L RSCAN0.RMDF153.UINT16[L]
+#define RSCAN0RMDF153LL RSCAN0.RMDF153.UINT8[LL]
+#define RSCAN0RMDF153LH RSCAN0.RMDF153.UINT8[LH]
+#define RSCAN0RMDF153H RSCAN0.RMDF153.UINT16[H]
+#define RSCAN0RMDF153HL RSCAN0.RMDF153.UINT8[HL]
+#define RSCAN0RMDF153HH RSCAN0.RMDF153.UINT8[HH]
+#define RSCAN0RMID54 RSCAN0.RMID54.UINT32
+#define RSCAN0RMID54L RSCAN0.RMID54.UINT16[L]
+#define RSCAN0RMID54LL RSCAN0.RMID54.UINT8[LL]
+#define RSCAN0RMID54LH RSCAN0.RMID54.UINT8[LH]
+#define RSCAN0RMID54H RSCAN0.RMID54.UINT16[H]
+#define RSCAN0RMID54HL RSCAN0.RMID54.UINT8[HL]
+#define RSCAN0RMID54HH RSCAN0.RMID54.UINT8[HH]
+#define RSCAN0RMPTR54 RSCAN0.RMPTR54.UINT32
+#define RSCAN0RMPTR54L RSCAN0.RMPTR54.UINT16[L]
+#define RSCAN0RMPTR54LL RSCAN0.RMPTR54.UINT8[LL]
+#define RSCAN0RMPTR54LH RSCAN0.RMPTR54.UINT8[LH]
+#define RSCAN0RMPTR54H RSCAN0.RMPTR54.UINT16[H]
+#define RSCAN0RMPTR54HL RSCAN0.RMPTR54.UINT8[HL]
+#define RSCAN0RMPTR54HH RSCAN0.RMPTR54.UINT8[HH]
+#define RSCAN0RMDF054 RSCAN0.RMDF054.UINT32
+#define RSCAN0RMDF054L RSCAN0.RMDF054.UINT16[L]
+#define RSCAN0RMDF054LL RSCAN0.RMDF054.UINT8[LL]
+#define RSCAN0RMDF054LH RSCAN0.RMDF054.UINT8[LH]
+#define RSCAN0RMDF054H RSCAN0.RMDF054.UINT16[H]
+#define RSCAN0RMDF054HL RSCAN0.RMDF054.UINT8[HL]
+#define RSCAN0RMDF054HH RSCAN0.RMDF054.UINT8[HH]
+#define RSCAN0RMDF154 RSCAN0.RMDF154.UINT32
+#define RSCAN0RMDF154L RSCAN0.RMDF154.UINT16[L]
+#define RSCAN0RMDF154LL RSCAN0.RMDF154.UINT8[LL]
+#define RSCAN0RMDF154LH RSCAN0.RMDF154.UINT8[LH]
+#define RSCAN0RMDF154H RSCAN0.RMDF154.UINT16[H]
+#define RSCAN0RMDF154HL RSCAN0.RMDF154.UINT8[HL]
+#define RSCAN0RMDF154HH RSCAN0.RMDF154.UINT8[HH]
+#define RSCAN0RMID55 RSCAN0.RMID55.UINT32
+#define RSCAN0RMID55L RSCAN0.RMID55.UINT16[L]
+#define RSCAN0RMID55LL RSCAN0.RMID55.UINT8[LL]
+#define RSCAN0RMID55LH RSCAN0.RMID55.UINT8[LH]
+#define RSCAN0RMID55H RSCAN0.RMID55.UINT16[H]
+#define RSCAN0RMID55HL RSCAN0.RMID55.UINT8[HL]
+#define RSCAN0RMID55HH RSCAN0.RMID55.UINT8[HH]
+#define RSCAN0RMPTR55 RSCAN0.RMPTR55.UINT32
+#define RSCAN0RMPTR55L RSCAN0.RMPTR55.UINT16[L]
+#define RSCAN0RMPTR55LL RSCAN0.RMPTR55.UINT8[LL]
+#define RSCAN0RMPTR55LH RSCAN0.RMPTR55.UINT8[LH]
+#define RSCAN0RMPTR55H RSCAN0.RMPTR55.UINT16[H]
+#define RSCAN0RMPTR55HL RSCAN0.RMPTR55.UINT8[HL]
+#define RSCAN0RMPTR55HH RSCAN0.RMPTR55.UINT8[HH]
+#define RSCAN0RMDF055 RSCAN0.RMDF055.UINT32
+#define RSCAN0RMDF055L RSCAN0.RMDF055.UINT16[L]
+#define RSCAN0RMDF055LL RSCAN0.RMDF055.UINT8[LL]
+#define RSCAN0RMDF055LH RSCAN0.RMDF055.UINT8[LH]
+#define RSCAN0RMDF055H RSCAN0.RMDF055.UINT16[H]
+#define RSCAN0RMDF055HL RSCAN0.RMDF055.UINT8[HL]
+#define RSCAN0RMDF055HH RSCAN0.RMDF055.UINT8[HH]
+#define RSCAN0RMDF155 RSCAN0.RMDF155.UINT32
+#define RSCAN0RMDF155L RSCAN0.RMDF155.UINT16[L]
+#define RSCAN0RMDF155LL RSCAN0.RMDF155.UINT8[LL]
+#define RSCAN0RMDF155LH RSCAN0.RMDF155.UINT8[LH]
+#define RSCAN0RMDF155H RSCAN0.RMDF155.UINT16[H]
+#define RSCAN0RMDF155HL RSCAN0.RMDF155.UINT8[HL]
+#define RSCAN0RMDF155HH RSCAN0.RMDF155.UINT8[HH]
+#define RSCAN0RMID56 RSCAN0.RMID56.UINT32
+#define RSCAN0RMID56L RSCAN0.RMID56.UINT16[L]
+#define RSCAN0RMID56LL RSCAN0.RMID56.UINT8[LL]
+#define RSCAN0RMID56LH RSCAN0.RMID56.UINT8[LH]
+#define RSCAN0RMID56H RSCAN0.RMID56.UINT16[H]
+#define RSCAN0RMID56HL RSCAN0.RMID56.UINT8[HL]
+#define RSCAN0RMID56HH RSCAN0.RMID56.UINT8[HH]
+#define RSCAN0RMPTR56 RSCAN0.RMPTR56.UINT32
+#define RSCAN0RMPTR56L RSCAN0.RMPTR56.UINT16[L]
+#define RSCAN0RMPTR56LL RSCAN0.RMPTR56.UINT8[LL]
+#define RSCAN0RMPTR56LH RSCAN0.RMPTR56.UINT8[LH]
+#define RSCAN0RMPTR56H RSCAN0.RMPTR56.UINT16[H]
+#define RSCAN0RMPTR56HL RSCAN0.RMPTR56.UINT8[HL]
+#define RSCAN0RMPTR56HH RSCAN0.RMPTR56.UINT8[HH]
+#define RSCAN0RMDF056 RSCAN0.RMDF056.UINT32
+#define RSCAN0RMDF056L RSCAN0.RMDF056.UINT16[L]
+#define RSCAN0RMDF056LL RSCAN0.RMDF056.UINT8[LL]
+#define RSCAN0RMDF056LH RSCAN0.RMDF056.UINT8[LH]
+#define RSCAN0RMDF056H RSCAN0.RMDF056.UINT16[H]
+#define RSCAN0RMDF056HL RSCAN0.RMDF056.UINT8[HL]
+#define RSCAN0RMDF056HH RSCAN0.RMDF056.UINT8[HH]
+#define RSCAN0RMDF156 RSCAN0.RMDF156.UINT32
+#define RSCAN0RMDF156L RSCAN0.RMDF156.UINT16[L]
+#define RSCAN0RMDF156LL RSCAN0.RMDF156.UINT8[LL]
+#define RSCAN0RMDF156LH RSCAN0.RMDF156.UINT8[LH]
+#define RSCAN0RMDF156H RSCAN0.RMDF156.UINT16[H]
+#define RSCAN0RMDF156HL RSCAN0.RMDF156.UINT8[HL]
+#define RSCAN0RMDF156HH RSCAN0.RMDF156.UINT8[HH]
+#define RSCAN0RMID57 RSCAN0.RMID57.UINT32
+#define RSCAN0RMID57L RSCAN0.RMID57.UINT16[L]
+#define RSCAN0RMID57LL RSCAN0.RMID57.UINT8[LL]
+#define RSCAN0RMID57LH RSCAN0.RMID57.UINT8[LH]
+#define RSCAN0RMID57H RSCAN0.RMID57.UINT16[H]
+#define RSCAN0RMID57HL RSCAN0.RMID57.UINT8[HL]
+#define RSCAN0RMID57HH RSCAN0.RMID57.UINT8[HH]
+#define RSCAN0RMPTR57 RSCAN0.RMPTR57.UINT32
+#define RSCAN0RMPTR57L RSCAN0.RMPTR57.UINT16[L]
+#define RSCAN0RMPTR57LL RSCAN0.RMPTR57.UINT8[LL]
+#define RSCAN0RMPTR57LH RSCAN0.RMPTR57.UINT8[LH]
+#define RSCAN0RMPTR57H RSCAN0.RMPTR57.UINT16[H]
+#define RSCAN0RMPTR57HL RSCAN0.RMPTR57.UINT8[HL]
+#define RSCAN0RMPTR57HH RSCAN0.RMPTR57.UINT8[HH]
+#define RSCAN0RMDF057 RSCAN0.RMDF057.UINT32
+#define RSCAN0RMDF057L RSCAN0.RMDF057.UINT16[L]
+#define RSCAN0RMDF057LL RSCAN0.RMDF057.UINT8[LL]
+#define RSCAN0RMDF057LH RSCAN0.RMDF057.UINT8[LH]
+#define RSCAN0RMDF057H RSCAN0.RMDF057.UINT16[H]
+#define RSCAN0RMDF057HL RSCAN0.RMDF057.UINT8[HL]
+#define RSCAN0RMDF057HH RSCAN0.RMDF057.UINT8[HH]
+#define RSCAN0RMDF157 RSCAN0.RMDF157.UINT32
+#define RSCAN0RMDF157L RSCAN0.RMDF157.UINT16[L]
+#define RSCAN0RMDF157LL RSCAN0.RMDF157.UINT8[LL]
+#define RSCAN0RMDF157LH RSCAN0.RMDF157.UINT8[LH]
+#define RSCAN0RMDF157H RSCAN0.RMDF157.UINT16[H]
+#define RSCAN0RMDF157HL RSCAN0.RMDF157.UINT8[HL]
+#define RSCAN0RMDF157HH RSCAN0.RMDF157.UINT8[HH]
+#define RSCAN0RMID58 RSCAN0.RMID58.UINT32
+#define RSCAN0RMID58L RSCAN0.RMID58.UINT16[L]
+#define RSCAN0RMID58LL RSCAN0.RMID58.UINT8[LL]
+#define RSCAN0RMID58LH RSCAN0.RMID58.UINT8[LH]
+#define RSCAN0RMID58H RSCAN0.RMID58.UINT16[H]
+#define RSCAN0RMID58HL RSCAN0.RMID58.UINT8[HL]
+#define RSCAN0RMID58HH RSCAN0.RMID58.UINT8[HH]
+#define RSCAN0RMPTR58 RSCAN0.RMPTR58.UINT32
+#define RSCAN0RMPTR58L RSCAN0.RMPTR58.UINT16[L]
+#define RSCAN0RMPTR58LL RSCAN0.RMPTR58.UINT8[LL]
+#define RSCAN0RMPTR58LH RSCAN0.RMPTR58.UINT8[LH]
+#define RSCAN0RMPTR58H RSCAN0.RMPTR58.UINT16[H]
+#define RSCAN0RMPTR58HL RSCAN0.RMPTR58.UINT8[HL]
+#define RSCAN0RMPTR58HH RSCAN0.RMPTR58.UINT8[HH]
+#define RSCAN0RMDF058 RSCAN0.RMDF058.UINT32
+#define RSCAN0RMDF058L RSCAN0.RMDF058.UINT16[L]
+#define RSCAN0RMDF058LL RSCAN0.RMDF058.UINT8[LL]
+#define RSCAN0RMDF058LH RSCAN0.RMDF058.UINT8[LH]
+#define RSCAN0RMDF058H RSCAN0.RMDF058.UINT16[H]
+#define RSCAN0RMDF058HL RSCAN0.RMDF058.UINT8[HL]
+#define RSCAN0RMDF058HH RSCAN0.RMDF058.UINT8[HH]
+#define RSCAN0RMDF158 RSCAN0.RMDF158.UINT32
+#define RSCAN0RMDF158L RSCAN0.RMDF158.UINT16[L]
+#define RSCAN0RMDF158LL RSCAN0.RMDF158.UINT8[LL]
+#define RSCAN0RMDF158LH RSCAN0.RMDF158.UINT8[LH]
+#define RSCAN0RMDF158H RSCAN0.RMDF158.UINT16[H]
+#define RSCAN0RMDF158HL RSCAN0.RMDF158.UINT8[HL]
+#define RSCAN0RMDF158HH RSCAN0.RMDF158.UINT8[HH]
+#define RSCAN0RMID59 RSCAN0.RMID59.UINT32
+#define RSCAN0RMID59L RSCAN0.RMID59.UINT16[L]
+#define RSCAN0RMID59LL RSCAN0.RMID59.UINT8[LL]
+#define RSCAN0RMID59LH RSCAN0.RMID59.UINT8[LH]
+#define RSCAN0RMID59H RSCAN0.RMID59.UINT16[H]
+#define RSCAN0RMID59HL RSCAN0.RMID59.UINT8[HL]
+#define RSCAN0RMID59HH RSCAN0.RMID59.UINT8[HH]
+#define RSCAN0RMPTR59 RSCAN0.RMPTR59.UINT32
+#define RSCAN0RMPTR59L RSCAN0.RMPTR59.UINT16[L]
+#define RSCAN0RMPTR59LL RSCAN0.RMPTR59.UINT8[LL]
+#define RSCAN0RMPTR59LH RSCAN0.RMPTR59.UINT8[LH]
+#define RSCAN0RMPTR59H RSCAN0.RMPTR59.UINT16[H]
+#define RSCAN0RMPTR59HL RSCAN0.RMPTR59.UINT8[HL]
+#define RSCAN0RMPTR59HH RSCAN0.RMPTR59.UINT8[HH]
+#define RSCAN0RMDF059 RSCAN0.RMDF059.UINT32
+#define RSCAN0RMDF059L RSCAN0.RMDF059.UINT16[L]
+#define RSCAN0RMDF059LL RSCAN0.RMDF059.UINT8[LL]
+#define RSCAN0RMDF059LH RSCAN0.RMDF059.UINT8[LH]
+#define RSCAN0RMDF059H RSCAN0.RMDF059.UINT16[H]
+#define RSCAN0RMDF059HL RSCAN0.RMDF059.UINT8[HL]
+#define RSCAN0RMDF059HH RSCAN0.RMDF059.UINT8[HH]
+#define RSCAN0RMDF159 RSCAN0.RMDF159.UINT32
+#define RSCAN0RMDF159L RSCAN0.RMDF159.UINT16[L]
+#define RSCAN0RMDF159LL RSCAN0.RMDF159.UINT8[LL]
+#define RSCAN0RMDF159LH RSCAN0.RMDF159.UINT8[LH]
+#define RSCAN0RMDF159H RSCAN0.RMDF159.UINT16[H]
+#define RSCAN0RMDF159HL RSCAN0.RMDF159.UINT8[HL]
+#define RSCAN0RMDF159HH RSCAN0.RMDF159.UINT8[HH]
+#define RSCAN0RMID60 RSCAN0.RMID60.UINT32
+#define RSCAN0RMID60L RSCAN0.RMID60.UINT16[L]
+#define RSCAN0RMID60LL RSCAN0.RMID60.UINT8[LL]
+#define RSCAN0RMID60LH RSCAN0.RMID60.UINT8[LH]
+#define RSCAN0RMID60H RSCAN0.RMID60.UINT16[H]
+#define RSCAN0RMID60HL RSCAN0.RMID60.UINT8[HL]
+#define RSCAN0RMID60HH RSCAN0.RMID60.UINT8[HH]
+#define RSCAN0RMPTR60 RSCAN0.RMPTR60.UINT32
+#define RSCAN0RMPTR60L RSCAN0.RMPTR60.UINT16[L]
+#define RSCAN0RMPTR60LL RSCAN0.RMPTR60.UINT8[LL]
+#define RSCAN0RMPTR60LH RSCAN0.RMPTR60.UINT8[LH]
+#define RSCAN0RMPTR60H RSCAN0.RMPTR60.UINT16[H]
+#define RSCAN0RMPTR60HL RSCAN0.RMPTR60.UINT8[HL]
+#define RSCAN0RMPTR60HH RSCAN0.RMPTR60.UINT8[HH]
+#define RSCAN0RMDF060 RSCAN0.RMDF060.UINT32
+#define RSCAN0RMDF060L RSCAN0.RMDF060.UINT16[L]
+#define RSCAN0RMDF060LL RSCAN0.RMDF060.UINT8[LL]
+#define RSCAN0RMDF060LH RSCAN0.RMDF060.UINT8[LH]
+#define RSCAN0RMDF060H RSCAN0.RMDF060.UINT16[H]
+#define RSCAN0RMDF060HL RSCAN0.RMDF060.UINT8[HL]
+#define RSCAN0RMDF060HH RSCAN0.RMDF060.UINT8[HH]
+#define RSCAN0RMDF160 RSCAN0.RMDF160.UINT32
+#define RSCAN0RMDF160L RSCAN0.RMDF160.UINT16[L]
+#define RSCAN0RMDF160LL RSCAN0.RMDF160.UINT8[LL]
+#define RSCAN0RMDF160LH RSCAN0.RMDF160.UINT8[LH]
+#define RSCAN0RMDF160H RSCAN0.RMDF160.UINT16[H]
+#define RSCAN0RMDF160HL RSCAN0.RMDF160.UINT8[HL]
+#define RSCAN0RMDF160HH RSCAN0.RMDF160.UINT8[HH]
+#define RSCAN0RMID61 RSCAN0.RMID61.UINT32
+#define RSCAN0RMID61L RSCAN0.RMID61.UINT16[L]
+#define RSCAN0RMID61LL RSCAN0.RMID61.UINT8[LL]
+#define RSCAN0RMID61LH RSCAN0.RMID61.UINT8[LH]
+#define RSCAN0RMID61H RSCAN0.RMID61.UINT16[H]
+#define RSCAN0RMID61HL RSCAN0.RMID61.UINT8[HL]
+#define RSCAN0RMID61HH RSCAN0.RMID61.UINT8[HH]
+#define RSCAN0RMPTR61 RSCAN0.RMPTR61.UINT32
+#define RSCAN0RMPTR61L RSCAN0.RMPTR61.UINT16[L]
+#define RSCAN0RMPTR61LL RSCAN0.RMPTR61.UINT8[LL]
+#define RSCAN0RMPTR61LH RSCAN0.RMPTR61.UINT8[LH]
+#define RSCAN0RMPTR61H RSCAN0.RMPTR61.UINT16[H]
+#define RSCAN0RMPTR61HL RSCAN0.RMPTR61.UINT8[HL]
+#define RSCAN0RMPTR61HH RSCAN0.RMPTR61.UINT8[HH]
+#define RSCAN0RMDF061 RSCAN0.RMDF061.UINT32
+#define RSCAN0RMDF061L RSCAN0.RMDF061.UINT16[L]
+#define RSCAN0RMDF061LL RSCAN0.RMDF061.UINT8[LL]
+#define RSCAN0RMDF061LH RSCAN0.RMDF061.UINT8[LH]
+#define RSCAN0RMDF061H RSCAN0.RMDF061.UINT16[H]
+#define RSCAN0RMDF061HL RSCAN0.RMDF061.UINT8[HL]
+#define RSCAN0RMDF061HH RSCAN0.RMDF061.UINT8[HH]
+#define RSCAN0RMDF161 RSCAN0.RMDF161.UINT32
+#define RSCAN0RMDF161L RSCAN0.RMDF161.UINT16[L]
+#define RSCAN0RMDF161LL RSCAN0.RMDF161.UINT8[LL]
+#define RSCAN0RMDF161LH RSCAN0.RMDF161.UINT8[LH]
+#define RSCAN0RMDF161H RSCAN0.RMDF161.UINT16[H]
+#define RSCAN0RMDF161HL RSCAN0.RMDF161.UINT8[HL]
+#define RSCAN0RMDF161HH RSCAN0.RMDF161.UINT8[HH]
+#define RSCAN0RMID62 RSCAN0.RMID62.UINT32
+#define RSCAN0RMID62L RSCAN0.RMID62.UINT16[L]
+#define RSCAN0RMID62LL RSCAN0.RMID62.UINT8[LL]
+#define RSCAN0RMID62LH RSCAN0.RMID62.UINT8[LH]
+#define RSCAN0RMID62H RSCAN0.RMID62.UINT16[H]
+#define RSCAN0RMID62HL RSCAN0.RMID62.UINT8[HL]
+#define RSCAN0RMID62HH RSCAN0.RMID62.UINT8[HH]
+#define RSCAN0RMPTR62 RSCAN0.RMPTR62.UINT32
+#define RSCAN0RMPTR62L RSCAN0.RMPTR62.UINT16[L]
+#define RSCAN0RMPTR62LL RSCAN0.RMPTR62.UINT8[LL]
+#define RSCAN0RMPTR62LH RSCAN0.RMPTR62.UINT8[LH]
+#define RSCAN0RMPTR62H RSCAN0.RMPTR62.UINT16[H]
+#define RSCAN0RMPTR62HL RSCAN0.RMPTR62.UINT8[HL]
+#define RSCAN0RMPTR62HH RSCAN0.RMPTR62.UINT8[HH]
+#define RSCAN0RMDF062 RSCAN0.RMDF062.UINT32
+#define RSCAN0RMDF062L RSCAN0.RMDF062.UINT16[L]
+#define RSCAN0RMDF062LL RSCAN0.RMDF062.UINT8[LL]
+#define RSCAN0RMDF062LH RSCAN0.RMDF062.UINT8[LH]
+#define RSCAN0RMDF062H RSCAN0.RMDF062.UINT16[H]
+#define RSCAN0RMDF062HL RSCAN0.RMDF062.UINT8[HL]
+#define RSCAN0RMDF062HH RSCAN0.RMDF062.UINT8[HH]
+#define RSCAN0RMDF162 RSCAN0.RMDF162.UINT32
+#define RSCAN0RMDF162L RSCAN0.RMDF162.UINT16[L]
+#define RSCAN0RMDF162LL RSCAN0.RMDF162.UINT8[LL]
+#define RSCAN0RMDF162LH RSCAN0.RMDF162.UINT8[LH]
+#define RSCAN0RMDF162H RSCAN0.RMDF162.UINT16[H]
+#define RSCAN0RMDF162HL RSCAN0.RMDF162.UINT8[HL]
+#define RSCAN0RMDF162HH RSCAN0.RMDF162.UINT8[HH]
+#define RSCAN0RMID63 RSCAN0.RMID63.UINT32
+#define RSCAN0RMID63L RSCAN0.RMID63.UINT16[L]
+#define RSCAN0RMID63LL RSCAN0.RMID63.UINT8[LL]
+#define RSCAN0RMID63LH RSCAN0.RMID63.UINT8[LH]
+#define RSCAN0RMID63H RSCAN0.RMID63.UINT16[H]
+#define RSCAN0RMID63HL RSCAN0.RMID63.UINT8[HL]
+#define RSCAN0RMID63HH RSCAN0.RMID63.UINT8[HH]
+#define RSCAN0RMPTR63 RSCAN0.RMPTR63.UINT32
+#define RSCAN0RMPTR63L RSCAN0.RMPTR63.UINT16[L]
+#define RSCAN0RMPTR63LL RSCAN0.RMPTR63.UINT8[LL]
+#define RSCAN0RMPTR63LH RSCAN0.RMPTR63.UINT8[LH]
+#define RSCAN0RMPTR63H RSCAN0.RMPTR63.UINT16[H]
+#define RSCAN0RMPTR63HL RSCAN0.RMPTR63.UINT8[HL]
+#define RSCAN0RMPTR63HH RSCAN0.RMPTR63.UINT8[HH]
+#define RSCAN0RMDF063 RSCAN0.RMDF063.UINT32
+#define RSCAN0RMDF063L RSCAN0.RMDF063.UINT16[L]
+#define RSCAN0RMDF063LL RSCAN0.RMDF063.UINT8[LL]
+#define RSCAN0RMDF063LH RSCAN0.RMDF063.UINT8[LH]
+#define RSCAN0RMDF063H RSCAN0.RMDF063.UINT16[H]
+#define RSCAN0RMDF063HL RSCAN0.RMDF063.UINT8[HL]
+#define RSCAN0RMDF063HH RSCAN0.RMDF063.UINT8[HH]
+#define RSCAN0RMDF163 RSCAN0.RMDF163.UINT32
+#define RSCAN0RMDF163L RSCAN0.RMDF163.UINT16[L]
+#define RSCAN0RMDF163LL RSCAN0.RMDF163.UINT8[LL]
+#define RSCAN0RMDF163LH RSCAN0.RMDF163.UINT8[LH]
+#define RSCAN0RMDF163H RSCAN0.RMDF163.UINT16[H]
+#define RSCAN0RMDF163HL RSCAN0.RMDF163.UINT8[HL]
+#define RSCAN0RMDF163HH RSCAN0.RMDF163.UINT8[HH]
+#define RSCAN0RMID64 RSCAN0.RMID64.UINT32
+#define RSCAN0RMID64L RSCAN0.RMID64.UINT16[L]
+#define RSCAN0RMID64LL RSCAN0.RMID64.UINT8[LL]
+#define RSCAN0RMID64LH RSCAN0.RMID64.UINT8[LH]
+#define RSCAN0RMID64H RSCAN0.RMID64.UINT16[H]
+#define RSCAN0RMID64HL RSCAN0.RMID64.UINT8[HL]
+#define RSCAN0RMID64HH RSCAN0.RMID64.UINT8[HH]
+#define RSCAN0RMPTR64 RSCAN0.RMPTR64.UINT32
+#define RSCAN0RMPTR64L RSCAN0.RMPTR64.UINT16[L]
+#define RSCAN0RMPTR64LL RSCAN0.RMPTR64.UINT8[LL]
+#define RSCAN0RMPTR64LH RSCAN0.RMPTR64.UINT8[LH]
+#define RSCAN0RMPTR64H RSCAN0.RMPTR64.UINT16[H]
+#define RSCAN0RMPTR64HL RSCAN0.RMPTR64.UINT8[HL]
+#define RSCAN0RMPTR64HH RSCAN0.RMPTR64.UINT8[HH]
+#define RSCAN0RMDF064 RSCAN0.RMDF064.UINT32
+#define RSCAN0RMDF064L RSCAN0.RMDF064.UINT16[L]
+#define RSCAN0RMDF064LL RSCAN0.RMDF064.UINT8[LL]
+#define RSCAN0RMDF064LH RSCAN0.RMDF064.UINT8[LH]
+#define RSCAN0RMDF064H RSCAN0.RMDF064.UINT16[H]
+#define RSCAN0RMDF064HL RSCAN0.RMDF064.UINT8[HL]
+#define RSCAN0RMDF064HH RSCAN0.RMDF064.UINT8[HH]
+#define RSCAN0RMDF164 RSCAN0.RMDF164.UINT32
+#define RSCAN0RMDF164L RSCAN0.RMDF164.UINT16[L]
+#define RSCAN0RMDF164LL RSCAN0.RMDF164.UINT8[LL]
+#define RSCAN0RMDF164LH RSCAN0.RMDF164.UINT8[LH]
+#define RSCAN0RMDF164H RSCAN0.RMDF164.UINT16[H]
+#define RSCAN0RMDF164HL RSCAN0.RMDF164.UINT8[HL]
+#define RSCAN0RMDF164HH RSCAN0.RMDF164.UINT8[HH]
+#define RSCAN0RMID65 RSCAN0.RMID65.UINT32
+#define RSCAN0RMID65L RSCAN0.RMID65.UINT16[L]
+#define RSCAN0RMID65LL RSCAN0.RMID65.UINT8[LL]
+#define RSCAN0RMID65LH RSCAN0.RMID65.UINT8[LH]
+#define RSCAN0RMID65H RSCAN0.RMID65.UINT16[H]
+#define RSCAN0RMID65HL RSCAN0.RMID65.UINT8[HL]
+#define RSCAN0RMID65HH RSCAN0.RMID65.UINT8[HH]
+#define RSCAN0RMPTR65 RSCAN0.RMPTR65.UINT32
+#define RSCAN0RMPTR65L RSCAN0.RMPTR65.UINT16[L]
+#define RSCAN0RMPTR65LL RSCAN0.RMPTR65.UINT8[LL]
+#define RSCAN0RMPTR65LH RSCAN0.RMPTR65.UINT8[LH]
+#define RSCAN0RMPTR65H RSCAN0.RMPTR65.UINT16[H]
+#define RSCAN0RMPTR65HL RSCAN0.RMPTR65.UINT8[HL]
+#define RSCAN0RMPTR65HH RSCAN0.RMPTR65.UINT8[HH]
+#define RSCAN0RMDF065 RSCAN0.RMDF065.UINT32
+#define RSCAN0RMDF065L RSCAN0.RMDF065.UINT16[L]
+#define RSCAN0RMDF065LL RSCAN0.RMDF065.UINT8[LL]
+#define RSCAN0RMDF065LH RSCAN0.RMDF065.UINT8[LH]
+#define RSCAN0RMDF065H RSCAN0.RMDF065.UINT16[H]
+#define RSCAN0RMDF065HL RSCAN0.RMDF065.UINT8[HL]
+#define RSCAN0RMDF065HH RSCAN0.RMDF065.UINT8[HH]
+#define RSCAN0RMDF165 RSCAN0.RMDF165.UINT32
+#define RSCAN0RMDF165L RSCAN0.RMDF165.UINT16[L]
+#define RSCAN0RMDF165LL RSCAN0.RMDF165.UINT8[LL]
+#define RSCAN0RMDF165LH RSCAN0.RMDF165.UINT8[LH]
+#define RSCAN0RMDF165H RSCAN0.RMDF165.UINT16[H]
+#define RSCAN0RMDF165HL RSCAN0.RMDF165.UINT8[HL]
+#define RSCAN0RMDF165HH RSCAN0.RMDF165.UINT8[HH]
+#define RSCAN0RMID66 RSCAN0.RMID66.UINT32
+#define RSCAN0RMID66L RSCAN0.RMID66.UINT16[L]
+#define RSCAN0RMID66LL RSCAN0.RMID66.UINT8[LL]
+#define RSCAN0RMID66LH RSCAN0.RMID66.UINT8[LH]
+#define RSCAN0RMID66H RSCAN0.RMID66.UINT16[H]
+#define RSCAN0RMID66HL RSCAN0.RMID66.UINT8[HL]
+#define RSCAN0RMID66HH RSCAN0.RMID66.UINT8[HH]
+#define RSCAN0RMPTR66 RSCAN0.RMPTR66.UINT32
+#define RSCAN0RMPTR66L RSCAN0.RMPTR66.UINT16[L]
+#define RSCAN0RMPTR66LL RSCAN0.RMPTR66.UINT8[LL]
+#define RSCAN0RMPTR66LH RSCAN0.RMPTR66.UINT8[LH]
+#define RSCAN0RMPTR66H RSCAN0.RMPTR66.UINT16[H]
+#define RSCAN0RMPTR66HL RSCAN0.RMPTR66.UINT8[HL]
+#define RSCAN0RMPTR66HH RSCAN0.RMPTR66.UINT8[HH]
+#define RSCAN0RMDF066 RSCAN0.RMDF066.UINT32
+#define RSCAN0RMDF066L RSCAN0.RMDF066.UINT16[L]
+#define RSCAN0RMDF066LL RSCAN0.RMDF066.UINT8[LL]
+#define RSCAN0RMDF066LH RSCAN0.RMDF066.UINT8[LH]
+#define RSCAN0RMDF066H RSCAN0.RMDF066.UINT16[H]
+#define RSCAN0RMDF066HL RSCAN0.RMDF066.UINT8[HL]
+#define RSCAN0RMDF066HH RSCAN0.RMDF066.UINT8[HH]
+#define RSCAN0RMDF166 RSCAN0.RMDF166.UINT32
+#define RSCAN0RMDF166L RSCAN0.RMDF166.UINT16[L]
+#define RSCAN0RMDF166LL RSCAN0.RMDF166.UINT8[LL]
+#define RSCAN0RMDF166LH RSCAN0.RMDF166.UINT8[LH]
+#define RSCAN0RMDF166H RSCAN0.RMDF166.UINT16[H]
+#define RSCAN0RMDF166HL RSCAN0.RMDF166.UINT8[HL]
+#define RSCAN0RMDF166HH RSCAN0.RMDF166.UINT8[HH]
+#define RSCAN0RMID67 RSCAN0.RMID67.UINT32
+#define RSCAN0RMID67L RSCAN0.RMID67.UINT16[L]
+#define RSCAN0RMID67LL RSCAN0.RMID67.UINT8[LL]
+#define RSCAN0RMID67LH RSCAN0.RMID67.UINT8[LH]
+#define RSCAN0RMID67H RSCAN0.RMID67.UINT16[H]
+#define RSCAN0RMID67HL RSCAN0.RMID67.UINT8[HL]
+#define RSCAN0RMID67HH RSCAN0.RMID67.UINT8[HH]
+#define RSCAN0RMPTR67 RSCAN0.RMPTR67.UINT32
+#define RSCAN0RMPTR67L RSCAN0.RMPTR67.UINT16[L]
+#define RSCAN0RMPTR67LL RSCAN0.RMPTR67.UINT8[LL]
+#define RSCAN0RMPTR67LH RSCAN0.RMPTR67.UINT8[LH]
+#define RSCAN0RMPTR67H RSCAN0.RMPTR67.UINT16[H]
+#define RSCAN0RMPTR67HL RSCAN0.RMPTR67.UINT8[HL]
+#define RSCAN0RMPTR67HH RSCAN0.RMPTR67.UINT8[HH]
+#define RSCAN0RMDF067 RSCAN0.RMDF067.UINT32
+#define RSCAN0RMDF067L RSCAN0.RMDF067.UINT16[L]
+#define RSCAN0RMDF067LL RSCAN0.RMDF067.UINT8[LL]
+#define RSCAN0RMDF067LH RSCAN0.RMDF067.UINT8[LH]
+#define RSCAN0RMDF067H RSCAN0.RMDF067.UINT16[H]
+#define RSCAN0RMDF067HL RSCAN0.RMDF067.UINT8[HL]
+#define RSCAN0RMDF067HH RSCAN0.RMDF067.UINT8[HH]
+#define RSCAN0RMDF167 RSCAN0.RMDF167.UINT32
+#define RSCAN0RMDF167L RSCAN0.RMDF167.UINT16[L]
+#define RSCAN0RMDF167LL RSCAN0.RMDF167.UINT8[LL]
+#define RSCAN0RMDF167LH RSCAN0.RMDF167.UINT8[LH]
+#define RSCAN0RMDF167H RSCAN0.RMDF167.UINT16[H]
+#define RSCAN0RMDF167HL RSCAN0.RMDF167.UINT8[HL]
+#define RSCAN0RMDF167HH RSCAN0.RMDF167.UINT8[HH]
+#define RSCAN0RMID68 RSCAN0.RMID68.UINT32
+#define RSCAN0RMID68L RSCAN0.RMID68.UINT16[L]
+#define RSCAN0RMID68LL RSCAN0.RMID68.UINT8[LL]
+#define RSCAN0RMID68LH RSCAN0.RMID68.UINT8[LH]
+#define RSCAN0RMID68H RSCAN0.RMID68.UINT16[H]
+#define RSCAN0RMID68HL RSCAN0.RMID68.UINT8[HL]
+#define RSCAN0RMID68HH RSCAN0.RMID68.UINT8[HH]
+#define RSCAN0RMPTR68 RSCAN0.RMPTR68.UINT32
+#define RSCAN0RMPTR68L RSCAN0.RMPTR68.UINT16[L]
+#define RSCAN0RMPTR68LL RSCAN0.RMPTR68.UINT8[LL]
+#define RSCAN0RMPTR68LH RSCAN0.RMPTR68.UINT8[LH]
+#define RSCAN0RMPTR68H RSCAN0.RMPTR68.UINT16[H]
+#define RSCAN0RMPTR68HL RSCAN0.RMPTR68.UINT8[HL]
+#define RSCAN0RMPTR68HH RSCAN0.RMPTR68.UINT8[HH]
+#define RSCAN0RMDF068 RSCAN0.RMDF068.UINT32
+#define RSCAN0RMDF068L RSCAN0.RMDF068.UINT16[L]
+#define RSCAN0RMDF068LL RSCAN0.RMDF068.UINT8[LL]
+#define RSCAN0RMDF068LH RSCAN0.RMDF068.UINT8[LH]
+#define RSCAN0RMDF068H RSCAN0.RMDF068.UINT16[H]
+#define RSCAN0RMDF068HL RSCAN0.RMDF068.UINT8[HL]
+#define RSCAN0RMDF068HH RSCAN0.RMDF068.UINT8[HH]
+#define RSCAN0RMDF168 RSCAN0.RMDF168.UINT32
+#define RSCAN0RMDF168L RSCAN0.RMDF168.UINT16[L]
+#define RSCAN0RMDF168LL RSCAN0.RMDF168.UINT8[LL]
+#define RSCAN0RMDF168LH RSCAN0.RMDF168.UINT8[LH]
+#define RSCAN0RMDF168H RSCAN0.RMDF168.UINT16[H]
+#define RSCAN0RMDF168HL RSCAN0.RMDF168.UINT8[HL]
+#define RSCAN0RMDF168HH RSCAN0.RMDF168.UINT8[HH]
+#define RSCAN0RMID69 RSCAN0.RMID69.UINT32
+#define RSCAN0RMID69L RSCAN0.RMID69.UINT16[L]
+#define RSCAN0RMID69LL RSCAN0.RMID69.UINT8[LL]
+#define RSCAN0RMID69LH RSCAN0.RMID69.UINT8[LH]
+#define RSCAN0RMID69H RSCAN0.RMID69.UINT16[H]
+#define RSCAN0RMID69HL RSCAN0.RMID69.UINT8[HL]
+#define RSCAN0RMID69HH RSCAN0.RMID69.UINT8[HH]
+#define RSCAN0RMPTR69 RSCAN0.RMPTR69.UINT32
+#define RSCAN0RMPTR69L RSCAN0.RMPTR69.UINT16[L]
+#define RSCAN0RMPTR69LL RSCAN0.RMPTR69.UINT8[LL]
+#define RSCAN0RMPTR69LH RSCAN0.RMPTR69.UINT8[LH]
+#define RSCAN0RMPTR69H RSCAN0.RMPTR69.UINT16[H]
+#define RSCAN0RMPTR69HL RSCAN0.RMPTR69.UINT8[HL]
+#define RSCAN0RMPTR69HH RSCAN0.RMPTR69.UINT8[HH]
+#define RSCAN0RMDF069 RSCAN0.RMDF069.UINT32
+#define RSCAN0RMDF069L RSCAN0.RMDF069.UINT16[L]
+#define RSCAN0RMDF069LL RSCAN0.RMDF069.UINT8[LL]
+#define RSCAN0RMDF069LH RSCAN0.RMDF069.UINT8[LH]
+#define RSCAN0RMDF069H RSCAN0.RMDF069.UINT16[H]
+#define RSCAN0RMDF069HL RSCAN0.RMDF069.UINT8[HL]
+#define RSCAN0RMDF069HH RSCAN0.RMDF069.UINT8[HH]
+#define RSCAN0RMDF169 RSCAN0.RMDF169.UINT32
+#define RSCAN0RMDF169L RSCAN0.RMDF169.UINT16[L]
+#define RSCAN0RMDF169LL RSCAN0.RMDF169.UINT8[LL]
+#define RSCAN0RMDF169LH RSCAN0.RMDF169.UINT8[LH]
+#define RSCAN0RMDF169H RSCAN0.RMDF169.UINT16[H]
+#define RSCAN0RMDF169HL RSCAN0.RMDF169.UINT8[HL]
+#define RSCAN0RMDF169HH RSCAN0.RMDF169.UINT8[HH]
+#define RSCAN0RMID70 RSCAN0.RMID70.UINT32
+#define RSCAN0RMID70L RSCAN0.RMID70.UINT16[L]
+#define RSCAN0RMID70LL RSCAN0.RMID70.UINT8[LL]
+#define RSCAN0RMID70LH RSCAN0.RMID70.UINT8[LH]
+#define RSCAN0RMID70H RSCAN0.RMID70.UINT16[H]
+#define RSCAN0RMID70HL RSCAN0.RMID70.UINT8[HL]
+#define RSCAN0RMID70HH RSCAN0.RMID70.UINT8[HH]
+#define RSCAN0RMPTR70 RSCAN0.RMPTR70.UINT32
+#define RSCAN0RMPTR70L RSCAN0.RMPTR70.UINT16[L]
+#define RSCAN0RMPTR70LL RSCAN0.RMPTR70.UINT8[LL]
+#define RSCAN0RMPTR70LH RSCAN0.RMPTR70.UINT8[LH]
+#define RSCAN0RMPTR70H RSCAN0.RMPTR70.UINT16[H]
+#define RSCAN0RMPTR70HL RSCAN0.RMPTR70.UINT8[HL]
+#define RSCAN0RMPTR70HH RSCAN0.RMPTR70.UINT8[HH]
+#define RSCAN0RMDF070 RSCAN0.RMDF070.UINT32
+#define RSCAN0RMDF070L RSCAN0.RMDF070.UINT16[L]
+#define RSCAN0RMDF070LL RSCAN0.RMDF070.UINT8[LL]
+#define RSCAN0RMDF070LH RSCAN0.RMDF070.UINT8[LH]
+#define RSCAN0RMDF070H RSCAN0.RMDF070.UINT16[H]
+#define RSCAN0RMDF070HL RSCAN0.RMDF070.UINT8[HL]
+#define RSCAN0RMDF070HH RSCAN0.RMDF070.UINT8[HH]
+#define RSCAN0RMDF170 RSCAN0.RMDF170.UINT32
+#define RSCAN0RMDF170L RSCAN0.RMDF170.UINT16[L]
+#define RSCAN0RMDF170LL RSCAN0.RMDF170.UINT8[LL]
+#define RSCAN0RMDF170LH RSCAN0.RMDF170.UINT8[LH]
+#define RSCAN0RMDF170H RSCAN0.RMDF170.UINT16[H]
+#define RSCAN0RMDF170HL RSCAN0.RMDF170.UINT8[HL]
+#define RSCAN0RMDF170HH RSCAN0.RMDF170.UINT8[HH]
+#define RSCAN0RMID71 RSCAN0.RMID71.UINT32
+#define RSCAN0RMID71L RSCAN0.RMID71.UINT16[L]
+#define RSCAN0RMID71LL RSCAN0.RMID71.UINT8[LL]
+#define RSCAN0RMID71LH RSCAN0.RMID71.UINT8[LH]
+#define RSCAN0RMID71H RSCAN0.RMID71.UINT16[H]
+#define RSCAN0RMID71HL RSCAN0.RMID71.UINT8[HL]
+#define RSCAN0RMID71HH RSCAN0.RMID71.UINT8[HH]
+#define RSCAN0RMPTR71 RSCAN0.RMPTR71.UINT32
+#define RSCAN0RMPTR71L RSCAN0.RMPTR71.UINT16[L]
+#define RSCAN0RMPTR71LL RSCAN0.RMPTR71.UINT8[LL]
+#define RSCAN0RMPTR71LH RSCAN0.RMPTR71.UINT8[LH]
+#define RSCAN0RMPTR71H RSCAN0.RMPTR71.UINT16[H]
+#define RSCAN0RMPTR71HL RSCAN0.RMPTR71.UINT8[HL]
+#define RSCAN0RMPTR71HH RSCAN0.RMPTR71.UINT8[HH]
+#define RSCAN0RMDF071 RSCAN0.RMDF071.UINT32
+#define RSCAN0RMDF071L RSCAN0.RMDF071.UINT16[L]
+#define RSCAN0RMDF071LL RSCAN0.RMDF071.UINT8[LL]
+#define RSCAN0RMDF071LH RSCAN0.RMDF071.UINT8[LH]
+#define RSCAN0RMDF071H RSCAN0.RMDF071.UINT16[H]
+#define RSCAN0RMDF071HL RSCAN0.RMDF071.UINT8[HL]
+#define RSCAN0RMDF071HH RSCAN0.RMDF071.UINT8[HH]
+#define RSCAN0RMDF171 RSCAN0.RMDF171.UINT32
+#define RSCAN0RMDF171L RSCAN0.RMDF171.UINT16[L]
+#define RSCAN0RMDF171LL RSCAN0.RMDF171.UINT8[LL]
+#define RSCAN0RMDF171LH RSCAN0.RMDF171.UINT8[LH]
+#define RSCAN0RMDF171H RSCAN0.RMDF171.UINT16[H]
+#define RSCAN0RMDF171HL RSCAN0.RMDF171.UINT8[HL]
+#define RSCAN0RMDF171HH RSCAN0.RMDF171.UINT8[HH]
+#define RSCAN0RMID72 RSCAN0.RMID72.UINT32
+#define RSCAN0RMID72L RSCAN0.RMID72.UINT16[L]
+#define RSCAN0RMID72LL RSCAN0.RMID72.UINT8[LL]
+#define RSCAN0RMID72LH RSCAN0.RMID72.UINT8[LH]
+#define RSCAN0RMID72H RSCAN0.RMID72.UINT16[H]
+#define RSCAN0RMID72HL RSCAN0.RMID72.UINT8[HL]
+#define RSCAN0RMID72HH RSCAN0.RMID72.UINT8[HH]
+#define RSCAN0RMPTR72 RSCAN0.RMPTR72.UINT32
+#define RSCAN0RMPTR72L RSCAN0.RMPTR72.UINT16[L]
+#define RSCAN0RMPTR72LL RSCAN0.RMPTR72.UINT8[LL]
+#define RSCAN0RMPTR72LH RSCAN0.RMPTR72.UINT8[LH]
+#define RSCAN0RMPTR72H RSCAN0.RMPTR72.UINT16[H]
+#define RSCAN0RMPTR72HL RSCAN0.RMPTR72.UINT8[HL]
+#define RSCAN0RMPTR72HH RSCAN0.RMPTR72.UINT8[HH]
+#define RSCAN0RMDF072 RSCAN0.RMDF072.UINT32
+#define RSCAN0RMDF072L RSCAN0.RMDF072.UINT16[L]
+#define RSCAN0RMDF072LL RSCAN0.RMDF072.UINT8[LL]
+#define RSCAN0RMDF072LH RSCAN0.RMDF072.UINT8[LH]
+#define RSCAN0RMDF072H RSCAN0.RMDF072.UINT16[H]
+#define RSCAN0RMDF072HL RSCAN0.RMDF072.UINT8[HL]
+#define RSCAN0RMDF072HH RSCAN0.RMDF072.UINT8[HH]
+#define RSCAN0RMDF172 RSCAN0.RMDF172.UINT32
+#define RSCAN0RMDF172L RSCAN0.RMDF172.UINT16[L]
+#define RSCAN0RMDF172LL RSCAN0.RMDF172.UINT8[LL]
+#define RSCAN0RMDF172LH RSCAN0.RMDF172.UINT8[LH]
+#define RSCAN0RMDF172H RSCAN0.RMDF172.UINT16[H]
+#define RSCAN0RMDF172HL RSCAN0.RMDF172.UINT8[HL]
+#define RSCAN0RMDF172HH RSCAN0.RMDF172.UINT8[HH]
+#define RSCAN0RMID73 RSCAN0.RMID73.UINT32
+#define RSCAN0RMID73L RSCAN0.RMID73.UINT16[L]
+#define RSCAN0RMID73LL RSCAN0.RMID73.UINT8[LL]
+#define RSCAN0RMID73LH RSCAN0.RMID73.UINT8[LH]
+#define RSCAN0RMID73H RSCAN0.RMID73.UINT16[H]
+#define RSCAN0RMID73HL RSCAN0.RMID73.UINT8[HL]
+#define RSCAN0RMID73HH RSCAN0.RMID73.UINT8[HH]
+#define RSCAN0RMPTR73 RSCAN0.RMPTR73.UINT32
+#define RSCAN0RMPTR73L RSCAN0.RMPTR73.UINT16[L]
+#define RSCAN0RMPTR73LL RSCAN0.RMPTR73.UINT8[LL]
+#define RSCAN0RMPTR73LH RSCAN0.RMPTR73.UINT8[LH]
+#define RSCAN0RMPTR73H RSCAN0.RMPTR73.UINT16[H]
+#define RSCAN0RMPTR73HL RSCAN0.RMPTR73.UINT8[HL]
+#define RSCAN0RMPTR73HH RSCAN0.RMPTR73.UINT8[HH]
+#define RSCAN0RMDF073 RSCAN0.RMDF073.UINT32
+#define RSCAN0RMDF073L RSCAN0.RMDF073.UINT16[L]
+#define RSCAN0RMDF073LL RSCAN0.RMDF073.UINT8[LL]
+#define RSCAN0RMDF073LH RSCAN0.RMDF073.UINT8[LH]
+#define RSCAN0RMDF073H RSCAN0.RMDF073.UINT16[H]
+#define RSCAN0RMDF073HL RSCAN0.RMDF073.UINT8[HL]
+#define RSCAN0RMDF073HH RSCAN0.RMDF073.UINT8[HH]
+#define RSCAN0RMDF173 RSCAN0.RMDF173.UINT32
+#define RSCAN0RMDF173L RSCAN0.RMDF173.UINT16[L]
+#define RSCAN0RMDF173LL RSCAN0.RMDF173.UINT8[LL]
+#define RSCAN0RMDF173LH RSCAN0.RMDF173.UINT8[LH]
+#define RSCAN0RMDF173H RSCAN0.RMDF173.UINT16[H]
+#define RSCAN0RMDF173HL RSCAN0.RMDF173.UINT8[HL]
+#define RSCAN0RMDF173HH RSCAN0.RMDF173.UINT8[HH]
+#define RSCAN0RMID74 RSCAN0.RMID74.UINT32
+#define RSCAN0RMID74L RSCAN0.RMID74.UINT16[L]
+#define RSCAN0RMID74LL RSCAN0.RMID74.UINT8[LL]
+#define RSCAN0RMID74LH RSCAN0.RMID74.UINT8[LH]
+#define RSCAN0RMID74H RSCAN0.RMID74.UINT16[H]
+#define RSCAN0RMID74HL RSCAN0.RMID74.UINT8[HL]
+#define RSCAN0RMID74HH RSCAN0.RMID74.UINT8[HH]
+#define RSCAN0RMPTR74 RSCAN0.RMPTR74.UINT32
+#define RSCAN0RMPTR74L RSCAN0.RMPTR74.UINT16[L]
+#define RSCAN0RMPTR74LL RSCAN0.RMPTR74.UINT8[LL]
+#define RSCAN0RMPTR74LH RSCAN0.RMPTR74.UINT8[LH]
+#define RSCAN0RMPTR74H RSCAN0.RMPTR74.UINT16[H]
+#define RSCAN0RMPTR74HL RSCAN0.RMPTR74.UINT8[HL]
+#define RSCAN0RMPTR74HH RSCAN0.RMPTR74.UINT8[HH]
+#define RSCAN0RMDF074 RSCAN0.RMDF074.UINT32
+#define RSCAN0RMDF074L RSCAN0.RMDF074.UINT16[L]
+#define RSCAN0RMDF074LL RSCAN0.RMDF074.UINT8[LL]
+#define RSCAN0RMDF074LH RSCAN0.RMDF074.UINT8[LH]
+#define RSCAN0RMDF074H RSCAN0.RMDF074.UINT16[H]
+#define RSCAN0RMDF074HL RSCAN0.RMDF074.UINT8[HL]
+#define RSCAN0RMDF074HH RSCAN0.RMDF074.UINT8[HH]
+#define RSCAN0RMDF174 RSCAN0.RMDF174.UINT32
+#define RSCAN0RMDF174L RSCAN0.RMDF174.UINT16[L]
+#define RSCAN0RMDF174LL RSCAN0.RMDF174.UINT8[LL]
+#define RSCAN0RMDF174LH RSCAN0.RMDF174.UINT8[LH]
+#define RSCAN0RMDF174H RSCAN0.RMDF174.UINT16[H]
+#define RSCAN0RMDF174HL RSCAN0.RMDF174.UINT8[HL]
+#define RSCAN0RMDF174HH RSCAN0.RMDF174.UINT8[HH]
+#define RSCAN0RMID75 RSCAN0.RMID75.UINT32
+#define RSCAN0RMID75L RSCAN0.RMID75.UINT16[L]
+#define RSCAN0RMID75LL RSCAN0.RMID75.UINT8[LL]
+#define RSCAN0RMID75LH RSCAN0.RMID75.UINT8[LH]
+#define RSCAN0RMID75H RSCAN0.RMID75.UINT16[H]
+#define RSCAN0RMID75HL RSCAN0.RMID75.UINT8[HL]
+#define RSCAN0RMID75HH RSCAN0.RMID75.UINT8[HH]
+#define RSCAN0RMPTR75 RSCAN0.RMPTR75.UINT32
+#define RSCAN0RMPTR75L RSCAN0.RMPTR75.UINT16[L]
+#define RSCAN0RMPTR75LL RSCAN0.RMPTR75.UINT8[LL]
+#define RSCAN0RMPTR75LH RSCAN0.RMPTR75.UINT8[LH]
+#define RSCAN0RMPTR75H RSCAN0.RMPTR75.UINT16[H]
+#define RSCAN0RMPTR75HL RSCAN0.RMPTR75.UINT8[HL]
+#define RSCAN0RMPTR75HH RSCAN0.RMPTR75.UINT8[HH]
+#define RSCAN0RMDF075 RSCAN0.RMDF075.UINT32
+#define RSCAN0RMDF075L RSCAN0.RMDF075.UINT16[L]
+#define RSCAN0RMDF075LL RSCAN0.RMDF075.UINT8[LL]
+#define RSCAN0RMDF075LH RSCAN0.RMDF075.UINT8[LH]
+#define RSCAN0RMDF075H RSCAN0.RMDF075.UINT16[H]
+#define RSCAN0RMDF075HL RSCAN0.RMDF075.UINT8[HL]
+#define RSCAN0RMDF075HH RSCAN0.RMDF075.UINT8[HH]
+#define RSCAN0RMDF175 RSCAN0.RMDF175.UINT32
+#define RSCAN0RMDF175L RSCAN0.RMDF175.UINT16[L]
+#define RSCAN0RMDF175LL RSCAN0.RMDF175.UINT8[LL]
+#define RSCAN0RMDF175LH RSCAN0.RMDF175.UINT8[LH]
+#define RSCAN0RMDF175H RSCAN0.RMDF175.UINT16[H]
+#define RSCAN0RMDF175HL RSCAN0.RMDF175.UINT8[HL]
+#define RSCAN0RMDF175HH RSCAN0.RMDF175.UINT8[HH]
+#define RSCAN0RMID76 RSCAN0.RMID76.UINT32
+#define RSCAN0RMID76L RSCAN0.RMID76.UINT16[L]
+#define RSCAN0RMID76LL RSCAN0.RMID76.UINT8[LL]
+#define RSCAN0RMID76LH RSCAN0.RMID76.UINT8[LH]
+#define RSCAN0RMID76H RSCAN0.RMID76.UINT16[H]
+#define RSCAN0RMID76HL RSCAN0.RMID76.UINT8[HL]
+#define RSCAN0RMID76HH RSCAN0.RMID76.UINT8[HH]
+#define RSCAN0RMPTR76 RSCAN0.RMPTR76.UINT32
+#define RSCAN0RMPTR76L RSCAN0.RMPTR76.UINT16[L]
+#define RSCAN0RMPTR76LL RSCAN0.RMPTR76.UINT8[LL]
+#define RSCAN0RMPTR76LH RSCAN0.RMPTR76.UINT8[LH]
+#define RSCAN0RMPTR76H RSCAN0.RMPTR76.UINT16[H]
+#define RSCAN0RMPTR76HL RSCAN0.RMPTR76.UINT8[HL]
+#define RSCAN0RMPTR76HH RSCAN0.RMPTR76.UINT8[HH]
+#define RSCAN0RMDF076 RSCAN0.RMDF076.UINT32
+#define RSCAN0RMDF076L RSCAN0.RMDF076.UINT16[L]
+#define RSCAN0RMDF076LL RSCAN0.RMDF076.UINT8[LL]
+#define RSCAN0RMDF076LH RSCAN0.RMDF076.UINT8[LH]
+#define RSCAN0RMDF076H RSCAN0.RMDF076.UINT16[H]
+#define RSCAN0RMDF076HL RSCAN0.RMDF076.UINT8[HL]
+#define RSCAN0RMDF076HH RSCAN0.RMDF076.UINT8[HH]
+#define RSCAN0RMDF176 RSCAN0.RMDF176.UINT32
+#define RSCAN0RMDF176L RSCAN0.RMDF176.UINT16[L]
+#define RSCAN0RMDF176LL RSCAN0.RMDF176.UINT8[LL]
+#define RSCAN0RMDF176LH RSCAN0.RMDF176.UINT8[LH]
+#define RSCAN0RMDF176H RSCAN0.RMDF176.UINT16[H]
+#define RSCAN0RMDF176HL RSCAN0.RMDF176.UINT8[HL]
+#define RSCAN0RMDF176HH RSCAN0.RMDF176.UINT8[HH]
+#define RSCAN0RMID77 RSCAN0.RMID77.UINT32
+#define RSCAN0RMID77L RSCAN0.RMID77.UINT16[L]
+#define RSCAN0RMID77LL RSCAN0.RMID77.UINT8[LL]
+#define RSCAN0RMID77LH RSCAN0.RMID77.UINT8[LH]
+#define RSCAN0RMID77H RSCAN0.RMID77.UINT16[H]
+#define RSCAN0RMID77HL RSCAN0.RMID77.UINT8[HL]
+#define RSCAN0RMID77HH RSCAN0.RMID77.UINT8[HH]
+#define RSCAN0RMPTR77 RSCAN0.RMPTR77.UINT32
+#define RSCAN0RMPTR77L RSCAN0.RMPTR77.UINT16[L]
+#define RSCAN0RMPTR77LL RSCAN0.RMPTR77.UINT8[LL]
+#define RSCAN0RMPTR77LH RSCAN0.RMPTR77.UINT8[LH]
+#define RSCAN0RMPTR77H RSCAN0.RMPTR77.UINT16[H]
+#define RSCAN0RMPTR77HL RSCAN0.RMPTR77.UINT8[HL]
+#define RSCAN0RMPTR77HH RSCAN0.RMPTR77.UINT8[HH]
+#define RSCAN0RMDF077 RSCAN0.RMDF077.UINT32
+#define RSCAN0RMDF077L RSCAN0.RMDF077.UINT16[L]
+#define RSCAN0RMDF077LL RSCAN0.RMDF077.UINT8[LL]
+#define RSCAN0RMDF077LH RSCAN0.RMDF077.UINT8[LH]
+#define RSCAN0RMDF077H RSCAN0.RMDF077.UINT16[H]
+#define RSCAN0RMDF077HL RSCAN0.RMDF077.UINT8[HL]
+#define RSCAN0RMDF077HH RSCAN0.RMDF077.UINT8[HH]
+#define RSCAN0RMDF177 RSCAN0.RMDF177.UINT32
+#define RSCAN0RMDF177L RSCAN0.RMDF177.UINT16[L]
+#define RSCAN0RMDF177LL RSCAN0.RMDF177.UINT8[LL]
+#define RSCAN0RMDF177LH RSCAN0.RMDF177.UINT8[LH]
+#define RSCAN0RMDF177H RSCAN0.RMDF177.UINT16[H]
+#define RSCAN0RMDF177HL RSCAN0.RMDF177.UINT8[HL]
+#define RSCAN0RMDF177HH RSCAN0.RMDF177.UINT8[HH]
+#define RSCAN0RMID78 RSCAN0.RMID78.UINT32
+#define RSCAN0RMID78L RSCAN0.RMID78.UINT16[L]
+#define RSCAN0RMID78LL RSCAN0.RMID78.UINT8[LL]
+#define RSCAN0RMID78LH RSCAN0.RMID78.UINT8[LH]
+#define RSCAN0RMID78H RSCAN0.RMID78.UINT16[H]
+#define RSCAN0RMID78HL RSCAN0.RMID78.UINT8[HL]
+#define RSCAN0RMID78HH RSCAN0.RMID78.UINT8[HH]
+#define RSCAN0RMPTR78 RSCAN0.RMPTR78.UINT32
+#define RSCAN0RMPTR78L RSCAN0.RMPTR78.UINT16[L]
+#define RSCAN0RMPTR78LL RSCAN0.RMPTR78.UINT8[LL]
+#define RSCAN0RMPTR78LH RSCAN0.RMPTR78.UINT8[LH]
+#define RSCAN0RMPTR78H RSCAN0.RMPTR78.UINT16[H]
+#define RSCAN0RMPTR78HL RSCAN0.RMPTR78.UINT8[HL]
+#define RSCAN0RMPTR78HH RSCAN0.RMPTR78.UINT8[HH]
+#define RSCAN0RMDF078 RSCAN0.RMDF078.UINT32
+#define RSCAN0RMDF078L RSCAN0.RMDF078.UINT16[L]
+#define RSCAN0RMDF078LL RSCAN0.RMDF078.UINT8[LL]
+#define RSCAN0RMDF078LH RSCAN0.RMDF078.UINT8[LH]
+#define RSCAN0RMDF078H RSCAN0.RMDF078.UINT16[H]
+#define RSCAN0RMDF078HL RSCAN0.RMDF078.UINT8[HL]
+#define RSCAN0RMDF078HH RSCAN0.RMDF078.UINT8[HH]
+#define RSCAN0RMDF178 RSCAN0.RMDF178.UINT32
+#define RSCAN0RMDF178L RSCAN0.RMDF178.UINT16[L]
+#define RSCAN0RMDF178LL RSCAN0.RMDF178.UINT8[LL]
+#define RSCAN0RMDF178LH RSCAN0.RMDF178.UINT8[LH]
+#define RSCAN0RMDF178H RSCAN0.RMDF178.UINT16[H]
+#define RSCAN0RMDF178HL RSCAN0.RMDF178.UINT8[HL]
+#define RSCAN0RMDF178HH RSCAN0.RMDF178.UINT8[HH]
+#define RSCAN0RMID79 RSCAN0.RMID79.UINT32
+#define RSCAN0RMID79L RSCAN0.RMID79.UINT16[L]
+#define RSCAN0RMID79LL RSCAN0.RMID79.UINT8[LL]
+#define RSCAN0RMID79LH RSCAN0.RMID79.UINT8[LH]
+#define RSCAN0RMID79H RSCAN0.RMID79.UINT16[H]
+#define RSCAN0RMID79HL RSCAN0.RMID79.UINT8[HL]
+#define RSCAN0RMID79HH RSCAN0.RMID79.UINT8[HH]
+#define RSCAN0RMPTR79 RSCAN0.RMPTR79.UINT32
+#define RSCAN0RMPTR79L RSCAN0.RMPTR79.UINT16[L]
+#define RSCAN0RMPTR79LL RSCAN0.RMPTR79.UINT8[LL]
+#define RSCAN0RMPTR79LH RSCAN0.RMPTR79.UINT8[LH]
+#define RSCAN0RMPTR79H RSCAN0.RMPTR79.UINT16[H]
+#define RSCAN0RMPTR79HL RSCAN0.RMPTR79.UINT8[HL]
+#define RSCAN0RMPTR79HH RSCAN0.RMPTR79.UINT8[HH]
+#define RSCAN0RMDF079 RSCAN0.RMDF079.UINT32
+#define RSCAN0RMDF079L RSCAN0.RMDF079.UINT16[L]
+#define RSCAN0RMDF079LL RSCAN0.RMDF079.UINT8[LL]
+#define RSCAN0RMDF079LH RSCAN0.RMDF079.UINT8[LH]
+#define RSCAN0RMDF079H RSCAN0.RMDF079.UINT16[H]
+#define RSCAN0RMDF079HL RSCAN0.RMDF079.UINT8[HL]
+#define RSCAN0RMDF079HH RSCAN0.RMDF079.UINT8[HH]
+#define RSCAN0RMDF179 RSCAN0.RMDF179.UINT32
+#define RSCAN0RMDF179L RSCAN0.RMDF179.UINT16[L]
+#define RSCAN0RMDF179LL RSCAN0.RMDF179.UINT8[LL]
+#define RSCAN0RMDF179LH RSCAN0.RMDF179.UINT8[LH]
+#define RSCAN0RMDF179H RSCAN0.RMDF179.UINT16[H]
+#define RSCAN0RMDF179HL RSCAN0.RMDF179.UINT8[HL]
+#define RSCAN0RMDF179HH RSCAN0.RMDF179.UINT8[HH]
+#define RSCAN0RFID0 RSCAN0.RFID0.UINT32
+#define RSCAN0RFID0L RSCAN0.RFID0.UINT16[L]
+#define RSCAN0RFID0LL RSCAN0.RFID0.UINT8[LL]
+#define RSCAN0RFID0LH RSCAN0.RFID0.UINT8[LH]
+#define RSCAN0RFID0H RSCAN0.RFID0.UINT16[H]
+#define RSCAN0RFID0HL RSCAN0.RFID0.UINT8[HL]
+#define RSCAN0RFID0HH RSCAN0.RFID0.UINT8[HH]
+#define RSCAN0RFPTR0 RSCAN0.RFPTR0.UINT32
+#define RSCAN0RFPTR0L RSCAN0.RFPTR0.UINT16[L]
+#define RSCAN0RFPTR0LL RSCAN0.RFPTR0.UINT8[LL]
+#define RSCAN0RFPTR0LH RSCAN0.RFPTR0.UINT8[LH]
+#define RSCAN0RFPTR0H RSCAN0.RFPTR0.UINT16[H]
+#define RSCAN0RFPTR0HL RSCAN0.RFPTR0.UINT8[HL]
+#define RSCAN0RFPTR0HH RSCAN0.RFPTR0.UINT8[HH]
+#define RSCAN0RFDF00 RSCAN0.RFDF00.UINT32
+#define RSCAN0RFDF00L RSCAN0.RFDF00.UINT16[L]
+#define RSCAN0RFDF00LL RSCAN0.RFDF00.UINT8[LL]
+#define RSCAN0RFDF00LH RSCAN0.RFDF00.UINT8[LH]
+#define RSCAN0RFDF00H RSCAN0.RFDF00.UINT16[H]
+#define RSCAN0RFDF00HL RSCAN0.RFDF00.UINT8[HL]
+#define RSCAN0RFDF00HH RSCAN0.RFDF00.UINT8[HH]
+#define RSCAN0RFDF10 RSCAN0.RFDF10.UINT32
+#define RSCAN0RFDF10L RSCAN0.RFDF10.UINT16[L]
+#define RSCAN0RFDF10LL RSCAN0.RFDF10.UINT8[LL]
+#define RSCAN0RFDF10LH RSCAN0.RFDF10.UINT8[LH]
+#define RSCAN0RFDF10H RSCAN0.RFDF10.UINT16[H]
+#define RSCAN0RFDF10HL RSCAN0.RFDF10.UINT8[HL]
+#define RSCAN0RFDF10HH RSCAN0.RFDF10.UINT8[HH]
+#define RSCAN0RFID1 RSCAN0.RFID1.UINT32
+#define RSCAN0RFID1L RSCAN0.RFID1.UINT16[L]
+#define RSCAN0RFID1LL RSCAN0.RFID1.UINT8[LL]
+#define RSCAN0RFID1LH RSCAN0.RFID1.UINT8[LH]
+#define RSCAN0RFID1H RSCAN0.RFID1.UINT16[H]
+#define RSCAN0RFID1HL RSCAN0.RFID1.UINT8[HL]
+#define RSCAN0RFID1HH RSCAN0.RFID1.UINT8[HH]
+#define RSCAN0RFPTR1 RSCAN0.RFPTR1.UINT32
+#define RSCAN0RFPTR1L RSCAN0.RFPTR1.UINT16[L]
+#define RSCAN0RFPTR1LL RSCAN0.RFPTR1.UINT8[LL]
+#define RSCAN0RFPTR1LH RSCAN0.RFPTR1.UINT8[LH]
+#define RSCAN0RFPTR1H RSCAN0.RFPTR1.UINT16[H]
+#define RSCAN0RFPTR1HL RSCAN0.RFPTR1.UINT8[HL]
+#define RSCAN0RFPTR1HH RSCAN0.RFPTR1.UINT8[HH]
+#define RSCAN0RFDF01 RSCAN0.RFDF01.UINT32
+#define RSCAN0RFDF01L RSCAN0.RFDF01.UINT16[L]
+#define RSCAN0RFDF01LL RSCAN0.RFDF01.UINT8[LL]
+#define RSCAN0RFDF01LH RSCAN0.RFDF01.UINT8[LH]
+#define RSCAN0RFDF01H RSCAN0.RFDF01.UINT16[H]
+#define RSCAN0RFDF01HL RSCAN0.RFDF01.UINT8[HL]
+#define RSCAN0RFDF01HH RSCAN0.RFDF01.UINT8[HH]
+#define RSCAN0RFDF11 RSCAN0.RFDF11.UINT32
+#define RSCAN0RFDF11L RSCAN0.RFDF11.UINT16[L]
+#define RSCAN0RFDF11LL RSCAN0.RFDF11.UINT8[LL]
+#define RSCAN0RFDF11LH RSCAN0.RFDF11.UINT8[LH]
+#define RSCAN0RFDF11H RSCAN0.RFDF11.UINT16[H]
+#define RSCAN0RFDF11HL RSCAN0.RFDF11.UINT8[HL]
+#define RSCAN0RFDF11HH RSCAN0.RFDF11.UINT8[HH]
+#define RSCAN0RFID2 RSCAN0.RFID2.UINT32
+#define RSCAN0RFID2L RSCAN0.RFID2.UINT16[L]
+#define RSCAN0RFID2LL RSCAN0.RFID2.UINT8[LL]
+#define RSCAN0RFID2LH RSCAN0.RFID2.UINT8[LH]
+#define RSCAN0RFID2H RSCAN0.RFID2.UINT16[H]
+#define RSCAN0RFID2HL RSCAN0.RFID2.UINT8[HL]
+#define RSCAN0RFID2HH RSCAN0.RFID2.UINT8[HH]
+#define RSCAN0RFPTR2 RSCAN0.RFPTR2.UINT32
+#define RSCAN0RFPTR2L RSCAN0.RFPTR2.UINT16[L]
+#define RSCAN0RFPTR2LL RSCAN0.RFPTR2.UINT8[LL]
+#define RSCAN0RFPTR2LH RSCAN0.RFPTR2.UINT8[LH]
+#define RSCAN0RFPTR2H RSCAN0.RFPTR2.UINT16[H]
+#define RSCAN0RFPTR2HL RSCAN0.RFPTR2.UINT8[HL]
+#define RSCAN0RFPTR2HH RSCAN0.RFPTR2.UINT8[HH]
+#define RSCAN0RFDF02 RSCAN0.RFDF02.UINT32
+#define RSCAN0RFDF02L RSCAN0.RFDF02.UINT16[L]
+#define RSCAN0RFDF02LL RSCAN0.RFDF02.UINT8[LL]
+#define RSCAN0RFDF02LH RSCAN0.RFDF02.UINT8[LH]
+#define RSCAN0RFDF02H RSCAN0.RFDF02.UINT16[H]
+#define RSCAN0RFDF02HL RSCAN0.RFDF02.UINT8[HL]
+#define RSCAN0RFDF02HH RSCAN0.RFDF02.UINT8[HH]
+#define RSCAN0RFDF12 RSCAN0.RFDF12.UINT32
+#define RSCAN0RFDF12L RSCAN0.RFDF12.UINT16[L]
+#define RSCAN0RFDF12LL RSCAN0.RFDF12.UINT8[LL]
+#define RSCAN0RFDF12LH RSCAN0.RFDF12.UINT8[LH]
+#define RSCAN0RFDF12H RSCAN0.RFDF12.UINT16[H]
+#define RSCAN0RFDF12HL RSCAN0.RFDF12.UINT8[HL]
+#define RSCAN0RFDF12HH RSCAN0.RFDF12.UINT8[HH]
+#define RSCAN0RFID3 RSCAN0.RFID3.UINT32
+#define RSCAN0RFID3L RSCAN0.RFID3.UINT16[L]
+#define RSCAN0RFID3LL RSCAN0.RFID3.UINT8[LL]
+#define RSCAN0RFID3LH RSCAN0.RFID3.UINT8[LH]
+#define RSCAN0RFID3H RSCAN0.RFID3.UINT16[H]
+#define RSCAN0RFID3HL RSCAN0.RFID3.UINT8[HL]
+#define RSCAN0RFID3HH RSCAN0.RFID3.UINT8[HH]
+#define RSCAN0RFPTR3 RSCAN0.RFPTR3.UINT32
+#define RSCAN0RFPTR3L RSCAN0.RFPTR3.UINT16[L]
+#define RSCAN0RFPTR3LL RSCAN0.RFPTR3.UINT8[LL]
+#define RSCAN0RFPTR3LH RSCAN0.RFPTR3.UINT8[LH]
+#define RSCAN0RFPTR3H RSCAN0.RFPTR3.UINT16[H]
+#define RSCAN0RFPTR3HL RSCAN0.RFPTR3.UINT8[HL]
+#define RSCAN0RFPTR3HH RSCAN0.RFPTR3.UINT8[HH]
+#define RSCAN0RFDF03 RSCAN0.RFDF03.UINT32
+#define RSCAN0RFDF03L RSCAN0.RFDF03.UINT16[L]
+#define RSCAN0RFDF03LL RSCAN0.RFDF03.UINT8[LL]
+#define RSCAN0RFDF03LH RSCAN0.RFDF03.UINT8[LH]
+#define RSCAN0RFDF03H RSCAN0.RFDF03.UINT16[H]
+#define RSCAN0RFDF03HL RSCAN0.RFDF03.UINT8[HL]
+#define RSCAN0RFDF03HH RSCAN0.RFDF03.UINT8[HH]
+#define RSCAN0RFDF13 RSCAN0.RFDF13.UINT32
+#define RSCAN0RFDF13L RSCAN0.RFDF13.UINT16[L]
+#define RSCAN0RFDF13LL RSCAN0.RFDF13.UINT8[LL]
+#define RSCAN0RFDF13LH RSCAN0.RFDF13.UINT8[LH]
+#define RSCAN0RFDF13H RSCAN0.RFDF13.UINT16[H]
+#define RSCAN0RFDF13HL RSCAN0.RFDF13.UINT8[HL]
+#define RSCAN0RFDF13HH RSCAN0.RFDF13.UINT8[HH]
+#define RSCAN0RFID4 RSCAN0.RFID4.UINT32
+#define RSCAN0RFID4L RSCAN0.RFID4.UINT16[L]
+#define RSCAN0RFID4LL RSCAN0.RFID4.UINT8[LL]
+#define RSCAN0RFID4LH RSCAN0.RFID4.UINT8[LH]
+#define RSCAN0RFID4H RSCAN0.RFID4.UINT16[H]
+#define RSCAN0RFID4HL RSCAN0.RFID4.UINT8[HL]
+#define RSCAN0RFID4HH RSCAN0.RFID4.UINT8[HH]
+#define RSCAN0RFPTR4 RSCAN0.RFPTR4.UINT32
+#define RSCAN0RFPTR4L RSCAN0.RFPTR4.UINT16[L]
+#define RSCAN0RFPTR4LL RSCAN0.RFPTR4.UINT8[LL]
+#define RSCAN0RFPTR4LH RSCAN0.RFPTR4.UINT8[LH]
+#define RSCAN0RFPTR4H RSCAN0.RFPTR4.UINT16[H]
+#define RSCAN0RFPTR4HL RSCAN0.RFPTR4.UINT8[HL]
+#define RSCAN0RFPTR4HH RSCAN0.RFPTR4.UINT8[HH]
+#define RSCAN0RFDF04 RSCAN0.RFDF04.UINT32
+#define RSCAN0RFDF04L RSCAN0.RFDF04.UINT16[L]
+#define RSCAN0RFDF04LL RSCAN0.RFDF04.UINT8[LL]
+#define RSCAN0RFDF04LH RSCAN0.RFDF04.UINT8[LH]
+#define RSCAN0RFDF04H RSCAN0.RFDF04.UINT16[H]
+#define RSCAN0RFDF04HL RSCAN0.RFDF04.UINT8[HL]
+#define RSCAN0RFDF04HH RSCAN0.RFDF04.UINT8[HH]
+#define RSCAN0RFDF14 RSCAN0.RFDF14.UINT32
+#define RSCAN0RFDF14L RSCAN0.RFDF14.UINT16[L]
+#define RSCAN0RFDF14LL RSCAN0.RFDF14.UINT8[LL]
+#define RSCAN0RFDF14LH RSCAN0.RFDF14.UINT8[LH]
+#define RSCAN0RFDF14H RSCAN0.RFDF14.UINT16[H]
+#define RSCAN0RFDF14HL RSCAN0.RFDF14.UINT8[HL]
+#define RSCAN0RFDF14HH RSCAN0.RFDF14.UINT8[HH]
+#define RSCAN0RFID5 RSCAN0.RFID5.UINT32
+#define RSCAN0RFID5L RSCAN0.RFID5.UINT16[L]
+#define RSCAN0RFID5LL RSCAN0.RFID5.UINT8[LL]
+#define RSCAN0RFID5LH RSCAN0.RFID5.UINT8[LH]
+#define RSCAN0RFID5H RSCAN0.RFID5.UINT16[H]
+#define RSCAN0RFID5HL RSCAN0.RFID5.UINT8[HL]
+#define RSCAN0RFID5HH RSCAN0.RFID5.UINT8[HH]
+#define RSCAN0RFPTR5 RSCAN0.RFPTR5.UINT32
+#define RSCAN0RFPTR5L RSCAN0.RFPTR5.UINT16[L]
+#define RSCAN0RFPTR5LL RSCAN0.RFPTR5.UINT8[LL]
+#define RSCAN0RFPTR5LH RSCAN0.RFPTR5.UINT8[LH]
+#define RSCAN0RFPTR5H RSCAN0.RFPTR5.UINT16[H]
+#define RSCAN0RFPTR5HL RSCAN0.RFPTR5.UINT8[HL]
+#define RSCAN0RFPTR5HH RSCAN0.RFPTR5.UINT8[HH]
+#define RSCAN0RFDF05 RSCAN0.RFDF05.UINT32
+#define RSCAN0RFDF05L RSCAN0.RFDF05.UINT16[L]
+#define RSCAN0RFDF05LL RSCAN0.RFDF05.UINT8[LL]
+#define RSCAN0RFDF05LH RSCAN0.RFDF05.UINT8[LH]
+#define RSCAN0RFDF05H RSCAN0.RFDF05.UINT16[H]
+#define RSCAN0RFDF05HL RSCAN0.RFDF05.UINT8[HL]
+#define RSCAN0RFDF05HH RSCAN0.RFDF05.UINT8[HH]
+#define RSCAN0RFDF15 RSCAN0.RFDF15.UINT32
+#define RSCAN0RFDF15L RSCAN0.RFDF15.UINT16[L]
+#define RSCAN0RFDF15LL RSCAN0.RFDF15.UINT8[LL]
+#define RSCAN0RFDF15LH RSCAN0.RFDF15.UINT8[LH]
+#define RSCAN0RFDF15H RSCAN0.RFDF15.UINT16[H]
+#define RSCAN0RFDF15HL RSCAN0.RFDF15.UINT8[HL]
+#define RSCAN0RFDF15HH RSCAN0.RFDF15.UINT8[HH]
+#define RSCAN0RFID6 RSCAN0.RFID6.UINT32
+#define RSCAN0RFID6L RSCAN0.RFID6.UINT16[L]
+#define RSCAN0RFID6LL RSCAN0.RFID6.UINT8[LL]
+#define RSCAN0RFID6LH RSCAN0.RFID6.UINT8[LH]
+#define RSCAN0RFID6H RSCAN0.RFID6.UINT16[H]
+#define RSCAN0RFID6HL RSCAN0.RFID6.UINT8[HL]
+#define RSCAN0RFID6HH RSCAN0.RFID6.UINT8[HH]
+#define RSCAN0RFPTR6 RSCAN0.RFPTR6.UINT32
+#define RSCAN0RFPTR6L RSCAN0.RFPTR6.UINT16[L]
+#define RSCAN0RFPTR6LL RSCAN0.RFPTR6.UINT8[LL]
+#define RSCAN0RFPTR6LH RSCAN0.RFPTR6.UINT8[LH]
+#define RSCAN0RFPTR6H RSCAN0.RFPTR6.UINT16[H]
+#define RSCAN0RFPTR6HL RSCAN0.RFPTR6.UINT8[HL]
+#define RSCAN0RFPTR6HH RSCAN0.RFPTR6.UINT8[HH]
+#define RSCAN0RFDF06 RSCAN0.RFDF06.UINT32
+#define RSCAN0RFDF06L RSCAN0.RFDF06.UINT16[L]
+#define RSCAN0RFDF06LL RSCAN0.RFDF06.UINT8[LL]
+#define RSCAN0RFDF06LH RSCAN0.RFDF06.UINT8[LH]
+#define RSCAN0RFDF06H RSCAN0.RFDF06.UINT16[H]
+#define RSCAN0RFDF06HL RSCAN0.RFDF06.UINT8[HL]
+#define RSCAN0RFDF06HH RSCAN0.RFDF06.UINT8[HH]
+#define RSCAN0RFDF16 RSCAN0.RFDF16.UINT32
+#define RSCAN0RFDF16L RSCAN0.RFDF16.UINT16[L]
+#define RSCAN0RFDF16LL RSCAN0.RFDF16.UINT8[LL]
+#define RSCAN0RFDF16LH RSCAN0.RFDF16.UINT8[LH]
+#define RSCAN0RFDF16H RSCAN0.RFDF16.UINT16[H]
+#define RSCAN0RFDF16HL RSCAN0.RFDF16.UINT8[HL]
+#define RSCAN0RFDF16HH RSCAN0.RFDF16.UINT8[HH]
+#define RSCAN0RFID7 RSCAN0.RFID7.UINT32
+#define RSCAN0RFID7L RSCAN0.RFID7.UINT16[L]
+#define RSCAN0RFID7LL RSCAN0.RFID7.UINT8[LL]
+#define RSCAN0RFID7LH RSCAN0.RFID7.UINT8[LH]
+#define RSCAN0RFID7H RSCAN0.RFID7.UINT16[H]
+#define RSCAN0RFID7HL RSCAN0.RFID7.UINT8[HL]
+#define RSCAN0RFID7HH RSCAN0.RFID7.UINT8[HH]
+#define RSCAN0RFPTR7 RSCAN0.RFPTR7.UINT32
+#define RSCAN0RFPTR7L RSCAN0.RFPTR7.UINT16[L]
+#define RSCAN0RFPTR7LL RSCAN0.RFPTR7.UINT8[LL]
+#define RSCAN0RFPTR7LH RSCAN0.RFPTR7.UINT8[LH]
+#define RSCAN0RFPTR7H RSCAN0.RFPTR7.UINT16[H]
+#define RSCAN0RFPTR7HL RSCAN0.RFPTR7.UINT8[HL]
+#define RSCAN0RFPTR7HH RSCAN0.RFPTR7.UINT8[HH]
+#define RSCAN0RFDF07 RSCAN0.RFDF07.UINT32
+#define RSCAN0RFDF07L RSCAN0.RFDF07.UINT16[L]
+#define RSCAN0RFDF07LL RSCAN0.RFDF07.UINT8[LL]
+#define RSCAN0RFDF07LH RSCAN0.RFDF07.UINT8[LH]
+#define RSCAN0RFDF07H RSCAN0.RFDF07.UINT16[H]
+#define RSCAN0RFDF07HL RSCAN0.RFDF07.UINT8[HL]
+#define RSCAN0RFDF07HH RSCAN0.RFDF07.UINT8[HH]
+#define RSCAN0RFDF17 RSCAN0.RFDF17.UINT32
+#define RSCAN0RFDF17L RSCAN0.RFDF17.UINT16[L]
+#define RSCAN0RFDF17LL RSCAN0.RFDF17.UINT8[LL]
+#define RSCAN0RFDF17LH RSCAN0.RFDF17.UINT8[LH]
+#define RSCAN0RFDF17H RSCAN0.RFDF17.UINT16[H]
+#define RSCAN0RFDF17HL RSCAN0.RFDF17.UINT8[HL]
+#define RSCAN0RFDF17HH RSCAN0.RFDF17.UINT8[HH]
+#define RSCAN0CFID0 RSCAN0.CFID0.UINT32
+#define RSCAN0CFID0L RSCAN0.CFID0.UINT16[L]
+#define RSCAN0CFID0LL RSCAN0.CFID0.UINT8[LL]
+#define RSCAN0CFID0LH RSCAN0.CFID0.UINT8[LH]
+#define RSCAN0CFID0H RSCAN0.CFID0.UINT16[H]
+#define RSCAN0CFID0HL RSCAN0.CFID0.UINT8[HL]
+#define RSCAN0CFID0HH RSCAN0.CFID0.UINT8[HH]
+#define RSCAN0CFPTR0 RSCAN0.CFPTR0.UINT32
+#define RSCAN0CFPTR0L RSCAN0.CFPTR0.UINT16[L]
+#define RSCAN0CFPTR0LL RSCAN0.CFPTR0.UINT8[LL]
+#define RSCAN0CFPTR0LH RSCAN0.CFPTR0.UINT8[LH]
+#define RSCAN0CFPTR0H RSCAN0.CFPTR0.UINT16[H]
+#define RSCAN0CFPTR0HL RSCAN0.CFPTR0.UINT8[HL]
+#define RSCAN0CFPTR0HH RSCAN0.CFPTR0.UINT8[HH]
+#define RSCAN0CFDF00 RSCAN0.CFDF00.UINT32
+#define RSCAN0CFDF00L RSCAN0.CFDF00.UINT16[L]
+#define RSCAN0CFDF00LL RSCAN0.CFDF00.UINT8[LL]
+#define RSCAN0CFDF00LH RSCAN0.CFDF00.UINT8[LH]
+#define RSCAN0CFDF00H RSCAN0.CFDF00.UINT16[H]
+#define RSCAN0CFDF00HL RSCAN0.CFDF00.UINT8[HL]
+#define RSCAN0CFDF00HH RSCAN0.CFDF00.UINT8[HH]
+#define RSCAN0CFDF10 RSCAN0.CFDF10.UINT32
+#define RSCAN0CFDF10L RSCAN0.CFDF10.UINT16[L]
+#define RSCAN0CFDF10LL RSCAN0.CFDF10.UINT8[LL]
+#define RSCAN0CFDF10LH RSCAN0.CFDF10.UINT8[LH]
+#define RSCAN0CFDF10H RSCAN0.CFDF10.UINT16[H]
+#define RSCAN0CFDF10HL RSCAN0.CFDF10.UINT8[HL]
+#define RSCAN0CFDF10HH RSCAN0.CFDF10.UINT8[HH]
+#define RSCAN0CFID1 RSCAN0.CFID1.UINT32
+#define RSCAN0CFID1L RSCAN0.CFID1.UINT16[L]
+#define RSCAN0CFID1LL RSCAN0.CFID1.UINT8[LL]
+#define RSCAN0CFID1LH RSCAN0.CFID1.UINT8[LH]
+#define RSCAN0CFID1H RSCAN0.CFID1.UINT16[H]
+#define RSCAN0CFID1HL RSCAN0.CFID1.UINT8[HL]
+#define RSCAN0CFID1HH RSCAN0.CFID1.UINT8[HH]
+#define RSCAN0CFPTR1 RSCAN0.CFPTR1.UINT32
+#define RSCAN0CFPTR1L RSCAN0.CFPTR1.UINT16[L]
+#define RSCAN0CFPTR1LL RSCAN0.CFPTR1.UINT8[LL]
+#define RSCAN0CFPTR1LH RSCAN0.CFPTR1.UINT8[LH]
+#define RSCAN0CFPTR1H RSCAN0.CFPTR1.UINT16[H]
+#define RSCAN0CFPTR1HL RSCAN0.CFPTR1.UINT8[HL]
+#define RSCAN0CFPTR1HH RSCAN0.CFPTR1.UINT8[HH]
+#define RSCAN0CFDF01 RSCAN0.CFDF01.UINT32
+#define RSCAN0CFDF01L RSCAN0.CFDF01.UINT16[L]
+#define RSCAN0CFDF01LL RSCAN0.CFDF01.UINT8[LL]
+#define RSCAN0CFDF01LH RSCAN0.CFDF01.UINT8[LH]
+#define RSCAN0CFDF01H RSCAN0.CFDF01.UINT16[H]
+#define RSCAN0CFDF01HL RSCAN0.CFDF01.UINT8[HL]
+#define RSCAN0CFDF01HH RSCAN0.CFDF01.UINT8[HH]
+#define RSCAN0CFDF11 RSCAN0.CFDF11.UINT32
+#define RSCAN0CFDF11L RSCAN0.CFDF11.UINT16[L]
+#define RSCAN0CFDF11LL RSCAN0.CFDF11.UINT8[LL]
+#define RSCAN0CFDF11LH RSCAN0.CFDF11.UINT8[LH]
+#define RSCAN0CFDF11H RSCAN0.CFDF11.UINT16[H]
+#define RSCAN0CFDF11HL RSCAN0.CFDF11.UINT8[HL]
+#define RSCAN0CFDF11HH RSCAN0.CFDF11.UINT8[HH]
+#define RSCAN0CFID2 RSCAN0.CFID2.UINT32
+#define RSCAN0CFID2L RSCAN0.CFID2.UINT16[L]
+#define RSCAN0CFID2LL RSCAN0.CFID2.UINT8[LL]
+#define RSCAN0CFID2LH RSCAN0.CFID2.UINT8[LH]
+#define RSCAN0CFID2H RSCAN0.CFID2.UINT16[H]
+#define RSCAN0CFID2HL RSCAN0.CFID2.UINT8[HL]
+#define RSCAN0CFID2HH RSCAN0.CFID2.UINT8[HH]
+#define RSCAN0CFPTR2 RSCAN0.CFPTR2.UINT32
+#define RSCAN0CFPTR2L RSCAN0.CFPTR2.UINT16[L]
+#define RSCAN0CFPTR2LL RSCAN0.CFPTR2.UINT8[LL]
+#define RSCAN0CFPTR2LH RSCAN0.CFPTR2.UINT8[LH]
+#define RSCAN0CFPTR2H RSCAN0.CFPTR2.UINT16[H]
+#define RSCAN0CFPTR2HL RSCAN0.CFPTR2.UINT8[HL]
+#define RSCAN0CFPTR2HH RSCAN0.CFPTR2.UINT8[HH]
+#define RSCAN0CFDF02 RSCAN0.CFDF02.UINT32
+#define RSCAN0CFDF02L RSCAN0.CFDF02.UINT16[L]
+#define RSCAN0CFDF02LL RSCAN0.CFDF02.UINT8[LL]
+#define RSCAN0CFDF02LH RSCAN0.CFDF02.UINT8[LH]
+#define RSCAN0CFDF02H RSCAN0.CFDF02.UINT16[H]
+#define RSCAN0CFDF02HL RSCAN0.CFDF02.UINT8[HL]
+#define RSCAN0CFDF02HH RSCAN0.CFDF02.UINT8[HH]
+#define RSCAN0CFDF12 RSCAN0.CFDF12.UINT32
+#define RSCAN0CFDF12L RSCAN0.CFDF12.UINT16[L]
+#define RSCAN0CFDF12LL RSCAN0.CFDF12.UINT8[LL]
+#define RSCAN0CFDF12LH RSCAN0.CFDF12.UINT8[LH]
+#define RSCAN0CFDF12H RSCAN0.CFDF12.UINT16[H]
+#define RSCAN0CFDF12HL RSCAN0.CFDF12.UINT8[HL]
+#define RSCAN0CFDF12HH RSCAN0.CFDF12.UINT8[HH]
+#define RSCAN0CFID3 RSCAN0.CFID3.UINT32
+#define RSCAN0CFID3L RSCAN0.CFID3.UINT16[L]
+#define RSCAN0CFID3LL RSCAN0.CFID3.UINT8[LL]
+#define RSCAN0CFID3LH RSCAN0.CFID3.UINT8[LH]
+#define RSCAN0CFID3H RSCAN0.CFID3.UINT16[H]
+#define RSCAN0CFID3HL RSCAN0.CFID3.UINT8[HL]
+#define RSCAN0CFID3HH RSCAN0.CFID3.UINT8[HH]
+#define RSCAN0CFPTR3 RSCAN0.CFPTR3.UINT32
+#define RSCAN0CFPTR3L RSCAN0.CFPTR3.UINT16[L]
+#define RSCAN0CFPTR3LL RSCAN0.CFPTR3.UINT8[LL]
+#define RSCAN0CFPTR3LH RSCAN0.CFPTR3.UINT8[LH]
+#define RSCAN0CFPTR3H RSCAN0.CFPTR3.UINT16[H]
+#define RSCAN0CFPTR3HL RSCAN0.CFPTR3.UINT8[HL]
+#define RSCAN0CFPTR3HH RSCAN0.CFPTR3.UINT8[HH]
+#define RSCAN0CFDF03 RSCAN0.CFDF03.UINT32
+#define RSCAN0CFDF03L RSCAN0.CFDF03.UINT16[L]
+#define RSCAN0CFDF03LL RSCAN0.CFDF03.UINT8[LL]
+#define RSCAN0CFDF03LH RSCAN0.CFDF03.UINT8[LH]
+#define RSCAN0CFDF03H RSCAN0.CFDF03.UINT16[H]
+#define RSCAN0CFDF03HL RSCAN0.CFDF03.UINT8[HL]
+#define RSCAN0CFDF03HH RSCAN0.CFDF03.UINT8[HH]
+#define RSCAN0CFDF13 RSCAN0.CFDF13.UINT32
+#define RSCAN0CFDF13L RSCAN0.CFDF13.UINT16[L]
+#define RSCAN0CFDF13LL RSCAN0.CFDF13.UINT8[LL]
+#define RSCAN0CFDF13LH RSCAN0.CFDF13.UINT8[LH]
+#define RSCAN0CFDF13H RSCAN0.CFDF13.UINT16[H]
+#define RSCAN0CFDF13HL RSCAN0.CFDF13.UINT8[HL]
+#define RSCAN0CFDF13HH RSCAN0.CFDF13.UINT8[HH]
+#define RSCAN0CFID4 RSCAN0.CFID4.UINT32
+#define RSCAN0CFID4L RSCAN0.CFID4.UINT16[L]
+#define RSCAN0CFID4LL RSCAN0.CFID4.UINT8[LL]
+#define RSCAN0CFID4LH RSCAN0.CFID4.UINT8[LH]
+#define RSCAN0CFID4H RSCAN0.CFID4.UINT16[H]
+#define RSCAN0CFID4HL RSCAN0.CFID4.UINT8[HL]
+#define RSCAN0CFID4HH RSCAN0.CFID4.UINT8[HH]
+#define RSCAN0CFPTR4 RSCAN0.CFPTR4.UINT32
+#define RSCAN0CFPTR4L RSCAN0.CFPTR4.UINT16[L]
+#define RSCAN0CFPTR4LL RSCAN0.CFPTR4.UINT8[LL]
+#define RSCAN0CFPTR4LH RSCAN0.CFPTR4.UINT8[LH]
+#define RSCAN0CFPTR4H RSCAN0.CFPTR4.UINT16[H]
+#define RSCAN0CFPTR4HL RSCAN0.CFPTR4.UINT8[HL]
+#define RSCAN0CFPTR4HH RSCAN0.CFPTR4.UINT8[HH]
+#define RSCAN0CFDF04 RSCAN0.CFDF04.UINT32
+#define RSCAN0CFDF04L RSCAN0.CFDF04.UINT16[L]
+#define RSCAN0CFDF04LL RSCAN0.CFDF04.UINT8[LL]
+#define RSCAN0CFDF04LH RSCAN0.CFDF04.UINT8[LH]
+#define RSCAN0CFDF04H RSCAN0.CFDF04.UINT16[H]
+#define RSCAN0CFDF04HL RSCAN0.CFDF04.UINT8[HL]
+#define RSCAN0CFDF04HH RSCAN0.CFDF04.UINT8[HH]
+#define RSCAN0CFDF14 RSCAN0.CFDF14.UINT32
+#define RSCAN0CFDF14L RSCAN0.CFDF14.UINT16[L]
+#define RSCAN0CFDF14LL RSCAN0.CFDF14.UINT8[LL]
+#define RSCAN0CFDF14LH RSCAN0.CFDF14.UINT8[LH]
+#define RSCAN0CFDF14H RSCAN0.CFDF14.UINT16[H]
+#define RSCAN0CFDF14HL RSCAN0.CFDF14.UINT8[HL]
+#define RSCAN0CFDF14HH RSCAN0.CFDF14.UINT8[HH]
+#define RSCAN0CFID5 RSCAN0.CFID5.UINT32
+#define RSCAN0CFID5L RSCAN0.CFID5.UINT16[L]
+#define RSCAN0CFID5LL RSCAN0.CFID5.UINT8[LL]
+#define RSCAN0CFID5LH RSCAN0.CFID5.UINT8[LH]
+#define RSCAN0CFID5H RSCAN0.CFID5.UINT16[H]
+#define RSCAN0CFID5HL RSCAN0.CFID5.UINT8[HL]
+#define RSCAN0CFID5HH RSCAN0.CFID5.UINT8[HH]
+#define RSCAN0CFPTR5 RSCAN0.CFPTR5.UINT32
+#define RSCAN0CFPTR5L RSCAN0.CFPTR5.UINT16[L]
+#define RSCAN0CFPTR5LL RSCAN0.CFPTR5.UINT8[LL]
+#define RSCAN0CFPTR5LH RSCAN0.CFPTR5.UINT8[LH]
+#define RSCAN0CFPTR5H RSCAN0.CFPTR5.UINT16[H]
+#define RSCAN0CFPTR5HL RSCAN0.CFPTR5.UINT8[HL]
+#define RSCAN0CFPTR5HH RSCAN0.CFPTR5.UINT8[HH]
+#define RSCAN0CFDF05 RSCAN0.CFDF05.UINT32
+#define RSCAN0CFDF05L RSCAN0.CFDF05.UINT16[L]
+#define RSCAN0CFDF05LL RSCAN0.CFDF05.UINT8[LL]
+#define RSCAN0CFDF05LH RSCAN0.CFDF05.UINT8[LH]
+#define RSCAN0CFDF05H RSCAN0.CFDF05.UINT16[H]
+#define RSCAN0CFDF05HL RSCAN0.CFDF05.UINT8[HL]
+#define RSCAN0CFDF05HH RSCAN0.CFDF05.UINT8[HH]
+#define RSCAN0CFDF15 RSCAN0.CFDF15.UINT32
+#define RSCAN0CFDF15L RSCAN0.CFDF15.UINT16[L]
+#define RSCAN0CFDF15LL RSCAN0.CFDF15.UINT8[LL]
+#define RSCAN0CFDF15LH RSCAN0.CFDF15.UINT8[LH]
+#define RSCAN0CFDF15H RSCAN0.CFDF15.UINT16[H]
+#define RSCAN0CFDF15HL RSCAN0.CFDF15.UINT8[HL]
+#define RSCAN0CFDF15HH RSCAN0.CFDF15.UINT8[HH]
+#define RSCAN0CFID6 RSCAN0.CFID6.UINT32
+#define RSCAN0CFID6L RSCAN0.CFID6.UINT16[L]
+#define RSCAN0CFID6LL RSCAN0.CFID6.UINT8[LL]
+#define RSCAN0CFID6LH RSCAN0.CFID6.UINT8[LH]
+#define RSCAN0CFID6H RSCAN0.CFID6.UINT16[H]
+#define RSCAN0CFID6HL RSCAN0.CFID6.UINT8[HL]
+#define RSCAN0CFID6HH RSCAN0.CFID6.UINT8[HH]
+#define RSCAN0CFPTR6 RSCAN0.CFPTR6.UINT32
+#define RSCAN0CFPTR6L RSCAN0.CFPTR6.UINT16[L]
+#define RSCAN0CFPTR6LL RSCAN0.CFPTR6.UINT8[LL]
+#define RSCAN0CFPTR6LH RSCAN0.CFPTR6.UINT8[LH]
+#define RSCAN0CFPTR6H RSCAN0.CFPTR6.UINT16[H]
+#define RSCAN0CFPTR6HL RSCAN0.CFPTR6.UINT8[HL]
+#define RSCAN0CFPTR6HH RSCAN0.CFPTR6.UINT8[HH]
+#define RSCAN0CFDF06 RSCAN0.CFDF06.UINT32
+#define RSCAN0CFDF06L RSCAN0.CFDF06.UINT16[L]
+#define RSCAN0CFDF06LL RSCAN0.CFDF06.UINT8[LL]
+#define RSCAN0CFDF06LH RSCAN0.CFDF06.UINT8[LH]
+#define RSCAN0CFDF06H RSCAN0.CFDF06.UINT16[H]
+#define RSCAN0CFDF06HL RSCAN0.CFDF06.UINT8[HL]
+#define RSCAN0CFDF06HH RSCAN0.CFDF06.UINT8[HH]
+#define RSCAN0CFDF16 RSCAN0.CFDF16.UINT32
+#define RSCAN0CFDF16L RSCAN0.CFDF16.UINT16[L]
+#define RSCAN0CFDF16LL RSCAN0.CFDF16.UINT8[LL]
+#define RSCAN0CFDF16LH RSCAN0.CFDF16.UINT8[LH]
+#define RSCAN0CFDF16H RSCAN0.CFDF16.UINT16[H]
+#define RSCAN0CFDF16HL RSCAN0.CFDF16.UINT8[HL]
+#define RSCAN0CFDF16HH RSCAN0.CFDF16.UINT8[HH]
+#define RSCAN0CFID7 RSCAN0.CFID7.UINT32
+#define RSCAN0CFID7L RSCAN0.CFID7.UINT16[L]
+#define RSCAN0CFID7LL RSCAN0.CFID7.UINT8[LL]
+#define RSCAN0CFID7LH RSCAN0.CFID7.UINT8[LH]
+#define RSCAN0CFID7H RSCAN0.CFID7.UINT16[H]
+#define RSCAN0CFID7HL RSCAN0.CFID7.UINT8[HL]
+#define RSCAN0CFID7HH RSCAN0.CFID7.UINT8[HH]
+#define RSCAN0CFPTR7 RSCAN0.CFPTR7.UINT32
+#define RSCAN0CFPTR7L RSCAN0.CFPTR7.UINT16[L]
+#define RSCAN0CFPTR7LL RSCAN0.CFPTR7.UINT8[LL]
+#define RSCAN0CFPTR7LH RSCAN0.CFPTR7.UINT8[LH]
+#define RSCAN0CFPTR7H RSCAN0.CFPTR7.UINT16[H]
+#define RSCAN0CFPTR7HL RSCAN0.CFPTR7.UINT8[HL]
+#define RSCAN0CFPTR7HH RSCAN0.CFPTR7.UINT8[HH]
+#define RSCAN0CFDF07 RSCAN0.CFDF07.UINT32
+#define RSCAN0CFDF07L RSCAN0.CFDF07.UINT16[L]
+#define RSCAN0CFDF07LL RSCAN0.CFDF07.UINT8[LL]
+#define RSCAN0CFDF07LH RSCAN0.CFDF07.UINT8[LH]
+#define RSCAN0CFDF07H RSCAN0.CFDF07.UINT16[H]
+#define RSCAN0CFDF07HL RSCAN0.CFDF07.UINT8[HL]
+#define RSCAN0CFDF07HH RSCAN0.CFDF07.UINT8[HH]
+#define RSCAN0CFDF17 RSCAN0.CFDF17.UINT32
+#define RSCAN0CFDF17L RSCAN0.CFDF17.UINT16[L]
+#define RSCAN0CFDF17LL RSCAN0.CFDF17.UINT8[LL]
+#define RSCAN0CFDF17LH RSCAN0.CFDF17.UINT8[LH]
+#define RSCAN0CFDF17H RSCAN0.CFDF17.UINT16[H]
+#define RSCAN0CFDF17HL RSCAN0.CFDF17.UINT8[HL]
+#define RSCAN0CFDF17HH RSCAN0.CFDF17.UINT8[HH]
+#define RSCAN0CFID8 RSCAN0.CFID8.UINT32
+#define RSCAN0CFID8L RSCAN0.CFID8.UINT16[L]
+#define RSCAN0CFID8LL RSCAN0.CFID8.UINT8[LL]
+#define RSCAN0CFID8LH RSCAN0.CFID8.UINT8[LH]
+#define RSCAN0CFID8H RSCAN0.CFID8.UINT16[H]
+#define RSCAN0CFID8HL RSCAN0.CFID8.UINT8[HL]
+#define RSCAN0CFID8HH RSCAN0.CFID8.UINT8[HH]
+#define RSCAN0CFPTR8 RSCAN0.CFPTR8.UINT32
+#define RSCAN0CFPTR8L RSCAN0.CFPTR8.UINT16[L]
+#define RSCAN0CFPTR8LL RSCAN0.CFPTR8.UINT8[LL]
+#define RSCAN0CFPTR8LH RSCAN0.CFPTR8.UINT8[LH]
+#define RSCAN0CFPTR8H RSCAN0.CFPTR8.UINT16[H]
+#define RSCAN0CFPTR8HL RSCAN0.CFPTR8.UINT8[HL]
+#define RSCAN0CFPTR8HH RSCAN0.CFPTR8.UINT8[HH]
+#define RSCAN0CFDF08 RSCAN0.CFDF08.UINT32
+#define RSCAN0CFDF08L RSCAN0.CFDF08.UINT16[L]
+#define RSCAN0CFDF08LL RSCAN0.CFDF08.UINT8[LL]
+#define RSCAN0CFDF08LH RSCAN0.CFDF08.UINT8[LH]
+#define RSCAN0CFDF08H RSCAN0.CFDF08.UINT16[H]
+#define RSCAN0CFDF08HL RSCAN0.CFDF08.UINT8[HL]
+#define RSCAN0CFDF08HH RSCAN0.CFDF08.UINT8[HH]
+#define RSCAN0CFDF18 RSCAN0.CFDF18.UINT32
+#define RSCAN0CFDF18L RSCAN0.CFDF18.UINT16[L]
+#define RSCAN0CFDF18LL RSCAN0.CFDF18.UINT8[LL]
+#define RSCAN0CFDF18LH RSCAN0.CFDF18.UINT8[LH]
+#define RSCAN0CFDF18H RSCAN0.CFDF18.UINT16[H]
+#define RSCAN0CFDF18HL RSCAN0.CFDF18.UINT8[HL]
+#define RSCAN0CFDF18HH RSCAN0.CFDF18.UINT8[HH]
+#define RSCAN0CFID9 RSCAN0.CFID9.UINT32
+#define RSCAN0CFID9L RSCAN0.CFID9.UINT16[L]
+#define RSCAN0CFID9LL RSCAN0.CFID9.UINT8[LL]
+#define RSCAN0CFID9LH RSCAN0.CFID9.UINT8[LH]
+#define RSCAN0CFID9H RSCAN0.CFID9.UINT16[H]
+#define RSCAN0CFID9HL RSCAN0.CFID9.UINT8[HL]
+#define RSCAN0CFID9HH RSCAN0.CFID9.UINT8[HH]
+#define RSCAN0CFPTR9 RSCAN0.CFPTR9.UINT32
+#define RSCAN0CFPTR9L RSCAN0.CFPTR9.UINT16[L]
+#define RSCAN0CFPTR9LL RSCAN0.CFPTR9.UINT8[LL]
+#define RSCAN0CFPTR9LH RSCAN0.CFPTR9.UINT8[LH]
+#define RSCAN0CFPTR9H RSCAN0.CFPTR9.UINT16[H]
+#define RSCAN0CFPTR9HL RSCAN0.CFPTR9.UINT8[HL]
+#define RSCAN0CFPTR9HH RSCAN0.CFPTR9.UINT8[HH]
+#define RSCAN0CFDF09 RSCAN0.CFDF09.UINT32
+#define RSCAN0CFDF09L RSCAN0.CFDF09.UINT16[L]
+#define RSCAN0CFDF09LL RSCAN0.CFDF09.UINT8[LL]
+#define RSCAN0CFDF09LH RSCAN0.CFDF09.UINT8[LH]
+#define RSCAN0CFDF09H RSCAN0.CFDF09.UINT16[H]
+#define RSCAN0CFDF09HL RSCAN0.CFDF09.UINT8[HL]
+#define RSCAN0CFDF09HH RSCAN0.CFDF09.UINT8[HH]
+#define RSCAN0CFDF19 RSCAN0.CFDF19.UINT32
+#define RSCAN0CFDF19L RSCAN0.CFDF19.UINT16[L]
+#define RSCAN0CFDF19LL RSCAN0.CFDF19.UINT8[LL]
+#define RSCAN0CFDF19LH RSCAN0.CFDF19.UINT8[LH]
+#define RSCAN0CFDF19H RSCAN0.CFDF19.UINT16[H]
+#define RSCAN0CFDF19HL RSCAN0.CFDF19.UINT8[HL]
+#define RSCAN0CFDF19HH RSCAN0.CFDF19.UINT8[HH]
+#define RSCAN0CFID10 RSCAN0.CFID10.UINT32
+#define RSCAN0CFID10L RSCAN0.CFID10.UINT16[L]
+#define RSCAN0CFID10LL RSCAN0.CFID10.UINT8[LL]
+#define RSCAN0CFID10LH RSCAN0.CFID10.UINT8[LH]
+#define RSCAN0CFID10H RSCAN0.CFID10.UINT16[H]
+#define RSCAN0CFID10HL RSCAN0.CFID10.UINT8[HL]
+#define RSCAN0CFID10HH RSCAN0.CFID10.UINT8[HH]
+#define RSCAN0CFPTR10 RSCAN0.CFPTR10.UINT32
+#define RSCAN0CFPTR10L RSCAN0.CFPTR10.UINT16[L]
+#define RSCAN0CFPTR10LL RSCAN0.CFPTR10.UINT8[LL]
+#define RSCAN0CFPTR10LH RSCAN0.CFPTR10.UINT8[LH]
+#define RSCAN0CFPTR10H RSCAN0.CFPTR10.UINT16[H]
+#define RSCAN0CFPTR10HL RSCAN0.CFPTR10.UINT8[HL]
+#define RSCAN0CFPTR10HH RSCAN0.CFPTR10.UINT8[HH]
+#define RSCAN0CFDF010 RSCAN0.CFDF010.UINT32
+#define RSCAN0CFDF010L RSCAN0.CFDF010.UINT16[L]
+#define RSCAN0CFDF010LL RSCAN0.CFDF010.UINT8[LL]
+#define RSCAN0CFDF010LH RSCAN0.CFDF010.UINT8[LH]
+#define RSCAN0CFDF010H RSCAN0.CFDF010.UINT16[H]
+#define RSCAN0CFDF010HL RSCAN0.CFDF010.UINT8[HL]
+#define RSCAN0CFDF010HH RSCAN0.CFDF010.UINT8[HH]
+#define RSCAN0CFDF110 RSCAN0.CFDF110.UINT32
+#define RSCAN0CFDF110L RSCAN0.CFDF110.UINT16[L]
+#define RSCAN0CFDF110LL RSCAN0.CFDF110.UINT8[LL]
+#define RSCAN0CFDF110LH RSCAN0.CFDF110.UINT8[LH]
+#define RSCAN0CFDF110H RSCAN0.CFDF110.UINT16[H]
+#define RSCAN0CFDF110HL RSCAN0.CFDF110.UINT8[HL]
+#define RSCAN0CFDF110HH RSCAN0.CFDF110.UINT8[HH]
+#define RSCAN0CFID11 RSCAN0.CFID11.UINT32
+#define RSCAN0CFID11L RSCAN0.CFID11.UINT16[L]
+#define RSCAN0CFID11LL RSCAN0.CFID11.UINT8[LL]
+#define RSCAN0CFID11LH RSCAN0.CFID11.UINT8[LH]
+#define RSCAN0CFID11H RSCAN0.CFID11.UINT16[H]
+#define RSCAN0CFID11HL RSCAN0.CFID11.UINT8[HL]
+#define RSCAN0CFID11HH RSCAN0.CFID11.UINT8[HH]
+#define RSCAN0CFPTR11 RSCAN0.CFPTR11.UINT32
+#define RSCAN0CFPTR11L RSCAN0.CFPTR11.UINT16[L]
+#define RSCAN0CFPTR11LL RSCAN0.CFPTR11.UINT8[LL]
+#define RSCAN0CFPTR11LH RSCAN0.CFPTR11.UINT8[LH]
+#define RSCAN0CFPTR11H RSCAN0.CFPTR11.UINT16[H]
+#define RSCAN0CFPTR11HL RSCAN0.CFPTR11.UINT8[HL]
+#define RSCAN0CFPTR11HH RSCAN0.CFPTR11.UINT8[HH]
+#define RSCAN0CFDF011 RSCAN0.CFDF011.UINT32
+#define RSCAN0CFDF011L RSCAN0.CFDF011.UINT16[L]
+#define RSCAN0CFDF011LL RSCAN0.CFDF011.UINT8[LL]
+#define RSCAN0CFDF011LH RSCAN0.CFDF011.UINT8[LH]
+#define RSCAN0CFDF011H RSCAN0.CFDF011.UINT16[H]
+#define RSCAN0CFDF011HL RSCAN0.CFDF011.UINT8[HL]
+#define RSCAN0CFDF011HH RSCAN0.CFDF011.UINT8[HH]
+#define RSCAN0CFDF111 RSCAN0.CFDF111.UINT32
+#define RSCAN0CFDF111L RSCAN0.CFDF111.UINT16[L]
+#define RSCAN0CFDF111LL RSCAN0.CFDF111.UINT8[LL]
+#define RSCAN0CFDF111LH RSCAN0.CFDF111.UINT8[LH]
+#define RSCAN0CFDF111H RSCAN0.CFDF111.UINT16[H]
+#define RSCAN0CFDF111HL RSCAN0.CFDF111.UINT8[HL]
+#define RSCAN0CFDF111HH RSCAN0.CFDF111.UINT8[HH]
+#define RSCAN0CFID12 RSCAN0.CFID12.UINT32
+#define RSCAN0CFID12L RSCAN0.CFID12.UINT16[L]
+#define RSCAN0CFID12LL RSCAN0.CFID12.UINT8[LL]
+#define RSCAN0CFID12LH RSCAN0.CFID12.UINT8[LH]
+#define RSCAN0CFID12H RSCAN0.CFID12.UINT16[H]
+#define RSCAN0CFID12HL RSCAN0.CFID12.UINT8[HL]
+#define RSCAN0CFID12HH RSCAN0.CFID12.UINT8[HH]
+#define RSCAN0CFPTR12 RSCAN0.CFPTR12.UINT32
+#define RSCAN0CFPTR12L RSCAN0.CFPTR12.UINT16[L]
+#define RSCAN0CFPTR12LL RSCAN0.CFPTR12.UINT8[LL]
+#define RSCAN0CFPTR12LH RSCAN0.CFPTR12.UINT8[LH]
+#define RSCAN0CFPTR12H RSCAN0.CFPTR12.UINT16[H]
+#define RSCAN0CFPTR12HL RSCAN0.CFPTR12.UINT8[HL]
+#define RSCAN0CFPTR12HH RSCAN0.CFPTR12.UINT8[HH]
+#define RSCAN0CFDF012 RSCAN0.CFDF012.UINT32
+#define RSCAN0CFDF012L RSCAN0.CFDF012.UINT16[L]
+#define RSCAN0CFDF012LL RSCAN0.CFDF012.UINT8[LL]
+#define RSCAN0CFDF012LH RSCAN0.CFDF012.UINT8[LH]
+#define RSCAN0CFDF012H RSCAN0.CFDF012.UINT16[H]
+#define RSCAN0CFDF012HL RSCAN0.CFDF012.UINT8[HL]
+#define RSCAN0CFDF012HH RSCAN0.CFDF012.UINT8[HH]
+#define RSCAN0CFDF112 RSCAN0.CFDF112.UINT32
+#define RSCAN0CFDF112L RSCAN0.CFDF112.UINT16[L]
+#define RSCAN0CFDF112LL RSCAN0.CFDF112.UINT8[LL]
+#define RSCAN0CFDF112LH RSCAN0.CFDF112.UINT8[LH]
+#define RSCAN0CFDF112H RSCAN0.CFDF112.UINT16[H]
+#define RSCAN0CFDF112HL RSCAN0.CFDF112.UINT8[HL]
+#define RSCAN0CFDF112HH RSCAN0.CFDF112.UINT8[HH]
+#define RSCAN0CFID13 RSCAN0.CFID13.UINT32
+#define RSCAN0CFID13L RSCAN0.CFID13.UINT16[L]
+#define RSCAN0CFID13LL RSCAN0.CFID13.UINT8[LL]
+#define RSCAN0CFID13LH RSCAN0.CFID13.UINT8[LH]
+#define RSCAN0CFID13H RSCAN0.CFID13.UINT16[H]
+#define RSCAN0CFID13HL RSCAN0.CFID13.UINT8[HL]
+#define RSCAN0CFID13HH RSCAN0.CFID13.UINT8[HH]
+#define RSCAN0CFPTR13 RSCAN0.CFPTR13.UINT32
+#define RSCAN0CFPTR13L RSCAN0.CFPTR13.UINT16[L]
+#define RSCAN0CFPTR13LL RSCAN0.CFPTR13.UINT8[LL]
+#define RSCAN0CFPTR13LH RSCAN0.CFPTR13.UINT8[LH]
+#define RSCAN0CFPTR13H RSCAN0.CFPTR13.UINT16[H]
+#define RSCAN0CFPTR13HL RSCAN0.CFPTR13.UINT8[HL]
+#define RSCAN0CFPTR13HH RSCAN0.CFPTR13.UINT8[HH]
+#define RSCAN0CFDF013 RSCAN0.CFDF013.UINT32
+#define RSCAN0CFDF013L RSCAN0.CFDF013.UINT16[L]
+#define RSCAN0CFDF013LL RSCAN0.CFDF013.UINT8[LL]
+#define RSCAN0CFDF013LH RSCAN0.CFDF013.UINT8[LH]
+#define RSCAN0CFDF013H RSCAN0.CFDF013.UINT16[H]
+#define RSCAN0CFDF013HL RSCAN0.CFDF013.UINT8[HL]
+#define RSCAN0CFDF013HH RSCAN0.CFDF013.UINT8[HH]
+#define RSCAN0CFDF113 RSCAN0.CFDF113.UINT32
+#define RSCAN0CFDF113L RSCAN0.CFDF113.UINT16[L]
+#define RSCAN0CFDF113LL RSCAN0.CFDF113.UINT8[LL]
+#define RSCAN0CFDF113LH RSCAN0.CFDF113.UINT8[LH]
+#define RSCAN0CFDF113H RSCAN0.CFDF113.UINT16[H]
+#define RSCAN0CFDF113HL RSCAN0.CFDF113.UINT8[HL]
+#define RSCAN0CFDF113HH RSCAN0.CFDF113.UINT8[HH]
+#define RSCAN0CFID14 RSCAN0.CFID14.UINT32
+#define RSCAN0CFID14L RSCAN0.CFID14.UINT16[L]
+#define RSCAN0CFID14LL RSCAN0.CFID14.UINT8[LL]
+#define RSCAN0CFID14LH RSCAN0.CFID14.UINT8[LH]
+#define RSCAN0CFID14H RSCAN0.CFID14.UINT16[H]
+#define RSCAN0CFID14HL RSCAN0.CFID14.UINT8[HL]
+#define RSCAN0CFID14HH RSCAN0.CFID14.UINT8[HH]
+#define RSCAN0CFPTR14 RSCAN0.CFPTR14.UINT32
+#define RSCAN0CFPTR14L RSCAN0.CFPTR14.UINT16[L]
+#define RSCAN0CFPTR14LL RSCAN0.CFPTR14.UINT8[LL]
+#define RSCAN0CFPTR14LH RSCAN0.CFPTR14.UINT8[LH]
+#define RSCAN0CFPTR14H RSCAN0.CFPTR14.UINT16[H]
+#define RSCAN0CFPTR14HL RSCAN0.CFPTR14.UINT8[HL]
+#define RSCAN0CFPTR14HH RSCAN0.CFPTR14.UINT8[HH]
+#define RSCAN0CFDF014 RSCAN0.CFDF014.UINT32
+#define RSCAN0CFDF014L RSCAN0.CFDF014.UINT16[L]
+#define RSCAN0CFDF014LL RSCAN0.CFDF014.UINT8[LL]
+#define RSCAN0CFDF014LH RSCAN0.CFDF014.UINT8[LH]
+#define RSCAN0CFDF014H RSCAN0.CFDF014.UINT16[H]
+#define RSCAN0CFDF014HL RSCAN0.CFDF014.UINT8[HL]
+#define RSCAN0CFDF014HH RSCAN0.CFDF014.UINT8[HH]
+#define RSCAN0CFDF114 RSCAN0.CFDF114.UINT32
+#define RSCAN0CFDF114L RSCAN0.CFDF114.UINT16[L]
+#define RSCAN0CFDF114LL RSCAN0.CFDF114.UINT8[LL]
+#define RSCAN0CFDF114LH RSCAN0.CFDF114.UINT8[LH]
+#define RSCAN0CFDF114H RSCAN0.CFDF114.UINT16[H]
+#define RSCAN0CFDF114HL RSCAN0.CFDF114.UINT8[HL]
+#define RSCAN0CFDF114HH RSCAN0.CFDF114.UINT8[HH]
+#define RSCAN0TMID0 RSCAN0.TMID0.UINT32
+#define RSCAN0TMID0L RSCAN0.TMID0.UINT16[L]
+#define RSCAN0TMID0LL RSCAN0.TMID0.UINT8[LL]
+#define RSCAN0TMID0LH RSCAN0.TMID0.UINT8[LH]
+#define RSCAN0TMID0H RSCAN0.TMID0.UINT16[H]
+#define RSCAN0TMID0HL RSCAN0.TMID0.UINT8[HL]
+#define RSCAN0TMID0HH RSCAN0.TMID0.UINT8[HH]
+#define RSCAN0TMPTR0 RSCAN0.TMPTR0.UINT32
+#define RSCAN0TMPTR0L RSCAN0.TMPTR0.UINT16[L]
+#define RSCAN0TMPTR0LL RSCAN0.TMPTR0.UINT8[LL]
+#define RSCAN0TMPTR0LH RSCAN0.TMPTR0.UINT8[LH]
+#define RSCAN0TMPTR0H RSCAN0.TMPTR0.UINT16[H]
+#define RSCAN0TMPTR0HL RSCAN0.TMPTR0.UINT8[HL]
+#define RSCAN0TMPTR0HH RSCAN0.TMPTR0.UINT8[HH]
+#define RSCAN0TMDF00 RSCAN0.TMDF00.UINT32
+#define RSCAN0TMDF00L RSCAN0.TMDF00.UINT16[L]
+#define RSCAN0TMDF00LL RSCAN0.TMDF00.UINT8[LL]
+#define RSCAN0TMDF00LH RSCAN0.TMDF00.UINT8[LH]
+#define RSCAN0TMDF00H RSCAN0.TMDF00.UINT16[H]
+#define RSCAN0TMDF00HL RSCAN0.TMDF00.UINT8[HL]
+#define RSCAN0TMDF00HH RSCAN0.TMDF00.UINT8[HH]
+#define RSCAN0TMDF10 RSCAN0.TMDF10.UINT32
+#define RSCAN0TMDF10L RSCAN0.TMDF10.UINT16[L]
+#define RSCAN0TMDF10LL RSCAN0.TMDF10.UINT8[LL]
+#define RSCAN0TMDF10LH RSCAN0.TMDF10.UINT8[LH]
+#define RSCAN0TMDF10H RSCAN0.TMDF10.UINT16[H]
+#define RSCAN0TMDF10HL RSCAN0.TMDF10.UINT8[HL]
+#define RSCAN0TMDF10HH RSCAN0.TMDF10.UINT8[HH]
+#define RSCAN0TMID1 RSCAN0.TMID1.UINT32
+#define RSCAN0TMID1L RSCAN0.TMID1.UINT16[L]
+#define RSCAN0TMID1LL RSCAN0.TMID1.UINT8[LL]
+#define RSCAN0TMID1LH RSCAN0.TMID1.UINT8[LH]
+#define RSCAN0TMID1H RSCAN0.TMID1.UINT16[H]
+#define RSCAN0TMID1HL RSCAN0.TMID1.UINT8[HL]
+#define RSCAN0TMID1HH RSCAN0.TMID1.UINT8[HH]
+#define RSCAN0TMPTR1 RSCAN0.TMPTR1.UINT32
+#define RSCAN0TMPTR1L RSCAN0.TMPTR1.UINT16[L]
+#define RSCAN0TMPTR1LL RSCAN0.TMPTR1.UINT8[LL]
+#define RSCAN0TMPTR1LH RSCAN0.TMPTR1.UINT8[LH]
+#define RSCAN0TMPTR1H RSCAN0.TMPTR1.UINT16[H]
+#define RSCAN0TMPTR1HL RSCAN0.TMPTR1.UINT8[HL]
+#define RSCAN0TMPTR1HH RSCAN0.TMPTR1.UINT8[HH]
+#define RSCAN0TMDF01 RSCAN0.TMDF01.UINT32
+#define RSCAN0TMDF01L RSCAN0.TMDF01.UINT16[L]
+#define RSCAN0TMDF01LL RSCAN0.TMDF01.UINT8[LL]
+#define RSCAN0TMDF01LH RSCAN0.TMDF01.UINT8[LH]
+#define RSCAN0TMDF01H RSCAN0.TMDF01.UINT16[H]
+#define RSCAN0TMDF01HL RSCAN0.TMDF01.UINT8[HL]
+#define RSCAN0TMDF01HH RSCAN0.TMDF01.UINT8[HH]
+#define RSCAN0TMDF11 RSCAN0.TMDF11.UINT32
+#define RSCAN0TMDF11L RSCAN0.TMDF11.UINT16[L]
+#define RSCAN0TMDF11LL RSCAN0.TMDF11.UINT8[LL]
+#define RSCAN0TMDF11LH RSCAN0.TMDF11.UINT8[LH]
+#define RSCAN0TMDF11H RSCAN0.TMDF11.UINT16[H]
+#define RSCAN0TMDF11HL RSCAN0.TMDF11.UINT8[HL]
+#define RSCAN0TMDF11HH RSCAN0.TMDF11.UINT8[HH]
+#define RSCAN0TMID2 RSCAN0.TMID2.UINT32
+#define RSCAN0TMID2L RSCAN0.TMID2.UINT16[L]
+#define RSCAN0TMID2LL RSCAN0.TMID2.UINT8[LL]
+#define RSCAN0TMID2LH RSCAN0.TMID2.UINT8[LH]
+#define RSCAN0TMID2H RSCAN0.TMID2.UINT16[H]
+#define RSCAN0TMID2HL RSCAN0.TMID2.UINT8[HL]
+#define RSCAN0TMID2HH RSCAN0.TMID2.UINT8[HH]
+#define RSCAN0TMPTR2 RSCAN0.TMPTR2.UINT32
+#define RSCAN0TMPTR2L RSCAN0.TMPTR2.UINT16[L]
+#define RSCAN0TMPTR2LL RSCAN0.TMPTR2.UINT8[LL]
+#define RSCAN0TMPTR2LH RSCAN0.TMPTR2.UINT8[LH]
+#define RSCAN0TMPTR2H RSCAN0.TMPTR2.UINT16[H]
+#define RSCAN0TMPTR2HL RSCAN0.TMPTR2.UINT8[HL]
+#define RSCAN0TMPTR2HH RSCAN0.TMPTR2.UINT8[HH]
+#define RSCAN0TMDF02 RSCAN0.TMDF02.UINT32
+#define RSCAN0TMDF02L RSCAN0.TMDF02.UINT16[L]
+#define RSCAN0TMDF02LL RSCAN0.TMDF02.UINT8[LL]
+#define RSCAN0TMDF02LH RSCAN0.TMDF02.UINT8[LH]
+#define RSCAN0TMDF02H RSCAN0.TMDF02.UINT16[H]
+#define RSCAN0TMDF02HL RSCAN0.TMDF02.UINT8[HL]
+#define RSCAN0TMDF02HH RSCAN0.TMDF02.UINT8[HH]
+#define RSCAN0TMDF12 RSCAN0.TMDF12.UINT32
+#define RSCAN0TMDF12L RSCAN0.TMDF12.UINT16[L]
+#define RSCAN0TMDF12LL RSCAN0.TMDF12.UINT8[LL]
+#define RSCAN0TMDF12LH RSCAN0.TMDF12.UINT8[LH]
+#define RSCAN0TMDF12H RSCAN0.TMDF12.UINT16[H]
+#define RSCAN0TMDF12HL RSCAN0.TMDF12.UINT8[HL]
+#define RSCAN0TMDF12HH RSCAN0.TMDF12.UINT8[HH]
+#define RSCAN0TMID3 RSCAN0.TMID3.UINT32
+#define RSCAN0TMID3L RSCAN0.TMID3.UINT16[L]
+#define RSCAN0TMID3LL RSCAN0.TMID3.UINT8[LL]
+#define RSCAN0TMID3LH RSCAN0.TMID3.UINT8[LH]
+#define RSCAN0TMID3H RSCAN0.TMID3.UINT16[H]
+#define RSCAN0TMID3HL RSCAN0.TMID3.UINT8[HL]
+#define RSCAN0TMID3HH RSCAN0.TMID3.UINT8[HH]
+#define RSCAN0TMPTR3 RSCAN0.TMPTR3.UINT32
+#define RSCAN0TMPTR3L RSCAN0.TMPTR3.UINT16[L]
+#define RSCAN0TMPTR3LL RSCAN0.TMPTR3.UINT8[LL]
+#define RSCAN0TMPTR3LH RSCAN0.TMPTR3.UINT8[LH]
+#define RSCAN0TMPTR3H RSCAN0.TMPTR3.UINT16[H]
+#define RSCAN0TMPTR3HL RSCAN0.TMPTR3.UINT8[HL]
+#define RSCAN0TMPTR3HH RSCAN0.TMPTR3.UINT8[HH]
+#define RSCAN0TMDF03 RSCAN0.TMDF03.UINT32
+#define RSCAN0TMDF03L RSCAN0.TMDF03.UINT16[L]
+#define RSCAN0TMDF03LL RSCAN0.TMDF03.UINT8[LL]
+#define RSCAN0TMDF03LH RSCAN0.TMDF03.UINT8[LH]
+#define RSCAN0TMDF03H RSCAN0.TMDF03.UINT16[H]
+#define RSCAN0TMDF03HL RSCAN0.TMDF03.UINT8[HL]
+#define RSCAN0TMDF03HH RSCAN0.TMDF03.UINT8[HH]
+#define RSCAN0TMDF13 RSCAN0.TMDF13.UINT32
+#define RSCAN0TMDF13L RSCAN0.TMDF13.UINT16[L]
+#define RSCAN0TMDF13LL RSCAN0.TMDF13.UINT8[LL]
+#define RSCAN0TMDF13LH RSCAN0.TMDF13.UINT8[LH]
+#define RSCAN0TMDF13H RSCAN0.TMDF13.UINT16[H]
+#define RSCAN0TMDF13HL RSCAN0.TMDF13.UINT8[HL]
+#define RSCAN0TMDF13HH RSCAN0.TMDF13.UINT8[HH]
+#define RSCAN0TMID4 RSCAN0.TMID4.UINT32
+#define RSCAN0TMID4L RSCAN0.TMID4.UINT16[L]
+#define RSCAN0TMID4LL RSCAN0.TMID4.UINT8[LL]
+#define RSCAN0TMID4LH RSCAN0.TMID4.UINT8[LH]
+#define RSCAN0TMID4H RSCAN0.TMID4.UINT16[H]
+#define RSCAN0TMID4HL RSCAN0.TMID4.UINT8[HL]
+#define RSCAN0TMID4HH RSCAN0.TMID4.UINT8[HH]
+#define RSCAN0TMPTR4 RSCAN0.TMPTR4.UINT32
+#define RSCAN0TMPTR4L RSCAN0.TMPTR4.UINT16[L]
+#define RSCAN0TMPTR4LL RSCAN0.TMPTR4.UINT8[LL]
+#define RSCAN0TMPTR4LH RSCAN0.TMPTR4.UINT8[LH]
+#define RSCAN0TMPTR4H RSCAN0.TMPTR4.UINT16[H]
+#define RSCAN0TMPTR4HL RSCAN0.TMPTR4.UINT8[HL]
+#define RSCAN0TMPTR4HH RSCAN0.TMPTR4.UINT8[HH]
+#define RSCAN0TMDF04 RSCAN0.TMDF04.UINT32
+#define RSCAN0TMDF04L RSCAN0.TMDF04.UINT16[L]
+#define RSCAN0TMDF04LL RSCAN0.TMDF04.UINT8[LL]
+#define RSCAN0TMDF04LH RSCAN0.TMDF04.UINT8[LH]
+#define RSCAN0TMDF04H RSCAN0.TMDF04.UINT16[H]
+#define RSCAN0TMDF04HL RSCAN0.TMDF04.UINT8[HL]
+#define RSCAN0TMDF04HH RSCAN0.TMDF04.UINT8[HH]
+#define RSCAN0TMDF14 RSCAN0.TMDF14.UINT32
+#define RSCAN0TMDF14L RSCAN0.TMDF14.UINT16[L]
+#define RSCAN0TMDF14LL RSCAN0.TMDF14.UINT8[LL]
+#define RSCAN0TMDF14LH RSCAN0.TMDF14.UINT8[LH]
+#define RSCAN0TMDF14H RSCAN0.TMDF14.UINT16[H]
+#define RSCAN0TMDF14HL RSCAN0.TMDF14.UINT8[HL]
+#define RSCAN0TMDF14HH RSCAN0.TMDF14.UINT8[HH]
+#define RSCAN0TMID5 RSCAN0.TMID5.UINT32
+#define RSCAN0TMID5L RSCAN0.TMID5.UINT16[L]
+#define RSCAN0TMID5LL RSCAN0.TMID5.UINT8[LL]
+#define RSCAN0TMID5LH RSCAN0.TMID5.UINT8[LH]
+#define RSCAN0TMID5H RSCAN0.TMID5.UINT16[H]
+#define RSCAN0TMID5HL RSCAN0.TMID5.UINT8[HL]
+#define RSCAN0TMID5HH RSCAN0.TMID5.UINT8[HH]
+#define RSCAN0TMPTR5 RSCAN0.TMPTR5.UINT32
+#define RSCAN0TMPTR5L RSCAN0.TMPTR5.UINT16[L]
+#define RSCAN0TMPTR5LL RSCAN0.TMPTR5.UINT8[LL]
+#define RSCAN0TMPTR5LH RSCAN0.TMPTR5.UINT8[LH]
+#define RSCAN0TMPTR5H RSCAN0.TMPTR5.UINT16[H]
+#define RSCAN0TMPTR5HL RSCAN0.TMPTR5.UINT8[HL]
+#define RSCAN0TMPTR5HH RSCAN0.TMPTR5.UINT8[HH]
+#define RSCAN0TMDF05 RSCAN0.TMDF05.UINT32
+#define RSCAN0TMDF05L RSCAN0.TMDF05.UINT16[L]
+#define RSCAN0TMDF05LL RSCAN0.TMDF05.UINT8[LL]
+#define RSCAN0TMDF05LH RSCAN0.TMDF05.UINT8[LH]
+#define RSCAN0TMDF05H RSCAN0.TMDF05.UINT16[H]
+#define RSCAN0TMDF05HL RSCAN0.TMDF05.UINT8[HL]
+#define RSCAN0TMDF05HH RSCAN0.TMDF05.UINT8[HH]
+#define RSCAN0TMDF15 RSCAN0.TMDF15.UINT32
+#define RSCAN0TMDF15L RSCAN0.TMDF15.UINT16[L]
+#define RSCAN0TMDF15LL RSCAN0.TMDF15.UINT8[LL]
+#define RSCAN0TMDF15LH RSCAN0.TMDF15.UINT8[LH]
+#define RSCAN0TMDF15H RSCAN0.TMDF15.UINT16[H]
+#define RSCAN0TMDF15HL RSCAN0.TMDF15.UINT8[HL]
+#define RSCAN0TMDF15HH RSCAN0.TMDF15.UINT8[HH]
+#define RSCAN0TMID6 RSCAN0.TMID6.UINT32
+#define RSCAN0TMID6L RSCAN0.TMID6.UINT16[L]
+#define RSCAN0TMID6LL RSCAN0.TMID6.UINT8[LL]
+#define RSCAN0TMID6LH RSCAN0.TMID6.UINT8[LH]
+#define RSCAN0TMID6H RSCAN0.TMID6.UINT16[H]
+#define RSCAN0TMID6HL RSCAN0.TMID6.UINT8[HL]
+#define RSCAN0TMID6HH RSCAN0.TMID6.UINT8[HH]
+#define RSCAN0TMPTR6 RSCAN0.TMPTR6.UINT32
+#define RSCAN0TMPTR6L RSCAN0.TMPTR6.UINT16[L]
+#define RSCAN0TMPTR6LL RSCAN0.TMPTR6.UINT8[LL]
+#define RSCAN0TMPTR6LH RSCAN0.TMPTR6.UINT8[LH]
+#define RSCAN0TMPTR6H RSCAN0.TMPTR6.UINT16[H]
+#define RSCAN0TMPTR6HL RSCAN0.TMPTR6.UINT8[HL]
+#define RSCAN0TMPTR6HH RSCAN0.TMPTR6.UINT8[HH]
+#define RSCAN0TMDF06 RSCAN0.TMDF06.UINT32
+#define RSCAN0TMDF06L RSCAN0.TMDF06.UINT16[L]
+#define RSCAN0TMDF06LL RSCAN0.TMDF06.UINT8[LL]
+#define RSCAN0TMDF06LH RSCAN0.TMDF06.UINT8[LH]
+#define RSCAN0TMDF06H RSCAN0.TMDF06.UINT16[H]
+#define RSCAN0TMDF06HL RSCAN0.TMDF06.UINT8[HL]
+#define RSCAN0TMDF06HH RSCAN0.TMDF06.UINT8[HH]
+#define RSCAN0TMDF16 RSCAN0.TMDF16.UINT32
+#define RSCAN0TMDF16L RSCAN0.TMDF16.UINT16[L]
+#define RSCAN0TMDF16LL RSCAN0.TMDF16.UINT8[LL]
+#define RSCAN0TMDF16LH RSCAN0.TMDF16.UINT8[LH]
+#define RSCAN0TMDF16H RSCAN0.TMDF16.UINT16[H]
+#define RSCAN0TMDF16HL RSCAN0.TMDF16.UINT8[HL]
+#define RSCAN0TMDF16HH RSCAN0.TMDF16.UINT8[HH]
+#define RSCAN0TMID7 RSCAN0.TMID7.UINT32
+#define RSCAN0TMID7L RSCAN0.TMID7.UINT16[L]
+#define RSCAN0TMID7LL RSCAN0.TMID7.UINT8[LL]
+#define RSCAN0TMID7LH RSCAN0.TMID7.UINT8[LH]
+#define RSCAN0TMID7H RSCAN0.TMID7.UINT16[H]
+#define RSCAN0TMID7HL RSCAN0.TMID7.UINT8[HL]
+#define RSCAN0TMID7HH RSCAN0.TMID7.UINT8[HH]
+#define RSCAN0TMPTR7 RSCAN0.TMPTR7.UINT32
+#define RSCAN0TMPTR7L RSCAN0.TMPTR7.UINT16[L]
+#define RSCAN0TMPTR7LL RSCAN0.TMPTR7.UINT8[LL]
+#define RSCAN0TMPTR7LH RSCAN0.TMPTR7.UINT8[LH]
+#define RSCAN0TMPTR7H RSCAN0.TMPTR7.UINT16[H]
+#define RSCAN0TMPTR7HL RSCAN0.TMPTR7.UINT8[HL]
+#define RSCAN0TMPTR7HH RSCAN0.TMPTR7.UINT8[HH]
+#define RSCAN0TMDF07 RSCAN0.TMDF07.UINT32
+#define RSCAN0TMDF07L RSCAN0.TMDF07.UINT16[L]
+#define RSCAN0TMDF07LL RSCAN0.TMDF07.UINT8[LL]
+#define RSCAN0TMDF07LH RSCAN0.TMDF07.UINT8[LH]
+#define RSCAN0TMDF07H RSCAN0.TMDF07.UINT16[H]
+#define RSCAN0TMDF07HL RSCAN0.TMDF07.UINT8[HL]
+#define RSCAN0TMDF07HH RSCAN0.TMDF07.UINT8[HH]
+#define RSCAN0TMDF17 RSCAN0.TMDF17.UINT32
+#define RSCAN0TMDF17L RSCAN0.TMDF17.UINT16[L]
+#define RSCAN0TMDF17LL RSCAN0.TMDF17.UINT8[LL]
+#define RSCAN0TMDF17LH RSCAN0.TMDF17.UINT8[LH]
+#define RSCAN0TMDF17H RSCAN0.TMDF17.UINT16[H]
+#define RSCAN0TMDF17HL RSCAN0.TMDF17.UINT8[HL]
+#define RSCAN0TMDF17HH RSCAN0.TMDF17.UINT8[HH]
+#define RSCAN0TMID8 RSCAN0.TMID8.UINT32
+#define RSCAN0TMID8L RSCAN0.TMID8.UINT16[L]
+#define RSCAN0TMID8LL RSCAN0.TMID8.UINT8[LL]
+#define RSCAN0TMID8LH RSCAN0.TMID8.UINT8[LH]
+#define RSCAN0TMID8H RSCAN0.TMID8.UINT16[H]
+#define RSCAN0TMID8HL RSCAN0.TMID8.UINT8[HL]
+#define RSCAN0TMID8HH RSCAN0.TMID8.UINT8[HH]
+#define RSCAN0TMPTR8 RSCAN0.TMPTR8.UINT32
+#define RSCAN0TMPTR8L RSCAN0.TMPTR8.UINT16[L]
+#define RSCAN0TMPTR8LL RSCAN0.TMPTR8.UINT8[LL]
+#define RSCAN0TMPTR8LH RSCAN0.TMPTR8.UINT8[LH]
+#define RSCAN0TMPTR8H RSCAN0.TMPTR8.UINT16[H]
+#define RSCAN0TMPTR8HL RSCAN0.TMPTR8.UINT8[HL]
+#define RSCAN0TMPTR8HH RSCAN0.TMPTR8.UINT8[HH]
+#define RSCAN0TMDF08 RSCAN0.TMDF08.UINT32
+#define RSCAN0TMDF08L RSCAN0.TMDF08.UINT16[L]
+#define RSCAN0TMDF08LL RSCAN0.TMDF08.UINT8[LL]
+#define RSCAN0TMDF08LH RSCAN0.TMDF08.UINT8[LH]
+#define RSCAN0TMDF08H RSCAN0.TMDF08.UINT16[H]
+#define RSCAN0TMDF08HL RSCAN0.TMDF08.UINT8[HL]
+#define RSCAN0TMDF08HH RSCAN0.TMDF08.UINT8[HH]
+#define RSCAN0TMDF18 RSCAN0.TMDF18.UINT32
+#define RSCAN0TMDF18L RSCAN0.TMDF18.UINT16[L]
+#define RSCAN0TMDF18LL RSCAN0.TMDF18.UINT8[LL]
+#define RSCAN0TMDF18LH RSCAN0.TMDF18.UINT8[LH]
+#define RSCAN0TMDF18H RSCAN0.TMDF18.UINT16[H]
+#define RSCAN0TMDF18HL RSCAN0.TMDF18.UINT8[HL]
+#define RSCAN0TMDF18HH RSCAN0.TMDF18.UINT8[HH]
+#define RSCAN0TMID9 RSCAN0.TMID9.UINT32
+#define RSCAN0TMID9L RSCAN0.TMID9.UINT16[L]
+#define RSCAN0TMID9LL RSCAN0.TMID9.UINT8[LL]
+#define RSCAN0TMID9LH RSCAN0.TMID9.UINT8[LH]
+#define RSCAN0TMID9H RSCAN0.TMID9.UINT16[H]
+#define RSCAN0TMID9HL RSCAN0.TMID9.UINT8[HL]
+#define RSCAN0TMID9HH RSCAN0.TMID9.UINT8[HH]
+#define RSCAN0TMPTR9 RSCAN0.TMPTR9.UINT32
+#define RSCAN0TMPTR9L RSCAN0.TMPTR9.UINT16[L]
+#define RSCAN0TMPTR9LL RSCAN0.TMPTR9.UINT8[LL]
+#define RSCAN0TMPTR9LH RSCAN0.TMPTR9.UINT8[LH]
+#define RSCAN0TMPTR9H RSCAN0.TMPTR9.UINT16[H]
+#define RSCAN0TMPTR9HL RSCAN0.TMPTR9.UINT8[HL]
+#define RSCAN0TMPTR9HH RSCAN0.TMPTR9.UINT8[HH]
+#define RSCAN0TMDF09 RSCAN0.TMDF09.UINT32
+#define RSCAN0TMDF09L RSCAN0.TMDF09.UINT16[L]
+#define RSCAN0TMDF09LL RSCAN0.TMDF09.UINT8[LL]
+#define RSCAN0TMDF09LH RSCAN0.TMDF09.UINT8[LH]
+#define RSCAN0TMDF09H RSCAN0.TMDF09.UINT16[H]
+#define RSCAN0TMDF09HL RSCAN0.TMDF09.UINT8[HL]
+#define RSCAN0TMDF09HH RSCAN0.TMDF09.UINT8[HH]
+#define RSCAN0TMDF19 RSCAN0.TMDF19.UINT32
+#define RSCAN0TMDF19L RSCAN0.TMDF19.UINT16[L]
+#define RSCAN0TMDF19LL RSCAN0.TMDF19.UINT8[LL]
+#define RSCAN0TMDF19LH RSCAN0.TMDF19.UINT8[LH]
+#define RSCAN0TMDF19H RSCAN0.TMDF19.UINT16[H]
+#define RSCAN0TMDF19HL RSCAN0.TMDF19.UINT8[HL]
+#define RSCAN0TMDF19HH RSCAN0.TMDF19.UINT8[HH]
+#define RSCAN0TMID10 RSCAN0.TMID10.UINT32
+#define RSCAN0TMID10L RSCAN0.TMID10.UINT16[L]
+#define RSCAN0TMID10LL RSCAN0.TMID10.UINT8[LL]
+#define RSCAN0TMID10LH RSCAN0.TMID10.UINT8[LH]
+#define RSCAN0TMID10H RSCAN0.TMID10.UINT16[H]
+#define RSCAN0TMID10HL RSCAN0.TMID10.UINT8[HL]
+#define RSCAN0TMID10HH RSCAN0.TMID10.UINT8[HH]
+#define RSCAN0TMPTR10 RSCAN0.TMPTR10.UINT32
+#define RSCAN0TMPTR10L RSCAN0.TMPTR10.UINT16[L]
+#define RSCAN0TMPTR10LL RSCAN0.TMPTR10.UINT8[LL]
+#define RSCAN0TMPTR10LH RSCAN0.TMPTR10.UINT8[LH]
+#define RSCAN0TMPTR10H RSCAN0.TMPTR10.UINT16[H]
+#define RSCAN0TMPTR10HL RSCAN0.TMPTR10.UINT8[HL]
+#define RSCAN0TMPTR10HH RSCAN0.TMPTR10.UINT8[HH]
+#define RSCAN0TMDF010 RSCAN0.TMDF010.UINT32
+#define RSCAN0TMDF010L RSCAN0.TMDF010.UINT16[L]
+#define RSCAN0TMDF010LL RSCAN0.TMDF010.UINT8[LL]
+#define RSCAN0TMDF010LH RSCAN0.TMDF010.UINT8[LH]
+#define RSCAN0TMDF010H RSCAN0.TMDF010.UINT16[H]
+#define RSCAN0TMDF010HL RSCAN0.TMDF010.UINT8[HL]
+#define RSCAN0TMDF010HH RSCAN0.TMDF010.UINT8[HH]
+#define RSCAN0TMDF110 RSCAN0.TMDF110.UINT32
+#define RSCAN0TMDF110L RSCAN0.TMDF110.UINT16[L]
+#define RSCAN0TMDF110LL RSCAN0.TMDF110.UINT8[LL]
+#define RSCAN0TMDF110LH RSCAN0.TMDF110.UINT8[LH]
+#define RSCAN0TMDF110H RSCAN0.TMDF110.UINT16[H]
+#define RSCAN0TMDF110HL RSCAN0.TMDF110.UINT8[HL]
+#define RSCAN0TMDF110HH RSCAN0.TMDF110.UINT8[HH]
+#define RSCAN0TMID11 RSCAN0.TMID11.UINT32
+#define RSCAN0TMID11L RSCAN0.TMID11.UINT16[L]
+#define RSCAN0TMID11LL RSCAN0.TMID11.UINT8[LL]
+#define RSCAN0TMID11LH RSCAN0.TMID11.UINT8[LH]
+#define RSCAN0TMID11H RSCAN0.TMID11.UINT16[H]
+#define RSCAN0TMID11HL RSCAN0.TMID11.UINT8[HL]
+#define RSCAN0TMID11HH RSCAN0.TMID11.UINT8[HH]
+#define RSCAN0TMPTR11 RSCAN0.TMPTR11.UINT32
+#define RSCAN0TMPTR11L RSCAN0.TMPTR11.UINT16[L]
+#define RSCAN0TMPTR11LL RSCAN0.TMPTR11.UINT8[LL]
+#define RSCAN0TMPTR11LH RSCAN0.TMPTR11.UINT8[LH]
+#define RSCAN0TMPTR11H RSCAN0.TMPTR11.UINT16[H]
+#define RSCAN0TMPTR11HL RSCAN0.TMPTR11.UINT8[HL]
+#define RSCAN0TMPTR11HH RSCAN0.TMPTR11.UINT8[HH]
+#define RSCAN0TMDF011 RSCAN0.TMDF011.UINT32
+#define RSCAN0TMDF011L RSCAN0.TMDF011.UINT16[L]
+#define RSCAN0TMDF011LL RSCAN0.TMDF011.UINT8[LL]
+#define RSCAN0TMDF011LH RSCAN0.TMDF011.UINT8[LH]
+#define RSCAN0TMDF011H RSCAN0.TMDF011.UINT16[H]
+#define RSCAN0TMDF011HL RSCAN0.TMDF011.UINT8[HL]
+#define RSCAN0TMDF011HH RSCAN0.TMDF011.UINT8[HH]
+#define RSCAN0TMDF111 RSCAN0.TMDF111.UINT32
+#define RSCAN0TMDF111L RSCAN0.TMDF111.UINT16[L]
+#define RSCAN0TMDF111LL RSCAN0.TMDF111.UINT8[LL]
+#define RSCAN0TMDF111LH RSCAN0.TMDF111.UINT8[LH]
+#define RSCAN0TMDF111H RSCAN0.TMDF111.UINT16[H]
+#define RSCAN0TMDF111HL RSCAN0.TMDF111.UINT8[HL]
+#define RSCAN0TMDF111HH RSCAN0.TMDF111.UINT8[HH]
+#define RSCAN0TMID12 RSCAN0.TMID12.UINT32
+#define RSCAN0TMID12L RSCAN0.TMID12.UINT16[L]
+#define RSCAN0TMID12LL RSCAN0.TMID12.UINT8[LL]
+#define RSCAN0TMID12LH RSCAN0.TMID12.UINT8[LH]
+#define RSCAN0TMID12H RSCAN0.TMID12.UINT16[H]
+#define RSCAN0TMID12HL RSCAN0.TMID12.UINT8[HL]
+#define RSCAN0TMID12HH RSCAN0.TMID12.UINT8[HH]
+#define RSCAN0TMPTR12 RSCAN0.TMPTR12.UINT32
+#define RSCAN0TMPTR12L RSCAN0.TMPTR12.UINT16[L]
+#define RSCAN0TMPTR12LL RSCAN0.TMPTR12.UINT8[LL]
+#define RSCAN0TMPTR12LH RSCAN0.TMPTR12.UINT8[LH]
+#define RSCAN0TMPTR12H RSCAN0.TMPTR12.UINT16[H]
+#define RSCAN0TMPTR12HL RSCAN0.TMPTR12.UINT8[HL]
+#define RSCAN0TMPTR12HH RSCAN0.TMPTR12.UINT8[HH]
+#define RSCAN0TMDF012 RSCAN0.TMDF012.UINT32
+#define RSCAN0TMDF012L RSCAN0.TMDF012.UINT16[L]
+#define RSCAN0TMDF012LL RSCAN0.TMDF012.UINT8[LL]
+#define RSCAN0TMDF012LH RSCAN0.TMDF012.UINT8[LH]
+#define RSCAN0TMDF012H RSCAN0.TMDF012.UINT16[H]
+#define RSCAN0TMDF012HL RSCAN0.TMDF012.UINT8[HL]
+#define RSCAN0TMDF012HH RSCAN0.TMDF012.UINT8[HH]
+#define RSCAN0TMDF112 RSCAN0.TMDF112.UINT32
+#define RSCAN0TMDF112L RSCAN0.TMDF112.UINT16[L]
+#define RSCAN0TMDF112LL RSCAN0.TMDF112.UINT8[LL]
+#define RSCAN0TMDF112LH RSCAN0.TMDF112.UINT8[LH]
+#define RSCAN0TMDF112H RSCAN0.TMDF112.UINT16[H]
+#define RSCAN0TMDF112HL RSCAN0.TMDF112.UINT8[HL]
+#define RSCAN0TMDF112HH RSCAN0.TMDF112.UINT8[HH]
+#define RSCAN0TMID13 RSCAN0.TMID13.UINT32
+#define RSCAN0TMID13L RSCAN0.TMID13.UINT16[L]
+#define RSCAN0TMID13LL RSCAN0.TMID13.UINT8[LL]
+#define RSCAN0TMID13LH RSCAN0.TMID13.UINT8[LH]
+#define RSCAN0TMID13H RSCAN0.TMID13.UINT16[H]
+#define RSCAN0TMID13HL RSCAN0.TMID13.UINT8[HL]
+#define RSCAN0TMID13HH RSCAN0.TMID13.UINT8[HH]
+#define RSCAN0TMPTR13 RSCAN0.TMPTR13.UINT32
+#define RSCAN0TMPTR13L RSCAN0.TMPTR13.UINT16[L]
+#define RSCAN0TMPTR13LL RSCAN0.TMPTR13.UINT8[LL]
+#define RSCAN0TMPTR13LH RSCAN0.TMPTR13.UINT8[LH]
+#define RSCAN0TMPTR13H RSCAN0.TMPTR13.UINT16[H]
+#define RSCAN0TMPTR13HL RSCAN0.TMPTR13.UINT8[HL]
+#define RSCAN0TMPTR13HH RSCAN0.TMPTR13.UINT8[HH]
+#define RSCAN0TMDF013 RSCAN0.TMDF013.UINT32
+#define RSCAN0TMDF013L RSCAN0.TMDF013.UINT16[L]
+#define RSCAN0TMDF013LL RSCAN0.TMDF013.UINT8[LL]
+#define RSCAN0TMDF013LH RSCAN0.TMDF013.UINT8[LH]
+#define RSCAN0TMDF013H RSCAN0.TMDF013.UINT16[H]
+#define RSCAN0TMDF013HL RSCAN0.TMDF013.UINT8[HL]
+#define RSCAN0TMDF013HH RSCAN0.TMDF013.UINT8[HH]
+#define RSCAN0TMDF113 RSCAN0.TMDF113.UINT32
+#define RSCAN0TMDF113L RSCAN0.TMDF113.UINT16[L]
+#define RSCAN0TMDF113LL RSCAN0.TMDF113.UINT8[LL]
+#define RSCAN0TMDF113LH RSCAN0.TMDF113.UINT8[LH]
+#define RSCAN0TMDF113H RSCAN0.TMDF113.UINT16[H]
+#define RSCAN0TMDF113HL RSCAN0.TMDF113.UINT8[HL]
+#define RSCAN0TMDF113HH RSCAN0.TMDF113.UINT8[HH]
+#define RSCAN0TMID14 RSCAN0.TMID14.UINT32
+#define RSCAN0TMID14L RSCAN0.TMID14.UINT16[L]
+#define RSCAN0TMID14LL RSCAN0.TMID14.UINT8[LL]
+#define RSCAN0TMID14LH RSCAN0.TMID14.UINT8[LH]
+#define RSCAN0TMID14H RSCAN0.TMID14.UINT16[H]
+#define RSCAN0TMID14HL RSCAN0.TMID14.UINT8[HL]
+#define RSCAN0TMID14HH RSCAN0.TMID14.UINT8[HH]
+#define RSCAN0TMPTR14 RSCAN0.TMPTR14.UINT32
+#define RSCAN0TMPTR14L RSCAN0.TMPTR14.UINT16[L]
+#define RSCAN0TMPTR14LL RSCAN0.TMPTR14.UINT8[LL]
+#define RSCAN0TMPTR14LH RSCAN0.TMPTR14.UINT8[LH]
+#define RSCAN0TMPTR14H RSCAN0.TMPTR14.UINT16[H]
+#define RSCAN0TMPTR14HL RSCAN0.TMPTR14.UINT8[HL]
+#define RSCAN0TMPTR14HH RSCAN0.TMPTR14.UINT8[HH]
+#define RSCAN0TMDF014 RSCAN0.TMDF014.UINT32
+#define RSCAN0TMDF014L RSCAN0.TMDF014.UINT16[L]
+#define RSCAN0TMDF014LL RSCAN0.TMDF014.UINT8[LL]
+#define RSCAN0TMDF014LH RSCAN0.TMDF014.UINT8[LH]
+#define RSCAN0TMDF014H RSCAN0.TMDF014.UINT16[H]
+#define RSCAN0TMDF014HL RSCAN0.TMDF014.UINT8[HL]
+#define RSCAN0TMDF014HH RSCAN0.TMDF014.UINT8[HH]
+#define RSCAN0TMDF114 RSCAN0.TMDF114.UINT32
+#define RSCAN0TMDF114L RSCAN0.TMDF114.UINT16[L]
+#define RSCAN0TMDF114LL RSCAN0.TMDF114.UINT8[LL]
+#define RSCAN0TMDF114LH RSCAN0.TMDF114.UINT8[LH]
+#define RSCAN0TMDF114H RSCAN0.TMDF114.UINT16[H]
+#define RSCAN0TMDF114HL RSCAN0.TMDF114.UINT8[HL]
+#define RSCAN0TMDF114HH RSCAN0.TMDF114.UINT8[HH]
+#define RSCAN0TMID15 RSCAN0.TMID15.UINT32
+#define RSCAN0TMID15L RSCAN0.TMID15.UINT16[L]
+#define RSCAN0TMID15LL RSCAN0.TMID15.UINT8[LL]
+#define RSCAN0TMID15LH RSCAN0.TMID15.UINT8[LH]
+#define RSCAN0TMID15H RSCAN0.TMID15.UINT16[H]
+#define RSCAN0TMID15HL RSCAN0.TMID15.UINT8[HL]
+#define RSCAN0TMID15HH RSCAN0.TMID15.UINT8[HH]
+#define RSCAN0TMPTR15 RSCAN0.TMPTR15.UINT32
+#define RSCAN0TMPTR15L RSCAN0.TMPTR15.UINT16[L]
+#define RSCAN0TMPTR15LL RSCAN0.TMPTR15.UINT8[LL]
+#define RSCAN0TMPTR15LH RSCAN0.TMPTR15.UINT8[LH]
+#define RSCAN0TMPTR15H RSCAN0.TMPTR15.UINT16[H]
+#define RSCAN0TMPTR15HL RSCAN0.TMPTR15.UINT8[HL]
+#define RSCAN0TMPTR15HH RSCAN0.TMPTR15.UINT8[HH]
+#define RSCAN0TMDF015 RSCAN0.TMDF015.UINT32
+#define RSCAN0TMDF015L RSCAN0.TMDF015.UINT16[L]
+#define RSCAN0TMDF015LL RSCAN0.TMDF015.UINT8[LL]
+#define RSCAN0TMDF015LH RSCAN0.TMDF015.UINT8[LH]
+#define RSCAN0TMDF015H RSCAN0.TMDF015.UINT16[H]
+#define RSCAN0TMDF015HL RSCAN0.TMDF015.UINT8[HL]
+#define RSCAN0TMDF015HH RSCAN0.TMDF015.UINT8[HH]
+#define RSCAN0TMDF115 RSCAN0.TMDF115.UINT32
+#define RSCAN0TMDF115L RSCAN0.TMDF115.UINT16[L]
+#define RSCAN0TMDF115LL RSCAN0.TMDF115.UINT8[LL]
+#define RSCAN0TMDF115LH RSCAN0.TMDF115.UINT8[LH]
+#define RSCAN0TMDF115H RSCAN0.TMDF115.UINT16[H]
+#define RSCAN0TMDF115HL RSCAN0.TMDF115.UINT8[HL]
+#define RSCAN0TMDF115HH RSCAN0.TMDF115.UINT8[HH]
+#define RSCAN0TMID16 RSCAN0.TMID16.UINT32
+#define RSCAN0TMID16L RSCAN0.TMID16.UINT16[L]
+#define RSCAN0TMID16LL RSCAN0.TMID16.UINT8[LL]
+#define RSCAN0TMID16LH RSCAN0.TMID16.UINT8[LH]
+#define RSCAN0TMID16H RSCAN0.TMID16.UINT16[H]
+#define RSCAN0TMID16HL RSCAN0.TMID16.UINT8[HL]
+#define RSCAN0TMID16HH RSCAN0.TMID16.UINT8[HH]
+#define RSCAN0TMPTR16 RSCAN0.TMPTR16.UINT32
+#define RSCAN0TMPTR16L RSCAN0.TMPTR16.UINT16[L]
+#define RSCAN0TMPTR16LL RSCAN0.TMPTR16.UINT8[LL]
+#define RSCAN0TMPTR16LH RSCAN0.TMPTR16.UINT8[LH]
+#define RSCAN0TMPTR16H RSCAN0.TMPTR16.UINT16[H]
+#define RSCAN0TMPTR16HL RSCAN0.TMPTR16.UINT8[HL]
+#define RSCAN0TMPTR16HH RSCAN0.TMPTR16.UINT8[HH]
+#define RSCAN0TMDF016 RSCAN0.TMDF016.UINT32
+#define RSCAN0TMDF016L RSCAN0.TMDF016.UINT16[L]
+#define RSCAN0TMDF016LL RSCAN0.TMDF016.UINT8[LL]
+#define RSCAN0TMDF016LH RSCAN0.TMDF016.UINT8[LH]
+#define RSCAN0TMDF016H RSCAN0.TMDF016.UINT16[H]
+#define RSCAN0TMDF016HL RSCAN0.TMDF016.UINT8[HL]
+#define RSCAN0TMDF016HH RSCAN0.TMDF016.UINT8[HH]
+#define RSCAN0TMDF116 RSCAN0.TMDF116.UINT32
+#define RSCAN0TMDF116L RSCAN0.TMDF116.UINT16[L]
+#define RSCAN0TMDF116LL RSCAN0.TMDF116.UINT8[LL]
+#define RSCAN0TMDF116LH RSCAN0.TMDF116.UINT8[LH]
+#define RSCAN0TMDF116H RSCAN0.TMDF116.UINT16[H]
+#define RSCAN0TMDF116HL RSCAN0.TMDF116.UINT8[HL]
+#define RSCAN0TMDF116HH RSCAN0.TMDF116.UINT8[HH]
+#define RSCAN0TMID17 RSCAN0.TMID17.UINT32
+#define RSCAN0TMID17L RSCAN0.TMID17.UINT16[L]
+#define RSCAN0TMID17LL RSCAN0.TMID17.UINT8[LL]
+#define RSCAN0TMID17LH RSCAN0.TMID17.UINT8[LH]
+#define RSCAN0TMID17H RSCAN0.TMID17.UINT16[H]
+#define RSCAN0TMID17HL RSCAN0.TMID17.UINT8[HL]
+#define RSCAN0TMID17HH RSCAN0.TMID17.UINT8[HH]
+#define RSCAN0TMPTR17 RSCAN0.TMPTR17.UINT32
+#define RSCAN0TMPTR17L RSCAN0.TMPTR17.UINT16[L]
+#define RSCAN0TMPTR17LL RSCAN0.TMPTR17.UINT8[LL]
+#define RSCAN0TMPTR17LH RSCAN0.TMPTR17.UINT8[LH]
+#define RSCAN0TMPTR17H RSCAN0.TMPTR17.UINT16[H]
+#define RSCAN0TMPTR17HL RSCAN0.TMPTR17.UINT8[HL]
+#define RSCAN0TMPTR17HH RSCAN0.TMPTR17.UINT8[HH]
+#define RSCAN0TMDF017 RSCAN0.TMDF017.UINT32
+#define RSCAN0TMDF017L RSCAN0.TMDF017.UINT16[L]
+#define RSCAN0TMDF017LL RSCAN0.TMDF017.UINT8[LL]
+#define RSCAN0TMDF017LH RSCAN0.TMDF017.UINT8[LH]
+#define RSCAN0TMDF017H RSCAN0.TMDF017.UINT16[H]
+#define RSCAN0TMDF017HL RSCAN0.TMDF017.UINT8[HL]
+#define RSCAN0TMDF017HH RSCAN0.TMDF017.UINT8[HH]
+#define RSCAN0TMDF117 RSCAN0.TMDF117.UINT32
+#define RSCAN0TMDF117L RSCAN0.TMDF117.UINT16[L]
+#define RSCAN0TMDF117LL RSCAN0.TMDF117.UINT8[LL]
+#define RSCAN0TMDF117LH RSCAN0.TMDF117.UINT8[LH]
+#define RSCAN0TMDF117H RSCAN0.TMDF117.UINT16[H]
+#define RSCAN0TMDF117HL RSCAN0.TMDF117.UINT8[HL]
+#define RSCAN0TMDF117HH RSCAN0.TMDF117.UINT8[HH]
+#define RSCAN0TMID18 RSCAN0.TMID18.UINT32
+#define RSCAN0TMID18L RSCAN0.TMID18.UINT16[L]
+#define RSCAN0TMID18LL RSCAN0.TMID18.UINT8[LL]
+#define RSCAN0TMID18LH RSCAN0.TMID18.UINT8[LH]
+#define RSCAN0TMID18H RSCAN0.TMID18.UINT16[H]
+#define RSCAN0TMID18HL RSCAN0.TMID18.UINT8[HL]
+#define RSCAN0TMID18HH RSCAN0.TMID18.UINT8[HH]
+#define RSCAN0TMPTR18 RSCAN0.TMPTR18.UINT32
+#define RSCAN0TMPTR18L RSCAN0.TMPTR18.UINT16[L]
+#define RSCAN0TMPTR18LL RSCAN0.TMPTR18.UINT8[LL]
+#define RSCAN0TMPTR18LH RSCAN0.TMPTR18.UINT8[LH]
+#define RSCAN0TMPTR18H RSCAN0.TMPTR18.UINT16[H]
+#define RSCAN0TMPTR18HL RSCAN0.TMPTR18.UINT8[HL]
+#define RSCAN0TMPTR18HH RSCAN0.TMPTR18.UINT8[HH]
+#define RSCAN0TMDF018 RSCAN0.TMDF018.UINT32
+#define RSCAN0TMDF018L RSCAN0.TMDF018.UINT16[L]
+#define RSCAN0TMDF018LL RSCAN0.TMDF018.UINT8[LL]
+#define RSCAN0TMDF018LH RSCAN0.TMDF018.UINT8[LH]
+#define RSCAN0TMDF018H RSCAN0.TMDF018.UINT16[H]
+#define RSCAN0TMDF018HL RSCAN0.TMDF018.UINT8[HL]
+#define RSCAN0TMDF018HH RSCAN0.TMDF018.UINT8[HH]
+#define RSCAN0TMDF118 RSCAN0.TMDF118.UINT32
+#define RSCAN0TMDF118L RSCAN0.TMDF118.UINT16[L]
+#define RSCAN0TMDF118LL RSCAN0.TMDF118.UINT8[LL]
+#define RSCAN0TMDF118LH RSCAN0.TMDF118.UINT8[LH]
+#define RSCAN0TMDF118H RSCAN0.TMDF118.UINT16[H]
+#define RSCAN0TMDF118HL RSCAN0.TMDF118.UINT8[HL]
+#define RSCAN0TMDF118HH RSCAN0.TMDF118.UINT8[HH]
+#define RSCAN0TMID19 RSCAN0.TMID19.UINT32
+#define RSCAN0TMID19L RSCAN0.TMID19.UINT16[L]
+#define RSCAN0TMID19LL RSCAN0.TMID19.UINT8[LL]
+#define RSCAN0TMID19LH RSCAN0.TMID19.UINT8[LH]
+#define RSCAN0TMID19H RSCAN0.TMID19.UINT16[H]
+#define RSCAN0TMID19HL RSCAN0.TMID19.UINT8[HL]
+#define RSCAN0TMID19HH RSCAN0.TMID19.UINT8[HH]
+#define RSCAN0TMPTR19 RSCAN0.TMPTR19.UINT32
+#define RSCAN0TMPTR19L RSCAN0.TMPTR19.UINT16[L]
+#define RSCAN0TMPTR19LL RSCAN0.TMPTR19.UINT8[LL]
+#define RSCAN0TMPTR19LH RSCAN0.TMPTR19.UINT8[LH]
+#define RSCAN0TMPTR19H RSCAN0.TMPTR19.UINT16[H]
+#define RSCAN0TMPTR19HL RSCAN0.TMPTR19.UINT8[HL]
+#define RSCAN0TMPTR19HH RSCAN0.TMPTR19.UINT8[HH]
+#define RSCAN0TMDF019 RSCAN0.TMDF019.UINT32
+#define RSCAN0TMDF019L RSCAN0.TMDF019.UINT16[L]
+#define RSCAN0TMDF019LL RSCAN0.TMDF019.UINT8[LL]
+#define RSCAN0TMDF019LH RSCAN0.TMDF019.UINT8[LH]
+#define RSCAN0TMDF019H RSCAN0.TMDF019.UINT16[H]
+#define RSCAN0TMDF019HL RSCAN0.TMDF019.UINT8[HL]
+#define RSCAN0TMDF019HH RSCAN0.TMDF019.UINT8[HH]
+#define RSCAN0TMDF119 RSCAN0.TMDF119.UINT32
+#define RSCAN0TMDF119L RSCAN0.TMDF119.UINT16[L]
+#define RSCAN0TMDF119LL RSCAN0.TMDF119.UINT8[LL]
+#define RSCAN0TMDF119LH RSCAN0.TMDF119.UINT8[LH]
+#define RSCAN0TMDF119H RSCAN0.TMDF119.UINT16[H]
+#define RSCAN0TMDF119HL RSCAN0.TMDF119.UINT8[HL]
+#define RSCAN0TMDF119HH RSCAN0.TMDF119.UINT8[HH]
+#define RSCAN0TMID20 RSCAN0.TMID20.UINT32
+#define RSCAN0TMID20L RSCAN0.TMID20.UINT16[L]
+#define RSCAN0TMID20LL RSCAN0.TMID20.UINT8[LL]
+#define RSCAN0TMID20LH RSCAN0.TMID20.UINT8[LH]
+#define RSCAN0TMID20H RSCAN0.TMID20.UINT16[H]
+#define RSCAN0TMID20HL RSCAN0.TMID20.UINT8[HL]
+#define RSCAN0TMID20HH RSCAN0.TMID20.UINT8[HH]
+#define RSCAN0TMPTR20 RSCAN0.TMPTR20.UINT32
+#define RSCAN0TMPTR20L RSCAN0.TMPTR20.UINT16[L]
+#define RSCAN0TMPTR20LL RSCAN0.TMPTR20.UINT8[LL]
+#define RSCAN0TMPTR20LH RSCAN0.TMPTR20.UINT8[LH]
+#define RSCAN0TMPTR20H RSCAN0.TMPTR20.UINT16[H]
+#define RSCAN0TMPTR20HL RSCAN0.TMPTR20.UINT8[HL]
+#define RSCAN0TMPTR20HH RSCAN0.TMPTR20.UINT8[HH]
+#define RSCAN0TMDF020 RSCAN0.TMDF020.UINT32
+#define RSCAN0TMDF020L RSCAN0.TMDF020.UINT16[L]
+#define RSCAN0TMDF020LL RSCAN0.TMDF020.UINT8[LL]
+#define RSCAN0TMDF020LH RSCAN0.TMDF020.UINT8[LH]
+#define RSCAN0TMDF020H RSCAN0.TMDF020.UINT16[H]
+#define RSCAN0TMDF020HL RSCAN0.TMDF020.UINT8[HL]
+#define RSCAN0TMDF020HH RSCAN0.TMDF020.UINT8[HH]
+#define RSCAN0TMDF120 RSCAN0.TMDF120.UINT32
+#define RSCAN0TMDF120L RSCAN0.TMDF120.UINT16[L]
+#define RSCAN0TMDF120LL RSCAN0.TMDF120.UINT8[LL]
+#define RSCAN0TMDF120LH RSCAN0.TMDF120.UINT8[LH]
+#define RSCAN0TMDF120H RSCAN0.TMDF120.UINT16[H]
+#define RSCAN0TMDF120HL RSCAN0.TMDF120.UINT8[HL]
+#define RSCAN0TMDF120HH RSCAN0.TMDF120.UINT8[HH]
+#define RSCAN0TMID21 RSCAN0.TMID21.UINT32
+#define RSCAN0TMID21L RSCAN0.TMID21.UINT16[L]
+#define RSCAN0TMID21LL RSCAN0.TMID21.UINT8[LL]
+#define RSCAN0TMID21LH RSCAN0.TMID21.UINT8[LH]
+#define RSCAN0TMID21H RSCAN0.TMID21.UINT16[H]
+#define RSCAN0TMID21HL RSCAN0.TMID21.UINT8[HL]
+#define RSCAN0TMID21HH RSCAN0.TMID21.UINT8[HH]
+#define RSCAN0TMPTR21 RSCAN0.TMPTR21.UINT32
+#define RSCAN0TMPTR21L RSCAN0.TMPTR21.UINT16[L]
+#define RSCAN0TMPTR21LL RSCAN0.TMPTR21.UINT8[LL]
+#define RSCAN0TMPTR21LH RSCAN0.TMPTR21.UINT8[LH]
+#define RSCAN0TMPTR21H RSCAN0.TMPTR21.UINT16[H]
+#define RSCAN0TMPTR21HL RSCAN0.TMPTR21.UINT8[HL]
+#define RSCAN0TMPTR21HH RSCAN0.TMPTR21.UINT8[HH]
+#define RSCAN0TMDF021 RSCAN0.TMDF021.UINT32
+#define RSCAN0TMDF021L RSCAN0.TMDF021.UINT16[L]
+#define RSCAN0TMDF021LL RSCAN0.TMDF021.UINT8[LL]
+#define RSCAN0TMDF021LH RSCAN0.TMDF021.UINT8[LH]
+#define RSCAN0TMDF021H RSCAN0.TMDF021.UINT16[H]
+#define RSCAN0TMDF021HL RSCAN0.TMDF021.UINT8[HL]
+#define RSCAN0TMDF021HH RSCAN0.TMDF021.UINT8[HH]
+#define RSCAN0TMDF121 RSCAN0.TMDF121.UINT32
+#define RSCAN0TMDF121L RSCAN0.TMDF121.UINT16[L]
+#define RSCAN0TMDF121LL RSCAN0.TMDF121.UINT8[LL]
+#define RSCAN0TMDF121LH RSCAN0.TMDF121.UINT8[LH]
+#define RSCAN0TMDF121H RSCAN0.TMDF121.UINT16[H]
+#define RSCAN0TMDF121HL RSCAN0.TMDF121.UINT8[HL]
+#define RSCAN0TMDF121HH RSCAN0.TMDF121.UINT8[HH]
+#define RSCAN0TMID22 RSCAN0.TMID22.UINT32
+#define RSCAN0TMID22L RSCAN0.TMID22.UINT16[L]
+#define RSCAN0TMID22LL RSCAN0.TMID22.UINT8[LL]
+#define RSCAN0TMID22LH RSCAN0.TMID22.UINT8[LH]
+#define RSCAN0TMID22H RSCAN0.TMID22.UINT16[H]
+#define RSCAN0TMID22HL RSCAN0.TMID22.UINT8[HL]
+#define RSCAN0TMID22HH RSCAN0.TMID22.UINT8[HH]
+#define RSCAN0TMPTR22 RSCAN0.TMPTR22.UINT32
+#define RSCAN0TMPTR22L RSCAN0.TMPTR22.UINT16[L]
+#define RSCAN0TMPTR22LL RSCAN0.TMPTR22.UINT8[LL]
+#define RSCAN0TMPTR22LH RSCAN0.TMPTR22.UINT8[LH]
+#define RSCAN0TMPTR22H RSCAN0.TMPTR22.UINT16[H]
+#define RSCAN0TMPTR22HL RSCAN0.TMPTR22.UINT8[HL]
+#define RSCAN0TMPTR22HH RSCAN0.TMPTR22.UINT8[HH]
+#define RSCAN0TMDF022 RSCAN0.TMDF022.UINT32
+#define RSCAN0TMDF022L RSCAN0.TMDF022.UINT16[L]
+#define RSCAN0TMDF022LL RSCAN0.TMDF022.UINT8[LL]
+#define RSCAN0TMDF022LH RSCAN0.TMDF022.UINT8[LH]
+#define RSCAN0TMDF022H RSCAN0.TMDF022.UINT16[H]
+#define RSCAN0TMDF022HL RSCAN0.TMDF022.UINT8[HL]
+#define RSCAN0TMDF022HH RSCAN0.TMDF022.UINT8[HH]
+#define RSCAN0TMDF122 RSCAN0.TMDF122.UINT32
+#define RSCAN0TMDF122L RSCAN0.TMDF122.UINT16[L]
+#define RSCAN0TMDF122LL RSCAN0.TMDF122.UINT8[LL]
+#define RSCAN0TMDF122LH RSCAN0.TMDF122.UINT8[LH]
+#define RSCAN0TMDF122H RSCAN0.TMDF122.UINT16[H]
+#define RSCAN0TMDF122HL RSCAN0.TMDF122.UINT8[HL]
+#define RSCAN0TMDF122HH RSCAN0.TMDF122.UINT8[HH]
+#define RSCAN0TMID23 RSCAN0.TMID23.UINT32
+#define RSCAN0TMID23L RSCAN0.TMID23.UINT16[L]
+#define RSCAN0TMID23LL RSCAN0.TMID23.UINT8[LL]
+#define RSCAN0TMID23LH RSCAN0.TMID23.UINT8[LH]
+#define RSCAN0TMID23H RSCAN0.TMID23.UINT16[H]
+#define RSCAN0TMID23HL RSCAN0.TMID23.UINT8[HL]
+#define RSCAN0TMID23HH RSCAN0.TMID23.UINT8[HH]
+#define RSCAN0TMPTR23 RSCAN0.TMPTR23.UINT32
+#define RSCAN0TMPTR23L RSCAN0.TMPTR23.UINT16[L]
+#define RSCAN0TMPTR23LL RSCAN0.TMPTR23.UINT8[LL]
+#define RSCAN0TMPTR23LH RSCAN0.TMPTR23.UINT8[LH]
+#define RSCAN0TMPTR23H RSCAN0.TMPTR23.UINT16[H]
+#define RSCAN0TMPTR23HL RSCAN0.TMPTR23.UINT8[HL]
+#define RSCAN0TMPTR23HH RSCAN0.TMPTR23.UINT8[HH]
+#define RSCAN0TMDF023 RSCAN0.TMDF023.UINT32
+#define RSCAN0TMDF023L RSCAN0.TMDF023.UINT16[L]
+#define RSCAN0TMDF023LL RSCAN0.TMDF023.UINT8[LL]
+#define RSCAN0TMDF023LH RSCAN0.TMDF023.UINT8[LH]
+#define RSCAN0TMDF023H RSCAN0.TMDF023.UINT16[H]
+#define RSCAN0TMDF023HL RSCAN0.TMDF023.UINT8[HL]
+#define RSCAN0TMDF023HH RSCAN0.TMDF023.UINT8[HH]
+#define RSCAN0TMDF123 RSCAN0.TMDF123.UINT32
+#define RSCAN0TMDF123L RSCAN0.TMDF123.UINT16[L]
+#define RSCAN0TMDF123LL RSCAN0.TMDF123.UINT8[LL]
+#define RSCAN0TMDF123LH RSCAN0.TMDF123.UINT8[LH]
+#define RSCAN0TMDF123H RSCAN0.TMDF123.UINT16[H]
+#define RSCAN0TMDF123HL RSCAN0.TMDF123.UINT8[HL]
+#define RSCAN0TMDF123HH RSCAN0.TMDF123.UINT8[HH]
+#define RSCAN0TMID24 RSCAN0.TMID24.UINT32
+#define RSCAN0TMID24L RSCAN0.TMID24.UINT16[L]
+#define RSCAN0TMID24LL RSCAN0.TMID24.UINT8[LL]
+#define RSCAN0TMID24LH RSCAN0.TMID24.UINT8[LH]
+#define RSCAN0TMID24H RSCAN0.TMID24.UINT16[H]
+#define RSCAN0TMID24HL RSCAN0.TMID24.UINT8[HL]
+#define RSCAN0TMID24HH RSCAN0.TMID24.UINT8[HH]
+#define RSCAN0TMPTR24 RSCAN0.TMPTR24.UINT32
+#define RSCAN0TMPTR24L RSCAN0.TMPTR24.UINT16[L]
+#define RSCAN0TMPTR24LL RSCAN0.TMPTR24.UINT8[LL]
+#define RSCAN0TMPTR24LH RSCAN0.TMPTR24.UINT8[LH]
+#define RSCAN0TMPTR24H RSCAN0.TMPTR24.UINT16[H]
+#define RSCAN0TMPTR24HL RSCAN0.TMPTR24.UINT8[HL]
+#define RSCAN0TMPTR24HH RSCAN0.TMPTR24.UINT8[HH]
+#define RSCAN0TMDF024 RSCAN0.TMDF024.UINT32
+#define RSCAN0TMDF024L RSCAN0.TMDF024.UINT16[L]
+#define RSCAN0TMDF024LL RSCAN0.TMDF024.UINT8[LL]
+#define RSCAN0TMDF024LH RSCAN0.TMDF024.UINT8[LH]
+#define RSCAN0TMDF024H RSCAN0.TMDF024.UINT16[H]
+#define RSCAN0TMDF024HL RSCAN0.TMDF024.UINT8[HL]
+#define RSCAN0TMDF024HH RSCAN0.TMDF024.UINT8[HH]
+#define RSCAN0TMDF124 RSCAN0.TMDF124.UINT32
+#define RSCAN0TMDF124L RSCAN0.TMDF124.UINT16[L]
+#define RSCAN0TMDF124LL RSCAN0.TMDF124.UINT8[LL]
+#define RSCAN0TMDF124LH RSCAN0.TMDF124.UINT8[LH]
+#define RSCAN0TMDF124H RSCAN0.TMDF124.UINT16[H]
+#define RSCAN0TMDF124HL RSCAN0.TMDF124.UINT8[HL]
+#define RSCAN0TMDF124HH RSCAN0.TMDF124.UINT8[HH]
+#define RSCAN0TMID25 RSCAN0.TMID25.UINT32
+#define RSCAN0TMID25L RSCAN0.TMID25.UINT16[L]
+#define RSCAN0TMID25LL RSCAN0.TMID25.UINT8[LL]
+#define RSCAN0TMID25LH RSCAN0.TMID25.UINT8[LH]
+#define RSCAN0TMID25H RSCAN0.TMID25.UINT16[H]
+#define RSCAN0TMID25HL RSCAN0.TMID25.UINT8[HL]
+#define RSCAN0TMID25HH RSCAN0.TMID25.UINT8[HH]
+#define RSCAN0TMPTR25 RSCAN0.TMPTR25.UINT32
+#define RSCAN0TMPTR25L RSCAN0.TMPTR25.UINT16[L]
+#define RSCAN0TMPTR25LL RSCAN0.TMPTR25.UINT8[LL]
+#define RSCAN0TMPTR25LH RSCAN0.TMPTR25.UINT8[LH]
+#define RSCAN0TMPTR25H RSCAN0.TMPTR25.UINT16[H]
+#define RSCAN0TMPTR25HL RSCAN0.TMPTR25.UINT8[HL]
+#define RSCAN0TMPTR25HH RSCAN0.TMPTR25.UINT8[HH]
+#define RSCAN0TMDF025 RSCAN0.TMDF025.UINT32
+#define RSCAN0TMDF025L RSCAN0.TMDF025.UINT16[L]
+#define RSCAN0TMDF025LL RSCAN0.TMDF025.UINT8[LL]
+#define RSCAN0TMDF025LH RSCAN0.TMDF025.UINT8[LH]
+#define RSCAN0TMDF025H RSCAN0.TMDF025.UINT16[H]
+#define RSCAN0TMDF025HL RSCAN0.TMDF025.UINT8[HL]
+#define RSCAN0TMDF025HH RSCAN0.TMDF025.UINT8[HH]
+#define RSCAN0TMDF125 RSCAN0.TMDF125.UINT32
+#define RSCAN0TMDF125L RSCAN0.TMDF125.UINT16[L]
+#define RSCAN0TMDF125LL RSCAN0.TMDF125.UINT8[LL]
+#define RSCAN0TMDF125LH RSCAN0.TMDF125.UINT8[LH]
+#define RSCAN0TMDF125H RSCAN0.TMDF125.UINT16[H]
+#define RSCAN0TMDF125HL RSCAN0.TMDF125.UINT8[HL]
+#define RSCAN0TMDF125HH RSCAN0.TMDF125.UINT8[HH]
+#define RSCAN0TMID26 RSCAN0.TMID26.UINT32
+#define RSCAN0TMID26L RSCAN0.TMID26.UINT16[L]
+#define RSCAN0TMID26LL RSCAN0.TMID26.UINT8[LL]
+#define RSCAN0TMID26LH RSCAN0.TMID26.UINT8[LH]
+#define RSCAN0TMID26H RSCAN0.TMID26.UINT16[H]
+#define RSCAN0TMID26HL RSCAN0.TMID26.UINT8[HL]
+#define RSCAN0TMID26HH RSCAN0.TMID26.UINT8[HH]
+#define RSCAN0TMPTR26 RSCAN0.TMPTR26.UINT32
+#define RSCAN0TMPTR26L RSCAN0.TMPTR26.UINT16[L]
+#define RSCAN0TMPTR26LL RSCAN0.TMPTR26.UINT8[LL]
+#define RSCAN0TMPTR26LH RSCAN0.TMPTR26.UINT8[LH]
+#define RSCAN0TMPTR26H RSCAN0.TMPTR26.UINT16[H]
+#define RSCAN0TMPTR26HL RSCAN0.TMPTR26.UINT8[HL]
+#define RSCAN0TMPTR26HH RSCAN0.TMPTR26.UINT8[HH]
+#define RSCAN0TMDF026 RSCAN0.TMDF026.UINT32
+#define RSCAN0TMDF026L RSCAN0.TMDF026.UINT16[L]
+#define RSCAN0TMDF026LL RSCAN0.TMDF026.UINT8[LL]
+#define RSCAN0TMDF026LH RSCAN0.TMDF026.UINT8[LH]
+#define RSCAN0TMDF026H RSCAN0.TMDF026.UINT16[H]
+#define RSCAN0TMDF026HL RSCAN0.TMDF026.UINT8[HL]
+#define RSCAN0TMDF026HH RSCAN0.TMDF026.UINT8[HH]
+#define RSCAN0TMDF126 RSCAN0.TMDF126.UINT32
+#define RSCAN0TMDF126L RSCAN0.TMDF126.UINT16[L]
+#define RSCAN0TMDF126LL RSCAN0.TMDF126.UINT8[LL]
+#define RSCAN0TMDF126LH RSCAN0.TMDF126.UINT8[LH]
+#define RSCAN0TMDF126H RSCAN0.TMDF126.UINT16[H]
+#define RSCAN0TMDF126HL RSCAN0.TMDF126.UINT8[HL]
+#define RSCAN0TMDF126HH RSCAN0.TMDF126.UINT8[HH]
+#define RSCAN0TMID27 RSCAN0.TMID27.UINT32
+#define RSCAN0TMID27L RSCAN0.TMID27.UINT16[L]
+#define RSCAN0TMID27LL RSCAN0.TMID27.UINT8[LL]
+#define RSCAN0TMID27LH RSCAN0.TMID27.UINT8[LH]
+#define RSCAN0TMID27H RSCAN0.TMID27.UINT16[H]
+#define RSCAN0TMID27HL RSCAN0.TMID27.UINT8[HL]
+#define RSCAN0TMID27HH RSCAN0.TMID27.UINT8[HH]
+#define RSCAN0TMPTR27 RSCAN0.TMPTR27.UINT32
+#define RSCAN0TMPTR27L RSCAN0.TMPTR27.UINT16[L]
+#define RSCAN0TMPTR27LL RSCAN0.TMPTR27.UINT8[LL]
+#define RSCAN0TMPTR27LH RSCAN0.TMPTR27.UINT8[LH]
+#define RSCAN0TMPTR27H RSCAN0.TMPTR27.UINT16[H]
+#define RSCAN0TMPTR27HL RSCAN0.TMPTR27.UINT8[HL]
+#define RSCAN0TMPTR27HH RSCAN0.TMPTR27.UINT8[HH]
+#define RSCAN0TMDF027 RSCAN0.TMDF027.UINT32
+#define RSCAN0TMDF027L RSCAN0.TMDF027.UINT16[L]
+#define RSCAN0TMDF027LL RSCAN0.TMDF027.UINT8[LL]
+#define RSCAN0TMDF027LH RSCAN0.TMDF027.UINT8[LH]
+#define RSCAN0TMDF027H RSCAN0.TMDF027.UINT16[H]
+#define RSCAN0TMDF027HL RSCAN0.TMDF027.UINT8[HL]
+#define RSCAN0TMDF027HH RSCAN0.TMDF027.UINT8[HH]
+#define RSCAN0TMDF127 RSCAN0.TMDF127.UINT32
+#define RSCAN0TMDF127L RSCAN0.TMDF127.UINT16[L]
+#define RSCAN0TMDF127LL RSCAN0.TMDF127.UINT8[LL]
+#define RSCAN0TMDF127LH RSCAN0.TMDF127.UINT8[LH]
+#define RSCAN0TMDF127H RSCAN0.TMDF127.UINT16[H]
+#define RSCAN0TMDF127HL RSCAN0.TMDF127.UINT8[HL]
+#define RSCAN0TMDF127HH RSCAN0.TMDF127.UINT8[HH]
+#define RSCAN0TMID28 RSCAN0.TMID28.UINT32
+#define RSCAN0TMID28L RSCAN0.TMID28.UINT16[L]
+#define RSCAN0TMID28LL RSCAN0.TMID28.UINT8[LL]
+#define RSCAN0TMID28LH RSCAN0.TMID28.UINT8[LH]
+#define RSCAN0TMID28H RSCAN0.TMID28.UINT16[H]
+#define RSCAN0TMID28HL RSCAN0.TMID28.UINT8[HL]
+#define RSCAN0TMID28HH RSCAN0.TMID28.UINT8[HH]
+#define RSCAN0TMPTR28 RSCAN0.TMPTR28.UINT32
+#define RSCAN0TMPTR28L RSCAN0.TMPTR28.UINT16[L]
+#define RSCAN0TMPTR28LL RSCAN0.TMPTR28.UINT8[LL]
+#define RSCAN0TMPTR28LH RSCAN0.TMPTR28.UINT8[LH]
+#define RSCAN0TMPTR28H RSCAN0.TMPTR28.UINT16[H]
+#define RSCAN0TMPTR28HL RSCAN0.TMPTR28.UINT8[HL]
+#define RSCAN0TMPTR28HH RSCAN0.TMPTR28.UINT8[HH]
+#define RSCAN0TMDF028 RSCAN0.TMDF028.UINT32
+#define RSCAN0TMDF028L RSCAN0.TMDF028.UINT16[L]
+#define RSCAN0TMDF028LL RSCAN0.TMDF028.UINT8[LL]
+#define RSCAN0TMDF028LH RSCAN0.TMDF028.UINT8[LH]
+#define RSCAN0TMDF028H RSCAN0.TMDF028.UINT16[H]
+#define RSCAN0TMDF028HL RSCAN0.TMDF028.UINT8[HL]
+#define RSCAN0TMDF028HH RSCAN0.TMDF028.UINT8[HH]
+#define RSCAN0TMDF128 RSCAN0.TMDF128.UINT32
+#define RSCAN0TMDF128L RSCAN0.TMDF128.UINT16[L]
+#define RSCAN0TMDF128LL RSCAN0.TMDF128.UINT8[LL]
+#define RSCAN0TMDF128LH RSCAN0.TMDF128.UINT8[LH]
+#define RSCAN0TMDF128H RSCAN0.TMDF128.UINT16[H]
+#define RSCAN0TMDF128HL RSCAN0.TMDF128.UINT8[HL]
+#define RSCAN0TMDF128HH RSCAN0.TMDF128.UINT8[HH]
+#define RSCAN0TMID29 RSCAN0.TMID29.UINT32
+#define RSCAN0TMID29L RSCAN0.TMID29.UINT16[L]
+#define RSCAN0TMID29LL RSCAN0.TMID29.UINT8[LL]
+#define RSCAN0TMID29LH RSCAN0.TMID29.UINT8[LH]
+#define RSCAN0TMID29H RSCAN0.TMID29.UINT16[H]
+#define RSCAN0TMID29HL RSCAN0.TMID29.UINT8[HL]
+#define RSCAN0TMID29HH RSCAN0.TMID29.UINT8[HH]
+#define RSCAN0TMPTR29 RSCAN0.TMPTR29.UINT32
+#define RSCAN0TMPTR29L RSCAN0.TMPTR29.UINT16[L]
+#define RSCAN0TMPTR29LL RSCAN0.TMPTR29.UINT8[LL]
+#define RSCAN0TMPTR29LH RSCAN0.TMPTR29.UINT8[LH]
+#define RSCAN0TMPTR29H RSCAN0.TMPTR29.UINT16[H]
+#define RSCAN0TMPTR29HL RSCAN0.TMPTR29.UINT8[HL]
+#define RSCAN0TMPTR29HH RSCAN0.TMPTR29.UINT8[HH]
+#define RSCAN0TMDF029 RSCAN0.TMDF029.UINT32
+#define RSCAN0TMDF029L RSCAN0.TMDF029.UINT16[L]
+#define RSCAN0TMDF029LL RSCAN0.TMDF029.UINT8[LL]
+#define RSCAN0TMDF029LH RSCAN0.TMDF029.UINT8[LH]
+#define RSCAN0TMDF029H RSCAN0.TMDF029.UINT16[H]
+#define RSCAN0TMDF029HL RSCAN0.TMDF029.UINT8[HL]
+#define RSCAN0TMDF029HH RSCAN0.TMDF029.UINT8[HH]
+#define RSCAN0TMDF129 RSCAN0.TMDF129.UINT32
+#define RSCAN0TMDF129L RSCAN0.TMDF129.UINT16[L]
+#define RSCAN0TMDF129LL RSCAN0.TMDF129.UINT8[LL]
+#define RSCAN0TMDF129LH RSCAN0.TMDF129.UINT8[LH]
+#define RSCAN0TMDF129H RSCAN0.TMDF129.UINT16[H]
+#define RSCAN0TMDF129HL RSCAN0.TMDF129.UINT8[HL]
+#define RSCAN0TMDF129HH RSCAN0.TMDF129.UINT8[HH]
+#define RSCAN0TMID30 RSCAN0.TMID30.UINT32
+#define RSCAN0TMID30L RSCAN0.TMID30.UINT16[L]
+#define RSCAN0TMID30LL RSCAN0.TMID30.UINT8[LL]
+#define RSCAN0TMID30LH RSCAN0.TMID30.UINT8[LH]
+#define RSCAN0TMID30H RSCAN0.TMID30.UINT16[H]
+#define RSCAN0TMID30HL RSCAN0.TMID30.UINT8[HL]
+#define RSCAN0TMID30HH RSCAN0.TMID30.UINT8[HH]
+#define RSCAN0TMPTR30 RSCAN0.TMPTR30.UINT32
+#define RSCAN0TMPTR30L RSCAN0.TMPTR30.UINT16[L]
+#define RSCAN0TMPTR30LL RSCAN0.TMPTR30.UINT8[LL]
+#define RSCAN0TMPTR30LH RSCAN0.TMPTR30.UINT8[LH]
+#define RSCAN0TMPTR30H RSCAN0.TMPTR30.UINT16[H]
+#define RSCAN0TMPTR30HL RSCAN0.TMPTR30.UINT8[HL]
+#define RSCAN0TMPTR30HH RSCAN0.TMPTR30.UINT8[HH]
+#define RSCAN0TMDF030 RSCAN0.TMDF030.UINT32
+#define RSCAN0TMDF030L RSCAN0.TMDF030.UINT16[L]
+#define RSCAN0TMDF030LL RSCAN0.TMDF030.UINT8[LL]
+#define RSCAN0TMDF030LH RSCAN0.TMDF030.UINT8[LH]
+#define RSCAN0TMDF030H RSCAN0.TMDF030.UINT16[H]
+#define RSCAN0TMDF030HL RSCAN0.TMDF030.UINT8[HL]
+#define RSCAN0TMDF030HH RSCAN0.TMDF030.UINT8[HH]
+#define RSCAN0TMDF130 RSCAN0.TMDF130.UINT32
+#define RSCAN0TMDF130L RSCAN0.TMDF130.UINT16[L]
+#define RSCAN0TMDF130LL RSCAN0.TMDF130.UINT8[LL]
+#define RSCAN0TMDF130LH RSCAN0.TMDF130.UINT8[LH]
+#define RSCAN0TMDF130H RSCAN0.TMDF130.UINT16[H]
+#define RSCAN0TMDF130HL RSCAN0.TMDF130.UINT8[HL]
+#define RSCAN0TMDF130HH RSCAN0.TMDF130.UINT8[HH]
+#define RSCAN0TMID31 RSCAN0.TMID31.UINT32
+#define RSCAN0TMID31L RSCAN0.TMID31.UINT16[L]
+#define RSCAN0TMID31LL RSCAN0.TMID31.UINT8[LL]
+#define RSCAN0TMID31LH RSCAN0.TMID31.UINT8[LH]
+#define RSCAN0TMID31H RSCAN0.TMID31.UINT16[H]
+#define RSCAN0TMID31HL RSCAN0.TMID31.UINT8[HL]
+#define RSCAN0TMID31HH RSCAN0.TMID31.UINT8[HH]
+#define RSCAN0TMPTR31 RSCAN0.TMPTR31.UINT32
+#define RSCAN0TMPTR31L RSCAN0.TMPTR31.UINT16[L]
+#define RSCAN0TMPTR31LL RSCAN0.TMPTR31.UINT8[LL]
+#define RSCAN0TMPTR31LH RSCAN0.TMPTR31.UINT8[LH]
+#define RSCAN0TMPTR31H RSCAN0.TMPTR31.UINT16[H]
+#define RSCAN0TMPTR31HL RSCAN0.TMPTR31.UINT8[HL]
+#define RSCAN0TMPTR31HH RSCAN0.TMPTR31.UINT8[HH]
+#define RSCAN0TMDF031 RSCAN0.TMDF031.UINT32
+#define RSCAN0TMDF031L RSCAN0.TMDF031.UINT16[L]
+#define RSCAN0TMDF031LL RSCAN0.TMDF031.UINT8[LL]
+#define RSCAN0TMDF031LH RSCAN0.TMDF031.UINT8[LH]
+#define RSCAN0TMDF031H RSCAN0.TMDF031.UINT16[H]
+#define RSCAN0TMDF031HL RSCAN0.TMDF031.UINT8[HL]
+#define RSCAN0TMDF031HH RSCAN0.TMDF031.UINT8[HH]
+#define RSCAN0TMDF131 RSCAN0.TMDF131.UINT32
+#define RSCAN0TMDF131L RSCAN0.TMDF131.UINT16[L]
+#define RSCAN0TMDF131LL RSCAN0.TMDF131.UINT8[LL]
+#define RSCAN0TMDF131LH RSCAN0.TMDF131.UINT8[LH]
+#define RSCAN0TMDF131H RSCAN0.TMDF131.UINT16[H]
+#define RSCAN0TMDF131HL RSCAN0.TMDF131.UINT8[HL]
+#define RSCAN0TMDF131HH RSCAN0.TMDF131.UINT8[HH]
+#define RSCAN0TMID32 RSCAN0.TMID32.UINT32
+#define RSCAN0TMID32L RSCAN0.TMID32.UINT16[L]
+#define RSCAN0TMID32LL RSCAN0.TMID32.UINT8[LL]
+#define RSCAN0TMID32LH RSCAN0.TMID32.UINT8[LH]
+#define RSCAN0TMID32H RSCAN0.TMID32.UINT16[H]
+#define RSCAN0TMID32HL RSCAN0.TMID32.UINT8[HL]
+#define RSCAN0TMID32HH RSCAN0.TMID32.UINT8[HH]
+#define RSCAN0TMPTR32 RSCAN0.TMPTR32.UINT32
+#define RSCAN0TMPTR32L RSCAN0.TMPTR32.UINT16[L]
+#define RSCAN0TMPTR32LL RSCAN0.TMPTR32.UINT8[LL]
+#define RSCAN0TMPTR32LH RSCAN0.TMPTR32.UINT8[LH]
+#define RSCAN0TMPTR32H RSCAN0.TMPTR32.UINT16[H]
+#define RSCAN0TMPTR32HL RSCAN0.TMPTR32.UINT8[HL]
+#define RSCAN0TMPTR32HH RSCAN0.TMPTR32.UINT8[HH]
+#define RSCAN0TMDF032 RSCAN0.TMDF032.UINT32
+#define RSCAN0TMDF032L RSCAN0.TMDF032.UINT16[L]
+#define RSCAN0TMDF032LL RSCAN0.TMDF032.UINT8[LL]
+#define RSCAN0TMDF032LH RSCAN0.TMDF032.UINT8[LH]
+#define RSCAN0TMDF032H RSCAN0.TMDF032.UINT16[H]
+#define RSCAN0TMDF032HL RSCAN0.TMDF032.UINT8[HL]
+#define RSCAN0TMDF032HH RSCAN0.TMDF032.UINT8[HH]
+#define RSCAN0TMDF132 RSCAN0.TMDF132.UINT32
+#define RSCAN0TMDF132L RSCAN0.TMDF132.UINT16[L]
+#define RSCAN0TMDF132LL RSCAN0.TMDF132.UINT8[LL]
+#define RSCAN0TMDF132LH RSCAN0.TMDF132.UINT8[LH]
+#define RSCAN0TMDF132H RSCAN0.TMDF132.UINT16[H]
+#define RSCAN0TMDF132HL RSCAN0.TMDF132.UINT8[HL]
+#define RSCAN0TMDF132HH RSCAN0.TMDF132.UINT8[HH]
+#define RSCAN0TMID33 RSCAN0.TMID33.UINT32
+#define RSCAN0TMID33L RSCAN0.TMID33.UINT16[L]
+#define RSCAN0TMID33LL RSCAN0.TMID33.UINT8[LL]
+#define RSCAN0TMID33LH RSCAN0.TMID33.UINT8[LH]
+#define RSCAN0TMID33H RSCAN0.TMID33.UINT16[H]
+#define RSCAN0TMID33HL RSCAN0.TMID33.UINT8[HL]
+#define RSCAN0TMID33HH RSCAN0.TMID33.UINT8[HH]
+#define RSCAN0TMPTR33 RSCAN0.TMPTR33.UINT32
+#define RSCAN0TMPTR33L RSCAN0.TMPTR33.UINT16[L]
+#define RSCAN0TMPTR33LL RSCAN0.TMPTR33.UINT8[LL]
+#define RSCAN0TMPTR33LH RSCAN0.TMPTR33.UINT8[LH]
+#define RSCAN0TMPTR33H RSCAN0.TMPTR33.UINT16[H]
+#define RSCAN0TMPTR33HL RSCAN0.TMPTR33.UINT8[HL]
+#define RSCAN0TMPTR33HH RSCAN0.TMPTR33.UINT8[HH]
+#define RSCAN0TMDF033 RSCAN0.TMDF033.UINT32
+#define RSCAN0TMDF033L RSCAN0.TMDF033.UINT16[L]
+#define RSCAN0TMDF033LL RSCAN0.TMDF033.UINT8[LL]
+#define RSCAN0TMDF033LH RSCAN0.TMDF033.UINT8[LH]
+#define RSCAN0TMDF033H RSCAN0.TMDF033.UINT16[H]
+#define RSCAN0TMDF033HL RSCAN0.TMDF033.UINT8[HL]
+#define RSCAN0TMDF033HH RSCAN0.TMDF033.UINT8[HH]
+#define RSCAN0TMDF133 RSCAN0.TMDF133.UINT32
+#define RSCAN0TMDF133L RSCAN0.TMDF133.UINT16[L]
+#define RSCAN0TMDF133LL RSCAN0.TMDF133.UINT8[LL]
+#define RSCAN0TMDF133LH RSCAN0.TMDF133.UINT8[LH]
+#define RSCAN0TMDF133H RSCAN0.TMDF133.UINT16[H]
+#define RSCAN0TMDF133HL RSCAN0.TMDF133.UINT8[HL]
+#define RSCAN0TMDF133HH RSCAN0.TMDF133.UINT8[HH]
+#define RSCAN0TMID34 RSCAN0.TMID34.UINT32
+#define RSCAN0TMID34L RSCAN0.TMID34.UINT16[L]
+#define RSCAN0TMID34LL RSCAN0.TMID34.UINT8[LL]
+#define RSCAN0TMID34LH RSCAN0.TMID34.UINT8[LH]
+#define RSCAN0TMID34H RSCAN0.TMID34.UINT16[H]
+#define RSCAN0TMID34HL RSCAN0.TMID34.UINT8[HL]
+#define RSCAN0TMID34HH RSCAN0.TMID34.UINT8[HH]
+#define RSCAN0TMPTR34 RSCAN0.TMPTR34.UINT32
+#define RSCAN0TMPTR34L RSCAN0.TMPTR34.UINT16[L]
+#define RSCAN0TMPTR34LL RSCAN0.TMPTR34.UINT8[LL]
+#define RSCAN0TMPTR34LH RSCAN0.TMPTR34.UINT8[LH]
+#define RSCAN0TMPTR34H RSCAN0.TMPTR34.UINT16[H]
+#define RSCAN0TMPTR34HL RSCAN0.TMPTR34.UINT8[HL]
+#define RSCAN0TMPTR34HH RSCAN0.TMPTR34.UINT8[HH]
+#define RSCAN0TMDF034 RSCAN0.TMDF034.UINT32
+#define RSCAN0TMDF034L RSCAN0.TMDF034.UINT16[L]
+#define RSCAN0TMDF034LL RSCAN0.TMDF034.UINT8[LL]
+#define RSCAN0TMDF034LH RSCAN0.TMDF034.UINT8[LH]
+#define RSCAN0TMDF034H RSCAN0.TMDF034.UINT16[H]
+#define RSCAN0TMDF034HL RSCAN0.TMDF034.UINT8[HL]
+#define RSCAN0TMDF034HH RSCAN0.TMDF034.UINT8[HH]
+#define RSCAN0TMDF134 RSCAN0.TMDF134.UINT32
+#define RSCAN0TMDF134L RSCAN0.TMDF134.UINT16[L]
+#define RSCAN0TMDF134LL RSCAN0.TMDF134.UINT8[LL]
+#define RSCAN0TMDF134LH RSCAN0.TMDF134.UINT8[LH]
+#define RSCAN0TMDF134H RSCAN0.TMDF134.UINT16[H]
+#define RSCAN0TMDF134HL RSCAN0.TMDF134.UINT8[HL]
+#define RSCAN0TMDF134HH RSCAN0.TMDF134.UINT8[HH]
+#define RSCAN0TMID35 RSCAN0.TMID35.UINT32
+#define RSCAN0TMID35L RSCAN0.TMID35.UINT16[L]
+#define RSCAN0TMID35LL RSCAN0.TMID35.UINT8[LL]
+#define RSCAN0TMID35LH RSCAN0.TMID35.UINT8[LH]
+#define RSCAN0TMID35H RSCAN0.TMID35.UINT16[H]
+#define RSCAN0TMID35HL RSCAN0.TMID35.UINT8[HL]
+#define RSCAN0TMID35HH RSCAN0.TMID35.UINT8[HH]
+#define RSCAN0TMPTR35 RSCAN0.TMPTR35.UINT32
+#define RSCAN0TMPTR35L RSCAN0.TMPTR35.UINT16[L]
+#define RSCAN0TMPTR35LL RSCAN0.TMPTR35.UINT8[LL]
+#define RSCAN0TMPTR35LH RSCAN0.TMPTR35.UINT8[LH]
+#define RSCAN0TMPTR35H RSCAN0.TMPTR35.UINT16[H]
+#define RSCAN0TMPTR35HL RSCAN0.TMPTR35.UINT8[HL]
+#define RSCAN0TMPTR35HH RSCAN0.TMPTR35.UINT8[HH]
+#define RSCAN0TMDF035 RSCAN0.TMDF035.UINT32
+#define RSCAN0TMDF035L RSCAN0.TMDF035.UINT16[L]
+#define RSCAN0TMDF035LL RSCAN0.TMDF035.UINT8[LL]
+#define RSCAN0TMDF035LH RSCAN0.TMDF035.UINT8[LH]
+#define RSCAN0TMDF035H RSCAN0.TMDF035.UINT16[H]
+#define RSCAN0TMDF035HL RSCAN0.TMDF035.UINT8[HL]
+#define RSCAN0TMDF035HH RSCAN0.TMDF035.UINT8[HH]
+#define RSCAN0TMDF135 RSCAN0.TMDF135.UINT32
+#define RSCAN0TMDF135L RSCAN0.TMDF135.UINT16[L]
+#define RSCAN0TMDF135LL RSCAN0.TMDF135.UINT8[LL]
+#define RSCAN0TMDF135LH RSCAN0.TMDF135.UINT8[LH]
+#define RSCAN0TMDF135H RSCAN0.TMDF135.UINT16[H]
+#define RSCAN0TMDF135HL RSCAN0.TMDF135.UINT8[HL]
+#define RSCAN0TMDF135HH RSCAN0.TMDF135.UINT8[HH]
+#define RSCAN0TMID36 RSCAN0.TMID36.UINT32
+#define RSCAN0TMID36L RSCAN0.TMID36.UINT16[L]
+#define RSCAN0TMID36LL RSCAN0.TMID36.UINT8[LL]
+#define RSCAN0TMID36LH RSCAN0.TMID36.UINT8[LH]
+#define RSCAN0TMID36H RSCAN0.TMID36.UINT16[H]
+#define RSCAN0TMID36HL RSCAN0.TMID36.UINT8[HL]
+#define RSCAN0TMID36HH RSCAN0.TMID36.UINT8[HH]
+#define RSCAN0TMPTR36 RSCAN0.TMPTR36.UINT32
+#define RSCAN0TMPTR36L RSCAN0.TMPTR36.UINT16[L]
+#define RSCAN0TMPTR36LL RSCAN0.TMPTR36.UINT8[LL]
+#define RSCAN0TMPTR36LH RSCAN0.TMPTR36.UINT8[LH]
+#define RSCAN0TMPTR36H RSCAN0.TMPTR36.UINT16[H]
+#define RSCAN0TMPTR36HL RSCAN0.TMPTR36.UINT8[HL]
+#define RSCAN0TMPTR36HH RSCAN0.TMPTR36.UINT8[HH]
+#define RSCAN0TMDF036 RSCAN0.TMDF036.UINT32
+#define RSCAN0TMDF036L RSCAN0.TMDF036.UINT16[L]
+#define RSCAN0TMDF036LL RSCAN0.TMDF036.UINT8[LL]
+#define RSCAN0TMDF036LH RSCAN0.TMDF036.UINT8[LH]
+#define RSCAN0TMDF036H RSCAN0.TMDF036.UINT16[H]
+#define RSCAN0TMDF036HL RSCAN0.TMDF036.UINT8[HL]
+#define RSCAN0TMDF036HH RSCAN0.TMDF036.UINT8[HH]
+#define RSCAN0TMDF136 RSCAN0.TMDF136.UINT32
+#define RSCAN0TMDF136L RSCAN0.TMDF136.UINT16[L]
+#define RSCAN0TMDF136LL RSCAN0.TMDF136.UINT8[LL]
+#define RSCAN0TMDF136LH RSCAN0.TMDF136.UINT8[LH]
+#define RSCAN0TMDF136H RSCAN0.TMDF136.UINT16[H]
+#define RSCAN0TMDF136HL RSCAN0.TMDF136.UINT8[HL]
+#define RSCAN0TMDF136HH RSCAN0.TMDF136.UINT8[HH]
+#define RSCAN0TMID37 RSCAN0.TMID37.UINT32
+#define RSCAN0TMID37L RSCAN0.TMID37.UINT16[L]
+#define RSCAN0TMID37LL RSCAN0.TMID37.UINT8[LL]
+#define RSCAN0TMID37LH RSCAN0.TMID37.UINT8[LH]
+#define RSCAN0TMID37H RSCAN0.TMID37.UINT16[H]
+#define RSCAN0TMID37HL RSCAN0.TMID37.UINT8[HL]
+#define RSCAN0TMID37HH RSCAN0.TMID37.UINT8[HH]
+#define RSCAN0TMPTR37 RSCAN0.TMPTR37.UINT32
+#define RSCAN0TMPTR37L RSCAN0.TMPTR37.UINT16[L]
+#define RSCAN0TMPTR37LL RSCAN0.TMPTR37.UINT8[LL]
+#define RSCAN0TMPTR37LH RSCAN0.TMPTR37.UINT8[LH]
+#define RSCAN0TMPTR37H RSCAN0.TMPTR37.UINT16[H]
+#define RSCAN0TMPTR37HL RSCAN0.TMPTR37.UINT8[HL]
+#define RSCAN0TMPTR37HH RSCAN0.TMPTR37.UINT8[HH]
+#define RSCAN0TMDF037 RSCAN0.TMDF037.UINT32
+#define RSCAN0TMDF037L RSCAN0.TMDF037.UINT16[L]
+#define RSCAN0TMDF037LL RSCAN0.TMDF037.UINT8[LL]
+#define RSCAN0TMDF037LH RSCAN0.TMDF037.UINT8[LH]
+#define RSCAN0TMDF037H RSCAN0.TMDF037.UINT16[H]
+#define RSCAN0TMDF037HL RSCAN0.TMDF037.UINT8[HL]
+#define RSCAN0TMDF037HH RSCAN0.TMDF037.UINT8[HH]
+#define RSCAN0TMDF137 RSCAN0.TMDF137.UINT32
+#define RSCAN0TMDF137L RSCAN0.TMDF137.UINT16[L]
+#define RSCAN0TMDF137LL RSCAN0.TMDF137.UINT8[LL]
+#define RSCAN0TMDF137LH RSCAN0.TMDF137.UINT8[LH]
+#define RSCAN0TMDF137H RSCAN0.TMDF137.UINT16[H]
+#define RSCAN0TMDF137HL RSCAN0.TMDF137.UINT8[HL]
+#define RSCAN0TMDF137HH RSCAN0.TMDF137.UINT8[HH]
+#define RSCAN0TMID38 RSCAN0.TMID38.UINT32
+#define RSCAN0TMID38L RSCAN0.TMID38.UINT16[L]
+#define RSCAN0TMID38LL RSCAN0.TMID38.UINT8[LL]
+#define RSCAN0TMID38LH RSCAN0.TMID38.UINT8[LH]
+#define RSCAN0TMID38H RSCAN0.TMID38.UINT16[H]
+#define RSCAN0TMID38HL RSCAN0.TMID38.UINT8[HL]
+#define RSCAN0TMID38HH RSCAN0.TMID38.UINT8[HH]
+#define RSCAN0TMPTR38 RSCAN0.TMPTR38.UINT32
+#define RSCAN0TMPTR38L RSCAN0.TMPTR38.UINT16[L]
+#define RSCAN0TMPTR38LL RSCAN0.TMPTR38.UINT8[LL]
+#define RSCAN0TMPTR38LH RSCAN0.TMPTR38.UINT8[LH]
+#define RSCAN0TMPTR38H RSCAN0.TMPTR38.UINT16[H]
+#define RSCAN0TMPTR38HL RSCAN0.TMPTR38.UINT8[HL]
+#define RSCAN0TMPTR38HH RSCAN0.TMPTR38.UINT8[HH]
+#define RSCAN0TMDF038 RSCAN0.TMDF038.UINT32
+#define RSCAN0TMDF038L RSCAN0.TMDF038.UINT16[L]
+#define RSCAN0TMDF038LL RSCAN0.TMDF038.UINT8[LL]
+#define RSCAN0TMDF038LH RSCAN0.TMDF038.UINT8[LH]
+#define RSCAN0TMDF038H RSCAN0.TMDF038.UINT16[H]
+#define RSCAN0TMDF038HL RSCAN0.TMDF038.UINT8[HL]
+#define RSCAN0TMDF038HH RSCAN0.TMDF038.UINT8[HH]
+#define RSCAN0TMDF138 RSCAN0.TMDF138.UINT32
+#define RSCAN0TMDF138L RSCAN0.TMDF138.UINT16[L]
+#define RSCAN0TMDF138LL RSCAN0.TMDF138.UINT8[LL]
+#define RSCAN0TMDF138LH RSCAN0.TMDF138.UINT8[LH]
+#define RSCAN0TMDF138H RSCAN0.TMDF138.UINT16[H]
+#define RSCAN0TMDF138HL RSCAN0.TMDF138.UINT8[HL]
+#define RSCAN0TMDF138HH RSCAN0.TMDF138.UINT8[HH]
+#define RSCAN0TMID39 RSCAN0.TMID39.UINT32
+#define RSCAN0TMID39L RSCAN0.TMID39.UINT16[L]
+#define RSCAN0TMID39LL RSCAN0.TMID39.UINT8[LL]
+#define RSCAN0TMID39LH RSCAN0.TMID39.UINT8[LH]
+#define RSCAN0TMID39H RSCAN0.TMID39.UINT16[H]
+#define RSCAN0TMID39HL RSCAN0.TMID39.UINT8[HL]
+#define RSCAN0TMID39HH RSCAN0.TMID39.UINT8[HH]
+#define RSCAN0TMPTR39 RSCAN0.TMPTR39.UINT32
+#define RSCAN0TMPTR39L RSCAN0.TMPTR39.UINT16[L]
+#define RSCAN0TMPTR39LL RSCAN0.TMPTR39.UINT8[LL]
+#define RSCAN0TMPTR39LH RSCAN0.TMPTR39.UINT8[LH]
+#define RSCAN0TMPTR39H RSCAN0.TMPTR39.UINT16[H]
+#define RSCAN0TMPTR39HL RSCAN0.TMPTR39.UINT8[HL]
+#define RSCAN0TMPTR39HH RSCAN0.TMPTR39.UINT8[HH]
+#define RSCAN0TMDF039 RSCAN0.TMDF039.UINT32
+#define RSCAN0TMDF039L RSCAN0.TMDF039.UINT16[L]
+#define RSCAN0TMDF039LL RSCAN0.TMDF039.UINT8[LL]
+#define RSCAN0TMDF039LH RSCAN0.TMDF039.UINT8[LH]
+#define RSCAN0TMDF039H RSCAN0.TMDF039.UINT16[H]
+#define RSCAN0TMDF039HL RSCAN0.TMDF039.UINT8[HL]
+#define RSCAN0TMDF039HH RSCAN0.TMDF039.UINT8[HH]
+#define RSCAN0TMDF139 RSCAN0.TMDF139.UINT32
+#define RSCAN0TMDF139L RSCAN0.TMDF139.UINT16[L]
+#define RSCAN0TMDF139LL RSCAN0.TMDF139.UINT8[LL]
+#define RSCAN0TMDF139LH RSCAN0.TMDF139.UINT8[LH]
+#define RSCAN0TMDF139H RSCAN0.TMDF139.UINT16[H]
+#define RSCAN0TMDF139HL RSCAN0.TMDF139.UINT8[HL]
+#define RSCAN0TMDF139HH RSCAN0.TMDF139.UINT8[HH]
+#define RSCAN0TMID40 RSCAN0.TMID40.UINT32
+#define RSCAN0TMID40L RSCAN0.TMID40.UINT16[L]
+#define RSCAN0TMID40LL RSCAN0.TMID40.UINT8[LL]
+#define RSCAN0TMID40LH RSCAN0.TMID40.UINT8[LH]
+#define RSCAN0TMID40H RSCAN0.TMID40.UINT16[H]
+#define RSCAN0TMID40HL RSCAN0.TMID40.UINT8[HL]
+#define RSCAN0TMID40HH RSCAN0.TMID40.UINT8[HH]
+#define RSCAN0TMPTR40 RSCAN0.TMPTR40.UINT32
+#define RSCAN0TMPTR40L RSCAN0.TMPTR40.UINT16[L]
+#define RSCAN0TMPTR40LL RSCAN0.TMPTR40.UINT8[LL]
+#define RSCAN0TMPTR40LH RSCAN0.TMPTR40.UINT8[LH]
+#define RSCAN0TMPTR40H RSCAN0.TMPTR40.UINT16[H]
+#define RSCAN0TMPTR40HL RSCAN0.TMPTR40.UINT8[HL]
+#define RSCAN0TMPTR40HH RSCAN0.TMPTR40.UINT8[HH]
+#define RSCAN0TMDF040 RSCAN0.TMDF040.UINT32
+#define RSCAN0TMDF040L RSCAN0.TMDF040.UINT16[L]
+#define RSCAN0TMDF040LL RSCAN0.TMDF040.UINT8[LL]
+#define RSCAN0TMDF040LH RSCAN0.TMDF040.UINT8[LH]
+#define RSCAN0TMDF040H RSCAN0.TMDF040.UINT16[H]
+#define RSCAN0TMDF040HL RSCAN0.TMDF040.UINT8[HL]
+#define RSCAN0TMDF040HH RSCAN0.TMDF040.UINT8[HH]
+#define RSCAN0TMDF140 RSCAN0.TMDF140.UINT32
+#define RSCAN0TMDF140L RSCAN0.TMDF140.UINT16[L]
+#define RSCAN0TMDF140LL RSCAN0.TMDF140.UINT8[LL]
+#define RSCAN0TMDF140LH RSCAN0.TMDF140.UINT8[LH]
+#define RSCAN0TMDF140H RSCAN0.TMDF140.UINT16[H]
+#define RSCAN0TMDF140HL RSCAN0.TMDF140.UINT8[HL]
+#define RSCAN0TMDF140HH RSCAN0.TMDF140.UINT8[HH]
+#define RSCAN0TMID41 RSCAN0.TMID41.UINT32
+#define RSCAN0TMID41L RSCAN0.TMID41.UINT16[L]
+#define RSCAN0TMID41LL RSCAN0.TMID41.UINT8[LL]
+#define RSCAN0TMID41LH RSCAN0.TMID41.UINT8[LH]
+#define RSCAN0TMID41H RSCAN0.TMID41.UINT16[H]
+#define RSCAN0TMID41HL RSCAN0.TMID41.UINT8[HL]
+#define RSCAN0TMID41HH RSCAN0.TMID41.UINT8[HH]
+#define RSCAN0TMPTR41 RSCAN0.TMPTR41.UINT32
+#define RSCAN0TMPTR41L RSCAN0.TMPTR41.UINT16[L]
+#define RSCAN0TMPTR41LL RSCAN0.TMPTR41.UINT8[LL]
+#define RSCAN0TMPTR41LH RSCAN0.TMPTR41.UINT8[LH]
+#define RSCAN0TMPTR41H RSCAN0.TMPTR41.UINT16[H]
+#define RSCAN0TMPTR41HL RSCAN0.TMPTR41.UINT8[HL]
+#define RSCAN0TMPTR41HH RSCAN0.TMPTR41.UINT8[HH]
+#define RSCAN0TMDF041 RSCAN0.TMDF041.UINT32
+#define RSCAN0TMDF041L RSCAN0.TMDF041.UINT16[L]
+#define RSCAN0TMDF041LL RSCAN0.TMDF041.UINT8[LL]
+#define RSCAN0TMDF041LH RSCAN0.TMDF041.UINT8[LH]
+#define RSCAN0TMDF041H RSCAN0.TMDF041.UINT16[H]
+#define RSCAN0TMDF041HL RSCAN0.TMDF041.UINT8[HL]
+#define RSCAN0TMDF041HH RSCAN0.TMDF041.UINT8[HH]
+#define RSCAN0TMDF141 RSCAN0.TMDF141.UINT32
+#define RSCAN0TMDF141L RSCAN0.TMDF141.UINT16[L]
+#define RSCAN0TMDF141LL RSCAN0.TMDF141.UINT8[LL]
+#define RSCAN0TMDF141LH RSCAN0.TMDF141.UINT8[LH]
+#define RSCAN0TMDF141H RSCAN0.TMDF141.UINT16[H]
+#define RSCAN0TMDF141HL RSCAN0.TMDF141.UINT8[HL]
+#define RSCAN0TMDF141HH RSCAN0.TMDF141.UINT8[HH]
+#define RSCAN0TMID42 RSCAN0.TMID42.UINT32
+#define RSCAN0TMID42L RSCAN0.TMID42.UINT16[L]
+#define RSCAN0TMID42LL RSCAN0.TMID42.UINT8[LL]
+#define RSCAN0TMID42LH RSCAN0.TMID42.UINT8[LH]
+#define RSCAN0TMID42H RSCAN0.TMID42.UINT16[H]
+#define RSCAN0TMID42HL RSCAN0.TMID42.UINT8[HL]
+#define RSCAN0TMID42HH RSCAN0.TMID42.UINT8[HH]
+#define RSCAN0TMPTR42 RSCAN0.TMPTR42.UINT32
+#define RSCAN0TMPTR42L RSCAN0.TMPTR42.UINT16[L]
+#define RSCAN0TMPTR42LL RSCAN0.TMPTR42.UINT8[LL]
+#define RSCAN0TMPTR42LH RSCAN0.TMPTR42.UINT8[LH]
+#define RSCAN0TMPTR42H RSCAN0.TMPTR42.UINT16[H]
+#define RSCAN0TMPTR42HL RSCAN0.TMPTR42.UINT8[HL]
+#define RSCAN0TMPTR42HH RSCAN0.TMPTR42.UINT8[HH]
+#define RSCAN0TMDF042 RSCAN0.TMDF042.UINT32
+#define RSCAN0TMDF042L RSCAN0.TMDF042.UINT16[L]
+#define RSCAN0TMDF042LL RSCAN0.TMDF042.UINT8[LL]
+#define RSCAN0TMDF042LH RSCAN0.TMDF042.UINT8[LH]
+#define RSCAN0TMDF042H RSCAN0.TMDF042.UINT16[H]
+#define RSCAN0TMDF042HL RSCAN0.TMDF042.UINT8[HL]
+#define RSCAN0TMDF042HH RSCAN0.TMDF042.UINT8[HH]
+#define RSCAN0TMDF142 RSCAN0.TMDF142.UINT32
+#define RSCAN0TMDF142L RSCAN0.TMDF142.UINT16[L]
+#define RSCAN0TMDF142LL RSCAN0.TMDF142.UINT8[LL]
+#define RSCAN0TMDF142LH RSCAN0.TMDF142.UINT8[LH]
+#define RSCAN0TMDF142H RSCAN0.TMDF142.UINT16[H]
+#define RSCAN0TMDF142HL RSCAN0.TMDF142.UINT8[HL]
+#define RSCAN0TMDF142HH RSCAN0.TMDF142.UINT8[HH]
+#define RSCAN0TMID43 RSCAN0.TMID43.UINT32
+#define RSCAN0TMID43L RSCAN0.TMID43.UINT16[L]
+#define RSCAN0TMID43LL RSCAN0.TMID43.UINT8[LL]
+#define RSCAN0TMID43LH RSCAN0.TMID43.UINT8[LH]
+#define RSCAN0TMID43H RSCAN0.TMID43.UINT16[H]
+#define RSCAN0TMID43HL RSCAN0.TMID43.UINT8[HL]
+#define RSCAN0TMID43HH RSCAN0.TMID43.UINT8[HH]
+#define RSCAN0TMPTR43 RSCAN0.TMPTR43.UINT32
+#define RSCAN0TMPTR43L RSCAN0.TMPTR43.UINT16[L]
+#define RSCAN0TMPTR43LL RSCAN0.TMPTR43.UINT8[LL]
+#define RSCAN0TMPTR43LH RSCAN0.TMPTR43.UINT8[LH]
+#define RSCAN0TMPTR43H RSCAN0.TMPTR43.UINT16[H]
+#define RSCAN0TMPTR43HL RSCAN0.TMPTR43.UINT8[HL]
+#define RSCAN0TMPTR43HH RSCAN0.TMPTR43.UINT8[HH]
+#define RSCAN0TMDF043 RSCAN0.TMDF043.UINT32
+#define RSCAN0TMDF043L RSCAN0.TMDF043.UINT16[L]
+#define RSCAN0TMDF043LL RSCAN0.TMDF043.UINT8[LL]
+#define RSCAN0TMDF043LH RSCAN0.TMDF043.UINT8[LH]
+#define RSCAN0TMDF043H RSCAN0.TMDF043.UINT16[H]
+#define RSCAN0TMDF043HL RSCAN0.TMDF043.UINT8[HL]
+#define RSCAN0TMDF043HH RSCAN0.TMDF043.UINT8[HH]
+#define RSCAN0TMDF143 RSCAN0.TMDF143.UINT32
+#define RSCAN0TMDF143L RSCAN0.TMDF143.UINT16[L]
+#define RSCAN0TMDF143LL RSCAN0.TMDF143.UINT8[LL]
+#define RSCAN0TMDF143LH RSCAN0.TMDF143.UINT8[LH]
+#define RSCAN0TMDF143H RSCAN0.TMDF143.UINT16[H]
+#define RSCAN0TMDF143HL RSCAN0.TMDF143.UINT8[HL]
+#define RSCAN0TMDF143HH RSCAN0.TMDF143.UINT8[HH]
+#define RSCAN0TMID44 RSCAN0.TMID44.UINT32
+#define RSCAN0TMID44L RSCAN0.TMID44.UINT16[L]
+#define RSCAN0TMID44LL RSCAN0.TMID44.UINT8[LL]
+#define RSCAN0TMID44LH RSCAN0.TMID44.UINT8[LH]
+#define RSCAN0TMID44H RSCAN0.TMID44.UINT16[H]
+#define RSCAN0TMID44HL RSCAN0.TMID44.UINT8[HL]
+#define RSCAN0TMID44HH RSCAN0.TMID44.UINT8[HH]
+#define RSCAN0TMPTR44 RSCAN0.TMPTR44.UINT32
+#define RSCAN0TMPTR44L RSCAN0.TMPTR44.UINT16[L]
+#define RSCAN0TMPTR44LL RSCAN0.TMPTR44.UINT8[LL]
+#define RSCAN0TMPTR44LH RSCAN0.TMPTR44.UINT8[LH]
+#define RSCAN0TMPTR44H RSCAN0.TMPTR44.UINT16[H]
+#define RSCAN0TMPTR44HL RSCAN0.TMPTR44.UINT8[HL]
+#define RSCAN0TMPTR44HH RSCAN0.TMPTR44.UINT8[HH]
+#define RSCAN0TMDF044 RSCAN0.TMDF044.UINT32
+#define RSCAN0TMDF044L RSCAN0.TMDF044.UINT16[L]
+#define RSCAN0TMDF044LL RSCAN0.TMDF044.UINT8[LL]
+#define RSCAN0TMDF044LH RSCAN0.TMDF044.UINT8[LH]
+#define RSCAN0TMDF044H RSCAN0.TMDF044.UINT16[H]
+#define RSCAN0TMDF044HL RSCAN0.TMDF044.UINT8[HL]
+#define RSCAN0TMDF044HH RSCAN0.TMDF044.UINT8[HH]
+#define RSCAN0TMDF144 RSCAN0.TMDF144.UINT32
+#define RSCAN0TMDF144L RSCAN0.TMDF144.UINT16[L]
+#define RSCAN0TMDF144LL RSCAN0.TMDF144.UINT8[LL]
+#define RSCAN0TMDF144LH RSCAN0.TMDF144.UINT8[LH]
+#define RSCAN0TMDF144H RSCAN0.TMDF144.UINT16[H]
+#define RSCAN0TMDF144HL RSCAN0.TMDF144.UINT8[HL]
+#define RSCAN0TMDF144HH RSCAN0.TMDF144.UINT8[HH]
+#define RSCAN0TMID45 RSCAN0.TMID45.UINT32
+#define RSCAN0TMID45L RSCAN0.TMID45.UINT16[L]
+#define RSCAN0TMID45LL RSCAN0.TMID45.UINT8[LL]
+#define RSCAN0TMID45LH RSCAN0.TMID45.UINT8[LH]
+#define RSCAN0TMID45H RSCAN0.TMID45.UINT16[H]
+#define RSCAN0TMID45HL RSCAN0.TMID45.UINT8[HL]
+#define RSCAN0TMID45HH RSCAN0.TMID45.UINT8[HH]
+#define RSCAN0TMPTR45 RSCAN0.TMPTR45.UINT32
+#define RSCAN0TMPTR45L RSCAN0.TMPTR45.UINT16[L]
+#define RSCAN0TMPTR45LL RSCAN0.TMPTR45.UINT8[LL]
+#define RSCAN0TMPTR45LH RSCAN0.TMPTR45.UINT8[LH]
+#define RSCAN0TMPTR45H RSCAN0.TMPTR45.UINT16[H]
+#define RSCAN0TMPTR45HL RSCAN0.TMPTR45.UINT8[HL]
+#define RSCAN0TMPTR45HH RSCAN0.TMPTR45.UINT8[HH]
+#define RSCAN0TMDF045 RSCAN0.TMDF045.UINT32
+#define RSCAN0TMDF045L RSCAN0.TMDF045.UINT16[L]
+#define RSCAN0TMDF045LL RSCAN0.TMDF045.UINT8[LL]
+#define RSCAN0TMDF045LH RSCAN0.TMDF045.UINT8[LH]
+#define RSCAN0TMDF045H RSCAN0.TMDF045.UINT16[H]
+#define RSCAN0TMDF045HL RSCAN0.TMDF045.UINT8[HL]
+#define RSCAN0TMDF045HH RSCAN0.TMDF045.UINT8[HH]
+#define RSCAN0TMDF145 RSCAN0.TMDF145.UINT32
+#define RSCAN0TMDF145L RSCAN0.TMDF145.UINT16[L]
+#define RSCAN0TMDF145LL RSCAN0.TMDF145.UINT8[LL]
+#define RSCAN0TMDF145LH RSCAN0.TMDF145.UINT8[LH]
+#define RSCAN0TMDF145H RSCAN0.TMDF145.UINT16[H]
+#define RSCAN0TMDF145HL RSCAN0.TMDF145.UINT8[HL]
+#define RSCAN0TMDF145HH RSCAN0.TMDF145.UINT8[HH]
+#define RSCAN0TMID46 RSCAN0.TMID46.UINT32
+#define RSCAN0TMID46L RSCAN0.TMID46.UINT16[L]
+#define RSCAN0TMID46LL RSCAN0.TMID46.UINT8[LL]
+#define RSCAN0TMID46LH RSCAN0.TMID46.UINT8[LH]
+#define RSCAN0TMID46H RSCAN0.TMID46.UINT16[H]
+#define RSCAN0TMID46HL RSCAN0.TMID46.UINT8[HL]
+#define RSCAN0TMID46HH RSCAN0.TMID46.UINT8[HH]
+#define RSCAN0TMPTR46 RSCAN0.TMPTR46.UINT32
+#define RSCAN0TMPTR46L RSCAN0.TMPTR46.UINT16[L]
+#define RSCAN0TMPTR46LL RSCAN0.TMPTR46.UINT8[LL]
+#define RSCAN0TMPTR46LH RSCAN0.TMPTR46.UINT8[LH]
+#define RSCAN0TMPTR46H RSCAN0.TMPTR46.UINT16[H]
+#define RSCAN0TMPTR46HL RSCAN0.TMPTR46.UINT8[HL]
+#define RSCAN0TMPTR46HH RSCAN0.TMPTR46.UINT8[HH]
+#define RSCAN0TMDF046 RSCAN0.TMDF046.UINT32
+#define RSCAN0TMDF046L RSCAN0.TMDF046.UINT16[L]
+#define RSCAN0TMDF046LL RSCAN0.TMDF046.UINT8[LL]
+#define RSCAN0TMDF046LH RSCAN0.TMDF046.UINT8[LH]
+#define RSCAN0TMDF046H RSCAN0.TMDF046.UINT16[H]
+#define RSCAN0TMDF046HL RSCAN0.TMDF046.UINT8[HL]
+#define RSCAN0TMDF046HH RSCAN0.TMDF046.UINT8[HH]
+#define RSCAN0TMDF146 RSCAN0.TMDF146.UINT32
+#define RSCAN0TMDF146L RSCAN0.TMDF146.UINT16[L]
+#define RSCAN0TMDF146LL RSCAN0.TMDF146.UINT8[LL]
+#define RSCAN0TMDF146LH RSCAN0.TMDF146.UINT8[LH]
+#define RSCAN0TMDF146H RSCAN0.TMDF146.UINT16[H]
+#define RSCAN0TMDF146HL RSCAN0.TMDF146.UINT8[HL]
+#define RSCAN0TMDF146HH RSCAN0.TMDF146.UINT8[HH]
+#define RSCAN0TMID47 RSCAN0.TMID47.UINT32
+#define RSCAN0TMID47L RSCAN0.TMID47.UINT16[L]
+#define RSCAN0TMID47LL RSCAN0.TMID47.UINT8[LL]
+#define RSCAN0TMID47LH RSCAN0.TMID47.UINT8[LH]
+#define RSCAN0TMID47H RSCAN0.TMID47.UINT16[H]
+#define RSCAN0TMID47HL RSCAN0.TMID47.UINT8[HL]
+#define RSCAN0TMID47HH RSCAN0.TMID47.UINT8[HH]
+#define RSCAN0TMPTR47 RSCAN0.TMPTR47.UINT32
+#define RSCAN0TMPTR47L RSCAN0.TMPTR47.UINT16[L]
+#define RSCAN0TMPTR47LL RSCAN0.TMPTR47.UINT8[LL]
+#define RSCAN0TMPTR47LH RSCAN0.TMPTR47.UINT8[LH]
+#define RSCAN0TMPTR47H RSCAN0.TMPTR47.UINT16[H]
+#define RSCAN0TMPTR47HL RSCAN0.TMPTR47.UINT8[HL]
+#define RSCAN0TMPTR47HH RSCAN0.TMPTR47.UINT8[HH]
+#define RSCAN0TMDF047 RSCAN0.TMDF047.UINT32
+#define RSCAN0TMDF047L RSCAN0.TMDF047.UINT16[L]
+#define RSCAN0TMDF047LL RSCAN0.TMDF047.UINT8[LL]
+#define RSCAN0TMDF047LH RSCAN0.TMDF047.UINT8[LH]
+#define RSCAN0TMDF047H RSCAN0.TMDF047.UINT16[H]
+#define RSCAN0TMDF047HL RSCAN0.TMDF047.UINT8[HL]
+#define RSCAN0TMDF047HH RSCAN0.TMDF047.UINT8[HH]
+#define RSCAN0TMDF147 RSCAN0.TMDF147.UINT32
+#define RSCAN0TMDF147L RSCAN0.TMDF147.UINT16[L]
+#define RSCAN0TMDF147LL RSCAN0.TMDF147.UINT8[LL]
+#define RSCAN0TMDF147LH RSCAN0.TMDF147.UINT8[LH]
+#define RSCAN0TMDF147H RSCAN0.TMDF147.UINT16[H]
+#define RSCAN0TMDF147HL RSCAN0.TMDF147.UINT8[HL]
+#define RSCAN0TMDF147HH RSCAN0.TMDF147.UINT8[HH]
+#define RSCAN0TMID48 RSCAN0.TMID48.UINT32
+#define RSCAN0TMID48L RSCAN0.TMID48.UINT16[L]
+#define RSCAN0TMID48LL RSCAN0.TMID48.UINT8[LL]
+#define RSCAN0TMID48LH RSCAN0.TMID48.UINT8[LH]
+#define RSCAN0TMID48H RSCAN0.TMID48.UINT16[H]
+#define RSCAN0TMID48HL RSCAN0.TMID48.UINT8[HL]
+#define RSCAN0TMID48HH RSCAN0.TMID48.UINT8[HH]
+#define RSCAN0TMPTR48 RSCAN0.TMPTR48.UINT32
+#define RSCAN0TMPTR48L RSCAN0.TMPTR48.UINT16[L]
+#define RSCAN0TMPTR48LL RSCAN0.TMPTR48.UINT8[LL]
+#define RSCAN0TMPTR48LH RSCAN0.TMPTR48.UINT8[LH]
+#define RSCAN0TMPTR48H RSCAN0.TMPTR48.UINT16[H]
+#define RSCAN0TMPTR48HL RSCAN0.TMPTR48.UINT8[HL]
+#define RSCAN0TMPTR48HH RSCAN0.TMPTR48.UINT8[HH]
+#define RSCAN0TMDF048 RSCAN0.TMDF048.UINT32
+#define RSCAN0TMDF048L RSCAN0.TMDF048.UINT16[L]
+#define RSCAN0TMDF048LL RSCAN0.TMDF048.UINT8[LL]
+#define RSCAN0TMDF048LH RSCAN0.TMDF048.UINT8[LH]
+#define RSCAN0TMDF048H RSCAN0.TMDF048.UINT16[H]
+#define RSCAN0TMDF048HL RSCAN0.TMDF048.UINT8[HL]
+#define RSCAN0TMDF048HH RSCAN0.TMDF048.UINT8[HH]
+#define RSCAN0TMDF148 RSCAN0.TMDF148.UINT32
+#define RSCAN0TMDF148L RSCAN0.TMDF148.UINT16[L]
+#define RSCAN0TMDF148LL RSCAN0.TMDF148.UINT8[LL]
+#define RSCAN0TMDF148LH RSCAN0.TMDF148.UINT8[LH]
+#define RSCAN0TMDF148H RSCAN0.TMDF148.UINT16[H]
+#define RSCAN0TMDF148HL RSCAN0.TMDF148.UINT8[HL]
+#define RSCAN0TMDF148HH RSCAN0.TMDF148.UINT8[HH]
+#define RSCAN0TMID49 RSCAN0.TMID49.UINT32
+#define RSCAN0TMID49L RSCAN0.TMID49.UINT16[L]
+#define RSCAN0TMID49LL RSCAN0.TMID49.UINT8[LL]
+#define RSCAN0TMID49LH RSCAN0.TMID49.UINT8[LH]
+#define RSCAN0TMID49H RSCAN0.TMID49.UINT16[H]
+#define RSCAN0TMID49HL RSCAN0.TMID49.UINT8[HL]
+#define RSCAN0TMID49HH RSCAN0.TMID49.UINT8[HH]
+#define RSCAN0TMPTR49 RSCAN0.TMPTR49.UINT32
+#define RSCAN0TMPTR49L RSCAN0.TMPTR49.UINT16[L]
+#define RSCAN0TMPTR49LL RSCAN0.TMPTR49.UINT8[LL]
+#define RSCAN0TMPTR49LH RSCAN0.TMPTR49.UINT8[LH]
+#define RSCAN0TMPTR49H RSCAN0.TMPTR49.UINT16[H]
+#define RSCAN0TMPTR49HL RSCAN0.TMPTR49.UINT8[HL]
+#define RSCAN0TMPTR49HH RSCAN0.TMPTR49.UINT8[HH]
+#define RSCAN0TMDF049 RSCAN0.TMDF049.UINT32
+#define RSCAN0TMDF049L RSCAN0.TMDF049.UINT16[L]
+#define RSCAN0TMDF049LL RSCAN0.TMDF049.UINT8[LL]
+#define RSCAN0TMDF049LH RSCAN0.TMDF049.UINT8[LH]
+#define RSCAN0TMDF049H RSCAN0.TMDF049.UINT16[H]
+#define RSCAN0TMDF049HL RSCAN0.TMDF049.UINT8[HL]
+#define RSCAN0TMDF049HH RSCAN0.TMDF049.UINT8[HH]
+#define RSCAN0TMDF149 RSCAN0.TMDF149.UINT32
+#define RSCAN0TMDF149L RSCAN0.TMDF149.UINT16[L]
+#define RSCAN0TMDF149LL RSCAN0.TMDF149.UINT8[LL]
+#define RSCAN0TMDF149LH RSCAN0.TMDF149.UINT8[LH]
+#define RSCAN0TMDF149H RSCAN0.TMDF149.UINT16[H]
+#define RSCAN0TMDF149HL RSCAN0.TMDF149.UINT8[HL]
+#define RSCAN0TMDF149HH RSCAN0.TMDF149.UINT8[HH]
+#define RSCAN0TMID50 RSCAN0.TMID50.UINT32
+#define RSCAN0TMID50L RSCAN0.TMID50.UINT16[L]
+#define RSCAN0TMID50LL RSCAN0.TMID50.UINT8[LL]
+#define RSCAN0TMID50LH RSCAN0.TMID50.UINT8[LH]
+#define RSCAN0TMID50H RSCAN0.TMID50.UINT16[H]
+#define RSCAN0TMID50HL RSCAN0.TMID50.UINT8[HL]
+#define RSCAN0TMID50HH RSCAN0.TMID50.UINT8[HH]
+#define RSCAN0TMPTR50 RSCAN0.TMPTR50.UINT32
+#define RSCAN0TMPTR50L RSCAN0.TMPTR50.UINT16[L]
+#define RSCAN0TMPTR50LL RSCAN0.TMPTR50.UINT8[LL]
+#define RSCAN0TMPTR50LH RSCAN0.TMPTR50.UINT8[LH]
+#define RSCAN0TMPTR50H RSCAN0.TMPTR50.UINT16[H]
+#define RSCAN0TMPTR50HL RSCAN0.TMPTR50.UINT8[HL]
+#define RSCAN0TMPTR50HH RSCAN0.TMPTR50.UINT8[HH]
+#define RSCAN0TMDF050 RSCAN0.TMDF050.UINT32
+#define RSCAN0TMDF050L RSCAN0.TMDF050.UINT16[L]
+#define RSCAN0TMDF050LL RSCAN0.TMDF050.UINT8[LL]
+#define RSCAN0TMDF050LH RSCAN0.TMDF050.UINT8[LH]
+#define RSCAN0TMDF050H RSCAN0.TMDF050.UINT16[H]
+#define RSCAN0TMDF050HL RSCAN0.TMDF050.UINT8[HL]
+#define RSCAN0TMDF050HH RSCAN0.TMDF050.UINT8[HH]
+#define RSCAN0TMDF150 RSCAN0.TMDF150.UINT32
+#define RSCAN0TMDF150L RSCAN0.TMDF150.UINT16[L]
+#define RSCAN0TMDF150LL RSCAN0.TMDF150.UINT8[LL]
+#define RSCAN0TMDF150LH RSCAN0.TMDF150.UINT8[LH]
+#define RSCAN0TMDF150H RSCAN0.TMDF150.UINT16[H]
+#define RSCAN0TMDF150HL RSCAN0.TMDF150.UINT8[HL]
+#define RSCAN0TMDF150HH RSCAN0.TMDF150.UINT8[HH]
+#define RSCAN0TMID51 RSCAN0.TMID51.UINT32
+#define RSCAN0TMID51L RSCAN0.TMID51.UINT16[L]
+#define RSCAN0TMID51LL RSCAN0.TMID51.UINT8[LL]
+#define RSCAN0TMID51LH RSCAN0.TMID51.UINT8[LH]
+#define RSCAN0TMID51H RSCAN0.TMID51.UINT16[H]
+#define RSCAN0TMID51HL RSCAN0.TMID51.UINT8[HL]
+#define RSCAN0TMID51HH RSCAN0.TMID51.UINT8[HH]
+#define RSCAN0TMPTR51 RSCAN0.TMPTR51.UINT32
+#define RSCAN0TMPTR51L RSCAN0.TMPTR51.UINT16[L]
+#define RSCAN0TMPTR51LL RSCAN0.TMPTR51.UINT8[LL]
+#define RSCAN0TMPTR51LH RSCAN0.TMPTR51.UINT8[LH]
+#define RSCAN0TMPTR51H RSCAN0.TMPTR51.UINT16[H]
+#define RSCAN0TMPTR51HL RSCAN0.TMPTR51.UINT8[HL]
+#define RSCAN0TMPTR51HH RSCAN0.TMPTR51.UINT8[HH]
+#define RSCAN0TMDF051 RSCAN0.TMDF051.UINT32
+#define RSCAN0TMDF051L RSCAN0.TMDF051.UINT16[L]
+#define RSCAN0TMDF051LL RSCAN0.TMDF051.UINT8[LL]
+#define RSCAN0TMDF051LH RSCAN0.TMDF051.UINT8[LH]
+#define RSCAN0TMDF051H RSCAN0.TMDF051.UINT16[H]
+#define RSCAN0TMDF051HL RSCAN0.TMDF051.UINT8[HL]
+#define RSCAN0TMDF051HH RSCAN0.TMDF051.UINT8[HH]
+#define RSCAN0TMDF151 RSCAN0.TMDF151.UINT32
+#define RSCAN0TMDF151L RSCAN0.TMDF151.UINT16[L]
+#define RSCAN0TMDF151LL RSCAN0.TMDF151.UINT8[LL]
+#define RSCAN0TMDF151LH RSCAN0.TMDF151.UINT8[LH]
+#define RSCAN0TMDF151H RSCAN0.TMDF151.UINT16[H]
+#define RSCAN0TMDF151HL RSCAN0.TMDF151.UINT8[HL]
+#define RSCAN0TMDF151HH RSCAN0.TMDF151.UINT8[HH]
+#define RSCAN0TMID52 RSCAN0.TMID52.UINT32
+#define RSCAN0TMID52L RSCAN0.TMID52.UINT16[L]
+#define RSCAN0TMID52LL RSCAN0.TMID52.UINT8[LL]
+#define RSCAN0TMID52LH RSCAN0.TMID52.UINT8[LH]
+#define RSCAN0TMID52H RSCAN0.TMID52.UINT16[H]
+#define RSCAN0TMID52HL RSCAN0.TMID52.UINT8[HL]
+#define RSCAN0TMID52HH RSCAN0.TMID52.UINT8[HH]
+#define RSCAN0TMPTR52 RSCAN0.TMPTR52.UINT32
+#define RSCAN0TMPTR52L RSCAN0.TMPTR52.UINT16[L]
+#define RSCAN0TMPTR52LL RSCAN0.TMPTR52.UINT8[LL]
+#define RSCAN0TMPTR52LH RSCAN0.TMPTR52.UINT8[LH]
+#define RSCAN0TMPTR52H RSCAN0.TMPTR52.UINT16[H]
+#define RSCAN0TMPTR52HL RSCAN0.TMPTR52.UINT8[HL]
+#define RSCAN0TMPTR52HH RSCAN0.TMPTR52.UINT8[HH]
+#define RSCAN0TMDF052 RSCAN0.TMDF052.UINT32
+#define RSCAN0TMDF052L RSCAN0.TMDF052.UINT16[L]
+#define RSCAN0TMDF052LL RSCAN0.TMDF052.UINT8[LL]
+#define RSCAN0TMDF052LH RSCAN0.TMDF052.UINT8[LH]
+#define RSCAN0TMDF052H RSCAN0.TMDF052.UINT16[H]
+#define RSCAN0TMDF052HL RSCAN0.TMDF052.UINT8[HL]
+#define RSCAN0TMDF052HH RSCAN0.TMDF052.UINT8[HH]
+#define RSCAN0TMDF152 RSCAN0.TMDF152.UINT32
+#define RSCAN0TMDF152L RSCAN0.TMDF152.UINT16[L]
+#define RSCAN0TMDF152LL RSCAN0.TMDF152.UINT8[LL]
+#define RSCAN0TMDF152LH RSCAN0.TMDF152.UINT8[LH]
+#define RSCAN0TMDF152H RSCAN0.TMDF152.UINT16[H]
+#define RSCAN0TMDF152HL RSCAN0.TMDF152.UINT8[HL]
+#define RSCAN0TMDF152HH RSCAN0.TMDF152.UINT8[HH]
+#define RSCAN0TMID53 RSCAN0.TMID53.UINT32
+#define RSCAN0TMID53L RSCAN0.TMID53.UINT16[L]
+#define RSCAN0TMID53LL RSCAN0.TMID53.UINT8[LL]
+#define RSCAN0TMID53LH RSCAN0.TMID53.UINT8[LH]
+#define RSCAN0TMID53H RSCAN0.TMID53.UINT16[H]
+#define RSCAN0TMID53HL RSCAN0.TMID53.UINT8[HL]
+#define RSCAN0TMID53HH RSCAN0.TMID53.UINT8[HH]
+#define RSCAN0TMPTR53 RSCAN0.TMPTR53.UINT32
+#define RSCAN0TMPTR53L RSCAN0.TMPTR53.UINT16[L]
+#define RSCAN0TMPTR53LL RSCAN0.TMPTR53.UINT8[LL]
+#define RSCAN0TMPTR53LH RSCAN0.TMPTR53.UINT8[LH]
+#define RSCAN0TMPTR53H RSCAN0.TMPTR53.UINT16[H]
+#define RSCAN0TMPTR53HL RSCAN0.TMPTR53.UINT8[HL]
+#define RSCAN0TMPTR53HH RSCAN0.TMPTR53.UINT8[HH]
+#define RSCAN0TMDF053 RSCAN0.TMDF053.UINT32
+#define RSCAN0TMDF053L RSCAN0.TMDF053.UINT16[L]
+#define RSCAN0TMDF053LL RSCAN0.TMDF053.UINT8[LL]
+#define RSCAN0TMDF053LH RSCAN0.TMDF053.UINT8[LH]
+#define RSCAN0TMDF053H RSCAN0.TMDF053.UINT16[H]
+#define RSCAN0TMDF053HL RSCAN0.TMDF053.UINT8[HL]
+#define RSCAN0TMDF053HH RSCAN0.TMDF053.UINT8[HH]
+#define RSCAN0TMDF153 RSCAN0.TMDF153.UINT32
+#define RSCAN0TMDF153L RSCAN0.TMDF153.UINT16[L]
+#define RSCAN0TMDF153LL RSCAN0.TMDF153.UINT8[LL]
+#define RSCAN0TMDF153LH RSCAN0.TMDF153.UINT8[LH]
+#define RSCAN0TMDF153H RSCAN0.TMDF153.UINT16[H]
+#define RSCAN0TMDF153HL RSCAN0.TMDF153.UINT8[HL]
+#define RSCAN0TMDF153HH RSCAN0.TMDF153.UINT8[HH]
+#define RSCAN0TMID54 RSCAN0.TMID54.UINT32
+#define RSCAN0TMID54L RSCAN0.TMID54.UINT16[L]
+#define RSCAN0TMID54LL RSCAN0.TMID54.UINT8[LL]
+#define RSCAN0TMID54LH RSCAN0.TMID54.UINT8[LH]
+#define RSCAN0TMID54H RSCAN0.TMID54.UINT16[H]
+#define RSCAN0TMID54HL RSCAN0.TMID54.UINT8[HL]
+#define RSCAN0TMID54HH RSCAN0.TMID54.UINT8[HH]
+#define RSCAN0TMPTR54 RSCAN0.TMPTR54.UINT32
+#define RSCAN0TMPTR54L RSCAN0.TMPTR54.UINT16[L]
+#define RSCAN0TMPTR54LL RSCAN0.TMPTR54.UINT8[LL]
+#define RSCAN0TMPTR54LH RSCAN0.TMPTR54.UINT8[LH]
+#define RSCAN0TMPTR54H RSCAN0.TMPTR54.UINT16[H]
+#define RSCAN0TMPTR54HL RSCAN0.TMPTR54.UINT8[HL]
+#define RSCAN0TMPTR54HH RSCAN0.TMPTR54.UINT8[HH]
+#define RSCAN0TMDF054 RSCAN0.TMDF054.UINT32
+#define RSCAN0TMDF054L RSCAN0.TMDF054.UINT16[L]
+#define RSCAN0TMDF054LL RSCAN0.TMDF054.UINT8[LL]
+#define RSCAN0TMDF054LH RSCAN0.TMDF054.UINT8[LH]
+#define RSCAN0TMDF054H RSCAN0.TMDF054.UINT16[H]
+#define RSCAN0TMDF054HL RSCAN0.TMDF054.UINT8[HL]
+#define RSCAN0TMDF054HH RSCAN0.TMDF054.UINT8[HH]
+#define RSCAN0TMDF154 RSCAN0.TMDF154.UINT32
+#define RSCAN0TMDF154L RSCAN0.TMDF154.UINT16[L]
+#define RSCAN0TMDF154LL RSCAN0.TMDF154.UINT8[LL]
+#define RSCAN0TMDF154LH RSCAN0.TMDF154.UINT8[LH]
+#define RSCAN0TMDF154H RSCAN0.TMDF154.UINT16[H]
+#define RSCAN0TMDF154HL RSCAN0.TMDF154.UINT8[HL]
+#define RSCAN0TMDF154HH RSCAN0.TMDF154.UINT8[HH]
+#define RSCAN0TMID55 RSCAN0.TMID55.UINT32
+#define RSCAN0TMID55L RSCAN0.TMID55.UINT16[L]
+#define RSCAN0TMID55LL RSCAN0.TMID55.UINT8[LL]
+#define RSCAN0TMID55LH RSCAN0.TMID55.UINT8[LH]
+#define RSCAN0TMID55H RSCAN0.TMID55.UINT16[H]
+#define RSCAN0TMID55HL RSCAN0.TMID55.UINT8[HL]
+#define RSCAN0TMID55HH RSCAN0.TMID55.UINT8[HH]
+#define RSCAN0TMPTR55 RSCAN0.TMPTR55.UINT32
+#define RSCAN0TMPTR55L RSCAN0.TMPTR55.UINT16[L]
+#define RSCAN0TMPTR55LL RSCAN0.TMPTR55.UINT8[LL]
+#define RSCAN0TMPTR55LH RSCAN0.TMPTR55.UINT8[LH]
+#define RSCAN0TMPTR55H RSCAN0.TMPTR55.UINT16[H]
+#define RSCAN0TMPTR55HL RSCAN0.TMPTR55.UINT8[HL]
+#define RSCAN0TMPTR55HH RSCAN0.TMPTR55.UINT8[HH]
+#define RSCAN0TMDF055 RSCAN0.TMDF055.UINT32
+#define RSCAN0TMDF055L RSCAN0.TMDF055.UINT16[L]
+#define RSCAN0TMDF055LL RSCAN0.TMDF055.UINT8[LL]
+#define RSCAN0TMDF055LH RSCAN0.TMDF055.UINT8[LH]
+#define RSCAN0TMDF055H RSCAN0.TMDF055.UINT16[H]
+#define RSCAN0TMDF055HL RSCAN0.TMDF055.UINT8[HL]
+#define RSCAN0TMDF055HH RSCAN0.TMDF055.UINT8[HH]
+#define RSCAN0TMDF155 RSCAN0.TMDF155.UINT32
+#define RSCAN0TMDF155L RSCAN0.TMDF155.UINT16[L]
+#define RSCAN0TMDF155LL RSCAN0.TMDF155.UINT8[LL]
+#define RSCAN0TMDF155LH RSCAN0.TMDF155.UINT8[LH]
+#define RSCAN0TMDF155H RSCAN0.TMDF155.UINT16[H]
+#define RSCAN0TMDF155HL RSCAN0.TMDF155.UINT8[HL]
+#define RSCAN0TMDF155HH RSCAN0.TMDF155.UINT8[HH]
+#define RSCAN0TMID56 RSCAN0.TMID56.UINT32
+#define RSCAN0TMID56L RSCAN0.TMID56.UINT16[L]
+#define RSCAN0TMID56LL RSCAN0.TMID56.UINT8[LL]
+#define RSCAN0TMID56LH RSCAN0.TMID56.UINT8[LH]
+#define RSCAN0TMID56H RSCAN0.TMID56.UINT16[H]
+#define RSCAN0TMID56HL RSCAN0.TMID56.UINT8[HL]
+#define RSCAN0TMID56HH RSCAN0.TMID56.UINT8[HH]
+#define RSCAN0TMPTR56 RSCAN0.TMPTR56.UINT32
+#define RSCAN0TMPTR56L RSCAN0.TMPTR56.UINT16[L]
+#define RSCAN0TMPTR56LL RSCAN0.TMPTR56.UINT8[LL]
+#define RSCAN0TMPTR56LH RSCAN0.TMPTR56.UINT8[LH]
+#define RSCAN0TMPTR56H RSCAN0.TMPTR56.UINT16[H]
+#define RSCAN0TMPTR56HL RSCAN0.TMPTR56.UINT8[HL]
+#define RSCAN0TMPTR56HH RSCAN0.TMPTR56.UINT8[HH]
+#define RSCAN0TMDF056 RSCAN0.TMDF056.UINT32
+#define RSCAN0TMDF056L RSCAN0.TMDF056.UINT16[L]
+#define RSCAN0TMDF056LL RSCAN0.TMDF056.UINT8[LL]
+#define RSCAN0TMDF056LH RSCAN0.TMDF056.UINT8[LH]
+#define RSCAN0TMDF056H RSCAN0.TMDF056.UINT16[H]
+#define RSCAN0TMDF056HL RSCAN0.TMDF056.UINT8[HL]
+#define RSCAN0TMDF056HH RSCAN0.TMDF056.UINT8[HH]
+#define RSCAN0TMDF156 RSCAN0.TMDF156.UINT32
+#define RSCAN0TMDF156L RSCAN0.TMDF156.UINT16[L]
+#define RSCAN0TMDF156LL RSCAN0.TMDF156.UINT8[LL]
+#define RSCAN0TMDF156LH RSCAN0.TMDF156.UINT8[LH]
+#define RSCAN0TMDF156H RSCAN0.TMDF156.UINT16[H]
+#define RSCAN0TMDF156HL RSCAN0.TMDF156.UINT8[HL]
+#define RSCAN0TMDF156HH RSCAN0.TMDF156.UINT8[HH]
+#define RSCAN0TMID57 RSCAN0.TMID57.UINT32
+#define RSCAN0TMID57L RSCAN0.TMID57.UINT16[L]
+#define RSCAN0TMID57LL RSCAN0.TMID57.UINT8[LL]
+#define RSCAN0TMID57LH RSCAN0.TMID57.UINT8[LH]
+#define RSCAN0TMID57H RSCAN0.TMID57.UINT16[H]
+#define RSCAN0TMID57HL RSCAN0.TMID57.UINT8[HL]
+#define RSCAN0TMID57HH RSCAN0.TMID57.UINT8[HH]
+#define RSCAN0TMPTR57 RSCAN0.TMPTR57.UINT32
+#define RSCAN0TMPTR57L RSCAN0.TMPTR57.UINT16[L]
+#define RSCAN0TMPTR57LL RSCAN0.TMPTR57.UINT8[LL]
+#define RSCAN0TMPTR57LH RSCAN0.TMPTR57.UINT8[LH]
+#define RSCAN0TMPTR57H RSCAN0.TMPTR57.UINT16[H]
+#define RSCAN0TMPTR57HL RSCAN0.TMPTR57.UINT8[HL]
+#define RSCAN0TMPTR57HH RSCAN0.TMPTR57.UINT8[HH]
+#define RSCAN0TMDF057 RSCAN0.TMDF057.UINT32
+#define RSCAN0TMDF057L RSCAN0.TMDF057.UINT16[L]
+#define RSCAN0TMDF057LL RSCAN0.TMDF057.UINT8[LL]
+#define RSCAN0TMDF057LH RSCAN0.TMDF057.UINT8[LH]
+#define RSCAN0TMDF057H RSCAN0.TMDF057.UINT16[H]
+#define RSCAN0TMDF057HL RSCAN0.TMDF057.UINT8[HL]
+#define RSCAN0TMDF057HH RSCAN0.TMDF057.UINT8[HH]
+#define RSCAN0TMDF157 RSCAN0.TMDF157.UINT32
+#define RSCAN0TMDF157L RSCAN0.TMDF157.UINT16[L]
+#define RSCAN0TMDF157LL RSCAN0.TMDF157.UINT8[LL]
+#define RSCAN0TMDF157LH RSCAN0.TMDF157.UINT8[LH]
+#define RSCAN0TMDF157H RSCAN0.TMDF157.UINT16[H]
+#define RSCAN0TMDF157HL RSCAN0.TMDF157.UINT8[HL]
+#define RSCAN0TMDF157HH RSCAN0.TMDF157.UINT8[HH]
+#define RSCAN0TMID58 RSCAN0.TMID58.UINT32
+#define RSCAN0TMID58L RSCAN0.TMID58.UINT16[L]
+#define RSCAN0TMID58LL RSCAN0.TMID58.UINT8[LL]
+#define RSCAN0TMID58LH RSCAN0.TMID58.UINT8[LH]
+#define RSCAN0TMID58H RSCAN0.TMID58.UINT16[H]
+#define RSCAN0TMID58HL RSCAN0.TMID58.UINT8[HL]
+#define RSCAN0TMID58HH RSCAN0.TMID58.UINT8[HH]
+#define RSCAN0TMPTR58 RSCAN0.TMPTR58.UINT32
+#define RSCAN0TMPTR58L RSCAN0.TMPTR58.UINT16[L]
+#define RSCAN0TMPTR58LL RSCAN0.TMPTR58.UINT8[LL]
+#define RSCAN0TMPTR58LH RSCAN0.TMPTR58.UINT8[LH]
+#define RSCAN0TMPTR58H RSCAN0.TMPTR58.UINT16[H]
+#define RSCAN0TMPTR58HL RSCAN0.TMPTR58.UINT8[HL]
+#define RSCAN0TMPTR58HH RSCAN0.TMPTR58.UINT8[HH]
+#define RSCAN0TMDF058 RSCAN0.TMDF058.UINT32
+#define RSCAN0TMDF058L RSCAN0.TMDF058.UINT16[L]
+#define RSCAN0TMDF058LL RSCAN0.TMDF058.UINT8[LL]
+#define RSCAN0TMDF058LH RSCAN0.TMDF058.UINT8[LH]
+#define RSCAN0TMDF058H RSCAN0.TMDF058.UINT16[H]
+#define RSCAN0TMDF058HL RSCAN0.TMDF058.UINT8[HL]
+#define RSCAN0TMDF058HH RSCAN0.TMDF058.UINT8[HH]
+#define RSCAN0TMDF158 RSCAN0.TMDF158.UINT32
+#define RSCAN0TMDF158L RSCAN0.TMDF158.UINT16[L]
+#define RSCAN0TMDF158LL RSCAN0.TMDF158.UINT8[LL]
+#define RSCAN0TMDF158LH RSCAN0.TMDF158.UINT8[LH]
+#define RSCAN0TMDF158H RSCAN0.TMDF158.UINT16[H]
+#define RSCAN0TMDF158HL RSCAN0.TMDF158.UINT8[HL]
+#define RSCAN0TMDF158HH RSCAN0.TMDF158.UINT8[HH]
+#define RSCAN0TMID59 RSCAN0.TMID59.UINT32
+#define RSCAN0TMID59L RSCAN0.TMID59.UINT16[L]
+#define RSCAN0TMID59LL RSCAN0.TMID59.UINT8[LL]
+#define RSCAN0TMID59LH RSCAN0.TMID59.UINT8[LH]
+#define RSCAN0TMID59H RSCAN0.TMID59.UINT16[H]
+#define RSCAN0TMID59HL RSCAN0.TMID59.UINT8[HL]
+#define RSCAN0TMID59HH RSCAN0.TMID59.UINT8[HH]
+#define RSCAN0TMPTR59 RSCAN0.TMPTR59.UINT32
+#define RSCAN0TMPTR59L RSCAN0.TMPTR59.UINT16[L]
+#define RSCAN0TMPTR59LL RSCAN0.TMPTR59.UINT8[LL]
+#define RSCAN0TMPTR59LH RSCAN0.TMPTR59.UINT8[LH]
+#define RSCAN0TMPTR59H RSCAN0.TMPTR59.UINT16[H]
+#define RSCAN0TMPTR59HL RSCAN0.TMPTR59.UINT8[HL]
+#define RSCAN0TMPTR59HH RSCAN0.TMPTR59.UINT8[HH]
+#define RSCAN0TMDF059 RSCAN0.TMDF059.UINT32
+#define RSCAN0TMDF059L RSCAN0.TMDF059.UINT16[L]
+#define RSCAN0TMDF059LL RSCAN0.TMDF059.UINT8[LL]
+#define RSCAN0TMDF059LH RSCAN0.TMDF059.UINT8[LH]
+#define RSCAN0TMDF059H RSCAN0.TMDF059.UINT16[H]
+#define RSCAN0TMDF059HL RSCAN0.TMDF059.UINT8[HL]
+#define RSCAN0TMDF059HH RSCAN0.TMDF059.UINT8[HH]
+#define RSCAN0TMDF159 RSCAN0.TMDF159.UINT32
+#define RSCAN0TMDF159L RSCAN0.TMDF159.UINT16[L]
+#define RSCAN0TMDF159LL RSCAN0.TMDF159.UINT8[LL]
+#define RSCAN0TMDF159LH RSCAN0.TMDF159.UINT8[LH]
+#define RSCAN0TMDF159H RSCAN0.TMDF159.UINT16[H]
+#define RSCAN0TMDF159HL RSCAN0.TMDF159.UINT8[HL]
+#define RSCAN0TMDF159HH RSCAN0.TMDF159.UINT8[HH]
+#define RSCAN0TMID60 RSCAN0.TMID60.UINT32
+#define RSCAN0TMID60L RSCAN0.TMID60.UINT16[L]
+#define RSCAN0TMID60LL RSCAN0.TMID60.UINT8[LL]
+#define RSCAN0TMID60LH RSCAN0.TMID60.UINT8[LH]
+#define RSCAN0TMID60H RSCAN0.TMID60.UINT16[H]
+#define RSCAN0TMID60HL RSCAN0.TMID60.UINT8[HL]
+#define RSCAN0TMID60HH RSCAN0.TMID60.UINT8[HH]
+#define RSCAN0TMPTR60 RSCAN0.TMPTR60.UINT32
+#define RSCAN0TMPTR60L RSCAN0.TMPTR60.UINT16[L]
+#define RSCAN0TMPTR60LL RSCAN0.TMPTR60.UINT8[LL]
+#define RSCAN0TMPTR60LH RSCAN0.TMPTR60.UINT8[LH]
+#define RSCAN0TMPTR60H RSCAN0.TMPTR60.UINT16[H]
+#define RSCAN0TMPTR60HL RSCAN0.TMPTR60.UINT8[HL]
+#define RSCAN0TMPTR60HH RSCAN0.TMPTR60.UINT8[HH]
+#define RSCAN0TMDF060 RSCAN0.TMDF060.UINT32
+#define RSCAN0TMDF060L RSCAN0.TMDF060.UINT16[L]
+#define RSCAN0TMDF060LL RSCAN0.TMDF060.UINT8[LL]
+#define RSCAN0TMDF060LH RSCAN0.TMDF060.UINT8[LH]
+#define RSCAN0TMDF060H RSCAN0.TMDF060.UINT16[H]
+#define RSCAN0TMDF060HL RSCAN0.TMDF060.UINT8[HL]
+#define RSCAN0TMDF060HH RSCAN0.TMDF060.UINT8[HH]
+#define RSCAN0TMDF160 RSCAN0.TMDF160.UINT32
+#define RSCAN0TMDF160L RSCAN0.TMDF160.UINT16[L]
+#define RSCAN0TMDF160LL RSCAN0.TMDF160.UINT8[LL]
+#define RSCAN0TMDF160LH RSCAN0.TMDF160.UINT8[LH]
+#define RSCAN0TMDF160H RSCAN0.TMDF160.UINT16[H]
+#define RSCAN0TMDF160HL RSCAN0.TMDF160.UINT8[HL]
+#define RSCAN0TMDF160HH RSCAN0.TMDF160.UINT8[HH]
+#define RSCAN0TMID61 RSCAN0.TMID61.UINT32
+#define RSCAN0TMID61L RSCAN0.TMID61.UINT16[L]
+#define RSCAN0TMID61LL RSCAN0.TMID61.UINT8[LL]
+#define RSCAN0TMID61LH RSCAN0.TMID61.UINT8[LH]
+#define RSCAN0TMID61H RSCAN0.TMID61.UINT16[H]
+#define RSCAN0TMID61HL RSCAN0.TMID61.UINT8[HL]
+#define RSCAN0TMID61HH RSCAN0.TMID61.UINT8[HH]
+#define RSCAN0TMPTR61 RSCAN0.TMPTR61.UINT32
+#define RSCAN0TMPTR61L RSCAN0.TMPTR61.UINT16[L]
+#define RSCAN0TMPTR61LL RSCAN0.TMPTR61.UINT8[LL]
+#define RSCAN0TMPTR61LH RSCAN0.TMPTR61.UINT8[LH]
+#define RSCAN0TMPTR61H RSCAN0.TMPTR61.UINT16[H]
+#define RSCAN0TMPTR61HL RSCAN0.TMPTR61.UINT8[HL]
+#define RSCAN0TMPTR61HH RSCAN0.TMPTR61.UINT8[HH]
+#define RSCAN0TMDF061 RSCAN0.TMDF061.UINT32
+#define RSCAN0TMDF061L RSCAN0.TMDF061.UINT16[L]
+#define RSCAN0TMDF061LL RSCAN0.TMDF061.UINT8[LL]
+#define RSCAN0TMDF061LH RSCAN0.TMDF061.UINT8[LH]
+#define RSCAN0TMDF061H RSCAN0.TMDF061.UINT16[H]
+#define RSCAN0TMDF061HL RSCAN0.TMDF061.UINT8[HL]
+#define RSCAN0TMDF061HH RSCAN0.TMDF061.UINT8[HH]
+#define RSCAN0TMDF161 RSCAN0.TMDF161.UINT32
+#define RSCAN0TMDF161L RSCAN0.TMDF161.UINT16[L]
+#define RSCAN0TMDF161LL RSCAN0.TMDF161.UINT8[LL]
+#define RSCAN0TMDF161LH RSCAN0.TMDF161.UINT8[LH]
+#define RSCAN0TMDF161H RSCAN0.TMDF161.UINT16[H]
+#define RSCAN0TMDF161HL RSCAN0.TMDF161.UINT8[HL]
+#define RSCAN0TMDF161HH RSCAN0.TMDF161.UINT8[HH]
+#define RSCAN0TMID62 RSCAN0.TMID62.UINT32
+#define RSCAN0TMID62L RSCAN0.TMID62.UINT16[L]
+#define RSCAN0TMID62LL RSCAN0.TMID62.UINT8[LL]
+#define RSCAN0TMID62LH RSCAN0.TMID62.UINT8[LH]
+#define RSCAN0TMID62H RSCAN0.TMID62.UINT16[H]
+#define RSCAN0TMID62HL RSCAN0.TMID62.UINT8[HL]
+#define RSCAN0TMID62HH RSCAN0.TMID62.UINT8[HH]
+#define RSCAN0TMPTR62 RSCAN0.TMPTR62.UINT32
+#define RSCAN0TMPTR62L RSCAN0.TMPTR62.UINT16[L]
+#define RSCAN0TMPTR62LL RSCAN0.TMPTR62.UINT8[LL]
+#define RSCAN0TMPTR62LH RSCAN0.TMPTR62.UINT8[LH]
+#define RSCAN0TMPTR62H RSCAN0.TMPTR62.UINT16[H]
+#define RSCAN0TMPTR62HL RSCAN0.TMPTR62.UINT8[HL]
+#define RSCAN0TMPTR62HH RSCAN0.TMPTR62.UINT8[HH]
+#define RSCAN0TMDF062 RSCAN0.TMDF062.UINT32
+#define RSCAN0TMDF062L RSCAN0.TMDF062.UINT16[L]
+#define RSCAN0TMDF062LL RSCAN0.TMDF062.UINT8[LL]
+#define RSCAN0TMDF062LH RSCAN0.TMDF062.UINT8[LH]
+#define RSCAN0TMDF062H RSCAN0.TMDF062.UINT16[H]
+#define RSCAN0TMDF062HL RSCAN0.TMDF062.UINT8[HL]
+#define RSCAN0TMDF062HH RSCAN0.TMDF062.UINT8[HH]
+#define RSCAN0TMDF162 RSCAN0.TMDF162.UINT32
+#define RSCAN0TMDF162L RSCAN0.TMDF162.UINT16[L]
+#define RSCAN0TMDF162LL RSCAN0.TMDF162.UINT8[LL]
+#define RSCAN0TMDF162LH RSCAN0.TMDF162.UINT8[LH]
+#define RSCAN0TMDF162H RSCAN0.TMDF162.UINT16[H]
+#define RSCAN0TMDF162HL RSCAN0.TMDF162.UINT8[HL]
+#define RSCAN0TMDF162HH RSCAN0.TMDF162.UINT8[HH]
+#define RSCAN0TMID63 RSCAN0.TMID63.UINT32
+#define RSCAN0TMID63L RSCAN0.TMID63.UINT16[L]
+#define RSCAN0TMID63LL RSCAN0.TMID63.UINT8[LL]
+#define RSCAN0TMID63LH RSCAN0.TMID63.UINT8[LH]
+#define RSCAN0TMID63H RSCAN0.TMID63.UINT16[H]
+#define RSCAN0TMID63HL RSCAN0.TMID63.UINT8[HL]
+#define RSCAN0TMID63HH RSCAN0.TMID63.UINT8[HH]
+#define RSCAN0TMPTR63 RSCAN0.TMPTR63.UINT32
+#define RSCAN0TMPTR63L RSCAN0.TMPTR63.UINT16[L]
+#define RSCAN0TMPTR63LL RSCAN0.TMPTR63.UINT8[LL]
+#define RSCAN0TMPTR63LH RSCAN0.TMPTR63.UINT8[LH]
+#define RSCAN0TMPTR63H RSCAN0.TMPTR63.UINT16[H]
+#define RSCAN0TMPTR63HL RSCAN0.TMPTR63.UINT8[HL]
+#define RSCAN0TMPTR63HH RSCAN0.TMPTR63.UINT8[HH]
+#define RSCAN0TMDF063 RSCAN0.TMDF063.UINT32
+#define RSCAN0TMDF063L RSCAN0.TMDF063.UINT16[L]
+#define RSCAN0TMDF063LL RSCAN0.TMDF063.UINT8[LL]
+#define RSCAN0TMDF063LH RSCAN0.TMDF063.UINT8[LH]
+#define RSCAN0TMDF063H RSCAN0.TMDF063.UINT16[H]
+#define RSCAN0TMDF063HL RSCAN0.TMDF063.UINT8[HL]
+#define RSCAN0TMDF063HH RSCAN0.TMDF063.UINT8[HH]
+#define RSCAN0TMDF163 RSCAN0.TMDF163.UINT32
+#define RSCAN0TMDF163L RSCAN0.TMDF163.UINT16[L]
+#define RSCAN0TMDF163LL RSCAN0.TMDF163.UINT8[LL]
+#define RSCAN0TMDF163LH RSCAN0.TMDF163.UINT8[LH]
+#define RSCAN0TMDF163H RSCAN0.TMDF163.UINT16[H]
+#define RSCAN0TMDF163HL RSCAN0.TMDF163.UINT8[HL]
+#define RSCAN0TMDF163HH RSCAN0.TMDF163.UINT8[HH]
+#define RSCAN0TMID64 RSCAN0.TMID64.UINT32
+#define RSCAN0TMID64L RSCAN0.TMID64.UINT16[L]
+#define RSCAN0TMID64LL RSCAN0.TMID64.UINT8[LL]
+#define RSCAN0TMID64LH RSCAN0.TMID64.UINT8[LH]
+#define RSCAN0TMID64H RSCAN0.TMID64.UINT16[H]
+#define RSCAN0TMID64HL RSCAN0.TMID64.UINT8[HL]
+#define RSCAN0TMID64HH RSCAN0.TMID64.UINT8[HH]
+#define RSCAN0TMPTR64 RSCAN0.TMPTR64.UINT32
+#define RSCAN0TMPTR64L RSCAN0.TMPTR64.UINT16[L]
+#define RSCAN0TMPTR64LL RSCAN0.TMPTR64.UINT8[LL]
+#define RSCAN0TMPTR64LH RSCAN0.TMPTR64.UINT8[LH]
+#define RSCAN0TMPTR64H RSCAN0.TMPTR64.UINT16[H]
+#define RSCAN0TMPTR64HL RSCAN0.TMPTR64.UINT8[HL]
+#define RSCAN0TMPTR64HH RSCAN0.TMPTR64.UINT8[HH]
+#define RSCAN0TMDF064 RSCAN0.TMDF064.UINT32
+#define RSCAN0TMDF064L RSCAN0.TMDF064.UINT16[L]
+#define RSCAN0TMDF064LL RSCAN0.TMDF064.UINT8[LL]
+#define RSCAN0TMDF064LH RSCAN0.TMDF064.UINT8[LH]
+#define RSCAN0TMDF064H RSCAN0.TMDF064.UINT16[H]
+#define RSCAN0TMDF064HL RSCAN0.TMDF064.UINT8[HL]
+#define RSCAN0TMDF064HH RSCAN0.TMDF064.UINT8[HH]
+#define RSCAN0TMDF164 RSCAN0.TMDF164.UINT32
+#define RSCAN0TMDF164L RSCAN0.TMDF164.UINT16[L]
+#define RSCAN0TMDF164LL RSCAN0.TMDF164.UINT8[LL]
+#define RSCAN0TMDF164LH RSCAN0.TMDF164.UINT8[LH]
+#define RSCAN0TMDF164H RSCAN0.TMDF164.UINT16[H]
+#define RSCAN0TMDF164HL RSCAN0.TMDF164.UINT8[HL]
+#define RSCAN0TMDF164HH RSCAN0.TMDF164.UINT8[HH]
+#define RSCAN0TMID65 RSCAN0.TMID65.UINT32
+#define RSCAN0TMID65L RSCAN0.TMID65.UINT16[L]
+#define RSCAN0TMID65LL RSCAN0.TMID65.UINT8[LL]
+#define RSCAN0TMID65LH RSCAN0.TMID65.UINT8[LH]
+#define RSCAN0TMID65H RSCAN0.TMID65.UINT16[H]
+#define RSCAN0TMID65HL RSCAN0.TMID65.UINT8[HL]
+#define RSCAN0TMID65HH RSCAN0.TMID65.UINT8[HH]
+#define RSCAN0TMPTR65 RSCAN0.TMPTR65.UINT32
+#define RSCAN0TMPTR65L RSCAN0.TMPTR65.UINT16[L]
+#define RSCAN0TMPTR65LL RSCAN0.TMPTR65.UINT8[LL]
+#define RSCAN0TMPTR65LH RSCAN0.TMPTR65.UINT8[LH]
+#define RSCAN0TMPTR65H RSCAN0.TMPTR65.UINT16[H]
+#define RSCAN0TMPTR65HL RSCAN0.TMPTR65.UINT8[HL]
+#define RSCAN0TMPTR65HH RSCAN0.TMPTR65.UINT8[HH]
+#define RSCAN0TMDF065 RSCAN0.TMDF065.UINT32
+#define RSCAN0TMDF065L RSCAN0.TMDF065.UINT16[L]
+#define RSCAN0TMDF065LL RSCAN0.TMDF065.UINT8[LL]
+#define RSCAN0TMDF065LH RSCAN0.TMDF065.UINT8[LH]
+#define RSCAN0TMDF065H RSCAN0.TMDF065.UINT16[H]
+#define RSCAN0TMDF065HL RSCAN0.TMDF065.UINT8[HL]
+#define RSCAN0TMDF065HH RSCAN0.TMDF065.UINT8[HH]
+#define RSCAN0TMDF165 RSCAN0.TMDF165.UINT32
+#define RSCAN0TMDF165L RSCAN0.TMDF165.UINT16[L]
+#define RSCAN0TMDF165LL RSCAN0.TMDF165.UINT8[LL]
+#define RSCAN0TMDF165LH RSCAN0.TMDF165.UINT8[LH]
+#define RSCAN0TMDF165H RSCAN0.TMDF165.UINT16[H]
+#define RSCAN0TMDF165HL RSCAN0.TMDF165.UINT8[HL]
+#define RSCAN0TMDF165HH RSCAN0.TMDF165.UINT8[HH]
+#define RSCAN0TMID66 RSCAN0.TMID66.UINT32
+#define RSCAN0TMID66L RSCAN0.TMID66.UINT16[L]
+#define RSCAN0TMID66LL RSCAN0.TMID66.UINT8[LL]
+#define RSCAN0TMID66LH RSCAN0.TMID66.UINT8[LH]
+#define RSCAN0TMID66H RSCAN0.TMID66.UINT16[H]
+#define RSCAN0TMID66HL RSCAN0.TMID66.UINT8[HL]
+#define RSCAN0TMID66HH RSCAN0.TMID66.UINT8[HH]
+#define RSCAN0TMPTR66 RSCAN0.TMPTR66.UINT32
+#define RSCAN0TMPTR66L RSCAN0.TMPTR66.UINT16[L]
+#define RSCAN0TMPTR66LL RSCAN0.TMPTR66.UINT8[LL]
+#define RSCAN0TMPTR66LH RSCAN0.TMPTR66.UINT8[LH]
+#define RSCAN0TMPTR66H RSCAN0.TMPTR66.UINT16[H]
+#define RSCAN0TMPTR66HL RSCAN0.TMPTR66.UINT8[HL]
+#define RSCAN0TMPTR66HH RSCAN0.TMPTR66.UINT8[HH]
+#define RSCAN0TMDF066 RSCAN0.TMDF066.UINT32
+#define RSCAN0TMDF066L RSCAN0.TMDF066.UINT16[L]
+#define RSCAN0TMDF066LL RSCAN0.TMDF066.UINT8[LL]
+#define RSCAN0TMDF066LH RSCAN0.TMDF066.UINT8[LH]
+#define RSCAN0TMDF066H RSCAN0.TMDF066.UINT16[H]
+#define RSCAN0TMDF066HL RSCAN0.TMDF066.UINT8[HL]
+#define RSCAN0TMDF066HH RSCAN0.TMDF066.UINT8[HH]
+#define RSCAN0TMDF166 RSCAN0.TMDF166.UINT32
+#define RSCAN0TMDF166L RSCAN0.TMDF166.UINT16[L]
+#define RSCAN0TMDF166LL RSCAN0.TMDF166.UINT8[LL]
+#define RSCAN0TMDF166LH RSCAN0.TMDF166.UINT8[LH]
+#define RSCAN0TMDF166H RSCAN0.TMDF166.UINT16[H]
+#define RSCAN0TMDF166HL RSCAN0.TMDF166.UINT8[HL]
+#define RSCAN0TMDF166HH RSCAN0.TMDF166.UINT8[HH]
+#define RSCAN0TMID67 RSCAN0.TMID67.UINT32
+#define RSCAN0TMID67L RSCAN0.TMID67.UINT16[L]
+#define RSCAN0TMID67LL RSCAN0.TMID67.UINT8[LL]
+#define RSCAN0TMID67LH RSCAN0.TMID67.UINT8[LH]
+#define RSCAN0TMID67H RSCAN0.TMID67.UINT16[H]
+#define RSCAN0TMID67HL RSCAN0.TMID67.UINT8[HL]
+#define RSCAN0TMID67HH RSCAN0.TMID67.UINT8[HH]
+#define RSCAN0TMPTR67 RSCAN0.TMPTR67.UINT32
+#define RSCAN0TMPTR67L RSCAN0.TMPTR67.UINT16[L]
+#define RSCAN0TMPTR67LL RSCAN0.TMPTR67.UINT8[LL]
+#define RSCAN0TMPTR67LH RSCAN0.TMPTR67.UINT8[LH]
+#define RSCAN0TMPTR67H RSCAN0.TMPTR67.UINT16[H]
+#define RSCAN0TMPTR67HL RSCAN0.TMPTR67.UINT8[HL]
+#define RSCAN0TMPTR67HH RSCAN0.TMPTR67.UINT8[HH]
+#define RSCAN0TMDF067 RSCAN0.TMDF067.UINT32
+#define RSCAN0TMDF067L RSCAN0.TMDF067.UINT16[L]
+#define RSCAN0TMDF067LL RSCAN0.TMDF067.UINT8[LL]
+#define RSCAN0TMDF067LH RSCAN0.TMDF067.UINT8[LH]
+#define RSCAN0TMDF067H RSCAN0.TMDF067.UINT16[H]
+#define RSCAN0TMDF067HL RSCAN0.TMDF067.UINT8[HL]
+#define RSCAN0TMDF067HH RSCAN0.TMDF067.UINT8[HH]
+#define RSCAN0TMDF167 RSCAN0.TMDF167.UINT32
+#define RSCAN0TMDF167L RSCAN0.TMDF167.UINT16[L]
+#define RSCAN0TMDF167LL RSCAN0.TMDF167.UINT8[LL]
+#define RSCAN0TMDF167LH RSCAN0.TMDF167.UINT8[LH]
+#define RSCAN0TMDF167H RSCAN0.TMDF167.UINT16[H]
+#define RSCAN0TMDF167HL RSCAN0.TMDF167.UINT8[HL]
+#define RSCAN0TMDF167HH RSCAN0.TMDF167.UINT8[HH]
+#define RSCAN0TMID68 RSCAN0.TMID68.UINT32
+#define RSCAN0TMID68L RSCAN0.TMID68.UINT16[L]
+#define RSCAN0TMID68LL RSCAN0.TMID68.UINT8[LL]
+#define RSCAN0TMID68LH RSCAN0.TMID68.UINT8[LH]
+#define RSCAN0TMID68H RSCAN0.TMID68.UINT16[H]
+#define RSCAN0TMID68HL RSCAN0.TMID68.UINT8[HL]
+#define RSCAN0TMID68HH RSCAN0.TMID68.UINT8[HH]
+#define RSCAN0TMPTR68 RSCAN0.TMPTR68.UINT32
+#define RSCAN0TMPTR68L RSCAN0.TMPTR68.UINT16[L]
+#define RSCAN0TMPTR68LL RSCAN0.TMPTR68.UINT8[LL]
+#define RSCAN0TMPTR68LH RSCAN0.TMPTR68.UINT8[LH]
+#define RSCAN0TMPTR68H RSCAN0.TMPTR68.UINT16[H]
+#define RSCAN0TMPTR68HL RSCAN0.TMPTR68.UINT8[HL]
+#define RSCAN0TMPTR68HH RSCAN0.TMPTR68.UINT8[HH]
+#define RSCAN0TMDF068 RSCAN0.TMDF068.UINT32
+#define RSCAN0TMDF068L RSCAN0.TMDF068.UINT16[L]
+#define RSCAN0TMDF068LL RSCAN0.TMDF068.UINT8[LL]
+#define RSCAN0TMDF068LH RSCAN0.TMDF068.UINT8[LH]
+#define RSCAN0TMDF068H RSCAN0.TMDF068.UINT16[H]
+#define RSCAN0TMDF068HL RSCAN0.TMDF068.UINT8[HL]
+#define RSCAN0TMDF068HH RSCAN0.TMDF068.UINT8[HH]
+#define RSCAN0TMDF168 RSCAN0.TMDF168.UINT32
+#define RSCAN0TMDF168L RSCAN0.TMDF168.UINT16[L]
+#define RSCAN0TMDF168LL RSCAN0.TMDF168.UINT8[LL]
+#define RSCAN0TMDF168LH RSCAN0.TMDF168.UINT8[LH]
+#define RSCAN0TMDF168H RSCAN0.TMDF168.UINT16[H]
+#define RSCAN0TMDF168HL RSCAN0.TMDF168.UINT8[HL]
+#define RSCAN0TMDF168HH RSCAN0.TMDF168.UINT8[HH]
+#define RSCAN0TMID69 RSCAN0.TMID69.UINT32
+#define RSCAN0TMID69L RSCAN0.TMID69.UINT16[L]
+#define RSCAN0TMID69LL RSCAN0.TMID69.UINT8[LL]
+#define RSCAN0TMID69LH RSCAN0.TMID69.UINT8[LH]
+#define RSCAN0TMID69H RSCAN0.TMID69.UINT16[H]
+#define RSCAN0TMID69HL RSCAN0.TMID69.UINT8[HL]
+#define RSCAN0TMID69HH RSCAN0.TMID69.UINT8[HH]
+#define RSCAN0TMPTR69 RSCAN0.TMPTR69.UINT32
+#define RSCAN0TMPTR69L RSCAN0.TMPTR69.UINT16[L]
+#define RSCAN0TMPTR69LL RSCAN0.TMPTR69.UINT8[LL]
+#define RSCAN0TMPTR69LH RSCAN0.TMPTR69.UINT8[LH]
+#define RSCAN0TMPTR69H RSCAN0.TMPTR69.UINT16[H]
+#define RSCAN0TMPTR69HL RSCAN0.TMPTR69.UINT8[HL]
+#define RSCAN0TMPTR69HH RSCAN0.TMPTR69.UINT8[HH]
+#define RSCAN0TMDF069 RSCAN0.TMDF069.UINT32
+#define RSCAN0TMDF069L RSCAN0.TMDF069.UINT16[L]
+#define RSCAN0TMDF069LL RSCAN0.TMDF069.UINT8[LL]
+#define RSCAN0TMDF069LH RSCAN0.TMDF069.UINT8[LH]
+#define RSCAN0TMDF069H RSCAN0.TMDF069.UINT16[H]
+#define RSCAN0TMDF069HL RSCAN0.TMDF069.UINT8[HL]
+#define RSCAN0TMDF069HH RSCAN0.TMDF069.UINT8[HH]
+#define RSCAN0TMDF169 RSCAN0.TMDF169.UINT32
+#define RSCAN0TMDF169L RSCAN0.TMDF169.UINT16[L]
+#define RSCAN0TMDF169LL RSCAN0.TMDF169.UINT8[LL]
+#define RSCAN0TMDF169LH RSCAN0.TMDF169.UINT8[LH]
+#define RSCAN0TMDF169H RSCAN0.TMDF169.UINT16[H]
+#define RSCAN0TMDF169HL RSCAN0.TMDF169.UINT8[HL]
+#define RSCAN0TMDF169HH RSCAN0.TMDF169.UINT8[HH]
+#define RSCAN0TMID70 RSCAN0.TMID70.UINT32
+#define RSCAN0TMID70L RSCAN0.TMID70.UINT16[L]
+#define RSCAN0TMID70LL RSCAN0.TMID70.UINT8[LL]
+#define RSCAN0TMID70LH RSCAN0.TMID70.UINT8[LH]
+#define RSCAN0TMID70H RSCAN0.TMID70.UINT16[H]
+#define RSCAN0TMID70HL RSCAN0.TMID70.UINT8[HL]
+#define RSCAN0TMID70HH RSCAN0.TMID70.UINT8[HH]
+#define RSCAN0TMPTR70 RSCAN0.TMPTR70.UINT32
+#define RSCAN0TMPTR70L RSCAN0.TMPTR70.UINT16[L]
+#define RSCAN0TMPTR70LL RSCAN0.TMPTR70.UINT8[LL]
+#define RSCAN0TMPTR70LH RSCAN0.TMPTR70.UINT8[LH]
+#define RSCAN0TMPTR70H RSCAN0.TMPTR70.UINT16[H]
+#define RSCAN0TMPTR70HL RSCAN0.TMPTR70.UINT8[HL]
+#define RSCAN0TMPTR70HH RSCAN0.TMPTR70.UINT8[HH]
+#define RSCAN0TMDF070 RSCAN0.TMDF070.UINT32
+#define RSCAN0TMDF070L RSCAN0.TMDF070.UINT16[L]
+#define RSCAN0TMDF070LL RSCAN0.TMDF070.UINT8[LL]
+#define RSCAN0TMDF070LH RSCAN0.TMDF070.UINT8[LH]
+#define RSCAN0TMDF070H RSCAN0.TMDF070.UINT16[H]
+#define RSCAN0TMDF070HL RSCAN0.TMDF070.UINT8[HL]
+#define RSCAN0TMDF070HH RSCAN0.TMDF070.UINT8[HH]
+#define RSCAN0TMDF170 RSCAN0.TMDF170.UINT32
+#define RSCAN0TMDF170L RSCAN0.TMDF170.UINT16[L]
+#define RSCAN0TMDF170LL RSCAN0.TMDF170.UINT8[LL]
+#define RSCAN0TMDF170LH RSCAN0.TMDF170.UINT8[LH]
+#define RSCAN0TMDF170H RSCAN0.TMDF170.UINT16[H]
+#define RSCAN0TMDF170HL RSCAN0.TMDF170.UINT8[HL]
+#define RSCAN0TMDF170HH RSCAN0.TMDF170.UINT8[HH]
+#define RSCAN0TMID71 RSCAN0.TMID71.UINT32
+#define RSCAN0TMID71L RSCAN0.TMID71.UINT16[L]
+#define RSCAN0TMID71LL RSCAN0.TMID71.UINT8[LL]
+#define RSCAN0TMID71LH RSCAN0.TMID71.UINT8[LH]
+#define RSCAN0TMID71H RSCAN0.TMID71.UINT16[H]
+#define RSCAN0TMID71HL RSCAN0.TMID71.UINT8[HL]
+#define RSCAN0TMID71HH RSCAN0.TMID71.UINT8[HH]
+#define RSCAN0TMPTR71 RSCAN0.TMPTR71.UINT32
+#define RSCAN0TMPTR71L RSCAN0.TMPTR71.UINT16[L]
+#define RSCAN0TMPTR71LL RSCAN0.TMPTR71.UINT8[LL]
+#define RSCAN0TMPTR71LH RSCAN0.TMPTR71.UINT8[LH]
+#define RSCAN0TMPTR71H RSCAN0.TMPTR71.UINT16[H]
+#define RSCAN0TMPTR71HL RSCAN0.TMPTR71.UINT8[HL]
+#define RSCAN0TMPTR71HH RSCAN0.TMPTR71.UINT8[HH]
+#define RSCAN0TMDF071 RSCAN0.TMDF071.UINT32
+#define RSCAN0TMDF071L RSCAN0.TMDF071.UINT16[L]
+#define RSCAN0TMDF071LL RSCAN0.TMDF071.UINT8[LL]
+#define RSCAN0TMDF071LH RSCAN0.TMDF071.UINT8[LH]
+#define RSCAN0TMDF071H RSCAN0.TMDF071.UINT16[H]
+#define RSCAN0TMDF071HL RSCAN0.TMDF071.UINT8[HL]
+#define RSCAN0TMDF071HH RSCAN0.TMDF071.UINT8[HH]
+#define RSCAN0TMDF171 RSCAN0.TMDF171.UINT32
+#define RSCAN0TMDF171L RSCAN0.TMDF171.UINT16[L]
+#define RSCAN0TMDF171LL RSCAN0.TMDF171.UINT8[LL]
+#define RSCAN0TMDF171LH RSCAN0.TMDF171.UINT8[LH]
+#define RSCAN0TMDF171H RSCAN0.TMDF171.UINT16[H]
+#define RSCAN0TMDF171HL RSCAN0.TMDF171.UINT8[HL]
+#define RSCAN0TMDF171HH RSCAN0.TMDF171.UINT8[HH]
+#define RSCAN0TMID72 RSCAN0.TMID72.UINT32
+#define RSCAN0TMID72L RSCAN0.TMID72.UINT16[L]
+#define RSCAN0TMID72LL RSCAN0.TMID72.UINT8[LL]
+#define RSCAN0TMID72LH RSCAN0.TMID72.UINT8[LH]
+#define RSCAN0TMID72H RSCAN0.TMID72.UINT16[H]
+#define RSCAN0TMID72HL RSCAN0.TMID72.UINT8[HL]
+#define RSCAN0TMID72HH RSCAN0.TMID72.UINT8[HH]
+#define RSCAN0TMPTR72 RSCAN0.TMPTR72.UINT32
+#define RSCAN0TMPTR72L RSCAN0.TMPTR72.UINT16[L]
+#define RSCAN0TMPTR72LL RSCAN0.TMPTR72.UINT8[LL]
+#define RSCAN0TMPTR72LH RSCAN0.TMPTR72.UINT8[LH]
+#define RSCAN0TMPTR72H RSCAN0.TMPTR72.UINT16[H]
+#define RSCAN0TMPTR72HL RSCAN0.TMPTR72.UINT8[HL]
+#define RSCAN0TMPTR72HH RSCAN0.TMPTR72.UINT8[HH]
+#define RSCAN0TMDF072 RSCAN0.TMDF072.UINT32
+#define RSCAN0TMDF072L RSCAN0.TMDF072.UINT16[L]
+#define RSCAN0TMDF072LL RSCAN0.TMDF072.UINT8[LL]
+#define RSCAN0TMDF072LH RSCAN0.TMDF072.UINT8[LH]
+#define RSCAN0TMDF072H RSCAN0.TMDF072.UINT16[H]
+#define RSCAN0TMDF072HL RSCAN0.TMDF072.UINT8[HL]
+#define RSCAN0TMDF072HH RSCAN0.TMDF072.UINT8[HH]
+#define RSCAN0TMDF172 RSCAN0.TMDF172.UINT32
+#define RSCAN0TMDF172L RSCAN0.TMDF172.UINT16[L]
+#define RSCAN0TMDF172LL RSCAN0.TMDF172.UINT8[LL]
+#define RSCAN0TMDF172LH RSCAN0.TMDF172.UINT8[LH]
+#define RSCAN0TMDF172H RSCAN0.TMDF172.UINT16[H]
+#define RSCAN0TMDF172HL RSCAN0.TMDF172.UINT8[HL]
+#define RSCAN0TMDF172HH RSCAN0.TMDF172.UINT8[HH]
+#define RSCAN0TMID73 RSCAN0.TMID73.UINT32
+#define RSCAN0TMID73L RSCAN0.TMID73.UINT16[L]
+#define RSCAN0TMID73LL RSCAN0.TMID73.UINT8[LL]
+#define RSCAN0TMID73LH RSCAN0.TMID73.UINT8[LH]
+#define RSCAN0TMID73H RSCAN0.TMID73.UINT16[H]
+#define RSCAN0TMID73HL RSCAN0.TMID73.UINT8[HL]
+#define RSCAN0TMID73HH RSCAN0.TMID73.UINT8[HH]
+#define RSCAN0TMPTR73 RSCAN0.TMPTR73.UINT32
+#define RSCAN0TMPTR73L RSCAN0.TMPTR73.UINT16[L]
+#define RSCAN0TMPTR73LL RSCAN0.TMPTR73.UINT8[LL]
+#define RSCAN0TMPTR73LH RSCAN0.TMPTR73.UINT8[LH]
+#define RSCAN0TMPTR73H RSCAN0.TMPTR73.UINT16[H]
+#define RSCAN0TMPTR73HL RSCAN0.TMPTR73.UINT8[HL]
+#define RSCAN0TMPTR73HH RSCAN0.TMPTR73.UINT8[HH]
+#define RSCAN0TMDF073 RSCAN0.TMDF073.UINT32
+#define RSCAN0TMDF073L RSCAN0.TMDF073.UINT16[L]
+#define RSCAN0TMDF073LL RSCAN0.TMDF073.UINT8[LL]
+#define RSCAN0TMDF073LH RSCAN0.TMDF073.UINT8[LH]
+#define RSCAN0TMDF073H RSCAN0.TMDF073.UINT16[H]
+#define RSCAN0TMDF073HL RSCAN0.TMDF073.UINT8[HL]
+#define RSCAN0TMDF073HH RSCAN0.TMDF073.UINT8[HH]
+#define RSCAN0TMDF173 RSCAN0.TMDF173.UINT32
+#define RSCAN0TMDF173L RSCAN0.TMDF173.UINT16[L]
+#define RSCAN0TMDF173LL RSCAN0.TMDF173.UINT8[LL]
+#define RSCAN0TMDF173LH RSCAN0.TMDF173.UINT8[LH]
+#define RSCAN0TMDF173H RSCAN0.TMDF173.UINT16[H]
+#define RSCAN0TMDF173HL RSCAN0.TMDF173.UINT8[HL]
+#define RSCAN0TMDF173HH RSCAN0.TMDF173.UINT8[HH]
+#define RSCAN0TMID74 RSCAN0.TMID74.UINT32
+#define RSCAN0TMID74L RSCAN0.TMID74.UINT16[L]
+#define RSCAN0TMID74LL RSCAN0.TMID74.UINT8[LL]
+#define RSCAN0TMID74LH RSCAN0.TMID74.UINT8[LH]
+#define RSCAN0TMID74H RSCAN0.TMID74.UINT16[H]
+#define RSCAN0TMID74HL RSCAN0.TMID74.UINT8[HL]
+#define RSCAN0TMID74HH RSCAN0.TMID74.UINT8[HH]
+#define RSCAN0TMPTR74 RSCAN0.TMPTR74.UINT32
+#define RSCAN0TMPTR74L RSCAN0.TMPTR74.UINT16[L]
+#define RSCAN0TMPTR74LL RSCAN0.TMPTR74.UINT8[LL]
+#define RSCAN0TMPTR74LH RSCAN0.TMPTR74.UINT8[LH]
+#define RSCAN0TMPTR74H RSCAN0.TMPTR74.UINT16[H]
+#define RSCAN0TMPTR74HL RSCAN0.TMPTR74.UINT8[HL]
+#define RSCAN0TMPTR74HH RSCAN0.TMPTR74.UINT8[HH]
+#define RSCAN0TMDF074 RSCAN0.TMDF074.UINT32
+#define RSCAN0TMDF074L RSCAN0.TMDF074.UINT16[L]
+#define RSCAN0TMDF074LL RSCAN0.TMDF074.UINT8[LL]
+#define RSCAN0TMDF074LH RSCAN0.TMDF074.UINT8[LH]
+#define RSCAN0TMDF074H RSCAN0.TMDF074.UINT16[H]
+#define RSCAN0TMDF074HL RSCAN0.TMDF074.UINT8[HL]
+#define RSCAN0TMDF074HH RSCAN0.TMDF074.UINT8[HH]
+#define RSCAN0TMDF174 RSCAN0.TMDF174.UINT32
+#define RSCAN0TMDF174L RSCAN0.TMDF174.UINT16[L]
+#define RSCAN0TMDF174LL RSCAN0.TMDF174.UINT8[LL]
+#define RSCAN0TMDF174LH RSCAN0.TMDF174.UINT8[LH]
+#define RSCAN0TMDF174H RSCAN0.TMDF174.UINT16[H]
+#define RSCAN0TMDF174HL RSCAN0.TMDF174.UINT8[HL]
+#define RSCAN0TMDF174HH RSCAN0.TMDF174.UINT8[HH]
+#define RSCAN0TMID75 RSCAN0.TMID75.UINT32
+#define RSCAN0TMID75L RSCAN0.TMID75.UINT16[L]
+#define RSCAN0TMID75LL RSCAN0.TMID75.UINT8[LL]
+#define RSCAN0TMID75LH RSCAN0.TMID75.UINT8[LH]
+#define RSCAN0TMID75H RSCAN0.TMID75.UINT16[H]
+#define RSCAN0TMID75HL RSCAN0.TMID75.UINT8[HL]
+#define RSCAN0TMID75HH RSCAN0.TMID75.UINT8[HH]
+#define RSCAN0TMPTR75 RSCAN0.TMPTR75.UINT32
+#define RSCAN0TMPTR75L RSCAN0.TMPTR75.UINT16[L]
+#define RSCAN0TMPTR75LL RSCAN0.TMPTR75.UINT8[LL]
+#define RSCAN0TMPTR75LH RSCAN0.TMPTR75.UINT8[LH]
+#define RSCAN0TMPTR75H RSCAN0.TMPTR75.UINT16[H]
+#define RSCAN0TMPTR75HL RSCAN0.TMPTR75.UINT8[HL]
+#define RSCAN0TMPTR75HH RSCAN0.TMPTR75.UINT8[HH]
+#define RSCAN0TMDF075 RSCAN0.TMDF075.UINT32
+#define RSCAN0TMDF075L RSCAN0.TMDF075.UINT16[L]
+#define RSCAN0TMDF075LL RSCAN0.TMDF075.UINT8[LL]
+#define RSCAN0TMDF075LH RSCAN0.TMDF075.UINT8[LH]
+#define RSCAN0TMDF075H RSCAN0.TMDF075.UINT16[H]
+#define RSCAN0TMDF075HL RSCAN0.TMDF075.UINT8[HL]
+#define RSCAN0TMDF075HH RSCAN0.TMDF075.UINT8[HH]
+#define RSCAN0TMDF175 RSCAN0.TMDF175.UINT32
+#define RSCAN0TMDF175L RSCAN0.TMDF175.UINT16[L]
+#define RSCAN0TMDF175LL RSCAN0.TMDF175.UINT8[LL]
+#define RSCAN0TMDF175LH RSCAN0.TMDF175.UINT8[LH]
+#define RSCAN0TMDF175H RSCAN0.TMDF175.UINT16[H]
+#define RSCAN0TMDF175HL RSCAN0.TMDF175.UINT8[HL]
+#define RSCAN0TMDF175HH RSCAN0.TMDF175.UINT8[HH]
+#define RSCAN0TMID76 RSCAN0.TMID76.UINT32
+#define RSCAN0TMID76L RSCAN0.TMID76.UINT16[L]
+#define RSCAN0TMID76LL RSCAN0.TMID76.UINT8[LL]
+#define RSCAN0TMID76LH RSCAN0.TMID76.UINT8[LH]
+#define RSCAN0TMID76H RSCAN0.TMID76.UINT16[H]
+#define RSCAN0TMID76HL RSCAN0.TMID76.UINT8[HL]
+#define RSCAN0TMID76HH RSCAN0.TMID76.UINT8[HH]
+#define RSCAN0TMPTR76 RSCAN0.TMPTR76.UINT32
+#define RSCAN0TMPTR76L RSCAN0.TMPTR76.UINT16[L]
+#define RSCAN0TMPTR76LL RSCAN0.TMPTR76.UINT8[LL]
+#define RSCAN0TMPTR76LH RSCAN0.TMPTR76.UINT8[LH]
+#define RSCAN0TMPTR76H RSCAN0.TMPTR76.UINT16[H]
+#define RSCAN0TMPTR76HL RSCAN0.TMPTR76.UINT8[HL]
+#define RSCAN0TMPTR76HH RSCAN0.TMPTR76.UINT8[HH]
+#define RSCAN0TMDF076 RSCAN0.TMDF076.UINT32
+#define RSCAN0TMDF076L RSCAN0.TMDF076.UINT16[L]
+#define RSCAN0TMDF076LL RSCAN0.TMDF076.UINT8[LL]
+#define RSCAN0TMDF076LH RSCAN0.TMDF076.UINT8[LH]
+#define RSCAN0TMDF076H RSCAN0.TMDF076.UINT16[H]
+#define RSCAN0TMDF076HL RSCAN0.TMDF076.UINT8[HL]
+#define RSCAN0TMDF076HH RSCAN0.TMDF076.UINT8[HH]
+#define RSCAN0TMDF176 RSCAN0.TMDF176.UINT32
+#define RSCAN0TMDF176L RSCAN0.TMDF176.UINT16[L]
+#define RSCAN0TMDF176LL RSCAN0.TMDF176.UINT8[LL]
+#define RSCAN0TMDF176LH RSCAN0.TMDF176.UINT8[LH]
+#define RSCAN0TMDF176H RSCAN0.TMDF176.UINT16[H]
+#define RSCAN0TMDF176HL RSCAN0.TMDF176.UINT8[HL]
+#define RSCAN0TMDF176HH RSCAN0.TMDF176.UINT8[HH]
+#define RSCAN0TMID77 RSCAN0.TMID77.UINT32
+#define RSCAN0TMID77L RSCAN0.TMID77.UINT16[L]
+#define RSCAN0TMID77LL RSCAN0.TMID77.UINT8[LL]
+#define RSCAN0TMID77LH RSCAN0.TMID77.UINT8[LH]
+#define RSCAN0TMID77H RSCAN0.TMID77.UINT16[H]
+#define RSCAN0TMID77HL RSCAN0.TMID77.UINT8[HL]
+#define RSCAN0TMID77HH RSCAN0.TMID77.UINT8[HH]
+#define RSCAN0TMPTR77 RSCAN0.TMPTR77.UINT32
+#define RSCAN0TMPTR77L RSCAN0.TMPTR77.UINT16[L]
+#define RSCAN0TMPTR77LL RSCAN0.TMPTR77.UINT8[LL]
+#define RSCAN0TMPTR77LH RSCAN0.TMPTR77.UINT8[LH]
+#define RSCAN0TMPTR77H RSCAN0.TMPTR77.UINT16[H]
+#define RSCAN0TMPTR77HL RSCAN0.TMPTR77.UINT8[HL]
+#define RSCAN0TMPTR77HH RSCAN0.TMPTR77.UINT8[HH]
+#define RSCAN0TMDF077 RSCAN0.TMDF077.UINT32
+#define RSCAN0TMDF077L RSCAN0.TMDF077.UINT16[L]
+#define RSCAN0TMDF077LL RSCAN0.TMDF077.UINT8[LL]
+#define RSCAN0TMDF077LH RSCAN0.TMDF077.UINT8[LH]
+#define RSCAN0TMDF077H RSCAN0.TMDF077.UINT16[H]
+#define RSCAN0TMDF077HL RSCAN0.TMDF077.UINT8[HL]
+#define RSCAN0TMDF077HH RSCAN0.TMDF077.UINT8[HH]
+#define RSCAN0TMDF177 RSCAN0.TMDF177.UINT32
+#define RSCAN0TMDF177L RSCAN0.TMDF177.UINT16[L]
+#define RSCAN0TMDF177LL RSCAN0.TMDF177.UINT8[LL]
+#define RSCAN0TMDF177LH RSCAN0.TMDF177.UINT8[LH]
+#define RSCAN0TMDF177H RSCAN0.TMDF177.UINT16[H]
+#define RSCAN0TMDF177HL RSCAN0.TMDF177.UINT8[HL]
+#define RSCAN0TMDF177HH RSCAN0.TMDF177.UINT8[HH]
+#define RSCAN0TMID78 RSCAN0.TMID78.UINT32
+#define RSCAN0TMID78L RSCAN0.TMID78.UINT16[L]
+#define RSCAN0TMID78LL RSCAN0.TMID78.UINT8[LL]
+#define RSCAN0TMID78LH RSCAN0.TMID78.UINT8[LH]
+#define RSCAN0TMID78H RSCAN0.TMID78.UINT16[H]
+#define RSCAN0TMID78HL RSCAN0.TMID78.UINT8[HL]
+#define RSCAN0TMID78HH RSCAN0.TMID78.UINT8[HH]
+#define RSCAN0TMPTR78 RSCAN0.TMPTR78.UINT32
+#define RSCAN0TMPTR78L RSCAN0.TMPTR78.UINT16[L]
+#define RSCAN0TMPTR78LL RSCAN0.TMPTR78.UINT8[LL]
+#define RSCAN0TMPTR78LH RSCAN0.TMPTR78.UINT8[LH]
+#define RSCAN0TMPTR78H RSCAN0.TMPTR78.UINT16[H]
+#define RSCAN0TMPTR78HL RSCAN0.TMPTR78.UINT8[HL]
+#define RSCAN0TMPTR78HH RSCAN0.TMPTR78.UINT8[HH]
+#define RSCAN0TMDF078 RSCAN0.TMDF078.UINT32
+#define RSCAN0TMDF078L RSCAN0.TMDF078.UINT16[L]
+#define RSCAN0TMDF078LL RSCAN0.TMDF078.UINT8[LL]
+#define RSCAN0TMDF078LH RSCAN0.TMDF078.UINT8[LH]
+#define RSCAN0TMDF078H RSCAN0.TMDF078.UINT16[H]
+#define RSCAN0TMDF078HL RSCAN0.TMDF078.UINT8[HL]
+#define RSCAN0TMDF078HH RSCAN0.TMDF078.UINT8[HH]
+#define RSCAN0TMDF178 RSCAN0.TMDF178.UINT32
+#define RSCAN0TMDF178L RSCAN0.TMDF178.UINT16[L]
+#define RSCAN0TMDF178LL RSCAN0.TMDF178.UINT8[LL]
+#define RSCAN0TMDF178LH RSCAN0.TMDF178.UINT8[LH]
+#define RSCAN0TMDF178H RSCAN0.TMDF178.UINT16[H]
+#define RSCAN0TMDF178HL RSCAN0.TMDF178.UINT8[HL]
+#define RSCAN0TMDF178HH RSCAN0.TMDF178.UINT8[HH]
+#define RSCAN0TMID79 RSCAN0.TMID79.UINT32
+#define RSCAN0TMID79L RSCAN0.TMID79.UINT16[L]
+#define RSCAN0TMID79LL RSCAN0.TMID79.UINT8[LL]
+#define RSCAN0TMID79LH RSCAN0.TMID79.UINT8[LH]
+#define RSCAN0TMID79H RSCAN0.TMID79.UINT16[H]
+#define RSCAN0TMID79HL RSCAN0.TMID79.UINT8[HL]
+#define RSCAN0TMID79HH RSCAN0.TMID79.UINT8[HH]
+#define RSCAN0TMPTR79 RSCAN0.TMPTR79.UINT32
+#define RSCAN0TMPTR79L RSCAN0.TMPTR79.UINT16[L]
+#define RSCAN0TMPTR79LL RSCAN0.TMPTR79.UINT8[LL]
+#define RSCAN0TMPTR79LH RSCAN0.TMPTR79.UINT8[LH]
+#define RSCAN0TMPTR79H RSCAN0.TMPTR79.UINT16[H]
+#define RSCAN0TMPTR79HL RSCAN0.TMPTR79.UINT8[HL]
+#define RSCAN0TMPTR79HH RSCAN0.TMPTR79.UINT8[HH]
+#define RSCAN0TMDF079 RSCAN0.TMDF079.UINT32
+#define RSCAN0TMDF079L RSCAN0.TMDF079.UINT16[L]
+#define RSCAN0TMDF079LL RSCAN0.TMDF079.UINT8[LL]
+#define RSCAN0TMDF079LH RSCAN0.TMDF079.UINT8[LH]
+#define RSCAN0TMDF079H RSCAN0.TMDF079.UINT16[H]
+#define RSCAN0TMDF079HL RSCAN0.TMDF079.UINT8[HL]
+#define RSCAN0TMDF079HH RSCAN0.TMDF079.UINT8[HH]
+#define RSCAN0TMDF179 RSCAN0.TMDF179.UINT32
+#define RSCAN0TMDF179L RSCAN0.TMDF179.UINT16[L]
+#define RSCAN0TMDF179LL RSCAN0.TMDF179.UINT8[LL]
+#define RSCAN0TMDF179LH RSCAN0.TMDF179.UINT8[LH]
+#define RSCAN0TMDF179H RSCAN0.TMDF179.UINT16[H]
+#define RSCAN0TMDF179HL RSCAN0.TMDF179.UINT8[HL]
+#define RSCAN0TMDF179HH RSCAN0.TMDF179.UINT8[HH]
+#define RSCAN0THLACC0 RSCAN0.THLACC0.UINT32
+#define RSCAN0THLACC0L RSCAN0.THLACC0.UINT16[L]
+#define RSCAN0THLACC0LL RSCAN0.THLACC0.UINT8[LL]
+#define RSCAN0THLACC0LH RSCAN0.THLACC0.UINT8[LH]
+#define RSCAN0THLACC0H RSCAN0.THLACC0.UINT16[H]
+#define RSCAN0THLACC0HL RSCAN0.THLACC0.UINT8[HL]
+#define RSCAN0THLACC0HH RSCAN0.THLACC0.UINT8[HH]
+#define RSCAN0THLACC1 RSCAN0.THLACC1.UINT32
+#define RSCAN0THLACC1L RSCAN0.THLACC1.UINT16[L]
+#define RSCAN0THLACC1LL RSCAN0.THLACC1.UINT8[LL]
+#define RSCAN0THLACC1LH RSCAN0.THLACC1.UINT8[LH]
+#define RSCAN0THLACC1H RSCAN0.THLACC1.UINT16[H]
+#define RSCAN0THLACC1HL RSCAN0.THLACC1.UINT8[HL]
+#define RSCAN0THLACC1HH RSCAN0.THLACC1.UINT8[HH]
+#define RSCAN0THLACC2 RSCAN0.THLACC2.UINT32
+#define RSCAN0THLACC2L RSCAN0.THLACC2.UINT16[L]
+#define RSCAN0THLACC2LL RSCAN0.THLACC2.UINT8[LL]
+#define RSCAN0THLACC2LH RSCAN0.THLACC2.UINT8[LH]
+#define RSCAN0THLACC2H RSCAN0.THLACC2.UINT16[H]
+#define RSCAN0THLACC2HL RSCAN0.THLACC2.UINT8[HL]
+#define RSCAN0THLACC2HH RSCAN0.THLACC2.UINT8[HH]
+#define RSCAN0THLACC3 RSCAN0.THLACC3.UINT32
+#define RSCAN0THLACC3L RSCAN0.THLACC3.UINT16[L]
+#define RSCAN0THLACC3LL RSCAN0.THLACC3.UINT8[LL]
+#define RSCAN0THLACC3LH RSCAN0.THLACC3.UINT8[LH]
+#define RSCAN0THLACC3H RSCAN0.THLACC3.UINT16[H]
+#define RSCAN0THLACC3HL RSCAN0.THLACC3.UINT8[HL]
+#define RSCAN0THLACC3HH RSCAN0.THLACC3.UINT8[HH]
+#define RSCAN0THLACC4 RSCAN0.THLACC4.UINT32
+#define RSCAN0THLACC4L RSCAN0.THLACC4.UINT16[L]
+#define RSCAN0THLACC4LL RSCAN0.THLACC4.UINT8[LL]
+#define RSCAN0THLACC4LH RSCAN0.THLACC4.UINT8[LH]
+#define RSCAN0THLACC4H RSCAN0.THLACC4.UINT16[H]
+#define RSCAN0THLACC4HL RSCAN0.THLACC4.UINT8[HL]
+#define RSCAN0THLACC4HH RSCAN0.THLACC4.UINT8[HH]
+/* <-SEC M1.10.1 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,205 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rspi_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef RSPI_IODEFINE_H
+#define RSPI_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+#include "reg32_t.h"
+
+struct st_rspi
+{ /* RSPI */
+ volatile uint8_t SPCR; /* SPCR */
+ volatile uint8_t SSLP; /* SSLP */
+ volatile uint8_t SPPCR; /* SPPCR */
+ volatile uint8_t SPSR; /* SPSR */
+ union reg32_t SPDR; /* SPDR */
+
+ volatile uint8_t SPSCR; /* SPSCR */
+ volatile uint8_t SPSSR; /* SPSSR */
+ volatile uint8_t SPBR; /* SPBR */
+ volatile uint8_t SPDCR; /* SPDCR */
+ volatile uint8_t SPCKD; /* SPCKD */
+ volatile uint8_t SSLND; /* SSLND */
+ volatile uint8_t SPND; /* SPND */
+ volatile uint8_t dummy1[1]; /* */
+#define SPCMD_COUNT 4
+ volatile uint16_t SPCMD0; /* SPCMD0 */
+ volatile uint16_t SPCMD1; /* SPCMD1 */
+ volatile uint16_t SPCMD2; /* SPCMD2 */
+ volatile uint16_t SPCMD3; /* SPCMD3 */
+ volatile uint8_t dummy2[8]; /* */
+ volatile uint8_t SPBFCR; /* SPBFCR */
+ volatile uint8_t dummy3[1]; /* */
+ volatile uint16_t SPBFDR; /* SPBFDR */
+};
+
+
+#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */
+#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */
+#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */
+#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */
+#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */
+
+
+/* Start of channnel array defines of RSPI */
+
+/* Channnel array defines of RSPI */
+/*(Sample) value = RSPI[ channel ]->SPCR; */
+#define RSPI_COUNT 5
+#define RSPI_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of RSPI */
+
+
+#define SPCR_0 RSPI0.SPCR
+#define SSLP_0 RSPI0.SSLP
+#define SPPCR_0 RSPI0.SPPCR
+#define SPSR_0 RSPI0.SPSR
+#define SPDR_0 RSPI0.SPDR.UINT32
+#define SPDR_0L RSPI0.SPDR.UINT16[L]
+#define SPDR_0H RSPI0.SPDR.UINT16[H]
+#define SPDR_0LL RSPI0.SPDR.UINT8[LL]
+#define SPDR_0LH RSPI0.SPDR.UINT8[LH]
+#define SPDR_0HL RSPI0.SPDR.UINT8[HL]
+#define SPDR_0HH RSPI0.SPDR.UINT8[HH]
+#define SPSCR_0 RSPI0.SPSCR
+#define SPSSR_0 RSPI0.SPSSR
+#define SPBR_0 RSPI0.SPBR
+#define SPDCR_0 RSPI0.SPDCR
+#define SPCKD_0 RSPI0.SPCKD
+#define SSLND_0 RSPI0.SSLND
+#define SPND_0 RSPI0.SPND
+#define SPCMD0_0 RSPI0.SPCMD0
+#define SPCMD1_0 RSPI0.SPCMD1
+#define SPCMD2_0 RSPI0.SPCMD2
+#define SPCMD3_0 RSPI0.SPCMD3
+#define SPBFCR_0 RSPI0.SPBFCR
+#define SPBFDR_0 RSPI0.SPBFDR
+#define SPCR_1 RSPI1.SPCR
+#define SSLP_1 RSPI1.SSLP
+#define SPPCR_1 RSPI1.SPPCR
+#define SPSR_1 RSPI1.SPSR
+#define SPDR_1 RSPI1.SPDR.UINT32
+#define SPDR_1L RSPI1.SPDR.UINT16[L]
+#define SPDR_1H RSPI1.SPDR.UINT16[H]
+#define SPDR_1LL RSPI1.SPDR.UINT8[LL]
+#define SPDR_1LH RSPI1.SPDR.UINT8[LH]
+#define SPDR_1HL RSPI1.SPDR.UINT8[HL]
+#define SPDR_1HH RSPI1.SPDR.UINT8[HH]
+#define SPSCR_1 RSPI1.SPSCR
+#define SPSSR_1 RSPI1.SPSSR
+#define SPBR_1 RSPI1.SPBR
+#define SPDCR_1 RSPI1.SPDCR
+#define SPCKD_1 RSPI1.SPCKD
+#define SSLND_1 RSPI1.SSLND
+#define SPND_1 RSPI1.SPND
+#define SPCMD0_1 RSPI1.SPCMD0
+#define SPCMD1_1 RSPI1.SPCMD1
+#define SPCMD2_1 RSPI1.SPCMD2
+#define SPCMD3_1 RSPI1.SPCMD3
+#define SPBFCR_1 RSPI1.SPBFCR
+#define SPBFDR_1 RSPI1.SPBFDR
+#define SPCR_2 RSPI2.SPCR
+#define SSLP_2 RSPI2.SSLP
+#define SPPCR_2 RSPI2.SPPCR
+#define SPSR_2 RSPI2.SPSR
+#define SPDR_2 RSPI2.SPDR.UINT32
+#define SPDR_2L RSPI2.SPDR.UINT16[L]
+#define SPDR_2H RSPI2.SPDR.UINT16[H]
+#define SPDR_2LL RSPI2.SPDR.UINT8[LL]
+#define SPDR_2LH RSPI2.SPDR.UINT8[LH]
+#define SPDR_2HL RSPI2.SPDR.UINT8[HL]
+#define SPDR_2HH RSPI2.SPDR.UINT8[HH]
+#define SPSCR_2 RSPI2.SPSCR
+#define SPSSR_2 RSPI2.SPSSR
+#define SPBR_2 RSPI2.SPBR
+#define SPDCR_2 RSPI2.SPDCR
+#define SPCKD_2 RSPI2.SPCKD
+#define SSLND_2 RSPI2.SSLND
+#define SPND_2 RSPI2.SPND
+#define SPCMD0_2 RSPI2.SPCMD0
+#define SPCMD1_2 RSPI2.SPCMD1
+#define SPCMD2_2 RSPI2.SPCMD2
+#define SPCMD3_2 RSPI2.SPCMD3
+#define SPBFCR_2 RSPI2.SPBFCR
+#define SPBFDR_2 RSPI2.SPBFDR
+#define SPCR_3 RSPI3.SPCR
+#define SSLP_3 RSPI3.SSLP
+#define SPPCR_3 RSPI3.SPPCR
+#define SPSR_3 RSPI3.SPSR
+#define SPDR_3 RSPI3.SPDR.UINT32
+#define SPDR_3L RSPI3.SPDR.UINT16[L]
+#define SPDR_3H RSPI3.SPDR.UINT16[H]
+#define SPDR_3LL RSPI3.SPDR.UINT8[LL]
+#define SPDR_3LH RSPI3.SPDR.UINT8[LH]
+#define SPDR_3HL RSPI3.SPDR.UINT8[HL]
+#define SPDR_3HH RSPI3.SPDR.UINT8[HH]
+#define SPSCR_3 RSPI3.SPSCR
+#define SPSSR_3 RSPI3.SPSSR
+#define SPBR_3 RSPI3.SPBR
+#define SPDCR_3 RSPI3.SPDCR
+#define SPCKD_3 RSPI3.SPCKD
+#define SSLND_3 RSPI3.SSLND
+#define SPND_3 RSPI3.SPND
+#define SPCMD0_3 RSPI3.SPCMD0
+#define SPCMD1_3 RSPI3.SPCMD1
+#define SPCMD2_3 RSPI3.SPCMD2
+#define SPCMD3_3 RSPI3.SPCMD3
+#define SPBFCR_3 RSPI3.SPBFCR
+#define SPBFDR_3 RSPI3.SPBFDR
+#define SPCR_4 RSPI4.SPCR
+#define SSLP_4 RSPI4.SSLP
+#define SPPCR_4 RSPI4.SPPCR
+#define SPSR_4 RSPI4.SPSR
+#define SPDR_4 RSPI4.SPDR.UINT32
+#define SPDR_4L RSPI4.SPDR.UINT16[L]
+#define SPDR_4H RSPI4.SPDR.UINT16[H]
+#define SPDR_4LL RSPI4.SPDR.UINT8[LL]
+#define SPDR_4LH RSPI4.SPDR.UINT8[LH]
+#define SPDR_4HL RSPI4.SPDR.UINT8[HL]
+#define SPDR_4HH RSPI4.SPDR.UINT8[HH]
+#define SPSCR_4 RSPI4.SPSCR
+#define SPSSR_4 RSPI4.SPSSR
+#define SPBR_4 RSPI4.SPBR
+#define SPDCR_4 RSPI4.SPDCR
+#define SPCKD_4 RSPI4.SPCKD
+#define SSLND_4 RSPI4.SSLND
+#define SPND_4 RSPI4.SPND
+#define SPCMD0_4 RSPI4.SPCMD0
+#define SPCMD1_4 RSPI4.SPCMD1
+#define SPCMD2_4 RSPI4.SPCMD2
+#define SPCMD3_4 RSPI4.SPCMD3
+#define SPBFCR_4 RSPI4.SPBFCR
+#define SPBFDR_4 RSPI4.SPBFDR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,103 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rtc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef RTC_IODEFINE_H
+#define RTC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_rtc
+{ /* RTC */
+ volatile uint8_t R64CNT; /* R64CNT */
+ volatile uint8_t dummy537[1]; /* */
+ volatile uint8_t RSECCNT; /* RSECCNT */
+ volatile uint8_t dummy538[1]; /* */
+ volatile uint8_t RMINCNT; /* RMINCNT */
+ volatile uint8_t dummy539[1]; /* */
+ volatile uint8_t RHRCNT; /* RHRCNT */
+ volatile uint8_t dummy540[1]; /* */
+ volatile uint8_t RWKCNT; /* RWKCNT */
+ volatile uint8_t dummy541[1]; /* */
+ volatile uint8_t RDAYCNT; /* RDAYCNT */
+ volatile uint8_t dummy542[1]; /* */
+ volatile uint8_t RMONCNT; /* RMONCNT */
+ volatile uint8_t dummy543[1]; /* */
+ volatile uint16_t RYRCNT; /* RYRCNT */
+ volatile uint8_t RSECAR; /* RSECAR */
+ volatile uint8_t dummy544[1]; /* */
+ volatile uint8_t RMINAR; /* RMINAR */
+ volatile uint8_t dummy545[1]; /* */
+ volatile uint8_t RHRAR; /* RHRAR */
+ volatile uint8_t dummy546[1]; /* */
+ volatile uint8_t RWKAR; /* RWKAR */
+ volatile uint8_t dummy547[1]; /* */
+ volatile uint8_t RDAYAR; /* RDAYAR */
+ volatile uint8_t dummy548[1]; /* */
+ volatile uint8_t RMONAR; /* RMONAR */
+ volatile uint8_t dummy549[1]; /* */
+ volatile uint8_t RCR1; /* RCR1 */
+ volatile uint8_t dummy550[1]; /* */
+ volatile uint8_t RCR2; /* RCR2 */
+ volatile uint8_t dummy551[1]; /* */
+ volatile uint16_t RYRAR; /* RYRAR */
+ volatile uint8_t dummy552[2]; /* */
+ volatile uint8_t RCR3; /* RCR3 */
+ volatile uint8_t dummy553[1]; /* */
+ volatile uint8_t RCR5; /* RCR5 */
+ volatile uint8_t dummy554[3]; /* */
+ volatile uint16_t RFRH; /* RFRH */
+ volatile uint16_t RFRL; /* RFRL */
+};
+
+
+#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */
+
+
+#define RTCR64CNT RTC.R64CNT
+#define RTCRSECCNT RTC.RSECCNT
+#define RTCRMINCNT RTC.RMINCNT
+#define RTCRHRCNT RTC.RHRCNT
+#define RTCRWKCNT RTC.RWKCNT
+#define RTCRDAYCNT RTC.RDAYCNT
+#define RTCRMONCNT RTC.RMONCNT
+#define RTCRYRCNT RTC.RYRCNT
+#define RTCRSECAR RTC.RSECAR
+#define RTCRMINAR RTC.RMINAR
+#define RTCRHRAR RTC.RHRAR
+#define RTCRWKAR RTC.RWKAR
+#define RTCRDAYAR RTC.RDAYAR
+#define RTCRMONAR RTC.RMONAR
+#define RTCRCR1 RTC.RCR1
+#define RTCRCR2 RTC.RCR2
+#define RTCRYRAR RTC.RYRAR
+#define RTCRCR3 RTC.RCR3
+#define RTCRCR5 RTC.RCR5
+#define RTCRFRH RTC.RFRH
+#define RTCRFRL RTC.RFRL
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,183 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scif_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SCIF_IODEFINE_H
+#define SCIF_IODEFINE_H
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_scif
+{ /* SCIF */
+ volatile uint16_t SCSMR; /* SCSMR */
+ volatile uint8_t dummy1[2]; /* */
+ volatile uint8_t SCBRR; /* SCBRR */
+ volatile uint8_t dummy2[3]; /* */
+ volatile uint16_t SCSCR; /* SCSCR */
+ volatile uint8_t dummy3[2]; /* */
+ volatile uint8_t SCFTDR; /* SCFTDR */
+ volatile uint8_t dummy4[3]; /* */
+ volatile uint16_t SCFSR; /* SCFSR */
+ volatile uint8_t dummy5[2]; /* */
+ volatile uint8_t SCFRDR; /* SCFRDR */
+ volatile uint8_t dummy6[3]; /* */
+ volatile uint16_t SCFCR; /* SCFCR */
+ volatile uint8_t dummy7[2]; /* */
+ volatile uint16_t SCFDR; /* SCFDR */
+ volatile uint8_t dummy8[2]; /* */
+ volatile uint16_t SCSPTR; /* SCSPTR */
+ volatile uint8_t dummy9[2]; /* */
+ volatile uint16_t SCLSR; /* SCLSR */
+ volatile uint8_t dummy10[2]; /* */
+ volatile uint16_t SCEMR; /* SCEMR */
+};
+
+
+#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */
+#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */
+#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */
+#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */
+#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */
+#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */
+#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */
+#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */
+
+#define P_SCIF0 (0xE8007000uL) /* SCIF0 */
+#define P_SCIF1 (0xE8007800uL) /* SCIF1 */
+#define P_SCIF2 (0xE8008000uL) /* SCIF2 */
+#define P_SCIF3 (0xE8008800uL) /* SCIF3 */
+#define P_SCIF4 (0xE8009000uL) /* SCIF4 */
+#define P_SCIF5 (0xE8009800uL) /* SCIF5 */
+#define P_SCIF6 (0xE800A000uL) /* SCIF6 */
+#define P_SCIF7 (0xE800A800uL) /* SCIF7 */
+
+
+/* Start of channnel array defines of SCIF */
+
+/* Channnel array defines of SCIF */
+/*(Sample) value = SCIF[ channel ]->SCSMR; */
+#define SCIF_COUNT 8
+#define SCIF_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SCIF */
+
+
+#define SCSMR_0 SCIF0.SCSMR
+#define SCBRR_0 SCIF0.SCBRR
+#define SCSCR_0 SCIF0.SCSCR
+#define SCFTDR_0 SCIF0.SCFTDR
+#define SCFSR_0 SCIF0.SCFSR
+#define SCFRDR_0 SCIF0.SCFRDR
+#define SCFCR_0 SCIF0.SCFCR
+#define SCFDR_0 SCIF0.SCFDR
+#define SCSPTR_0 SCIF0.SCSPTR
+#define SCLSR_0 SCIF0.SCLSR
+#define SCEMR_0 SCIF0.SCEMR
+#define SCSMR_1 SCIF1.SCSMR
+#define SCBRR_1 SCIF1.SCBRR
+#define SCSCR_1 SCIF1.SCSCR
+#define SCFTDR_1 SCIF1.SCFTDR
+#define SCFSR_1 SCIF1.SCFSR
+#define SCFRDR_1 SCIF1.SCFRDR
+#define SCFCR_1 SCIF1.SCFCR
+#define SCFDR_1 SCIF1.SCFDR
+#define SCSPTR_1 SCIF1.SCSPTR
+#define SCLSR_1 SCIF1.SCLSR
+#define SCEMR_1 SCIF1.SCEMR
+#define SCSMR_2 SCIF2.SCSMR
+#define SCBRR_2 SCIF2.SCBRR
+#define SCSCR_2 SCIF2.SCSCR
+#define SCFTDR_2 SCIF2.SCFTDR
+#define SCFSR_2 SCIF2.SCFSR
+#define SCFRDR_2 SCIF2.SCFRDR
+#define SCFCR_2 SCIF2.SCFCR
+#define SCFDR_2 SCIF2.SCFDR
+#define SCSPTR_2 SCIF2.SCSPTR
+#define SCLSR_2 SCIF2.SCLSR
+#define SCEMR_2 SCIF2.SCEMR
+#define SCSMR_3 SCIF3.SCSMR
+#define SCBRR_3 SCIF3.SCBRR
+#define SCSCR_3 SCIF3.SCSCR
+#define SCFTDR_3 SCIF3.SCFTDR
+#define SCFSR_3 SCIF3.SCFSR
+#define SCFRDR_3 SCIF3.SCFRDR
+#define SCFCR_3 SCIF3.SCFCR
+#define SCFDR_3 SCIF3.SCFDR
+#define SCSPTR_3 SCIF3.SCSPTR
+#define SCLSR_3 SCIF3.SCLSR
+#define SCEMR_3 SCIF3.SCEMR
+#define SCSMR_4 SCIF4.SCSMR
+#define SCBRR_4 SCIF4.SCBRR
+#define SCSCR_4 SCIF4.SCSCR
+#define SCFTDR_4 SCIF4.SCFTDR
+#define SCFSR_4 SCIF4.SCFSR
+#define SCFRDR_4 SCIF4.SCFRDR
+#define SCFCR_4 SCIF4.SCFCR
+#define SCFDR_4 SCIF4.SCFDR
+#define SCSPTR_4 SCIF4.SCSPTR
+#define SCLSR_4 SCIF4.SCLSR
+#define SCEMR_4 SCIF4.SCEMR
+#define SCSMR_5 SCIF5.SCSMR
+#define SCBRR_5 SCIF5.SCBRR
+#define SCSCR_5 SCIF5.SCSCR
+#define SCFTDR_5 SCIF5.SCFTDR
+#define SCFSR_5 SCIF5.SCFSR
+#define SCFRDR_5 SCIF5.SCFRDR
+#define SCFCR_5 SCIF5.SCFCR
+#define SCFDR_5 SCIF5.SCFDR
+#define SCSPTR_5 SCIF5.SCSPTR
+#define SCLSR_5 SCIF5.SCLSR
+#define SCEMR_5 SCIF5.SCEMR
+#define SCSMR_6 SCIF6.SCSMR
+#define SCBRR_6 SCIF6.SCBRR
+#define SCSCR_6 SCIF6.SCSCR
+#define SCFTDR_6 SCIF6.SCFTDR
+#define SCFSR_6 SCIF6.SCFSR
+#define SCFRDR_6 SCIF6.SCFRDR
+#define SCFCR_6 SCIF6.SCFCR
+#define SCFDR_6 SCIF6.SCFDR
+#define SCSPTR_6 SCIF6.SCSPTR
+#define SCLSR_6 SCIF6.SCLSR
+#define SCEMR_6 SCIF6.SCEMR
+#define SCSMR_7 SCIF7.SCSMR
+#define SCBRR_7 SCIF7.SCBRR
+#define SCSCR_7 SCIF7.SCSCR
+#define SCFTDR_7 SCIF7.SCFTDR
+#define SCFSR_7 SCIF7.SCFSR
+#define SCFRDR_7 SCIF7.SCFRDR
+#define SCFCR_7 SCIF7.SCFCR
+#define SCFDR_7 SCIF7.SCFDR
+#define SCSPTR_7 SCIF7.SCSPTR
+#define SCLSR_7 SCIF7.SCLSR
+#define SCEMR_7 SCIF7.SCEMR
+/* <-SEC M1.10.1 */
+/* <-QAC 0857 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,88 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scim_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SCIM_IODEFINE_H
+#define SCIM_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_scim
+{ /* SCIM */
+ volatile uint8_t SMR; /* SMR */
+ volatile uint8_t BRR; /* BRR */
+ volatile uint8_t SCR; /* SCR */
+ volatile uint8_t TDR; /* TDR */
+ volatile uint8_t SSR; /* SSR */
+ volatile uint8_t RDR; /* RDR */
+ volatile uint8_t SCMR; /* SCMR */
+ volatile uint8_t SEMR; /* SEMR */
+ volatile uint8_t SNFR; /* SNFR */
+ volatile uint8_t dummy1[4]; /* */
+ volatile uint8_t SECR; /* SECR */
+};
+
+
+#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */
+#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */
+
+
+/* Start of channnel array defines of SCIM */
+
+/* Channnel array defines of SCIM */
+/*(Sample) value = SCIM[ channel ]->SMR; */
+#define SCIM_COUNT 2
+#define SCIM_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCIM0, &SCIM1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SCIM */
+
+
+#define SMR0 SCIM0.SMR
+#define BRR0 SCIM0.BRR
+#define SCR0 SCIM0.SCR
+#define TDR0 SCIM0.TDR
+#define SSR0 SCIM0.SSR
+#define RDR0 SCIM0.RDR
+#define SCMR0 SCIM0.SCMR
+#define SEMR0 SCIM0.SEMR
+#define SNFR0 SCIM0.SNFR
+#define SECR0 SCIM0.SECR
+#define SMR1 SCIM1.SMR
+#define BRR1 SCIM1.BRR
+#define SCR1 SCIM1.SCR
+#define TDR1 SCIM1.TDR
+#define SSR1 SCIM1.SSR
+#define RDR1 SCIM1.RDR
+#define SCMR1 SCIM1.SCMR
+#define SEMR1 SCIM1.SEMR
+#define SNFR1 SCIM1.SNFR
+#define SECR1 SCIM1.SECR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,809 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scux_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SCUX_IODEFINE_H
+#define SCUX_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_scux
+{ /* SCUX */
+/* start of struct st_scux_from_ipcir_ipc0_n */
+ volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
+ volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
+ volatile uint8_t dummy259[248]; /* */
+/* end of struct st_scux_from_ipcir_ipc0_n */
+/* start of struct st_scux_from_ipcir_ipc0_n */
+ volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */
+ volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */
+ volatile uint8_t dummy260[248]; /* */
+/* end of struct st_scux_from_ipcir_ipc0_n */
+/* start of struct st_scux_from_ipcir_ipc0_n */
+ volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */
+ volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */
+ volatile uint8_t dummy261[248]; /* */
+/* end of struct st_scux_from_ipcir_ipc0_n */
+/* start of struct st_scux_from_ipcir_ipc0_n */
+ volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */
+ volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */
+ volatile uint8_t dummy262[248]; /* */
+/* end of struct st_scux_from_ipcir_ipc0_n */
+/* start of struct st_scux_from_opcir_opc0_n */
+ volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
+ volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
+ volatile uint8_t dummy263[248]; /* */
+/* end of struct st_scux_from_opcir_opc0_n */
+/* start of struct st_scux_from_opcir_opc0_n */
+ volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */
+ volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */
+ volatile uint8_t dummy264[248]; /* */
+/* end of struct st_scux_from_opcir_opc0_n */
+/* start of struct st_scux_from_opcir_opc0_n */
+ volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */
+ volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */
+ volatile uint8_t dummy265[248]; /* */
+/* end of struct st_scux_from_opcir_opc0_n */
+/* start of struct st_scux_from_opcir_opc0_n */
+ volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */
+ volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */
+ volatile uint8_t dummy266[248]; /* */
+/* end of struct st_scux_from_opcir_opc0_n */
+/* start of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
+ volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
+ volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
+ volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
+ volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
+ volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
+ volatile uint8_t dummy267[4]; /* */
+ volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
+/* end of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint8_t dummy268[224]; /* */
+/* start of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */
+ volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */
+ volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */
+ volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */
+ volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */
+ volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */
+ volatile uint8_t dummy269[4]; /* */
+ volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */
+/* end of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint8_t dummy270[224]; /* */
+/* start of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */
+ volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */
+ volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */
+ volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */
+ volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */
+ volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */
+ volatile uint8_t dummy271[4]; /* */
+ volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */
+/* end of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint8_t dummy272[224]; /* */
+/* start of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */
+ volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */
+ volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */
+ volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */
+ volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */
+ volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */
+ volatile uint8_t dummy273[4]; /* */
+ volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */
+/* end of struct st_scux_from_ffdir_ffd0_n */
+ volatile uint8_t dummy274[224]; /* */
+/* start of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
+ volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
+ volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
+ volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
+ volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
+ volatile uint8_t dummy275[4]; /* */
+ volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
+/* end of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint8_t dummy276[228]; /* */
+/* start of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */
+ volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */
+ volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */
+ volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */
+ volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */
+ volatile uint8_t dummy277[4]; /* */
+ volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */
+/* end of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint8_t dummy278[228]; /* */
+/* start of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */
+ volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */
+ volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */
+ volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */
+ volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */
+ volatile uint8_t dummy279[4]; /* */
+ volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */
+/* end of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint8_t dummy280[228]; /* */
+/* start of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */
+ volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */
+ volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */
+ volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */
+ volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */
+ volatile uint8_t dummy281[4]; /* */
+ volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */
+/* end of struct st_scux_from_ffuir_ffu0_n */
+ volatile uint8_t dummy282[228]; /* */
+/* start of struct st_scux_from_srcir0_2src0_n */
+ volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
+ volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
+ volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
+ volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
+ volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
+ volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
+ volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
+ volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
+ volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
+ volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
+ volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
+ volatile uint8_t dummy283[4]; /* */
+ volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
+ volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
+ volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
+ volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
+ volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
+ volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
+ volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
+ volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
+ volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
+ volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
+ volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
+ volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
+ volatile uint8_t dummy284[4]; /* */
+ volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
+ volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
+/* end of struct st_scux_from_srcir0_2src0_n */
+ volatile uint8_t dummy285[148]; /* */
+/* start of struct st_scux_from_srcir0_2src0_n */
+ volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */
+ volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */
+ volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */
+ volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */
+ volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */
+ volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */
+ volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */
+ volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */
+ volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */
+ volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */
+ volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */
+ volatile uint8_t dummy286[4]; /* */
+ volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */
+ volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */
+ volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */
+ volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */
+ volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */
+ volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */
+ volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */
+ volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */
+ volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */
+ volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */
+ volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */
+ volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */
+ volatile uint8_t dummy287[4]; /* */
+ volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */
+ volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */
+/* end of struct st_scux_from_srcir0_2src0_n */
+ volatile uint8_t dummy288[148]; /* */
+/* start of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
+ volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
+ volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
+ volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
+ volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
+ volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
+ volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
+ volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
+ volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
+ volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
+ volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
+ volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
+ volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
+ volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
+ volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
+ volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
+ volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
+ volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
+ volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
+ volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
+ volatile uint8_t dummy289[4]; /* */
+ volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
+/* end of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint8_t dummy290[168]; /* */
+/* start of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */
+ volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */
+ volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */
+ volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */
+ volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */
+ volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */
+ volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */
+ volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */
+ volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */
+ volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */
+ volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */
+ volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */
+ volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */
+ volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */
+ volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */
+ volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */
+ volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */
+ volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */
+ volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */
+ volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */
+ volatile uint8_t dummy291[4]; /* */
+ volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */
+/* end of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint8_t dummy292[168]; /* */
+/* start of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */
+ volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */
+ volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */
+ volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */
+ volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */
+ volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */
+ volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */
+ volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */
+ volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */
+ volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */
+ volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */
+ volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */
+ volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */
+ volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */
+ volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */
+ volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */
+ volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */
+ volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */
+ volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */
+ volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */
+ volatile uint8_t dummy293[4]; /* */
+ volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */
+/* end of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint8_t dummy294[168]; /* */
+/* start of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */
+ volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */
+ volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */
+ volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */
+ volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */
+ volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */
+ volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */
+ volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */
+ volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */
+ volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */
+ volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */
+ volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */
+ volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */
+ volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */
+ volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */
+ volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */
+ volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */
+ volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */
+ volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */
+ volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */
+ volatile uint8_t dummy295[4]; /* */
+ volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */
+/* end of struct st_scux_from_dvuir_dvu0_n */
+ volatile uint8_t dummy296[168]; /* */
+ volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */
+ volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */
+ volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */
+ volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */
+ volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */
+ volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */
+ volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */
+ volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */
+ volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */
+ volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */
+ volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */
+ volatile uint8_t dummy297[212]; /* */
+ volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */
+ volatile uint32_t DMACR_CIM; /* DMACR_CIM */
+#define SCUX_DMATDn_CIM_COUNT 4
+ union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */
+ union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */
+ union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */
+ union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */
+#define SCUX_DMATUn_CIM_COUNT 4
+ union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */
+ union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */
+ union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */
+ union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */
+
+ volatile uint8_t dummy298[16]; /* */
+ volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */
+#define SCUX_FDTSELn_CIM_COUNT 4
+ volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */
+ volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */
+ volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */
+ volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */
+#define SCUX_FUTSELn_CIM_COUNT 4
+ volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */
+ volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */
+ volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */
+ volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */
+ volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */
+ volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */
+#define SCUX_SRCRSELn_CIM_COUNT 4
+ volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */
+ volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */
+ volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */
+ volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */
+ volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */
+};
+
+
+struct st_scux_from_ipcir_ipc0_n
+{
+ volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
+ volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
+ volatile uint8_t dummy1[248]; /* */
+};
+
+
+struct st_scux_from_opcir_opc0_n
+{
+ volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
+ volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
+ volatile uint8_t dummy1[248]; /* */
+};
+
+
+struct st_scux_from_ffdir_ffd0_n
+{
+ volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
+ volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
+ volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
+ volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
+ volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
+ volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
+ volatile uint8_t dummy1[4]; /* */
+ volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
+};
+
+
+struct st_scux_from_ffuir_ffu0_n
+{
+ volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
+ volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
+ volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
+ volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
+ volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
+ volatile uint8_t dummy1[4]; /* */
+ volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
+};
+
+
+struct st_scux_from_srcir0_2src0_n
+{
+ volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
+ volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
+ volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
+ volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
+ volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
+ volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
+ volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
+ volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
+ volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
+ volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
+ volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
+ volatile uint8_t dummy1[4]; /* */
+ volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
+ volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
+ volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
+ volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
+ volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
+ volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
+ volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
+ volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
+ volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
+ volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
+ volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
+ volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
+ volatile uint8_t dummy2[4]; /* */
+ volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
+ volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
+};
+
+
+struct st_scux_from_dvuir_dvu0_n
+{
+ volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
+ volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
+ volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
+ volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
+ volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
+ volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
+ volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
+ volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
+ volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
+ volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
+ volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
+ volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
+ volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
+ volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
+ volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
+ volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
+ volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
+ volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
+ volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
+ volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
+ volatile uint8_t dummy1[4]; /* */
+ volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
+};
+
+
+#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */
+
+
+/* Start of channnel array defines of SCUX */
+
+/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
+#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
+#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
+#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
+
+
+/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
+#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
+
+
+/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
+#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
+#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
+#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
+
+
+/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
+#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
+#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
+#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
+
+
+/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
+#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
+#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
+#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
+
+
+/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
+#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
+#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
+#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
+
+/* End of channnel array defines of SCUX */
+
+
+#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0
+#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0
+#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1
+#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1
+#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2
+#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2
+#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3
+#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3
+#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0
+#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0
+#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1
+#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1
+#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2
+#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2
+#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3
+#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3
+#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0
+#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0
+#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0
+#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0
+#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0
+#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0
+#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0
+#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1
+#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1
+#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1
+#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1
+#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1
+#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1
+#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1
+#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2
+#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2
+#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2
+#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2
+#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2
+#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2
+#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2
+#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3
+#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3
+#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3
+#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3
+#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3
+#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3
+#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3
+#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0
+#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0
+#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0
+#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0
+#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0
+#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0
+#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1
+#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1
+#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1
+#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1
+#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1
+#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1
+#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2
+#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2
+#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2
+#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2
+#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2
+#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2
+#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3
+#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3
+#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3
+#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3
+#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3
+#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3
+#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0
+#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0
+#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0
+#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0
+#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0
+#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0
+#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0
+#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0
+#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0
+#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0
+#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0
+#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0
+#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0
+#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0
+#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0
+#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0
+#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0
+#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0
+#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0
+#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0
+#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0
+#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0
+#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0
+#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0
+#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0
+#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1
+#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1
+#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1
+#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1
+#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1
+#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1
+#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1
+#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1
+#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1
+#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1
+#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1
+#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1
+#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1
+#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1
+#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1
+#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1
+#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1
+#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1
+#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1
+#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1
+#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1
+#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1
+#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1
+#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1
+#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1
+#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0
+#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0
+#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0
+#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0
+#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0
+#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0
+#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0
+#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0
+#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0
+#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0
+#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0
+#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0
+#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0
+#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0
+#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0
+#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0
+#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0
+#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0
+#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0
+#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0
+#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0
+#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1
+#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1
+#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1
+#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1
+#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1
+#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1
+#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1
+#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1
+#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1
+#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1
+#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1
+#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1
+#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1
+#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1
+#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1
+#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1
+#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1
+#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1
+#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1
+#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1
+#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1
+#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2
+#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2
+#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2
+#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2
+#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2
+#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2
+#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2
+#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2
+#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2
+#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2
+#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2
+#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2
+#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2
+#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2
+#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2
+#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2
+#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2
+#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2
+#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2
+#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2
+#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2
+#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3
+#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3
+#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3
+#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3
+#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3
+#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3
+#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3
+#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3
+#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3
+#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3
+#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3
+#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3
+#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3
+#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3
+#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3
+#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3
+#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3
+#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3
+#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3
+#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3
+#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3
+#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0
+#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0
+#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0
+#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0
+#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0
+#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0
+#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0
+#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0
+#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0
+#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0
+#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0
+#define SCUXSWRSR_CIM SCUX.SWRSR_CIM
+#define SCUXDMACR_CIM SCUX.DMACR_CIM
+#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32
+#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L]
+#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H]
+#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32
+#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L]
+#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H]
+#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32
+#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L]
+#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H]
+#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32
+#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L]
+#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H]
+#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32
+#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L]
+#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H]
+#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32
+#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L]
+#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H]
+#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32
+#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L]
+#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H]
+#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32
+#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L]
+#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H]
+#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM
+#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM
+#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM
+#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM
+#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM
+#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM
+#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM
+#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM
+#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM
+#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM
+#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM
+#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM
+#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM
+#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM
+#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM
+#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,87 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : sdg_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SDG_IODEFINE_H
+#define SDG_IODEFINE_H
+
+struct st_sdg
+{ /* SDG */
+ volatile uint8_t SGCR1; /* SGCR1 */
+ volatile uint8_t SGCSR; /* SGCSR */
+ volatile uint8_t SGCR2; /* SGCR2 */
+ volatile uint8_t SGLR; /* SGLR */
+ volatile uint8_t SGTFR; /* SGTFR */
+ volatile uint8_t SGSFR; /* SGSFR */
+};
+
+
+#define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */
+#define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */
+#define SDG2 (*(struct st_sdg *)0xFCFF4C00uL) /* SDG2 */
+#define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */
+
+
+/* Start of channnel array defines of SDG */
+
+/* Channnel array defines of SDG */
+/*(Sample) value = SDG[ channel ]->SGCR1; */
+#define SDG_COUNT 4
+#define SDG_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SDG0, &SDG1, &SDG2, &SDG3 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SDG */
+
+
+#define SGCR1_0 SDG0.SGCR1
+#define SGCSR_0 SDG0.SGCSR
+#define SGCR2_0 SDG0.SGCR2
+#define SGLR_0 SDG0.SGLR
+#define SGTFR_0 SDG0.SGTFR
+#define SGSFR_0 SDG0.SGSFR
+#define SGCR1_1 SDG1.SGCR1
+#define SGCSR_1 SDG1.SGCSR
+#define SGCR2_1 SDG1.SGCR2
+#define SGLR_1 SDG1.SGLR
+#define SGTFR_1 SDG1.SGTFR
+#define SGSFR_1 SDG1.SGSFR
+#define SGCR1_2 SDG2.SGCR1
+#define SGCSR_2 SDG2.SGCSR
+#define SGCR2_2 SDG2.SGCR2
+#define SGLR_2 SDG2.SGLR
+#define SGTFR_2 SDG2.SGTFR
+#define SGSFR_2 SDG2.SGSFR
+#define SGCR1_3 SDG3.SGCR1
+#define SGCSR_3 SDG3.SGCSR
+#define SGCR2_3 SDG3.SGCR2
+#define SGLR_3 SDG3.SGLR
+#define SGTFR_3 SDG3.SGTFR
+#define SGSFR_3 SDG3.SGSFR
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,69 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : spdif_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SPDIF_IODEFINE_H
+#define SPDIF_IODEFINE_H
+
+struct st_spdif
+{ /* SPDIF */
+ volatile uint32_t TLCA; /* TLCA */
+ volatile uint32_t TRCA; /* TRCA */
+ volatile uint32_t TLCS; /* TLCS */
+ volatile uint32_t TRCS; /* TRCS */
+ volatile uint32_t TUI; /* TUI */
+ volatile uint32_t RLCA; /* RLCA */
+ volatile uint32_t RRCA; /* RRCA */
+ volatile uint32_t RLCS; /* RLCS */
+ volatile uint32_t RRCS; /* RRCS */
+ volatile uint32_t RUI; /* RUI */
+ volatile uint32_t CTRL; /* CTRL */
+ volatile uint32_t STAT; /* STAT */
+ volatile uint32_t TDAD; /* TDAD */
+ volatile uint32_t RDAD; /* RDAD */
+};
+
+
+#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */
+
+
+#define SPDIFTLCA SPDIF.TLCA
+#define SPDIFTRCA SPDIF.TRCA
+#define SPDIFTLCS SPDIF.TLCS
+#define SPDIFTRCS SPDIF.TRCS
+#define SPDIFTUI SPDIF.TUI
+#define SPDIFRLCA SPDIF.RLCA
+#define SPDIFRRCA SPDIF.RRCA
+#define SPDIFRLCS SPDIF.RLCS
+#define SPDIFRRCS SPDIF.RRCS
+#define SPDIFRUI SPDIF.RUI
+#define SPDIFCTRL SPDIF.CTRL
+#define SPDIFSTAT SPDIF.STAT
+#define SPDIFTDAD SPDIF.TDAD
+#define SPDIFRDAD SPDIF.RDAD
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,174 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : spibsc_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SPIBSC_IODEFINE_H
+#define SPIBSC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_spibsc
+{ /* SPIBSC */
+ volatile uint32_t CMNCR; /* CMNCR */
+ volatile uint32_t SSLDR; /* SSLDR */
+ volatile uint32_t SPBCR; /* SPBCR */
+ volatile uint32_t DRCR; /* DRCR */
+ volatile uint32_t DRCMR; /* DRCMR */
+ volatile uint32_t DREAR; /* DREAR */
+ volatile uint32_t DROPR; /* DROPR */
+ volatile uint32_t DRENR; /* DRENR */
+ volatile uint32_t SMCR; /* SMCR */
+ volatile uint32_t SMCMR; /* SMCMR */
+ volatile uint32_t SMADR; /* SMADR */
+ volatile uint32_t SMOPR; /* SMOPR */
+ volatile uint32_t SMENR; /* SMENR */
+ volatile uint8_t dummy1[4]; /* */
+ union iodefine_reg32_t SMRDR0; /* SMRDR0 */
+ union iodefine_reg32_t SMRDR1; /* SMRDR1 */
+ union iodefine_reg32_t SMWDR0; /* SMWDR0 */
+ union iodefine_reg32_t SMWDR1; /* SMWDR1 */
+
+ volatile uint32_t CMNSR; /* CMNSR */
+ volatile uint8_t dummy2[12]; /* */
+ volatile uint32_t DRDMCR; /* DRDMCR */
+ volatile uint32_t DRDRENR; /* DRDRENR */
+ volatile uint32_t SMDMCR; /* SMDMCR */
+ volatile uint32_t SMDRENR; /* SMDRENR */
+};
+
+
+#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */
+#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */
+
+
+/* Start of channnel array defines of SPIBSC */
+
+/* Channnel array defines of SPIBSC */
+/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
+#define SPIBSC_COUNT 2
+#define SPIBSC_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SPIBSC0, &SPIBSC1 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SPIBSC */
+
+
+#define CMNCR_0 SPIBSC0.CMNCR
+#define SSLDR_0 SPIBSC0.SSLDR
+#define SPBCR_0 SPIBSC0.SPBCR
+#define DRCR_0 SPIBSC0.DRCR
+#define DRCMR_0 SPIBSC0.DRCMR
+#define DREAR_0 SPIBSC0.DREAR
+#define DROPR_0 SPIBSC0.DROPR
+#define DRENR_0 SPIBSC0.DRENR
+#define SMCR_0 SPIBSC0.SMCR
+#define SMCMR_0 SPIBSC0.SMCMR
+#define SMADR_0 SPIBSC0.SMADR
+#define SMOPR_0 SPIBSC0.SMOPR
+#define SMENR_0 SPIBSC0.SMENR
+#define SMRDR0_0 SPIBSC0.SMRDR0.UINT32
+#define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L]
+#define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H]
+#define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL]
+#define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH]
+#define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL]
+#define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH]
+#define SMRDR1_0 SPIBSC0.SMRDR1.UINT32
+#define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L]
+#define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H]
+#define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL]
+#define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH]
+#define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL]
+#define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH]
+#define SMWDR0_0 SPIBSC0.SMWDR0.UINT32
+#define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L]
+#define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H]
+#define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL]
+#define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH]
+#define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL]
+#define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH]
+#define SMWDR1_0 SPIBSC0.SMWDR1.UINT32
+#define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L]
+#define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H]
+#define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL]
+#define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH]
+#define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL]
+#define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH]
+#define CMNSR_0 SPIBSC0.CMNSR
+#define DRDMCR_0 SPIBSC0.DRDMCR
+#define DRDRENR_0 SPIBSC0.DRDRENR
+#define SMDMCR_0 SPIBSC0.SMDMCR
+#define SMDRENR_0 SPIBSC0.SMDRENR
+#define CMNCR_1 SPIBSC1.CMNCR
+#define SSLDR_1 SPIBSC1.SSLDR
+#define SPBCR_1 SPIBSC1.SPBCR
+#define DRCR_1 SPIBSC1.DRCR
+#define DRCMR_1 SPIBSC1.DRCMR
+#define DREAR_1 SPIBSC1.DREAR
+#define DROPR_1 SPIBSC1.DROPR
+#define DRENR_1 SPIBSC1.DRENR
+#define SMCR_1 SPIBSC1.SMCR
+#define SMCMR_1 SPIBSC1.SMCMR
+#define SMADR_1 SPIBSC1.SMADR
+#define SMOPR_1 SPIBSC1.SMOPR
+#define SMENR_1 SPIBSC1.SMENR
+#define SMRDR0_1 SPIBSC1.SMRDR0.UINT32
+#define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L]
+#define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H]
+#define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL]
+#define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH]
+#define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL]
+#define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH]
+#define SMRDR1_1 SPIBSC1.SMRDR1.UINT32
+#define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L]
+#define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H]
+#define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL]
+#define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH]
+#define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL]
+#define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH]
+#define SMWDR0_1 SPIBSC1.SMWDR0.UINT32
+#define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L]
+#define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H]
+#define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL]
+#define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH]
+#define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL]
+#define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH]
+#define SMWDR1_1 SPIBSC1.SMWDR1.UINT32
+#define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L]
+#define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H]
+#define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL]
+#define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH]
+#define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL]
+#define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH]
+#define CMNSR_1 SPIBSC1.CMNSR
+#define DRDMCR_1 SPIBSC1.DRDMCR
+#define DRDRENR_1 SPIBSC1.DRDRENR
+#define SMDMCR_1 SPIBSC1.SMDMCR
+#define SMDRENR_1 SPIBSC1.SMDRENR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,132 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ssif_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SSIF_IODEFINE_H
+#define SSIF_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ssif
+{ /* SSIF */
+ volatile uint32_t SSICR; /* SSICR */
+ volatile uint32_t SSISR; /* SSISR */
+ volatile uint8_t dummy1[8]; /* */
+ volatile uint32_t SSIFCR; /* SSIFCR */
+ volatile uint32_t SSIFSR; /* SSIFSR */
+ volatile uint32_t SSIFTDR; /* SSIFTDR */
+ volatile uint32_t SSIFRDR; /* SSIFRDR */
+ volatile uint32_t SSITDMR; /* SSITDMR */
+ volatile uint32_t SSIFCCR; /* SSIFCCR */
+ volatile uint32_t SSIFCMR; /* SSIFCMR */
+ volatile uint32_t SSIFCSR; /* SSIFCSR */
+};
+
+
+#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */
+#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */
+#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */
+#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */
+#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */
+#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */
+
+
+/* Start of channnel array defines of SSIF */
+
+/* Channnel array defines of SSIF */
+/*(Sample) value = SSIF[ channel ]->SSICR; */
+#define SSIF_COUNT 6
+#define SSIF_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SSIF */
+
+
+#define SSICR_0 SSIF0.SSICR
+#define SSISR_0 SSIF0.SSISR
+#define SSIFCR_0 SSIF0.SSIFCR
+#define SSIFSR_0 SSIF0.SSIFSR
+#define SSIFTDR_0 SSIF0.SSIFTDR
+#define SSIFRDR_0 SSIF0.SSIFRDR
+#define SSITDMR_0 SSIF0.SSITDMR
+#define SSIFCCR_0 SSIF0.SSIFCCR
+#define SSIFCMR_0 SSIF0.SSIFCMR
+#define SSIFCSR_0 SSIF0.SSIFCSR
+#define SSICR_1 SSIF1.SSICR
+#define SSISR_1 SSIF1.SSISR
+#define SSIFCR_1 SSIF1.SSIFCR
+#define SSIFSR_1 SSIF1.SSIFSR
+#define SSIFTDR_1 SSIF1.SSIFTDR
+#define SSIFRDR_1 SSIF1.SSIFRDR
+#define SSITDMR_1 SSIF1.SSITDMR
+#define SSIFCCR_1 SSIF1.SSIFCCR
+#define SSIFCMR_1 SSIF1.SSIFCMR
+#define SSIFCSR_1 SSIF1.SSIFCSR
+#define SSICR_2 SSIF2.SSICR
+#define SSISR_2 SSIF2.SSISR
+#define SSIFCR_2 SSIF2.SSIFCR
+#define SSIFSR_2 SSIF2.SSIFSR
+#define SSIFTDR_2 SSIF2.SSIFTDR
+#define SSIFRDR_2 SSIF2.SSIFRDR
+#define SSITDMR_2 SSIF2.SSITDMR
+#define SSIFCCR_2 SSIF2.SSIFCCR
+#define SSIFCMR_2 SSIF2.SSIFCMR
+#define SSIFCSR_2 SSIF2.SSIFCSR
+#define SSICR_3 SSIF3.SSICR
+#define SSISR_3 SSIF3.SSISR
+#define SSIFCR_3 SSIF3.SSIFCR
+#define SSIFSR_3 SSIF3.SSIFSR
+#define SSIFTDR_3 SSIF3.SSIFTDR
+#define SSIFRDR_3 SSIF3.SSIFRDR
+#define SSITDMR_3 SSIF3.SSITDMR
+#define SSIFCCR_3 SSIF3.SSIFCCR
+#define SSIFCMR_3 SSIF3.SSIFCMR
+#define SSIFCSR_3 SSIF3.SSIFCSR
+#define SSICR_4 SSIF4.SSICR
+#define SSISR_4 SSIF4.SSISR
+#define SSIFCR_4 SSIF4.SSIFCR
+#define SSIFSR_4 SSIF4.SSIFSR
+#define SSIFTDR_4 SSIF4.SSIFTDR
+#define SSIFRDR_4 SSIF4.SSIFRDR
+#define SSITDMR_4 SSIF4.SSITDMR
+#define SSIFCCR_4 SSIF4.SSIFCCR
+#define SSIFCMR_4 SSIF4.SSIFCMR
+#define SSIFCSR_4 SSIF4.SSIFCSR
+#define SSICR_5 SSIF5.SSICR
+#define SSISR_5 SSIF5.SSISR
+#define SSIFCR_5 SSIF5.SSIFCR
+#define SSIFSR_5 SSIF5.SSIFSR
+#define SSIFTDR_5 SSIF5.SSIFTDR
+#define SSIFRDR_5 SSIF5.SSIFRDR
+#define SSITDMR_5 SSIF5.SSITDMR
+#define SSIFCCR_5 SSIF5.SSIFCCR
+#define SSIFCMR_5 SSIF5.SSIFCMR
+#define SSIFCSR_5 SSIF5.SSIFCSR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,547 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb20_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef USB20_IODEFINE_H
+#define USB20_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_usb20
+{ /* USB20 */
+ volatile uint16_t SYSCFG0; /* SYSCFG0 */
+ volatile uint16_t BUSWAIT; /* BUSWAIT */
+ volatile uint16_t SYSSTS0; /* SYSSTS0 */
+ volatile uint8_t dummy1[2]; /* */
+ volatile uint16_t DVSTCTR0; /* DVSTCTR0 */
+ volatile uint8_t dummy2[2]; /* */
+ volatile uint16_t TESTMODE; /* TESTMODE */
+ volatile uint8_t dummy3[2]; /* */
+#define USB20_D0FBCFG_COUNT 2
+ volatile uint16_t D0FBCFG; /* D0FBCFG */
+ volatile uint16_t D1FBCFG; /* D1FBCFG */
+ union iodefine_reg32_t CFIFO; /* CFIFO */
+#define USB20_D0FIFO_COUNT 2
+ union iodefine_reg32_t D0FIFO; /* D0FIFO */
+ union iodefine_reg32_t D1FIFO; /* D1FIFO */
+
+ volatile uint16_t CFIFOSEL; /* CFIFOSEL */
+ volatile uint16_t CFIFOCTR; /* CFIFOCTR */
+ volatile uint8_t dummy4[4]; /* */
+/* start of struct st_usb20_from_d0fifosel */
+ volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */
+ volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */
+/* end of struct st_usb20_from_d0fifosel */
+/* start of struct st_usb20_from_d0fifosel */
+ volatile uint16_t D1FIFOSEL; /* D1FIFOSEL */
+ volatile uint16_t D1FIFOCTR; /* D1FIFOCTR */
+/* end of struct st_usb20_from_d0fifosel */
+#define USB20_INTENB0_COUNT 2
+ volatile uint16_t INTENB0; /* INTENB0 */
+ volatile uint16_t INTENB1; /* INTENB1 */
+ volatile uint8_t dummy5[2]; /* */
+ volatile uint16_t BRDYENB; /* BRDYENB */
+ volatile uint16_t NRDYENB; /* NRDYENB */
+ volatile uint16_t BEMPENB; /* BEMPENB */
+ volatile uint16_t SOFCFG; /* SOFCFG */
+ volatile uint8_t dummy6[2]; /* */
+#define USB20_INTSTS0_COUNT 2
+ volatile uint16_t INTSTS0; /* INTSTS0 */
+ volatile uint16_t INTSTS1; /* INTSTS1 */
+ volatile uint8_t dummy7[2]; /* */
+ volatile uint16_t BRDYSTS; /* BRDYSTS */
+ volatile uint16_t NRDYSTS; /* NRDYSTS */
+ volatile uint16_t BEMPSTS; /* BEMPSTS */
+ volatile uint16_t FRMNUM; /* FRMNUM */
+ volatile uint16_t UFRMNUM; /* UFRMNUM */
+ volatile uint16_t USBADDR; /* USBADDR */
+ volatile uint8_t dummy8[2]; /* */
+ volatile uint16_t USBREQ; /* USBREQ */
+ volatile uint16_t USBVAL; /* USBVAL */
+ volatile uint16_t USBINDX; /* USBINDX */
+ volatile uint16_t USBLENG; /* USBLENG */
+ volatile uint16_t DCPCFG; /* DCPCFG */
+ volatile uint16_t DCPMAXP; /* DCPMAXP */
+ volatile uint16_t DCPCTR; /* DCPCTR */
+ volatile uint8_t dummy9[2]; /* */
+ volatile uint16_t PIPESEL; /* PIPESEL */
+ volatile uint8_t dummy10[2]; /* */
+ volatile uint16_t PIPECFG; /* PIPECFG */
+ volatile uint16_t PIPEBUF; /* PIPEBUF */
+ volatile uint16_t PIPEMAXP; /* PIPEMAXP */
+ volatile uint16_t PIPEPERI; /* PIPEPERI */
+#define USB20_PIPE1CTR_COUNT 0xF
+ volatile uint16_t PIPE1CTR; /* PIPE1CTR */
+ volatile uint16_t PIPE2CTR; /* PIPE2CTR */
+ volatile uint16_t PIPE3CTR; /* PIPE3CTR */
+ volatile uint16_t PIPE4CTR; /* PIPE4CTR */
+ volatile uint16_t PIPE5CTR; /* PIPE5CTR */
+ volatile uint16_t PIPE6CTR; /* PIPE6CTR */
+ volatile uint16_t PIPE7CTR; /* PIPE7CTR */
+ volatile uint16_t PIPE8CTR; /* PIPE8CTR */
+ volatile uint16_t PIPE9CTR; /* PIPE9CTR */
+ volatile uint16_t PIPEACTR; /* PIPEACTR */
+ volatile uint16_t PIPEBCTR; /* PIPEBCTR */
+ volatile uint16_t PIPECCTR; /* PIPECCTR */
+ volatile uint16_t PIPEDCTR; /* PIPEDCTR */
+ volatile uint16_t PIPEECTR; /* PIPEECTR */
+ volatile uint16_t PIPEFCTR; /* PIPEFCTR */
+ volatile uint8_t dummy11[2]; /* */
+/* start of struct st_usb20_from_pipe1tre */
+ volatile uint16_t PIPE1TRE; /* PIPE1TRE */
+ volatile uint16_t PIPE1TRN; /* PIPE1TRN */
+/* end of struct st_usb20_from_pipe1tre */
+/* start of struct st_usb20_from_pipe1tre */
+ volatile uint16_t PIPE2TRE; /* PIPE2TRE */
+ volatile uint16_t PIPE2TRN; /* PIPE2TRN */
+/* end of struct st_usb20_from_pipe1tre */
+/* start of struct st_usb20_from_pipe1tre */
+ volatile uint16_t PIPE3TRE; /* PIPE3TRE */
+ volatile uint16_t PIPE3TRN; /* PIPE3TRN */
+/* end of struct st_usb20_from_pipe1tre */
+/* start of struct st_usb20_from_pipe1tre */
+ volatile uint16_t PIPE4TRE; /* PIPE4TRE */
+ volatile uint16_t PIPE4TRN; /* PIPE4TRN */
+/* end of struct st_usb20_from_pipe1tre */
+/* start of struct st_usb20_from_pipe1tre */
+ volatile uint16_t PIPE5TRE; /* PIPE5TRE */
+ volatile uint16_t PIPE5TRN; /* PIPE5TRN */
+/* end of struct st_usb20_from_pipe1tre */
+ volatile uint16_t PIPEBTRE; /* PIPEBTRE */
+ volatile uint16_t PIPEBTRN; /* PIPEBTRN */
+ volatile uint16_t PIPECTRE; /* PIPECTRE */
+ volatile uint16_t PIPECTRN; /* PIPECTRN */
+ volatile uint16_t PIPEDTRE; /* PIPEDTRE */
+ volatile uint16_t PIPEDTRN; /* PIPEDTRN */
+ volatile uint16_t PIPEETRE; /* PIPEETRE */
+ volatile uint16_t PIPEETRN; /* PIPEETRN */
+ volatile uint16_t PIPEFTRE; /* PIPEFTRE */
+ volatile uint16_t PIPEFTRN; /* PIPEFTRN */
+ volatile uint16_t PIPE9TRE; /* PIPE9TRE */
+ volatile uint16_t PIPE9TRN; /* PIPE9TRN */
+ volatile uint16_t PIPEATRE; /* PIPEATRE */
+ volatile uint16_t PIPEATRN; /* PIPEATRN */
+ volatile uint8_t dummy12[16]; /* */
+#define USB20_DEVADD0_COUNT 0xB
+ volatile uint16_t DEVADD0; /* DEVADD0 */
+ volatile uint16_t DEVADD1; /* DEVADD1 */
+ volatile uint16_t DEVADD2; /* DEVADD2 */
+ volatile uint16_t DEVADD3; /* DEVADD3 */
+ volatile uint16_t DEVADD4; /* DEVADD4 */
+ volatile uint16_t DEVADD5; /* DEVADD5 */
+ volatile uint16_t DEVADD6; /* DEVADD6 */
+ volatile uint16_t DEVADD7; /* DEVADD7 */
+ volatile uint16_t DEVADD8; /* DEVADD8 */
+ volatile uint16_t DEVADD9; /* DEVADD9 */
+ volatile uint16_t DEVADDA; /* DEVADDA */
+ volatile uint8_t dummy13[28]; /* */
+ volatile uint16_t SUSPMODE; /* SUSPMODE */
+ volatile uint8_t dummy14[92]; /* */
+/* start of struct st_usb20_from_dmfifob0 */
+ volatile uint32_t D0FIFOB0; /* D0FIFOB0 */
+ volatile uint32_t D0FIFOB1; /* D0FIFOB1 */
+ volatile uint32_t D0FIFOB2; /* D0FIFOB2 */
+ volatile uint32_t D0FIFOB3; /* D0FIFOB3 */
+ volatile uint32_t D0FIFOB4; /* D0FIFOB4 */
+ volatile uint32_t D0FIFOB5; /* D0FIFOB5 */
+ volatile uint32_t D0FIFOB6; /* D0FIFOB6 */
+ volatile uint32_t D0FIFOB7; /* D0FIFOB7 */
+/* end of struct st_usb20_from_dmfifob0 */
+/* start of struct st_usb20_from_dmfifob0 */
+ volatile uint32_t D1FIFOB0; /* D1FIFOB0 */
+ volatile uint32_t D1FIFOB1; /* D1FIFOB1 */
+ volatile uint32_t D1FIFOB2; /* D1FIFOB2 */
+ volatile uint32_t D1FIFOB3; /* D1FIFOB3 */
+ volatile uint32_t D1FIFOB4; /* D1FIFOB4 */
+ volatile uint32_t D1FIFOB5; /* D1FIFOB5 */
+ volatile uint32_t D1FIFOB6; /* D1FIFOB6 */
+ volatile uint32_t D1FIFOB7; /* D1FIFOB7 */
+/* end of struct st_usb20_from_dmfifob0 */
+};
+
+
+struct st_usb20_from_d0fifosel
+{
+ volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */
+ volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */
+};
+
+
+struct st_usb20_from_pipe1tre
+{
+ volatile uint16_t PIPE1TRE; /* PIPE1TRE */
+ volatile uint16_t PIPE1TRN; /* PIPE1TRN */
+};
+
+
+struct st_usb20_from_dmfifob0
+{
+#define USB20_D0FIFOB0_COUNT 0x8
+ volatile uint32_t D0FIFOB0; /* D0FIFOB0 */
+ volatile uint32_t D0FIFOB1; /* D0FIFOB1 */
+ volatile uint32_t D0FIFOB2; /* D0FIFOB2 */
+ volatile uint32_t D0FIFOB3; /* D0FIFOB3 */
+ volatile uint32_t D0FIFOB4; /* D0FIFOB4 */
+ volatile uint32_t D0FIFOB5; /* D0FIFOB5 */
+ volatile uint32_t D0FIFOB6; /* D0FIFOB6 */
+ volatile uint32_t D0FIFOB7; /* D0FIFOB7 */
+};
+
+
+#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */
+#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */
+
+
+/* Start of channnel array defines of USB20 */
+
+/* Channnel array defines of USB20 */
+/*(Sample) value = USB20[ channel ]->SYSCFG0; */
+#define USB20_COUNT 2
+#define USB20_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &USB200, &USB201 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+
+
+/* Channnel array defines of USB20_FROM_D0FIFOB0 */
+/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
+#define USB20_FROM_D0FIFOB0_COUNT 2
+#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
+ &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
+#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
+#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
+#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
+
+
+
+
+/* Channnel array defines of USB20_FROM_PIPE1ATRE */
+/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
+#define USB20_FROM_PIPE1ATRE_COUNT 5
+#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
+ &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
+#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
+#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
+#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
+#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
+#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
+#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
+#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
+#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
+#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
+
+
+
+
+/* Channnel array defines of USB20_FROM_D0FIFOSEL */
+/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
+#define USB20_FROM_D0FIFOSEL_COUNT 2
+#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
+ &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
+#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
+#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
+#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
+
+
+/* End of channnel array defines of USB20 */
+
+
+#define SYSCFG0_0 USB200.SYSCFG0
+#define BUSWAIT_0 USB200.BUSWAIT
+#define SYSSTS0_0 USB200.SYSSTS0
+#define DVSTCTR0_0 USB200.DVSTCTR0
+#define TESTMODE_0 USB200.TESTMODE
+#define D0FBCFG_0 USB200.D0FBCFG
+#define D1FBCFG_0 USB200.D1FBCFG
+#define CFIFO_0 USB200.CFIFO.UINT32
+#define CFIFO_0L USB200.CFIFO.UINT16[L]
+#define CFIFO_0H USB200.CFIFO.UINT16[H]
+#define CFIFO_0LL USB200.CFIFO.UINT8[LL]
+#define CFIFO_0LH USB200.CFIFO.UINT8[LH]
+#define CFIFO_0HL USB200.CFIFO.UINT8[HL]
+#define CFIFO_0HH USB200.CFIFO.UINT8[HH]
+#define D0FIFO_0 USB200.D0FIFO.UINT32
+#define D0FIFO_0L USB200.D0FIFO.UINT16[L]
+#define D0FIFO_0H USB200.D0FIFO.UINT16[H]
+#define D0FIFO_0LL USB200.D0FIFO.UINT8[LL]
+#define D0FIFO_0LH USB200.D0FIFO.UINT8[LH]
+#define D0FIFO_0HL USB200.D0FIFO.UINT8[HL]
+#define D0FIFO_0HH USB200.D0FIFO.UINT8[HH]
+#define D1FIFO_0 USB200.D1FIFO.UINT32
+#define D1FIFO_0L USB200.D1FIFO.UINT16[L]
+#define D1FIFO_0H USB200.D1FIFO.UINT16[H]
+#define D1FIFO_0LL USB200.D1FIFO.UINT8[LL]
+#define D1FIFO_0LH USB200.D1FIFO.UINT8[LH]
+#define D1FIFO_0HL USB200.D1FIFO.UINT8[HL]
+#define D1FIFO_0HH USB200.D1FIFO.UINT8[HH]
+#define CFIFOSEL_0 USB200.CFIFOSEL
+#define CFIFOCTR_0 USB200.CFIFOCTR
+#define D0FIFOSEL_0 USB200.D0FIFOSEL
+#define D0FIFOCTR_0 USB200.D0FIFOCTR
+#define D1FIFOSEL_0 USB200.D1FIFOSEL
+#define D1FIFOCTR_0 USB200.D1FIFOCTR
+#define INTENB0_0 USB200.INTENB0
+#define INTENB1_0 USB200.INTENB1
+#define BRDYENB_0 USB200.BRDYENB
+#define NRDYENB_0 USB200.NRDYENB
+#define BEMPENB_0 USB200.BEMPENB
+#define SOFCFG_0 USB200.SOFCFG
+#define INTSTS0_0 USB200.INTSTS0
+#define INTSTS1_0 USB200.INTSTS1
+#define BRDYSTS_0 USB200.BRDYSTS
+#define NRDYSTS_0 USB200.NRDYSTS
+#define BEMPSTS_0 USB200.BEMPSTS
+#define FRMNUM_0 USB200.FRMNUM
+#define UFRMNUM_0 USB200.UFRMNUM
+#define USBADDR_0 USB200.USBADDR
+#define USBREQ_0 USB200.USBREQ
+#define USBVAL_0 USB200.USBVAL
+#define USBINDX_0 USB200.USBINDX
+#define USBLENG_0 USB200.USBLENG
+#define DCPCFG_0 USB200.DCPCFG
+#define DCPMAXP_0 USB200.DCPMAXP
+#define DCPCTR_0 USB200.DCPCTR
+#define PIPESEL_0 USB200.PIPESEL
+#define PIPECFG_0 USB200.PIPECFG
+#define PIPEBUF_0 USB200.PIPEBUF
+#define PIPEMAXP_0 USB200.PIPEMAXP
+#define PIPEPERI_0 USB200.PIPEPERI
+#define PIPE1CTR_0 USB200.PIPE1CTR
+#define PIPE2CTR_0 USB200.PIPE2CTR
+#define PIPE3CTR_0 USB200.PIPE3CTR
+#define PIPE4CTR_0 USB200.PIPE4CTR
+#define PIPE5CTR_0 USB200.PIPE5CTR
+#define PIPE6CTR_0 USB200.PIPE6CTR
+#define PIPE7CTR_0 USB200.PIPE7CTR
+#define PIPE8CTR_0 USB200.PIPE8CTR
+#define PIPE9CTR_0 USB200.PIPE9CTR
+#define PIPEACTR_0 USB200.PIPEACTR
+#define PIPEBCTR_0 USB200.PIPEBCTR
+#define PIPECCTR_0 USB200.PIPECCTR
+#define PIPEDCTR_0 USB200.PIPEDCTR
+#define PIPEECTR_0 USB200.PIPEECTR
+#define PIPEFCTR_0 USB200.PIPEFCTR
+#define PIPE1TRE_0 USB200.PIPE1TRE
+#define PIPE1TRN_0 USB200.PIPE1TRN
+#define PIPE2TRE_0 USB200.PIPE2TRE
+#define PIPE2TRN_0 USB200.PIPE2TRN
+#define PIPE3TRE_0 USB200.PIPE3TRE
+#define PIPE3TRN_0 USB200.PIPE3TRN
+#define PIPE4TRE_0 USB200.PIPE4TRE
+#define PIPE4TRN_0 USB200.PIPE4TRN
+#define PIPE5TRE_0 USB200.PIPE5TRE
+#define PIPE5TRN_0 USB200.PIPE5TRN
+#define PIPEBTRE_0 USB200.PIPEBTRE
+#define PIPEBTRN_0 USB200.PIPEBTRN
+#define PIPECTRE_0 USB200.PIPECTRE
+#define PIPECTRN_0 USB200.PIPECTRN
+#define PIPEDTRE_0 USB200.PIPEDTRE
+#define PIPEDTRN_0 USB200.PIPEDTRN
+#define PIPEETRE_0 USB200.PIPEETRE
+#define PIPEETRN_0 USB200.PIPEETRN
+#define PIPEFTRE_0 USB200.PIPEFTRE
+#define PIPEFTRN_0 USB200.PIPEFTRN
+#define PIPE9TRE_0 USB200.PIPE9TRE
+#define PIPE9TRN_0 USB200.PIPE9TRN
+#define PIPEATRE_0 USB200.PIPEATRE
+#define PIPEATRN_0 USB200.PIPEATRN
+#define DEVADD0_0 USB200.DEVADD0
+#define DEVADD1_0 USB200.DEVADD1
+#define DEVADD2_0 USB200.DEVADD2
+#define DEVADD3_0 USB200.DEVADD3
+#define DEVADD4_0 USB200.DEVADD4
+#define DEVADD5_0 USB200.DEVADD5
+#define DEVADD6_0 USB200.DEVADD6
+#define DEVADD7_0 USB200.DEVADD7
+#define DEVADD8_0 USB200.DEVADD8
+#define DEVADD9_0 USB200.DEVADD9
+#define DEVADDA_0 USB200.DEVADDA
+#define SUSPMODE_0 USB200.SUSPMODE
+#define D0FIFOB0_0 USB200.D0FIFOB0
+#define D0FIFOB1_0 USB200.D0FIFOB1
+#define D0FIFOB2_0 USB200.D0FIFOB2
+#define D0FIFOB3_0 USB200.D0FIFOB3
+#define D0FIFOB4_0 USB200.D0FIFOB4
+#define D0FIFOB5_0 USB200.D0FIFOB5
+#define D0FIFOB6_0 USB200.D0FIFOB6
+#define D0FIFOB7_0 USB200.D0FIFOB7
+#define D1FIFOB0_0 USB200.D1FIFOB0
+#define D1FIFOB1_0 USB200.D1FIFOB1
+#define D1FIFOB2_0 USB200.D1FIFOB2
+#define D1FIFOB3_0 USB200.D1FIFOB3
+#define D1FIFOB4_0 USB200.D1FIFOB4
+#define D1FIFOB5_0 USB200.D1FIFOB5
+#define D1FIFOB6_0 USB200.D1FIFOB6
+#define D1FIFOB7_0 USB200.D1FIFOB7
+#define SYSCFG0_1 USB201.SYSCFG0
+#define BUSWAIT_1 USB201.BUSWAIT
+#define SYSSTS0_1 USB201.SYSSTS0
+#define DVSTCTR0_1 USB201.DVSTCTR0
+#define TESTMODE_1 USB201.TESTMODE
+#define D0FBCFG_1 USB201.D0FBCFG
+#define D1FBCFG_1 USB201.D1FBCFG
+#define CFIFO_1 USB201.CFIFO.UINT32
+#define CFIFO_1L USB201.CFIFO.UINT16[L]
+#define CFIFO_1H USB201.CFIFO.UINT16[H]
+#define CFIFO_1LL USB201.CFIFO.UINT8[LL]
+#define CFIFO_1LH USB201.CFIFO.UINT8[LH]
+#define CFIFO_1HL USB201.CFIFO.UINT8[HL]
+#define CFIFO_1HH USB201.CFIFO.UINT8[HH]
+#define D0FIFO_1 USB201.D0FIFO.UINT32
+#define D0FIFO_1L USB201.D0FIFO.UINT16[L]
+#define D0FIFO_1H USB201.D0FIFO.UINT16[H]
+#define D0FIFO_1LL USB201.D0FIFO.UINT8[LL]
+#define D0FIFO_1LH USB201.D0FIFO.UINT8[LH]
+#define D0FIFO_1HL USB201.D0FIFO.UINT8[HL]
+#define D0FIFO_1HH USB201.D0FIFO.UINT8[HH]
+#define D1FIFO_1 USB201.D1FIFO.UINT32
+#define D1FIFO_1L USB201.D1FIFO.UINT16[L]
+#define D1FIFO_1H USB201.D1FIFO.UINT16[H]
+#define D1FIFO_1LL USB201.D1FIFO.UINT8[LL]
+#define D1FIFO_1LH USB201.D1FIFO.UINT8[LH]
+#define D1FIFO_1HL USB201.D1FIFO.UINT8[HL]
+#define D1FIFO_1HH USB201.D1FIFO.UINT8[HH]
+#define CFIFOSEL_1 USB201.CFIFOSEL
+#define CFIFOCTR_1 USB201.CFIFOCTR
+#define D0FIFOSEL_1 USB201.D0FIFOSEL
+#define D0FIFOCTR_1 USB201.D0FIFOCTR
+#define D1FIFOSEL_1 USB201.D1FIFOSEL
+#define D1FIFOCTR_1 USB201.D1FIFOCTR
+#define INTENB0_1 USB201.INTENB0
+#define INTENB1_1 USB201.INTENB1
+#define BRDYENB_1 USB201.BRDYENB
+#define NRDYENB_1 USB201.NRDYENB
+#define BEMPENB_1 USB201.BEMPENB
+#define SOFCFG_1 USB201.SOFCFG
+#define INTSTS0_1 USB201.INTSTS0
+#define INTSTS1_1 USB201.INTSTS1
+#define BRDYSTS_1 USB201.BRDYSTS
+#define NRDYSTS_1 USB201.NRDYSTS
+#define BEMPSTS_1 USB201.BEMPSTS
+#define FRMNUM_1 USB201.FRMNUM
+#define UFRMNUM_1 USB201.UFRMNUM
+#define USBADDR_1 USB201.USBADDR
+#define USBREQ_1 USB201.USBREQ
+#define USBVAL_1 USB201.USBVAL
+#define USBINDX_1 USB201.USBINDX
+#define USBLENG_1 USB201.USBLENG
+#define DCPCFG_1 USB201.DCPCFG
+#define DCPMAXP_1 USB201.DCPMAXP
+#define DCPCTR_1 USB201.DCPCTR
+#define PIPESEL_1 USB201.PIPESEL
+#define PIPECFG_1 USB201.PIPECFG
+#define PIPEBUF_1 USB201.PIPEBUF
+#define PIPEMAXP_1 USB201.PIPEMAXP
+#define PIPEPERI_1 USB201.PIPEPERI
+#define PIPE1CTR_1 USB201.PIPE1CTR
+#define PIPE2CTR_1 USB201.PIPE2CTR
+#define PIPE3CTR_1 USB201.PIPE3CTR
+#define PIPE4CTR_1 USB201.PIPE4CTR
+#define PIPE5CTR_1 USB201.PIPE5CTR
+#define PIPE6CTR_1 USB201.PIPE6CTR
+#define PIPE7CTR_1 USB201.PIPE7CTR
+#define PIPE8CTR_1 USB201.PIPE8CTR
+#define PIPE9CTR_1 USB201.PIPE9CTR
+#define PIPEACTR_1 USB201.PIPEACTR
+#define PIPEBCTR_1 USB201.PIPEBCTR
+#define PIPECCTR_1 USB201.PIPECCTR
+#define PIPEDCTR_1 USB201.PIPEDCTR
+#define PIPEECTR_1 USB201.PIPEECTR
+#define PIPEFCTR_1 USB201.PIPEFCTR
+#define PIPE1TRE_1 USB201.PIPE1TRE
+#define PIPE1TRN_1 USB201.PIPE1TRN
+#define PIPE2TRE_1 USB201.PIPE2TRE
+#define PIPE2TRN_1 USB201.PIPE2TRN
+#define PIPE3TRE_1 USB201.PIPE3TRE
+#define PIPE3TRN_1 USB201.PIPE3TRN
+#define PIPE4TRE_1 USB201.PIPE4TRE
+#define PIPE4TRN_1 USB201.PIPE4TRN
+#define PIPE5TRE_1 USB201.PIPE5TRE
+#define PIPE5TRN_1 USB201.PIPE5TRN
+#define PIPEBTRE_1 USB201.PIPEBTRE
+#define PIPEBTRN_1 USB201.PIPEBTRN
+#define PIPECTRE_1 USB201.PIPECTRE
+#define PIPECTRN_1 USB201.PIPECTRN
+#define PIPEDTRE_1 USB201.PIPEDTRE
+#define PIPEDTRN_1 USB201.PIPEDTRN
+#define PIPEETRE_1 USB201.PIPEETRE
+#define PIPEETRN_1 USB201.PIPEETRN
+#define PIPEFTRE_1 USB201.PIPEFTRE
+#define PIPEFTRN_1 USB201.PIPEFTRN
+#define PIPE9TRE_1 USB201.PIPE9TRE
+#define PIPE9TRN_1 USB201.PIPE9TRN
+#define PIPEATRE_1 USB201.PIPEATRE
+#define PIPEATRN_1 USB201.PIPEATRN
+#define DEVADD0_1 USB201.DEVADD0
+#define DEVADD1_1 USB201.DEVADD1
+#define DEVADD2_1 USB201.DEVADD2
+#define DEVADD3_1 USB201.DEVADD3
+#define DEVADD4_1 USB201.DEVADD4
+#define DEVADD5_1 USB201.DEVADD5
+#define DEVADD6_1 USB201.DEVADD6
+#define DEVADD7_1 USB201.DEVADD7
+#define DEVADD8_1 USB201.DEVADD8
+#define DEVADD9_1 USB201.DEVADD9
+#define DEVADDA_1 USB201.DEVADDA
+#define SUSPMODE_1 USB201.SUSPMODE
+#define D0FIFOB0_1 USB201.D0FIFOB0
+#define D0FIFOB1_1 USB201.D0FIFOB1
+#define D0FIFOB2_1 USB201.D0FIFOB2
+#define D0FIFOB3_1 USB201.D0FIFOB3
+#define D0FIFOB4_1 USB201.D0FIFOB4
+#define D0FIFOB5_1 USB201.D0FIFOB5
+#define D0FIFOB6_1 USB201.D0FIFOB6
+#define D0FIFOB7_1 USB201.D0FIFOB7
+#define D1FIFOB0_1 USB201.D1FIFOB0
+#define D1FIFOB1_1 USB201.D1FIFOB1
+#define D1FIFOB2_1 USB201.D1FIFOB2
+#define D1FIFOB3_1 USB201.D1FIFOB3
+#define D1FIFOB4_1 USB201.D1FIFOB4
+#define D1FIFOB5_1 USB201.D1FIFOB5
+#define D1FIFOB6_1 USB201.D1FIFOB6
+#define D1FIFOB7_1 USB201.D1FIFOB7
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,1597 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : vdc5_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef VDC5_IODEFINE_H
+#define VDC5_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_vdc5
+{ /* VDC5 */
+ volatile uint32_t INP_UPDATE; /* INP_UPDATE */
+ volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */
+ volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */
+ volatile uint32_t INP_VSYNC_PH_ADJ; /* INP_VSYNC_PH_ADJ */
+ volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */
+ volatile uint8_t dummy1[108]; /* */
+ volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */
+#define VDC5_IMGCNT_NR_CNT0_COUNT 2
+ volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */
+ volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */
+ volatile uint8_t dummy2[20]; /* */
+ volatile uint32_t IMGCNT_MTX_MODE; /* IMGCNT_MTX_MODE */
+ volatile uint32_t IMGCNT_MTX_YG_ADJ0; /* IMGCNT_MTX_YG_ADJ0 */
+ volatile uint32_t IMGCNT_MTX_YG_ADJ1; /* IMGCNT_MTX_YG_ADJ1 */
+ volatile uint32_t IMGCNT_MTX_CBB_ADJ0; /* IMGCNT_MTX_CBB_ADJ0 */
+ volatile uint32_t IMGCNT_MTX_CBB_ADJ1; /* IMGCNT_MTX_CBB_ADJ1 */
+ volatile uint32_t IMGCNT_MTX_CRR_ADJ0; /* IMGCNT_MTX_CRR_ADJ0 */
+ volatile uint32_t IMGCNT_MTX_CRR_ADJ1; /* IMGCNT_MTX_CRR_ADJ1 */
+ volatile uint8_t dummy3[4]; /* */
+ volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */
+ volatile uint8_t dummy4[60]; /* */
+/* start of struct st_vdc5_from_sc0_scl0_update */
+ volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */
+#define VDC5_SC0_SCL0_FRC1_COUNT 7
+ volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */
+ volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */
+ volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */
+ volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */
+ volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */
+ volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */
+ volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */
+ volatile uint8_t dummy5[4]; /* */
+ volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */
+ volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */
+ volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */
+#define VDC5_SC0_SCL0_DS1_COUNT 7
+ volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */
+ volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */
+ volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */
+ volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */
+ volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */
+ volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */
+ volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */
+#define VDC5_SC0_SCL0_US1_COUNT 8
+ volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */
+ volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */
+ volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */
+ volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */
+ volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */
+ volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */
+ volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */
+ volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */
+ volatile uint8_t dummy6[4]; /* */
+ volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */
+ volatile uint8_t dummy7[16]; /* */
+ volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */
+ volatile uint8_t dummy8[4]; /* */
+#define VDC5_SC0_SCL1_WR1_COUNT 4
+ volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */
+ volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */
+ volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */
+ volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */
+ volatile uint8_t dummy9[4]; /* */
+ volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */
+ volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */
+ volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */
+ volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */
+ volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */
+ volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */
+/* end of struct st_vdc5_from_sc0_scl0_update */
+ volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */
+ volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */
+/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
+#define VDC5_SC0_SCL1_PBUF0_COUNT 4
+ volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */
+ volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */
+ volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */
+ volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */
+ volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */
+ volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */
+/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
+ volatile uint8_t dummy10[44]; /* */
+/* start of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */
+ volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */
+#define VDC5_GR0_FLM1_COUNT 6
+ volatile uint32_t GR0_FLM1; /* GR0_FLM1 */
+ volatile uint32_t GR0_FLM2; /* GR0_FLM2 */
+ volatile uint32_t GR0_FLM3; /* GR0_FLM3 */
+ volatile uint32_t GR0_FLM4; /* GR0_FLM4 */
+ volatile uint32_t GR0_FLM5; /* GR0_FLM5 */
+ volatile uint32_t GR0_FLM6; /* GR0_FLM6 */
+#define VDC5_GR0_AB1_COUNT 3
+ volatile uint32_t GR0_AB1; /* GR0_AB1 */
+ volatile uint32_t GR0_AB2; /* GR0_AB2 */
+ volatile uint32_t GR0_AB3; /* GR0_AB3 */
+/* end of struct st_vdc5_from_gr0_update */
+ volatile uint8_t dummy11[12]; /* */
+/* start of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR0_AB7; /* GR0_AB7 */
+ volatile uint32_t GR0_AB8; /* GR0_AB8 */
+ volatile uint32_t GR0_AB9; /* GR0_AB9 */
+ volatile uint32_t GR0_AB10; /* GR0_AB10 */
+ volatile uint32_t GR0_AB11; /* GR0_AB11 */
+ volatile uint32_t GR0_BASE; /* GR0_BASE */
+/* end of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR0_CLUT; /* GR0_CLUT */
+ volatile uint8_t dummy12[44]; /* */
+/* start of struct st_vdc5_from_adj0_update */
+ volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */
+ volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */
+#define VDC5_ADJ0_ENH_TIM1_COUNT 3
+ volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */
+ volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */
+ volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */
+#define VDC5_ADJ0_ENH_SHP1_COUNT 6
+ volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */
+ volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */
+ volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */
+ volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */
+ volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */
+ volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */
+#define VDC5_ADJ0_ENH_LTI1_COUNT 2
+ volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */
+ volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */
+ volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */
+ volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */
+ volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */
+ volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */
+ volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */
+ volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */
+ volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */
+/* end of struct st_vdc5_from_adj0_update */
+ volatile uint8_t dummy13[48]; /* */
+/* start of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */
+ volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */
+#define VDC5_GR2_FLM1_COUNT 6
+ volatile uint32_t GR2_FLM1; /* GR2_FLM1 */
+ volatile uint32_t GR2_FLM2; /* GR2_FLM2 */
+ volatile uint32_t GR2_FLM3; /* GR2_FLM3 */
+ volatile uint32_t GR2_FLM4; /* GR2_FLM4 */
+ volatile uint32_t GR2_FLM5; /* GR2_FLM5 */
+ volatile uint32_t GR2_FLM6; /* GR2_FLM6 */
+#define VDC5_GR2_AB1_COUNT 3
+ volatile uint32_t GR2_AB1; /* GR2_AB1 */
+ volatile uint32_t GR2_AB2; /* GR2_AB2 */
+ volatile uint32_t GR2_AB3; /* GR2_AB3 */
+/* end of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR2_AB4; /* GR2_AB4 */
+ volatile uint32_t GR2_AB5; /* GR2_AB5 */
+ volatile uint32_t GR2_AB6; /* GR2_AB6 */
+/* start of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR2_AB7; /* GR2_AB7 */
+ volatile uint32_t GR2_AB8; /* GR2_AB8 */
+ volatile uint32_t GR2_AB9; /* GR2_AB9 */
+ volatile uint32_t GR2_AB10; /* GR2_AB10 */
+ volatile uint32_t GR2_AB11; /* GR2_AB11 */
+ volatile uint32_t GR2_BASE; /* GR2_BASE */
+/* end of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR2_CLUT; /* GR2_CLUT */
+ volatile uint32_t GR2_MON; /* GR2_MON */
+ volatile uint8_t dummy14[40]; /* */
+/* start of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */
+ volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */
+#define VDC5_GR3_FLM1_COUNT 6
+ volatile uint32_t GR3_FLM1; /* GR3_FLM1 */
+ volatile uint32_t GR3_FLM2; /* GR3_FLM2 */
+ volatile uint32_t GR3_FLM3; /* GR3_FLM3 */
+ volatile uint32_t GR3_FLM4; /* GR3_FLM4 */
+ volatile uint32_t GR3_FLM5; /* GR3_FLM5 */
+ volatile uint32_t GR3_FLM6; /* GR3_FLM6 */
+#define VDC5_GR3_AB1_COUNT 3
+ volatile uint32_t GR3_AB1; /* GR3_AB1 */
+ volatile uint32_t GR3_AB2; /* GR3_AB2 */
+ volatile uint32_t GR3_AB3; /* GR3_AB3 */
+/* end of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR3_AB4; /* GR3_AB4 */
+ volatile uint32_t GR3_AB5; /* GR3_AB5 */
+ volatile uint32_t GR3_AB6; /* GR3_AB6 */
+/* start of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR3_AB7; /* GR3_AB7 */
+ volatile uint32_t GR3_AB8; /* GR3_AB8 */
+ volatile uint32_t GR3_AB9; /* GR3_AB9 */
+ volatile uint32_t GR3_AB10; /* GR3_AB10 */
+ volatile uint32_t GR3_AB11; /* GR3_AB11 */
+ volatile uint32_t GR3_BASE; /* GR3_BASE */
+/* end of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */
+ volatile uint32_t GR3_MON; /* GR3_MON */
+ volatile uint8_t dummy15[40]; /* */
+ volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */
+ volatile uint32_t GAM_SW; /* GAM_SW */
+#define VDC5_GAM_G_LUT1_COUNT 16
+ volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */
+ volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */
+ volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */
+ volatile uint32_t GAM_G_LUT4; /* GAM_G_LUT4 */
+ volatile uint32_t GAM_G_LUT5; /* GAM_G_LUT5 */
+ volatile uint32_t GAM_G_LUT6; /* GAM_G_LUT6 */
+ volatile uint32_t GAM_G_LUT7; /* GAM_G_LUT7 */
+ volatile uint32_t GAM_G_LUT8; /* GAM_G_LUT8 */
+ volatile uint32_t GAM_G_LUT9; /* GAM_G_LUT9 */
+ volatile uint32_t GAM_G_LUT10; /* GAM_G_LUT10 */
+ volatile uint32_t GAM_G_LUT11; /* GAM_G_LUT11 */
+ volatile uint32_t GAM_G_LUT12; /* GAM_G_LUT12 */
+ volatile uint32_t GAM_G_LUT13; /* GAM_G_LUT13 */
+ volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */
+ volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */
+ volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */
+#define VDC5_GAM_G_AREA1_COUNT 8
+ volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */
+ volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */
+ volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */
+ volatile uint32_t GAM_G_AREA4; /* GAM_G_AREA4 */
+ volatile uint32_t GAM_G_AREA5; /* GAM_G_AREA5 */
+ volatile uint32_t GAM_G_AREA6; /* GAM_G_AREA6 */
+ volatile uint32_t GAM_G_AREA7; /* GAM_G_AREA7 */
+ volatile uint32_t GAM_G_AREA8; /* GAM_G_AREA8 */
+ volatile uint8_t dummy16[24]; /* */
+ volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */
+ volatile uint8_t dummy17[4]; /* */
+#define VDC5_GAM_B_LUT1_COUNT 16
+ volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */
+ volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */
+ volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */
+ volatile uint32_t GAM_B_LUT4; /* GAM_B_LUT4 */
+ volatile uint32_t GAM_B_LUT5; /* GAM_B_LUT5 */
+ volatile uint32_t GAM_B_LUT6; /* GAM_B_LUT6 */
+ volatile uint32_t GAM_B_LUT7; /* GAM_B_LUT7 */
+ volatile uint32_t GAM_B_LUT8; /* GAM_B_LUT8 */
+ volatile uint32_t GAM_B_LUT9; /* GAM_B_LUT9 */
+ volatile uint32_t GAM_B_LUT10; /* GAM_B_LUT10 */
+ volatile uint32_t GAM_B_LUT11; /* GAM_B_LUT11 */
+ volatile uint32_t GAM_B_LUT12; /* GAM_B_LUT12 */
+ volatile uint32_t GAM_B_LUT13; /* GAM_B_LUT13 */
+ volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */
+ volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */
+ volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */
+#define VDC5_GAM_B_AREA1_COUNT 8
+ volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */
+ volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */
+ volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */
+ volatile uint32_t GAM_B_AREA4; /* GAM_B_AREA4 */
+ volatile uint32_t GAM_B_AREA5; /* GAM_B_AREA5 */
+ volatile uint32_t GAM_B_AREA6; /* GAM_B_AREA6 */
+ volatile uint32_t GAM_B_AREA7; /* GAM_B_AREA7 */
+ volatile uint32_t GAM_B_AREA8; /* GAM_B_AREA8 */
+ volatile uint8_t dummy18[24]; /* */
+ volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */
+ volatile uint8_t dummy19[4]; /* */
+#define VDC5_GAM_R_LUT1_COUNT 16
+ volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */
+ volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */
+ volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */
+ volatile uint32_t GAM_R_LUT4; /* GAM_R_LUT4 */
+ volatile uint32_t GAM_R_LUT5; /* GAM_R_LUT5 */
+ volatile uint32_t GAM_R_LUT6; /* GAM_R_LUT6 */
+ volatile uint32_t GAM_R_LUT7; /* GAM_R_LUT7 */
+ volatile uint32_t GAM_R_LUT8; /* GAM_R_LUT8 */
+ volatile uint32_t GAM_R_LUT9; /* GAM_R_LUT9 */
+ volatile uint32_t GAM_R_LUT10; /* GAM_R_LUT10 */
+ volatile uint32_t GAM_R_LUT11; /* GAM_R_LUT11 */
+ volatile uint32_t GAM_R_LUT12; /* GAM_R_LUT12 */
+ volatile uint32_t GAM_R_LUT13; /* GAM_R_LUT13 */
+ volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */
+ volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */
+ volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */
+#define VDC5_GAM_R_AREA1_COUNT 8
+ volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */
+ volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */
+ volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */
+ volatile uint32_t GAM_R_AREA4; /* GAM_R_AREA4 */
+ volatile uint32_t GAM_R_AREA5; /* GAM_R_AREA5 */
+ volatile uint32_t GAM_R_AREA6; /* GAM_R_AREA6 */
+ volatile uint32_t GAM_R_AREA7; /* GAM_R_AREA7 */
+ volatile uint32_t GAM_R_AREA8; /* GAM_R_AREA8 */
+ volatile uint8_t dummy20[24]; /* */
+ volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */
+ volatile uint32_t TCON_TIM; /* TCON_TIM */
+#define VDC5_TCON_TIM_STVA1_COUNT 2
+ volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */
+ volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */
+#define VDC5_TCON_TIM_STVB1_COUNT 2
+ volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */
+ volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */
+#define VDC5_TCON_TIM_STH1_COUNT 2
+ volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */
+ volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */
+#define VDC5_TCON_TIM_STB1_COUNT 2
+ volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */
+ volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */
+#define VDC5_TCON_TIM_CPV1_COUNT 2
+ volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */
+ volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */
+#define VDC5_TCON_TIM_POLA1_COUNT 2
+ volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */
+ volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */
+#define VDC5_TCON_TIM_POLB1_COUNT 2
+ volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */
+ volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */
+ volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */
+ volatile uint8_t dummy21[60]; /* */
+ volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */
+ volatile uint32_t OUT_SET; /* OUT_SET */
+#define VDC5_OUT_BRIGHT1_COUNT 2
+ volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */
+ volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */
+ volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */
+ volatile uint32_t OUT_PDTHA; /* OUT_PDTHA */
+ volatile uint8_t dummy22[12]; /* */
+ volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */
+ volatile uint8_t dummy23[88]; /* */
+#define VDC5_SYSCNT_INT1_COUNT 6
+ volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */
+ volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */
+ volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */
+ volatile uint32_t SYSCNT_INT4; /* SYSCNT_INT4 */
+ volatile uint32_t SYSCNT_INT5; /* SYSCNT_INT5 */
+ volatile uint32_t SYSCNT_INT6; /* SYSCNT_INT6 */
+ volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */
+ volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */
+ volatile uint8_t dummy24[356]; /* */
+/* start of struct st_vdc5_from_sc0_scl0_update */
+ volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */
+#define VDC5_SC1_SCL0_FRC1_COUNT 7
+ volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */
+ volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */
+ volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */
+ volatile uint32_t SC1_SCL0_FRC4; /* SC1_SCL0_FRC4 */
+ volatile uint32_t SC1_SCL0_FRC5; /* SC1_SCL0_FRC5 */
+ volatile uint32_t SC1_SCL0_FRC6; /* SC1_SCL0_FRC6 */
+ volatile uint32_t SC1_SCL0_FRC7; /* SC1_SCL0_FRC7 */
+ volatile uint8_t dummy25[4]; /* */
+ volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */
+ volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */
+ volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */
+#define VDC5_SC1_SC1_SCL0_DS1_COUNT 7
+ volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */
+ volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */
+ volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */
+ volatile uint32_t SC1_SCL0_DS4; /* SC1_SCL0_DS4 */
+ volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */
+ volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */
+ volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */
+#define VDC5_SC1_SC1_SCL0_US1_COUNT 8
+ volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */
+ volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */
+ volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */
+ volatile uint32_t SC1_SCL0_US4; /* SC1_SCL0_US4 */
+ volatile uint32_t SC1_SCL0_US5; /* SC1_SCL0_US5 */
+ volatile uint32_t SC1_SCL0_US6; /* SC1_SCL0_US6 */
+ volatile uint32_t SC1_SCL0_US7; /* SC1_SCL0_US7 */
+ volatile uint32_t SC1_SCL0_US8; /* SC1_SCL0_US8 */
+ volatile uint8_t dummy26[4]; /* */
+ volatile uint32_t SC1_SCL0_OVR1; /* SC1_SCL0_OVR1 */
+ volatile uint8_t dummy27[16]; /* */
+ volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */
+ volatile uint8_t dummy28[4]; /* */
+#define VDC5_SC1_SCL1_WR1_COUNT 4
+ volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */
+ volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */
+ volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */
+ volatile uint32_t SC1_SCL1_WR4; /* SC1_SCL1_WR4 */
+ volatile uint8_t dummy29[4]; /* */
+ volatile uint32_t SC1_SCL1_WR5; /* SC1_SCL1_WR5 */
+ volatile uint32_t SC1_SCL1_WR6; /* SC1_SCL1_WR6 */
+ volatile uint32_t SC1_SCL1_WR7; /* SC1_SCL1_WR7 */
+ volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */
+ volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */
+ volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */
+/* end of struct st_vdc5_from_sc0_scl0_update */
+ volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */
+ volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */
+/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
+#define VDC5_SC1_SCL1_PBUF0_COUNT 4
+ volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */
+ volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */
+ volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */
+ volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */
+ volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */
+ volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */
+/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
+ volatile uint8_t dummy30[44]; /* */
+/* start of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */
+ volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */
+#define VDC5_GR1_FLM1_COUNT 6
+ volatile uint32_t GR1_FLM1; /* GR1_FLM1 */
+ volatile uint32_t GR1_FLM2; /* GR1_FLM2 */
+ volatile uint32_t GR1_FLM3; /* GR1_FLM3 */
+ volatile uint32_t GR1_FLM4; /* GR1_FLM4 */
+ volatile uint32_t GR1_FLM5; /* GR1_FLM5 */
+ volatile uint32_t GR1_FLM6; /* GR1_FLM6 */
+#define VDC5_GR1_AB1_COUNT 3
+ volatile uint32_t GR1_AB1; /* GR1_AB1 */
+ volatile uint32_t GR1_AB2; /* GR1_AB2 */
+ volatile uint32_t GR1_AB3; /* GR1_AB3 */
+/* end of struct st_vdc5_from_gr0_update */
+ volatile uint32_t GR1_AB4; /* GR1_AB4 */
+ volatile uint32_t GR1_AB5; /* GR1_AB5 */
+ volatile uint32_t GR1_AB6; /* GR1_AB6 */
+/* start of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR1_AB7; /* GR1_AB7 */
+ volatile uint32_t GR1_AB8; /* GR1_AB8 */
+ volatile uint32_t GR1_AB9; /* GR1_AB9 */
+ volatile uint32_t GR1_AB10; /* GR1_AB10 */
+ volatile uint32_t GR1_AB11; /* GR1_AB11 */
+ volatile uint32_t GR1_BASE; /* GR1_BASE */
+/* end of struct st_vdc5_from_gr0_ab7 */
+ volatile uint32_t GR1_CLUT; /* GR1_CLUT */
+ volatile uint32_t GR1_MON; /* GR1_MON */
+ volatile uint8_t dummy31[40]; /* */
+/* start of struct st_vdc5_from_adj0_update */
+ volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */
+ volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */
+#define VDC5_ADJ1_ENH_TIM1_COUNT 3
+ volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */
+ volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */
+ volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */
+#define VDC5_ADJ1_ENH_SHP1_COUNT 6
+ volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */
+ volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */
+ volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */
+ volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */
+ volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */
+ volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */
+#define VDC5_ADJ1_ENH_LTI1_COUNT 2
+ volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */
+ volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */
+ volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */
+ volatile uint32_t ADJ1_MTX_YG_ADJ0; /* ADJ1_MTX_YG_ADJ0 */
+ volatile uint32_t ADJ1_MTX_YG_ADJ1; /* ADJ1_MTX_YG_ADJ1 */
+ volatile uint32_t ADJ1_MTX_CBB_ADJ0; /* ADJ1_MTX_CBB_ADJ0 */
+ volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */
+ volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */
+ volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */
+/* end of struct st_vdc5_from_adj0_update */
+ volatile uint8_t dummy32[48]; /* */
+ volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */
+ volatile uint8_t dummy33[28]; /* */
+#define VDC5_GR_VIN_AB1_COUNT 7
+ volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */
+ volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */
+ volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */
+ volatile uint32_t GR_VIN_AB4; /* GR_VIN_AB4 */
+ volatile uint32_t GR_VIN_AB5; /* GR_VIN_AB5 */
+ volatile uint32_t GR_VIN_AB6; /* GR_VIN_AB6 */
+ volatile uint32_t GR_VIN_AB7; /* GR_VIN_AB7 */
+ volatile uint8_t dummy34[16]; /* */
+ volatile uint32_t GR_VIN_BASE; /* GR_VIN_BASE */
+ volatile uint8_t dummy35[4]; /* */
+ volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */
+ volatile uint8_t dummy36[40]; /* */
+ volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */
+#define VDC5_OIR_SCL0_FRC1_COUNT 7
+ volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */
+ volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */
+ volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */
+ volatile uint32_t OIR_SCL0_FRC4; /* OIR_SCL0_FRC4 */
+ volatile uint32_t OIR_SCL0_FRC5; /* OIR_SCL0_FRC5 */
+ volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */
+ volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */
+ volatile uint8_t dummy37[12]; /* */
+#define VDC5_OIR_SCL0_DS1_COUNT 3
+ volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */
+ volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */
+ volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */
+ volatile uint8_t dummy38[12]; /* */
+ volatile uint32_t OIR_SCL0_DS7; /* OIR_SCL0_DS7 */
+ volatile uint32_t OIR_SCL0_US1; /* OIR_SCL0_US1 */
+ volatile uint32_t OIR_SCL0_US2; /* OIR_SCL0_US2 */
+ volatile uint32_t OIR_SCL0_US3; /* OIR_SCL0_US3 */
+ volatile uint8_t dummy39[16]; /* */
+ volatile uint32_t OIR_SCL0_US8; /* OIR_SCL0_US8 */
+ volatile uint8_t dummy40[4]; /* */
+ volatile uint32_t OIR_SCL0_OVR1; /* OIR_SCL0_OVR1 */
+ volatile uint8_t dummy41[16]; /* */
+ volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */
+ volatile uint8_t dummy42[4]; /* */
+#define VDC5_OIR_SCL1_WR1_COUNT 4
+ volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */
+ volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */
+ volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */
+ volatile uint32_t OIR_SCL1_WR4; /* OIR_SCL1_WR4 */
+ volatile uint8_t dummy43[4]; /* */
+ volatile uint32_t OIR_SCL1_WR5; /* OIR_SCL1_WR5 */
+ volatile uint32_t OIR_SCL1_WR6; /* OIR_SCL1_WR6 */
+ volatile uint32_t OIR_SCL1_WR7; /* OIR_SCL1_WR7 */
+ volatile uint8_t dummy44[88]; /* */
+ volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */
+ volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */
+#define VDC5_GR_OIR_FLM1_COUNT 6
+ volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */
+ volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */
+ volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */
+ volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */
+ volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */
+ volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */
+#define VDC5_GR_OIR_AB1_COUNT 3
+ volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */
+ volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */
+ volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */
+ volatile uint8_t dummy45[12]; /* */
+ volatile uint32_t GR_OIR_AB7; /* GR_OIR_AB7 */
+ volatile uint32_t GR_OIR_AB8; /* GR_OIR_AB8 */
+ volatile uint32_t GR_OIR_AB9; /* GR_OIR_AB9 */
+ volatile uint32_t GR_OIR_AB10; /* GR_OIR_AB10 */
+ volatile uint32_t GR_OIR_AB11; /* GR_OIR_AB11 */
+ volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */
+ volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */
+ volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */
+};
+
+
+struct st_vdc5_from_gr0_update
+{
+ volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */
+ volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */
+ volatile uint32_t GR0_FLM1; /* GR0_FLM1 */
+ volatile uint32_t GR0_FLM2; /* GR0_FLM2 */
+ volatile uint32_t GR0_FLM3; /* GR0_FLM3 */
+ volatile uint32_t GR0_FLM4; /* GR0_FLM4 */
+ volatile uint32_t GR0_FLM5; /* GR0_FLM5 */
+ volatile uint32_t GR0_FLM6; /* GR0_FLM6 */
+ volatile uint32_t GR0_AB1; /* GR0_AB1 */
+ volatile uint32_t GR0_AB2; /* GR0_AB2 */
+ volatile uint32_t GR0_AB3; /* GR0_AB3 */
+};
+
+
+struct st_vdc5_from_gr0_ab7
+{
+ volatile uint32_t GR0_AB7; /* GR0_AB7 */
+ volatile uint32_t GR0_AB8; /* GR0_AB8 */
+ volatile uint32_t GR0_AB9; /* GR0_AB9 */
+ volatile uint32_t GR0_AB10; /* GR0_AB10 */
+ volatile uint32_t GR0_AB11; /* GR0_AB11 */
+ volatile uint32_t GR0_BASE; /* GR0_BASE */
+};
+
+
+struct st_vdc5_from_adj0_update
+{
+ volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */
+ volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */
+ volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */
+ volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */
+ volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */
+ volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */
+ volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */
+ volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */
+ volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */
+ volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */
+ volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */
+ volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */
+ volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */
+ volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */
+ volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */
+ volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */
+ volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */
+ volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */
+ volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */
+ volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */
+};
+
+
+struct st_vdc5_from_sc0_scl0_update
+{
+ volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */
+ volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */
+ volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */
+ volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */
+ volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */
+ volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */
+ volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */
+ volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */
+ volatile uint8_t dummy5[4]; /* */
+ volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */
+ volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */
+ volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */
+ volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */
+ volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */
+ volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */
+ volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */
+ volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */
+ volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */
+ volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */
+ volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */
+ volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */
+ volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */
+ volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */
+ volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */
+ volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */
+ volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */
+ volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */
+ volatile uint8_t dummy6[4]; /* */
+ volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */
+ volatile uint8_t dummy7[16]; /* */
+ volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */
+ volatile uint8_t dummy8[4]; /* */
+ volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */
+ volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */
+ volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */
+ volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */
+ volatile uint8_t dummy9[4]; /* */
+ volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */
+ volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */
+ volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */
+ volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */
+ volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */
+ volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */
+};
+
+
+struct st_vdc5_from_sc0_scl1_pbuf0
+{
+ volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */
+ volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */
+ volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */
+ volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */
+ volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */
+ volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */
+};
+
+
+#define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */
+#define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */
+
+
+/* Start of channnel array defines of VDC5 */
+
+/* Channnel array defines of VDC5 */
+/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
+#define VDC5_COUNT 2
+#define VDC5_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+ &VDC50, &VDC51 \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+
+
+/* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */
+/*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
+#define VDC5n_FROM_GR2_AB7_ARRAY_COUNT 2
+#define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
+ &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
+#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
+#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
+#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */
+/*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
+#define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT 2
+#define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
+ &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
+#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
+#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
+#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */
+/*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
+#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT 2
+#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
+ &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
+#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
+#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
+#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */
+/*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
+#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT 2
+#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
+ &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
+#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
+#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
+#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */
+/*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
+#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT 2
+#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
+ &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
+#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
+#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
+#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */
+/*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
+#define VDC5n_FROM_GR0_AB7_ARRAY_COUNT 2
+#define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
+ &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
+#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
+#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
+#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */
+/*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
+#define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT 2
+#define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
+{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+ &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
+ &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
+} \
+} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
+#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
+#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
+#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
+
+
+/* End of channnel array defines of VDC5 */
+
+
+#define VDC50INP_UPDATE VDC50.INP_UPDATE
+#define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT
+#define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT
+#define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ
+#define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ
+#define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE
+#define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0
+#define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1
+#define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE
+#define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0
+#define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1
+#define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0
+#define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1
+#define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0
+#define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1
+#define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG
+#define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE
+#define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1
+#define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2
+#define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3
+#define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4
+#define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5
+#define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6
+#define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7
+#define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9
+#define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0
+#define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT
+#define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1
+#define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2
+#define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3
+#define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4
+#define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5
+#define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6
+#define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7
+#define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1
+#define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2
+#define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3
+#define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4
+#define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5
+#define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6
+#define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7
+#define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8
+#define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1
+#define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE
+#define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1
+#define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2
+#define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3
+#define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4
+#define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5
+#define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6
+#define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7
+#define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8
+#define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9
+#define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10
+#define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11
+#define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1
+#define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0
+#define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1
+#define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2
+#define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3
+#define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD
+#define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT
+#define VDC50GR0_UPDATE VDC50.GR0_UPDATE
+#define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD
+#define VDC50GR0_FLM1 VDC50.GR0_FLM1
+#define VDC50GR0_FLM2 VDC50.GR0_FLM2
+#define VDC50GR0_FLM3 VDC50.GR0_FLM3
+#define VDC50GR0_FLM4 VDC50.GR0_FLM4
+#define VDC50GR0_FLM5 VDC50.GR0_FLM5
+#define VDC50GR0_FLM6 VDC50.GR0_FLM6
+#define VDC50GR0_AB1 VDC50.GR0_AB1
+#define VDC50GR0_AB2 VDC50.GR0_AB2
+#define VDC50GR0_AB3 VDC50.GR0_AB3
+#define VDC50GR0_AB7 VDC50.GR0_AB7
+#define VDC50GR0_AB8 VDC50.GR0_AB8
+#define VDC50GR0_AB9 VDC50.GR0_AB9
+#define VDC50GR0_AB10 VDC50.GR0_AB10
+#define VDC50GR0_AB11 VDC50.GR0_AB11
+#define VDC50GR0_BASE VDC50.GR0_BASE
+#define VDC50GR0_CLUT VDC50.GR0_CLUT
+#define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE
+#define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET
+#define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1
+#define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2
+#define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3
+#define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1
+#define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2
+#define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3
+#define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4
+#define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5
+#define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6
+#define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1
+#define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2
+#define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE
+#define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0
+#define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1
+#define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0
+#define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1
+#define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0
+#define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1
+#define VDC50GR2_UPDATE VDC50.GR2_UPDATE
+#define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD
+#define VDC50GR2_FLM1 VDC50.GR2_FLM1
+#define VDC50GR2_FLM2 VDC50.GR2_FLM2
+#define VDC50GR2_FLM3 VDC50.GR2_FLM3
+#define VDC50GR2_FLM4 VDC50.GR2_FLM4
+#define VDC50GR2_FLM5 VDC50.GR2_FLM5
+#define VDC50GR2_FLM6 VDC50.GR2_FLM6
+#define VDC50GR2_AB1 VDC50.GR2_AB1
+#define VDC50GR2_AB2 VDC50.GR2_AB2
+#define VDC50GR2_AB3 VDC50.GR2_AB3
+#define VDC50GR2_AB4 VDC50.GR2_AB4
+#define VDC50GR2_AB5 VDC50.GR2_AB5
+#define VDC50GR2_AB6 VDC50.GR2_AB6
+#define VDC50GR2_AB7 VDC50.GR2_AB7
+#define VDC50GR2_AB8 VDC50.GR2_AB8
+#define VDC50GR2_AB9 VDC50.GR2_AB9
+#define VDC50GR2_AB10 VDC50.GR2_AB10
+#define VDC50GR2_AB11 VDC50.GR2_AB11
+#define VDC50GR2_BASE VDC50.GR2_BASE
+#define VDC50GR2_CLUT VDC50.GR2_CLUT
+#define VDC50GR2_MON VDC50.GR2_MON
+#define VDC50GR3_UPDATE VDC50.GR3_UPDATE
+#define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD
+#define VDC50GR3_FLM1 VDC50.GR3_FLM1
+#define VDC50GR3_FLM2 VDC50.GR3_FLM2
+#define VDC50GR3_FLM3 VDC50.GR3_FLM3
+#define VDC50GR3_FLM4 VDC50.GR3_FLM4
+#define VDC50GR3_FLM5 VDC50.GR3_FLM5
+#define VDC50GR3_FLM6 VDC50.GR3_FLM6
+#define VDC50GR3_AB1 VDC50.GR3_AB1
+#define VDC50GR3_AB2 VDC50.GR3_AB2
+#define VDC50GR3_AB3 VDC50.GR3_AB3
+#define VDC50GR3_AB4 VDC50.GR3_AB4
+#define VDC50GR3_AB5 VDC50.GR3_AB5
+#define VDC50GR3_AB6 VDC50.GR3_AB6
+#define VDC50GR3_AB7 VDC50.GR3_AB7
+#define VDC50GR3_AB8 VDC50.GR3_AB8
+#define VDC50GR3_AB9 VDC50.GR3_AB9
+#define VDC50GR3_AB10 VDC50.GR3_AB10
+#define VDC50GR3_AB11 VDC50.GR3_AB11
+#define VDC50GR3_BASE VDC50.GR3_BASE
+#define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT
+#define VDC50GR3_MON VDC50.GR3_MON
+#define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE
+#define VDC50GAM_SW VDC50.GAM_SW
+#define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1
+#define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2
+#define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3
+#define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4
+#define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5
+#define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6
+#define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7
+#define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8
+#define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9
+#define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10
+#define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11
+#define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12
+#define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13
+#define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14
+#define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15
+#define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16
+#define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1
+#define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2
+#define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3
+#define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4
+#define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5
+#define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6
+#define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7
+#define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8
+#define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE
+#define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1
+#define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2
+#define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3
+#define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4
+#define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5
+#define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6
+#define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7
+#define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8
+#define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9
+#define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10
+#define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11
+#define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12
+#define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13
+#define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14
+#define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15
+#define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16
+#define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1
+#define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2
+#define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3
+#define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4
+#define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5
+#define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6
+#define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7
+#define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8
+#define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE
+#define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1
+#define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2
+#define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3
+#define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4
+#define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5
+#define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6
+#define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7
+#define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8
+#define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9
+#define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10
+#define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11
+#define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12
+#define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13
+#define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14
+#define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15
+#define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16
+#define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1
+#define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2
+#define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3
+#define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4
+#define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5
+#define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6
+#define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7
+#define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8
+#define VDC50TCON_UPDATE VDC50.TCON_UPDATE
+#define VDC50TCON_TIM VDC50.TCON_TIM
+#define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1
+#define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2
+#define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1
+#define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2
+#define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1
+#define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2
+#define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1
+#define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2
+#define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1
+#define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2
+#define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1
+#define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2
+#define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1
+#define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2
+#define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE
+#define VDC50OUT_UPDATE VDC50.OUT_UPDATE
+#define VDC50OUT_SET VDC50.OUT_SET
+#define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1
+#define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2
+#define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST
+#define VDC50OUT_PDTHA VDC50.OUT_PDTHA
+#define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE
+#define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1
+#define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2
+#define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3
+#define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4
+#define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5
+#define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6
+#define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK
+#define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT
+#define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE
+#define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1
+#define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2
+#define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3
+#define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4
+#define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5
+#define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6
+#define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7
+#define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9
+#define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0
+#define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT
+#define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1
+#define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2
+#define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3
+#define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4
+#define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5
+#define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6
+#define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7
+#define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1
+#define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2
+#define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3
+#define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4
+#define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5
+#define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6
+#define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7
+#define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8
+#define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1
+#define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE
+#define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1
+#define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2
+#define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3
+#define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4
+#define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5
+#define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6
+#define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7
+#define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8
+#define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9
+#define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10
+#define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11
+#define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1
+#define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0
+#define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1
+#define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2
+#define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3
+#define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD
+#define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT
+#define VDC50GR1_UPDATE VDC50.GR1_UPDATE
+#define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD
+#define VDC50GR1_FLM1 VDC50.GR1_FLM1
+#define VDC50GR1_FLM2 VDC50.GR1_FLM2
+#define VDC50GR1_FLM3 VDC50.GR1_FLM3
+#define VDC50GR1_FLM4 VDC50.GR1_FLM4
+#define VDC50GR1_FLM5 VDC50.GR1_FLM5
+#define VDC50GR1_FLM6 VDC50.GR1_FLM6
+#define VDC50GR1_AB1 VDC50.GR1_AB1
+#define VDC50GR1_AB2 VDC50.GR1_AB2
+#define VDC50GR1_AB3 VDC50.GR1_AB3
+#define VDC50GR1_AB4 VDC50.GR1_AB4
+#define VDC50GR1_AB5 VDC50.GR1_AB5
+#define VDC50GR1_AB6 VDC50.GR1_AB6
+#define VDC50GR1_AB7 VDC50.GR1_AB7
+#define VDC50GR1_AB8 VDC50.GR1_AB8
+#define VDC50GR1_AB9 VDC50.GR1_AB9
+#define VDC50GR1_AB10 VDC50.GR1_AB10
+#define VDC50GR1_AB11 VDC50.GR1_AB11
+#define VDC50GR1_BASE VDC50.GR1_BASE
+#define VDC50GR1_CLUT VDC50.GR1_CLUT
+#define VDC50GR1_MON VDC50.GR1_MON
+#define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE
+#define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET
+#define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1
+#define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2
+#define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3
+#define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1
+#define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2
+#define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3
+#define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4
+#define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5
+#define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6
+#define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1
+#define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2
+#define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE
+#define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0
+#define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1
+#define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0
+#define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1
+#define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0
+#define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1
+#define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE
+#define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1
+#define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2
+#define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3
+#define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4
+#define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5
+#define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6
+#define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7
+#define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE
+#define VDC50GR_VIN_MON VDC50.GR_VIN_MON
+#define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE
+#define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1
+#define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2
+#define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3
+#define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4
+#define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5
+#define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6
+#define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7
+#define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1
+#define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2
+#define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3
+#define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7
+#define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1
+#define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2
+#define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3
+#define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8
+#define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1
+#define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE
+#define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1
+#define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2
+#define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3
+#define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4
+#define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5
+#define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6
+#define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7
+#define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE
+#define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD
+#define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1
+#define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2
+#define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3
+#define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4
+#define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5
+#define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6
+#define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1
+#define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2
+#define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3
+#define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7
+#define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8
+#define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9
+#define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10
+#define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11
+#define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE
+#define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT
+#define VDC50GR_OIR_MON VDC50.GR_OIR_MON
+#define VDC51INP_UPDATE VDC51.INP_UPDATE
+#define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT
+#define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT
+#define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ
+#define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ
+#define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE
+#define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0
+#define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1
+#define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE
+#define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0
+#define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1
+#define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0
+#define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1
+#define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0
+#define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1
+#define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG
+#define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE
+#define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1
+#define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2
+#define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3
+#define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4
+#define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5
+#define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6
+#define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7
+#define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9
+#define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0
+#define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT
+#define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1
+#define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2
+#define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3
+#define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4
+#define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5
+#define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6
+#define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7
+#define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1
+#define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2
+#define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3
+#define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4
+#define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5
+#define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6
+#define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7
+#define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8
+#define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1
+#define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE
+#define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1
+#define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2
+#define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3
+#define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4
+#define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5
+#define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6
+#define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7
+#define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8
+#define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9
+#define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10
+#define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11
+#define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1
+#define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0
+#define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1
+#define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2
+#define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3
+#define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD
+#define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT
+#define VDC51GR0_UPDATE VDC51.GR0_UPDATE
+#define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD
+#define VDC51GR0_FLM1 VDC51.GR0_FLM1
+#define VDC51GR0_FLM2 VDC51.GR0_FLM2
+#define VDC51GR0_FLM3 VDC51.GR0_FLM3
+#define VDC51GR0_FLM4 VDC51.GR0_FLM4
+#define VDC51GR0_FLM5 VDC51.GR0_FLM5
+#define VDC51GR0_FLM6 VDC51.GR0_FLM6
+#define VDC51GR0_AB1 VDC51.GR0_AB1
+#define VDC51GR0_AB2 VDC51.GR0_AB2
+#define VDC51GR0_AB3 VDC51.GR0_AB3
+#define VDC51GR0_AB7 VDC51.GR0_AB7
+#define VDC51GR0_AB8 VDC51.GR0_AB8
+#define VDC51GR0_AB9 VDC51.GR0_AB9
+#define VDC51GR0_AB10 VDC51.GR0_AB10
+#define VDC51GR0_AB11 VDC51.GR0_AB11
+#define VDC51GR0_BASE VDC51.GR0_BASE
+#define VDC51GR0_CLUT VDC51.GR0_CLUT
+#define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE
+#define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET
+#define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1
+#define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2
+#define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3
+#define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1
+#define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2
+#define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3
+#define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4
+#define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5
+#define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6
+#define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1
+#define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2
+#define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE
+#define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0
+#define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1
+#define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0
+#define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1
+#define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0
+#define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1
+#define VDC51GR2_UPDATE VDC51.GR2_UPDATE
+#define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD
+#define VDC51GR2_FLM1 VDC51.GR2_FLM1
+#define VDC51GR2_FLM2 VDC51.GR2_FLM2
+#define VDC51GR2_FLM3 VDC51.GR2_FLM3
+#define VDC51GR2_FLM4 VDC51.GR2_FLM4
+#define VDC51GR2_FLM5 VDC51.GR2_FLM5
+#define VDC51GR2_FLM6 VDC51.GR2_FLM6
+#define VDC51GR2_AB1 VDC51.GR2_AB1
+#define VDC51GR2_AB2 VDC51.GR2_AB2
+#define VDC51GR2_AB3 VDC51.GR2_AB3
+#define VDC51GR2_AB4 VDC51.GR2_AB4
+#define VDC51GR2_AB5 VDC51.GR2_AB5
+#define VDC51GR2_AB6 VDC51.GR2_AB6
+#define VDC51GR2_AB7 VDC51.GR2_AB7
+#define VDC51GR2_AB8 VDC51.GR2_AB8
+#define VDC51GR2_AB9 VDC51.GR2_AB9
+#define VDC51GR2_AB10 VDC51.GR2_AB10
+#define VDC51GR2_AB11 VDC51.GR2_AB11
+#define VDC51GR2_BASE VDC51.GR2_BASE
+#define VDC51GR2_CLUT VDC51.GR2_CLUT
+#define VDC51GR2_MON VDC51.GR2_MON
+#define VDC51GR3_UPDATE VDC51.GR3_UPDATE
+#define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD
+#define VDC51GR3_FLM1 VDC51.GR3_FLM1
+#define VDC51GR3_FLM2 VDC51.GR3_FLM2
+#define VDC51GR3_FLM3 VDC51.GR3_FLM3
+#define VDC51GR3_FLM4 VDC51.GR3_FLM4
+#define VDC51GR3_FLM5 VDC51.GR3_FLM5
+#define VDC51GR3_FLM6 VDC51.GR3_FLM6
+#define VDC51GR3_AB1 VDC51.GR3_AB1
+#define VDC51GR3_AB2 VDC51.GR3_AB2
+#define VDC51GR3_AB3 VDC51.GR3_AB3
+#define VDC51GR3_AB4 VDC51.GR3_AB4
+#define VDC51GR3_AB5 VDC51.GR3_AB5
+#define VDC51GR3_AB6 VDC51.GR3_AB6
+#define VDC51GR3_AB7 VDC51.GR3_AB7
+#define VDC51GR3_AB8 VDC51.GR3_AB8
+#define VDC51GR3_AB9 VDC51.GR3_AB9
+#define VDC51GR3_AB10 VDC51.GR3_AB10
+#define VDC51GR3_AB11 VDC51.GR3_AB11
+#define VDC51GR3_BASE VDC51.GR3_BASE
+#define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT
+#define VDC51GR3_MON VDC51.GR3_MON
+#define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE
+#define VDC51GAM_SW VDC51.GAM_SW
+#define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1
+#define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2
+#define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3
+#define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4
+#define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5
+#define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6
+#define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7
+#define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8
+#define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9
+#define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10
+#define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11
+#define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12
+#define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13
+#define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14
+#define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15
+#define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16
+#define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1
+#define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2
+#define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3
+#define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4
+#define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5
+#define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6
+#define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7
+#define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8
+#define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE
+#define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1
+#define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2
+#define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3
+#define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4
+#define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5
+#define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6
+#define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7
+#define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8
+#define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9
+#define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10
+#define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11
+#define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12
+#define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13
+#define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14
+#define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15
+#define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16
+#define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1
+#define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2
+#define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3
+#define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4
+#define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5
+#define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6
+#define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7
+#define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8
+#define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE
+#define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1
+#define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2
+#define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3
+#define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4
+#define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5
+#define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6
+#define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7
+#define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8
+#define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9
+#define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10
+#define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11
+#define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12
+#define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13
+#define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14
+#define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15
+#define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16
+#define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1
+#define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2
+#define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3
+#define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4
+#define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5
+#define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6
+#define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7
+#define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8
+#define VDC51TCON_UPDATE VDC51.TCON_UPDATE
+#define VDC51TCON_TIM VDC51.TCON_TIM
+#define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1
+#define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2
+#define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1
+#define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2
+#define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1
+#define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2
+#define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1
+#define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2
+#define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1
+#define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2
+#define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1
+#define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2
+#define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1
+#define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2
+#define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE
+#define VDC51OUT_UPDATE VDC51.OUT_UPDATE
+#define VDC51OUT_SET VDC51.OUT_SET
+#define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1
+#define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2
+#define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST
+#define VDC51OUT_PDTHA VDC51.OUT_PDTHA
+#define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE
+#define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1
+#define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2
+#define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3
+#define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4
+#define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5
+#define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6
+#define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK
+#define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT
+#define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE
+#define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1
+#define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2
+#define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3
+#define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4
+#define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5
+#define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6
+#define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7
+#define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9
+#define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0
+#define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT
+#define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1
+#define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2
+#define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3
+#define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4
+#define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5
+#define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6
+#define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7
+#define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1
+#define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2
+#define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3
+#define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4
+#define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5
+#define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6
+#define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7
+#define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8
+#define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1
+#define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE
+#define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1
+#define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2
+#define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3
+#define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4
+#define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5
+#define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6
+#define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7
+#define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8
+#define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9
+#define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10
+#define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11
+#define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1
+#define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0
+#define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1
+#define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2
+#define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3
+#define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD
+#define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT
+#define VDC51GR1_UPDATE VDC51.GR1_UPDATE
+#define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD
+#define VDC51GR1_FLM1 VDC51.GR1_FLM1
+#define VDC51GR1_FLM2 VDC51.GR1_FLM2
+#define VDC51GR1_FLM3 VDC51.GR1_FLM3
+#define VDC51GR1_FLM4 VDC51.GR1_FLM4
+#define VDC51GR1_FLM5 VDC51.GR1_FLM5
+#define VDC51GR1_FLM6 VDC51.GR1_FLM6
+#define VDC51GR1_AB1 VDC51.GR1_AB1
+#define VDC51GR1_AB2 VDC51.GR1_AB2
+#define VDC51GR1_AB3 VDC51.GR1_AB3
+#define VDC51GR1_AB4 VDC51.GR1_AB4
+#define VDC51GR1_AB5 VDC51.GR1_AB5
+#define VDC51GR1_AB6 VDC51.GR1_AB6
+#define VDC51GR1_AB7 VDC51.GR1_AB7
+#define VDC51GR1_AB8 VDC51.GR1_AB8
+#define VDC51GR1_AB9 VDC51.GR1_AB9
+#define VDC51GR1_AB10 VDC51.GR1_AB10
+#define VDC51GR1_AB11 VDC51.GR1_AB11
+#define VDC51GR1_BASE VDC51.GR1_BASE
+#define VDC51GR1_CLUT VDC51.GR1_CLUT
+#define VDC51GR1_MON VDC51.GR1_MON
+#define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE
+#define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET
+#define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1
+#define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2
+#define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3
+#define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1
+#define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2
+#define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3
+#define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4
+#define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5
+#define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6
+#define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1
+#define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2
+#define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE
+#define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0
+#define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1
+#define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0
+#define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1
+#define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0
+#define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1
+#define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE
+#define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1
+#define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2
+#define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3
+#define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4
+#define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5
+#define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6
+#define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7
+#define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE
+#define VDC51GR_VIN_MON VDC51.GR_VIN_MON
+#define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE
+#define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1
+#define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2
+#define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3
+#define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4
+#define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5
+#define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6
+#define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7
+#define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1
+#define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2
+#define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3
+#define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7
+#define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1
+#define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2
+#define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3
+#define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8
+#define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1
+#define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE
+#define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1
+#define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2
+#define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3
+#define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4
+#define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5
+#define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6
+#define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7
+#define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE
+#define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD
+#define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1
+#define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2
+#define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3
+#define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4
+#define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5
+#define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6
+#define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1
+#define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2
+#define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3
+#define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7
+#define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8
+#define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9
+#define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10
+#define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11
+#define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE
+#define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT
+#define VDC51GR_OIR_MON VDC51.GR_OIR_MON
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,47 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : wdt_iodefine.h
+* $Rev: $
+* $Date:: $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef WDT_IODEFINE_H
+#define WDT_IODEFINE_H
+
+struct st_wdt
+{ /* WDT */
+ volatile uint16_t WTCSR; /* WTCSR */
+ volatile uint16_t WTCNT; /* WTCNT */
+ volatile uint16_t WRCSR; /* WRCSR */
+};
+
+
+#define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */
+
+
+#define WDTWTCSR WDT.WTCSR
+#define WDTWTCNT WDT.WTCNT
+#define WDTWRCSR WDT.WRCSR
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/reg32_t.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,12 @@
+#ifndef __REG32_T
+#define __REG32_T
+
+union reg32_t {
+ volatile uint32_t UINT32;
+ volatile uint16_t UINT16[2];
+ volatile uint8_t UINT8[4];
+};
+
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/rza_io_regrw.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rza_io_regrw.h
+* $Rev: 1135 $
+* $Date:: 2014-08-08 10:11:30 +0900#$
+* Description : Low level register read/write header
+*******************************************************************************/
+#ifndef RZA_IO_REGRW_H
+#define RZA_IO_REGRW_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+/* ==== includes each bit mask header ==== */
+#include "cpg_iobitmask.h"
+#include "intc_iobitmask.h"
+#include "bsc_iobitmask.h"
+#include "dmac_iobitmask.h"
+#include "mtu2_iobitmask.h"
+#include "ostm_iobitmask.h"
+#include "scif_iobitmask.h"
+#include "rspi_iobitmask.h"
+#include "riic_iobitmask.h"
+#include "usb_iobitmask.h"
+#include "gpio_iobitmask.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void RZA_IO_RegWrite_8 (volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask);
+void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask);
+void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask);
+uint8_t RZA_IO_RegRead_8 (volatile uint8_t * ioreg, uint8_t shift, uint8_t mask);
+uint16_t RZA_IO_RegRead_16 (volatile uint16_t * ioreg, uint16_t shift, uint16_t mask);
+uint32_t RZA_IO_RegRead_32 (volatile uint32_t * ioreg, uint32_t shift, uint32_t mask);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RZA_IO_REGRW_H */
+
+/* End of File */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mbed_sf_boot.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,829 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file mbed_sf_boot.c
+* $Rev: $
+* $Date:: $
+* @brief RZ_A1 serial flash boot loader
+******************************************************************************/
+#if defined (__CC_ARM)
+#pragma arm section rodata = "BOOT_LOADER"
+const char boot_loader[] __attribute__((used)) =
+
+#elif defined (__ICCARM__)
+__root const char boot_loader[] @ 0x18000000 =
+#else
+const char boot_loader[] __attribute__ ((section(".boot_loader"), used)) =
+
+#endif
+{
+ 0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,
+ 0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,
+ 0x00,0x30,0x00,0x18,0x74,0x30,0x00,0x18,0x78,0x30,0x00,0x18,0x7C,0x30,0x00,0x18,
+ 0x80,0x30,0x00,0x18,0x84,0x30,0x00,0x18,0x88,0x30,0x00,0x18,0x8C,0x30,0x00,0x18,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0x2C,0x30,0x9F,0xE5,0x00,0x20,0xA0,0xE3,0x28,0x10,0x9F,0xE5,0x28,0x00,0x9F,0xE5,
+ 0x10,0x40,0x2D,0xE9,0x23,0x31,0xA0,0xE1,0x02,0x00,0x00,0xEA,0x04,0x40,0x91,0xE4,
+ 0x01,0x20,0x82,0xE2,0x04,0x40,0x80,0xE4,0x03,0x00,0x52,0xE1,0xFA,0xFF,0xFF,0xBA,
+ 0x10,0x80,0xBD,0xE8,0x97,0x28,0x00,0x00,0x00,0x04,0x00,0x18,0x00,0x02,0x02,0x20,
+ 0x70,0x40,0x2D,0xE9,0x02,0x29,0xA0,0xE3,0xC8,0x40,0x9F,0xE5,0x0F,0x10,0xA0,0xE3,
+ 0x04,0x00,0xA0,0xE1,0x4C,0x00,0x00,0xEB,0x01,0x00,0x50,0xE3,0x06,0x00,0x00,0x1A,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+ 0x33,0x00,0x00,0xEB,0x08,0x00,0x44,0xE2,0xB8,0x00,0xD0,0xE1,0x01,0x34,0xA0,0xE3,
+ 0x94,0x50,0x9F,0xE5,0x18,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,
+ 0x32,0x00,0x00,0xEB,0x3C,0x40,0x85,0xE2,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x04,0x00,0xA0,0xE1,0x3C,0x00,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF9,0xFF,0xFF,0x1A,
+ 0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x36,0x00,0x00,0xEB,
+ 0x01,0x00,0x50,0xE3,0xF9,0xFF,0xFF,0x1A,0x00,0x00,0xA0,0xE3,0x4C,0x10,0x9F,0xE5,
+ 0x04,0x00,0x81,0xE5,0x00,0x20,0xA0,0xE1,0x44,0x40,0x9F,0xE5,0x00,0x10,0xA0,0xE1,
+ 0x03,0x30,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x1C,0x00,0x00,0xEB,0xFF,0x3C,0xA0,0xE3,
+ 0x08,0x20,0xA0,0xE3,0x02,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x17,0x00,0x00,0xEB,
+ 0x05,0x00,0xA0,0xE1,0x01,0x3C,0xA0,0xE3,0x70,0x40,0xBD,0xE8,0x08,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x11,0x00,0x00,0xEA,0x08,0x18,0xFF,0xFC,0x0C,0xA0,0xEF,0x3F,
+ 0x00,0xA0,0xEF,0x3F,0x08,0xA0,0xEF,0x3F,0x10,0x40,0x2D,0xE9,0x00,0x40,0xD0,0xE5,
+ 0x11,0x12,0xA0,0xE1,0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1,0x00,0x10,0xC0,0xE5,
+ 0x10,0x80,0xBD,0xE8,0x10,0x40,0x2D,0xE9,0xB0,0x40,0xD0,0xE1,0x11,0x12,0xA0,0xE1,
+ 0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1,0xB0,0x10,0xC0,0xE1,0x10,0x80,0xBD,0xE8,
+ 0x10,0x40,0x2D,0xE9,0x00,0x40,0x90,0xE5,0x11,0x12,0xA0,0xE1,0x03,0x20,0xC4,0xE1,
+ 0x02,0x10,0x81,0xE1,0x00,0x10,0x80,0xE5,0x10,0x80,0xBD,0xE8,0x00,0x00,0xD0,0xE5,
+ 0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0xB0,0x00,0xD0,0xE1,
+ 0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x90,0xE5,
+ 0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0x10,0xFF,0x2F,0xE1,0x10,0x40,0x2D,0xE9,0x00,0x00,0xA0,0xE3,0x7D,0x03,0x00,0xEB,
+ 0x2C,0x10,0x9F,0xE5,0x00,0x00,0xA0,0xE3,0x7B,0x03,0x00,0xEB,0x20,0x20,0x9F,0xE5,
+ 0x00,0x10,0xA0,0xE3,0x01,0x00,0xA0,0xE1,0x51,0x03,0x00,0xEB,0x00,0x00,0x50,0xE3,
+ 0x00,0x00,0x00,0x0A,0xFE,0xFF,0xFF,0xEA,0x10,0x40,0xBD,0xE8,0x04,0x00,0x9F,0xE5,
+ 0xEE,0xFF,0xFF,0xEA,0x94,0x2A,0x02,0x20,0x00,0x40,0x00,0x18,0xF0,0x41,0x2D,0xE9,
+ 0x00,0x40,0xA0,0xE1,0x03,0x70,0xA0,0xE1,0x02,0x50,0xA0,0xE1,0x18,0x60,0x9D,0xE5,
+ 0x01,0x80,0xA0,0xE1,0x01,0x00,0xA0,0xE1,0xD9,0x01,0x00,0xEB,0x00,0x00,0x50,0xE3,
+ 0xF0,0x81,0xBD,0x18,0x00,0x00,0xA0,0xE3,0x01,0x20,0xA0,0xE3,0x0F,0x00,0x56,0xE3,
+ 0x54,0x16,0x9F,0xE5,0x18,0x30,0x81,0xE2,0x00,0x00,0x81,0xE5,0x08,0x00,0x81,0xE5,
+ 0x14,0x20,0x81,0xE5,0xD8,0x20,0xA0,0x13,0x41,0x00,0x83,0xE8,0xDC,0x20,0xA0,0x03,
+ 0x20,0x00,0x81,0xE5,0x01,0x00,0x55,0xE3,0x24,0x00,0x81,0xE5,0x28,0x00,0x81,0xE5,
+ 0x2C,0x00,0x81,0xE5,0x30,0x00,0x81,0xE5,0x46,0x20,0xC1,0xE5,0xA4,0x20,0xA0,0x01,
+ 0x48,0x20,0x81,0x05,0x48,0x40,0x81,0x15,0x34,0x00,0x81,0xE5,0x38,0x00,0x81,0xE5,
+ 0x3C,0x00,0x81,0xE5,0x40,0x00,0x81,0xE5,0x08,0x00,0xA0,0xE1,0xF8,0x15,0x9F,0xE5,
+ 0x91,0x08,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x07,0x20,0xA0,0xE1,
+ 0x05,0x10,0xA0,0xE1,0x08,0x00,0xA0,0xE1,0xF0,0x41,0xBD,0xE8,0x9E,0x01,0x00,0xEA,
+ 0xFF,0x5F,0x2D,0xE9,0x00,0xB0,0xA0,0xE1,0x02,0x70,0xA0,0xE1,0x01,0x60,0xA0,0xE1,
+ 0x0C,0x00,0x9D,0xE5,0x40,0x80,0x9D,0xE5,0x3C,0x90,0x9D,0xE5,0x38,0xA0,0x9D,0xE5,
+ 0xAB,0x01,0x00,0xEB,0x00,0x00,0x50,0xE3,0x7A,0x00,0x00,0x1A,0x00,0x50,0xA0,0xE3,
+ 0xA4,0x45,0x9F,0xE5,0x01,0x00,0xA0,0xE3,0x00,0x00,0x59,0xE3,0x14,0x10,0x84,0xE2,
+ 0x00,0x50,0x84,0xE5,0x08,0x50,0x84,0xE5,0x21,0x01,0x81,0xE8,0x28,0x10,0x84,0xE2,
+ 0x20,0x50,0x84,0xE5,0x24,0x50,0x84,0xE5,0x21,0x00,0x81,0xE8,0x30,0x50,0x84,0xE5,
+ 0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,0x40,0x50,0x84,0xE5,
+ 0x22,0x00,0x00,0x0A,0x0F,0x00,0x58,0xE3,0x34,0x00,0xA0,0x03,0x32,0x00,0xA0,0x13,
+ 0x01,0x00,0x5A,0xE3,0x50,0x15,0x9F,0xE5,0x46,0x00,0xC4,0xE5,0xAB,0x00,0xA0,0x01,
+ 0x48,0x00,0x84,0x05,0x48,0xB0,0x84,0x15,0x0C,0x00,0x9D,0xE5,0x62,0x08,0x00,0xEB,
+ 0x00,0x00,0x50,0xE3,0x5B,0x00,0x00,0x1A,0x14,0x50,0x84,0xE5,0x10,0x90,0x84,0xE5,
+ 0x01,0x30,0xA0,0xE3,0x18,0x50,0x84,0xE5,0x01,0x00,0x5A,0xE3,0x1C,0x50,0x84,0xE5,
+ 0x0F,0x00,0xA0,0xE3,0x20,0x50,0x84,0xE5,0x08,0x10,0xA0,0xE3,0x30,0x30,0x84,0xE5,
+ 0x0C,0x20,0xA0,0xE3,0x2C,0x50,0x84,0xE5,0x0C,0x00,0x00,0x0A,0x03,0x00,0x17,0xE3,
+ 0x20,0x00,0x00,0x0A,0x01,0x00,0x17,0xE3,0x23,0x00,0x00,0x0A,0x00,0x00,0x57,0xE3,
+ 0x01,0x80,0xA0,0xE3,0x24,0x10,0x84,0xE5,0x42,0x00,0x00,0xDA,0x2C,0x00,0x00,0xEA,
+ 0x0F,0x00,0x58,0xE3,0x02,0x00,0xA0,0x13,0x12,0x00,0xA0,0x03,0xDB,0xFF,0xFF,0xEA,
+ 0x07,0x00,0x17,0xE3,0x09,0x00,0x00,0x0A,0x03,0x00,0x17,0xE3,0x0C,0x00,0x00,0x0A,
+ 0x01,0x00,0x17,0xE3,0x00,0x00,0xE0,0x13,0x3A,0x00,0x00,0x1A,0x00,0x00,0x57,0xE3,
+ 0x02,0x80,0xA0,0xE3,0x24,0x10,0x84,0xE5,0x1F,0x00,0x00,0xCA,0x31,0x00,0x00,0xEA,
+ 0x00,0x00,0x57,0xE3,0x08,0x80,0xA0,0xE3,0x24,0x00,0x84,0xE5,0x1E,0x00,0x00,0xCA,
+ 0x2C,0x00,0x00,0xEA,0x00,0x00,0x57,0xE3,0x04,0x80,0xA0,0xE3,0x24,0x20,0x84,0xE5,
+ 0x17,0x00,0x00,0xCA,0x27,0x00,0x00,0xEA,0x00,0x00,0x57,0xE3,0x04,0x80,0xA0,0xE3,
+ 0x24,0x00,0x84,0xE5,0x12,0x00,0x00,0xCA,0x22,0x00,0x00,0xEA,0x00,0x00,0x57,0xE3,
+ 0x02,0x80,0xA0,0xE3,0x24,0x20,0x84,0xE5,0x0B,0x00,0x00,0xCA,0x1D,0x00,0x00,0xEA,
+ 0x01,0x00,0x58,0xE3,0x06,0x00,0x00,0x0A,0x02,0x00,0x58,0xE3,0x06,0x00,0x00,0x0A,
+ 0x04,0x00,0x58,0xE3,0x06,0x00,0x00,0x0A,0x08,0x00,0x58,0xE3,0x0A,0x00,0x00,0x1A,
+ 0x05,0x00,0x00,0xEA,0x00,0x00,0xD6,0xE5,0x06,0x00,0x00,0xEA,0xB0,0x00,0xD6,0xE1,
+ 0x04,0x00,0x00,0xEA,0x00,0x00,0x96,0xE5,0x02,0x00,0x00,0xEA,0x00,0x10,0x96,0xE5,
+ 0x5C,0x10,0x84,0xE5,0x04,0x00,0x96,0xE5,0x58,0x00,0x84,0xE5,0x08,0x70,0x47,0xE0,
+ 0x00,0x00,0x57,0xE3,0xF0,0x13,0x9F,0xE5,0x28,0x50,0x84,0xD5,0x08,0x60,0x86,0xE0,
+ 0x0C,0x00,0x9D,0xE5,0x0C,0x08,0x00,0xEB,0x00,0x00,0x50,0xE3,0x05,0x00,0x00,0x1A,
+ 0x00,0x00,0x57,0xE3,0xE1,0xFF,0xFF,0xCA,0x0C,0x00,0x9D,0xE5,0x09,0x20,0xA0,0xE1,
+ 0x0A,0x10,0xA0,0xE1,0x18,0x01,0x00,0xEB,0x10,0xD0,0x8D,0xE2,0xF0,0x9F,0xBD,0xE8,
+ 0xF0,0x47,0x2D,0xE9,0x01,0x50,0xA0,0xE1,0xAC,0x43,0x9F,0xE5,0x00,0x70,0xA0,0xE3,
+ 0x24,0x10,0x9D,0xE5,0x01,0x80,0xA0,0xE3,0x20,0x90,0x9D,0xE5,0x02,0x60,0xA0,0xE1,
+ 0x1C,0x20,0x84,0xE2,0x03,0xA0,0xA0,0xE1,0x00,0x70,0x84,0xE5,0x0F,0x00,0x51,0xE3,
+ 0x08,0x70,0x84,0xE5,0x14,0x80,0x84,0xE5,0x18,0x70,0x84,0xE5,0x82,0x00,0x82,0xE8,
+ 0x24,0x20,0x84,0xE2,0x6C,0x10,0xA0,0x03,0x6B,0x10,0xA0,0x13,0x80,0x01,0x82,0xE8,
+ 0x01,0x00,0x59,0xE3,0x2C,0x70,0x84,0xE5,0xA0,0x00,0xA0,0x01,0x30,0x70,0x84,0xE5,
+ 0x46,0x10,0xC4,0xE5,0x07,0x10,0xA0,0xE3,0x34,0x80,0x84,0xE5,0x44,0x70,0xC4,0xE5,
+ 0x45,0x10,0xC4,0xE5,0x38,0x70,0x84,0xE5,0x3C,0x70,0x84,0xE5,0x38,0x13,0x9F,0xE5,
+ 0x40,0x70,0x84,0xE5,0x48,0x00,0x84,0xE5,0x03,0x00,0xA0,0xE1,0xDE,0x07,0x00,0xEB,
+ 0x00,0x00,0x50,0xE3,0xF0,0x87,0xBD,0x18,0x02,0x30,0xA0,0xE3,0x10,0xC0,0x84,0xE2,
+ 0x01,0x00,0x59,0xE3,0x0F,0x00,0xA0,0xE3,0x08,0x10,0xA0,0xE3,0x88,0x00,0x8C,0xE8,
+ 0x0C,0x20,0xA0,0xE3,0x18,0x70,0x84,0xE5,0x1C,0x70,0x84,0xE5,0x20,0x70,0x84,0xE5,
+ 0x2C,0x80,0x84,0xE5,0x30,0x70,0x84,0xE5,0x34,0x70,0x84,0xE5,0x04,0x00,0x00,0x0A,
+ 0x04,0x00,0x56,0xE3,0x1F,0x00,0x00,0x0A,0x02,0x00,0x56,0xE3,0x1F,0x00,0x00,0x0A,
+ 0x06,0x00,0x00,0xEA,0x08,0x00,0x56,0xE3,0x1A,0x00,0x00,0x0A,0x04,0x00,0x56,0xE3,
+ 0x1A,0x00,0x00,0x0A,0x02,0x00,0x56,0xE3,0x00,0x00,0xE0,0x13,0xF0,0x87,0xBD,0x18,
+ 0x24,0x10,0x84,0xE5,0x0A,0x00,0xA0,0xE1,0x28,0x70,0x84,0xE5,0xA8,0x12,0x9F,0xE5,
+ 0xBD,0x07,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x87,0xBD,0x18,0x01,0x00,0x56,0xE3,
+ 0x50,0x00,0xD4,0x05,0x00,0x00,0xC5,0x05,0x12,0x00,0x00,0x0A,0x02,0x00,0x56,0xE3,
+ 0xB0,0x05,0xD4,0x01,0xB0,0x00,0xC5,0x01,0x0E,0x00,0x00,0x0A,0x04,0x00,0x56,0xE3,
+ 0x50,0x00,0x94,0x05,0x00,0x00,0x85,0x05,0x0A,0x00,0x00,0x0A,0x08,0x00,0x56,0xE3,
+ 0x04,0x00,0x00,0x0A,0x07,0x00,0x00,0xEA,0x24,0x00,0x84,0xE5,0xE8,0xFF,0xFF,0xEA,
+ 0x24,0x20,0x84,0xE5,0xE6,0xFF,0xFF,0xEA,0x54,0x00,0x94,0xE5,0x00,0x00,0x85,0xE5,
+ 0x50,0x00,0x94,0xE5,0x04,0x00,0x85,0xE5,0x00,0x00,0xA0,0xE3,0xF0,0x87,0xBD,0xE8,
+ 0xF0,0x5F,0x2D,0xE9,0x01,0x60,0xA0,0xE1,0x2C,0x42,0x9F,0xE5,0x00,0x50,0xA0,0xE3,
+ 0x2C,0x10,0x9D,0xE5,0x01,0x80,0xA0,0xE3,0x28,0xA0,0x9D,0xE5,0x02,0x70,0xA0,0xE1,
+ 0x1C,0x20,0x84,0xE2,0x0C,0x90,0xA0,0xE3,0x00,0x50,0x84,0xE5,0x0F,0x00,0x51,0xE3,
+ 0x08,0x50,0x84,0xE5,0x03,0xB0,0xA0,0xE1,0x14,0x80,0x84,0xE5,0x18,0x50,0x84,0xE5,
+ 0x22,0x00,0x82,0xE8,0x24,0x20,0x84,0xE2,0x0B,0x10,0xA0,0x13,0x20,0x01,0x82,0xE8,
+ 0x2C,0x50,0x84,0xE5,0x30,0x50,0x84,0xE5,0x46,0x90,0xC4,0x05,0x46,0x10,0xC4,0x15,
+ 0x07,0x10,0xA0,0xE3,0x34,0x80,0x84,0xE5,0x01,0x00,0x5A,0xE3,0x44,0x50,0xC4,0xE5,
+ 0xA0,0x00,0xA0,0x01,0x45,0x10,0xC4,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,
+ 0xB4,0x11,0x9F,0xE5,0x40,0x50,0x84,0xE5,0x48,0x00,0x84,0xE5,0x03,0x00,0xA0,0xE1,
+ 0x7D,0x07,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x9F,0xBD,0x18,0x0F,0x00,0xA0,0xE3,
+ 0x01,0x00,0x5A,0xE3,0x08,0x10,0xA0,0xE3,0x10,0x50,0x84,0xE5,0x14,0x50,0x84,0xE5,
+ 0x18,0x50,0x84,0xE5,0x1C,0x50,0x84,0xE5,0x20,0x50,0x84,0xE5,0x2C,0x80,0x84,0xE5,
+ 0x30,0x50,0x84,0xE5,0x34,0x50,0x84,0xE5,0x04,0x00,0x00,0x0A,0x04,0x00,0x57,0xE3,
+ 0x1F,0x00,0x00,0x0A,0x02,0x00,0x57,0xE3,0x1F,0x00,0x00,0x0A,0x06,0x00,0x00,0xEA,
+ 0x08,0x00,0x57,0xE3,0x1A,0x00,0x00,0x0A,0x04,0x00,0x57,0xE3,0x1A,0x00,0x00,0x0A,
+ 0x02,0x00,0x57,0xE3,0x00,0x00,0xE0,0x13,0xF0,0x9F,0xBD,0x18,0x24,0x10,0x84,0xE5,
+ 0x0B,0x00,0xA0,0xE1,0x28,0x50,0x84,0xE5,0x2C,0x11,0x9F,0xE5,0x5E,0x07,0x00,0xEB,
+ 0x00,0x00,0x50,0xE3,0xF0,0x9F,0xBD,0x18,0x01,0x00,0x57,0xE3,0x50,0x00,0xD4,0x05,
+ 0x00,0x00,0xC6,0x05,0x12,0x00,0x00,0x0A,0x02,0x00,0x57,0xE3,0xB0,0x05,0xD4,0x01,
+ 0xB0,0x00,0xC6,0x01,0x0E,0x00,0x00,0x0A,0x04,0x00,0x57,0xE3,0x50,0x00,0x94,0x05,
+ 0x00,0x00,0x86,0x05,0x0A,0x00,0x00,0x0A,0x08,0x00,0x57,0xE3,0x04,0x00,0x00,0x0A,
+ 0x07,0x00,0x00,0xEA,0x24,0x00,0x84,0xE5,0xE8,0xFF,0xFF,0xEA,0x24,0x90,0x84,0xE5,
+ 0xE6,0xFF,0xFF,0xEA,0x54,0x00,0x94,0xE5,0x00,0x00,0x86,0xE5,0x50,0x00,0x94,0xE5,
+ 0x04,0x00,0x86,0xE5,0x00,0x00,0xA0,0xE3,0xF0,0x9F,0xBD,0xE8,0xFC,0x5F,0x2D,0xE9,
+ 0x00,0x80,0xA0,0xE1,0x30,0x00,0x8D,0xE2,0x03,0xB0,0xA0,0xE1,0x38,0x90,0x9D,0xE5,
+ 0x02,0x50,0xA0,0xE1,0x40,0x04,0x90,0xE8,0x01,0x70,0xA0,0xE1,0x01,0x00,0x56,0xE3,
+ 0x00,0x00,0xA0,0xE3,0x05,0x00,0x00,0x0A,0x03,0x00,0x15,0xE3,0x0D,0x00,0x00,0x0A,
+ 0x01,0x00,0x15,0xE3,0x01,0x40,0xA0,0x13,0x08,0x00,0x00,0x0A,0x0A,0x00,0x00,0xEA,
+ 0x07,0x00,0x15,0xE3,0x08,0x40,0xA0,0x03,0x07,0x00,0x00,0x0A,0x03,0x00,0x15,0xE3,
+ 0x04,0x00,0x00,0x0A,0x01,0x00,0x15,0xE3,0x00,0x00,0xE0,0x13,0x11,0x00,0x00,0x1A,
+ 0x02,0x40,0xA0,0xE3,0x00,0x00,0x00,0xEA,0x04,0x40,0xA0,0xE3,0x00,0x00,0x55,0xE3,
+ 0x0C,0x00,0x00,0xDA,0x00,0x00,0x5A,0xE3,0x40,0x02,0x8D,0xE8,0x0B,0x30,0xA0,0xE1,
+ 0x04,0x20,0xA0,0xE1,0x07,0x10,0xA0,0xE1,0x08,0x00,0xA0,0xE1,0x06,0x00,0x00,0x0A,
+ 0x1A,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x04,0x80,0x88,0x00,0x04,0x70,0x87,0x00,
+ 0x04,0x50,0x45,0x00,0xF0,0xFF,0xFF,0x0A,0xFC,0x9F,0xBD,0xE8,0x73,0xFF,0xFF,0xEB,
+ 0xF7,0xFF,0xFF,0xEA,0x14,0x07,0x00,0xEA,0xB1,0x00,0x00,0xEA,0xA4,0x2A,0x02,0x20,
+ 0xF0,0x41,0x2D,0xE9,0x00,0x50,0xA0,0xE3,0x64,0x45,0x9F,0xE5,0x03,0x60,0xB0,0xE1,
+ 0x00,0x80,0xA0,0xE1,0x01,0x00,0xA0,0xE3,0x01,0x70,0xA0,0xE1,0x08,0x10,0xA0,0xE3,
+ 0x14,0x30,0x84,0xE2,0x00,0x50,0x84,0xE5,0x10,0x50,0x84,0xE5,0x21,0x00,0x83,0xE8,
+ 0x1C,0x50,0x84,0xE5,0x24,0x10,0x84,0xE5,0x05,0x10,0xA0,0xE3,0x20,0x50,0x84,0xE5,
+ 0x2C,0x00,0x84,0xE5,0x28,0x50,0x84,0xE5,0x30,0x00,0x84,0xE5,0x02,0x00,0xA0,0xE1,
+ 0x46,0x10,0xC4,0xE5,0x00,0x10,0x84,0xE2,0x58,0x50,0x84,0xE5,0x5C,0x50,0x84,0xE5,
+ 0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,0x40,0x50,0x84,0xE5,
+ 0xDF,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x00,0x00,0x56,0xE3,
+ 0x50,0x10,0xD4,0xE5,0x00,0x10,0xC8,0xE5,0xB0,0x15,0xD4,0x11,0x21,0x14,0xA0,0x11,
+ 0x00,0x10,0xC7,0x15,0x00,0x50,0xC7,0x05,0xF0,0x81,0xBD,0xE8,0xFE,0x40,0x2D,0xE9,
+ 0x02,0x50,0xA0,0xE1,0x01,0x40,0xA0,0xE1,0x00,0x60,0xA0,0xE1,0x04,0x30,0xA0,0xE1,
+ 0x06,0x20,0xA0,0xE1,0x08,0x10,0x8D,0xE2,0x04,0x00,0x8D,0xE2,0x00,0x50,0x8D,0xE5,
+ 0xCE,0xFF,0xFF,0xEB,0x01,0x00,0x54,0xE3,0x04,0x10,0xDD,0x05,0x08,0x20,0xDD,0x05,
+ 0x02,0x10,0x81,0x01,0x03,0x00,0x00,0x0A,0x00,0x00,0x54,0xE3,0x04,0x10,0xDD,0x05,
+ 0x00,0x00,0xE0,0x13,0x01,0x00,0x00,0x1A,0x01,0x00,0x11,0xE3,0xEE,0xFF,0xFF,0x1A,
+ 0xFE,0x80,0xBD,0xE8,0x78,0x14,0x9F,0xE5,0x00,0x20,0xA0,0xE3,0x01,0x30,0xA0,0xE3,
+ 0x00,0x20,0x81,0xE5,0x14,0x30,0x81,0xE5,0x06,0x30,0xA0,0xE3,0x18,0x20,0x81,0xE5,
+ 0x1C,0x20,0x81,0xE5,0x20,0x20,0x81,0xE5,0x24,0x20,0x81,0xE5,0x28,0x20,0x81,0xE5,
+ 0x2C,0x20,0x81,0xE5,0x30,0x20,0x81,0xE5,0x46,0x30,0xC1,0xE5,0x34,0x20,0x81,0xE5,
+ 0x38,0x20,0x81,0xE5,0x3C,0x20,0x81,0xE5,0x40,0x20,0x81,0xE5,0xAC,0xFF,0xFF,0xEA,
+ 0xF0,0x41,0x2D,0xE9,0x80,0x00,0x10,0xE3,0x03,0x60,0xA0,0xE1,0x02,0x70,0xA0,0xE1,
+ 0x18,0x80,0x9D,0xE5,0x01,0x50,0xA0,0xE1,0x00,0x40,0xA0,0xE1,0x07,0x00,0x00,0x0A,
+ 0x80,0x40,0xC4,0xE3,0x06,0x20,0xA0,0xE1,0x08,0x30,0xA0,0xE1,0x07,0x10,0xA0,0xE1,
+ 0x04,0x00,0xA0,0xE1,0x7F,0x00,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,
+ 0x07,0x00,0xA0,0xE1,0xDA,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,
+ 0x00,0x10,0xA0,0xE3,0x01,0x20,0xA0,0xE3,0x0C,0x30,0xA0,0xE3,0xD0,0x03,0x9F,0xE5,
+ 0x1C,0xC0,0x80,0xE2,0x00,0x10,0x80,0xE5,0x0C,0x10,0x80,0xE5,0x14,0x20,0x80,0xE5,
+ 0x18,0x10,0x80,0xE5,0x0A,0x00,0x8C,0xE8,0x24,0x10,0x80,0xE5,0x28,0x10,0x80,0xE5,
+ 0x2C,0x10,0x80,0xE5,0x30,0x10,0x80,0xE5,0x46,0x20,0xC0,0xE5,0x4C,0x40,0xC0,0xE5,
+ 0x4D,0x50,0xC0,0xE5,0x4E,0x10,0xC0,0xE5,0x4F,0x10,0xC0,0xE5,0x34,0x10,0x80,0xE5,
+ 0x38,0x10,0x80,0xE5,0x3C,0x10,0x80,0xE5,0x40,0x10,0x80,0xE5,0x00,0x10,0x80,0xE2,
+ 0x07,0x00,0xA0,0xE1,0x7E,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,
+ 0x08,0x20,0xA0,0xE1,0x06,0x10,0xA0,0xE1,0x07,0x00,0xA0,0xE1,0xF0,0x41,0xBD,0xE8,
+ 0xA1,0xFF,0xFF,0xEA,0xF0,0x41,0x2D,0xE9,0x00,0x50,0xA0,0xE3,0x50,0x43,0x9F,0xE5,
+ 0x03,0x60,0xB0,0xE1,0x00,0x80,0xA0,0xE1,0x01,0x00,0xA0,0xE3,0x01,0x70,0xA0,0xE1,
+ 0x08,0x10,0xA0,0xE3,0x14,0x30,0x84,0xE2,0x00,0x50,0x84,0xE5,0x10,0x50,0x84,0xE5,
+ 0x21,0x00,0x83,0xE8,0x1C,0x50,0x84,0xE5,0x24,0x10,0x84,0xE5,0x35,0x10,0xA0,0xE3,
+ 0x20,0x50,0x84,0xE5,0x2C,0x00,0x84,0xE5,0x28,0x50,0x84,0xE5,0x30,0x00,0x84,0xE5,
+ 0x02,0x00,0xA0,0xE1,0x46,0x10,0xC4,0xE5,0x00,0x10,0x84,0xE2,0x58,0x50,0x84,0xE5,
+ 0x5C,0x50,0x84,0xE5,0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,
+ 0x40,0x50,0x84,0xE5,0x5A,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,
+ 0x00,0x00,0x56,0xE3,0x50,0x10,0xD4,0xE5,0x00,0x10,0xC8,0xE5,0xB0,0x15,0xD4,0x11,
+ 0x21,0x14,0xA0,0x11,0x00,0x10,0xC7,0x15,0x00,0x50,0xC7,0x05,0xF0,0x81,0xBD,0xE8,
+ 0x38,0x40,0x2D,0xE9,0x10,0x40,0x9D,0xE5,0x00,0x40,0x8D,0xE5,0x57,0x00,0x00,0xEB,
+ 0x38,0x80,0xBD,0xE8,0xF0,0x40,0x2D,0xE9,0x03,0x40,0xA0,0xE1,0x14,0xD0,0x4D,0xE2,
+ 0x00,0x50,0xA0,0xE1,0x02,0x60,0xA0,0xE1,0x01,0x70,0xA0,0xE1,0x00,0x30,0x8D,0xE5,
+ 0x02,0x30,0xA0,0xE1,0x01,0x20,0xA0,0xE1,0x0C,0x10,0x8D,0xE2,0x04,0x00,0x8D,0xE2,
+ 0x42,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x1C,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1,
+ 0x07,0x20,0xA0,0xE1,0x10,0x10,0x8D,0xE2,0x08,0x00,0x8D,0xE2,0x00,0x40,0x8D,0xE5,
+ 0xBF,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x14,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1,
+ 0x08,0x00,0xDD,0xE5,0x07,0x20,0xA0,0xE1,0x00,0x40,0x8D,0xE5,0x01,0x10,0xC0,0xE3,
+ 0x04,0x00,0xDD,0xE5,0x81,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x1A,
+ 0x01,0x00,0x55,0xE3,0x04,0x00,0xDD,0xE5,0x06,0x30,0xA0,0xE1,0x07,0x20,0xA0,0xE1,
+ 0x00,0x40,0x8D,0xE5,0x1C,0x00,0x80,0x13,0x1C,0x00,0xC0,0x03,0x04,0x00,0xCD,0xE5,
+ 0x08,0x00,0xDD,0xE5,0x01,0x10,0x80,0xE3,0x04,0x00,0xDD,0xE5,0x73,0xFF,0xFF,0xEB,
+ 0x14,0xD0,0x8D,0xE2,0xF0,0x80,0xBD,0xE8,0xF0,0x41,0x2D,0xE9,0x00,0x40,0xA0,0xE1,
+ 0x03,0x50,0xA0,0xE1,0x02,0x60,0xA0,0xE1,0x01,0x70,0xA0,0xE1,0x01,0x00,0xA0,0xE1,
+ 0x57,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x00,0x10,0xA0,0xE3,
+ 0x01,0x20,0xA0,0xE3,0x08,0x30,0xA0,0xE3,0xC4,0x01,0x9F,0xE5,0x1C,0x80,0x80,0xE2,
+ 0x00,0x10,0x80,0xE5,0x0C,0x10,0x80,0xE5,0x14,0x20,0x80,0xE5,0x18,0x10,0x80,0xE5,
+ 0x0A,0x00,0x88,0xE8,0x24,0x10,0x80,0xE5,0x28,0x10,0x80,0xE5,0x2C,0x10,0x80,0xE5,
+ 0x30,0x10,0x80,0xE5,0x46,0x20,0xC0,0xE5,0x4C,0x40,0xC0,0xE5,0x4D,0x10,0xC0,0xE5,
+ 0x4E,0x10,0xC0,0xE5,0x4F,0x10,0xC0,0xE5,0x34,0x10,0x80,0xE5,0x38,0x10,0x80,0xE5,
+ 0x3C,0x10,0x80,0xE5,0x40,0x10,0x80,0xE5,0x00,0x10,0x80,0xE2,0x07,0x00,0xA0,0xE1,
+ 0xFB,0xFE,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x05,0x20,0xA0,0xE1,
+ 0x06,0x10,0xA0,0xE1,0x07,0x00,0xA0,0xE1,0xF0,0x41,0xBD,0xE8,0x1E,0xFF,0xFF,0xEA,
+ 0xF0,0x40,0x2D,0xE9,0x03,0x40,0xA0,0xE1,0x1C,0xD0,0x4D,0xE2,0x02,0x50,0xA0,0xE1,
+ 0x01,0x60,0xA0,0xE1,0x00,0x70,0xA0,0xE1,0x00,0x20,0xA0,0xE1,0x00,0x30,0x8D,0xE5,
+ 0x01,0x30,0xA0,0xE1,0x0C,0x10,0x8D,0xE2,0x08,0x00,0x8D,0xE2,0xEB,0xFE,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x1F,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1,0x07,0x20,0xA0,0xE1,
+ 0x10,0x10,0x8D,0xE2,0x04,0x00,0x8D,0xE2,0x00,0x40,0x8D,0xE5,0x68,0xFF,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x17,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1,0x07,0x20,0xA0,0xE1,
+ 0x18,0x10,0x8D,0xE2,0x14,0x00,0x8D,0xE2,0x00,0x40,0x8D,0xE5,0x13,0x00,0x00,0xEB,
+ 0x00,0x00,0x50,0xE3,0x0F,0x00,0x00,0x1A,0x02,0x00,0x55,0xE3,0x04,0x00,0xDD,0x05,
+ 0x02,0x00,0xC0,0x03,0x04,0x00,0x00,0x0A,0x03,0x00,0x55,0xE3,0x04,0x00,0xDD,0x05,
+ 0x02,0x00,0x80,0x03,0x00,0x00,0xE0,0x13,0x06,0x00,0x00,0x1A,0x3F,0x10,0x00,0xE2,
+ 0x08,0x00,0xDD,0xE5,0x06,0x30,0xA0,0xE1,0x04,0x10,0xCD,0xE5,0x07,0x20,0xA0,0xE1,
+ 0x00,0x40,0x8D,0xE5,0x19,0xFF,0xFF,0xEB,0x1C,0xD0,0x8D,0xE2,0xF0,0x80,0xBD,0xE8,
+ 0xF0,0x41,0x2D,0xE9,0x00,0x50,0xA0,0xE3,0x84,0x40,0x9F,0xE5,0x03,0x80,0xA0,0xE1,
+ 0x00,0x70,0xA0,0xE1,0x01,0x00,0xA0,0xE3,0x01,0x60,0xA0,0xE1,0x08,0x10,0xA0,0xE3,
+ 0x14,0x30,0x84,0xE2,0x00,0x50,0x84,0xE5,0x10,0x50,0x84,0xE5,0x21,0x00,0x83,0xE8,
+ 0x24,0x30,0x84,0xE2,0x1C,0x50,0x84,0xE5,0x20,0x50,0x84,0xE5,0x22,0x00,0x83,0xE8,
+ 0x16,0x10,0xA0,0xE3,0x2C,0x00,0x84,0xE5,0x30,0x00,0x84,0xE5,0x02,0x00,0xA0,0xE1,
+ 0x46,0x10,0xC4,0xE5,0x00,0x10,0x84,0xE2,0x58,0x50,0x84,0xE5,0x5C,0x50,0x84,0xE5,
+ 0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,0x40,0x50,0x84,0xE5,
+ 0xA7,0xFE,0xFF,0xEB,0x50,0x10,0xD4,0xE5,0x00,0x00,0x58,0xE3,0x00,0x10,0xC7,0xE5,
+ 0xB0,0x15,0xD4,0x11,0x00,0x50,0xC6,0x05,0x21,0x14,0xA0,0x11,0x00,0x10,0xC6,0x15,
+ 0xF0,0x81,0xBD,0xE8,0xA4,0x2A,0x02,0x20,0x89,0x05,0x00,0xEA,0x9D,0x05,0x00,0xEA,
+ 0x73,0x05,0x00,0xEA,0xF8,0x40,0x2D,0xE9,0x02,0x40,0xA0,0xE1,0x18,0x20,0x8D,0xE2,
+ 0x03,0xC0,0xA0,0xE1,0x01,0x60,0xA0,0xE1,0x00,0x70,0xA0,0xE1,0x28,0x00,0x92,0xE8,
+ 0x0C,0x20,0xA0,0xE1,0x00,0x40,0x8D,0xE5,0x2E,0x04,0x00,0xEB,0x00,0x00,0x50,0xE3,
+ 0x0B,0x00,0x00,0x1A,0x00,0x00,0x54,0xE3,0x02,0x20,0xA0,0x03,0x03,0x00,0x00,0x0A,
+ 0x02,0x00,0x54,0xE3,0x03,0x20,0xA0,0x03,0x00,0x00,0xE0,0x13,0x04,0x00,0x00,0x1A,
+ 0x04,0x30,0xA0,0xE1,0x06,0x10,0xA0,0xE1,0x07,0x00,0xA0,0xE1,0x00,0x50,0x8D,0xE5,
+ 0x32,0xFF,0xFF,0xEB,0xF8,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,
+ 0x02,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x00,0x00,0xE0,0x83,0x70,0x80,0xBD,0x88,
+ 0x00,0x00,0x51,0xE3,0x00,0x10,0xA0,0x03,0x01,0x10,0xA0,0x13,0x0B,0x20,0xD4,0xE5,
+ 0xE9,0x03,0x00,0xEB,0x00,0x00,0x50,0xE3,0x70,0x80,0xBD,0x18,0x04,0x10,0xA0,0xE1,
+ 0x05,0x00,0xA0,0xE1,0x70,0x40,0xBD,0xE8,0x9D,0x04,0x00,0xEA,0x01,0x20,0xD1,0xE5,
+ 0x02,0x00,0x52,0xE3,0x0E,0x00,0xD1,0x95,0x02,0x00,0x50,0x93,0x12,0x00,0x00,0x8A,
+ 0x06,0x00,0xD1,0xE5,0x0F,0x00,0x50,0xE3,0x07,0x00,0xD1,0x95,0x02,0x00,0x50,0x93,
+ 0x0D,0x00,0x00,0x8A,0x08,0x00,0xD1,0xE5,0x07,0x00,0x50,0xE3,0x09,0x00,0xD1,0x95,
+ 0x01,0x00,0x50,0x93,0x08,0x00,0x00,0x8A,0x0A,0x00,0xD1,0xE5,0x02,0x00,0x50,0xE3,
+ 0x0B,0x00,0xD1,0x95,0x02,0x00,0x50,0x93,0x03,0x00,0x00,0x8A,0x0D,0x00,0xD1,0xE5,
+ 0x03,0x00,0x50,0xE3,0x00,0x00,0xA0,0x93,0x1E,0xFF,0x2F,0x91,0x00,0x00,0xE0,0xE3,
+ 0x1E,0xFF,0x2F,0xE1,0xF8,0x40,0x2D,0xE9,0x01,0x50,0xA0,0xE1,0x02,0x40,0xA0,0xE1,
+ 0x00,0x60,0xA0,0xE1,0x02,0x10,0xA0,0xE1,0xDF,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,
+ 0x1B,0x00,0x00,0x1A,0x05,0x10,0xA0,0xE1,0x0B,0x00,0xD4,0xE5,0x00,0x00,0x8D,0xE5,
+ 0x06,0x00,0xA0,0xE1,0x0D,0x30,0xD4,0xE5,0x0C,0x20,0xD4,0xE5,0xE5,0x03,0x00,0xEB,
+ 0x00,0x00,0x50,0xE3,0x12,0x00,0x00,0x1A,0x0B,0x30,0xD4,0xE5,0x00,0x00,0x53,0xE3,
+ 0x02,0x20,0xA0,0x03,0x03,0x00,0x00,0x0A,0x02,0x00,0x53,0xE3,0x03,0x20,0xA0,0x03,
+ 0x00,0x00,0xE0,0x13,0x0A,0x00,0x00,0x1A,0x05,0x10,0xA0,0xE1,0x0F,0x00,0xD4,0xE5,
+ 0x00,0x00,0x8D,0xE5,0x06,0x00,0xA0,0xE1,0xE8,0xFE,0xFF,0xEB,0x00,0x00,0x50,0xE3,
+ 0x03,0x00,0x00,0x1A,0x04,0x20,0xA0,0xE1,0x05,0x10,0xA0,0xE1,0x06,0x00,0xA0,0xE1,
+ 0xB0,0xFF,0xFF,0xEB,0xF8,0x80,0xBD,0xE8,0x52,0x04,0x00,0xEA,0x70,0x40,0x2D,0xE9,
+ 0x01,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x7F,0x06,0x00,0xEB,0x04,0x10,0xA0,0xE1,
+ 0x05,0x00,0xA0,0xE1,0x70,0x40,0xBD,0xE8,0xB7,0xFF,0xFF,0xEA,0xF7,0x4F,0x2D,0xE9,
+ 0x01,0x00,0x50,0xE3,0x01,0x40,0xA0,0xE1,0x00,0x00,0xE0,0x83,0x92,0x03,0x00,0x8A,
+ 0x00,0x00,0x50,0xE3,0xE5,0x00,0x00,0x0A,0x01,0x3A,0xA0,0xE3,0x3C,0x5E,0x9F,0xE5,
+ 0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x38,0xFC,0xFF,0xEB,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0x62,0x85,0xE1,
+ 0x06,0x00,0xA0,0xE1,0x32,0xFC,0xFF,0xEB,0x3D,0x7C,0x45,0xE2,0x01,0x3A,0xA0,0xE3,
+ 0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x2C,0xFC,0xFF,0xEB,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0x82,0x87,0xE0,
+ 0x08,0x00,0xA0,0xE1,0x26,0xFC,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x02,0x93,0x26,0xE0,0x09,0x00,0xA0,0xE1,0x20,0xFC,0xFF,0xEB,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0x1B,0xFC,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x82,0xA3,0x27,0xE0,0x0A,0x00,0xA0,0xE1,0x15,0xFC,0xFF,0xEB,0x01,0x10,0xA0,0xE3,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0xB4,0x8A,0xE0,0x0B,0x00,0xA0,0xE1,
+ 0x0F,0xFC,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x82,0x03,0x88,0xE0,0x0A,0xFC,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x05,0xFC,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,
+ 0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x00,0xFC,0xFF,0xEB,
+ 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,
+ 0xFB,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x06,0x00,0xA0,0xE1,0xF6,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xF1,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+ 0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xEC,0xFB,0xFF,0xEB,
+ 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+ 0xE7,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x06,0x00,0xA0,0xE1,0xE2,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0xDD,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+ 0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xD8,0xFB,0xFF,0xEB,
+ 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0xC3,0x01,0x8B,0xE0,
+ 0xD3,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x09,0x00,0xA0,0xE1,0xCE,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xC9,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+ 0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xC4,0xFB,0xFF,0xEB,
+ 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xBF,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0xBA,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xB5,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+ 0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xB0,0xFB,0xFF,0xEB,
+ 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xAB,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x0A,0x00,0xA0,0xE1,0xA6,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xA1,0xFB,0xFF,0xEB,0x0E,0x20,0xA0,0xE3,
+ 0x01,0x39,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x03,0x87,0xE0,0x9C,0xFB,0xFF,0xEB,
+ 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+ 0x97,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0x92,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x8D,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+ 0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x88,0xFB,0xFF,0xEB,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+ 0x83,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0x7E,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x79,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+ 0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x74,0xFB,0xFF,0xEB,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,
+ 0x6F,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x0B,0x00,0xA0,0xE1,0x6A,0xFB,0xFF,0xEB,0x0F,0x20,0xA0,0xE3,0x02,0x39,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x02,0x04,0x2A,0xE0,0x65,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+ 0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x60,0xFB,0xFF,0xEB,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0x5B,0xFB,0xFF,0xEB,0x02,0x00,0x54,0xE3,0x3B,0x02,0x00,0x0A,0xA9,0x02,0x00,0xEA,
+ 0xAC,0x5A,0x9F,0xE5,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0x52,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x82,0x63,0x85,0xE1,0x06,0x00,0xA0,0xE1,0x4C,0xFB,0xFF,0xEB,
+ 0x3D,0x7C,0x45,0xE2,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0x46,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x82,0x83,0x87,0xE0,0x08,0x00,0xA0,0xE1,0x40,0xFB,0xFF,0xEB,
+ 0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x93,0x86,0xE0,
+ 0x09,0x00,0xA0,0xE1,0x3A,0xFB,0xFF,0xEB,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x35,0xFB,0xFF,0xEB,0x01,0x10,0xA0,0xE3,
+ 0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0xA4,0x88,0xE1,0x0A,0x00,0xA0,0xE1,
+ 0x2F,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x82,0xB3,0x8A,0xE0,0x0B,0x00,0xA0,0xE1,0x29,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,
+ 0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x04,0x8B,0xE0,0x24,0xFB,0xFF,0xEB,
+ 0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+ 0x1F,0xFB,0xFF,0xEB,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0x1A,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x15,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,
+ 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x10,0xFB,0xFF,0xEB,
+ 0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+ 0x0B,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0x06,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x01,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,
+ 0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xFC,0xFA,0xFF,0xEB,
+ 0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,
+ 0xF7,0xFA,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x0B,0x00,0xA0,0xE1,0xF2,0xFA,0xFF,0xEB,0x03,0x20,0xA0,0xE3,0x08,0x30,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x82,0x04,0x88,0xE0,0xED,0xFA,0xFF,0xEB,0x08,0x30,0xA0,0xE3,
+ 0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xE8,0xFA,0xFF,0xEB,
+ 0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0xE3,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0xDE,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xD9,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,
+ 0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xD4,0xFA,0xFF,0xEB,
+ 0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0xCF,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x09,0x00,0xA0,0xE1,0xCA,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xC5,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,
+ 0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0xC0,0xFA,0xFF,0xEB,
+ 0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+ 0xBB,0xFA,0xFF,0xEB,0x04,0x20,0xA0,0xE3,0x10,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x02,0x04,0x8B,0xE0,0xB6,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xB1,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,
+ 0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xAC,0xFA,0xFF,0xEB,
+ 0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,
+ 0xA7,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x06,0x00,0xA0,0xE1,0xA2,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x9D,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,
+ 0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x98,0xFA,0xFF,0xEB,
+ 0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+ 0x93,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x06,0x00,0xA0,0xE1,0x8E,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x89,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,
+ 0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0x84,0xFA,0xFF,0xEB,
+ 0x05,0x20,0xA0,0xE3,0x20,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x02,0x04,0x8A,0xE0,
+ 0x7F,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x09,0x00,0xA0,0xE1,0x7A,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x75,0xFA,0xFF,0xEB,0x02,0x00,0x54,0xE3,
+ 0xC4,0x01,0x00,0x1A,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0x6E,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x69,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,
+ 0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x64,0xFA,0xFF,0xEB,
+ 0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0x5F,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x09,0x00,0xA0,0xE1,0x5A,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x55,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,
+ 0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x50,0xFA,0xFF,0xEB,
+ 0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+ 0x4B,0xFA,0xFF,0xEB,0x06,0x20,0xA0,0xE3,0x40,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x02,0x44,0x88,0xE0,0x04,0x00,0xA0,0xE1,0x45,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,
+ 0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x40,0xFA,0xFF,0xEB,
+ 0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0x3B,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0x36,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x31,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,
+ 0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x2C,0xFA,0xFF,0xEB,
+ 0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0x27,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x09,0x00,0xA0,0xE1,0x22,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x1D,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,
+ 0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x18,0xFA,0xFF,0xEB,
+ 0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+ 0x13,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x04,0x00,0xA0,0xE1,0x0E,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x09,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,
+ 0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x04,0xFA,0xFF,0xEB,
+ 0x08,0x00,0x9D,0xE5,0x01,0x00,0x50,0xE3,0x52,0x01,0x00,0x1A,0x1C,0x40,0x45,0xE2,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+ 0xFB,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x43,0x52,0x84,0xE1,0x05,0x00,0xA0,0xE1,0xF5,0xF9,0xFF,0xEB,0x3D,0x6C,0x44,0xE2,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xEF,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x43,0x72,0x86,0xE0,0x07,0x00,0xA0,0xE1,0xE9,0xF9,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,
+ 0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x02,0x83,0x25,0xE0,0x08,0x00,0xA0,0xE1,
+ 0xE3,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0xDE,0xF9,0xFF,0xEB,0x01,0x10,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,
+ 0x0C,0x20,0xA0,0xE3,0x01,0x94,0x87,0xE1,0x09,0x00,0xA0,0xE1,0xD8,0xF9,0xFF,0xEB,
+ 0x01,0x10,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0xA4,0x89,0xE0,
+ 0x0A,0x00,0xA0,0xE1,0xD2,0xF9,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x82,0xB3,0x87,0xE0,0x0B,0x00,0xA0,0xE1,0xCC,0xF9,0xFF,0xEB,
+ 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0xC7,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0xC2,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0xBD,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+ 0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xB8,0xF9,0xFF,0xEB,
+ 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xB3,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0xAE,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xA9,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+ 0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xA4,0xF9,0xFF,0xEB,
+ 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+ 0x9F,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x0A,0x00,0xA0,0xE1,0x9A,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0x95,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+ 0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x90,0xF9,0xFF,0xEB,
+ 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+ 0x8B,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x04,0x00,0xA0,0xE1,0x86,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x81,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+ 0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x7C,0xF9,0xFF,0xEB,
+ 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+ 0x77,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0x72,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x6D,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+ 0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x68,0xF9,0xFF,0xEB,
+ 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,
+ 0x63,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x0B,0x00,0xA0,0xE1,0x5E,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x59,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+ 0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x54,0xF9,0xFF,0xEB,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+ 0x4F,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0x4A,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x45,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+ 0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x40,0xF9,0xFF,0xEB,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+ 0x3B,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x05,0x00,0xA0,0xE1,0x36,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x31,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+ 0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x2C,0xF9,0xFF,0xEB,
+ 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+ 0x27,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0x22,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x6D,0x00,0x00,0xEA,0x01,0x3B,0xA0,0xE3,
+ 0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x18,0xF9,0xFF,0xEB,
+ 0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0x13,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0x0E,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x09,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,
+ 0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x04,0xF9,0xFF,0xEB,
+ 0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xFF,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x0A,0x00,0xA0,0xE1,0xFA,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xF5,0xF8,0xFF,0xEB,0x24,0x41,0x9F,0xE5,
+ 0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+ 0xEF,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x09,0x00,0xA0,0xE1,0xEA,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xE5,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,
+ 0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xE0,0xF8,0xFF,0xEB,
+ 0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xDB,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0xD6,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xD1,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,
+ 0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xCC,0xF8,0xFF,0xEB,
+ 0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+ 0xC7,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x0A,0x00,0xA0,0xE1,0xC2,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xBD,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,
+ 0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0xB8,0xF8,0xFF,0xEB,
+ 0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+ 0xB3,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x08,0x00,0xA0,0xE1,0xAE,0xF8,0xFF,0xEB,0x00,0x00,0xA0,0xE3,0xFE,0x8F,0xBD,0xE8,
+ 0x20,0x70,0xFE,0xFC,0x24,0x70,0xFE,0xFC,0x20,0x3A,0xFE,0xFC,0xF0,0x41,0x2D,0xE9,
+ 0x01,0x00,0x50,0xE3,0x02,0x70,0xA0,0xE1,0x01,0x50,0xA0,0xE1,0x00,0x40,0xA0,0xE1,
+ 0x15,0x00,0x00,0x8A,0x54,0x6B,0x9F,0xE5,0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x04,0x01,0x96,0xE7,0x48,0x00,0x80,0xE2,0xB3,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,
+ 0x0D,0x00,0x00,0x1A,0x04,0x01,0x96,0xE7,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0xAD,0xF8,0xFF,0xEB,0x05,0x00,0x50,0xE1,0x14,0x00,0x00,0x0A,0x01,0x00,0x55,0xE3,
+ 0x07,0x00,0x00,0x1A,0x05,0x20,0xA0,0xE1,0x07,0x10,0xA0,0xE1,0x04,0x00,0xA0,0xE1,
+ 0x49,0xFC,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0xAA,0x00,0x00,0xE0,0xE3,
+ 0xF0,0x81,0xBD,0xE8,0x04,0x01,0x96,0xE7,0x03,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,
+ 0x05,0x10,0xA0,0xE1,0x8D,0xF8,0xFF,0xEB,0x04,0x01,0x96,0xE7,0x02,0x3C,0xA0,0xE3,
+ 0x09,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,0x87,0xF8,0xFF,0xEB,
+ 0x00,0x00,0xA0,0xE3,0xF0,0x81,0xBD,0xE8,0xF0,0x47,0x2D,0xE9,0x01,0x00,0x50,0xE3,
+ 0x03,0x70,0xA0,0xE1,0x02,0x80,0xA0,0xE1,0x20,0x60,0x9D,0xE5,0x01,0x90,0xA0,0xE1,
+ 0x00,0x40,0xA0,0xE1,0x71,0x00,0x00,0x8A,0x01,0x20,0xA0,0xE1,0x06,0x10,0xA0,0xE1,
+ 0x2D,0xFC,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x6C,0x00,0x00,0xBA,0x01,0x20,0xA0,0xE3,
+ 0x88,0x5A,0x9F,0xE5,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x48,0x00,0x80,0xE2,
+ 0x81,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x64,0x00,0x00,0x1A,0x04,0x01,0x95,0xE7,
+ 0x03,0x35,0xA0,0xE3,0x16,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x6B,0xF8,0xFF,0xEB,
+ 0x04,0x01,0x95,0xE7,0x03,0x36,0xA0,0xE3,0x14,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,
+ 0x66,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x37,0xA0,0xE3,0x12,0x20,0xA0,0xE3,
+ 0x03,0x10,0xA0,0xE3,0x61,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x38,0xA0,0xE3,
+ 0x10,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x5C,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x03,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x57,0xF8,0xFF,0xEB,
+ 0x04,0x01,0x95,0xE7,0x03,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,
+ 0x52,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+ 0x03,0x10,0xA0,0xE3,0x4D,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x34,0xA0,0xE3,
+ 0x18,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x48,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0xF8,0xFF,0xEB,
+ 0x04,0x01,0x95,0xE7,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x3E,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x39,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x08,0x30,0xA0,0xE3,
+ 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x34,0xF8,0xFF,0xEB,0x06,0x20,0xA0,0xE1,
+ 0x09,0x10,0xA0,0xE1,0x04,0x00,0xA0,0xE1,0x7F,0xFF,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x07,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0x80,0xE2,
+ 0x2A,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x07,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x04,0x00,0x80,0xE2,0x24,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x00,0x20,0xA0,0xE3,0x07,0x30,0xA0,0xE3,0x02,0x10,0xA0,0xE1,0x04,0x00,0x80,0xE2,
+ 0x1E,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0xFF,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+ 0x08,0x10,0xA0,0xE1,0x08,0x00,0x80,0xE2,0x18,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x03,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,0x07,0x10,0xA0,0xE1,0x08,0x00,0x80,0xE2,
+ 0x12,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x48,0x00,0x80,0xE2,0x1C,0xF8,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,
+ 0x00,0x00,0xE0,0xE3,0xF0,0x87,0xBD,0xE8,0x04,0x11,0x95,0xE7,0x08,0x05,0x0A,0xE3,
+ 0x50,0x00,0x81,0xE5,0x04,0x11,0x95,0xE7,0xC4,0x08,0x9F,0xE5,0x68,0x00,0x81,0xE5,
+ 0x00,0x00,0xA0,0xE3,0xF0,0x87,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,
+ 0xA8,0x58,0x9F,0xE5,0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x48,0x00,0x80,0xE2,0x08,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,0xF8,0xFF,0xFF,0x1A,
+ 0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,0x01,0x60,0xA0,0xE1,
+ 0x00,0x40,0xA0,0xE1,0x07,0x00,0x00,0x8A,0x01,0x20,0xA0,0xE3,0x6C,0x58,0x9F,0xE5,
+ 0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x48,0x00,0x80,0xE2,0xFA,0xF7,0xFF,0xEB,
+ 0x01,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,0x00,0x00,0xE0,0xE3,0x70,0x80,0xBD,0xE8,
+ 0x04,0x01,0x95,0xE7,0x02,0x31,0xA0,0xE3,0x1F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0xE2,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x0F,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,0xDC,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x01,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,
+ 0xD6,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,
+ 0x03,0x10,0xA0,0xE1,0x0C,0x00,0x80,0xE2,0xD0,0xF7,0xFF,0xEB,0x00,0x10,0xD6,0xE5,
+ 0xFF,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x10,0x20,0xA0,0xE3,0x10,0x00,0x80,0xE2,
+ 0xCA,0xF7,0xFF,0xEB,0x01,0x10,0xD6,0xE5,0x03,0x31,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x1E,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xC4,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+ 0xBE,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0xFF,0x30,0xA0,0xE3,
+ 0x02,0x10,0xA0,0xE1,0x10,0x00,0x80,0xE2,0xB8,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x03,0x32,0xA0,0xE3,0x1C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+ 0xB2,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xAC,0xF7,0xFF,0xEB,0x0E,0x10,0xD6,0xE5,
+ 0x03,0x34,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x18,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+ 0xA6,0xF7,0xFF,0xEB,0x0F,0x10,0xD6,0xE5,0x0F,0x3C,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x08,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xA0,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0xFF,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x14,0x00,0x80,0xE2,
+ 0x9A,0xF7,0xFF,0xEB,0x02,0x10,0xD6,0xE5,0xFF,0x34,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x18,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,0x94,0xF7,0xFF,0xEB,0x03,0x10,0xD6,0xE5,
+ 0xFF,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x10,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,
+ 0x8E,0xF7,0xFF,0xEB,0x04,0x10,0xD6,0xE5,0xFF,0x3C,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x08,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,0x88,0xF7,0xFF,0xEB,0x05,0x10,0xD6,0xE5,
+ 0xFF,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,
+ 0x82,0xF7,0xFF,0xEB,0x07,0x10,0xD6,0xE5,0x03,0x36,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x14,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0x7C,0xF7,0xFF,0xEB,0x06,0x10,0xD6,0xE5,
+ 0xF0,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x04,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+ 0x76,0xF7,0xFF,0xEB,0x0B,0x10,0xD6,0xE5,0x03,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x10,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0x70,0xF7,0xFF,0xEB,0x09,0x10,0xD6,0xE5,
+ 0x02,0x39,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x0F,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+ 0x6A,0xF7,0xFF,0xEB,0x0A,0x10,0xD6,0xE5,0x03,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x10,0x20,0xA0,0xE3,0x58,0x00,0x80,0xE2,0x64,0xF7,0xFF,0xEB,0x08,0x10,0xD6,0xE5,
+ 0x07,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x58,0x00,0x80,0xE2,
+ 0x5E,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x5C,0x00,0x80,0xE2,0x58,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+ 0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x5C,0x00,0x80,0xE2,
+ 0x52,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x01,0x30,0xA0,0xE3,
+ 0x02,0x10,0xA0,0xE1,0x5C,0x00,0x80,0xE2,0x4C,0xF7,0xFF,0xEB,0x00,0x00,0xA0,0xE3,
+ 0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,0x00,0x40,0xA0,0xE1,
+ 0x00,0x00,0xE0,0x83,0x70,0x80,0xBD,0x88,0x01,0x34,0xA0,0xE3,0x18,0x20,0xA0,0xE3,
+ 0x01,0x10,0xA0,0xE3,0xB4,0x55,0x9F,0xE5,0x04,0x01,0x95,0xE7,0x0C,0x00,0x80,0xE2,
+ 0x3E,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+ 0x48,0x00,0x80,0xE2,0x48,0xF7,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF8,0xFF,0xFF,0x1A,
+ 0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,0x7C,0x55,0x9F,0xE5,
+ 0x02,0x21,0xA0,0xE3,0x1F,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x3E,0xF7,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x09,0x00,0x00,0x0A,0x04,0x00,0xA0,0xE1,0xE0,0xFF,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x00,0x00,0xE0,0xB3,0x70,0x80,0xBD,0xB8,0x02,0x31,0xA0,0xE3,
+ 0x1F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x23,0xF7,0xFF,0xEB,
+ 0x00,0x00,0xA0,0xE3,0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,
+ 0x28,0x55,0x9F,0xE5,0x02,0x21,0xA0,0xE3,0x1F,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x29,0xF7,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x09,0x00,0x00,0x0A,0x04,0x00,0xA0,0xE1,
+ 0xCB,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x00,0x00,0xE0,0xB3,0x70,0x80,0xBD,0xB8,
+ 0x02,0x31,0xA0,0xE3,0x1F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+ 0x0E,0xF7,0xFF,0xEB,0x00,0x00,0xA0,0xE3,0x70,0x80,0xBD,0xE8,0xF0,0x41,0x2D,0xE9,
+ 0x01,0x00,0x50,0xE3,0x01,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x19,0x00,0x00,0x8A,
+ 0x02,0x21,0xA0,0xE3,0xC4,0x64,0x9F,0xE5,0x1F,0x10,0xA0,0xE3,0x05,0x01,0x96,0xE7,
+ 0x11,0xF7,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,
+ 0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x48,0x00,0x80,0xE2,0x0A,0xF7,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x1A,0x05,0x01,0x96,0xE7,0x02,0x31,0xA0,0xE3,
+ 0x1F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0xF4,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+ 0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x48,0x00,0x80,0xE2,0xFE,0xF6,0xFF,0xEB,
+ 0x01,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,0x00,0x00,0xE0,0xE3,0xF0,0x81,0xBD,0xE8,
+ 0x05,0x01,0x96,0xE7,0x01,0x39,0xA0,0xE3,0x14,0x10,0x94,0xE5,0x0E,0x20,0xA0,0xE3,
+ 0x30,0x00,0x80,0xE2,0xE5,0xF6,0xFF,0xEB,0x14,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,
+ 0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,0x46,0x10,0xD4,0xE5,0xFF,0x38,0xA0,0xE3,
+ 0x24,0x00,0x80,0xE2,0x10,0x20,0xA0,0xE3,0xDC,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+ 0x03,0x31,0xA0,0xE3,0x00,0x10,0x94,0xE5,0x1E,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,
+ 0xD6,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3A,0xA0,0xE3,0x18,0x10,0x94,0xE5,
+ 0x0C,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xD0,0xF6,0xFF,0xEB,0x18,0x00,0x94,0xE5,
+ 0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,0x47,0x10,0xD4,0xE5,
+ 0xFF,0x30,0xA0,0xE3,0x24,0x00,0x80,0xE2,0x00,0x20,0xA0,0xE3,0xC7,0xF6,0xFF,0xEB,
+ 0x05,0x01,0x96,0xE7,0x03,0x32,0xA0,0xE3,0x04,0x10,0x94,0xE5,0x1C,0x20,0xA0,0xE3,
+ 0x30,0x00,0x80,0xE2,0xC1,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x0F,0x3C,0xA0,0xE3,
+ 0x1C,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xBB,0xF6,0xFF,0xEB,
+ 0x1C,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,
+ 0x48,0x10,0x94,0xE5,0x00,0x30,0xE0,0xE3,0x00,0x20,0xA0,0xE3,0x28,0x00,0x80,0xE2,
+ 0xB2,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x03,0x34,0xA0,0xE3,0x08,0x10,0x94,0xE5,
+ 0x18,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xAC,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+ 0xF0,0x30,0xA0,0xE3,0x20,0x10,0x94,0xE5,0x04,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,
+ 0xA6,0xF6,0xFF,0xEB,0x20,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x1D,0x00,0x00,0x0A,
+ 0x05,0x01,0x96,0xE7,0x4C,0x10,0xD4,0xE5,0xFF,0x34,0xA0,0xE3,0x2C,0x00,0x80,0xE2,
+ 0x18,0x20,0xA0,0xE3,0x9D,0xF6,0xFF,0xEB,0x4D,0x10,0xD4,0xE5,0xFF,0x38,0xA0,0xE3,
+ 0x05,0x01,0x96,0xE7,0x10,0x20,0xA0,0xE3,0x2C,0x00,0x80,0xE2,0x97,0xF6,0xFF,0xEB,
+ 0x4E,0x10,0xD4,0xE5,0xFF,0x3C,0xA0,0xE3,0x05,0x01,0x96,0xE7,0x08,0x20,0xA0,0xE3,
+ 0x2C,0x00,0x80,0xE2,0x91,0xF6,0xFF,0xEB,0x4F,0x10,0xD4,0xE5,0xFF,0x30,0xA0,0xE3,
+ 0x05,0x01,0x96,0xE7,0x00,0x20,0xA0,0xE3,0x2C,0x00,0x80,0xE2,0x8B,0xF6,0xFF,0xEB,
+ 0x05,0x01,0x96,0xE7,0x03,0x36,0xA0,0xE3,0x0C,0x10,0x94,0xE5,0x14,0x20,0xA0,0xE3,
+ 0x30,0x00,0x80,0xE2,0x85,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x02,0x39,0xA0,0xE3,
+ 0x34,0x10,0x94,0xE5,0x0F,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0x7F,0xF6,0xFF,0xEB,
+ 0x34,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,
+ 0x44,0x10,0xD4,0xE5,0x03,0x38,0xA0,0xE3,0x60,0x00,0x80,0xE2,0x10,0x20,0xA0,0xE3,
+ 0x76,0xF6,0xFF,0xEB,0x45,0x10,0xD4,0xE5,0x07,0x30,0xA0,0xE3,0x05,0x01,0x96,0xE7,
+ 0x00,0x20,0xA0,0xE3,0x60,0x00,0x80,0xE2,0x70,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+ 0x0F,0x30,0xA0,0xE3,0x24,0x10,0x94,0xE5,0x00,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,
+ 0x6A,0xF6,0xFF,0xEB,0x24,0x00,0x94,0xE5,0x58,0x72,0x9F,0xE5,0x00,0x00,0x50,0xE3,
+ 0x2C,0x00,0x00,0x0A,0x08,0x00,0x50,0xE3,0x04,0x00,0x00,0x0A,0x0C,0x00,0x50,0xE3,
+ 0x0C,0x00,0x00,0x0A,0x0F,0x00,0x50,0xE3,0x14,0x00,0x00,0x0A,0x1F,0x00,0x00,0xEA,
+ 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x6A,0xF6,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x58,0x00,0xD4,0x05,0x05,0x11,0x96,0x07,0x40,0x00,0xC1,0x05,
+ 0x06,0x00,0x00,0x1A,0x15,0x00,0x00,0xEA,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0x60,0xF6,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x53,0x00,0x00,0x1A,
+ 0x05,0x11,0x96,0xE7,0xB8,0x05,0xD4,0xE1,0xB0,0x04,0xC1,0xE1,0x0B,0x00,0x00,0xEA,
+ 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x56,0xF6,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x49,0x00,0x00,0x0A,0x05,0x11,0x96,0xE7,0x58,0x00,0x94,0xE5,
+ 0x40,0x00,0x81,0xE5,0x05,0x01,0x96,0xE7,0x5C,0x10,0x94,0xE5,0x44,0x10,0x80,0xE5,
+ 0x03,0x38,0xA0,0xE3,0x05,0x01,0x96,0xE7,0x10,0x20,0xA0,0xE3,0x10,0x10,0x94,0xE5,
+ 0x30,0x00,0x80,0xE2,0x39,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3C,0xA0,0xE3,
+ 0x28,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x20,0x00,0x80,0xE2,0x33,0xF6,0xFF,0xEB,
+ 0x10,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x24,0x00,0x94,0x15,0x00,0x00,0x50,0x13,
+ 0x04,0x00,0x00,0x0A,0x2C,0x00,0x94,0xE5,0x01,0x00,0x50,0xE3,0x30,0x00,0x94,0x05,
+ 0x01,0x00,0x50,0x03,0x3B,0xFF,0xFF,0x0A,0x05,0x01,0x96,0xE7,0x2C,0x10,0x94,0xE5,
+ 0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x20,0x00,0x80,0xE2,0x23,0xF6,0xFF,0xEB,
+ 0x05,0x01,0x96,0xE7,0x02,0x30,0xA0,0xE3,0x30,0x10,0x94,0xE5,0x01,0x20,0xA0,0xE3,
+ 0x20,0x00,0x80,0xE2,0x1D,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3C,0xA0,0xE3,
+ 0x38,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x64,0x00,0x80,0xE2,0x17,0xF6,0xFF,0xEB,
+ 0x05,0x01,0x96,0xE7,0x10,0x30,0xA0,0xE3,0x3C,0x10,0x94,0xE5,0x04,0x20,0xA0,0xE3,
+ 0x64,0x00,0x80,0xE2,0x11,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x30,0xA0,0xE3,
+ 0x40,0x10,0x94,0xE5,0x00,0x20,0xA0,0xE3,0x64,0x00,0x80,0xE2,0x0B,0xF6,0xFF,0xEB,
+ 0x05,0x01,0x96,0xE7,0x01,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE1,
+ 0x20,0x00,0x80,0xE2,0x05,0xF6,0xFF,0xEB,0x05,0x00,0xA0,0xE1,0xAD,0xF9,0xFF,0xEB,
+ 0x24,0x00,0x94,0xE5,0x08,0x00,0x50,0xE3,0x08,0x00,0x00,0x0A,0x0C,0x00,0x50,0xE3,
+ 0x11,0x00,0x00,0x0A,0x0F,0x00,0x50,0xE3,0x16,0x00,0x00,0x0A,0x21,0x00,0x00,0xEA,
+ 0x05,0x11,0x96,0xE7,0x58,0x00,0x94,0xE5,0x40,0x00,0x81,0xE5,0xB7,0xFF,0xFF,0xEA,
+ 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x02,0xF6,0xFF,0xEB,
+ 0x00,0x00,0x50,0xE3,0x05,0x01,0x96,0x07,0x38,0x00,0xD0,0x05,0x19,0x00,0x00,0x0A,
+ 0x05,0x01,0x96,0xE7,0xB8,0x03,0xD0,0xE1,0x16,0x00,0x00,0xEA,0x03,0x20,0xA0,0xE3,
+ 0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xF7,0xF5,0xFF,0xEB,0x00,0x00,0x50,0xE3,
+ 0x0E,0x00,0x00,0x1A,0xF5,0xFF,0xFF,0xEA,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+ 0x07,0x00,0xA0,0xE1,0xF0,0xF5,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x07,0x00,0x00,0x0A,
+ 0x05,0x01,0x96,0xE7,0x38,0x00,0x90,0xE5,0x50,0x00,0x84,0xE5,0x05,0x01,0x96,0xE7,
+ 0x3C,0x00,0x90,0xE5,0x54,0x00,0x84,0xE5,0x00,0x00,0xA0,0xE3,0xF0,0x81,0xBD,0xE8,
+ 0x05,0x01,0x96,0xE7,0x38,0x00,0x90,0xE5,0x50,0x00,0x84,0xE5,0xF9,0xFF,0xFF,0xEA,
+ 0x8C,0x2A,0x02,0x20,0x63,0x63,0x00,0xA5,0x00,0xA0,0xEF,0x3F,0xF0,0x40,0x2D,0xE9,
+ 0xEB,0xC0,0xA0,0xE3,0x00,0xC0,0xC1,0xE5,0x08,0x70,0xA0,0xE3,0x06,0x70,0xC1,0xE5,
+ 0x03,0x60,0xA0,0xE3,0x08,0x60,0xC1,0xE5,0x55,0x50,0xA0,0xE3,0x02,0x50,0xC1,0xE5,
+ 0x01,0x40,0xA0,0xE3,0x09,0x40,0xC1,0xE5,0x02,0x30,0xA0,0xE3,0x0E,0x30,0xC1,0xE5,
+ 0x00,0x20,0xA0,0xE3,0x07,0x30,0xC1,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x30,0xC1,0xE5,
+ 0x07,0x00,0xA0,0xE3,0x01,0x20,0xC1,0xE5,0x03,0x20,0xC1,0xE5,0x04,0x20,0xC1,0xE5,
+ 0x05,0x20,0xC1,0xE5,0x0A,0x20,0xC1,0xE5,0x0C,0x40,0xC1,0x05,0x0C,0x30,0xC1,0x15,
+ 0x0D,0x20,0xC1,0xE5,0x0F,0x00,0xC1,0xE5,0xF0,0x80,0xBD,0xE8,0x00,0xA0,0xEF,0x3F,
+ 0x00,0xB0,0xEF,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+ 0x5C,0x00,0x9F,0xE5,0x01,0x10,0xA0,0xE3,0x00,0x10,0x80,0xE5,0x00,0x00,0x90,0xE5,
+ 0x50,0x00,0x9F,0xE5,0x35,0x10,0x01,0xE3,0xB0,0x10,0xC0,0xE1,0x00,0x00,0x90,0xE5,
+ 0x44,0x00,0x9F,0xE5,0x01,0x10,0xA0,0xE3,0xB0,0x10,0xC0,0xE1,0x00,0x00,0x90,0xE5,
+ 0x10,0x0F,0x11,0xEE,0x02,0x0A,0xC0,0xE3,0x01,0x0A,0xC0,0xE3,0x04,0x00,0xC0,0xE3,
+ 0x01,0x00,0xC0,0xE3,0x10,0x0F,0x01,0xEE,0x26,0x00,0x00,0xEB,0x1C,0xD0,0x9F,0xE5,
+ 0x14,0x00,0x00,0xEB,0x0D,0x00,0x00,0xEB,0x0E,0x00,0x00,0xEB,0x0F,0x00,0x00,0xEB,
+ 0xFE,0xFF,0xFF,0xEA,0x80,0xFF,0xFF,0x3F,0x10,0x00,0xFE,0xFC,0x14,0x00,0xFE,0xFC,
+ 0x00,0x00,0x03,0x20,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,
+ 0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,
+ 0x04,0xF0,0x1F,0xE5,0x40,0x00,0x02,0x20,0x04,0xF0,0x1F,0xE5,0x00,0x00,0x02,0x20,
+ 0x04,0xF0,0x1F,0xE5,0x04,0x02,0x02,0x20,0x2C,0x30,0x9F,0xE5,0x00,0x20,0xA0,0xE3,
+ 0x28,0x10,0x9F,0xE5,0x28,0x00,0x9F,0xE5,0x10,0x40,0x2D,0xE9,0x23,0x31,0xA0,0xE1,
+ 0x02,0x00,0x00,0xEA,0x04,0x40,0x91,0xE4,0x01,0x20,0x82,0xE2,0x04,0x40,0x80,0xE4,
+ 0x03,0x00,0x52,0xE1,0xFA,0xFF,0xFF,0xBA,0x10,0x80,0xBD,0xE8,0xAF,0x01,0x00,0x00,
+ 0x00,0x02,0x00,0x18,0x00,0x00,0x02,0x20,0x04,0x00,0x9F,0xE5,0x10,0x0F,0x0C,0xEE,
+ 0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x00,0x18,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+};
+#if defined (__CC_ARM)
+#pragma arm section
+#endif
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mmu_Renesas_RZ_A1.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,244 @@
+/**************************************************************************//**
+ * @file mmu_Renesas_RZ_A1.c
+ * @brief MMU Startup File for
+ * mmu_Renesas_RZ_A1 Device Series
+ * @version V1.01
+ * @date 2 Aug 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
+#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
+#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
+#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings.
+//CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors place all memory in domain 0
+//There are no restrictions by privilege level (PL0 can access all memory)
+
+#include <stdint.h>
+#include "MBRZA1H.h"
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RO_DATA$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+#if !defined ( __ICCARM__ )
+extern uint32_t Image$$TTB$$ZI$$Base;
+#endif
+
+#if defined( __CC_ARM )
+#elif defined( __ICCARM__ )
+#else
+extern uint32_t Image$$RW_DATA_NC$$Base;
+extern uint32_t Image$$ZI_DATA_NC$$Base;
+#endif
+
+extern uint32_t Image$$VECTORS$$Limit;
+extern uint32_t Image$$RO_DATA$$Limit;
+extern uint32_t Image$$RW_DATA$$Limit;
+extern uint32_t Image$$ZI_DATA$$Limit;
+#if defined( __CC_ARM )
+#else
+extern uint32_t Image$$RW_DATA_NC$$Limit;
+extern uint32_t Image$$ZI_DATA_NC$$Limit;
+#endif
+
+#if defined( __ICCARM__ )
+#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
+#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
+#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
+#define ZI_DATA_SIZE (((uint32_t)Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)Image$$ZI_DATA$$Base >> 20) + 1)
+#else
+#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
+#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
+#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
+#define ZI_DATA_SIZE (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1)
+#endif
+
+#if defined( __CC_ARM )
+#else
+#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
+#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
+#endif
+
+static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k = 0x0; //generic
+static uint32_t Page_L1_64k = 0x0; //generic
+static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+#if defined ( __ICCARM__ )
+__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
+uint32_t Image$$VECTORS$$Base;
+uint32_t Image$$RO_DATA$$Base;
+uint32_t Image$$RW_DATA$$Base;
+uint32_t Image$$ZI_DATA$$Base;
+
+uint32_t Image$$VECTORS$$Limit;
+uint32_t Image$$RO_DATA$$Limit;
+uint32_t Image$$RW_DATA$$Limit;
+uint32_t Image$$ZI_DATA$$Limit;
+#endif
+
+void create_translation_table(void)
+{
+ mmu_region_attributes_Type region;
+#if defined ( __ICCARM__ )
+#pragma section=".intvec"
+#pragma section=".rodata"
+#pragma section=".rwdata"
+#pragma section=".bss"
+
+ Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
+ Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
+ Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
+ Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
+ Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata");
+ Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
+ Image$$ZI_DATA$$Base = (uint32_t) __section_begin(".bss");
+ Image$$ZI_DATA$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
+#endif
+ /*
+ * Generate descriptors. Refer to MBRZA1H.h to get information about attributes
+ *
+ */
+ //Create descriptors for Vectors, RO, RW, ZI sections
+ section_normal(Sect_Normal, region);
+ section_normal_cod(Sect_Normal_Cod, region);
+ section_normal_ro(Sect_Normal_RO, region);
+ section_normal_rw(Sect_Normal_RW, region);
+ //Create descriptors for peripherals
+ section_device_ro(Sect_Device_RO, region);
+ section_device_rw(Sect_Device_RW, region);
+ section_normal_nc(Sect_Normal_NC, region);
+ //Create descriptors for 64k pages
+ page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+ //Create descriptors for 4k pages
+ page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+ /*
+ * Define MMU flat-map regions and attributes
+ *
+ */
+
+ //Create 4GB of faulting entries
+ __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+ // R7S72100 memory map.
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0 , 64, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1 , 64, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0 , 64, Sect_Normal_RO);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1 , 64, Sect_Normal_RO);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE , 1, Sect_Device_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW);
+
+#if defined( __ICCARM__ )
+ //Define Image
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_Cod);
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
+#else
+ //Define Image
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_Cod);
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
+#endif
+
+#if defined( __CC_ARM )
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC);
+#elif defined ( __ICCARM__ )
+ __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC);
+
+#else
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
+ __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
+#endif
+
+ /* Set location of level 1 page table
+ ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+ ; 13:7 - 0x0
+ ; 6 - IRGN[0] 0x0 (Inner WB WA)
+ ; 5 - NOS 0x0 (Non-shared)
+ ; 4:3 - RGN 0x1 (Outer WB WA)
+ ; 2 - IMP 0x0 (Implementation Defined)
+ ; 1 - S 0x0 (Non-shared)
+ ; 0 - IRGN[1] 0x1 (Inner WB WA) */
+ __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+
+ /* Set up domain access control register
+ ; We set domain 0 to Client and all other domains to No Access.
+ ; All translation table entries specify domain 0 */
+ __set_DACR(1);
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,230 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file nvic_wrapper.c
+* $Rev: $
+* $Date:: $
+* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
+******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "MBRZA1H.h"
+#include "wdt_iodefine.h"
+#include "nvic_wrapper.h"
+#include "gic.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define PRIO_BITS (7) /* Set binary point to 0 in gic.c */
+#define WDT_WTCNT_WRITE (0x5A00)
+#define WDT_WTCSR_WRITE (0xA500)
+#define WDT_WRCSR_WOVF_WRITE (0xA500)
+#define WDT_WRCSR_RSTE_WRITE (0x5A00)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+
+/* ########################## NVIC functions #################################### */
+void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ GIC_SetBinaryPoint(PriorityGroup);
+}
+
+
+uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return GIC_GetBinaryPoint(0);
+}
+
+
+void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ GIC_EnableIRQ(IRQn);
+}
+
+
+void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ GIC_DisableIRQ(IRQn);
+}
+
+
+uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ uint32_t pending;
+
+ pending = GIC_GetIRQStatus(IRQn);
+ pending = (pending & 0x00000001);
+
+ return pending;
+}
+
+
+void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ GIC_SetPendingIRQ(IRQn);
+}
+
+
+void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ GIC_ClearPendingIRQ(IRQn);
+}
+
+
+uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ uint32_t active;
+
+ active = GIC_GetIRQStatus(IRQn);
+ active = ((active >> 1) & 0x00000001);
+
+ return active;
+}
+
+
+void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ GIC_SetPriority(IRQn, (priority << 3));
+}
+
+
+uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+ uint32_t priority_field;
+
+ priority_field = GIC_GetPriority(IRQn);
+ priority_field = (priority_field >> 3);
+ return priority_field;
+}
+
+
+uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+void NVIC_SystemReset(void)
+{
+ uint16_t reg;
+ uint8_t dummy_read;
+ /* Use Watch Dog Timer to system reset */
+
+ /* Set WT/IT bit of WTCSR to 1 = Watch Dog */
+ /* CLK = 000, 1xP0phi(=33.3333MHz) = 7.7us */
+ reg = (WDT_WTCSR_WRITE | 0x0058);
+ WDTWTCSR = reg;
+
+ /* Clear Count reg */
+ reg = (WDT_WTCNT_WRITE | 0x0000);
+ WDTWTCNT = reg;
+
+ /* Clear WOVF flag */
+ dummy_read = WDTWRCSR;
+ reg = (WDT_WRCSR_WOVF_WRITE | (dummy_read & 0x0000));
+ WDTWRCSR = reg;
+ /* Enable Internal Reset */
+ reg = (WDT_WRCSR_RSTE_WRITE | 0x005F);
+ WDTWRCSR = reg;
+
+ /* Watch Dog start */
+ reg = (WDT_WTCSR_WRITE | 0x0078);
+ WDTWTCSR = reg;
+
+ while(1); /* wait Internal Reset */
+}
+
+/* ################################## SysTick function ############################################ */
+uint32_t SysTick_Config(uint32_t ticks)
+{
+ /* Not support this function */
+ /* Use mbed Ticker */
+ return (1); /* impossible */
+}
+
+
+/* ##################################### Debug In/Output function ########################################### */
+uint32_t ITM_SendChar (uint32_t ch)
+{
+ /* Not support this function */
+ /* Use mbed Serial */
+ return (ch);
+}
+
+
+int32_t ITM_ReceiveChar (void) {
+ /* Not support this function */
+ /* Use mbed Serial */
+ return (-1); /* no character available */
+}
+
+
+int32_t ITM_CheckChar (void) {
+ /* Not support this function */
+ /* Use mbed Serial */
+ return (0); /* no character available */
+}
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,85 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file nvic_wrapper.h
+* $Rev: $
+* $Date:: $
+* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
+******************************************************************************/
+
+#ifndef NVIC_WRAPPER_H
+#define NVIC_WRAPPER_H
+
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/* NVIC functions */
+void NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+uint32_t NVIC_GetPriorityGrouping(void);
+void NVIC_EnableIRQ(IRQn_Type IRQn);
+void NVIC_DisableIRQ(IRQn_Type IRQn);
+uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t NVIC_GetActive(IRQn_Type IRQn);
+void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
+uint32_t NVIC_GetPriority(IRQn_Type IRQn);
+uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority);
+void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+void NVIC_SystemReset(void);
+/* SysTick function */
+uint32_t SysTick_Config(uint32_t ticks);
+/* Debug In/Output function */
+uint32_t ITM_SendChar (uint32_t ch);
+int32_t ITM_ReceiveChar (void);
+int32_t ITM_CheckChar (void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* NVIC_WRAPPER_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/pl310.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,129 @@
+/**************************************************************************//**
+ * @file pl310.c
+ * @brief Implementation of PL310 PrimeCell Level 2 Cache Controller functions
+ * @version
+ * @date 3 December 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+#include "MBRZA1H.h"
+
+//Cache Sync operation
+void PL310_Sync(void)
+{
+ PL310->CACHE_SYNC = 0x0;
+}
+
+//return Cache controller cache ID
+int PL310_GetID (void)
+{
+ return PL310->CACHE_ID;
+}
+
+//return Cache controller cache Type
+int PL310_GetType (void)
+{
+ return PL310->CACHE_TYPE;
+}
+
+//Invalidate all cache by way
+void PL310_InvAllByWay (void)
+{
+ unsigned int assoc;
+
+ if (PL310->AUX_CNT & (1<<16))
+ assoc = 16;
+ else
+ assoc = 8;
+
+ PL310->INV_WAY = (1 << assoc) - 1;
+ while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
+
+ PL310_Sync();
+}
+
+//Clean and Invalidate all cache by way
+void PL310_CleanInvAllByWay (void)
+{
+ unsigned int assoc;
+
+ if (PL310->AUX_CNT & (1<<16))
+ assoc = 16;
+ else
+ assoc = 8;
+
+ PL310->CLEAN_INV_WAY = (1 << assoc) - 1;
+ while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
+
+ PL310_Sync();
+}
+
+//Enable Cache
+void PL310_Enable(void)
+{
+ PL310->CONTROL = 0;
+ PL310->INTERRUPT_CLEAR = 0x000001FFuL;
+ PL310->DEBUG_CONTROL = 0;
+ PL310->DATA_LOCK_0_WAY = 0;
+ PL310->CACHE_SYNC = 0;
+
+ PL310->CONTROL = 0x01;
+ PL310_Sync();
+}
+//Disable Cache
+void PL310_Disable(void)
+{
+ PL310->CONTROL = 0x00;
+ PL310_Sync();
+}
+
+//Invalidate cache by physical address
+void PL310_InvPa (void *pa)
+{
+ PL310->INV_LINE_PA = (unsigned int)pa;
+ PL310_Sync();
+}
+
+//Clean cache by physical address
+void PL310_CleanPa (void *pa)
+{
+ PL310->CLEAN_LINE_PA = (unsigned int)pa;
+ PL310_Sync();
+}
+
+//Clean and invalidate cache by physical address
+void PL310_CleanInvPa (void *pa)
+{
+ PL310->CLEAN_INV_LINE_PA = (unsigned int)pa;
+ PL310_Sync();
+}
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/pl310.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,115 @@
+/**************************************************************************//**
+ * @file pl310.h
+ * @brief Implementation of pl310 functions
+ * @version
+ * @date 11 June 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+#ifndef __PL310
+#define __PL310
+
+typedef struct
+{
+ __I uint32_t CACHE_ID; /*!< Offset: 0x0000 Cache ID Register */
+ __I uint32_t CACHE_TYPE; /*!< Offset: 0x0004 Cache Type Register */
+ uint32_t RESERVED0[0x3e];
+ __IO uint32_t CONTROL; /*!< Offset: 0x0100 Control Register */
+ __IO uint32_t AUX_CNT; /*!< Offset: 0x0104 Auxiliary Control */
+ uint32_t RESERVED1[0x3e];
+ __IO uint32_t EVENT_CONTROL; /*!< Offset: 0x0200 Event Counter Control */
+ __IO uint32_t EVENT_COUNTER1_CONF; /*!< Offset: 0x0204 Event Counter 1 Configuration */
+ __IO uint32_t EVENT_COUNTER0_CONF; /*!< Offset: 0x0208 Event Counter 1 Configuration */
+ uint32_t RESERVED2[0x2];
+ __IO uint32_t INTERRUPT_MASK; /*!< Offset: 0x0214 Interrupt Mask */
+ __I uint32_t MASKED_INT_STATUS; /*!< Offset: 0x0218 Masked Interrupt Status */
+ __I uint32_t RAW_INT_STATUS; /*!< Offset: 0x021c Raw Interrupt Status */
+ __O uint32_t INTERRUPT_CLEAR; /*!< Offset: 0x0220 Interrupt Clear */
+ uint32_t RESERVED3[0x143];
+ __IO uint32_t CACHE_SYNC; /*!< Offset: 0x0730 Cache Sync */
+ uint32_t RESERVED4[0xf];
+ __IO uint32_t INV_LINE_PA; /*!< Offset: 0x0770 Invalidate Line By PA */
+ uint32_t RESERVED6[2];
+ __IO uint32_t INV_WAY; /*!< Offset: 0x077c Invalidate by Way */
+ uint32_t RESERVED5[0xc];
+ __IO uint32_t CLEAN_LINE_PA; /*!< Offset: 0x07b0 Clean Line by PA */
+ uint32_t RESERVED7[1];
+ __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< Offset: 0x07b8 Clean Line by Index/Way */
+ __IO uint32_t CLEAN_WAY; /*!< Offset: 0x07bc Clean by Way */
+ uint32_t RESERVED8[0xc];
+ __IO uint32_t CLEAN_INV_LINE_PA; /*!< Offset: 0x07f0 Clean and Invalidate Line by PA */
+ uint32_t RESERVED9[1];
+ __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< Offset: 0x07f8 Clean and Invalidate Line by Index/Way */
+ __IO uint32_t CLEAN_INV_WAY; /*!< Offset: 0x07fc Clean and Invalidate by Way */
+ uint32_t RESERVED10[0x40];
+ __IO uint32_t DATA_LOCK_0_WAY; /*!< Offset: 0x0900 Data Lockdown 0 by Way */
+ __IO uint32_t INST_LOCK_0_WAY; /*!< Offset: 0x0904 Instruction Lockdown 0 by Way */
+ __IO uint32_t DATA_LOCK_1_WAY; /*!< Offset: 0x0908 Data Lockdown 1 by Way */
+ __IO uint32_t INST_LOCK_1_WAY; /*!< Offset: 0x090c Instruction Lockdown 1 by Way */
+ __IO uint32_t DATA_LOCK_2_WAY; /*!< Offset: 0x0910 Data Lockdown 2 by Way */
+ __IO uint32_t INST_LOCK_2_WAY; /*!< Offset: 0x0914 Instruction Lockdown 2 by Way */
+ __IO uint32_t DATA_LOCK_3_WAY; /*!< Offset: 0x0918 Data Lockdown 3 by Way */
+ __IO uint32_t INST_LOCK_3_WAY; /*!< Offset: 0x091c Instruction Lockdown 3 by Way */
+ __IO uint32_t DATA_LOCK_4_WAY; /*!< Offset: 0x0920 Data Lockdown 4 by Way */
+ __IO uint32_t INST_LOCK_4_WAY; /*!< Offset: 0x0924 Instruction Lockdown 4 by Way */
+ __IO uint32_t DATA_LOCK_5_WAY; /*!< Offset: 0x0928 Data Lockdown 5 by Way */
+ __IO uint32_t INST_LOCK_5_WAY; /*!< Offset: 0x092c Instruction Lockdown 5 by Way */
+ __IO uint32_t DATA_LOCK_6_WAY; /*!< Offset: 0x0930 Data Lockdown 5 by Way */
+ __IO uint32_t INST_LOCK_6_WAY; /*!< Offset: 0x0934 Instruction Lockdown 5 by Way */
+ __IO uint32_t DATA_LOCK_7_WAY; /*!< Offset: 0x0938 Data Lockdown 6 by Way */
+ __IO uint32_t INST_LOCK_7_WAY; /*!< Offset: 0x093c Instruction Lockdown 6 by Way */
+ uint32_t RESERVED11[0x4];
+ __IO uint32_t LOCK_LINE_EN; /*!< Offset: 0x0950 Lockdown by Line Enable */
+ __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< Offset: 0x0954 Unlock All Lines by Way */
+ uint32_t RESERVED12[0xaa];
+ __IO uint32_t ADDRESS_FILTER_START; /*!< Offset: 0x0c00 Address Filtering Start */
+ __IO uint32_t ADDRESS_FILTER_END; /*!< Offset: 0x0c04 Address Filtering End */
+ uint32_t RESERVED13[0xce];
+ __IO uint32_t DEBUG_CONTROL; /*!< Offset: 0x0f40 Debug Control Register */
+
+} PL310_TypeDef;
+
+#define PL310 ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */
+
+extern int PL310_GetID (void);
+extern int PL310_GetType (void);
+extern void PL310_InvAllByWay (void);
+extern void PL310_CleanInvAllByWay(void);
+extern void PL310_Enable(void);
+extern void PL310_Disable(void);
+extern void PL310_InvPa (void *);
+extern void PL310_CleanPa (void *);
+extern void PL310_CleanInvPa (void *);
+
+#endif
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/r_typedefs.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,62 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2013 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_typedefs.h +* $Rev: 788 $ +* $Date:: 2014-04-07 18:57:13 +0900#$ +* Description : basic type definition +******************************************************************************/ +#ifndef R_TYPEDEFS_H +#define R_TYPEDEFS_H + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include <stddef.h> +#include <stdbool.h> +#include <stdint.h> + +#if defined(__ARM_NEON__) + +#include <arm_neon.h> + +#else /* __ARM_NEON__ */ + +typedef float float32_t; +typedef double float64_t; + +#endif /* __ARM_NEON__ */ + +/****************************************************************************** +Typedef definitions +******************************************************************************/ +typedef char char_t; +typedef int bool_t; +typedef int int_t; +typedef long double float128_t; +typedef signed long long_t; +typedef unsigned long ulong_t; + +#endif /* R_TYPEDEFS_H */ + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/rza_io_regrw.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,201 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rza_io_regrw.c
+* $Rev: 1121 $
+* $Date:: 2014-08-06 17:09:53 +0900#$
+* Description : Low level register read/write
+*******************************************************************************/
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+
+#ifdef __CC_ARM
+#pragma arm section code = "CODE_IO_REGRW"
+#pragma arm section rodata = "CONST_IO_REGRW"
+#pragma arm section rwdata = "DATA_IO_REGRW"
+#pragma arm section zidata = "BSS_IO_REGRW"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/******************************************************************************
+* Function Name: RZA_IO_RegWrite_8
+* Description : IO register 8-bit write
+* Arguments : volatile uint8_t * ioreg : IO register for writing
+* : : Use register definition name of the
+* : : iodefine.h
+* : uint8_t write_value : Write value for the IO register
+* : uint8_t shift : The number of left shifts to the
+* : : target bit
+* : uint8_t mask : Mask value for the IO register
+* : : (Target bit : "1")
+* Return Value : None
+******************************************************************************/
+void RZA_IO_RegWrite_8(volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask)
+{
+ uint8_t reg_value;
+
+ reg_value = *ioreg; /* Read from register */
+ reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */
+ *ioreg = reg_value; /* Write to register */
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegWrite_16
+* Description : IO register 16-bit write
+* Arguments : volatile uint16_t * ioreg : IO register for writing
+* : : Use register definition name of the
+* : : iodefine.h
+* : uint16_t write_value : Write value for the IO register
+* : uint16_t shift : The number of left shifts to the
+* : : target bit
+* : uint16_t mask : Mask value for the IO register
+* : : (Target bit : "1")
+* Return Value : None
+******************************************************************************/
+void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask)
+{
+ uint16_t reg_value;
+
+ reg_value = *ioreg; /* Read from register */
+ reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */
+ *ioreg = reg_value; /* Write to register */
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegWrite_32
+* Description : IO register 32-bit write
+* Arguments : volatile uint32_t * ioreg : IO register for writing
+* : : Use register definition name of the
+* : : iodefine.h
+* : uint32_t write_value : Write value for the IO register
+* : uint32_t shift : The number of left shifts to the
+* : : target bit
+* : uint32_t mask : Mask value for the IO register
+* : : (Target bit : "1")
+* Return Value : None
+******************************************************************************/
+void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask)
+{
+ uint32_t reg_value;
+
+ reg_value = *ioreg; /* Read from register */
+ reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */
+ *ioreg = reg_value; /* Write to register */
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegRead_8
+* Description : IO register 8-bit read
+* Arguments : volatile uint8_t * ioreg : IO register for reading
+* : : Use register definition name of the
+* : : iodefine.h
+* : uint8_t shift : The number of right shifts to the
+* : : target bit
+* : uint8_t mask : Mask bit for the IO register
+* : : (Target bit: "1")
+* Return Value : uint8_t : Value of the obtained target bit
+******************************************************************************/
+uint8_t RZA_IO_RegRead_8(volatile uint8_t * ioreg, uint8_t shift, uint8_t mask)
+{
+ uint8_t reg_value;
+
+ reg_value = *ioreg; /* Read from register */
+ reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */
+
+ return reg_value;
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegRead_16
+* Description : IO register 16-bit read
+* Arguments : volatile uint16_t * ioreg : IO register for reading
+* : : Use register definition name of the
+* : : iodefine.h
+* : uint16_t shift : The number of right shifts to the
+* : : target bit
+* : uint16_t mask : Mask bit for the IO register
+* : : (Target bit: "1")
+* Return Value : uint16_t : Value of the obtained target bit
+******************************************************************************/
+uint16_t RZA_IO_RegRead_16(volatile uint16_t * ioreg, uint16_t shift, uint16_t mask)
+{
+ uint16_t reg_value;
+
+ reg_value = *ioreg; /* Read from register */
+ reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */
+
+ return reg_value;
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegRead_32
+* Description : IO register 32-bit read
+* Arguments : volatile uint32_t * ioreg : IO register for reading
+* : : Use register definition name of the
+* : : iodefine.h
+* : uint32_t shift : The number of right shifts to the
+* : : target bit
+* : uint32_t mask : Mask bit for the IO register
+* : : (Target bit: "1")
+* Return Value : uint32_t : Value of the obtained target bit
+******************************************************************************/
+uint32_t RZA_IO_RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask)
+{
+ uint32_t reg_value;
+
+ reg_value = *ioreg; /* Read from register */
+ reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */
+
+ return reg_value;
+}
+
+
+/* End of File */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,522 @@
+/**************************************************************************//**
+ * @file system_MBRZA1H.c
+ * @brief CMSIS Device System Source File for
+ * ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 09 January 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#include <stdint.h>
+#include "MBRZA1H.h"
+#include "RZ_A1_Init.h"
+
+
+#if defined(__ARMCC_VERSION)
+extern void $Super$$main(void);
+__asm void FPUEnable(void);
+#else
+void FPUEnable(void);
+
+#endif
+
+#define FRQCR_IFC_MSK (0x0030)
+#define FRQCR_IFC_SHFT (8)
+#define FRQCR_IFC_1P1 (0) /* x1/1 */
+#define FRQCR_IFC_2P3 (1) /* x2/3 */
+#define FRQCR_IFC_1P3 (3) /* x1/3 */
+
+uint32_t IRQNestLevel;
+unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
+uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the cache.
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
+ */
+#if defined(__ARMCC_VERSION)
+#pragma push
+#pragma arm
+
+void InitMemorySubsystem(void) {
+
+ /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
+ * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
+ * You are not required to invalidate the main TLB, even though it is recommended for safety
+ * reasons. This ensures compatibility with future revisions of the processor. */
+
+ unsigned int l2_id;
+
+ /* Invalidate undefined data */
+ __ca9u_inv_tlb_all();
+ __v7_inv_icache_all();
+ __v7_inv_dcache_all();
+ __v7_inv_btac();
+
+ /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
+ * invalidate in order to flush the valid data to the next level cache.
+ */
+ __enable_mmu();
+
+ /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
+ __enable_caches();
+ __enable_btac();
+
+ /* If present, you may also need to Invalidate and Enable L2 cache here */
+ l2_id = PL310_GetID();
+ if (l2_id)
+ {
+ PL310_InvAllByWay();
+ PL310_Enable();
+ }
+}
+#pragma pop
+
+#elif defined(__GNUC__)
+
+void InitMemorySubsystem(void) {
+
+ /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
+ * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
+ * You are not required to invalidate the main TLB, even though it is recommended for safety
+ * reasons. This ensures compatibility with future revisions of the processor. */
+
+ unsigned int l2_id;
+
+ /* Invalidate undefined data */
+ __ca9u_inv_tlb_all();
+ __v7_inv_icache_all();
+ __v7_inv_dcache_all();
+ __v7_inv_btac();
+
+ /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
+ * invalidate in order to flush the valid data to the next level cache.
+ */
+ __enable_mmu();
+
+ /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
+ __enable_caches();
+ __enable_btac();
+
+ /* If present, you may also need to Invalidate and Enable L2 cache here */
+ l2_id = PL310_GetID();
+ if (l2_id)
+ {
+ PL310_InvAllByWay();
+ PL310_Enable();
+ }
+}
+#elif defined ( __ICCARM__ )
+
+void InitMemorySubsystem(void) {
+
+ /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
+ * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
+ * You are not required to invalidate the main TLB, even though it is recommended for safety
+ * reasons. This ensures compatibility with future revisions of the processor. */
+
+ unsigned int l2_id;
+
+ /* Invalidate undefined data */
+ __ca9u_inv_tlb_all();
+ __v7_inv_icache_all();
+ __v7_inv_dcache_all();
+ __v7_inv_btac();
+
+ /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
+ * invalidate in order to flush the valid data to the next level cache.
+ */
+ __enable_mmu();
+
+ /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
+ __enable_caches();
+ __enable_btac();
+
+ /* If present, you may also need to Invalidate and Enable L2 cache here */
+ l2_id = PL310_GetID();
+ if (l2_id)
+ {
+ PL310_InvAllByWay();
+ PL310_Enable();
+ }
+}
+#else
+
+#endif
+
+
+IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
+
+uint32_t IRQCount = sizeof IRQTable / 4;
+
+uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
+{
+ if (irq < IRQCount) {
+ IRQTable[irq] = handler;
+ return 0;
+ }
+ else {
+ return 1;
+ }
+}
+
+uint32_t InterruptHandlerUnregister (IRQn_Type irq)
+{
+ if (irq < IRQCount) {
+ IRQTable[irq] = 0;
+ return 0;
+ }
+ else {
+ return 1;
+ }
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock.
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
+
+ switch (frqcr_ifc) {
+ case FRQCR_IFC_1P1:
+ SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
+ break;
+ case FRQCR_IFC_2P3:
+ SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
+ break;
+ case FRQCR_IFC_1P3:
+ SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3;
+ break;
+ default:
+ /* do nothing */
+ break;
+ }
+}
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+ IRQNestLevel = 0;
+/* do not use global variables because this function is called before
+ reaching pre-main. RW section maybe overwritten afterwards. */
+ RZ_A1_InitClock();
+ RZ_A1_InitBus();
+
+ //Configure GIC ICDICFR GIC_SetICDICFR()
+ GIC_Enable();
+ __enable_irq();
+
+}
+
+
+//Fault Status Register (IFSR/DFSR) definitions
+#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
+#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external
+#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
+#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
+#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
+#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
+#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
+#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
+#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
+#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
+#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
+#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
+#define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal
+#define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal
+#define FSR_DEBUG_EVENT 0x02 //internal
+#define FSR_SYNC_EXT_ABORT 0x08 //sync/external
+#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
+#define FSR_LOCKDOWN 0x14 //internal
+#define FSR_COPROCESSOR_ABORT 0x1a //internal
+#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
+#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
+#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
+
+void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
+ uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
+
+ switch(FS) {
+ //Synchronous parity errors - retry
+ case FSR_SYNC_PARITY_ERROR:
+ case FSR_SYNC_PARITY_TTB_WALK_FIRST:
+ case FSR_SYNC_PARITY_TTB_WALK_SECOND:
+ return;
+
+ //Your code here. Value in DFAR is invalid for some fault statuses.
+ case FSR_ALIGNMENT_FAULT:
+ case FSR_INSTRUCTION_CACHE_MAINTENANCE:
+ case FSR_SYNC_EXT_TTB_WALK_FIRST:
+ case FSR_SYNC_EXT_TTB_WALK_SECOND:
+ case FSR_TRANSLATION_FAULT_FIRST:
+ case FSR_TRANSLATION_FAULT_SECOND:
+ case FSR_ACCESS_FLAG_FAULT_FIRST:
+ case FSR_ACCESS_FLAG_FAULT_SECOND:
+ case FSR_DOMAIN_FAULT_FIRST:
+ case FSR_DOMAIN_FAULT_SECOND:
+ case FSR_PERMISION_FAULT_FIRST:
+ case FSR_PERMISION_FAULT_SECOND:
+ case FSR_DEBUG_EVENT:
+ case FSR_SYNC_EXT_ABORT:
+ case FSR_TLB_CONFLICT_ABORT:
+ case FSR_LOCKDOWN:
+ case FSR_COPROCESSOR_ABORT:
+ case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
+ case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
+ default:
+ while(1);
+ }
+}
+
+void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
+ uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
+
+ switch(FS) {
+ //Synchronous parity errors - retry
+ case FSR_SYNC_PARITY_ERROR:
+ case FSR_SYNC_PARITY_TTB_WALK_FIRST:
+ case FSR_SYNC_PARITY_TTB_WALK_SECOND:
+ return;
+
+ //Your code here. Value in IFAR is invalid for some fault statuses.
+ case FSR_SYNC_EXT_TTB_WALK_FIRST:
+ case FSR_SYNC_EXT_TTB_WALK_SECOND:
+ case FSR_TRANSLATION_FAULT_FIRST:
+ case FSR_TRANSLATION_FAULT_SECOND:
+ case FSR_ACCESS_FLAG_FAULT_FIRST:
+ case FSR_ACCESS_FLAG_FAULT_SECOND:
+ case FSR_DOMAIN_FAULT_FIRST:
+ case FSR_DOMAIN_FAULT_SECOND:
+ case FSR_PERMISION_FAULT_FIRST:
+ case FSR_PERMISION_FAULT_SECOND:
+ case FSR_DEBUG_EVENT: //IFAR invalid
+ case FSR_SYNC_EXT_ABORT:
+ case FSR_TLB_CONFLICT_ABORT:
+ case FSR_LOCKDOWN:
+ case FSR_COPROCESSOR_ABORT:
+ default:
+ while(1);
+ }
+}
+
+//returns amount to decrement lr by
+//this will be 0 when we have emulated the instruction and want to execute the next instruction
+//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
+//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
+uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
+ const unsigned int THUMB = 2;
+ const unsigned int ARM = 4;
+ //Lazy VFP/NEON initialisation and switching
+
+ // (ARM ARM section A7.5) VFP data processing instruction?
+ // (ARM ARM section A7.6) VFP/NEON register load/store instruction?
+ // (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
+ // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
+ if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
+ (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
+ if (((opcode & 0x00000E00) >> 9) == 5) {
+ FPUEnable();
+ return state;
+ }
+ }
+
+ // (ARM ARM section A7.4) NEON data processing instruction?
+ if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
+ (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
+ // (ARM ARM section A7.7) NEON load/store instruction?
+ (state == ARM && ((opcode >> 24) == 0xF4)) ||
+ (state == THUMB && ((opcode >> 24) == 0xF9))) {
+ FPUEnable();
+ return state;
+ }
+
+ //Add code here for other Undef cases
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION)
+#pragma push
+#pragma arm
+//Critical section, called from undef handler, so systick is disabled
+__asm void FPUEnable(void) {
+ ARM
+
+ //Permit access to VFP/NEON, registers by modifying CPACR
+ MRC p15,0,R1,c1,c0,2
+ ORR R1,R1,#0x00F00000
+ MCR p15,0,R1,c1,c0,2
+
+ //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+ ISB
+
+ //Enable VFP/NEON
+ VMRS R1,FPEXC
+ ORR R1,R1,#0x40000000
+ VMSR FPEXC,R1
+
+ //Initialise VFP/NEON registers to 0
+ MOV R2,#0
+ //Initialise D16 registers to 0
+ VMOV D0, R2,R2
+ VMOV D1, R2,R2
+ VMOV D2, R2,R2
+ VMOV D3, R2,R2
+ VMOV D4, R2,R2
+ VMOV D5, R2,R2
+ VMOV D6, R2,R2
+ VMOV D7, R2,R2
+ VMOV D8, R2,R2
+ VMOV D9, R2,R2
+ VMOV D10,R2,R2
+ VMOV D11,R2,R2
+ VMOV D12,R2,R2
+ VMOV D13,R2,R2
+ VMOV D14,R2,R2
+ VMOV D15,R2,R2
+ //Initialise D32 registers to 0
+ VMOV D16,R2,R2
+ VMOV D17,R2,R2
+ VMOV D18,R2,R2
+ VMOV D19,R2,R2
+ VMOV D20,R2,R2
+ VMOV D21,R2,R2
+ VMOV D22,R2,R2
+ VMOV D23,R2,R2
+ VMOV D24,R2,R2
+ VMOV D25,R2,R2
+ VMOV D26,R2,R2
+ VMOV D27,R2,R2
+ VMOV D28,R2,R2
+ VMOV D29,R2,R2
+ VMOV D30,R2,R2
+ VMOV D31,R2,R2
+ //Initialise FPSCR to a known state
+ VMRS R2,FPSCR
+ LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ AND R2,R2,R3
+ VMSR FPSCR,R2
+
+ BX LR
+}
+#pragma pop
+
+#elif defined(__GNUC__)
+void FPUEnable(void) {
+ __asm__ (
+ ".ARM;"
+
+ //Permit access to VFP/NEON, registers by modifying CPACR
+ "MRC p15,0,R1,c1,c0,2;"
+ "ORR R1,R1,#0x00F00000;"
+ "MCR p15,0,R1,c1,c0,2;"
+
+ //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+ "ISB;"
+
+ //Enable VFP/NEON
+ "VMRS R1,FPEXC;"
+ "ORR R1,R1,#0x40000000;"
+ "VMSR FPEXC,R1;"
+
+ //Initialise VFP/NEON registers to 0
+ "MOV R2,#0;"
+ //Initialise D16 registers to 0
+ "VMOV D0, R2,R2;"
+ "VMOV D1, R2,R2;"
+ "VMOV D2, R2,R2;"
+ "VMOV D3, R2,R2;"
+ "VMOV D4, R2,R2;"
+ "VMOV D5, R2,R2;"
+ "VMOV D6, R2,R2;"
+ "VMOV D7, R2,R2;"
+ "VMOV D8, R2,R2;"
+ "VMOV D9, R2,R2;"
+ "VMOV D10,R2,R2;"
+ "VMOV D11,R2,R2;"
+ "VMOV D12,R2,R2;"
+ "VMOV D13,R2,R2;"
+ "VMOV D14,R2,R2;"
+ "VMOV D15,R2,R2;"
+ //Initialise D32 registers to 0
+ "VMOV D16,R2,R2;"
+ "VMOV D17,R2,R2;"
+ "VMOV D18,R2,R2;"
+ "VMOV D19,R2,R2;"
+ "VMOV D20,R2,R2;"
+ "VMOV D21,R2,R2;"
+ "VMOV D22,R2,R2;"
+ "VMOV D23,R2,R2;"
+ "VMOV D24,R2,R2;"
+ "VMOV D25,R2,R2;"
+ "VMOV D26,R2,R2;"
+ "VMOV D27,R2,R2;"
+ "VMOV D28,R2,R2;"
+ "VMOV D29,R2,R2;"
+ "VMOV D30,R2,R2;"
+ "VMOV D31,R2,R2;"
+
+ //Initialise FPSCR to a known state
+ "VMRS R2,FPSCR;"
+ "LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ "AND R2,R2,R3;"
+ "VMSR FPSCR,R2;"
+
+ //"BX LR;"
+ :
+ :
+ :"r1", "r2", "r3");
+ return;
+}
+#else
+#endif
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file system_MBRZA1H.h
+ * @brief CMSIS Device System Header File for
+ * ARMCA9 Device Series
+ * @version V1.00
+ * @date 11 June 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __SYSTEM_MBRZA1H
+#define __SYSTEM_MBRZA1H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+typedef void(*IRQHandler)();
+uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
+uint32_t InterruptHandlerUnregister(IRQn_Type);
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the Systd short int16_t;emCoreClock variable.
+ */
+extern void SystemInit (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_MBRZA1H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/vfp_neon_push_pop.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,167 @@
+#ifndef __VFP_NEON_PUSH_POP_H__
+#define __VFP_NEON_PUSH_POP_H__
+
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#pragma push
+#pragma arm
+__STATIC_ASM void __vfp_neon_push(void) {
+ ARM
+
+ VMRS R2,FPSCR
+ STMDB SP!,{R2,R4} ; Push FPSCR, maintain 8-byte alignment
+ VSTMDB SP!,{D0-D15}
+ VSTMDB SP!,{D16-D31}
+ BX LR
+}
+#pragma pop
+
+#pragma push
+#pragma arm
+__STATIC_ASM void __vfp_neon_pop(void) {
+ ARM
+
+ VLDMIA SP!,{D16-D31}
+ VLDMIA SP!,{D0-D15}
+ LDR R2,[SP]
+ VMSR FPSCR,R2
+ ADD SP,SP,#8
+ BX LR
+}
+#pragma pop
+
+
+#pragma push
+#pragma arm
+__STATIC_ASM void __vfp_push(void) {
+ ARM
+
+ VMRS R2,FPSCR
+ STMDB SP!,{R2,R4} ; Push FPSCR, maintain 8-byte alignment
+ VSTMDB SP!,{D0-D15}
+ BX LR
+}
+#pragma pop
+
+#pragma push
+#pragma arm
+__STATIC_ASM void __vfp_pop(void) {
+ ARM
+
+ VLDMIA SP!,{D0-D15}
+ LDR R2,[SP]
+ VMSR FPSCR,R2
+ ADD SP,SP,#8
+ BX LR
+}
+#pragma pop
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+
+__arm static inline void __vfp_neon_push(void) {
+__asm(
+ "ARM \n"
+ "VMRS R2,FPSCR \n"
+ "STMDB SP!,{R2,R4} \n" // Push FPSCR, maintain 8-byte alignment
+ "VSTMDB SP!,{D0-D15} \n"
+ "VSTMDB SP!,{D16-D31} \n"
+ "BX lr \n" );
+}
+
+__arm static inline void __vfp_neon_pop(void) {
+__asm(
+ "ARM \n"
+ "VLDMIA SP!,{D16-D31} \n"
+ "VLDMIA SP!,{D0-D15} \n"
+ "LDR R2,[SP] \n"
+ "VMSR FPSCR,R2 \n"
+ "ADD SP,SP,#8 \n"
+ "BX lr \n" );
+}
+
+__arm static inline void __vfp_push(void) {
+__asm(
+ "ARM \n"
+ "VMRS R2,FPSCR \n"
+ "STMDB SP!,{R2,R4} \n" // Push FPSCR, maintain 8-byte alignment
+ "VSTMDB SP!,{D0-D15} \n"
+ "BX lr \n" );
+}
+
+__arm static inline void __vfp_pop(void) {
+__asm(
+ "ARM \n"
+ "VLDMIA SP!,{D0-D15} \n"
+ "LDR R2,[SP] \n"
+ "VMSR FPSCR,R2 \n"
+ "ADD SP,SP,#8 \n"
+ "BX lr \n" );
+}
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_neon_push(void)
+{
+ __asm__ volatile (
+ ".ARM;"
+
+ "VMRS R2,FPSCR;"
+ "STMDB SP!,{R2,R4};" // Push FPSCR, maintain 8-byte alignment
+ "VSTMDB SP!,{D0-D15};"
+ "VSTMDB SP!,{D16-D31};"
+ :
+ : "i"(MODE_USR)
+ : );
+ return;
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_neon_pop(void)
+{
+ __asm__ volatile (
+ ".ARM;"
+
+ "VLDMIA SP!,{D16-D31};"
+ "VLDMIA SP!,{D0-D15};"
+ "LDR R2,[SP];"
+ "VMSR FPSCR,R2;"
+ "ADD SP,SP,#8;"
+ :
+ : "i"(MODE_USR)
+ : );
+ return;
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_push(void)
+{
+ __asm__ volatile (
+ ".ARM;"
+
+ "VMRS R2,FPSCR;"
+ "STMDB SP!,{R2,R4};" // Push FPSCR, maintain 8-byte alignment
+ "VSTMDB SP!,{D0-D15};"
+ :
+ : "i"(MODE_USR)
+ : );
+ return;
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_pop(void)
+{
+ __asm__ volatile (
+ ".ARM;"
+
+ "VLDMIA SP!,{D0-D15};"
+ "LDR R2,[SP];"
+ "VMSR FPSCR,R2;"
+ "ADD SP,SP,#8;"
+ :
+ : "i"(MODE_USR)
+ : );
+ return;
+}
+
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,706 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+#include "ethernet_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "mbed_toolchain.h"
+#include "mbed_error.h"
+#include "ether_iodefine.h"
+#include "ethernetext_api.h"
+
+/* Descriptor info */
+#define NUM_OF_TX_DESCRIPTOR (16)
+#define NUM_OF_RX_DESCRIPTOR (16)
+#define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */
+#define MAX_SEND_SIZE (1514)
+/* Ethernet Descriptor Value Define */
+#define TD0_TFP_TOP_BOTTOM (0x30000000)
+#define TD0_TACT (0x80000000)
+#define TD0_TDLE (0x40000000)
+#define RD0_RACT (0x80000000)
+#define RD0_RDLE (0x40000000)
+#define RD0_RFE (0x08000000)
+#define RD0_RCSE (0x04000000)
+#define RD0_RFS (0x03FF0000)
+#define RD0_RCS (0x0000FFFF)
+#define RD0_RFS_RFOF (0x02000000)
+#define RD0_RFS_RUAF (0x00400000)
+#define RD0_RFS_RRF (0x00100000)
+#define RD0_RFS_RTLF (0x00080000)
+#define RD0_RFS_RTSF (0x00040000)
+#define RD0_RFS_PRE (0x00020000)
+#define RD0_RFS_CERF (0x00010000)
+#define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \
+ RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF)
+#define RD1_RDL_MSK (0x0000FFFF)
+/* PHY Register */
+#define BASIC_MODE_CONTROL_REG (0)
+#define BASIC_MODE_STATUS_REG (1)
+#define PHY_IDENTIFIER1_REG (2)
+#define PHY_IDENTIFIER2_REG (3)
+#define PHY_SP_CTL_STS_REG (31)
+/* MII management interface access */
+#define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */
+#define PHY_ST (1)
+#define PHY_WRITE (1)
+#define PHY_READ (2)
+#define MDC_WAIT (6) /* 400ns/4 */
+#define BASIC_STS_MSK_LINK (0x0004) /* Link Status */
+#define BASIC_STS_MSK_AUTO_CMP (0x0020) /* Auto-Negotiate Complete */
+#define M_PHY_ID (0xFFFFFFF0)
+#define PHY_ID_LAN8710A (0x0007C0F0)
+/* ETHERPIR0 */
+#define PIR0_MDI (0x00000008)
+#define PIR0_MDO (0x00000004)
+#define PIR0_MMD (0x00000002)
+#define PIR0_MDC (0x00000001)
+#define PIR0_MDC_HIGH (0x00000001)
+#define PIR0_MDC_LOW (0x00000000)
+/* ETHEREDRRR0 */
+#define EDRRR0_RR (0x00000001)
+/* ETHEREDTRR0 */
+#define EDTRR0_TR (0x00000003)
+/* software wait */
+#define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */
+
+#define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */
+ /* 0x00040000 : Detect frame reception */
+ /* 0x00010000 : Receive FIFO overflow */
+ /* 0x00000010 : Residual bit frame reception */
+ /* 0x00000008 : Long frame reception */
+ /* 0x00000004 : Short frame reception */
+ /* 0x00000002 : PHY-LSI reception error */
+ /* 0x00000001 : Receive frame CRC error */
+#define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */
+
+/* Send descriptor */
+typedef struct tag_edmac_send_desc {
+ uint32_t td0;
+ uint32_t td1;
+ uint8_t *td2;
+ uint32_t padding4;
+} edmac_send_desc_t;
+
+/* Receive descriptor */
+typedef struct tag_edmac_recv_desc {
+ uint32_t rd0;
+ uint32_t rd1;
+ uint8_t *rd2;
+ uint32_t padding4;
+} edmac_recv_desc_t;
+
+/* memory */
+/* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
+/* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
+#if defined(__ICCARM__)
+#pragma data_alignment=16
+static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
+ (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
+ (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
+ (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned!
+ @ ".mirrorram";
+#else
+static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
+ (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
+ (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
+ (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
+ __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned!
+#endif
+static int32_t rx_read_offset; /* read offset */
+static int32_t tx_wite_offset; /* write offset */
+static uint32_t send_top_index;
+static uint32_t recv_top_index;
+static int32_t Interrupt_priority;
+static edmac_send_desc_t *p_eth_desc_dsend = NULL;
+static edmac_recv_desc_t *p_eth_desc_drecv = NULL;
+static edmac_recv_desc_t *p_recv_end_desc = NULL;
+static ethernetext_cb_fnc *p_recv_cb_fnc = NULL;
+static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */
+static uint32_t phy_id = 0;
+static uint32_t start_stop = 1; /* 0:stop 1:start */
+
+/* function */
+static void lan_reg_reset(void);
+static void lan_desc_create(void);
+static void lan_reg_set(int32_t link);
+static uint16_t phy_reg_read(uint16_t reg_addr);
+static void phy_reg_write(uint16_t reg_addr, uint16_t data);
+static void mii_preamble(void);
+static void mii_cmd(uint16_t reg_addr, uint32_t option);
+static void mii_reg_read(uint16_t *data);
+static void mii_reg_write(uint16_t data);
+static void mii_z(void);
+static void mii_write_1(void);
+static void mii_write_0(void);
+static void set_ether_pir(uint32_t set_data);
+static void wait_100us(int32_t wait_cnt);
+
+
+int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
+ int32_t i;
+ uint16_t val;
+
+ CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */
+
+ /* P4_2(PHY Reset) */
+ GPIOP4 &= ~0x0004; /* Outputs low level */
+ GPIOPMC4 &= ~0x0004; /* Port mode */
+ GPIOPM4 &= ~0x0004; /* Output mode */
+
+ /* GPIO P1 P1_14(ET_COL) */
+ GPIOPMC1 |= 0x4000;
+ GPIOPFCAE1 &= ~0x4000;
+ GPIOPFCE1 |= 0x4000;
+ GPIOPFC1 |= 0x4000;
+
+ /* P3_0(ET_TXCLK), P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
+ GPIOPMC3 |= 0x0079;
+ GPIOPFCAE3 &= ~0x0079;
+ GPIOPFCE3 &= ~0x0079;
+ GPIOPFC3 |= 0x0079;
+ GPIOPIPC3 |= 0x0079;
+
+ /* P5_9(ET_MDC) */
+ GPIOPMC5 |= 0x0200;
+ GPIOPFCAE5 &= ~0x0200;
+ GPIOPFCE5 &= ~0x0200;
+ GPIOPFC5 |= 0x0200;
+ GPIOPIPC5 |= 0x0200;
+
+ /* P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */
+ /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */
+ GPIOPMC10 |= 0x0FFE;
+ GPIOPFCAE10 &= ~0x0FFE;
+ GPIOPFCE10 |= 0x0FFE;
+ GPIOPFC10 |= 0x0FFE;
+ GPIOPIPC10 |= 0x0FFE;
+
+ /* Resets the E-MAC,E-DMAC */
+ lan_reg_reset();
+
+ /* PHY Reset */
+ GPIOP4 &= ~0x0004; /* P4_2 Outputs low level */
+ wait_100us(250); /* 25msec */
+ GPIOP4 |= 0x0004; /* P4_2 Outputs high level */
+ wait_100us(100); /* 10msec */
+
+ /* Resets the PHY-LSI */
+ phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
+ for (i = 10000; i > 0; i--) {
+ val = phy_reg_read(BASIC_MODE_CONTROL_REG);
+ if (((uint32_t)val & 0x8000uL) == 0) {
+ break; /* Reset complete */
+ }
+ }
+
+ phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
+ | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
+
+ Interrupt_priority = p_ethcfg->int_priority;
+ p_recv_cb_fnc = p_ethcfg->recv_cb;
+ start_stop = 1;
+
+ if (p_ethcfg->ether_mac != NULL) {
+ (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
+ } else {
+ ethernet_address(mac_addr); /* Get MAC Address */
+ }
+
+ return 0;
+}
+
+void ethernetext_start_stop(int32_t mode) {
+ if (mode == 1) {
+ /* start */
+ ETHEREDTRR0 |= EDTRR0_TR;
+ ETHEREDRRR0 |= EDRRR0_RR;
+ start_stop = 1;
+ } else {
+ /* stop */
+ ETHEREDTRR0 &= ~EDTRR0_TR;
+ ETHEREDRRR0 &= ~EDRRR0_RR;
+ start_stop = 0;
+ }
+}
+
+int ethernetext_chk_link_mode(void) {
+ int32_t link;
+ uint16_t data;
+
+ if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) {
+ data = phy_reg_read(PHY_SP_CTL_STS_REG);
+ switch (((uint32_t)data >> 2) & 0x00000007) {
+ case 0x0001:
+ link = HALF_10M;
+ break;
+ case 0x0005:
+ link = FULL_10M;
+ break;
+ case 0x0002:
+ link = HALF_TX;
+ break;
+ case 0x0006:
+ link = FULL_TX;
+ break;
+ default:
+ link = NEGO_FAIL;
+ break;
+ }
+ } else {
+ link = NEGO_FAIL;
+ }
+
+ return link;
+}
+
+void ethernetext_set_link_mode(int32_t link) {
+ lan_reg_reset(); /* Resets the E-MAC,E-DMAC */
+ lan_desc_create(); /* Initialize of buffer memory */
+ lan_reg_set(link); /* E-DMAC, E-MAC initialization */
+}
+
+int ethernet_init() {
+ ethernet_cfg_t ethcfg;
+
+ ethcfg.int_priority = 5;
+ ethcfg.recv_cb = NULL;
+ ethcfg.ether_mac = NULL;
+ ethernetext_init(ðcfg);
+ ethernet_set_link(-1, 0); /* Auto-Negotiation */
+
+ return 0;
+}
+
+void ethernet_free() {
+ ETHERARSTR |= 0x00000001; /* ETHER software reset */
+ CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
+}
+
+int ethernet_write(const char *data, int slen) {
+ edmac_send_desc_t *p_send_desc;
+ int32_t copy_size;
+
+ if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
+ || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
+ copy_size = 0;
+ } else {
+ p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
+ if ((p_send_desc->td0 & TD0_TACT) != 0) {
+ copy_size = 0;
+ } else {
+ copy_size = MAX_SEND_SIZE - tx_wite_offset;
+ if (copy_size > slen) {
+ copy_size = slen;
+ }
+ (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size);
+ tx_wite_offset += copy_size;
+ }
+ }
+
+ return copy_size;
+}
+
+int ethernet_send() {
+ edmac_send_desc_t *p_send_desc;
+ int32_t ret;
+
+ if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) {
+ ret = 0;
+ } else {
+ /* Transfer 1 frame */
+ p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
+
+ /* Sets the frame length */
+ p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16);
+ tx_wite_offset = 0;
+
+ /* Sets the transmit descriptor to transmit again */
+ p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM);
+ p_send_desc->td0 |= TD0_TACT;
+ if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) {
+ ETHEREDTRR0 |= EDTRR0_TR;
+ }
+
+ /* Update the current descriptor */
+ send_top_index++;
+ if (send_top_index >= NUM_OF_TX_DESCRIPTOR) {
+ send_top_index = 0;
+ }
+ ret = 1;
+ }
+
+ return ret;
+}
+
+int ethernet_receive() {
+ edmac_recv_desc_t *p_recv_desc;
+ int32_t receive_size = 0;
+
+ if (p_eth_desc_drecv != NULL) {
+ if (p_recv_end_desc != NULL) {
+ /* Sets the receive descriptor to receive again */
+ p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE);
+ p_recv_end_desc->rd0 |= RD0_RACT;
+ if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
+ ETHEREDRRR0 |= EDRRR0_RR;
+ }
+ p_recv_end_desc = NULL;
+ }
+
+ p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */
+ if ((p_recv_desc->rd0 & RD0_RACT) == 0) {
+ /* Receives 1 frame */
+ if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) {
+ /* Receive frame error */
+ /* Sets the receive descriptor to receive again */
+ p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE);
+ p_recv_desc->rd0 |= RD0_RACT;
+ if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
+ ETHEREDRRR0 |= EDRRR0_RR;
+ }
+ } else {
+ /* Copies the received frame */
+ rx_read_offset = 0;
+ p_recv_end_desc = p_recv_desc;
+ receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */
+ }
+
+ /* Update the current descriptor */
+ recv_top_index++;
+ if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) {
+ recv_top_index = 0;
+ }
+ }
+ }
+
+ return receive_size;
+}
+
+int ethernet_read(char *data, int dlen) {
+ edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */
+ int32_t copy_size;
+
+ if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) {
+ copy_size = 0;
+ } else {
+ copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset;
+ if (copy_size > dlen) {
+ copy_size = dlen;
+ }
+ (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size);
+ rx_read_offset += copy_size;
+ }
+
+ return copy_size;
+}
+
+void ethernet_address(char *mac) {
+ if (mac != NULL) {
+ mbed_mac_address(mac); /* Get MAC Address */
+ }
+}
+
+int ethernet_link(void) {
+ int32_t ret;
+ uint16_t data;
+
+ data = phy_reg_read(BASIC_MODE_STATUS_REG);
+ if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) {
+ ret = 1;
+ } else {
+ ret = 0;
+ }
+
+ return ret;
+}
+
+void ethernet_set_link(int speed, int duplex) {
+ uint16_t data;
+ int32_t i;
+ int32_t link;
+
+ if ((speed < 0) || (speed > 1)) {
+ data = 0x1000; /* Auto-Negotiation Enable */
+ phy_reg_write(BASIC_MODE_CONTROL_REG, data);
+ for (i = 0; i < 1000; i++) {
+ data = phy_reg_read(BASIC_MODE_STATUS_REG);
+ if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
+ break;
+ }
+ wait_100us(10);
+ }
+ } else {
+ data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8));
+ phy_reg_write(BASIC_MODE_CONTROL_REG, data);
+ wait_100us(1);
+ }
+
+ link = ethernetext_chk_link_mode();
+ ethernetext_set_link_mode(link);
+}
+
+void INT_Ether(void) {
+ uint32_t stat_edmac;
+ uint32_t stat_etherc;
+
+ /* Clear the interrupt request flag */
+ stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */
+ ETHEREESR0 = stat_edmac;
+ /* Reception-related */
+ if (stat_edmac & EDMAC_EESIPR_INI_RECV) {
+ if (p_recv_cb_fnc != NULL) {
+ p_recv_cb_fnc();
+ }
+ }
+ /* E-MAC-related */
+ if (stat_edmac & EDMAC_EESIPR_INI_EtherC) {
+ /* Clear the interrupt request flag */
+ stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */
+ ETHERECSR0 = stat_etherc;
+ }
+}
+
+static void lan_reg_reset(void) {
+ volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
+
+ ETHERARSTR |= 0x00000001; /* ETHER software reset */
+ while (j--) {
+ /* Do Nothing */
+ }
+
+ ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */
+ ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */
+
+ /* Check clear software reset */
+ while ((ETHEREDMR0 & 0x00000003) != 0) {
+ /* Do Nothing */
+ }
+}
+
+static void lan_desc_create(void) {
+ int32_t i;
+ uint8_t *p_memory_top;
+
+ (void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory));
+ p_memory_top = ethernet_nc_memory;
+
+ /* Descriptor area configuration */
+ p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top;
+ p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR);
+ p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top;
+ p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR);
+
+ /* Transmit descriptor */
+ for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) {
+ p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */
+ p_memory_top += SIZE_OF_BUFFER;
+ p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */
+ p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */
+ }
+ p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */
+
+ /* Receive descriptor */
+ for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) {
+ p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */
+ p_memory_top += SIZE_OF_BUFFER;
+ p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */
+ p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */
+ }
+ p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */
+
+ /* Initialize descriptor management information */
+ send_top_index = 0;
+ recv_top_index = 0;
+ rx_read_offset = 0;
+ tx_wite_offset = 0;
+ p_recv_end_desc = NULL;
+}
+
+static void lan_reg_set(int32_t link) {
+ /* MAC address setting */
+ ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24)
+ | ((uint32_t)mac_addr[1] << 16)
+ | ((uint32_t)mac_addr[2] << 8)
+ | (uint32_t)mac_addr[3];
+ ETHERMALR0 = ((uint32_t)mac_addr[4] << 8)
+ | (uint32_t)mac_addr[5];
+
+ /* E-DMAC */
+ ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0];
+ ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0];
+ ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0];
+ ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0];
+ ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1];
+ ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1];
+ ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */
+ ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */
+ ETHEREDMR0 |= 0x00000040; /* Little endian */
+ ETHERTRSCER0 &= ~0x0003009F; /* All clear */
+ ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */
+ ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */
+ ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */
+ ETHERFCFTR0 &= ~0x001F00FF;
+ ETHERFCFTR0 |= 0x00070007;
+ ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */
+
+ /* E-MAC */
+ ETHERECMR0 &= ~0x04BF2063; /* All clear */
+ ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */
+ ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */
+ ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */
+ ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */
+ ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */
+ if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) {
+ ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */
+ } else {
+ ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */
+ }
+
+ /* Interrupt-related */
+ if (p_recv_cb_fnc != NULL) {
+ ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */
+ ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */
+ ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */
+ ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */
+ InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */
+ GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */
+ GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */
+ }
+
+ ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */
+
+ /* Enable transmission/reception */
+ if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) {
+ ETHEREDRRR0 |= 0x00000001; /* RR */
+ }
+}
+
+static uint16_t phy_reg_read(uint16_t reg_addr) {
+ uint16_t data;
+
+ mii_preamble();
+ mii_cmd(reg_addr, PHY_READ);
+ mii_z();
+ mii_reg_read(&data);
+ mii_z();
+
+ return data;
+}
+
+static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
+ mii_preamble();
+ mii_cmd(reg_addr, PHY_WRITE);
+ mii_write_1();
+ mii_write_0();
+ mii_reg_write(data);
+ mii_z();
+}
+
+static void mii_preamble(void) {
+ int32_t i = 32;
+
+ for (i = 32; i > 0; i--) {
+ /* 1 is output via the MII (Media Independent Interface) block. */
+ mii_write_1();
+ }
+}
+
+static void mii_cmd(uint16_t reg_addr, uint32_t option) {
+ int32_t i;
+ uint16_t data = 0;
+
+ data |= (PHY_ST << 14); /* ST code */
+ data |= (option << 12); /* OP code */
+ data |= (PHY_ADDR << 7); /* PHY Address */
+ data |= (uint16_t)(reg_addr << 2); /* Reg Address */
+ for (i = 14; i > 0; i--) {
+ if ((data & 0x8000) == 0) {
+ mii_write_0();
+ } else {
+ mii_write_1();
+ }
+ data <<= 1;
+ }
+}
+
+static void mii_reg_read(uint16_t *data) {
+ int32_t i;
+ uint16_t reg_data = 0;
+
+ /* Data are read in one bit at a time */
+ for (i = 16; i > 0; i--) {
+ set_ether_pir(PIR0_MDC_LOW);
+ set_ether_pir(PIR0_MDC_HIGH);
+ reg_data <<= 1;
+ reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */
+ set_ether_pir(PIR0_MDC_HIGH);
+ set_ether_pir(PIR0_MDC_LOW);
+ }
+ *data = reg_data;
+}
+
+static void mii_reg_write(uint16_t data) {
+ int32_t i;
+
+ /* Data are written one bit at a time */
+ for (i = 16; i > 0; i--) {
+ if ((data & 0x8000) == 0) {
+ mii_write_0();
+ } else {
+ mii_write_1();
+ }
+ data <<= 1;
+ }
+}
+
+static void mii_z(void) {
+ set_ether_pir(PIR0_MDC_LOW);
+ set_ether_pir(PIR0_MDC_HIGH);
+ set_ether_pir(PIR0_MDC_HIGH);
+ set_ether_pir(PIR0_MDC_LOW);
+}
+
+static void mii_write_1(void) {
+ set_ether_pir(PIR0_MDO | PIR0_MMD);
+ set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
+ set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
+ set_ether_pir(PIR0_MDO | PIR0_MMD);
+}
+
+static void mii_write_0(void) {
+ set_ether_pir(PIR0_MMD);
+ set_ether_pir(PIR0_MMD | PIR0_MDC);
+ set_ether_pir(PIR0_MMD | PIR0_MDC);
+ set_ether_pir(PIR0_MMD);
+}
+
+static void set_ether_pir(uint32_t set_data) {
+ int32_t i;
+
+ for (i = MDC_WAIT; i > 0; i--) {
+ ETHERPIR0 = set_data;
+ }
+}
+
+static void wait_100us(int32_t wait_cnt) {
+ volatile int32_t j = LOOP_100us * wait_cnt;
+
+ while (--j) {
+ /* Do Nothing */
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernetext_api.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,21 @@
+
+/* PHY link mode */
+#define NEGO_FAIL (0)
+#define HALF_10M (1)
+#define FULL_10M (2)
+#define HALF_TX (3)
+#define FULL_TX (4)
+
+typedef void (ethernetext_cb_fnc)(void);
+
+typedef struct tag_ethernet_cfg {
+ int int_priority;
+ ethernetext_cb_fnc *recv_cb;
+ char *ether_mac;
+} ethernet_cfg_t;
+
+extern int ethernetext_init(ethernet_cfg_t *p_ethcfg);
+extern void ethernetext_start_stop(int32_t mode);
+extern int ethernetext_chk_link_mode(void);
+extern void ethernetext_set_link_mode(int32_t link);
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_addrdefine.h Fri Jul 21 01:26:54 2017 +0000 @@ -0,0 +1,23 @@ +#ifndef __GPIO_ADDRDEFINE__ +#define __GPIO_ADDRDEFINE__ + +#define GPIO_BASE ((long)0xFCFE3000uL) /* GPIO */ + +#define PORT(n) (volatile unsigned short *)(GPIO_BASE + 0x000 + ((n)*4)) +#define PSR(n) (volatile unsigned long *)(GPIO_BASE + 0x100 + ((n)*4)) +#define PPR(n) (volatile unsigned short *)(GPIO_BASE + 0x200 + ((n)*4)) +#define PM(n) (volatile unsigned short *)(GPIO_BASE + 0x300 + ((n)*4)) +#define PMC(n) (volatile unsigned short *)(GPIO_BASE + 0x400 + ((n)*4)) +#define PFC(n) (volatile unsigned short *)(GPIO_BASE + 0x500 + ((n)*4)) +#define PFCE(n) (volatile unsigned short *)(GPIO_BASE + 0x600 + ((n)*4)) +#define PNOT(n) (volatile unsigned short *)(GPIO_BASE + 0x700 + ((n)*4)) +#define PMSR(n) (volatile unsigned long *)(GPIO_BASE + 0x800 + ((n)*4)) +#define PMCSR(n) (volatile unsigned long *)(GPIO_BASE + 0x900 + ((n)*4)) +#define PFCAE(n) (volatile unsigned short *)(GPIO_BASE + 0xa00 + ((n)*4)) +#define PIBC(n) (volatile unsigned short *)(GPIO_BASE + 0x4000 +((n)*4)) +#define PBDC(n) (volatile unsigned short *)(GPIO_BASE + 0x4100 +((n)*4)) +#define PIPC(n) (volatile unsigned short *)(GPIO_BASE + 0x4200 +((n)*4)) + +#endif/*__GPIO_ADDRDEFINE__*/ + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "gpio_addrdefine.h"
+
+
+uint32_t gpio_set(PinName pin) {
+ pin_function(pin, 0);
+ return (1 << PINNO(pin));
+}
+
+void gpio_init(gpio_t *obj, PinName pin) {
+ int group ;
+ obj->pin = pin;
+ if(pin == NC) return;
+
+ obj->mask = gpio_set(pin);
+
+ group = PINGROUP(pin);
+ if (group > 11) return;
+
+ obj->reg_set = (volatile uint32_t *) PSR(group);
+ obj->reg_in = (volatile uint32_t *) PPR(group);
+ obj->reg_dir = (volatile uint32_t *)PMSR(group);
+ obj->reg_buf = (volatile uint32_t *)PIBC(group);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+/* Pull up and Pull down settings aren't supported because RZ/A1H doesn't have pull up/down for pins(signals). */
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+ switch (direction) {
+ case PIN_INPUT :
+ *obj->reg_dir = (obj->mask << 16) | obj->mask;
+ *obj->reg_buf |= obj->mask;
+ break;
+ case PIN_OUTPUT:
+ *obj->reg_dir = (obj->mask << 16) | 0;
+ *obj->reg_buf &= ~obj->mask;
+ break;
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,225 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+
+#include "gpio_irq_api.h"
+#include "intc_iodefine.h"
+#include "pinmap.h"
+#include "cmsis.h"
+#include "gpio_addrdefine.h"
+
+#define CHANNEL_NUM 8
+
+static void gpio_irq0(void);
+static void gpio_irq1(void);
+static void gpio_irq2(void);
+static void gpio_irq3(void);
+static void gpio_irq4(void);
+static void gpio_irq5(void);
+static void gpio_irq6(void);
+static void gpio_irq7(void);
+
+static gpio_irq_t *channel_obj[CHANNEL_NUM] = {NULL};
+static gpio_irq_handler irq_handler;
+static const int nIRQn_h = 32;
+extern PinName gpio_multi_guard;
+
+enum {
+ IRQ0,IRQ1,
+ IRQ2,IRQ3,
+ IRQ4,IRQ5,
+ IRQ6,IRQ7,
+
+} IRQNo;
+
+static const IRQHandler irq_tbl[CHANNEL_NUM] = {
+ &gpio_irq0,
+ &gpio_irq1,
+ &gpio_irq2,
+ &gpio_irq3,
+ &gpio_irq4,
+ &gpio_irq5,
+ &gpio_irq6,
+ &gpio_irq7,
+};
+
+static const PinMap PinMap_IRQ[] = {
+ {P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4},
+ {P1_3, IRQ3, 4}, {P1_4, IRQ4, 4}, {P1_5, IRQ5, 4},
+ {P1_6, IRQ6, 4}, {P1_7, IRQ7, 4}, {P1_8, IRQ2, 3},
+ {P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_11, IRQ5, 3}, // 11
+ {P2_0, IRQ5, 6}, {P2_12, IRQ6, 6}, {P2_13, IRQ7, 8},
+ {P2_14, IRQ0, 8}, {P2_15, IRQ1, 8}, // 16
+ {P3_0, IRQ2, 3}, {P3_1, IRQ6, 3}, {P3_3, IRQ4, 3},
+ {P3_9, IRQ6, 8}, // 20
+ {P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8},
+ {P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8},
+ {P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 28
+ {P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 31
+ {P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4},
+ {P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8},
+ {P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8},
+ {P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8},
+ {P6_15, IRQ7, 8}, // 44
+ {P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8},
+ {P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8},
+ {P7_14, IRQ6, 8}, // 51
+ {P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4},
+ {P9_1, IRQ0, 4}, // 55
+ {P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 57
+
+ {NC, NC, 0}
+};
+
+static void handle_interrupt_in(int irq_num) {
+ uint16_t irqs;
+ uint16_t edge_req;
+ gpio_irq_t *obj;
+ gpio_irq_event irq_event;
+
+ irqs = INTCIRQRR;
+ if (irqs & (1 << irq_num)) {
+ obj = channel_obj[irq_num];
+ if (obj != NULL) {
+ edge_req = ((INTCICR1 >> (obj->ch * 2)) & 3);
+ if (edge_req == 1) {
+ irq_event = IRQ_FALL;
+ } else if (edge_req == 2) {
+ irq_event = IRQ_RISE;
+ } else {
+ uint32_t mask = (1 << (obj->pin & 0x0F));
+ __I uint32_t *reg_in = (volatile uint32_t *) PPR((int)PINGROUP(obj->pin));
+
+ if ((*reg_in & mask) == 0) {
+ irq_event = IRQ_FALL;
+ } else {
+ irq_event = IRQ_RISE;
+ }
+ }
+ irq_handler(obj->port, irq_event);
+ }
+ INTCIRQRR &= ~(1 << irq_num);
+ }
+}
+
+static void gpio_irq0(void) {
+ handle_interrupt_in(0);
+}
+
+static void gpio_irq1(void) {
+ handle_interrupt_in(1);
+}
+
+static void gpio_irq2(void) {
+ handle_interrupt_in(2);
+}
+
+static void gpio_irq3(void) {
+ handle_interrupt_in(3);
+}
+
+static void gpio_irq4(void) {
+ handle_interrupt_in(4);
+}
+
+static void gpio_irq5(void) {
+ handle_interrupt_in(5);
+}
+
+static void gpio_irq6(void) {
+ handle_interrupt_in(6);
+}
+
+static void gpio_irq7(void) {
+ handle_interrupt_in(7);
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+ int shift;
+ if (pin == NC) return -1;
+
+ obj->ch = pinmap_peripheral(pin, PinMap_IRQ);
+ obj->pin = (int)pin ;
+ obj->port = (int)id ;
+
+ shift = obj->ch*2;
+ channel_obj[obj->ch] = obj;
+ irq_handler = handler;
+
+ pinmap_pinout(pin, PinMap_IRQ);
+ gpio_multi_guard = pin; /* Set multi guard */
+
+ // INTC settings
+ InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]);
+ INTCICR1 &= ~(0x3 << shift);
+ GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5);
+ obj->int_enable = 1;
+ __enable_irq();
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+ channel_obj[obj->ch] = NULL;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+ int shift = obj->ch*2;
+ uint16_t val = event == IRQ_RISE ? 2 :
+ event == IRQ_FALL ? 1 : 0;
+ uint16_t work_icr_val;
+
+ /* check edge interrupt setting */
+ work_icr_val = INTCICR1;
+ if (enable == 1) {
+ /* Set interrupt serect */
+ work_icr_val |= (val << shift);
+ } else {
+ /* Clear interrupt serect */
+ work_icr_val &= ~(val << shift);
+ }
+
+ if ((work_icr_val & (3 << shift)) == 0) {
+ /* No edge interrupt setting */
+ GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
+ /* Clear Interrupt flags */
+ INTCIRQRR &= ~(1 << obj->ch);
+ INTCICR1 = work_icr_val;
+ } else if (obj->int_enable == 1) {
+ INTCICR1 = work_icr_val;
+ GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
+ } else {
+ INTCICR1 = work_icr_val;
+ }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj) {
+ int shift = obj->ch*2;
+ uint16_t work_icr_val = INTCICR1;
+
+ /* check edge interrupt setting */
+ if ((work_icr_val & (3 << shift)) != 0) {
+ GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
+ }
+ obj->int_enable = 1;
+}
+
+void gpio_irq_disable(gpio_irq_t *obj) {
+ GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
+ obj->int_enable = 0;
+}
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __I uint32_t *reg_in;
+ __IO uint32_t *reg_buf;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ *obj->reg_set = (obj->mask << 16) | ((value != 0) ? obj->mask : 0);
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+static inline int gpio_is_connected(const gpio_t *obj) {
+ return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,1148 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "dma_api.h"
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "r_typedefs.h"
+
+#include "riic_iodefine.h"
+#include "RZ_A1_Init.h"
+#include "MBRZA1H.h"
+
+volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
+
+#define REG(N) \
+ RIIC[obj->i2c.i2c]->RIICn##N
+
+/* RIICnCR1 */
+#define CR1_RST (1 << 6)
+#define CR1_ICE (1 << 7)
+
+/* RIICnCR2 */
+#define CR2_ST (1 << 1)
+#define CR2_RS (1 << 2)
+#define CR2_SP (1 << 3)
+#define CR2_TRS (1 << 5)
+#define CR2_BBSY (1 << 7)
+
+/* RIICnMR3 */
+#define MR3_ACKBT (1 << 3)
+#define MR3_ACKWP (1 << 4)
+#define MR3_WAIT (1 << 6)
+
+/* RIICnSER */
+#define SER_SAR0E (1 << 0)
+
+/* RIICnSR1 */
+#define SR1_AAS0 (1 << 0)
+
+/* RIICnSR2 */
+#define SR2_START (1 << 2)
+#define SR2_STOP (1 << 3)
+#define SR2_NACKF (1 << 4)
+#define SR2_RDRF (1 << 5)
+#define SR2_TEND (1 << 6)
+#define SR2_TDRE (1 << 7)
+
+#define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */
+
+static const PinMap PinMap_I2C_SDA[] = {
+ {P1_1 , I2C_0, 1},
+ {P1_3 , I2C_1, 1},
+ {P1_7 , I2C_3, 1},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+ {P1_0 , I2C_0, 1},
+ {P1_2 , I2C_1, 1},
+ {P1_6 , I2C_3, 1},
+ {NC , NC, 0}
+};
+
+static inline int i2c_status(i2c_t *obj) {
+ return REG(SR2.UINT8[0]);
+}
+
+static void i2c_reg_reset(i2c_t *obj) {
+ /* full reset */
+ REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
+ REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on
+ REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on
+
+ REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack)
+ REG(SER.UINT8[0]) = 0x00; // no slave addr enabled
+
+ /* set frequency */
+ REG(MR1.UINT8[0]) |= obj->i2c.pclk_bit;
+ REG(BRL.UINT8[0]) = obj->i2c.width_low;
+ REG(BRH.UINT8[0]) = obj->i2c.width_hi;
+
+ REG(MR2.UINT8[0]) = 0x07;
+ REG(MR3.UINT8[0]) = 0x00;
+
+ REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT
+ REG(IER.UINT8[0]) = 0x00; // no interrupt
+
+ REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset
+}
+
+static inline int i2c_wait_RDRF(i2c_t *obj) {
+ int timeout = 0;
+
+ /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+ while ((i2c_status(obj) & SR2_RDRF) == 0) {
+ timeout ++;
+ if (timeout >= WAIT_TIMEOUT) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+static int i2c_wait_TDRE(i2c_t *obj) {
+ int timeout = 0;
+
+ /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+ while ((i2c_status(obj) & SR2_TDRE) == 0) {
+ timeout ++;
+ if (timeout >= WAIT_TIMEOUT) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+static int i2c_wait_TEND(i2c_t *obj) {
+ int timeout = 0;
+
+ /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+ while ((i2c_status(obj) & SR2_TEND) == 0) {
+ timeout ++;
+ if (timeout >= WAIT_TIMEOUT) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+
+static int i2c_wait_START(i2c_t *obj) {
+ int timeout = 0;
+
+ /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+ while ((i2c_status(obj) & SR2_START) == 0) {
+ timeout ++;
+ if (timeout >= WAIT_TIMEOUT) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+static int i2c_wait_STOP(i2c_t *obj) {
+ int timeout = 0;
+
+ /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+ while ((i2c_status(obj) & SR2_STOP) == 0) {
+ timeout ++;
+ if (timeout >= WAIT_TIMEOUT) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+static int i2c_set_STOP(i2c_t *obj) {
+ /* SR2.STOP = 0 */
+ REG(SR2.UINT32) &= ~SR2_STOP;
+ /* Stop condition */
+ REG(CR2.UINT32) |= CR2_SP;
+
+ return 0;
+}
+
+static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
+ /* SR2.NACKF = 0 */
+ REG(SR2.UINT32) &= ~SR2_NACKF;
+ /* SR2.STOP = 0 */
+ REG(SR2.UINT32) &= ~SR2_STOP;
+}
+
+static void i2c_set_MR3_NACK(i2c_t *obj) {
+ /* send a NOT ACK */
+ REG(MR3.UINT32) |= MR3_ACKWP;
+ REG(MR3.UINT32) |= MR3_ACKBT;
+ REG(MR3.UINT32) &= ~MR3_ACKWP;
+}
+
+static void i2c_set_MR3_ACK(i2c_t *obj) {
+ /* send a ACK */
+ REG(MR3.UINT32) |= MR3_ACKWP;
+ REG(MR3.UINT32) &= ~MR3_ACKBT;
+ REG(MR3.UINT32) &= ~MR3_ACKWP;
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+ volatile uint8_t dummy;
+ switch ((int)obj->i2c.i2c) {
+ case I2C_0:
+ CPGSTBCR9 &= ~(0x80);
+ break;
+ case I2C_1:
+ CPGSTBCR9 &= ~(0x40);
+ break;
+ case I2C_2:
+ CPGSTBCR9 &= ~(0x20);
+ break;
+ case I2C_3:
+ CPGSTBCR9 &= ~(0x10);
+ break;
+ }
+ dummy = CPGSTBCR9;
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+ /* determine the I2C to use */
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+ obj->i2c.i2c = pinmap_merge(i2c_sda, i2c_scl);
+ MBED_ASSERT((int)obj->i2c.i2c != NC);
+
+ /* enable power */
+ i2c_power_enable(obj);
+
+ /* set default frequency at 100k */
+ i2c_frequency(obj, 100000);
+
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+
+ obj->i2c.last_stop_flag = 1;
+}
+
+inline int i2c_start(i2c_t *obj) {
+ int timeout = 0;
+
+ while ((REG(CR2.UINT32) & CR2_BBSY) != 0) {
+ timeout ++;
+ if (timeout >= obj->i2c.bbsy_wait_cnt) {
+ break;
+ }
+ }
+ /* Start Condition */
+ REG(CR2.UINT8[0]) |= CR2_ST;
+
+ return 0;
+}
+
+static inline int i2c_restart(i2c_t *obj) {
+ /* SR2.START = 0 */
+ REG(SR2.UINT32) &= ~SR2_START;
+ /* ReStart condition */
+ REG(CR2.UINT32) |= CR2_RS;
+
+ return 0;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+ (void)i2c_set_STOP(obj);
+ (void)i2c_wait_STOP(obj);
+ i2c_set_SR2_NACKF_STOP(obj);
+
+ return 0;
+}
+
+static void i2c_set_err_noslave(i2c_t *obj) {
+ (void)i2c_set_STOP(obj);
+ (void)i2c_wait_STOP(obj);
+ i2c_set_SR2_NACKF_STOP(obj);
+ obj->i2c.last_stop_flag = 1;
+}
+
+static inline int i2c_do_write(i2c_t *obj, int value) {
+ int timeout = 0;
+
+ /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+ while ((i2c_status(obj) & SR2_TDRE) == 0) {
+ timeout ++;
+ if (timeout >= WAIT_TIMEOUT) {
+ return -1;
+ }
+ }
+ /* write the data */
+ REG(DRT.UINT32) = value;
+
+ return 0;
+}
+
+static inline int i2c_read_address_write(i2c_t *obj, int value) {
+ int status;
+
+ status = i2c_wait_TDRE(obj);
+ if (status == 0) {
+ /* write the data */
+ REG(DRT.UINT32) = value;
+ }
+
+ return status;
+
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+ if (last == 2) {
+ /* this time is befor last byte read */
+ /* Set MR3 WAIT bit is 1 */;
+ REG(MR3.UINT32) |= MR3_WAIT;
+ } else if (last == 1) {
+ i2c_set_MR3_NACK(obj);
+ } else {
+ i2c_set_MR3_ACK(obj);
+ }
+
+ /* return the data */
+ return (REG(DRR.UINT32) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+ float64_t pclk_val;
+ float64_t wait_utime;
+ volatile float64_t bps;
+ volatile float64_t L_time; /* H Width period */
+ volatile float64_t H_time; /* L Width period */
+ uint32_t tmp_L_width;
+ uint32_t tmp_H_width;
+ uint32_t remainder;
+ uint32_t wk_cks = 0;
+
+ /* set PCLK */
+ if (false == RZ_A1_IsClockMode0()) {
+ pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK;
+ } else {
+ pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK;
+ }
+
+ /* Min 10kHz, Max 400kHz */
+ if (hz < 10000) {
+ bps = 10000;
+ } else if (hz > 400000) {
+ bps = 400000;
+ } else {
+ bps = (float64_t)hz;
+ }
+
+ /* Calculation L width time */
+ L_time = (1 / (2 * bps)); /* Harf period of frequency */
+ H_time = L_time;
+
+ /* Check I2C mode of Speed */
+ if (bps > 100000) {
+ /* Fast-mode */
+ L_time -= 102E-9; /* Falling time of SCL clock. */
+ H_time -= 138E-9; /* Rising time of SCL clock. */
+ /* Check L wideth */
+ if (L_time < 1.3E-6) {
+ /* Wnen L width less than 1.3us */
+ /* Subtract Rise up and down time for SCL from H/L width */
+ L_time = 1.3E-6;
+ H_time = (1 / bps) - L_time - 138E-9 - 102E-9;
+ }
+ }
+
+ tmp_L_width = (uint32_t)(L_time * pclk_val * 10);
+ tmp_L_width >>= 1;
+ wk_cks++;
+ while (tmp_L_width >= 341) {
+ tmp_L_width >>= 1;
+ wk_cks++;
+ }
+ remainder = tmp_L_width % 10;
+ tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */
+
+ tmp_H_width = (uint32_t)(H_time * pclk_val * 10);
+ tmp_H_width >>= wk_cks;
+ if (remainder == 0) {
+ tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */
+ } else {
+ remainder += tmp_H_width % 10;
+ tmp_H_width = (tmp_H_width / 10) - 3;
+ if (remainder > 10) {
+ tmp_H_width += 1; /* fine adjustment */
+ }
+ }
+ /* timeout of BBSY bit is minimum low width by frequency */
+ /* so timeout calculates "(low width) * 2" by frequency */
+ wait_utime = (L_time * 2) * 1000000;
+ /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */
+ if (wait_utime <= 0.3) {
+ obj->i2c.bbsy_wait_cnt = 1;
+ } else {
+ obj->i2c.bbsy_wait_cnt = (int)(wait_utime / 0.3);
+ }
+
+
+ /* I2C Rate */
+ obj->i2c.pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */
+ obj->i2c.width_low = (uint8_t)(tmp_L_width | 0x000000E0);
+ obj->i2c.width_hi = (uint8_t)(tmp_H_width | 0x000000E0);
+
+ /* full reset */
+ i2c_reg_reset(obj);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+ int count = 0;
+ int status;
+ int value;
+ volatile uint32_t work_reg = 0;
+
+ i2c_set_MR3_ACK(obj);
+ /* There is a STOP condition for last processing */
+ if (obj->i2c.last_stop_flag != 0) {
+ status = i2c_start(obj);
+ if (status != 0) {
+ i2c_set_err_noslave(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+ }
+ obj->i2c.last_stop_flag = stop;
+ /* Send Slave address */
+ status = i2c_read_address_write(obj, (address | 0x01));
+ if (status != 0) {
+ i2c_set_err_noslave(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+ /* wait RDRF */
+ status = i2c_wait_RDRF(obj);
+ /* check ACK/NACK */
+ if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
+ /* Slave sends NACK */
+ (void)i2c_set_STOP(obj);
+ /* dummy read */
+ value = REG(DRR.UINT32);
+ (void)i2c_wait_STOP(obj);
+ i2c_set_SR2_NACKF_STOP(obj);
+ obj->i2c.last_stop_flag = 1;
+ return I2C_ERROR_NO_SLAVE;
+ }
+ if (length != 0) {
+ /* Read in all except last byte */
+ if (length > 2) {
+ /* dummy read */
+ value = REG(DRR.UINT32);
+ for (count = 0; count < (length - 1); count++) {
+ /* wait for it to arrive */
+ status = i2c_wait_RDRF(obj);
+ if (status != 0) {
+ i2c_set_err_noslave(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+ /* Recieve the data */
+ if (count == (length - 2)) {
+ value = i2c_do_read(obj, 1);
+ } else if ((length >= 3) && (count == (length - 3))) {
+ value = i2c_do_read(obj, 2);
+ } else {
+ value = i2c_do_read(obj, 0);
+ }
+ data[count] = (char)value;
+ }
+ } else if (length == 2) {
+ /* Set MR3 WAIT bit is 1 */
+ REG(MR3.UINT32) |= MR3_WAIT;
+ /* dummy read */
+ value = REG(DRR.UINT32);
+ /* wait for it to arrive */
+ status = i2c_wait_RDRF(obj);
+ if (status != 0) {
+ i2c_set_err_noslave(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+ i2c_set_MR3_NACK(obj);
+ data[count] = (char)REG(DRR.UINT32);
+ count++;
+ } else {
+ /* length == 1 */
+ /* Set MR3 WAIT bit is 1 */;
+ REG(MR3.UINT32) |= MR3_WAIT;
+ i2c_set_MR3_NACK(obj);
+ /* dummy read */
+ value = REG(DRR.UINT32);
+ }
+ /* wait for it to arrive */
+ status = i2c_wait_RDRF(obj);
+ if (status != 0) {
+ i2c_set_err_noslave(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ /* If not repeated start, send stop. */
+ if (stop) {
+ (void)i2c_set_STOP(obj);
+ /* RIICnDRR read */
+ value = (REG(DRR.UINT32) & 0xFF);
+ data[count] = (char)value;
+ /* RIICnMR3.WAIT = 0 */
+ REG(MR3.UINT32) &= ~MR3_WAIT;
+ (void)i2c_wait_STOP(obj);
+ i2c_set_SR2_NACKF_STOP(obj);
+ } else {
+ (void)i2c_restart(obj);
+ /* RIICnDRR read */
+ value = (REG(DRR.UINT32) & 0xFF);
+ data[count] = (char)value;
+ /* RIICnMR3.WAIT = 0 */
+ REG(MR3.UINT32) &= ~MR3_WAIT;
+ (void)i2c_wait_START(obj);
+ /* SR2.START = 0 */
+ REG(SR2.UINT32) &= ~SR2_START;
+ }
+ } else {
+ /* If not repeated start, send stop. */
+ if (stop) {
+ (void)i2c_set_STOP(obj);
+ (void)i2c_wait_STOP(obj);
+ i2c_set_SR2_NACKF_STOP(obj);
+ } else {
+ (void)i2c_restart(obj);
+ (void)i2c_wait_START(obj);
+ /* SR2.START = 0 */
+ REG(SR2.UINT32) &= ~SR2_START;
+ }
+ }
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+ int cnt;
+ int status;
+
+ /* There is a STOP condition for last processing */
+ if (obj->i2c.last_stop_flag != 0) {
+ status = i2c_start(obj);
+ if (status != 0) {
+ i2c_set_err_noslave(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+ }
+ obj->i2c.last_stop_flag = stop;
+ /* Send Slave address */
+ status = i2c_do_write(obj, address);
+ if (status != 0) {
+ i2c_set_err_noslave(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+ /* Wait send end */
+ status = i2c_wait_TEND(obj);
+ if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
+ /* Slave sends NACK */
+ i2c_set_err_noslave(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+ /* Send Write data */
+ for (cnt=0; cnt<length; cnt++) {
+ status = i2c_do_write(obj, data[cnt]);
+ if(status != 0) {
+ i2c_set_err_noslave(obj);
+ return cnt;
+ } else {
+ /* Wait send end */
+ status = i2c_wait_TEND(obj);
+ if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
+ /* Slave sends NACK */
+ i2c_set_err_noslave(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+ }
+ }
+ /* If not repeated start, send stop. */
+ if (stop) {
+ (void)i2c_set_STOP(obj);
+ (void)i2c_wait_STOP(obj);
+ i2c_set_SR2_NACKF_STOP(obj);
+ } else {
+ (void)i2c_restart(obj);
+ (void)i2c_wait_START(obj);
+ /* SR2.START = 0 */
+ REG(SR2.UINT32) &= ~SR2_START;
+
+ }
+
+ return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+ (void)i2c_set_STOP(obj);
+ (void)i2c_wait_STOP(obj);
+ i2c_set_SR2_NACKF_STOP(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+ int status;
+ int data;
+
+ data = i2c_do_read(obj, last);
+ /* wait for it to arrive */
+ status = i2c_wait_RDRF(obj);
+ if (status != 0) {
+ i2c_set_SR2_NACKF_STOP(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ return data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+ int ack = 0;
+ int status;
+ int timeout = 0;
+
+ status = i2c_do_write(obj, (data & 0xFF));
+ if (status != 0) {
+ i2c_set_SR2_NACKF_STOP(obj);
+ } else {
+ while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) {
+ timeout++;
+ if (timeout >= WAIT_TIMEOUT) {
+ return ack;
+ }
+ }
+ /* check ACK/NACK */
+ if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
+ /* NACK */
+ i2c_set_SR2_NACKF_STOP(obj);
+ } else {
+ ack = 1;
+ }
+ }
+
+ return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+ if (enable_slave != 0) {
+ REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled
+ } else {
+ REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled
+ }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+ int status;
+ int retval;
+
+ status = (REG(SR1.UINT8[0]) & SR1_AAS0);
+ status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4;
+
+ switch(status) {
+ case 0x01:
+ /* the master is writing to this slave */
+ retval = 3;
+ break;
+ case 0x02:
+ /* the master is writing to all slave */
+ retval = 2;
+ break;
+ case 0x03:
+ /* the master has requested a read from this slave */
+ retval = 1;
+ break;
+ default :
+ /* no data */
+ retval = 0;
+ break;
+ }
+
+ return retval;
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+ int timeout = 0;
+ int count;
+ int break_flg = 0;
+
+ if(length <= 0) {
+ return 0;
+ }
+ for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
+ /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+ while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) {
+ if ((i2c_status(obj) & SR2_STOP) != 0) {
+ break_flg = 1;
+ break;
+ }
+ timeout ++;
+ if (timeout >= WAIT_TIMEOUT) {
+ return -1;
+ }
+ }
+ if (break_flg == 0) {
+ if (count == 0) {
+ /* dummy read */
+ (void)REG(DRR.UINT32);
+ } else {
+ data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF);
+ }
+ }
+ }
+ if (break_flg == 0) {
+ (void)i2c_wait_STOP(obj);
+ } else {
+ if ((i2c_status(obj) & SR2_RDRF) != 0) {
+ if (count <= 1) {
+ /* fail safe */
+ /* dummy read */
+ (void)REG(DRR.UINT32);
+ } else {
+ data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF);
+ }
+ }
+ }
+ /* SR2.STOP = 0 */
+ REG(SR2.UINT32) &= ~SR2_STOP;
+
+ return (count - 1);
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+ int count = 0;
+ int status = 0;
+
+ if(length <= 0) {
+ return 0;
+ }
+
+ while ((count < length) && (status == 0)) {
+ status = i2c_do_write(obj, data[count]);
+ if(status == 0) {
+ /* Wait send end */
+ status = i2c_wait_TEND(obj);
+ if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) {
+ /* NACK */
+ break;
+ }
+ }
+ count++;
+ }
+ /* dummy read */
+ (void)REG(DRR.UINT32);
+ (void)i2c_wait_STOP(obj);
+ i2c_set_SR2_NACKF_STOP(obj);
+
+ return count;
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+ REG(SAR0.UINT32) = (address & 0xfffffffe);
+}
+
+#if DEVICE_I2C_ASYNCH
+
+#define IRQ_NUM 4
+#define IRQ_TX 0
+#define IRQ_RX 1
+#define IRQ_ERR1 2
+#define IRQ_ERR2 3
+
+static void i2c_irqs_set(i2c_t *obj, uint32_t enable);
+
+static void i2c0_tx_irq(void);
+static void i2c1_tx_irq(void);
+static void i2c2_tx_irq(void);
+static void i2c3_tx_irq(void);
+static void i2c0_rx_irq(void);
+static void i2c1_rx_irq(void);
+static void i2c2_rx_irq(void);
+static void i2c3_rx_irq(void);
+static void i2c0_al_irq(void);
+static void i2c1_al_irq(void);
+static void i2c2_al_irq(void);
+static void i2c3_al_irq(void);
+static void i2c0_to_irq(void);
+static void i2c1_to_irq(void);
+static void i2c2_to_irq(void);
+static void i2c3_to_irq(void);
+
+static const IRQn_Type irq_set_tbl[RIIC_COUNT][IRQ_NUM] = {
+ {INTIICTEI0_IRQn, INTIICRI0_IRQn, INTIICALI0_IRQn, INTIICTMOI0_IRQn},
+ {INTIICTEI1_IRQn, INTIICRI1_IRQn, INTIICALI1_IRQn, INTIICTMOI1_IRQn},
+ {INTIICTEI2_IRQn, INTIICRI2_IRQn, INTIICALI2_IRQn, INTIICTMOI2_IRQn},
+ {INTIICTEI3_IRQn, INTIICRI3_IRQn, INTIICALI3_IRQn, INTIICTMOI3_IRQn},
+};
+
+static const IRQHandler hander_set_tbl[RIIC_COUNT][IRQ_NUM] = {
+ {i2c0_tx_irq, i2c0_rx_irq, i2c0_al_irq, i2c0_to_irq},
+ {i2c1_tx_irq, i2c1_rx_irq, i2c1_al_irq, i2c1_to_irq},
+ {i2c2_tx_irq, i2c2_rx_irq, i2c2_al_irq, i2c2_to_irq},
+ {i2c3_tx_irq, i2c3_rx_irq, i2c3_al_irq, i2c3_to_irq},
+};
+
+struct i2c_global_data_s {
+ i2c_t *async_obj;
+ uint32_t async_callback, event, shouldStop, address;
+};
+
+static struct i2c_global_data_s i2c_data[RIIC_COUNT];
+
+static void i2c_transfer_finished(i2c_t *obj)
+{
+ i2c_irqs_set(obj, 0);
+ uint32_t index = obj->i2c.i2c;
+ i2c_data[index].event = I2C_EVENT_TRANSFER_COMPLETE;
+ i2c_data[index].async_obj = NULL;
+ ((void (*)())i2c_data[index].async_callback)();
+}
+
+static void i2c_tx_irq(IRQn_Type irq_num, uint32_t index)
+{
+ i2c_t *obj = i2c_data[index].async_obj;
+ if ((REG(SR2.UINT32) & SR2_NACKF)) {
+ /* Slave sends NACK */
+ i2c_set_err_noslave(obj);
+ i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK;
+ i2c_abort_asynch(obj);
+ ((void (*)())i2c_data[index].async_callback)();
+ return;
+ }
+ if (obj->tx_buff.pos == obj->tx_buff.length) {
+ /* All datas have tranferred */
+
+ /* Clear TEND */
+ REG(SR2.UINT32) &= ~(SR2_TEND);
+
+ /* If not repeated start, send stop. */
+ if (i2c_data[index].shouldStop && obj->rx_buff.length == 0) {
+ (void)i2c_set_STOP(obj);
+ (void)i2c_wait_STOP(obj);
+ i2c_set_SR2_NACKF_STOP(obj);
+ i2c_transfer_finished(obj);
+ } else {
+ (void)i2c_restart(obj);
+ (void)i2c_wait_START(obj);
+ /* SR2.START = 0 */
+ REG(SR2.UINT32) &= ~SR2_START;
+ if (obj->rx_buff.length) {
+ /* Ready to read */
+ i2c_set_MR3_ACK(obj);
+
+ /* Disable INTRIICTEI */
+ REG(IER.UINT8[0]) &= ~(1 << 6);
+
+ /* Send Slave address */
+ if (i2c_read_address_write(obj, (i2c_data[index].address | 0x01)) != 0) {
+ i2c_set_err_noslave(obj);
+ i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
+ i2c_abort_asynch(obj);
+ ((void (*)())i2c_data[index].async_callback)();
+ return;
+ }
+ } else {
+ i2c_transfer_finished(obj);
+ }
+ }
+ } else {
+ /* Send next 1 byte */
+ if (i2c_do_write(obj, *(uint8_t *)obj->tx_buff.buffer) != 0) {
+ i2c_set_err_noslave(obj);
+ i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
+ i2c_abort_asynch(obj);
+ ((void (*)())i2c_data[index].async_callback)();
+ return;
+ }
+ obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
+ ++obj->tx_buff.pos;
+ }
+}
+
+static void i2c_rx_irq(IRQn_Type irq_num, uint32_t index)
+{
+ i2c_t *obj = i2c_data[index].async_obj;
+ if (obj->rx_buff.pos == SIZE_MAX) {
+ if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
+ /* Slave sends NACK */
+ (void)i2c_set_STOP(obj);
+ /* dummy read */
+ if (REG(DRR.UINT32)) {}
+ (void)i2c_wait_STOP(obj);
+ i2c_set_SR2_NACKF_STOP(obj);
+ obj->i2c.last_stop_flag = 1;
+
+ i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK;
+ i2c_abort_asynch(obj);
+ ((void (*)())i2c_data[index].async_callback)();
+ return;
+ }
+ if (obj->rx_buff.length == 1) {
+ /* length == 1 */
+ /* Set MR3 WAIT bit is 1 */;
+ REG(MR3.UINT32) |= MR3_WAIT;
+ i2c_set_MR3_NACK(obj);
+ } else if (obj->rx_buff.length == 2) {
+ /* Set MR3 WAIT bit is 1 */
+ REG(MR3.UINT32) |= MR3_WAIT;
+ }
+ /* dummy read */
+ if (REG(DRR.UINT32)) {}
+ obj->rx_buff.pos = 0;
+ return;
+ }
+ if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
+ /* Slave sends NACK */
+ i2c_set_err_noslave(obj);
+ i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK;
+ i2c_abort_asynch(obj);
+ ((void (*)())i2c_data[index].async_callback)();
+ return;
+ } else {
+ switch (obj->rx_buff.length - obj->rx_buff.pos) {
+ case 1:
+ /* Finished */
+ /* If not repeated start, send stop. */
+ if (i2c_data[index].shouldStop) {
+ (void)i2c_set_STOP(obj);
+ /* RIICnDRR read */
+ *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF;
+ /* RIICnMR3.WAIT = 0 */
+ REG(MR3.UINT32) &= ~MR3_WAIT;
+ (void)i2c_wait_STOP(obj);
+ i2c_set_SR2_NACKF_STOP(obj);
+ } else {
+ (void)i2c_restart(obj);
+ /* RIICnDRR read */
+ *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF;
+ /* RIICnMR3.WAIT = 0 */
+ REG(MR3.UINT32) &= ~MR3_WAIT;
+ (void)i2c_wait_START(obj);
+ /* SR2.START = 0 */
+ REG(SR2.UINT32) &= ~SR2_START;
+ }
+
+ i2c_transfer_finished(obj);
+ return;
+
+ case 2:
+ i2c_set_MR3_NACK(obj);
+ break;
+
+ case 3:
+ /* this time is befor last byte read */
+ /* Set MR3 WAIT bit is 1 */
+ REG(MR3.UINT32) |= MR3_WAIT;
+ break;
+
+ default:
+ i2c_set_MR3_ACK(obj);
+ break;
+ }
+ *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF;
+ obj->rx_buff.buffer = (uint8_t *)obj->rx_buff.buffer + 1;
+ ++obj->rx_buff.pos;
+ }
+}
+
+static void i2c_err_irq(IRQn_Type irq_num, uint32_t index)
+{
+ i2c_t *obj = i2c_data[index].async_obj;
+ i2c_abort_asynch(obj);
+ i2c_data[index].event = I2C_EVENT_ERROR;
+ ((void (*)())i2c_data[index].async_callback)();
+}
+
+/* TX handler */
+static void i2c0_tx_irq(void)
+{
+ i2c_tx_irq(INTIICTEI0_IRQn, 0);
+}
+
+static void i2c1_tx_irq(void)
+{
+ i2c_tx_irq(INTIICTEI1_IRQn, 1);
+}
+
+static void i2c2_tx_irq(void)
+{
+ i2c_tx_irq(INTIICTEI2_IRQn, 2);
+}
+
+static void i2c3_tx_irq(void)
+{
+ i2c_tx_irq(INTIICTEI3_IRQn, 3);
+}
+
+/* RX handler */
+static void i2c0_rx_irq(void)
+{
+ i2c_rx_irq(INTIICRI0_IRQn, 0);
+}
+
+static void i2c1_rx_irq(void)
+{
+ i2c_rx_irq(INTIICRI1_IRQn, 1);
+}
+
+static void i2c2_rx_irq(void)
+{
+ i2c_rx_irq(INTIICRI2_IRQn, 2);
+}
+
+static void i2c3_rx_irq(void)
+{
+ i2c_rx_irq(INTIICRI3_IRQn, 3);
+}
+
+/* Arbitration Lost handler */
+static void i2c0_al_irq(void)
+{
+ i2c_err_irq(INTIICALI0_IRQn, 0);
+}
+
+static void i2c1_al_irq(void)
+{
+ i2c_err_irq(INTIICALI1_IRQn, 1);
+}
+
+static void i2c2_al_irq(void)
+{
+ i2c_err_irq(INTIICALI2_IRQn, 2);
+}
+
+static void i2c3_al_irq(void)
+{
+ i2c_err_irq(INTIICALI3_IRQn, 3);
+}
+
+/* Timeout handler */
+static void i2c0_to_irq(void)
+{
+ i2c_err_irq(INTIICTMOI0_IRQn, 0);
+}
+
+static void i2c1_to_irq(void)
+{
+ i2c_err_irq(INTIICTMOI1_IRQn, 1);
+}
+
+static void i2c2_to_irq(void)
+{
+ i2c_err_irq(INTIICTMOI2_IRQn, 2);
+}
+
+static void i2c3_to_irq(void)
+{
+ i2c_err_irq(INTIICTMOI3_IRQn, 3);
+}
+
+static void i2c_irqs_set(i2c_t *obj, uint32_t enable)
+{
+ int i;
+ const IRQn_Type *irqTable = irq_set_tbl[obj->i2c.i2c];
+ const IRQHandler *handlerTable = hander_set_tbl[obj->i2c.i2c];
+ for (i = 0; i < IRQ_NUM; ++i) {
+ if (enable) {
+ InterruptHandlerRegister(irqTable[i], handlerTable[i]);
+ GIC_SetPriority(irqTable[i], 5);
+ GIC_EnableIRQ(irqTable[i]);
+ } else {
+ GIC_DisableIRQ(irqTable[i]);
+ }
+ }
+ REG(IER.UINT8[0]) = enable ? 0x63 : 0x00;
+}
+
+/******************************************************************************
+ * ASYNCHRONOUS HAL
+ ******************************************************************************/
+
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ MBED_ASSERT(obj);
+ MBED_ASSERT(tx ? tx_length : 1);
+ MBED_ASSERT(rx ? rx_length : 1);
+ MBED_ASSERT((REG(SER.UINT32) & SER_SAR0E) == 0); /* Slave mode */
+
+ obj->tx_buff.buffer = (void *)tx;
+ obj->tx_buff.length = tx_length;
+ obj->tx_buff.pos = 0;
+ obj->tx_buff.width = 8;
+ obj->rx_buff.buffer = rx;
+ obj->rx_buff.length = rx_length;
+ obj->rx_buff.pos = SIZE_MAX;
+ obj->rx_buff.width = 8;
+ i2c_data[obj->i2c.i2c].async_obj = obj;
+ i2c_data[obj->i2c.i2c].async_callback = handler;
+ i2c_data[obj->i2c.i2c].event = 0;
+ i2c_data[obj->i2c.i2c].shouldStop = stop;
+ i2c_data[obj->i2c.i2c].address = address;
+ i2c_irqs_set(obj, 1);
+
+ /* There is a STOP condition for last processing */
+ if (obj->i2c.last_stop_flag != 0) {
+ if (i2c_start(obj) != 0) {
+ i2c_set_err_noslave(obj);
+ i2c_data[obj->i2c.i2c].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
+ i2c_abort_asynch(obj);
+ ((void (*)())handler)();
+ return;
+ }
+ }
+ obj->i2c.last_stop_flag = stop;
+
+ if (rx_length && tx_length == 0) {
+ /* Ready to read */
+ i2c_set_MR3_ACK(obj);
+
+ /* Disable INTRIICTEI */
+ REG(IER.UINT8[0]) &= ~(1 << 6);
+
+ address |= 0x01;
+ }
+ /* Send Slave address */
+ if (i2c_do_write(obj, address) != 0) {
+ i2c_set_err_noslave(obj);
+ i2c_data[obj->i2c.i2c].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
+ i2c_abort_asynch(obj);
+ ((void (*)())handler)();
+ return;
+ }
+}
+
+uint32_t i2c_irq_handler_asynch(i2c_t *obj)
+{
+ return i2c_data[obj->i2c.i2c].event;
+}
+
+uint8_t i2c_active(i2c_t *obj)
+{
+ return i2c_data[obj->i2c.i2c].async_obj != NULL;
+}
+
+void i2c_abort_asynch(i2c_t *obj)
+{
+ i2c_data[obj->i2c.i2c].async_obj = NULL;
+ i2c_irqs_set(obj, 0);
+ i2c_reg_reset(obj);
+}
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/objects.h Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include <stdint.h>
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "gpio_object.h"
+#include "rspi_iodefine.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct i2c_s {
+ uint32_t i2c;
+ uint32_t dummy;
+ uint8_t pclk_bit;
+ uint8_t width_low;
+ uint8_t width_hi;
+ int bbsy_wait_cnt;
+ int last_stop_flag;
+};
+
+struct spi_s {
+ struct st_rspi *spi;
+ uint32_t bits;
+ int index;
+};
+
+struct gpio_irq_s {
+ uint32_t port;
+ uint32_t pin;
+ uint32_t ch;
+ uint8_t int_enable;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_out;
+ __I uint32_t *reg_in;
+ PortName port;
+ uint32_t mask;
+};
+
+struct serial_s {
+ struct st_scif *uart;
+ int index;
+};
+
+struct pwmout_s {
+ uint32_t ch;
+ PWMName pwm;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct can_s {
+ uint32_t ch;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,173 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "gpio_addrdefine.h"
+
+PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */
+
+typedef struct {
+ PinName pin;
+ int function;
+ int pm;
+} PinFunc;
+
+static const PinFunc PIPC_0_tbl[] = {
+// pin func pm
+ {P4_0 , 2 , -1}, /* TIOC0A */
+ {P5_0 , 6 , -1}, /* TIOC0A */
+ {P7_0 , 7 , -1}, /* TIOC0A */
+ {P10_4 , 2 , -1}, /* TIOC0A */
+ {P4_1 , 2 , -1}, /* TIOC0B */
+ {P5_1 , 6 , -1}, /* TIOC0B */
+ {P7_1 , 7 , -1}, /* TIOC0B */
+ {P10_5 , 2 , -1}, /* TIOC0B */
+ {P4_2 , 2 , -1}, /* TIOC0C */
+ {P5_5 , 6 , -1}, /* TIOC0C */
+ {P7_2 , 7 , -1}, /* TIOC0C */
+ {P10_6 , 2 , -1}, /* TIOC0C */
+ {P4_3 , 2 , -1}, /* TIOC0D */
+ {P5_7 , 6 , -1}, /* TIOC0D */
+ {P7_3 , 7 , -1}, /* TIOC0D */
+ {P10_7 , 2 , -1}, /* TIOC0D */
+ {P2_11 , 5 , -1}, /* TIOC1A */
+ {P6_0 , 5 , -1}, /* TIOC1A */
+ {P7_4 , 7 , -1}, /* TIOC1A */
+ {P8_8 , 5 , -1}, /* TIOC1A */
+ {P9_7 , 4 , -1}, /* TIOC1A */
+ {P10_8 , 2 , -1}, /* TIOC1A */
+ {P2_12 , 8 , -1}, /* TIOC1B */
+ {P5_2 , 6 , -1}, /* TIOC1B */
+ {P6_1 , 5 , -1}, /* TIOC1B */
+ {P7_5 , 7 , -1}, /* TIOC1B */
+ {P8_9 , 5 , -1}, /* TIOC1B */
+ {P10_9 , 2 , -1}, /* TIOC1B */
+ {P2_1 , 6 , -1}, /* TIOC2A */
+ {P6_2 , 6 , -1}, /* TIOC2A */
+ {P7_6 , 7 , -1}, /* TIOC2A */
+ {P8_14 , 4 , -1}, /* TIOC2A */
+ {P10_10 , 2 , -1}, /* TIOC2A */
+ {P2_2 , 6 , -1}, /* TIOC2B */
+ {P6_3 , 6 , -1}, /* TIOC2B */
+ {P7_7 , 7 , -1}, /* TIOC2B */
+ {P8_15 , 4 , -1}, /* TIOC2B */
+ {P10_11 , 2 , -1}, /* TIOC2B */
+ {P10_11 , 2 , -1}, /* TIOC2B */
+ {P3_4 , 6 , -1}, /* TIOC3A */
+ {P7_8 , 7 , -1}, /* TIOC3A */
+ {P8_10 , 4 , -1}, /* TIOC3A */
+ {P3_5 , 6 , -1}, /* TIOC3B */
+ {P7_9 , 7 , -1}, /* TIOC3B */
+ {P8_11 , 4 , -1}, /* TIOC3B */
+ {P3_6 , 6 , -1}, /* TIOC3C */
+ {P5_3 , 6 , -1}, /* TIOC3C */
+ {P7_10 , 7 , -1}, /* TIOC3C */
+ {P8_12 , 4 , -1}, /* TIOC3C */
+ {P3_7 , 6 , -1}, /* TIOC3D */
+ {P5_4 , 6 , -1}, /* TIOC3D */
+ {P7_11 , 7 , -1}, /* TIOC3D */
+ {P8_13 , 4 , -1}, /* TIOC3D */
+ {P3_8 , 6 , -1}, /* TIOC4A */
+ {P4_4 , 3 , -1}, /* TIOC4A */
+ {P7_12 , 7 , -1}, /* TIOC4A */
+ {P11_0 , 2 , -1}, /* TIOC4A */
+ {P3_9 , 6 , -1}, /* TIOC4B */
+ {P4_5 , 3 , -1}, /* TIOC4B */
+ {P7_13 , 7 , -1}, /* TIOC4B */
+ {P11_1 , 2 , -1}, /* TIOC4B */
+ {P3_10 , 6 , -1}, /* TIOC4C */
+ {P4_6 , 3 , -1}, /* TIOC4C */
+ {P7_14 , 7 , -1}, /* TIOC4C */
+ {P11_2 , 2 , -1}, /* TIOC4C */
+ {P3_11 , 6 , -1}, /* TIOC4D */
+ {P4_7 , 3 , -1}, /* TIOC4D */
+ {P7_15 , 7 , -1}, /* TIOC4D */
+ {P11_3 , 2 , -1}, /* TIOC4D */
+ {P5_7 , 1 , 1 }, /* TXOUT0M */
+ {P5_6 , 1 , 1 }, /* TXOUT0P */
+ {P5_5 , 1 , 1 }, /* TXOUT1M */
+ {P5_4 , 1 , 1 }, /* TXOUT1P */
+ {P5_3 , 1 , 1 }, /* TXOUT2M */
+ {P5_2 , 1 , 1 }, /* TXOUT2P */
+ {P5_1 , 1 , 1 }, /* TXCLKOUTM */
+ {P5_0 , 1 , 1 }, /* TXCLKOUTP */
+ {P2_11 , 4 , 0 }, /* SSITxD0 */
+ {P4_7 , 5 , 0 }, /* SSITxD0 */
+ {P7_4 , 6 , 0 }, /* SSITxD1 */
+ {P10_15 , 2 , 0 }, /* SSITxD1 */
+ {P4_15 , 6 , 0 }, /* SSITxD3 */
+ {P7_11 , 2 , 0 }, /* SSITxD3 */
+ {P2_7 , 4 , 0 }, /* SSITxD5 */
+ {P4_11 , 5 , 0 }, /* SSITxD5 */
+ {P8_10 , 8 , 0 }, /* SSITxD5 */
+ {P3_7 , 8 , 0 }, /* WDTOVF */
+ {NC , 0 , -1}
+};
+
+void pin_function(PinName pin, int function) {
+ if (pin == (PinName)NC) return;
+
+ int n = pin >> 4;
+ int bitmask = 1<<(pin & 0xf);
+ const PinFunc * Pipc_0_func = PIPC_0_tbl;
+ int pipc_data = 1;
+
+ if (gpio_multi_guard != pin) {
+ if (function == 0) {
+ // means GPIO mode
+ *PMC(n) &= ~bitmask;
+ } else {
+ // alt-function mode
+ --function;
+
+ if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;}
+ if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;}
+ if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;}
+
+ while (Pipc_0_func->pin != NC) {
+ if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) {
+ pipc_data = 0;
+ if (Pipc_0_func->pm == 0) {
+ *PMSR(n) = (bitmask << 16) | 0;
+ } else if (Pipc_0_func->pm == 1) {
+ *PMSR(n) = (bitmask << 16) | bitmask;
+ } else {
+ // Do Nothing
+ }
+ break;
+ }
+ Pipc_0_func++;
+ }
+ if (pipc_data == 1) {
+ *PIPC(n) |= bitmask;
+ } else {
+ *PIPC(n) &= ~bitmask;
+ }
+
+ if (P1_0 <= pin && pin <= P1_7 && function == 0) {
+ *PBDC(n) |= bitmask;
+ }
+ *PMC(n) |= bitmask;
+ }
+ } else {
+ gpio_multi_guard = (PinName)NC;
+ }
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+// if (pin == (PinName)NC) { return; }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/port_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+PinName port_pin(PortName port, int pin_n) {
+ return (PinName)(0);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+ obj->port = port;
+ obj->mask = mask;
+
+ // Do not use masking, because it prevents the use of the unmasked pins
+ // port_reg->FIOMASK = ~mask;
+
+ uint32_t i;
+ // The function is set per pin: reuse gpio logic
+ for (i=0; i<32; i++) {
+ if (obj->mask & (1<<i)) {
+ gpio_set(port_pin(obj->port, i));
+ }
+ }
+
+ port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+ uint32_t i;
+ // The mode is set per pin: reuse pinmap logic
+ for (i=0; i<32; i++) {
+ if (obj->mask & (1<<i)) {
+ pin_mode(port_pin(obj->port, i), mode);
+ }
+ }
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+ switch (dir) {
+ case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+ case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
+ }
+}
+
+void port_write(port_t *obj, int value) {
+ *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj) {
+ return (*obj->reg_in & obj->mask);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,560 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "RZ_A1_Init.h"
+#include "cpg_iodefine.h"
+#include "pwm_iodefine.h"
+#include "gpio_addrdefine.h"
+
+#define MTU2_PWM_NUM 22
+#define MTU2_PWM_SIGNAL 2
+#define MTU2_PWM_OFFSET 0x20
+
+// PORT ID, PWM ID, Pin function
+static const PinMap PinMap_PWM[] = {
+ {P2_1 , MTU2_PWM0_PIN , 6},
+ {P2_11 , MTU2_PWM1_PIN , 5},
+ {P3_8 , MTU2_PWM2_PIN , 6},
+ {P3_10 , MTU2_PWM3_PIN , 6},
+ {P4_0 , MTU2_PWM4_PIN , 2},
+ {P4_4 , MTU2_PWM5_PIN , 3},
+ {P4_6 , MTU2_PWM6_PIN , 3},
+ {P5_0 , MTU2_PWM7_PIN , 6},
+ {P5_3 , MTU2_PWM8_PIN , 6},
+ {P5_5 , MTU2_PWM9_PIN , 6},
+ {P7_2 , MTU2_PWM10_PIN , 7},
+ {P7_4 , MTU2_PWM11_PIN , 7},
+ {P7_6 , MTU2_PWM12_PIN , 7},
+ {P7_10 , MTU2_PWM13_PIN , 7},
+ {P7_12 , MTU2_PWM14_PIN , 7},
+ {P7_14 , MTU2_PWM15_PIN , 7},
+ {P8_8 , MTU2_PWM16_PIN , 5},
+ {P8_10 , MTU2_PWM17_PIN , 4},
+ {P8_12 , MTU2_PWM18_PIN , 4},
+ {P8_14 , MTU2_PWM19_PIN , 4},
+ {P11_0 , MTU2_PWM20_PIN , 2},
+ {P11_2 , MTU2_PWM21_PIN , 2},
+ {P4_4 , PWM0_PIN , 4},
+ {P3_2 , PWM1_PIN , 7},
+ {P4_6 , PWM2_PIN , 4},
+ {P4_7 , PWM3_PIN , 4},
+ {P8_14 , PWM4_PIN , 6},
+ {P8_15 , PWM5_PIN , 6},
+ {P8_13 , PWM6_PIN , 6},
+ {P8_11 , PWM7_PIN , 6},
+ {P8_8 , PWM8_PIN , 6},
+ {P10_0 , PWM9_PIN , 3},
+ {P8_12 , PWM10_PIN , 6},
+ {P8_9 , PWM11_PIN , 6},
+ {P8_10 , PWM12_PIN , 6},
+ {P4_5 , PWM13_PIN , 4},
+ {NC , NC , 0}
+};
+
+static const PWMType PORT[] = {
+ PWM2E, // PWM0_PIN
+ PWM2C, // PWM1_PIN
+ PWM2G, // PWM2_PIN
+ PWM2H, // PWM3_PIN
+ PWM1G, // PWM4_PIN
+ PWM1H, // PWM5_PIN
+ PWM1F, // PWM6_PIN
+ PWM1D, // PWM7_PIN
+ PWM1A, // PWM8_PIN
+ PWM2A, // PWM9_PIN
+ PWM1E, // PWM10_PIN
+ PWM1B, // PWM11_PIN
+ PWM1C, // PWM12_PIN
+ PWM2F, // PWM13_PIN
+};
+
+static const MTU2_PWMType MTU2_PORT[] = {
+ TIOC2A, // MTU2_PWM0_PIN
+ TIOC1A, // MTU2_PWM1_PIN
+ TIOC4A, // MTU2_PWM2_PIN
+ TIOC4C, // MTU2_PWM3_PIN
+ TIOC0A, // MTU2_PWM4_PIN
+ TIOC4A, // MTU2_PWM5_PIN
+ TIOC4C, // MTU2_PWM6_PIN
+ TIOC0A, // MTU2_PWM7_PIN
+ TIOC3C, // MTU2_PWM8_PIN
+ TIOC0C, // MTU2_PWM9_PIN
+ TIOC0C, // MTU2_PWM10_PIN
+ TIOC1A, // MTU2_PWM11_PIN
+ TIOC2A, // MTU2_PWM12_PIN
+ TIOC3C, // MTU2_PWM13_PIN
+ TIOC4A, // MTU2_PWM14_PIN
+ TIOC4C, // MTU2_PWM15_PIN
+ TIOC1A, // MTU2_PWM16_PIN
+ TIOC3A, // MTU2_PWM17_PIN
+ TIOC3C, // MTU2_PWM18_PIN
+ TIOC2A, // MTU2_PWM19_PIN
+ TIOC4A, // MTU2_PWM20_PIN
+ TIOC4C, // MTU2_PWM21_PIN
+};
+
+static __IO uint16_t *PWM_MATCH[] = {
+ &PWMPWBFR_2E, // PWM0_PIN
+ &PWMPWBFR_2C, // PWM1_PIN
+ &PWMPWBFR_2G, // PWM2_PIN
+ &PWMPWBFR_2G, // PWM3_PIN
+ &PWMPWBFR_1G, // PWM4_PIN
+ &PWMPWBFR_1G, // PWM5_PIN
+ &PWMPWBFR_1E, // PWM6_PIN
+ &PWMPWBFR_1C, // PWM7_PIN
+ &PWMPWBFR_1A, // PWM8_PIN
+ &PWMPWBFR_2A, // PWM9_PIN
+ &PWMPWBFR_1E, // PWM10_PIN
+ &PWMPWBFR_1A, // PWM11_PIN
+ &PWMPWBFR_1C, // PWM12_PIN
+ &PWMPWBFR_2E, // PWM13_PIN
+};
+
+static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = {
+ { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM0_PIN
+ { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM1_PIN
+ { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM2_PIN
+ { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM3_PIN
+ { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM4_PIN
+ { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM5_PIN
+ { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM6_PIN
+ { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM7_PIN
+ { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM8_PIN
+ { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM9_PIN
+ { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM10_PIN
+ { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM11_PIN
+ { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM12_PIN
+ { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM13_PIN
+ { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM14_PIN
+ { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM15_PIN
+ { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM16_PIN
+ { &MTU2TGRA_3, &MTU2TGRB_3 }, // MTU2_PWM17_PIN
+ { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM18_PIN
+ { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM19_PIN
+ { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM20_PIN
+ { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM21_PIN
+};
+
+static __IO uint8_t *TCR_MATCH[] = {
+ &MTU2TCR_0,
+ &MTU2TCR_1,
+ &MTU2TCR_2,
+ &MTU2TCR_3,
+ &MTU2TCR_4,
+};
+
+static __IO uint8_t *TIORH_MATCH[] = {
+ &MTU2TIORH_0,
+ &MTU2TIOR_1,
+ &MTU2TIOR_2,
+ &MTU2TIORH_3,
+ &MTU2TIORH_4,
+};
+
+static __IO uint8_t *TIORL_MATCH[] = {
+ &MTU2TIORL_0,
+ NULL,
+ NULL,
+ &MTU2TIORL_3,
+ &MTU2TIORL_4,
+};
+
+static __IO uint16_t *TGRA_MATCH[] = {
+ &MTU2TGRA_0,
+ &MTU2TGRA_1,
+ &MTU2TGRA_2,
+ &MTU2TGRA_3,
+ &MTU2TGRA_4,
+};
+
+static __IO uint16_t *TGRC_MATCH[] = {
+ &MTU2TGRC_0,
+ NULL,
+ NULL,
+ &MTU2TGRC_3,
+ &MTU2TGRC_4,
+};
+
+static __IO uint8_t *TMDR_MATCH[] = {
+ &MTU2TMDR_0,
+ &MTU2TMDR_1,
+ &MTU2TMDR_2,
+ &MTU2TMDR_3,
+ &MTU2TMDR_4,
+};
+
+static int MAX_PERIOD[] = {
+ 125000,
+ 503000,
+ 2000000,
+ 2000000,
+ 2000000,
+};
+
+typedef enum {
+ MTU2_PULSE = 0,
+ MTU2_PERIOD
+} MTU2Signal;
+
+static uint16_t init_period_ch1 = 0;
+static uint16_t init_period_ch2 = 0;
+static uint16_t init_mtu2_period_ch[5] = {0};
+static int32_t period_ch1 = 1;
+static int32_t period_ch2 = 1;
+static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1};
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+ // determine the channel
+ PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+ MBED_ASSERT(pwm != (PWMName)NC);
+
+ if (pwm >= MTU2_PWM_OFFSET) {
+ /* PWM by MTU2 */
+ int tmp_pwm;
+
+ // power on
+ CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP33);
+
+ obj->pwm = pwm;
+ tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
+ if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) {
+ obj->ch = 4;
+ MTU2TOER |= 0x36;
+ } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) {
+ obj->ch = 3;
+ MTU2TOER |= 0x09;
+ } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) {
+ obj->ch = 2;
+ } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) {
+ obj->ch = 1;
+ } else {
+ obj->ch = 0;
+ }
+ // Wire pinout
+ pinmap_pinout(pin, PinMap_PWM);
+
+ int bitmask = 1 << (pin & 0xf);
+
+ *PMSR(PINGROUP(pin)) = (bitmask << 16) | 0;
+
+ // default duty 0.0f
+ pwmout_write(obj, 0);
+ if (init_mtu2_period_ch[obj->ch] == 0) {
+ // default period 1ms
+ pwmout_period_us(obj, 1000);
+ init_mtu2_period_ch[obj->ch] = 1;
+ }
+ } else {
+ /* PWM */
+ // power on
+ CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30);
+
+ obj->pwm = pwm;
+ if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) {
+ obj->ch = 2;
+ PWMPWPR_2_BYTE_L = 0x00;
+ } else {
+ obj->ch = 1;
+ PWMPWPR_1_BYTE_L = 0x00;
+ }
+
+ // Wire pinout
+ pinmap_pinout(pin, PinMap_PWM);
+
+ // default to 491us: standard for servos, and fine for e.g. brightness control
+ pwmout_write(obj, 0);
+ if ((obj->ch == 2) && (init_period_ch2 == 0)) {
+ pwmout_period_us(obj, 491);
+ init_period_ch2 = 1;
+ }
+ if ((obj->ch == 1) && (init_period_ch1 == 0)) {
+ pwmout_period_us(obj, 491);
+ init_period_ch1 = 1;
+ }
+ }
+}
+
+void pwmout_free(pwmout_t* obj) {
+ pwmout_write(obj, 0);
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+ uint32_t wk_cycle;
+ uint16_t v;
+
+ if (obj->pwm >= MTU2_PWM_OFFSET) {
+ /* PWM by MTU2 */
+ int tmp_pwm;
+
+ if (value < 0.0f) {
+ value = 0.0f;
+ } else if (value > 1.0f) {
+ value = 1.0f;
+ } else {
+ // Do Nothing
+ }
+ tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
+ wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
+ // set channel match to percentage
+ *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value);
+ } else {
+ /* PWM */
+ if (value < 0.0f) {
+ value = 0.0f;
+ } else if (value > 1.0f) {
+ value = 1.0f;
+ } else {
+ // Do Nothing
+ }
+
+ if (obj->ch == 2) {
+ wk_cycle = PWMPWCYR_2 & 0x03ff;
+ } else {
+ wk_cycle = PWMPWCYR_1 & 0x03ff;
+ }
+
+ // set channel match to percentage
+ v = (uint16_t)((float)wk_cycle * value);
+ *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12));
+ }
+}
+
+float pwmout_read(pwmout_t* obj) {
+ uint32_t wk_cycle;
+ float value;
+
+ if (obj->pwm >= MTU2_PWM_OFFSET) {
+ /* PWM by MTU2 */
+ uint32_t wk_pulse;
+ int tmp_pwm;
+
+ tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
+ wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
+ wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff;
+ value = ((float)wk_pulse / (float)wk_cycle);
+ } else {
+ /* PWM */
+ if (obj->ch == 2) {
+ wk_cycle = PWMPWCYR_2 & 0x03ff;
+ } else {
+ wk_cycle = PWMPWCYR_1 & 0x03ff;
+ }
+ value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle);
+ }
+
+ return (value > 1.0f) ? (1.0f) : (value);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+ pwmout_period_us(obj, ms * 1000);
+}
+
+static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
+ uint16_t wk_pwmpbfr;
+ float value;
+ uint16_t v;
+
+ wk_pwmpbfr = *p_pwmpbfr;
+ value = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle);
+ v = (uint16_t)((float)new_cycle * value);
+ *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000));
+}
+
+static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
+ uint16_t wk_pwmpbfr;
+ float value;
+
+ wk_pwmpbfr = *p_pwmpbfr;
+ value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle);
+ *p_pwmpbfr = (uint16_t)((float)new_cycle * value);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+ uint64_t wk_cycle_mtu2;
+ uint32_t pclk_base;
+ uint32_t wk_cycle;
+ uint32_t wk_cks = 0;
+ uint16_t wk_last_cycle;
+ int max_us = 0;
+
+ if (obj->pwm >= MTU2_PWM_OFFSET) {
+ /* PWM by MTU2 */
+ int tmp_pwm;
+ uint8_t tmp_tcr_up;
+ uint8_t tmp_tstr_sp;
+ uint8_t tmp_tstr_st;
+
+ max_us = MAX_PERIOD[obj->ch];
+ if (us > max_us) {
+ us = max_us;
+ } else if (us < 1) {
+ us = 1;
+ } else {
+ // Do Nothing
+ }
+
+ if (RZ_A1_IsClockMode0() == false) {
+ pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK;
+ } else {
+ pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK;
+ }
+
+ wk_cycle_mtu2 = (uint64_t)pclk_base * us;
+ while (wk_cycle_mtu2 >= 65535000000) {
+ if ((obj->ch == 1) && (wk_cks == 3)) {
+ wk_cks+=2;
+ } else if ((obj->ch == 2) && (wk_cks == 3)) {
+ wk_cycle_mtu2 >>= 2;
+ wk_cks+=3;
+ }
+ wk_cycle_mtu2 >>= 2;
+ wk_cks++;
+ }
+ wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000);
+
+ tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
+ if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) {
+ tmp_tcr_up = 0xC0;
+ } else {
+ tmp_tcr_up = 0x40;
+ }
+ if ((obj->ch == 4) || (obj->ch == 3)) {
+ tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3)));
+ tmp_tstr_st = (1 << (obj->ch + 3));
+ } else {
+ tmp_tstr_sp = ~(0x38 | (1 << obj->ch));
+ tmp_tstr_st = (1 << obj->ch);
+ }
+ // Counter Stop
+ MTU2TSTR &= tmp_tstr_sp;
+ wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
+ *TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks;
+ *TIORH_MATCH[obj->ch] = 0x21;
+ if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
+ *TIORL_MATCH[obj->ch] = 0x21;
+ }
+ *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period
+
+ // Set duty again(TGRA)
+ set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle);
+ if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
+ // Set duty again(TGRC)
+ set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle);
+ }
+ *TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1
+
+ // Counter Start
+ MTU2TSTR |= tmp_tstr_st;
+ // Save for future use
+ mtu2_period_ch[obj->ch] = us;
+ } else {
+ /* PWM */
+ if (us > 491) {
+ us = 491;
+ } else if (us < 1) {
+ us = 1;
+ } else {
+ // Do Nothing
+ }
+
+ if (RZ_A1_IsClockMode0() == false) {
+ pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000;
+ } else {
+ pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000;
+ }
+
+ wk_cycle = pclk_base * us;
+ while (wk_cycle >= 102350) {
+ wk_cycle >>= 1;
+ wk_cks++;
+ }
+ wk_cycle = (wk_cycle + 50) / 100;
+
+ if (obj->ch == 2) {
+ wk_last_cycle = PWMPWCYR_2 & 0x03ff;
+ PWMPWCR_2_BYTE_L = 0xc0 | wk_cks;
+ PWMPWCYR_2 = (uint16_t)wk_cycle;
+
+ // Set duty again
+ set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle);
+ set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle);
+ set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle);
+ set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle);
+
+ // Counter Start
+ PWMPWCR_2_BYTE_L |= 0x08;
+
+ // Save for future use
+ period_ch2 = us;
+ } else {
+ wk_last_cycle = PWMPWCYR_1 & 0x03ff;
+ PWMPWCR_1_BYTE_L = 0xc0 | wk_cks;
+ PWMPWCYR_1 = (uint16_t)wk_cycle;
+
+ // Set duty again
+ set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle);
+ set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle);
+ set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle);
+ set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle);
+
+ // Counter Start
+ PWMPWCR_1_BYTE_L |= 0x08;
+
+ // Save for future use
+ period_ch1 = us;
+ }
+ }
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+ float value = 0;
+
+ if (obj->pwm >= MTU2_PWM_OFFSET) {
+ /* PWM by MTU2 */
+ if (mtu2_period_ch[obj->ch] != 0) {
+ value = (float)us / (float)mtu2_period_ch[obj->ch];
+ }
+ } else {
+ /* PWM */
+ if (obj->ch == 2) {
+ if (period_ch2 != 0) {
+ value = (float)us / (float)period_ch2;
+ }
+ } else {
+ if (period_ch1 != 0) {
+ value = (float)us / (float)period_ch1;
+ }
+ }
+ }
+ pwmout_write(obj, value);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,375 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_assert.h"
+#include "device.h"
+
+#if DEVICE_RTC
+
+#include "rtc_api.h"
+#include "rtc_iodefine.h"
+
+
+#define RCR1_VAL_ON (0x08u) // AIE = 1
+#define RCR1_VAL_OFF (0x00u)
+#define RCR2_VAL_ALLSTOP (0x00u)
+#define RCR2_VAL_START (0x01u) // START = 1
+#define RCR2_VAL_RESET (0x02u) // RESET = 1
+#define RCR3_VAL (0x00u)
+#define RCR5_VAL_EXTAL (0x01u) // RCKSEL = connect EXTAL
+#define RCR5_VAL_RTCX1 (0x00u) // RCKSEL = disconnect EXTAL
+#define RFRH_VAL_13333 (0x8003u) // 13.3333MHz (= 64Hz * 0x32DCD)
+#define RFRL_VAL_13333 (0x2DCDu) //
+#define RFRH_VAL_MAX (0x0007u) // MAX value (= 128Hz * 0x7FFFF)
+#define RFRL_VAL_MAX (0xFFFFu) //
+
+#define MASK_00_03_POS (0x000Fu)
+#define MASK_04_07_POS (0x00F0u)
+#define MASK_08_11_POS (0x0F00u)
+#define MASK_12_15_POS (0xF000u)
+#define MASK_16_20_POS (0x000F0000u)
+#define SHIFT_1_HBYTE (4u)
+#define SHIFT_2_HBYTE (8u)
+#define SHIFT_3_HBYTE (12u)
+#define SHIFT_1BYTE (8u)
+#define SHIFT_2BYTE (16u)
+
+#define TIME_ERROR_VAL (0xFFFFFFFFu)
+
+static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val);
+static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val);
+static uint8_t rtc_hex8_to_dec(uint8_t hex_val);
+static uint16_t rtc_hex16_to_dec(uint16_t hex_val);
+
+
+/*
+ * Setup the RTC based on a time structure.
+ * The rtc_init function should be executed first.
+ * [in]
+ * None.
+ * [out]
+ * None.
+ */
+void rtc_init(void) {
+ volatile uint8_t dummy_read;
+
+ // Set control register
+ RTC.RCR2 = RCR2_VAL_ALLSTOP;
+ RTC.RCR1 = RCR1_VAL_ON;
+ RTC.RCR3 = RCR3_VAL;
+ RTC.RCR5 = RCR5_VAL_EXTAL;
+ RTC.RFRH = RFRH_VAL_13333;
+ RTC.RFRL = RFRL_VAL_13333;
+
+ // Dummy read
+ dummy_read = RTC.RCR2;
+ dummy_read = RTC.RCR2;
+
+ RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1
+
+ // Dummy read
+ dummy_read = RTC.RCR2;
+ dummy_read = RTC.RCR2;
+
+ // Set timer and alarm. Default value :01-01-1970 00:00:00
+ RTC.RSECCNT = 0;
+ RTC.RMINCNT = 0;
+ RTC.RHRCNT = 0;
+ RTC.RWKCNT = 0;
+ RTC.RDAYCNT = 1;
+ RTC.RMONCNT = 1;
+ RTC.RYRCNT = 0x1970;
+ RTC.RSECAR = 0;
+ RTC.RMINAR = 0;
+ RTC.RHRAR = 0;
+ RTC.RWKAR = 0;
+ RTC.RDAYAR = 1;
+ RTC.RMONAR = 1;
+ RTC.RYRAR = 0x1970;
+
+ // Dummy read
+ dummy_read = RTC.RYRCNT;
+ dummy_read = RTC.RYRCNT;
+
+}
+
+
+/*
+ * Release the RTC based on a time structure.
+ * [in]
+ * None.
+ * [out]
+ * None.
+ */
+void rtc_free(void) {
+ volatile uint8_t dummy_read;
+
+ // Set control register
+ RTC.RCR2 = RCR2_VAL_ALLSTOP;
+ RTC.RCR1 = RCR1_VAL_OFF;
+ RTC.RCR3 = RCR3_VAL;
+ RTC.RCR5 = RCR5_VAL_RTCX1;
+ RTC.RFRH = RFRH_VAL_MAX;
+ RTC.RFRL = RFRL_VAL_MAX;
+
+ // Dummy read
+ dummy_read = RTC.RCR2;
+ dummy_read = RTC.RCR2;
+ RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1
+
+ // Dummy read
+ dummy_read = RTC.RCR2;
+ dummy_read = RTC.RCR2;
+
+ // Set timer and alarm. Default value :01-01-1970 00:00:00
+ RTC.RSECCNT = 0;
+ RTC.RMINCNT = 0;
+ RTC.RHRCNT = 0;
+ RTC.RWKCNT = 0;
+ RTC.RDAYCNT = 1;
+ RTC.RMONCNT = 1;
+ RTC.RYRCNT = 0x1970;
+ RTC.RSECAR = 0;
+ RTC.RMINAR = 0;
+ RTC.RHRAR = 0;
+ RTC.RWKAR = 0;
+ RTC.RDAYAR = 1;
+ RTC.RMONAR = 1;
+ RTC.RYRAR = 0x1970;
+
+ // Dummy read
+ dummy_read = RTC.RYRCNT;
+ dummy_read = RTC.RYRCNT;
+
+}
+
+
+/*
+ * Check the RTC has been enabled.
+ * Clock Control Register RTC.RCR1(bit3): 0 = Disabled, 1 = Enabled.
+ * [in]
+ * None.
+ * [out]
+ * 0:Disabled, 1:Enabled.
+ */
+int rtc_isenabled(void) {
+ int ret_val = 0;
+
+ if ((RTC.RCR1 & RCR1_VAL_ON) != 0) { // RTC ON ?
+ ret_val = 1;
+ }
+
+ return ret_val;
+}
+
+
+/*
+ * RTC read function.
+ * [in]
+ * None.
+ * [out]
+ * UNIX timestamp value.
+ */
+time_t rtc_read(void) {
+
+ struct tm timeinfo;
+ int err = 0;
+ uint8_t tmp_regdata;
+ time_t t;
+
+ if (rtc_isenabled() != 0) {
+ RTC.RCR1 &= ~0x10u; // CIE = 0
+ do {
+ // before reading process
+ tmp_regdata = RTC.RCR1;
+ tmp_regdata &= ~0x80u; // CF = 0
+ tmp_regdata |= 0x01u; // AF = 1
+ RTC.RCR1 = tmp_regdata;
+
+ // Read RTC register
+ err = rtc_dec8_to_hex(RTC.RSECCNT , 0 , &timeinfo.tm_sec);
+ err += rtc_dec8_to_hex(RTC.RMINCNT , 0 , &timeinfo.tm_min);
+ err += rtc_dec8_to_hex(RTC.RHRCNT , 0 , &timeinfo.tm_hour);
+ err += rtc_dec8_to_hex(RTC.RDAYCNT , 0 , &timeinfo.tm_mday);
+ err += rtc_dec8_to_hex(RTC.RMONCNT , 1 , &timeinfo.tm_mon);
+ err += rtc_dec16_to_hex(RTC.RYRCNT , 1900 , &timeinfo.tm_year);
+ } while ((RTC.RCR1 & 0x80u) != 0);
+ } else {
+ err = 1;
+ }
+
+ if (err == 0) {
+ // Convert to timestamp
+ t = mktime(&timeinfo);
+ } else {
+ // Error
+ t = TIME_ERROR_VAL;
+ }
+
+ return t;
+}
+
+/*
+ * Dec(8bit) to Hex function for RTC.
+ * [in]
+ * dec_val:Decimal value (from 0x00 to 0x99).
+ * offset:Subtract offset from dec_val.
+ * hex_val:Pointer of output hexadecimal value.
+ * [out]
+ * 0:Success
+ * 1:Error
+ */
+static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val) {
+ int err = 0;
+ uint8_t ret_val;
+
+ if (hex_val != NULL) {
+ if (((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) ||
+ ((dec_val & MASK_00_03_POS) >= 0x0A)) {
+ err = 1;
+ } else {
+ ret_val = ((dec_val & MASK_04_07_POS) >> SHIFT_1_HBYTE) * 10 +
+ (dec_val & MASK_00_03_POS);
+ if (ret_val < offset) {
+ err = 1;
+ } else {
+ *hex_val = ret_val - offset;
+ }
+ }
+ } else {
+ err = 1;
+ }
+
+ return err;
+}
+
+/*
+ * Dec(16bit) to Hex function for RTC
+ * [in]
+ * dec_val:Decimal value (from 0x0000 to 0x9999).
+ * offset:Subtract offset from dec_val.
+ * hex_val:Pointer of output hexadecimal value.
+ * [out]
+ * 0:Success
+ * 1:Error
+ */
+static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val) {
+ int err = 0;
+ uint16_t ret_val;
+
+ if (hex_val != NULL) {
+ if (((dec_val & MASK_12_15_POS) >= (0x0A << SHIFT_3_HBYTE)) ||
+ ((dec_val & MASK_08_11_POS) >= (0x0A << SHIFT_2_HBYTE)) ||
+ ((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) ||
+ ((dec_val & MASK_00_03_POS) >= 0x0A)) {
+ err = 1;
+ *hex_val = 0;
+ } else {
+ ret_val = (((dec_val & MASK_12_15_POS)) >> SHIFT_3_HBYTE) * 1000 +
+ (((dec_val & MASK_08_11_POS)) >> SHIFT_2_HBYTE) * 100 +
+ (((dec_val & MASK_04_07_POS)) >> SHIFT_1_HBYTE) * 10 +
+ (dec_val & MASK_00_03_POS);
+ if (ret_val < offset) {
+ err = 1;
+ } else {
+ *hex_val = ret_val - offset;
+ }
+ }
+ } else {
+ err = 1;
+ }
+ return err;
+}
+
+/*
+ * RTC write function
+ * [in]
+ * t:UNIX timestamp value
+ * [out]
+ * None.
+ */
+void rtc_write(time_t t) {
+
+ struct tm *timeinfo = localtime(&t);
+ volatile uint16_t dummy_read;
+
+ if (rtc_isenabled() != 0) {
+ RTC.RCR2 = RCR2_VAL_ALLSTOP;
+ dummy_read = (uint16_t)RTC.RCR2;
+ dummy_read = (uint16_t)RTC.RCR2;
+ RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1
+ dummy_read = (uint16_t)RTC.RCR2;
+ dummy_read = (uint16_t)RTC.RCR2;
+
+ RTC.RSECCNT = rtc_hex8_to_dec(timeinfo->tm_sec);
+ RTC.RMINCNT = rtc_hex8_to_dec(timeinfo->tm_min);
+ RTC.RHRCNT = rtc_hex8_to_dec(timeinfo->tm_hour);
+ RTC.RDAYCNT = rtc_hex8_to_dec(timeinfo->tm_mday);
+ RTC.RMONCNT = rtc_hex8_to_dec(timeinfo->tm_mon + 1);
+ RTC.RYRCNT = rtc_hex16_to_dec(timeinfo->tm_year + 1900);
+ dummy_read = (uint16_t)RTC.RYRCNT;
+ dummy_read = (uint16_t)RTC.RYRCNT;
+
+ RTC.RCR2 = RCR2_VAL_START; // START = 1
+
+ dummy_read = (uint16_t)RTC.RCR2;
+ dummy_read = (uint16_t)RTC.RCR2;
+ }
+}
+
+/*
+ * HEX to Dec(8bit) function for RTC.
+ * [in]
+ * hex_val:Hexadecimal value.
+ * [out]
+ * decimal value:From 0x00 to 0x99.
+ */
+static uint8_t rtc_hex8_to_dec(uint8_t hex_val) {
+ uint32_t calc_data;
+
+ calc_data = hex_val / 10 * 0x10;
+ calc_data += hex_val % 10;
+
+ if (calc_data > 0x99) {
+ calc_data = 0;
+ }
+
+ return (uint8_t)calc_data;
+}
+
+/*
+ * HEX to Dec(16bit) function for RTC.
+ * [in]
+ * hex_val:Hexadecimal value.
+ * [out]
+ * decimal value:From 0x0000 to 0x9999.
+ */
+static uint16_t rtc_hex16_to_dec(uint16_t hex_val) {
+ uint32_t calc_data;
+ calc_data = hex_val / 1000 * 0x1000;
+ calc_data += ((hex_val / 100) % 10) * 0x100;
+ calc_data += ((hex_val / 10) % 10) * 0x10;
+ calc_data += hex_val % 10;
+
+ if (calc_data > 0x9999) {
+ calc_data = 0;
+ }
+ return (uint16_t)calc_data;
+
+}
+
+#endif /* DEVICE_RTC */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,943 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include "mbed_assert.h"
+#include <math.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+#include "scif_iodefine.h"
+#include "cpg_iodefine.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+#define PCLK (66666666) // Define the peripheral clock P1 frequency.
+
+#define UART_NUM 8
+#define IRQ_NUM 4
+
+static void uart0_tx_irq(void);
+static void uart1_tx_irq(void);
+static void uart2_tx_irq(void);
+static void uart3_tx_irq(void);
+static void uart4_tx_irq(void);
+static void uart5_tx_irq(void);
+static void uart6_tx_irq(void);
+static void uart7_tx_irq(void);
+static void uart0_rx_irq(void);
+static void uart1_rx_irq(void);
+static void uart2_rx_irq(void);
+static void uart3_rx_irq(void);
+static void uart4_rx_irq(void);
+static void uart5_rx_irq(void);
+static void uart6_rx_irq(void);
+static void uart7_rx_irq(void);
+static void uart0_er_irq(void);
+static void uart1_er_irq(void);
+static void uart2_er_irq(void);
+static void uart3_er_irq(void);
+static void uart4_er_irq(void);
+static void uart5_er_irq(void);
+static void uart6_er_irq(void);
+static void uart7_er_irq(void);
+
+static void serial_put_done(serial_t *obj);
+static uint8_t serial_available_buffer(serial_t *obj);
+static void serial_irq_err_set(serial_t *obj, uint32_t enable);
+
+static const PinMap PinMap_UART_TX[] = {
+ {P2_14 , UART0, 6},
+ {P2_5 , UART1, 6},
+ {P4_12 , UART1, 7},
+ {P6_3 , UART2, 7},
+ {P4_14 , UART2, 7},
+ {P5_3 , UART3, 5},
+ {P8_8 , UART3, 7},
+ {P5_0 , UART4, 5},
+ {P8_14 , UART4, 7},
+ {P8_13 , UART5, 5},
+ {P11_10, UART5, 3},
+ {P6_6 , UART5, 5},
+ {P5_6 , UART6, 5},
+ {P11_1 , UART6, 4},
+ {P7_4 , UART7, 4},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+ {P2_15 , UART0, 6},
+ {P2_6 , UART1, 6},
+ {P4_13 , UART1, 7},
+ {P6_2 , UART2, 7},
+ {P4_15 , UART2, 7},
+ {P5_4 , UART3, 5},
+ {P8_9 , UART3, 7},
+ {P5_1 , UART4, 5},
+ {P8_15 , UART4, 7},
+ {P8_11 , UART5, 5},
+ {P11_11, UART5, 3},
+ {P6_7 , UART5, 5},
+ {P5_7 , UART6, 5},
+ {P11_2 , UART6, 4},
+ {P7_5 , UART7, 4},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_UART_CTS[] = {
+ {P2_3 , UART1, 6},
+ {P11_7 , UART5, 3},
+ {P7_6 , UART7, 4},
+ {NC , NC , 0}
+};
+static const PinMap PinMap_UART_RTS[] = {
+ {P2_7 , UART1, 6},
+ {P11_8 , UART5, 3},
+ {P7_7 , UART7, 4},
+ {NC , NC , 0}
+};
+
+
+
+static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST;
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+struct serial_global_data_s {
+ uint32_t serial_irq_id;
+ gpio_t sw_rts, sw_cts;
+ uint8_t rx_irq_set_flow, rx_irq_set_api;
+ serial_t *tranferring_obj, *receiving_obj;
+ uint32_t async_tx_callback, async_rx_callback;
+ int event, wanted_rx_events;
+};
+
+static struct serial_global_data_s uart_data[UART_NUM];
+
+static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
+ {SCIFRXI0_IRQn, SCIFTXI0_IRQn, SCIFBRI0_IRQn, SCIFERI0_IRQn},
+ {SCIFRXI1_IRQn, SCIFTXI1_IRQn, SCIFBRI1_IRQn, SCIFERI1_IRQn},
+ {SCIFRXI2_IRQn, SCIFTXI2_IRQn, SCIFBRI2_IRQn, SCIFERI2_IRQn},
+ {SCIFRXI3_IRQn, SCIFTXI3_IRQn, SCIFBRI3_IRQn, SCIFERI3_IRQn},
+ {SCIFRXI4_IRQn, SCIFTXI4_IRQn, SCIFBRI4_IRQn, SCIFERI4_IRQn},
+ {SCIFRXI5_IRQn, SCIFTXI5_IRQn, SCIFBRI5_IRQn, SCIFERI5_IRQn},
+ {SCIFRXI6_IRQn, SCIFTXI6_IRQn, SCIFBRI6_IRQn, SCIFERI6_IRQn},
+ {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn}
+};
+
+static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
+ {uart0_rx_irq, uart0_tx_irq, uart0_er_irq, uart0_er_irq},
+ {uart1_rx_irq, uart1_tx_irq, uart1_er_irq, uart1_er_irq},
+ {uart2_rx_irq, uart2_tx_irq, uart2_er_irq, uart2_er_irq},
+ {uart3_rx_irq, uart3_tx_irq, uart3_er_irq, uart3_er_irq},
+ {uart4_rx_irq, uart4_tx_irq, uart4_er_irq, uart4_er_irq},
+ {uart5_rx_irq, uart5_tx_irq, uart5_er_irq, uart5_er_irq},
+ {uart6_rx_irq, uart6_tx_irq, uart6_er_irq, uart6_er_irq},
+ {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq}
+};
+
+static __IO uint16_t *SCSCR_MATCH[] = {
+ &SCSCR_0,
+ &SCSCR_1,
+ &SCSCR_2,
+ &SCSCR_3,
+ &SCSCR_4,
+ &SCSCR_5,
+ &SCSCR_6,
+ &SCSCR_7,
+};
+
+static __IO uint16_t *SCFSR_MATCH[] = {
+ &SCFSR_0,
+ &SCFSR_1,
+ &SCFSR_2,
+ &SCFSR_3,
+ &SCFSR_4,
+ &SCFSR_5,
+ &SCFSR_6,
+ &SCFSR_7,
+};
+
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+ volatile uint8_t dummy ;
+ int is_stdio_uart = 0;
+ // determine the UART to use
+ uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
+ uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
+ uint32_t uart = pinmap_merge(uart_tx, uart_rx);
+
+ MBED_ASSERT((int)uart != NC);
+
+ obj->serial.uart = (struct st_scif *)SCIF[uart];
+ // enable power
+ switch (uart) {
+ case UART0:
+ CPG.STBCR4 &= ~(1 << 7);
+ break;
+ case UART1:
+ CPG.STBCR4 &= ~(1 << 6);
+ break;
+ case UART2:
+ CPG.STBCR4 &= ~(1 << 5);
+ break;
+ case UART3:
+ CPG.STBCR4 &= ~(1 << 4);
+ break;
+ case UART4:
+ CPG.STBCR4 &= ~(1 << 3);
+ break;
+ case UART5:
+ CPG.STBCR4 &= ~(1 << 2);
+ break;
+ case UART6:
+ CPG.STBCR4 &= ~(1 << 1);
+ break;
+ case UART7:
+ CPG.STBCR4 &= ~(1 << 0);
+ break;
+ }
+ dummy = CPG.STBCR4;
+
+ /* ==== SCIF initial setting ==== */
+ /* ---- Serial control register (SCSCR) setting ---- */
+ /* B'00 : Internal CLK */
+ obj->serial.uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */
+
+ /* ---- FIFO control register (SCFCR) setting ---- */
+ /* Transmit FIFO reset & Receive FIFO data register reset */
+ obj->serial.uart->SCFCR = 0x0006;
+
+ /* ---- Serial status register (SCFSR) setting ---- */
+ dummy = obj->serial.uart->SCFSR;
+ obj->serial.uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */
+
+ /* ---- Line status register (SCLSR) setting ---- */
+ /* ORER bit clear */
+ obj->serial.uart->SCLSR = 0;
+
+ /* ---- Serial extension mode register (SCEMR) setting ----
+ b7 BGDM - Baud rate generator double-speed mode : Normal mode
+ b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */
+ obj->serial.uart->SCEMR = 0x0000u;
+
+ /* ---- Bit rate register (SCBRR) setting ---- */
+ serial_baud (obj, 9600);
+ serial_format(obj, 8, ParityNone, 1);
+
+ /* ---- FIFO control register (SCFCR) setting ---- */
+ obj->serial.uart->SCFCR = 0x0030u;
+
+ /* ---- Serial port register (SCSPTR) setting ----
+ b1 SPB2IO - Serial port break output : disabled
+ b0 SPB2DT - Serial port break data : High-level */
+ obj->serial.uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1
+
+ /* ---- Line status register (SCLSR) setting ----
+ b0 ORER - Overrun error detect : clear */
+
+ if (obj->serial.uart->SCLSR & 0x0001) {
+ obj->serial.uart->SCLSR = 0u; // ORER clear
+ }
+
+ // pinout the chosen uart
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+
+ switch (uart) {
+ case UART0:
+ obj->serial.index = 0;
+ break;
+ case UART1:
+ obj->serial.index = 1;
+ break;
+ case UART2:
+ obj->serial.index = 2;
+ break;
+ case UART3:
+ obj->serial.index = 3;
+ break;
+ case UART4:
+ obj->serial.index = 4;
+ break;
+ case UART5:
+ obj->serial.index = 5;
+ break;
+ case UART6:
+ obj->serial.index = 6;
+ break;
+ case UART7:
+ obj->serial.index = 7;
+ break;
+ }
+ uart_data[obj->serial.index].sw_rts.pin = NC;
+ uart_data[obj->serial.index].sw_cts.pin = NC;
+
+ /* ---- Serial control register (SCSCR) setting ---- */
+ /* Setting the TE and RE bits enables the TxD and RxD pins to be used. */
+ obj->serial.uart->SCSCR = 0x0070;
+
+ is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+
+ if (is_stdio_uart) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj) {
+ uart_data[obj->serial.index].serial_irq_id = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+ uint16_t DL;
+
+ obj->serial.uart->SCSMR &= ~0x0003;
+
+ if (baudrate > 32552) {
+ obj->serial.uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1
+ DL = PCLK / (8 * baudrate);
+ if (DL > 0) {
+ DL--;
+ }
+ obj->serial.uart->SCBRR = (uint8_t)DL;
+ } else if (baudrate > 16276) {
+ obj->serial.uart->SCEMR = 0x0080; // BGDM = 1
+ obj->serial.uart->SCBRR = PCLK / (16 * baudrate) - 1;
+ } else if (baudrate > 8138) {
+ obj->serial.uart->SCEMR = 0x0000;
+ obj->serial.uart->SCBRR = PCLK / (32 * baudrate) - 1;
+ } else if (baudrate > 4169) {
+ obj->serial.uart->SCSMR |= 0x0001;
+ obj->serial.uart->SCEMR = 0x0080; // BGDM = 1
+ obj->serial.uart->SCBRR = PCLK / (64 * baudrate) - 1;
+ } else if (baudrate > 2034) {
+ obj->serial.uart->SCSMR |= 0x0001;
+ obj->serial.uart->SCEMR = 0x0000;
+ obj->serial.uart->SCBRR = PCLK / (128 * baudrate) - 1;
+ } else if (baudrate > 1017) {
+ obj->serial.uart->SCSMR |= 0x0002;
+ obj->serial.uart->SCEMR = 0x0080; // BGDM = 1
+ obj->serial.uart->SCBRR = PCLK / (256 * baudrate) - 1;
+ } else if (baudrate > 508) {
+ obj->serial.uart->SCSMR |= 0x0002;
+ obj->serial.uart->SCEMR = 0x0000;
+ obj->serial.uart->SCBRR = PCLK / (512 * baudrate) - 1;
+ } else if (baudrate > 254) {
+ obj->serial.uart->SCSMR |= 0x0003;
+ obj->serial.uart->SCEMR = 0x0080; // BGDM = 1
+ obj->serial.uart->SCBRR = PCLK / (1024 * baudrate) - 1;
+ } else if (baudrate > 127) {
+ obj->serial.uart->SCSMR |= 0x0003;
+ obj->serial.uart->SCEMR = 0x0000;
+ obj->serial.uart->SCBRR = PCLK / (2048 * baudrate) - 1;
+ } else {
+ obj->serial.uart->SCSMR |= 0x0003;
+ obj->serial.uart->SCEMR = 0x0000;
+ obj->serial.uart->SCBRR = 0xFFu;
+ }
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+ int parity_enable;
+ int parity_select;
+
+ MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
+ MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits
+ MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
+ (parity == ParityForced1) || (parity == ParityForced0));
+
+ stop_bits = (stop_bits == 1)? 0:
+ (stop_bits == 2)? 1:
+ 0; // must not to be
+
+ data_bits = (data_bits == 8)? 0:
+ (data_bits == 7)? 1:
+ 0; // must not to be
+
+ switch (parity) {
+ case ParityNone:
+ parity_enable = 0;
+ parity_select = 0;
+ break;
+ case ParityOdd:
+ parity_enable = 1;
+ parity_select = 1;
+ break;
+ case ParityEven:
+ parity_enable = 1;
+ parity_select = 0;
+ break;
+ case ParityForced1:
+ case ParityForced0:
+ default:
+ parity_enable = 0;
+ parity_select = 0;
+ break;
+ }
+
+ obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0078)
+ | (data_bits << 6)
+ | (parity_enable << 5)
+ | (parity_select << 4)
+ | (stop_bits << 3);
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+
+static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
+ __IO uint16_t *dmy_rd_scscr;
+ __IO uint16_t *dmy_rd_scfsr;
+ serial_t *obj;
+ int i;
+
+ dmy_rd_scscr = SCSCR_MATCH[index];
+ *dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0
+ dmy_rd_scfsr = SCFSR_MATCH[index];
+ *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Set TEND
+
+ obj = uart_data[index].tranferring_obj;
+ if (obj) {
+ i = obj->tx_buff.length - obj->tx_buff.pos;
+ if (0 < i) {
+ if (serial_available_buffer(obj) < i) {
+ i = serial_available_buffer(obj);
+ }
+ do {
+ uint8_t c = *(uint8_t *)obj->tx_buff.buffer;
+ obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
+ ++obj->tx_buff.pos;
+ obj->serial.uart->SCFTDR = c;
+ } while (--i);
+ serial_put_done(obj);
+ } else {
+ uart_data[index].tranferring_obj = NULL;
+ uart_data[index].event = SERIAL_EVENT_TX_COMPLETE;
+ ((void (*)())uart_data[index].async_tx_callback)();
+ }
+ }
+
+ irq_handler(uart_data[index].serial_irq_id, TxIrq);
+}
+
+static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
+ __IO uint16_t *dmy_rd_scscr;
+ __IO uint16_t *dmy_rd_scfsr;
+ serial_t *obj;
+ int c;
+
+ dmy_rd_scscr = SCSCR_MATCH[index];
+ *dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0
+ dmy_rd_scfsr = SCFSR_MATCH[index];
+ *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR
+
+ obj = uart_data[index].receiving_obj;
+ if (obj) {
+ if (obj->serial.uart->SCLSR & 1) {
+ if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+ serial_rx_abort_asynch(obj);
+ uart_data[index].event = SERIAL_EVENT_RX_OVERRUN_ERROR;
+ ((void (*)())uart_data[index].async_rx_callback)();
+ }
+ return;
+ }
+ c = serial_getc(obj);
+ if (c != -1) {
+ ((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos] = c;
+ ++obj->rx_buff.pos;
+ if (c == obj->char_match && ! obj->char_found) {
+ obj->char_found = 1;
+ if (obj->rx_buff.pos == obj->rx_buff.length) {
+ if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) {
+ uart_data[index].event = SERIAL_EVENT_RX_COMPLETE;
+ }
+ }
+ if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
+ uart_data[index].event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
+ }
+ if (uart_data[index].event) {
+ uart_data[index].receiving_obj = NULL;
+ ((void (*)())uart_data[index].async_rx_callback)();
+ }
+ } else if (obj->rx_buff.pos == obj->rx_buff.length) {
+ uart_data[index].receiving_obj = NULL;
+ if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) {
+ uart_data[index].event = SERIAL_EVENT_RX_COMPLETE;
+ ((void (*)())uart_data[index].async_rx_callback)();
+ }
+ }
+ } else {
+ serial_rx_abort_asynch(obj);
+ if (uart_data[index].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) {
+ uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR;
+ if (obj->serial.uart->SCFSR & 1 << 2) {
+ uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR;
+ } else if (obj->serial.uart->SCFSR & 1 << 3) {
+ uart_data[index].event = SERIAL_EVENT_RX_FRAMING_ERROR;
+ }
+ ((void (*)())uart_data[index].async_rx_callback)();
+ }
+ return;
+ }
+ }
+
+ irq_handler(uart_data[index].serial_irq_id, RxIrq);
+}
+
+static void uart_err_irq(IRQn_Type irq_num, uint32_t index) {
+ serial_t *obj = uart_data[index].receiving_obj;
+ int was_masked, err_read;
+
+ if (obj) {
+ serial_irq_err_set(obj, 0);
+ if (uart_data[index].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) {
+ uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR;
+ if (obj->serial.uart->SCFSR & 1 << 2) {
+ uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR;
+ } else if (obj->serial.uart->SCFSR & 1 << 3) {
+ uart_data[index].event = SERIAL_EVENT_RX_FRAMING_ERROR;
+ }
+ ((void (*)())uart_data[index].async_rx_callback)();
+ }
+ serial_rx_abort_asynch(obj);
+
+#if defined ( __ICCARM__ )
+ was_masked = __disable_irq_iar();
+#else
+ was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+ if (obj->serial.uart->SCFSR & 0x93) {
+ err_read = obj->serial.uart->SCFSR;
+ obj->serial.uart->SCFSR = (err_read & ~0x93);
+ }
+ if (obj->serial.uart->SCLSR & 1) {
+ obj->serial.uart->SCLSR = 0;
+ }
+ if (!was_masked) {
+ __enable_irq();
+ }
+ }
+}
+
+/* TX handler */
+static void uart0_tx_irq(void) {
+ uart_tx_irq(SCIFTXI0_IRQn, 0);
+}
+static void uart1_tx_irq(void) {
+ uart_tx_irq(SCIFTXI1_IRQn, 1);
+}
+static void uart2_tx_irq(void) {
+ uart_tx_irq(SCIFTXI2_IRQn, 2);
+}
+static void uart3_tx_irq(void) {
+ uart_tx_irq(SCIFTXI3_IRQn, 3);
+}
+static void uart4_tx_irq(void) {
+ uart_tx_irq(SCIFTXI4_IRQn, 4);
+}
+static void uart5_tx_irq(void) {
+ uart_tx_irq(SCIFTXI5_IRQn, 5);
+}
+static void uart6_tx_irq(void) {
+ uart_tx_irq(SCIFTXI6_IRQn, 6);
+}
+static void uart7_tx_irq(void) {
+ uart_tx_irq(SCIFTXI7_IRQn, 7);
+}
+/* RX handler */
+static void uart0_rx_irq(void) {
+ uart_rx_irq(SCIFRXI0_IRQn, 0);
+}
+static void uart1_rx_irq(void) {
+ uart_rx_irq(SCIFRXI1_IRQn, 1);
+}
+static void uart2_rx_irq(void) {
+ uart_rx_irq(SCIFRXI2_IRQn, 2);
+}
+static void uart3_rx_irq(void) {
+ uart_rx_irq(SCIFRXI3_IRQn, 3);
+}
+static void uart4_rx_irq(void) {
+ uart_rx_irq(SCIFRXI4_IRQn, 4);
+}
+static void uart5_rx_irq(void) {
+ uart_rx_irq(SCIFRXI5_IRQn, 5);
+}
+static void uart6_rx_irq(void) {
+ uart_rx_irq(SCIFRXI6_IRQn, 6);
+}
+static void uart7_rx_irq(void) {
+ uart_rx_irq(SCIFRXI7_IRQn, 7);
+}
+/* Error handler */
+static void uart0_er_irq(void)
+{
+ uart_err_irq(SCIFERI0_IRQn, 0);
+}
+static void uart1_er_irq(void)
+{
+ uart_err_irq(SCIFERI0_IRQn, 1);
+}
+static void uart2_er_irq(void)
+{
+ uart_err_irq(SCIFERI0_IRQn, 2);
+}
+static void uart3_er_irq(void)
+{
+ uart_err_irq(SCIFERI0_IRQn, 3);
+}
+static void uart4_er_irq(void)
+{
+ uart_err_irq(SCIFERI0_IRQn, 4);
+}
+static void uart5_er_irq(void)
+{
+ uart_err_irq(SCIFERI0_IRQn, 5);
+}
+static void uart6_er_irq(void)
+{
+ uart_err_irq(SCIFERI0_IRQn, 6);
+}
+static void uart7_er_irq(void)
+{
+ uart_err_irq(SCIFERI0_IRQn, 7);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ uart_data[obj->serial.index].serial_irq_id = id;
+}
+
+static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enable)
+{
+ if (enable) {
+ InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
+ GIC_SetPriority(IRQn, 5);
+ GIC_EnableIRQ(IRQn);
+ } else {
+ GIC_DisableIRQ(IRQn);
+ }
+}
+
+static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ IRQn_Type IRQn;
+ IRQHandler handler;
+
+ IRQn = irq_set_tbl[obj->serial.index][irq];
+ handler = hander_set_tbl[obj->serial.index][irq];
+
+ if ((obj->serial.index >= 0) && (obj->serial.index <= 7)) {
+ serial_irq_set_irq(IRQn, handler, enable);
+ }
+}
+
+static void serial_irq_err_set(serial_t *obj, uint32_t enable)
+{
+ serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable);
+ serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable);
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ if (RxIrq == irq) {
+ uart_data[obj->serial.index].rx_irq_set_api = enable;
+ }
+ serial_irq_set_internal(obj, irq, enable);
+}
+
+static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
+ uart_data[obj->serial.index].rx_irq_set_flow = enable;
+ serial_irq_set_internal(obj, RxIrq, enable);
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+ uint16_t err_read;
+ int data;
+ int was_masked;
+
+#if defined ( __ICCARM__ )
+ was_masked = __disable_irq_iar();
+#else
+ was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+ if (obj->serial.uart->SCFSR & 0x93) {
+ err_read = obj->serial.uart->SCFSR;
+ obj->serial.uart->SCFSR = (err_read & ~0x93);
+ }
+ obj->serial.uart->SCSCR |= 0x0040; // Set RIE
+ if (!was_masked) {
+ __enable_irq();
+ }
+
+ if (obj->serial.uart->SCLSR & 0x0001) {
+ obj->serial.uart->SCLSR = 0u; // ORER clear
+ }
+
+ while (!serial_readable(obj));
+ data = obj->serial.uart->SCFRDR & 0xff;
+
+#if defined ( __ICCARM__ )
+ was_masked = __disable_irq_iar();
+#else
+ was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+ err_read = obj->serial.uart->SCFSR;
+ obj->serial.uart->SCFSR = (err_read & 0xfffD); // Clear RDF
+ if (!was_masked) {
+ __enable_irq();
+ }
+
+ if (err_read & 0x80) {
+ data = -1; //err
+ }
+ return data;
+}
+
+void serial_putc(serial_t *obj, int c) {
+ while (!serial_writable(obj));
+ obj->serial.uart->SCFTDR = c;
+ serial_put_done(obj);
+}
+
+static void serial_put_done(serial_t *obj)
+{
+ int was_masked;
+ volatile uint16_t dummy_read;
+
+#if defined ( __ICCARM__ )
+ was_masked = __disable_irq_iar();
+#else
+ was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+ dummy_read = obj->serial.uart->SCFSR;
+ obj->serial.uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE
+ obj->serial.uart->SCSCR |= 0x0080; // Set TIE
+ if (!was_masked) {
+ __enable_irq();
+ }
+}
+
+int serial_readable(serial_t *obj) {
+ return ((obj->serial.uart->SCFSR & 0x02) != 0); // RDF
+}
+
+int serial_writable(serial_t *obj) {
+ return ((obj->serial.uart->SCFSR & 0x20) != 0); // TDFE
+}
+
+void serial_clear(serial_t *obj) {
+ int was_masked;
+#if defined ( __ICCARM__ )
+ was_masked = __disable_irq_iar();
+#else
+ was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+
+ obj->serial.uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1
+ obj->serial.uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0
+ obj->serial.uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0
+
+ if (!was_masked) {
+ __enable_irq();
+ }
+}
+
+void serial_pinout_tx(PinName tx) {
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+ int was_masked;
+#if defined ( __ICCARM__ )
+ was_masked = __disable_irq_iar();
+#else
+ was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+ // TxD Output(L)
+ obj->serial.uart->SCSPTR &= ~0x0001u; // SPB2DT = 0
+ obj->serial.uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable)
+ if (!was_masked) {
+ __enable_irq();
+ }
+}
+
+void serial_break_clear(serial_t *obj) {
+ int was_masked;
+#if defined ( __ICCARM__ )
+ was_masked = __disable_irq_iar();
+#else
+ was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+ obj->serial.uart->SCSCR |= 0x0020u; // TE = 1 (Output enable)
+ obj->serial.uart->SCSPTR |= 0x0001u; // SPB2DT = 1
+ if (!was_masked) {
+ __enable_irq();
+ }
+}
+
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
+ // determine the UART to use
+ int was_masked;
+
+ serial_flow_irq_set(obj, 0);
+
+ if (type == FlowControlRTSCTS) {
+#if defined ( __ICCARM__ )
+ was_masked = __disable_irq_iar();
+#else
+ was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+ obj->serial.uart->SCFCR = 0x0008u; // CTS/RTS enable
+ if (!was_masked) {
+ __enable_irq();
+ }
+ pinmap_pinout(rxflow, PinMap_UART_RTS);
+ pinmap_pinout(txflow, PinMap_UART_CTS);
+ } else {
+#if defined ( __ICCARM__ )
+ was_masked = __disable_irq_iar();
+#else
+ was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+ obj->serial.uart->SCFCR = 0x0000u; // CTS/RTS diable
+ if (!was_masked) {
+ __enable_irq();
+ }
+ }
+}
+
+static uint8_t serial_available_buffer(serial_t *obj)
+{
+ return 1;
+ /* Faster but unstable way */
+ /*
+ uint16_t ret = 16 - ((obj->serial.uart->SCFDR >> 8) & 0x1F);
+ while (ret == 0) {
+ ret = 16 - ((obj->serial.uart->SCFDR >> 8) & 0x1F);
+ }
+ MBED_ASSERT(0 < ret && ret <= 16);
+ return ret;
+ */
+}
+
+#if DEVICE_SERIAL_ASYNCH
+
+/******************************************************************************
+ * ASYNCHRONOUS HAL
+ ******************************************************************************/
+
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ int i;
+ buffer_t *buf = &obj->tx_buff;
+ struct serial_global_data_s *data = uart_data + obj->serial.index;
+
+ if (tx_length == 0) {
+ return 0;
+ }
+
+ buf->buffer = (void *)tx;
+ buf->length = tx_length * tx_width / 8;
+ buf->pos = 0;
+ buf->width = tx_width;
+ data->tranferring_obj = obj;
+ data->async_tx_callback = handler;
+ serial_irq_set(obj, TxIrq, 1);
+
+ while (!serial_writable(obj));
+ i = buf->length;
+ if (serial_available_buffer(obj) < i) {
+ i = serial_available_buffer(obj);
+ }
+ do {
+ uint8_t c = *(uint8_t *)buf->buffer;
+ obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
+ ++buf->pos;
+ obj->serial.uart->SCFTDR = c;
+ } while (--i);
+ serial_put_done(obj);
+
+ return buf->length;
+}
+
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
+{
+ buffer_t *buf = &obj->rx_buff;
+ struct serial_global_data_s *data = uart_data + obj->serial.index;
+
+ if (rx_length == 0) {
+ return;
+ }
+
+ buf->buffer = rx;
+ buf->length = rx_length * rx_width / 8;
+ buf->pos = 0;
+ buf->width = rx_width;
+ obj->char_match = char_match;
+ obj->char_found = 0;
+ data->receiving_obj = obj;
+ data->async_rx_callback = handler;
+ data->event = 0;
+ data->wanted_rx_events = event;
+
+ serial_irq_set(obj, RxIrq, 1);
+ serial_irq_err_set(obj, 1);
+}
+
+uint8_t serial_tx_active(serial_t *obj)
+{
+ return uart_data[obj->serial.index].tranferring_obj != NULL;
+}
+
+uint8_t serial_rx_active(serial_t *obj)
+{
+ return uart_data[obj->serial.index].receiving_obj != NULL;
+}
+
+int serial_irq_handler_asynch(serial_t *obj)
+{
+ return uart_data[obj->serial.index].event;
+}
+
+void serial_tx_abort_asynch(serial_t *obj)
+{
+ uart_data[obj->serial.index].tranferring_obj = NULL;
+ obj->serial.uart->SCFCR |= 1 << 2;
+ obj->serial.uart->SCFCR &= ~(1 << 2);
+}
+
+void serial_rx_abort_asynch(serial_t *obj)
+{
+ uart_data[obj->serial.index].receiving_obj = NULL;
+ obj->serial.uart->SCFCR |= 1 << 1;
+ obj->serial.uart->SCFCR &= ~(1 << 1);
+}
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,596 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include <math.h>
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "RZ_A1_Init.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+ {P10_12, SPI_0, 4},
+ {P4_4 , SPI_1, 2},
+ {P6_4 , SPI_1, 7},
+ {P11_12, SPI_1, 2},
+ {P8_3 , SPI_2, 3},
+ {P5_0 , SPI_3, 8},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+ {P10_13, SPI_0, 4},
+ {P4_5 , SPI_1, 2},
+ {P6_5 , SPI_1, 7},
+ {P11_13, SPI_1, 2},
+ {P8_4 , SPI_2, 3},
+ {P5_1 , SPI_3, 8},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+ {P10_14, SPI_0, 4},
+ {P4_6 , SPI_1, 2},
+ {P6_6 , SPI_1, 7},
+ {P11_14, SPI_1, 2},
+ {P8_5 , SPI_2, 3},
+ {P5_2 , SPI_3, 8},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+ {P10_15, SPI_0, 4},
+ {P4_7 , SPI_1, 2},
+ {P6_7 , SPI_1, 7},
+ {P11_15, SPI_1, 2},
+ {P8_6 , SPI_2, 3},
+ {P5_3 , SPI_3, 8},
+ {NC , NC , 0}
+};
+
+static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
+
+static inline void spi_disable(spi_t *obj);
+static inline void spi_enable(spi_t *obj);
+static inline int spi_readable(spi_t *obj);
+static inline void spi_write(spi_t *obj, int value);
+static inline int spi_read(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+ // determine the SPI to use
+ volatile uint8_t dummy;
+ uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
+ uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+ uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
+ uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
+ uint32_t spi = pinmap_merge(spi_data, spi_cntl);
+
+ MBED_ASSERT((int)spi != NC);
+
+ obj->spi.spi = (struct st_rspi *)RSPI[spi];
+ obj->spi.index = spi;
+
+ // enable power and clocking
+ switch (spi) {
+ case SPI_0: CPGSTBCR10 &= ~(0x80); break;
+ case SPI_1: CPGSTBCR10 &= ~(0x40); break;
+ case SPI_2: CPGSTBCR10 &= ~(0x20); break;
+ case SPI_3: CPGSTBCR10 &= ~(0x10); break;
+ }
+ dummy = CPGSTBCR10;
+
+ obj->spi.spi->SPCR = 0x00; // CTRL to 0
+ obj->spi.spi->SPSCR = 0x00; // no sequential operation
+ obj->spi.spi->SSLP = 0x00; // SSL 'L' active
+ obj->spi.spi->SPDCR = 0x20; // byte access
+ obj->spi.spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK
+ obj->spi.spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK
+ obj->spi.spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK
+ obj->spi.spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0
+ obj->spi.spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1
+ obj->spi.spi->SPBFCR = 0x30; // and reset buffer
+
+ // pin out the spi pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+ if ((int)ssel != NC) {
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+ int DSS; // DSS (data select size)
+ int polarity = (mode & 0x2) ? 1 : 0;
+ int phase = (mode & 0x1) ? 1 : 0;
+ uint16_t tmp = 0;
+ uint16_t mask = 0xf03;
+ uint16_t wk_spcmd0;
+ uint8_t splw;
+
+ switch (mode) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ // Do Nothing
+ break;
+ default:
+ error("SPI format error");
+ return;
+ }
+
+ switch (bits) {
+ case 8:
+ DSS = 0x7;
+ splw = 0x20;
+ break;
+ case 16:
+ DSS = 0xf;
+ splw = 0x40;
+ break;
+ case 32:
+ DSS = 0x2;
+ splw = 0x60;
+ break;
+ default:
+ error("SPI module don't support other than 8/16/32bits");
+ return;
+ }
+ tmp |= phase;
+ tmp |= (polarity << 1);
+ tmp |= (DSS << 8);
+ obj->spi.bits = bits;
+
+ spi_disable(obj);
+ wk_spcmd0 = obj->spi.spi->SPCMD0;
+ wk_spcmd0 &= ~mask;
+ wk_spcmd0 |= (mask & tmp);
+ obj->spi.spi->SPCMD0 = wk_spcmd0;
+ obj->spi.spi->SPDCR = splw;
+ if (slave) {
+ obj->spi.spi->SPCR &=~(1 << 3); // MSTR to 0
+ } else {
+ obj->spi.spi->SPCR |= (1 << 3); // MSTR to 1
+ }
+ spi_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+ uint32_t pclk_base;
+ uint32_t div;
+ uint32_t brdv = 0;
+ uint32_t hz_max;
+ uint32_t hz_min;
+ uint16_t mask = 0x000c;
+ uint16_t wk_spcmd0;
+
+ /* set PCLK */
+ if (RZ_A1_IsClockMode0() == false) {
+ pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
+ } else {
+ pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
+ }
+
+ hz_min = pclk_base / 2 / 256 / 8;
+ hz_max = pclk_base / 2;
+ if ((hz < hz_min) || (hz > hz_max)) {
+ error("Couldn't setup requested SPI frequency");
+ return;
+ }
+
+ div = (pclk_base / hz / 2);
+ while (div > 256) {
+ div >>= 1;
+ brdv++;
+ }
+ div -= 1;
+ brdv = (brdv << 2);
+
+ spi_disable(obj);
+ obj->spi.spi->SPBR = div;
+ wk_spcmd0 = obj->spi.spi->SPCMD0;
+ wk_spcmd0 &= ~mask;
+ wk_spcmd0 |= (mask & brdv);
+ obj->spi.spi->SPCMD0 = wk_spcmd0;
+ spi_enable(obj);
+}
+
+static inline void spi_disable(spi_t *obj) {
+ obj->spi.spi->SPCR &= ~(1 << 6); // SPE to 0
+}
+
+static inline void spi_enable(spi_t *obj) {
+ obj->spi.spi->SPCR |= (1 << 6); // SPE to 1
+}
+
+static inline int spi_readable(spi_t *obj) {
+ return obj->spi.spi->SPSR & (1 << 7); // SPRF
+}
+
+static inline int spi_tend(spi_t *obj) {
+ return obj->spi.spi->SPSR & (1 << 6); // TEND
+}
+
+static inline void spi_write(spi_t *obj, int value) {
+ if (obj->spi.bits == 8) {
+ obj->spi.spi->SPDR.UINT8[0] = (uint8_t)value;
+ } else if (obj->spi.bits == 16) {
+ obj->spi.spi->SPDR.UINT16[0] = (uint16_t)value;
+ } else {
+ obj->spi.spi->SPDR.UINT32 = (uint32_t)value;
+ }
+}
+
+static inline int spi_read(spi_t *obj) {
+ int read_data;
+
+ if (obj->spi.bits == 8) {
+ read_data = obj->spi.spi->SPDR.UINT8[0];
+ } else if (obj->spi.bits == 16) {
+ read_data = obj->spi.spi->SPDR.UINT16[0];
+ } else {
+ read_data = obj->spi.spi->SPDR.UINT32;
+ }
+
+ return read_data;
+}
+
+int spi_master_write(spi_t *obj, int value) {
+ spi_write(obj, value);
+ while(!spi_tend(obj));
+ return spi_read(obj);
+}
+
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+ int total = (tx_length > rx_length) ? tx_length : rx_length;
+
+ for (int i = 0; i < total; i++) {
+ char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+ char in = spi_master_write(obj, out);
+ if (i < rx_length) {
+ rx_buffer[i] = in;
+ }
+ }
+
+ return total;
+}
+
+int spi_slave_receive(spi_t *obj) {
+ return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
+}
+
+int spi_slave_read(spi_t *obj) {
+ return spi_read(obj);
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+ spi_write(obj, value);
+}
+
+int spi_busy(spi_t *obj) {
+ return 0;
+}
+
+#if DEVICE_SPI_ASYNCH
+
+#define IRQ_NUM 2
+
+static void spi_irqs_set(spi_t *obj, uint32_t enable);
+static void spi_async_write(spi_t *obj);
+static void spi_async_read(spi_t *obj);
+
+static void spi0_rx_irq(void);
+static void spi1_rx_irq(void);
+static void spi2_rx_irq(void);
+static void spi3_rx_irq(void);
+static void spi4_rx_irq(void);
+static void spi0_er_irq(void);
+static void spi1_er_irq(void);
+static void spi2_er_irq(void);
+static void spi3_er_irq(void);
+static void spi4_er_irq(void);
+
+static const IRQn_Type irq_set_tbl[RSPI_COUNT][IRQ_NUM] = {
+ {RSPISPRI0_IRQn, RSPISPEI0_IRQn},
+ {RSPISPRI1_IRQn, RSPISPEI1_IRQn},
+ {RSPISPRI2_IRQn, RSPISPEI2_IRQn},
+ {RSPISPRI3_IRQn, RSPISPEI3_IRQn},
+ {RSPISPRI4_IRQn, RSPISPEI4_IRQn}
+};
+
+static const IRQHandler hander_set_tbl[RSPI_COUNT][IRQ_NUM] = {
+ {spi0_rx_irq, spi0_er_irq},
+ {spi1_rx_irq, spi1_er_irq},
+ {spi2_rx_irq, spi2_er_irq},
+ {spi3_rx_irq, spi3_er_irq},
+ {spi4_rx_irq, spi4_er_irq}
+};
+
+struct spi_global_data_s {
+ spi_t *async_obj;
+ uint32_t async_callback, event, wanted_events;
+};
+
+static struct spi_global_data_s spi_data[RSPI_COUNT];
+
+static void spi_rx_irq(IRQn_Type irq_num, uint32_t index)
+{
+ spi_t *obj = spi_data[index].async_obj;
+ if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+ spi_async_read(obj);
+ } else {
+ if (obj->rx_buff.buffer && obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
+ spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+ if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
+ spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
+ }
+ spi_irqs_set(obj, 0);
+ spi_data[obj->spi.index].async_obj = NULL;
+ ((void (*)())spi_data[obj->spi.index].async_callback)();
+ return;
+ }
+ spi_read(obj);
+ }
+ if (obj->tx_buff.buffer) {
+ if (obj->tx_buff.pos == obj->tx_buff.length) {
+ spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+ if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
+ spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
+ }
+ spi_irqs_set(obj, 0);
+ spi_data[obj->spi.index].async_obj = NULL;
+ ((void (*)())spi_data[obj->spi.index].async_callback)();
+ } else {
+ spi_async_write(obj);
+ }
+ } else {
+ if (obj->rx_buff.pos == obj->rx_buff.length) {
+ spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+ if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
+ spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
+ }
+ spi_irqs_set(obj, 0);
+ spi_data[obj->spi.index].async_obj = NULL;
+ ((void (*)())spi_data[obj->spi.index].async_callback)();
+ } else {
+ spi_async_write(obj);
+ }
+ }
+}
+
+static void spi_err_irq(IRQn_Type irq_num, uint32_t index)
+{
+ spi_t *obj = spi_data[index].async_obj;
+ spi_abort_asynch(obj);
+ spi_data[index].event = SPI_EVENT_ERROR;
+ if (spi_data[index].wanted_events & SPI_EVENT_ERROR) {
+ ((void (*)())spi_data[index].async_callback)();
+ }
+}
+
+static void spi0_rx_irq(void)
+{
+ spi_rx_irq(RSPISPRI0_IRQn, 0);
+}
+
+static void spi1_rx_irq(void)
+{
+ spi_rx_irq(RSPISPRI1_IRQn, 1);
+}
+
+static void spi2_rx_irq(void)
+{
+ spi_rx_irq(RSPISPRI2_IRQn, 2);
+}
+
+static void spi3_rx_irq(void)
+{
+ spi_rx_irq(RSPISPRI3_IRQn, 3);
+}
+
+static void spi4_rx_irq(void)
+{
+ spi_rx_irq(RSPISPRI4_IRQn, 4);
+}
+
+static void spi0_er_irq(void)
+{
+ spi_err_irq(RSPISPEI0_IRQn, 0);
+}
+
+static void spi1_er_irq(void)
+{
+ spi_err_irq(RSPISPEI1_IRQn, 1);
+}
+
+static void spi2_er_irq(void)
+{
+ spi_err_irq(RSPISPEI2_IRQn, 2);
+}
+
+static void spi3_er_irq(void)
+{
+ spi_err_irq(RSPISPEI3_IRQn, 3);
+}
+
+static void spi4_er_irq(void)
+{
+ spi_err_irq(RSPISPEI4_IRQn, 4);
+}
+
+static void spi_irqs_set(spi_t *obj, uint32_t enable)
+{
+ int i;
+ const IRQn_Type *irqTable = irq_set_tbl[obj->spi.index];
+ const IRQHandler *handlerTable = hander_set_tbl[obj->spi.index];
+ for (i = 0; i < IRQ_NUM; ++i) {
+ if (enable) {
+ InterruptHandlerRegister(irqTable[i], handlerTable[i]);
+ GIC_SetPriority(irqTable[i], 5);
+ GIC_EnableIRQ(irqTable[i]);
+ } else {
+ GIC_DisableIRQ(irqTable[i]);
+ }
+ }
+ if (enable) {
+ obj->spi.spi->SPCR |= (1 << 4) | (1 << 7);
+ } else {
+ obj->spi.spi->SPCR &= ~((1 << 4) | (1 << 7));
+ }
+}
+
+static void spi_async_write(spi_t *obj)
+{
+ uint8_t **width8;
+ uint16_t **width16;
+ uint32_t **width32;
+
+ if (obj->tx_buff.buffer) {
+ switch (obj->tx_buff.width) {
+ case 8:
+ width8 = (uint8_t **)&obj->tx_buff.buffer;
+ spi_write(obj, **width8);
+ ++*width8;
+ obj->tx_buff.pos += sizeof(uint8_t);
+ break;
+
+ case 16:
+ width16 = (uint16_t **)&obj->tx_buff.buffer;
+ spi_write(obj, **width16);
+ ++*width16;
+ obj->tx_buff.pos += sizeof(uint16_t);
+ break;
+
+ case 32:
+ width32 = (uint32_t **)&obj->tx_buff.buffer;
+ spi_write(obj, **width32);
+ ++*width32;
+ obj->tx_buff.pos += sizeof(uint32_t);
+ break;
+
+ default:
+ MBED_ASSERT(0);
+ break;
+ }
+ } else {
+ spi_write(obj, SPI_FILL_WORD);
+ }
+}
+
+static void spi_async_read(spi_t *obj)
+{
+ uint8_t **width8;
+ uint16_t **width16;
+ uint32_t **width32;
+
+ switch (obj->rx_buff.width) {
+ case 8:
+ width8 = (uint8_t **)&obj->rx_buff.buffer;
+ **width8 = spi_read(obj);
+ ++*width8;
+ obj->rx_buff.pos += sizeof(uint8_t);
+ break;
+
+ case 16:
+ width16 = (uint16_t **)&obj->rx_buff.buffer;
+ **width16 = spi_read(obj);
+ ++*width16;
+ obj->rx_buff.pos += sizeof(uint16_t);
+ break;
+
+ case 32:
+ width32 = (uint32_t **)&obj->rx_buff.buffer;
+ **width32 = spi_read(obj);
+ ++*width32;
+ obj->rx_buff.pos += sizeof(uint32_t);
+ break;
+
+ default:
+ MBED_ASSERT(0);
+ break;
+ }
+}
+
+/******************************************************************************
+ * ASYNCHRONOUS HAL
+ ******************************************************************************/
+
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ int i;
+ MBED_ASSERT(obj);
+ MBED_ASSERT(tx || rx);
+ MBED_ASSERT(tx && ! rx ? tx_length : 1);
+ MBED_ASSERT(rx && ! tx ? rx_length : 1);
+ MBED_ASSERT(obj->spi.spi->SPCR & (1 << 3)); /* Slave mode */
+ MBED_ASSERT(bit_width == 8 || bit_width == 16 || bit_width == 32);
+
+ if (tx_length) {
+ obj->tx_buff.buffer = (void *)tx;
+ } else {
+ obj->tx_buff.buffer = NULL;
+ }
+ obj->tx_buff.length = tx_length * bit_width / 8;
+ obj->tx_buff.pos = 0;
+ obj->tx_buff.width = bit_width;
+ if (rx_length) {
+ obj->rx_buff.buffer = rx;
+ } else {
+ obj->rx_buff.buffer = NULL;
+ }
+ obj->rx_buff.length = rx_length * bit_width / 8;
+ obj->rx_buff.pos = 0;
+ obj->rx_buff.width = bit_width;
+ for (i = 0; i < obj->rx_buff.length; i++) {
+ ((uint8_t *)obj->rx_buff.buffer)[i] = SPI_FILL_WORD;
+ }
+
+ spi_data[obj->spi.index].async_callback = handler;
+ spi_data[obj->spi.index].async_obj = obj;
+ spi_data[obj->spi.index].event = 0;
+ spi_data[obj->spi.index].wanted_events = event;
+
+ spi_irqs_set(obj, 1);
+
+ spi_async_write(obj);
+}
+
+uint32_t spi_irq_handler_asynch(spi_t *obj)
+{
+ return spi_data[obj->spi.index].event;
+}
+
+uint8_t spi_active(spi_t *obj)
+{
+ return spi_data[obj->spi.index].async_obj != NULL;
+}
+
+void spi_abort_asynch(spi_t *obj)
+{
+ spi_disable(obj);
+ spi_irqs_set(obj, 0);
+ spi_data[obj->spi.index].async_obj = NULL;
+ spi_enable(obj);
+}
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c Fri Jul 21 01:26:54 2017 +0000
@@ -0,0 +1,154 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+#include "ostm_iodefine.h"
+
+#include "RZ_A1_Init.h"
+#include "MBRZA1H.h"
+#include "vfp_neon_push_pop.h"
+
+#define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn)
+#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
+
+#define US_TICKER_CLOCK_US_DEV (1000000)
+
+int us_ticker_inited = 0;
+static double count_clock = 0;
+static uint32_t last_read = 0;
+static uint32_t wrap_arround = 0;
+static uint64_t ticker_us_last64 = 0;
+static uint64_t set_cmp_val64 = 0;
+static uint64_t timestamp64 = 0;
+
+void us_ticker_interrupt(void) {
+ us_ticker_irq_handler();
+}
+
+void us_ticker_init(void) {
+ if (us_ticker_inited) return;
+ us_ticker_inited = 1;
+
+ /* set Counter Clock(us) */
+ if (false == RZ_A1_IsClockMode0()) {
+ count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
+ } else {
+ count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
+ }
+
+ /* Power Control for Peripherals */
+ CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
+
+ // timer settings
+ OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */
+ OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */
+
+ OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
+
+ // INTC settings
+ InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
+ GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
+ GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+static uint64_t ticker_read_counter64(void) {
+ uint32_t cnt_val;
+ uint64_t cnt_val64;
+
+ if (!us_ticker_inited)
+ us_ticker_init();
+
+ /* read counter */
+ cnt_val = OSTM1CNT;
+ if (last_read > cnt_val) {
+ wrap_arround++;
+ }
+ last_read = cnt_val;
+ cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val;
+
+ return cnt_val64;
+}
+
+static void us_ticker_read_last(void) {
+ uint64_t cnt_val64;
+
+ cnt_val64 = ticker_read_counter64();
+
+ ticker_us_last64 = (cnt_val64 / count_clock);
+}
+
+uint32_t us_ticker_read() {
+ int check_irq_masked;
+
+#if defined ( __ICCARM__)
+ check_irq_masked = __disable_irq_iar();
+#else
+ check_irq_masked = __disable_irq();
+#endif /* __ICCARM__ */
+
+ __vfp_neon_push();
+ us_ticker_read_last();
+ __vfp_neon_pop();
+
+ if (!check_irq_masked) {
+ __enable_irq();
+ }
+
+ /* clock to us */
+ return (uint32_t)ticker_us_last64;
+}
+
+static void us_ticker_calc_compare_match(void) {
+ set_cmp_val64 = timestamp64 * count_clock;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp) {
+ // set match value
+ volatile uint32_t set_cmp_val;
+ uint64_t count_val_64;
+
+ /* calc compare mach timestamp */
+ timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp;
+ if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) {
+ /* This event is wrap arround */
+ timestamp64 += 0x100000000;
+ }
+
+ /* calc compare mach timestamp */
+ __vfp_neon_push();
+ us_ticker_calc_compare_match();
+ __vfp_neon_pop();
+
+ set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF);
+ count_val_64 = ticker_read_counter64();
+ if (set_cmp_val64 <= (count_val_64 + 500)) {
+ GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+ GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+ return;
+ }
+ OSTM1CMP = set_cmp_val;
+ GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+void us_ticker_disable_interrupt(void) {
+ GIC_DisableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+void us_ticker_clear_interrupt(void) {
+ GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+