drv_canfdspi_register.h

00001 /*******************************************************************************
00002   CAN FD SPI Driver: Register Header File
00003 
00004   Company:
00005     Microchip Technology Inc.
00006 
00007   File Name:
00008     drv_canfdspi_register.h
00009 
00010   Summary:
00011     This header file contains SPI instruction defines, register address defines,
00012     register structures, and reset values of registers.
00013 
00014   Description:
00015     This file is used by the API.
00016  *******************************************************************************/
00017 
00018 //DOM-IGNORE-BEGIN
00019 /*******************************************************************************
00020 Copyright (c) 2016 Microchip Technology Inc. and its subsidiaries.  
00021 You may use this software and any derivatives exclusively with Microchip products. 
00022   
00023 THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".  
00024 NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 
00025 INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 
00026 AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP PRODUCTS, 
00027 COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. 
00028 
00029 IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, 
00030 INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER 
00031 RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED 
00032 OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT ALLOWED BY LAW, 
00033 MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE 
00034 WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
00035 
00036 MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE TERMS.
00037  *******************************************************************************/
00038 //DOM-IGNORE-END
00039 
00040 #ifndef _DRV_CANFDSPI_REGISTER_H
00041 #define _DRV_CANFDSPI_REGISTER_H
00042 
00043 // *****************************************************************************
00044 // *****************************************************************************
00045 // Section: Included Files
00046 
00047 #include "drv_canfdspi_defines.h"
00048 
00049 // DOM-IGNORE-BEGIN
00050 #ifdef __cplusplus  // Provide C++ Compatibility
00051 extern "C" {
00052 #endif
00053 // DOM-IGNORE-END  
00054 
00055 
00056 // *****************************************************************************
00057 // *****************************************************************************
00058 /* SPI Instruction Set */
00059 
00060 #define cINSTRUCTION_RESET          0x00
00061 #define cINSTRUCTION_READ           0x03
00062 #define cINSTRUCTION_READ_CRC       0x0B
00063 #define cINSTRUCTION_WRITE          0x02
00064 #define cINSTRUCTION_WRITE_CRC      0x0A
00065 #define cINSTRUCTION_WRITE_SAFE     0x0C
00066 
00067 // *****************************************************************************
00068 // *****************************************************************************
00069 /* Register Addresses */
00070 
00071 /* can_fd_ubp */
00072 #define cREGADDR_CiCON      0x000
00073 #define cREGADDR_CiNBTCFG   0x004
00074 #define cREGADDR_CiDBTCFG   0x008
00075 #define cREGADDR_CiTDC      0x00C
00076 
00077 #define cREGADDR_CiTBC      0x010
00078 #define cREGADDR_CiTSCON    0x014
00079 #define cREGADDR_CiVEC      0x018
00080 #define cREGADDR_CiINT      0x01C
00081 #define cREGADDR_CiINTFLAG      cREGADDR_CiINT
00082 #define cREGADDR_CiINTENABLE    (cREGADDR_CiINT+2)
00083 
00084 #define cREGADDR_CiRXIF     0x020
00085 #define cREGADDR_CiTXIF     0x024
00086 #define cREGADDR_CiRXOVIF   0x028
00087 #define cREGADDR_CiTXATIF   0x02C
00088 
00089 #define cREGADDR_CiTXREQ    0x030
00090 #define cREGADDR_CiTREC     0x034
00091 #define cREGADDR_CiBDIAG0   0x038
00092 #define cREGADDR_CiBDIAG1   0x03C
00093 
00094 #define cREGADDR_CiTEFCON   0x040
00095 #define cREGADDR_CiTEFSTA   0x044
00096 #define cREGADDR_CiTEFUA    0x048
00097 #define cREGADDR_CiFIFOBA   0x04C
00098 
00099 #define cREGADDR_CiFIFOCON  0x050
00100 #define cREGADDR_CiFIFOSTA  0x054
00101 #define cREGADDR_CiFIFOUA   0x058
00102 #define CiFIFO_OFFSET       (3*4)
00103 
00104 #ifdef CAN_TXQUEUE_IMPLEMENTED
00105 #define cREGADDR_CiTXQCON  0x050
00106 #define cREGADDR_CiTXQSTA  0x054
00107 #define cREGADDR_CiTXQUA   0x058
00108 #endif
00109 
00110 #ifdef FIXED_FILTER_ADDRESS
00111 // Up to A1, the filter start address was fixed
00112 #define cREGADDR_CiFLTCON   0x1D0
00113 #define cREGADDR_CiFLTOBJ   0x1F0
00114 #define cREGADDR_CiMASK     0x1F4
00115 #else
00116 // Starting with B0, the filters start right after the FIFO control/status registers
00117 #define cREGADDR_CiFLTCON   (cREGADDR_CiFIFOCON+(CiFIFO_OFFSET*CAN_FIFO_TOTAL_CHANNELS))
00118 #define cREGADDR_CiFLTOBJ   (cREGADDR_CiFLTCON+CAN_FIFO_TOTAL_CHANNELS)
00119 #define cREGADDR_CiMASK     (cREGADDR_CiFLTOBJ+4)
00120 #endif
00121 
00122 #define CiFILTER_OFFSET     (2*4)
00123 
00124 /* MCP2517 Specific */
00125 #define cREGADDR_OSC        0xE00
00126 #define cREGADDR_IOCON      0xE04
00127 #define cREGADDR_CRC        0xE08
00128 #define cREGADDR_ECCCON     0xE0C
00129 #define cREGADDR_ECCSTA     0xE10
00130 
00131 /* RAM addresses */
00132 #define cRAM_SIZE       2048
00133 #define cRAMADDR_START  0x400
00134 #define cRAMADDR_END    (cRAMADDR_START+cRAM_SIZE)
00135 
00136 // *****************************************************************************
00137 // *****************************************************************************
00138 /* Register Structures */
00139 
00140 // *****************************************************************************
00141 //! General 32-bit Register
00142 
00143 typedef union _REG_t {
00144     uint8_t byte[4];
00145     uint32_t word;
00146 } REG_t;
00147 
00148 
00149 // *****************************************************************************
00150 // *****************************************************************************
00151 /* can_fd_ubp */
00152 
00153 // *****************************************************************************
00154 //! CAN Control Register
00155 
00156 typedef union _REG_CiCON {
00157 
00158     struct {
00159         uint32_t DNetFilterCount : 5;
00160         uint32_t IsoCrcEnable : 1;
00161         uint32_t ProtocolExceptionEventDisable : 1;
00162         uint32_t unimplemented1 : 1;
00163         uint32_t WakeUpFilterEnable : 1;
00164         uint32_t WakeUpFilterTime : 2;
00165         uint32_t unimplemented2 : 1;
00166         uint32_t BitRateSwitchDisable : 1;
00167         uint32_t unimplemented3 : 3;
00168         uint32_t RestrictReTxAttempts : 1;
00169         uint32_t EsiInGatewayMode : 1;
00170         uint32_t SystemErrorToListenOnly : 1;
00171         uint32_t StoreInTEF : 1;
00172         uint32_t TXQEnable : 1;
00173         uint32_t OpMode : 3;
00174         uint32_t RequestOpMode : 3;
00175         uint32_t AbortAllTx : 1;
00176         uint32_t TxBandWidthSharing : 4;
00177     } bF;
00178     uint32_t word;
00179     uint8_t byte[4];
00180 } REG_CiCON;
00181 
00182 // *****************************************************************************
00183 //! Nominal Bit Time Configuration Register
00184 
00185 typedef union _REG_CiNBTCFG {
00186 
00187     struct {
00188         uint32_t SJW : 7;
00189         uint32_t unimplemented1 : 1;
00190         uint32_t TSEG2 : 7;
00191         uint32_t unimplemented2 : 1;
00192         uint32_t TSEG1 : 8;
00193         uint32_t BRP : 8;
00194     } bF;
00195     uint32_t word;
00196     uint8_t byte[4];
00197 } REG_CiNBTCFG;
00198 
00199 // *****************************************************************************
00200 //! Data Bit Time Configuration Register
00201 
00202 typedef union _REG_CiDBTCFG {
00203 
00204     struct {
00205         uint32_t SJW : 4;
00206         uint32_t unimplemented1 : 4;
00207         uint32_t TSEG2 : 4;
00208         uint32_t unimplemented2 : 4;
00209         uint32_t TSEG1 : 5;
00210         uint32_t unimplemented3 : 3;
00211         uint32_t BRP : 8;
00212     } bF;
00213     uint32_t word;
00214     uint8_t byte[4];
00215 } REG_CiDBTCFG;
00216 
00217 // *****************************************************************************
00218 //! Transmitter Delay Compensation Register
00219 
00220 typedef union _REG_CiTDC {
00221 
00222     struct {
00223         uint32_t TDCValue : 6;
00224         uint32_t unimplemented1 : 2;
00225         uint32_t TDCOffset : 7;
00226         uint32_t unimplemented2 : 1;
00227         uint32_t TDCMode : 2;
00228         uint32_t unimplemented3 : 6;
00229         uint32_t SID11Enable : 1;
00230         uint32_t EdgeFilterEnable : 1;
00231         uint32_t unimplemented4 : 6;
00232     } bF;
00233     uint32_t word;
00234     uint8_t byte[4];
00235 } REG_CiTDC;
00236 
00237 // *****************************************************************************
00238 //! Time Stamp Configuration Register
00239 
00240 typedef union _REG_CiTSCON {
00241 
00242     struct {
00243         uint32_t TBCPrescaler : 10;
00244         uint32_t unimplemented1 : 6;
00245         uint32_t TBCEnable : 1;
00246         uint32_t TimeStampEOF : 1;
00247         uint32_t unimplemented2 : 14;
00248     } bF;
00249     uint32_t word;
00250     uint8_t byte[4];
00251 } REG_CiTSCON;
00252 
00253 // *****************************************************************************
00254 //! Interrupt Vector Register
00255 
00256 typedef union _REG_CiVEC {
00257 
00258     struct {
00259         uint32_t ICODE : 7;
00260         uint32_t unimplemented1 : 1;
00261         uint32_t FilterHit : 5;
00262         uint32_t unimplemented2 : 3;
00263         uint32_t TXCODE : 7;
00264         uint32_t unimplemented3 : 1;
00265         uint32_t RXCODE : 7;
00266         uint32_t unimplemented4 : 1;
00267     } bF;
00268     uint32_t word;
00269     uint8_t byte[4];
00270 } REG_CiVEC;
00271 
00272 // *****************************************************************************
00273 //! Interrupt Flags
00274 
00275 typedef struct _CAN_INT_FLAGS {
00276     uint32_t TXIF : 1;
00277     uint32_t RXIF : 1;
00278     uint32_t TBCIF : 1;
00279     uint32_t MODIF : 1;
00280     uint32_t TEFIF : 1;
00281     uint32_t unimplemented1 : 3;
00282 
00283     uint32_t ECCIF : 1;
00284     uint32_t SPICRCIF : 1;
00285     uint32_t TXATIF : 1;
00286     uint32_t RXOVIF : 1;
00287     uint32_t SERRIF : 1;
00288     uint32_t CERRIF : 1;
00289     uint32_t WAKIF : 1;
00290     uint32_t IVMIF : 1;
00291 } CAN_INT_FLAGS;
00292 
00293 // *****************************************************************************
00294 //! Interrupt Enables
00295 
00296 typedef struct _CAN_INT_ENABLES {
00297     uint32_t TXIE : 1;
00298     uint32_t RXIE : 1;
00299     uint32_t TBCIE : 1;
00300     uint32_t MODIE : 1;
00301     uint32_t TEFIE : 1;
00302     uint32_t unimplemented2 : 3;
00303 
00304     uint32_t ECCIE : 1;
00305     uint32_t SPICRCIE : 1;
00306     uint32_t TXATIE : 1;
00307     uint32_t RXOVIE : 1;
00308     uint32_t SERRIE : 1;
00309     uint32_t CERRIE : 1;
00310     uint32_t WAKIE : 1;
00311     uint32_t IVMIE : 1;
00312 } CAN_INT_ENABLES;
00313 
00314 // *****************************************************************************
00315 //! Interrupt Register
00316 
00317 typedef union _REG_CiINT {
00318 
00319     struct {
00320         CAN_INT_FLAGS IF;
00321         CAN_INT_ENABLES IE;
00322     } bF;
00323     uint32_t word;
00324     uint8_t byte[4];
00325 } REG_CiINT;
00326 
00327 // *****************************************************************************
00328 //! Interrupt Flag Register
00329 
00330 typedef union _REG_CiINTFLAG {
00331     CAN_INT_FLAGS IF;
00332     uint16_t word;
00333     uint8_t byte[2];
00334 } REG_CiINTFLAG;
00335 
00336 // *****************************************************************************
00337 //! Interrupt Enable Register
00338 
00339 typedef union _REG_CiINTENABLE {
00340     CAN_INT_ENABLES IE;
00341     uint16_t word;
00342     uint8_t byte[2];
00343 } REG_CiINTENABLE;
00344 
00345 // *****************************************************************************
00346 //! Transmit/Receive Error Count Register
00347 
00348 typedef union _REG_CiTREC {
00349 
00350     struct {
00351         uint32_t RxErrorCount : 8;
00352         uint32_t TxErrorCount : 8;
00353         uint32_t ErrorStateWarning : 1;
00354         uint32_t RxErrorStateWarning : 1;
00355         uint32_t TxErrorStateWarning : 1;
00356         uint32_t RxErrorStatePassive : 1;
00357         uint32_t TxErrorStatePassive : 1;
00358         uint32_t TxErrorStateBusOff : 1;
00359         uint32_t unimplemented1 : 10;
00360     } bF;
00361     uint32_t word;
00362     uint8_t byte[4];
00363 } REG_CiTREC;
00364 
00365 // *****************************************************************************
00366 //! Diagnostic Register 0
00367 
00368 typedef union _REG_CiBDIAG0 {
00369 
00370     struct {
00371         uint32_t NRxErrorCount : 8;
00372         uint32_t NTxErrorCount : 8;
00373         uint32_t DRxErrorCount : 8;
00374         uint32_t DTxErrorCount : 8;
00375     } bF;
00376     uint32_t word;
00377     uint8_t byte[4];
00378 } REG_CiBDIAG0;
00379 
00380 // *****************************************************************************
00381 //! Diagnostic Register 1
00382 
00383 typedef union _REG_CiBDIAG1 {
00384 
00385     struct {
00386         uint32_t ErrorFreeMsgCount : 16;
00387 
00388         uint32_t NBit0Error : 1;
00389         uint32_t NBit1Error : 1;
00390         uint32_t NAckError : 1;
00391         uint32_t NFormError : 1;
00392         uint32_t NStuffError : 1;
00393         uint32_t NCRCError : 1;
00394         uint32_t unimplemented1 : 1;
00395         uint32_t TXBOError : 1;
00396         uint32_t DBit0Error : 1;
00397         uint32_t DBit1Error : 1;
00398         uint32_t DAckError : 1;
00399         uint32_t DFormError : 1;
00400         uint32_t DStuffError : 1;
00401         uint32_t DCRCError : 1;
00402         uint32_t ESI : 1;
00403         uint32_t unimplemented2 : 1;
00404     } bF;
00405     uint32_t word;
00406     uint8_t byte[4];
00407 } REG_CiBDIAG1;
00408 
00409 // *****************************************************************************
00410 //! Transmit Event FIFO Control Register
00411 
00412 typedef union _REG_CiTEFCON {
00413 
00414     struct {
00415         uint32_t TEFNEIE : 1;
00416         uint32_t TEFHFIE : 1;
00417         uint32_t TEFFULIE : 1;
00418         uint32_t TEFOVIE : 1;
00419         uint32_t unimplemented1 : 1;
00420         uint32_t TimeStampEnable : 1;
00421         uint32_t unimplemented2 : 2;
00422         uint32_t UINC : 1;
00423         uint32_t unimplemented3 : 1;
00424         uint32_t FRESET : 1;
00425         uint32_t unimplemented4 : 13;
00426         uint32_t FifoSize : 5;
00427         uint32_t unimplemented5 : 3;
00428     } bF;
00429     uint32_t word;
00430     uint8_t byte[4];
00431 } REG_CiTEFCON;
00432 
00433 // *****************************************************************************
00434 //! Transmit Event FIFO Status Register
00435 
00436 typedef union _REG_CiTEFSTA {
00437 
00438     struct {
00439         uint32_t TEFNotEmptyIF : 1;
00440         uint32_t TEFHalfFullIF : 1;
00441         uint32_t TEFFullIF : 1;
00442         uint32_t TEFOVIF : 1;
00443         uint32_t unimplemented1 : 28;
00444     } bF;
00445     uint32_t word;
00446     uint8_t byte[4];
00447 } REG_CiTEFSTA;
00448 
00449 // *****************************************************************************
00450 //! Transmit Queue Control Register
00451 
00452 typedef union _REG_CiTXQCON {
00453 
00454     struct {
00455         uint32_t TxNotFullIE : 1;
00456         uint32_t unimplemented1 : 1;
00457         uint32_t TxEmptyIE : 1;
00458         uint32_t unimplemented2 : 1;
00459         uint32_t TxAttemptIE : 1;
00460         uint32_t unimplemented3 : 2;
00461         uint32_t TxEnable : 1;
00462         uint32_t UINC : 1;
00463         uint32_t TxRequest : 1;
00464         uint32_t FRESET : 1;
00465         uint32_t unimplemented4 : 5;
00466         uint32_t TxPriority : 5;
00467         uint32_t TxAttempts : 2;
00468         uint32_t unimplemented5 : 1;
00469         uint32_t FifoSize : 5;
00470         uint32_t PayLoadSize : 3;
00471     } txBF;
00472     uint32_t word;
00473     uint8_t byte[4];
00474 } REG_CiTXQCON;
00475 
00476 // *****************************************************************************
00477 //! Transmit Queue Status Register
00478 
00479 typedef union _REG_CiTXQSTA {
00480 
00481     struct {
00482         uint32_t TxNotFullIF : 1;
00483         uint32_t unimplemented1 : 1;
00484         uint32_t TxEmptyIF : 1;
00485         uint32_t unimplemented2 : 1;
00486         uint32_t TxAttemptIF : 1;
00487         uint32_t TxError : 1;
00488         uint32_t TxLostArbitration : 1;
00489         uint32_t TxAborted : 1;
00490         uint32_t FifoIndex : 5;
00491         uint32_t unimplemented3 : 19;
00492     } txBF;
00493     uint32_t word;
00494     uint8_t byte[4];
00495 } REG_CiTXQSTA;
00496 
00497 // *****************************************************************************
00498 //! FIFO Control Register
00499 
00500 typedef union _REG_CiFIFOCON {
00501     // Receive FIFO
00502 
00503     struct {
00504         uint32_t RxNotEmptyIE : 1;
00505         uint32_t RxHalfFullIE : 1;
00506         uint32_t RxFullIE : 1;
00507         uint32_t RxOverFlowIE : 1;
00508         uint32_t unimplemented1 : 1;
00509         uint32_t RxTimeStampEnable : 1;
00510         uint32_t unimplemented2 : 1;
00511         uint32_t TxEnable : 1;
00512         uint32_t UINC : 1;
00513         uint32_t unimplemented3 : 1;
00514         uint32_t FRESET : 1;
00515         uint32_t unimplemented4 : 13;
00516         uint32_t FifoSize : 5;
00517         uint32_t PayLoadSize : 3;
00518     } rxBF;
00519 
00520     // Transmit FIFO
00521 
00522     struct {
00523         uint32_t TxNotFullIE : 1;
00524         uint32_t TxHalfFullIE : 1;
00525         uint32_t TxEmptyIE : 1;
00526         uint32_t unimplemented1 : 1;
00527         uint32_t TxAttemptIE : 1;
00528         uint32_t unimplemented2 : 1;
00529         uint32_t RTREnable : 1;
00530         uint32_t TxEnable : 1;
00531         uint32_t UINC : 1;
00532         uint32_t TxRequest : 1;
00533         uint32_t FRESET : 1;
00534         uint32_t unimplemented3 : 5;
00535         uint32_t TxPriority : 5;
00536         uint32_t TxAttempts : 2;
00537         uint32_t unimplemented4 : 1;
00538         uint32_t FifoSize : 5;
00539         uint32_t PayLoadSize : 3;
00540     } txBF;
00541     uint32_t word;
00542     uint8_t byte[4];
00543 } REG_CiFIFOCON;
00544 
00545 // *****************************************************************************
00546 //! FIFO Status Register
00547 
00548 typedef union _REG_CiFIFOSTA {
00549     // Receive FIFO
00550 
00551     struct {
00552         uint32_t RxNotEmptyIF : 1;
00553         uint32_t RxHalfFullIF : 1;
00554         uint32_t RxFullIF : 1;
00555         uint32_t RxOverFlowIF : 1;
00556         uint32_t unimplemented1 : 4;
00557         uint32_t FifoIndex : 5;
00558         uint32_t unimplemented2 : 19;
00559     } rxBF;
00560 
00561     // Transmit FIFO
00562 
00563     struct {
00564         uint32_t TxNotFullIF : 1;
00565         uint32_t TxHalfFullIF : 1;
00566         uint32_t TxEmptyIF : 1;
00567         uint32_t unimplemented1 : 1;
00568         uint32_t TxAttemptIF : 1;
00569         uint32_t TxError : 1;
00570         uint32_t TxLostArbitration : 1;
00571         uint32_t TxAborted : 1;
00572         uint32_t FifoIndex : 5;
00573         uint32_t unimplemented2 : 19;
00574     } txBF;
00575     uint32_t word;
00576     uint8_t byte[4];
00577 } REG_CiFIFOSTA;
00578 
00579 // *****************************************************************************
00580 //! FIFO User Address Register
00581 
00582 typedef union _REG_CiFIFOUA {
00583 
00584     struct {
00585         uint32_t UserAddress : 12;
00586         uint32_t unimplemented1 : 20;
00587     } bF;
00588     uint32_t word;
00589     uint8_t byte[4];
00590 } REG_CiFIFOUA;
00591 
00592 // *****************************************************************************
00593 //! Filter Control Register
00594 
00595 typedef union _REG_CiFLTCON_BYTE {
00596 
00597     struct {
00598         uint32_t BufferPointer : 5;
00599         uint32_t unimplemented1 : 2;
00600         uint32_t Enable : 1;
00601     } bF;
00602     uint8_t byte;
00603 } REG_CiFLTCON_BYTE;
00604 
00605 // *****************************************************************************
00606 //! Filter Object Register
00607 
00608 typedef union _REG_CiFLTOBJ {
00609     CAN_FILTEROBJ_ID bF;
00610     uint32_t word;
00611     uint8_t byte[4];
00612 } REG_CiFLTOBJ;
00613 
00614 // *****************************************************************************
00615 //! Mask Object Register
00616 
00617 typedef union _REG_CiMASK {
00618     CAN_MASKOBJ_ID bF;
00619     uint32_t word;
00620     uint8_t byte[4];
00621 } REG_CiMASK;
00622 
00623 
00624 // *****************************************************************************
00625 // *****************************************************************************
00626 /* MCP2517 Specific */
00627 
00628 // *****************************************************************************
00629 //! Oscillator Control Register
00630 
00631 typedef union _REG_OSC {
00632 
00633     struct {
00634         uint32_t PllEnable : 1;
00635         uint32_t unimplemented1 : 1;
00636         uint32_t OscDisable : 1;
00637         uint32_t unimplemented2 : 1;
00638         uint32_t SCLKDIV : 1;
00639         uint32_t CLKODIV : 2;
00640         uint32_t unimplemented3 : 1;
00641         uint32_t PllReady : 1;
00642         uint32_t unimplemented4 : 1;
00643         uint32_t OscReady : 1;
00644         uint32_t unimplemented5 : 1;
00645         uint32_t SclkReady : 1;
00646         uint32_t unimplemented6 : 19;
00647     } bF;
00648     uint32_t word;
00649     uint8_t byte[4];
00650 } REG_OSC;
00651 
00652 // *****************************************************************************
00653 //! I/O Control Register
00654 
00655 typedef union _REG_IOCON {
00656 
00657     struct {
00658         uint32_t TRIS0 : 1;
00659         uint32_t TRIS1 : 1;
00660         uint32_t unimplemented1 : 2;
00661         uint32_t ClearAutoSleepOnMatch : 1;
00662         uint32_t AutoSleepEnable : 1;
00663         uint32_t XcrSTBYEnable : 1;
00664         uint32_t unimplemented2 : 1;
00665         uint32_t LAT0 : 1;
00666         uint32_t LAT1 : 1;
00667         uint32_t unimplemented3 : 5;
00668         uint32_t HVDETSEL : 1;
00669         uint32_t GPIO0 : 1;
00670         uint32_t GPIO1 : 1;
00671         uint32_t unimplemented4 : 6;
00672         uint32_t PinMode0 : 1;
00673         uint32_t PinMode1 : 1;
00674         uint32_t unimplemented5 : 2;
00675         uint32_t TXCANOpenDrain : 1;
00676         uint32_t SOFOutputEnable : 1;
00677         uint32_t INTPinOpenDrain : 1;
00678         uint32_t unimplemented6 : 1;
00679     } bF;
00680     uint32_t word;
00681     uint8_t byte[4];
00682 } REG_IOCON;
00683 
00684 // *****************************************************************************
00685 //! CRC Regsiter
00686 
00687 typedef union _REG_CRC {
00688 
00689     struct {
00690         uint32_t CRC : 16;
00691         uint32_t CRCERRIF : 1;
00692         uint32_t FERRIF : 1;
00693         uint32_t unimplemented1 : 6;
00694         uint32_t CRCERRIE : 1;
00695         uint32_t FERRIE : 1;
00696         uint32_t unimplemented2 : 6;
00697     } bF;
00698     uint32_t word;
00699     uint8_t byte[4];
00700 } REG_CRC;
00701 
00702 // *****************************************************************************
00703 //! ECC Control Register
00704 
00705 typedef union _REG_ECCCON {
00706 
00707     struct {
00708         uint32_t EccEn : 1;
00709         uint32_t SECIE : 1;
00710         uint32_t DEDIE : 1;
00711         uint32_t unimplemented1 : 5;
00712         uint32_t Parity : 7;
00713         uint32_t unimplemented2 : 17;
00714     } bF;
00715     uint32_t word;
00716     uint8_t byte[4];
00717 } REG_ECCCON;
00718 
00719 // *****************************************************************************
00720 //! ECC Status Register
00721 
00722 typedef union _REG_ECCSTA {
00723 
00724     struct {
00725         uint32_t unimplemented1 : 1;
00726         uint32_t SECIF : 1;
00727         uint32_t DEDIF : 1;
00728         uint32_t unimplemented2 : 13;
00729         uint32_t ErrorAddress : 12;
00730         uint32_t unimplemented3 : 4;
00731     } bF;
00732     uint32_t word;
00733     uint8_t byte[4];
00734 } REG_ECCSTA;
00735 
00736 
00737 // *****************************************************************************
00738 // *****************************************************************************
00739 /* Register Reset Values */
00740 
00741 // *****************************************************************************
00742 /* can_fd_ubp */
00743 
00744 // Control Register Reset Values up to FIFOs
00745 #define N_CAN_CTRL_REGS  20
00746 static uint32_t canControlResetValues[] = {
00747     /* Address 0x000 to 0x00C */
00748 #ifdef CAN_TXQUEUE_IMPLEMENTED
00749     0x04980760, 0x003E0F0F, 0x000E0303, 0x00021000,
00750 #else
00751     0x04880760, 0x003E0F0F, 0x000E0303, 0x00021000,
00752 #endif
00753     /* Address 0x010 to 0x01C */
00754     0x00000000, 0x00000000, 0x40400040, 0x00000000,
00755     /* Address 0x020 to 0x02C */
00756     0x00000000, 0x00000000, 0x00000000, 0x00000000,
00757     /* Address 0x030 to 0x03C */
00758     0x00000000, 0x00200000, 0x00000000, 0x00000000,
00759     /* Address 0x040 to 0x04C */
00760     0x00000400, 0x00000000, 0x00000000, 0x00000000
00761 };
00762 
00763 // FIFO Register Reset Values
00764 #define N_CAN_FIFO_REGS (CAN_FIFO_TOTAL_CHANNELS*CiFIFO_OFFSET)
00765 static uint32_t canFifoResetValues[] = {
00766     0x00600400, 0x00000000, 0x00000000
00767 };
00768 
00769 // Filter Control Register Reset Values
00770 #define N_CAN_FILTER_CTRL_REGS (CAN_FILTER_TOTAL/4)
00771 static uint32_t canFilterControlResetValue = 0x00000000;
00772 
00773 // Filter and Mask Object Reset Values
00774 #define N_CAN_FILTER_OBJ_REGS (CAN_FILTER_TOTAL*CiFILTER_OFFSET)
00775 static uint32_t canFilterObjectResetValues[] = {
00776     0x00000000, 0x00000000
00777 };
00778 
00779 // *****************************************************************************
00780 /* MCP2517 */
00781 
00782 #ifdef MCP2517FD
00783 #define N_MCP2517_CTRL_REGS 5
00784 static uint32_t mcp2517ControlResetValues[] = {
00785     0x00000460, 0x00000003, 0x00000000, 0x00000000, 0x00000000
00786 };
00787 #endif
00788 
00789 #ifdef __cplusplus  // Provide C++ Compatibility
00790 }
00791 #endif
00792 
00793 #endif // _DRV_CANFDSPI_REGISTER_H
00794 
00795 
00796