drv_canfdspi_defines.h

00001 /*******************************************************************************
00002    CAN FD SPI Driver: API Defines Header File
00003 
00004   Company:
00005     Microchip Technology Inc.
00006 
00007   File Name:
00008     drv_canfdspi_defines.h
00009 
00010   Summary:
00011     This header file contains object declarations used in the API.
00012     This also contains device specific defines.
00013 
00014   Description:
00015     None.
00016  *******************************************************************************/
00017 
00018 //DOM-IGNORE-BEGIN
00019 /*******************************************************************************
00020 Copyright (c) 2016 Microchip Technology Inc. and its subsidiaries.
00021 You may use this software and any derivatives exclusively with Microchip products.
00022 
00023 THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
00024 NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
00025 INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
00026 AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP PRODUCTS,
00027 COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
00028 
00029 IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
00030 INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER
00031 RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED
00032 OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT ALLOWED BY LAW,
00033 MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE
00034 WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
00035 
00036 MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE TERMS.
00037  *******************************************************************************/
00038 //DOM-IGNORE-END
00039 
00040 #ifndef _DRV_CANFDSPI_DEFINES_H
00041 #define _DRV_CANFDSPI_DEFINES_H
00042 
00043 // *****************************************************************************
00044 // *****************************************************************************
00045 // Section: Included Files
00046 
00047 #include <stdint.h>
00048 #include <stdbool.h>
00049 #include <stddef.h>
00050 #include <stdlib.h>
00051 
00052 
00053 // DOM-IGNORE-BEGIN
00054 #ifdef __cplusplus  // Provide C++ Compatibility
00055 extern "C" {
00056 #endif
00057 // DOM-IGNORE-END
00058 
00059 
00060 // *****************************************************************************
00061 // *****************************************************************************
00062 // Section: Implementation
00063 
00064 // Device selection
00065 #define MCP2517FD
00066 
00067 // Revision
00068 //#define REV_A
00069 #define REV_B
00070 
00071 // Select ISO/non-ISO CRC
00072 #define ISO_CRC 1
00073 
00074 // Before B0 address of filter registers was fixed
00075 #ifdef REV_A
00076 #define FIXED_FILTER_ADDRESS
00077 #endif
00078 
00079 // Number of implemented FIFOs
00080 #ifndef FPGA
00081 #define CAN_FIFO_08TO15_IMPLEMENTED
00082 #define CAN_FIFO_16TO31_IMPLEMENTED
00083 #endif
00084 
00085 // Number of implemented Filters
00086 #ifndef FPGA
00087 #define CAN_FILTER_08TO15_IMPLEMENTED
00088 #define CAN_FILTER_16TO31_IMPLEMENTED
00089 #endif
00090 
00091 // Internal oscillator implemented
00092 #ifdef MCP2520FD
00093 #define CAN_INTERNAL_OSC_PRESENT
00094 #endif
00095 
00096 // Restricted Operation Mode implemented
00097 #ifdef REV_B
00098 #define CAN_RESTRICTED_MODE_PRESENT
00099 #endif
00100 
00101 // Transmit Queue
00102 #ifdef REV_B
00103 #define CAN_TXQUEUE_IMPLEMENTED
00104 #endif
00105 
00106 // Up to A1 silicon we had to multiply user address by 4.
00107 #ifdef REV_A
00108 #define USERADDRESS_TIMES_FOUR
00109 #endif
00110 
00111 // Maximum Size of TX/RX Object
00112 #define MAX_MSG_SIZE 76
00113 
00114 // Maximum number of data bytes in message
00115 #define MAX_DATA_BYTES 64
00116 
00117 // *****************************************************************************
00118 // *****************************************************************************
00119 // Section: Object definitions
00120 
00121 //! CAN FIFO Channels
00122 
00123     typedef enum {
00124         CAN_FIFO_CH0,
00125         CAN_FIFO_CH1,
00126         CAN_FIFO_CH2,
00127         CAN_FIFO_CH3,
00128         CAN_FIFO_CH4,
00129         CAN_FIFO_CH5,
00130         CAN_FIFO_CH6,
00131         CAN_FIFO_CH7,
00132 #ifdef CAN_FIFO_08TO15_IMPLEMENTED
00133         CAN_FIFO_CH8,
00134         CAN_FIFO_CH9,
00135         CAN_FIFO_CH10,
00136         CAN_FIFO_CH11,
00137         CAN_FIFO_CH12,
00138         CAN_FIFO_CH13,
00139         CAN_FIFO_CH14,
00140         CAN_FIFO_CH15,
00141 #endif
00142 #ifdef CAN_FIFO_16TO31_IMPLEMENTED
00143         CAN_FIFO_CH16,
00144         CAN_FIFO_CH17,
00145         CAN_FIFO_CH18,
00146         CAN_FIFO_CH19,
00147         CAN_FIFO_CH20,
00148         CAN_FIFO_CH21,
00149         CAN_FIFO_CH22,
00150         CAN_FIFO_CH23,
00151         CAN_FIFO_CH24,
00152         CAN_FIFO_CH25,
00153         CAN_FIFO_CH26,
00154         CAN_FIFO_CH27,
00155         CAN_FIFO_CH28,
00156         CAN_FIFO_CH29,
00157         CAN_FIFO_CH30,
00158         CAN_FIFO_CH31,
00159 #endif
00160         CAN_FIFO_TOTAL_CHANNELS
00161     }
00162     CAN_FIFO_CHANNEL;
00163 
00164 #ifdef CAN_TXQUEUE_IMPLEMENTED
00165 #define CAN_FIFO_FIRST_CHANNEL  CAN_FIFO_CH1
00166 #define CAN_TXQUEUE_CH0         CAN_FIFO_CH0
00167 #else
00168 #define CAN_FIFO_FIRST_CHANNEL  CAN_FIFO_CH0
00169 #endif
00170 
00171 //! CAN Filter Channels
00172 
00173     typedef enum {
00174         CAN_FILTER0,
00175         CAN_FILTER1,
00176         CAN_FILTER2,
00177         CAN_FILTER3,
00178         CAN_FILTER4,
00179         CAN_FILTER5,
00180         CAN_FILTER6,
00181         CAN_FILTER7,
00182 #ifdef CAN_FILTER_08TO15_IMPLEMENTED
00183         CAN_FILTER8,
00184         CAN_FILTER9,
00185         CAN_FILTER10,
00186         CAN_FILTER11,
00187         CAN_FILTER12,
00188         CAN_FILTER13,
00189         CAN_FILTER14,
00190         CAN_FILTER15,
00191 #endif
00192 #ifdef CAN_FILTER_16TO31_IMPLEMENTED
00193         CAN_FILTER16,
00194         CAN_FILTER17,
00195         CAN_FILTER18,
00196         CAN_FILTER19,
00197         CAN_FILTER20,
00198         CAN_FILTER21,
00199         CAN_FILTER22,
00200         CAN_FILTER23,
00201         CAN_FILTER24,
00202         CAN_FILTER25,
00203         CAN_FILTER26,
00204         CAN_FILTER27,
00205         CAN_FILTER28,
00206         CAN_FILTER29,
00207         CAN_FILTER30,
00208         CAN_FILTER31,
00209 #endif
00210         CAN_FILTER_TOTAL,
00211     } CAN_FILTER;
00212 
00213 
00214 //! CAN Operation Modes
00215 
00216     typedef enum {
00217         CAN_NORMAL_MODE = 0x00,
00218         CAN_SLEEP_MODE = 0x01,
00219         CAN_INTERNAL_LOOPBACK_MODE = 0x02,
00220         CAN_LISTEN_ONLY_MODE = 0x03,
00221         CAN_CONFIGURATION_MODE = 0x04,
00222         CAN_EXTERNAL_LOOPBACK_MODE = 0x05,
00223         CAN_CLASSIC_MODE = 0x06,
00224         CAN_RESTRICTED_MODE = 0x07,
00225         CAN_INVALID_MODE = 0xFF
00226     } CAN_OPERATION_MODE;
00227 
00228 //! Transmit Bandwidth Sharing
00229 
00230     typedef enum {
00231         CAN_TXBWS_NO_DELAY,
00232         CAN_TXBWS_2,
00233         CAN_TXBWS_4,
00234         CAN_TXBWS_8,
00235         CAN_TXBWS_16,
00236         CAN_TXBWS_32,
00237         CAN_TXBWS_64,
00238         CAN_TXBWS_128,
00239         CAN_TXBWS_256,
00240         CAN_TXBWS_512,
00241         CAN_TXBWS_1024,
00242         CAN_TXBWS_2048,
00243         CAN_TXBWS_4096
00244     } CAN_TX_BANDWITH_SHARING;
00245 
00246 //! Wake-up Filter Time
00247 
00248     typedef enum {
00249         CAN_WFT00,
00250         CAN_WFT01,
00251         CAN_WFT10,
00252         CAN_WFT11
00253     } CAN_WAKEUP_FILTER_TIME;
00254 
00255 //! Data Byte Filter Number
00256 
00257     typedef enum {
00258         CAN_DNET_FILTER_DISABLE = 0,
00259         CAN_DNET_FILTER_SIZE_1_BIT,
00260         CAN_DNET_FILTER_SIZE_2_BIT,
00261         CAN_DNET_FILTER_SIZE_3_BIT,
00262         CAN_DNET_FILTER_SIZE_4_BIT,
00263         CAN_DNET_FILTER_SIZE_5_BIT,
00264         CAN_DNET_FILTER_SIZE_6_BIT,
00265         CAN_DNET_FILTER_SIZE_7_BIT,
00266         CAN_DNET_FILTER_SIZE_8_BIT,
00267         CAN_DNET_FILTER_SIZE_9_BIT,
00268         CAN_DNET_FILTER_SIZE_10_BIT,
00269         CAN_DNET_FILTER_SIZE_11_BIT,
00270         CAN_DNET_FILTER_SIZE_12_BIT,
00271         CAN_DNET_FILTER_SIZE_13_BIT,
00272         CAN_DNET_FILTER_SIZE_14_BIT,
00273         CAN_DNET_FILTER_SIZE_15_BIT,
00274         CAN_DNET_FILTER_SIZE_16_BIT,
00275         CAN_DNET_FILTER_SIZE_17_BIT,
00276         CAN_DNET_FILTER_SIZE_18_BIT
00277     } CAN_DNET_FILTER_SIZE;
00278 
00279 //! FIFO Payload Size
00280 
00281     typedef enum {
00282         CAN_PLSIZE_8,
00283         CAN_PLSIZE_12,
00284         CAN_PLSIZE_16,
00285         CAN_PLSIZE_20,
00286         CAN_PLSIZE_24,
00287         CAN_PLSIZE_32,
00288         CAN_PLSIZE_48,
00289         CAN_PLSIZE_64
00290     } CAN_FIFO_PLSIZE;
00291 
00292 //! CAN Configure
00293 
00294     typedef struct _CAN_CONFIG {
00295         uint32_t DNetFilterCount : 5;
00296         uint32_t IsoCrcEnable : 1;
00297         uint32_t ProtocolExpectionEventDisable : 1;
00298         uint32_t WakeUpFilterEnable : 1;
00299         uint32_t WakeUpFilterTime : 2;
00300         uint32_t BitRateSwitchDisable : 1;
00301         uint32_t RestrictReTxAttempts : 1;
00302         uint32_t EsiInGatewayMode : 1;
00303         uint32_t SystemErrorToListenOnly : 1;
00304         uint32_t StoreInTEF : 1;
00305         uint32_t TXQEnable : 1;
00306         uint32_t TxBandWidthSharing : 4;
00307     } CAN_CONFIG;
00308 
00309 //! CAN Transmit Channel Configure
00310 
00311     typedef struct _CAN_TX_FIFO_CONFIG {
00312         uint32_t RTREnable : 1;
00313         uint32_t TxPriority : 5;
00314         uint32_t TxAttempts : 2;
00315         uint32_t FifoSize : 5;
00316         uint32_t PayLoadSize : 3;
00317     } CAN_TX_FIFO_CONFIG;
00318 
00319 //! CAN Transmit Queue Configure
00320 
00321     typedef struct _CAN_TX_QUEUE_CONFIG {
00322         uint32_t TxPriority : 5;
00323         uint32_t TxAttempts : 2;
00324         uint32_t FifoSize : 5;
00325         uint32_t PayLoadSize : 3;
00326     } CAN_TX_QUEUE_CONFIG;
00327 
00328 //! CAN Receive Channel Configure
00329 
00330     typedef struct _CAN_RX_FIFO_CONFIG {
00331         uint32_t RxTimeStampEnable : 1;
00332         uint32_t FifoSize : 5;
00333         uint32_t PayLoadSize : 3;
00334     } CAN_RX_FIFO_CONFIG;
00335 
00336 //! CAN Transmit Event FIFO Configure
00337 
00338     typedef struct _CAN_TEF_CONFIG {
00339         uint32_t TimeStampEnable : 1;
00340         uint32_t FifoSize : 5;
00341     } CAN_TEF_CONFIG;
00342 
00343     /* CAN Message Objects */
00344 
00345 //! CAN Message Object ID
00346 
00347     typedef struct _CAN_MSGOBJ_ID {
00348         uint32_t SID : 11;
00349         uint32_t EID : 18;
00350         uint32_t SID11 : 1;
00351         uint32_t unimplemented1 : 2;
00352     } CAN_MSGOBJ_ID;
00353 
00354 //! CAN Data Length Code
00355 
00356     typedef enum {
00357         CAN_DLC_0,
00358         CAN_DLC_1,
00359         CAN_DLC_2,
00360         CAN_DLC_3,
00361         CAN_DLC_4,
00362         CAN_DLC_5,
00363         CAN_DLC_6,
00364         CAN_DLC_7,
00365         CAN_DLC_8,
00366         CAN_DLC_12,
00367         CAN_DLC_16,
00368         CAN_DLC_20,
00369         CAN_DLC_24,
00370         CAN_DLC_32,
00371         CAN_DLC_48,
00372         CAN_DLC_64
00373     } CAN_DLC;
00374 
00375 //! CAN TX Message Object Control
00376 
00377     typedef struct _CAN_TX_MSGOBJ_CTRL {
00378         uint32_t DLC : 4;
00379         uint32_t IDE : 1;
00380         uint32_t RTR : 1;
00381         uint32_t BRS : 1;
00382         uint32_t FDF : 1;
00383         uint32_t ESI : 1;
00384         uint32_t SEQ : 7;
00385         uint32_t unimplemented1 : 16;
00386     } CAN_TX_MSGOBJ_CTRL;
00387 
00388 //! CAN RX Message Object Control
00389 
00390     typedef struct _CAN_RX_MSGOBJ_CTRL {
00391         uint32_t DLC : 4;
00392         uint32_t IDE : 1;
00393         uint32_t RTR : 1;
00394         uint32_t BRS : 1;
00395         uint32_t FDF : 1;
00396         uint32_t ESI : 1;
00397         uint32_t unimplemented1 : 2;
00398         uint32_t FilterHit : 5;
00399         uint32_t unimplemented2 : 16;
00400     } CAN_RX_MSGOBJ_CTRL;
00401 
00402 //! CAN Message Time Stamp
00403     typedef uint32_t CAN_MSG_TIMESTAMP;
00404 
00405 //! CAN TX Message Object
00406 
00407     typedef union _CAN_TX_MSGOBJ {
00408 
00409         struct {
00410             CAN_MSGOBJ_ID id;
00411             CAN_TX_MSGOBJ_CTRL ctrl;
00412             CAN_MSG_TIMESTAMP timeStamp;
00413         } bF;
00414         uint32_t word[3];
00415         uint8_t byte[12];
00416     } CAN_TX_MSGOBJ;
00417 
00418 //! CAN RX Message Object
00419 
00420     typedef union _CAN_RX_MSGOBJ {
00421 
00422         struct {
00423             CAN_MSGOBJ_ID id;
00424             CAN_RX_MSGOBJ_CTRL ctrl;
00425             CAN_MSG_TIMESTAMP timeStamp;
00426         } bF;
00427         uint32_t word[3];
00428         uint8_t byte[12];
00429     } CAN_RX_MSGOBJ;
00430 
00431 //! CAN TEF Message Object
00432 
00433     typedef union _CAN_TEF_MSGOBJ {
00434 
00435         struct {
00436             CAN_MSGOBJ_ID id;
00437             CAN_TX_MSGOBJ_CTRL ctrl;
00438             CAN_MSG_TIMESTAMP timeStamp;
00439         } bF;
00440         uint32_t word[3];
00441         uint8_t byte[12];
00442     } CAN_TEF_MSGOBJ;
00443 
00444 //! CAN Filter Object ID
00445 
00446     typedef struct _CAN_FILTEROBJ_ID {
00447         uint32_t SID : 11;
00448         uint32_t EID : 18;
00449         uint32_t SID11 : 1;
00450         uint32_t EXIDE : 1;
00451         uint32_t unimplemented1 : 1;
00452     } CAN_FILTEROBJ_ID;
00453 
00454 //! CAN Mask Object ID
00455 
00456     typedef struct _CAN_MASKOBJ_ID {
00457         uint32_t MSID : 11;
00458         uint32_t MEID : 18;
00459         uint32_t MSID11 : 1;
00460         uint32_t MIDE : 1;
00461         uint32_t unimplemented1 : 1;
00462     } CAN_MASKOBJ_ID;
00463 
00464 //! CAN RX FIFO Status
00465 
00466     typedef enum {
00467         CAN_RX_FIFO_EMPTY = 0,
00468         CAN_RX_FIFO_STATUS_MASK = 0x0F,
00469         CAN_RX_FIFO_NOT_EMPTY = 0x01,
00470         CAN_RX_FIFO_HALF_FULL = 0x02,
00471         CAN_RX_FIFO_FULL = 0x04,
00472         CAN_RX_FIFO_OVERFLOW = 0x08
00473     } CAN_RX_FIFO_STATUS;
00474 
00475 //! CAN TX FIFO Status
00476 
00477     typedef enum {
00478         CAN_TX_FIFO_FULL = 0,
00479         CAN_TX_FIFO_STATUS_MASK = 0x1F7,
00480         CAN_TX_FIFO_NOT_FULL = 0x01,
00481         CAN_TX_FIFO_HALF_FULL = 0x02,
00482         CAN_TX_FIFO_EMPTY = 0x04,
00483         CAN_TX_FIFO_ATTEMPTS_EXHAUSTED = 0x10,
00484         CAN_TX_FIFO_ERROR = 0x20,
00485         CAN_TX_FIFO_ARBITRATION_LOST = 0x40,
00486         CAN_TX_FIFO_ABORTED = 0x80,
00487         CAN_TX_FIFO_TRANSMITTING = 0x100
00488     } CAN_TX_FIFO_STATUS;
00489 
00490 //! CAN TEF FIFO Status
00491 
00492     typedef enum {
00493         CAN_TEF_FIFO_EMPTY = 0,
00494         CAN_TEF_FIFO_STATUS_MASK = 0x0F,
00495         CAN_TEF_FIFO_NOT_EMPTY = 0x01,
00496         CAN_TEF_FIFO_HALF_FULL = 0x02,
00497         CAN_TEF_FIFO_FULL = 0x04,
00498         CAN_TEF_FIFO_OVERFLOW = 0x08
00499     } CAN_TEF_FIFO_STATUS;
00500 
00501 //! CAN Module Event (Interrupts)
00502 
00503     typedef enum {
00504         CAN_NO_EVENT = 0,
00505         CAN_ALL_EVENTS = 0xFF1F,
00506         CAN_TX_EVENT = 0x0001,
00507         CAN_RX_EVENT = 0x0002,
00508         CAN_TIME_BASE_COUNTER_EVENT = 0x0004,
00509         CAN_OPERATION_MODE_CHANGE_EVENT = 0x0008,
00510         CAN_TEF_EVENT = 0x0010,
00511 
00512         CAN_RAM_ECC_EVENT = 0x0100,
00513         CAN_SPI_CRC_EVENT = 0x0200,
00514         CAN_TX_ATTEMPTS_EVENT = 0x0400,
00515         CAN_RX_OVERFLOW_EVENT = 0x0800,
00516         CAN_SYSTEM_ERROR_EVENT = 0x1000,
00517         CAN_BUS_ERROR_EVENT = 0x2000,
00518         CAN_BUS_WAKEUP_EVENT = 0x4000,
00519         CAN_RX_INVALID_MESSAGE_EVENT = 0x8000
00520     } CAN_MODULE_EVENT;
00521 
00522 //! CAN TX FIFO Event (Interrupts)
00523 
00524     typedef enum {
00525         CAN_TX_FIFO_NO_EVENT = 0,
00526         CAN_TX_FIFO_ALL_EVENTS = 0x17,
00527         CAN_TX_FIFO_NOT_FULL_EVENT = 0x01,
00528         CAN_TX_FIFO_HALF_FULL_EVENT = 0x02,
00529         CAN_TX_FIFO_EMPTY_EVENT = 0x04,
00530         CAN_TX_FIFO_ATTEMPTS_EXHAUSTED_EVENT = 0x10
00531     } CAN_TX_FIFO_EVENT;
00532 
00533 //! CAN RX FIFO Event (Interrupts)
00534 
00535     typedef enum {
00536         CAN_RX_FIFO_NO_EVENT = 0,
00537         CAN_RX_FIFO_ALL_EVENTS = 0x0F,
00538         CAN_RX_FIFO_NOT_EMPTY_EVENT = 0x01,
00539         CAN_RX_FIFO_HALF_FULL_EVENT = 0x02,
00540         CAN_RX_FIFO_FULL_EVENT = 0x04,
00541         CAN_RX_FIFO_OVERFLOW_EVENT = 0x08
00542     } CAN_RX_FIFO_EVENT;
00543 
00544 //! CAN TEF FIFO Event (Interrupts)
00545 
00546     typedef enum {
00547         CAN_TEF_FIFO_NO_EVENT = 0,
00548         CAN_TEF_FIFO_ALL_EVENTS = 0x0F,
00549         CAN_TEF_FIFO_NOT_EMPTY_EVENT = 0x01,
00550         CAN_TEF_FIFO_HALF_FULL_EVENT = 0x02,
00551         CAN_TEF_FIFO_FULL_EVENT = 0x04,
00552         CAN_TEF_FIFO_OVERFLOW_EVENT = 0x08
00553     } CAN_TEF_FIFO_EVENT;
00554 
00555 //! CAN Bit Time Setup: Arbitration/Data Bit Phase
00556 
00557     typedef enum {
00558         CAN_500K_1M,    // 0x00
00559         CAN_500K_2M,    // 0x01
00560         CAN_500K_3M,
00561         CAN_500K_4M,
00562         CAN_500K_5M,    // 0x04
00563         CAN_500K_6M7,
00564         CAN_500K_8M,    // 0x06
00565         CAN_500K_10M,
00566         CAN_250K_500K,  // 0x08
00567         CAN_250K_833K,
00568         CAN_250K_1M,
00569         CAN_250K_1M5,
00570         CAN_250K_2M,
00571         CAN_250K_3M,
00572         CAN_250K_4M,
00573         CAN_1000K_4M,   // 0x0f
00574         CAN_1000K_8M,
00575         CAN_125K_500K   // 0x11
00576     } CAN_BITTIME_SETUP;
00577 
00578 //! CAN Nominal Bit Time Setup
00579 
00580     typedef enum {
00581         CAN_NBT_125K,
00582         CAN_NBT_250K,
00583         CAN_NBT_500K,
00584         CAN_NBT_1M
00585     } CAN_NOMINAL_BITTIME_SETUP;
00586 
00587 //! CAN Data Bit Time Setup
00588 
00589     typedef enum {
00590         CAN_DBT_500K,
00591         CAN_DBT_833K,
00592         CAN_DBT_1M,
00593         CAN_DBT_1M5,
00594         CAN_DBT_2M,
00595         CAN_DBT_3M,
00596         CAN_DBT_4M,
00597         CAN_DBT_5M,
00598         CAN_DBT_6M7,
00599         CAN_DBT_8M,
00600         CAN_DBT_10M
00601     } CAN_DATA_BITTIME_SETUP;
00602 
00603 //! Secondary Sample Point Mode
00604 
00605     typedef enum {
00606         CAN_SSP_MODE_OFF,
00607         CAN_SSP_MODE_MANUAL,
00608         CAN_SSP_MODE_AUTO
00609     } CAN_SSP_MODE;
00610 
00611 //! CAN Error State
00612 
00613     typedef enum {
00614         CAN_ERROR_FREE_STATE = 0,
00615         CAN_ERROR_ALL = 0x3F,
00616         CAN_TX_RX_WARNING_STATE = 0x01,
00617         CAN_RX_WARNING_STATE = 0x02,
00618         CAN_TX_WARNING_STATE = 0x04,
00619         CAN_RX_BUS_PASSIVE_STATE = 0x08,
00620         CAN_TX_BUS_PASSIVE_STATE = 0x10,
00621         CAN_TX_BUS_OFF_STATE = 0x20
00622     } CAN_ERROR_STATE;
00623 
00624 //! CAN Time Stamp Mode Select
00625 
00626     typedef enum {
00627         CAN_TS_SOF = 0x00,
00628         CAN_TS_EOF = 0x01,
00629         CAN_TS_RES = 0x02
00630     } CAN_TS_MODE;
00631 
00632 //! CAN ECC EVENT
00633 
00634     typedef enum {
00635         CAN_ECC_NO_EVENT = 0x00,
00636         CAN_ECC_ALL_EVENTS = 0x06,
00637         CAN_ECC_SEC_EVENT = 0x02,
00638         CAN_ECC_DED_EVENT = 0x04
00639     } CAN_ECC_EVENT;
00640 
00641 //! CAN CRC EVENT
00642 
00643     typedef enum {
00644         CAN_CRC_NO_EVENT = 0x00,
00645         CAN_CRC_ALL_EVENTS = 0x03,
00646         CAN_CRC_CRCERR_EVENT = 0x01,
00647         CAN_CRC_FORMERR_EVENT = 0x02
00648     } CAN_CRC_EVENT;
00649 
00650 //! GPIO Pin Position
00651 
00652     typedef enum {
00653         GPIO_PIN_0,
00654         GPIO_PIN_1
00655     } GPIO_PIN_POS;
00656 
00657 //! GPIO Pin Modes
00658 
00659     typedef enum {
00660         GPIO_MODE_INT,
00661         GPIO_MODE_GPIO
00662     } GPIO_PIN_MODE;
00663 
00664 //! GPIO Pin Directions
00665 
00666     typedef enum {
00667         GPIO_OUTPUT,
00668         GPIO_INPUT
00669     } GPIO_PIN_DIRECTION;
00670 
00671 //! GPIO Open Drain Mode
00672 
00673     typedef enum {
00674         GPIO_PUSH_PULL,
00675         GPIO_OPEN_DRAIN
00676     } GPIO_OPEN_DRAIN_MODE;
00677 
00678 //! GPIO Pin State
00679 
00680     typedef enum {
00681         GPIO_LOW,
00682         GPIO_HIGH
00683     } GPIO_PIN_STATE;
00684 
00685 //! Clock Output Mode
00686 
00687     typedef enum {
00688         GPIO_CLKO_CLOCK,
00689         GPIO_CLKO_SOF
00690     } GPIO_CLKO_MODE;
00691 
00692 //! CAN Bus Diagnostic flags
00693 
00694     typedef struct _CAN_BUS_DIAG_FLAGS {
00695         uint32_t NBIT0_ERR : 1;
00696         uint32_t NBIT1_ERR : 1;
00697         uint32_t NACK_ERR : 1;
00698         uint32_t NFORM_ERR : 1;
00699         uint32_t NSTUFF_ERR : 1;
00700         uint32_t NCRC_ERR : 1;
00701         uint32_t unimplemented1 : 1;
00702         uint32_t TXBO_ERR : 1;
00703         uint32_t DBIT0_ERR : 1;
00704         uint32_t DBIT1_ERR : 1;
00705         uint32_t unimplemented2 : 1;
00706         uint32_t DFORM_ERR : 1;
00707         uint32_t DSTUFF_ERR : 1;
00708         uint32_t DCRC_ERR : 1;
00709         uint32_t ESI : 1;
00710         uint32_t DLC_MISMATCH : 1;
00711     } CAN_BUS_DIAG_FLAGS;
00712 
00713 //! CAN Bus Diagnostic Error Counts
00714 
00715     typedef struct _CAN_BUS_ERROR_COUNT {
00716         uint8_t NREC;
00717         uint8_t NTEC;
00718         uint8_t DREC;
00719         uint8_t DTEC;
00720     } CAN_BUS_ERROR_COUNT;
00721 
00722 //! CAN BUS DIAGNOSTICS
00723 
00724     typedef union _CAN_BUS_DIAGNOSTIC {
00725 
00726         struct {
00727             CAN_BUS_ERROR_COUNT errorCount;
00728             uint16_t errorFreeMsgCount;
00729             CAN_BUS_DIAG_FLAGS flag;
00730         } bF;
00731         uint32_t word[2];
00732         uint8_t byte[8];
00733     } CAN_BUS_DIAGNOSTIC;
00734 
00735 //! TXREQ Channel Bits
00736 // Multiple channels can be or'ed together
00737 
00738     typedef enum {
00739         CAN_TXREQ_CH0 = 0x00000001,
00740         CAN_TXREQ_CH1 = 0x00000002,
00741         CAN_TXREQ_CH2 = 0x00000004,
00742         CAN_TXREQ_CH3 = 0x00000008,
00743         CAN_TXREQ_CH4 = 0x00000010,
00744         CAN_TXREQ_CH5 = 0x00000020,
00745         CAN_TXREQ_CH6 = 0x00000040,
00746         CAN_TXREQ_CH7 = 0x00000080,
00747 
00748         CAN_TXREQ_CH8 = 0x00000100,
00749         CAN_TXREQ_CH9 = 0x00000200,
00750         CAN_TXREQ_CH10 = 0x00000400,
00751         CAN_TXREQ_CH11 = 0x00000800,
00752         CAN_TXREQ_CH12 = 0x00001000,
00753         CAN_TXREQ_CH13 = 0x00002000,
00754         CAN_TXREQ_CH14 = 0x00004000,
00755         CAN_TXREQ_CH15 = 0x00008000,
00756 
00757         CAN_TXREQ_CH16 = 0x00010000,
00758         CAN_TXREQ_CH17 = 0x00020000,
00759         CAN_TXREQ_CH18 = 0x00040000,
00760         CAN_TXREQ_CH19 = 0x00080000,
00761         CAN_TXREQ_CH20 = 0x00100000,
00762         CAN_TXREQ_CH21 = 0x00200000,
00763         CAN_TXREQ_CH22 = 0x00400000,
00764         CAN_TXREQ_CH23 = 0x00800000,
00765 
00766         CAN_TXREQ_CH24 = 0x01000000,
00767         CAN_TXREQ_CH25 = 0x02000000,
00768         CAN_TXREQ_CH26 = 0x04000000,
00769         CAN_TXREQ_CH27 = 0x08000000,
00770         CAN_TXREQ_CH28 = 0x10000000,
00771         CAN_TXREQ_CH29 = 0x20000000,
00772         CAN_TXREQ_CH30 = 0x40000000,
00773         CAN_TXREQ_CH31 = 0x80000000
00774     } CAN_TXREQ_CHANNEL;
00775 
00776 //! Oscillator Control
00777 
00778     typedef struct _CAN_OSC_CTRL {
00779         uint32_t PllEnable : 1;
00780         uint32_t OscDisable : 1;
00781         uint32_t SclkDivide : 1;
00782         uint32_t ClkOutDivide : 2;
00783     } CAN_OSC_CTRL;
00784 
00785 //! Oscillator Status
00786 
00787     typedef struct _CAN_OSC_STATUS {
00788         uint32_t PllReady : 1;
00789         uint32_t OscReady : 1;
00790         uint32_t SclkReady : 1;
00791     } CAN_OSC_STATUS;
00792 
00793 //! ICODE
00794 
00795     typedef enum {
00796         CAN_ICODE_FIFO_CH0,
00797         CAN_ICODE_FIFO_CH1,
00798         CAN_ICODE_FIFO_CH2,
00799         CAN_ICODE_FIFO_CH3,
00800         CAN_ICODE_FIFO_CH4,
00801         CAN_ICODE_FIFO_CH5,
00802         CAN_ICODE_FIFO_CH6,
00803         CAN_ICODE_FIFO_CH7,
00804 #ifdef CAN_FIFO_08TO15_IMPLEMENTED
00805         CAN_ICODE_FIFO_CH8,
00806         CAN_ICODE_FIFO_CH9,
00807         CAN_ICODE_FIFO_CH10,
00808         CAN_ICODE_FIFO_CH11,
00809         CAN_ICODE_FIFO_CH12,
00810         CAN_ICODE_FIFO_CH13,
00811         CAN_ICODE_FIFO_CH14,
00812         CAN_ICODE_FIFO_CH15,
00813 #endif
00814 #ifdef CAN_FIFO_16TO31_IMPLEMENTED
00815         CAN_ICODE_FIFO_CH16,
00816         CAN_ICODE_FIFO_CH17,
00817         CAN_ICODE_FIFO_CH18,
00818         CAN_ICODE_FIFO_CH19,
00819         CAN_ICODE_FIFO_CH20,
00820         CAN_ICODE_FIFO_CH21,
00821         CAN_ICODE_FIFO_CH22,
00822         CAN_ICODE_FIFO_CH23,
00823         CAN_ICODE_FIFO_CH24,
00824         CAN_ICODE_FIFO_CH25,
00825         CAN_ICODE_FIFO_CH26,
00826         CAN_ICODE_FIFO_CH27,
00827         CAN_ICODE_FIFO_CH28,
00828         CAN_ICODE_FIFO_CH29,
00829         CAN_ICODE_FIFO_CH30,
00830         CAN_ICODE_FIFO_CH31,
00831 #endif
00832         CAN_ICODE_TOTAL_CHANNELS,
00833         CAN_ICODE_NO_INT = 0x40,
00834         CAN_ICODE_CERRIF,
00835         CAN_ICODE_WAKIF,
00836         CAN_ICODE_RXOVIF,
00837         CAN_ICODE_ADDRERR_SERRIF,
00838         CAN_ICODE_MABOV_SERRIF,
00839         CAN_ICODE_TBCIF,
00840         CAN_ICODE_MODIF,
00841         CAN_ICODE_IVMIF,
00842         CAN_ICODE_TEFIF,
00843         CAN_ICODE_TXATIF,
00844         CAN_ICODE_RESERVED
00845     } CAN_ICODE;
00846 
00847 //! RXCODE
00848 
00849     typedef enum {
00850         CAN_RXCODE_FIFO_CH0,
00851         CAN_RXCODE_FIFO_CH1,
00852         CAN_RXCODE_FIFO_CH2,
00853         CAN_RXCODE_FIFO_CH3,
00854         CAN_RXCODE_FIFO_CH4,
00855         CAN_RXCODE_FIFO_CH5,
00856         CAN_RXCODE_FIFO_CH6,
00857         CAN_RXCODE_FIFO_CH7,
00858 #ifdef CAN_FIFO_08TO15_IMPLEMENTED
00859         CAN_RXCODE_FIFO_CH8,
00860         CAN_RXCODE_FIFO_CH9,
00861         CAN_RXCODE_FIFO_CH10,
00862         CAN_RXCODE_FIFO_CH11,
00863         CAN_RXCODE_FIFO_CH12,
00864         CAN_RXCODE_FIFO_CH13,
00865         CAN_RXCODE_FIFO_CH14,
00866         CAN_RXCODE_FIFO_CH15,
00867 #endif
00868 #ifdef CAN_FIFO_16TO31_IMPLEMENTED
00869         CAN_RXCODE_FIFO_CH16,
00870         CAN_RXCODE_FIFO_CH17,
00871         CAN_RXCODE_FIFO_CH18,
00872         CAN_RXCODE_FIFO_CH19,
00873         CAN_RXCODE_FIFO_CH20,
00874         CAN_RXCODE_FIFO_CH21,
00875         CAN_RXCODE_FIFO_CH22,
00876         CAN_RXCODE_FIFO_CH23,
00877         CAN_RXCODE_FIFO_CH24,
00878         CAN_RXCODE_FIFO_CH25,
00879         CAN_RXCODE_FIFO_CH26,
00880         CAN_RXCODE_FIFO_CH27,
00881         CAN_RXCODE_FIFO_CH28,
00882         CAN_RXCODE_FIFO_CH29,
00883         CAN_RXCODE_FIFO_CH30,
00884         CAN_RXCODE_FIFO_CH31,
00885 #endif
00886         CAN_RXCODE_TOTAL_CHANNELS,
00887         CAN_RXCODE_NO_INT = 0x40,
00888         CAN_RXCODE_RESERVED
00889     } CAN_RXCODE;
00890 
00891 //! TXCODE
00892 
00893     typedef enum {
00894         CAN_TXCODE_FIFO_CH0,
00895         CAN_TXCODE_FIFO_CH1,
00896         CAN_TXCODE_FIFO_CH2,
00897         CAN_TXCODE_FIFO_CH3,
00898         CAN_TXCODE_FIFO_CH4,
00899         CAN_TXCODE_FIFO_CH5,
00900         CAN_TXCODE_FIFO_CH6,
00901         CAN_TXCODE_FIFO_CH7,
00902 #ifdef CAN_FIFO_08TO15_IMPLEMENTED
00903         CAN_TXCODE_FIFO_CH8,
00904         CAN_TXCODE_FIFO_CH9,
00905         CAN_TXCODE_FIFO_CH10,
00906         CAN_TXCODE_FIFO_CH11,
00907         CAN_TXCODE_FIFO_CH12,
00908         CAN_TXCODE_FIFO_CH13,
00909         CAN_TXCODE_FIFO_CH14,
00910         CAN_TXCODE_FIFO_CH15,
00911 #endif
00912 #ifdef CAN_FIFO_16TO31_IMPLEMENTED
00913         CAN_TXCODE_FIFO_CH16,
00914         CAN_TXCODE_FIFO_CH17,
00915         CAN_TXCODE_FIFO_CH18,
00916         CAN_TXCODE_FIFO_CH19,
00917         CAN_TXCODE_FIFO_CH20,
00918         CAN_TXCODE_FIFO_CH21,
00919         CAN_TXCODE_FIFO_CH22,
00920         CAN_TXCODE_FIFO_CH23,
00921         CAN_TXCODE_FIFO_CH24,
00922         CAN_TXCODE_FIFO_CH25,
00923         CAN_TXCODE_FIFO_CH26,
00924         CAN_TXCODE_FIFO_CH27,
00925         CAN_TXCODE_FIFO_CH28,
00926         CAN_TXCODE_FIFO_CH29,
00927         CAN_TXCODE_FIFO_CH30,
00928         CAN_TXCODE_FIFO_CH31,
00929 #endif
00930         CAN_TXCODE_TOTAL_CHANNELS,
00931         CAN_TXCODE_NO_INT = 0x40,
00932         CAN_TXCODE_RESERVED
00933     } CAN_TXCODE;
00934 
00935 //! System Clock Selection
00936 
00937     typedef enum {
00938         CAN_SYSCLK_40M,
00939         CAN_SYSCLK_20M,
00940         CAN_SYSCLK_10M
00941     } CAN_SYSCLK_SPEED;
00942 
00943 //! CLKO Divide
00944 
00945     typedef enum {
00946         OSC_CLKO_DIV1,
00947         OSC_CLKO_DIV2,
00948         OSC_CLKO_DIV4,
00949         OSC_CLKO_DIV10
00950     } OSC_CLKO_DIVIDE;
00951 
00952 #ifdef __cplusplus  // Provide C++ Compatibility
00953 }
00954 #endif
00955 
00956 #endif // _DRV_CANFDSPI_DEFINES_H
00957