drv_canfdspi_api.h

00001 /*******************************************************************************
00002   CAN FD SPI Driver: API Functions Header File
00003 
00004   Company:
00005     Microchip Technology Inc.
00006 
00007   File Name:
00008     drv_canfdspi_api.h
00009 
00010   Summary:
00011     This header file provides the API function prototypes for the CAN FD SPI
00012     controller.
00013 
00014   Description:
00015     API function prototypes for the CAN FD SPI controller like the MCP2517FD.
00016  *******************************************************************************/
00017 
00018 //DOM-IGNORE-BEGIN
00019 /*******************************************************************************
00020 Copyright (c) 2016 Microchip Technology Inc. and its subsidiaries.
00021 You may use this software and any derivatives exclusively with Microchip products.
00022 
00023 THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
00024 NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
00025 INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
00026 AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP PRODUCTS,
00027 COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
00028 
00029 IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
00030 INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER
00031 RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED
00032 OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT ALLOWED BY LAW,
00033 MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE
00034 WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
00035 
00036 MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE TERMS.
00037  *******************************************************************************/
00038 //DOM-IGNORE-END
00039 
00040 #ifndef _DRV_CANFDSPI_API_H
00041 #define _DRV_CANFDSPI_API_H
00042 
00043 // *****************************************************************************
00044 // *****************************************************************************
00045 // Section: Included Files
00046 
00047 #include <stdint.h>
00048 #include <stdbool.h>
00049 #include <stddef.h>
00050 #include <stdlib.h>
00051 #include "drv_canfdspi_defines.h"
00052 
00053 // DOM-IGNORE-BEGIN
00054 #ifdef __cplusplus  // Provide C++ Compatibility
00055 extern "C" {
00056 #endif
00057 // DOM-IGNORE-END
00058     #define MAX_MSG_SIZE 76
00059     typedef uint8_t CANFDSPI_MODULE_ID;
00060 
00061 
00062 // *****************************************************************************
00063 // *****************************************************************************
00064 //! Reset DUT
00065 
00066     int8_t DRV_CANFDSPI_Reset(CANFDSPI_MODULE_ID index);
00067 
00068 
00069 // *****************************************************************************
00070 // *****************************************************************************
00071 // Section: SPI Access Functions
00072 
00073 // *****************************************************************************
00074 //! SPI Read Byte
00075 
00076     int8_t DRV_CANFDSPI_ReadByte(CANFDSPI_MODULE_ID index, uint16_t address,
00077                                  uint8_t *rxd);
00078 
00079 // *****************************************************************************
00080 //! SPI Write Byte
00081 
00082     int8_t DRV_CANFDSPI_WriteByte(CANFDSPI_MODULE_ID index, uint16_t address,
00083                                   uint8_t txd);
00084 
00085 // *****************************************************************************
00086 //! SPI Read Word
00087 
00088     int8_t DRV_CANFDSPI_ReadWord(CANFDSPI_MODULE_ID index, uint16_t address,
00089                                  uint32_t *rxd);
00090 
00091 // *****************************************************************************
00092 //! SPI Write Word
00093 
00094     int8_t DRV_CANFDSPI_WriteWord(CANFDSPI_MODULE_ID index, uint16_t address,
00095                                   uint32_t txd);
00096 
00097 /// *****************************************************************************
00098 //! SPI Read Word
00099 
00100     int8_t DRV_CANFDSPI_ReadHalfWord(CANFDSPI_MODULE_ID index, uint16_t address,
00101                                      uint16_t *rxd);
00102 
00103 // *****************************************************************************
00104 //! SPI Write Word
00105 
00106     int8_t DRV_CANFDSPI_WriteHalfWord(CANFDSPI_MODULE_ID index, uint16_t address,
00107                                       uint16_t txd);
00108 
00109 // *****************************************************************************
00110 //! SPI Read Byte Array
00111 
00112     int8_t DRV_CANFDSPI_ReadByteArray(CANFDSPI_MODULE_ID index, uint16_t address,
00113                                       uint8_t *rxd, uint16_t nBytes);
00114 
00115 // *****************************************************************************
00116 //! SPI Write Byte Array
00117 
00118     int8_t DRV_CANFDSPI_WriteByteArray(CANFDSPI_MODULE_ID index, uint16_t address,
00119                                        uint8_t *txd, uint16_t nBytes);
00120 
00121 // *****************************************************************************
00122 //! SPI SFR Write Byte Safe
00123     /*!
00124      * Writes Byte to SFR at address using SPI CRC. Byte gets only written if CRC matches.
00125      *
00126      * Remark: The function doesn't check if the address is an SFR address.
00127      */
00128 
00129     int8_t DRV_CANFDSPI_WriteByteSafe(CANFDSPI_MODULE_ID index, uint16_t address,
00130                                       uint8_t txd);
00131 
00132 // *****************************************************************************
00133 //! SPI RAM Write Word Safe
00134     /*!
00135      * Writes Word to RAM at address using SPI CRC. Word gets only written if CRC matches.
00136      *
00137      * Remark: The function doesn't check if the address is a RAM address.
00138      */
00139 
00140     int8_t DRV_CANFDSPI_WriteWordSafe(CANFDSPI_MODULE_ID index, uint16_t address,
00141                                       uint32_t txd);
00142 
00143 // *****************************************************************************
00144 //! SPI Read Byte Array with CRC
00145 
00146     int8_t DRV_CANFDSPI_ReadByteArrayWithCRC(CANFDSPI_MODULE_ID index, uint16_t address,
00147             uint8_t *rxd, uint16_t nBytes, bool fromRam, bool* crcIsCorrect);
00148 
00149 // *****************************************************************************
00150 //! SPI Write Byte Array with CRC
00151 
00152     int8_t DRV_CANFDSPI_WriteByteArrayWithCRC(CANFDSPI_MODULE_ID index, uint16_t address,
00153             uint8_t *txd, uint16_t nBytes, bool fromRam);
00154 
00155 // *****************************************************************************
00156 //! SPI Read Word Array
00157 
00158     int8_t DRV_CANFDSPI_ReadWordArray(CANFDSPI_MODULE_ID index, uint16_t address,
00159                                       uint32_t *rxd, uint16_t nWords);
00160 
00161 // *****************************************************************************
00162 //! SPI Write Word Array
00163 
00164     int8_t DRV_CANFDSPI_WriteWordArray(CANFDSPI_MODULE_ID index, uint16_t address,
00165                                        uint32_t *txd, uint16_t nWords);
00166 
00167 
00168 // *****************************************************************************
00169 // *****************************************************************************
00170 // Section: Configuration
00171 
00172 // *****************************************************************************
00173 //! CAN Control register configuration
00174 
00175     int8_t DRV_CANFDSPI_Configure(CANFDSPI_MODULE_ID index, CAN_CONFIG* config);
00176 
00177 // *****************************************************************************
00178 //! Reset Configure object to reset values
00179     int8_t DRV_CANFDSPI_ConfigureObjectReset(CAN_CONFIG* config);
00180 
00181 
00182 // *****************************************************************************
00183 // *****************************************************************************
00184 // Section: Operating mode
00185 
00186 // *****************************************************************************
00187 //! Select Operation Mode
00188 
00189     int8_t DRV_CANFDSPI_OperationModeSelect(CANFDSPI_MODULE_ID index,
00190                                             CAN_OPERATION_MODE opMode);
00191 
00192 // *****************************************************************************
00193 //! Get Operation Mode
00194 
00195     CAN_OPERATION_MODE DRV_CANFDSPI_OperationModeGet(CANFDSPI_MODULE_ID index);
00196 
00197 
00198 // *****************************************************************************
00199 // *****************************************************************************
00200 // Section: CAN Transmit
00201 
00202 // *****************************************************************************
00203 //! Configure Transmit FIFO
00204 
00205     int8_t DRV_CANFDSPI_TransmitChannelConfigure(CANFDSPI_MODULE_ID index,
00206             CAN_FIFO_CHANNEL channel, CAN_TX_FIFO_CONFIG* config);
00207 
00208 // *****************************************************************************
00209 //! Reset TransmitChannelConfigure object to reset values
00210 
00211     int8_t DRV_CANFDSPI_TransmitChannelConfigureObjectReset(CAN_TX_FIFO_CONFIG* config);
00212 
00213 // *****************************************************************************
00214 //! Configure Transmit Queue
00215 
00216     int8_t DRV_CANFDSPI_TransmitQueueConfigure(CANFDSPI_MODULE_ID index,
00217             CAN_TX_QUEUE_CONFIG* config);
00218 
00219 // *****************************************************************************
00220 //! Reset TransmitQueueConfigure object to reset values
00221 
00222     int8_t DRV_CANFDSPI_TransmitQueueConfigureObjectReset(CAN_TX_QUEUE_CONFIG* config);
00223 
00224 // *****************************************************************************
00225 //! TX Channel Load
00226     /*!
00227      * Loads data into Transmit channel
00228      * Requests transmission, if flush==true
00229      */
00230 
00231     int8_t DRV_CANFDSPI_TransmitChannelLoad(CANFDSPI_MODULE_ID index,
00232                                             CAN_FIFO_CHANNEL channel, CAN_TX_MSGOBJ* txObj,
00233                                             uint8_t *txd, uint32_t txdNumBytes, bool flush);
00234 
00235 // *****************************************************************************
00236 //! TX Channel Flush
00237     /*!
00238      * Set TXREG of one channel
00239      */
00240 
00241     int8_t DRV_CANFDSPI_TransmitChannelFlush(CANFDSPI_MODULE_ID index,
00242             CAN_FIFO_CHANNEL channel);
00243 
00244 // *****************************************************************************
00245 //! Transmit Channel Status Get
00246 
00247     int8_t DRV_CANFDSPI_TransmitChannelStatusGet(CANFDSPI_MODULE_ID index,
00248             CAN_FIFO_CHANNEL channel, CAN_TX_FIFO_STATUS* status);
00249 
00250 // *****************************************************************************
00251 //! Transmit FIFO Reset
00252 
00253     int8_t DRV_CANFDSPI_TransmitChannelReset(CANFDSPI_MODULE_ID index,
00254             CAN_FIFO_CHANNEL channel);
00255 
00256 // *****************************************************************************
00257 //! Transmit FIFO Update
00258     /*!
00259      * Sets UINC of the transmit channel. Keeps TXREQ unchanged.
00260      */
00261 
00262     int8_t DRV_CANFDSPI_TransmitChannelUpdate(CANFDSPI_MODULE_ID index,
00263             CAN_FIFO_CHANNEL channel, bool flush);
00264 
00265 // *****************************************************************************
00266 //! Request transmissions using TXREQ register
00267 
00268     int8_t DRV_CANFDSPI_TransmitRequestSet(CANFDSPI_MODULE_ID index,
00269                                            CAN_TXREQ_CHANNEL txreq);
00270 
00271 // *****************************************************************************
00272 //! Get TXREQ register
00273 
00274     int8_t DRV_CANFDSPI_TransmitRequestGet(CANFDSPI_MODULE_ID index,
00275                                            uint32_t* txreq);
00276 
00277 // *****************************************************************************
00278 //! Abort transmission of single FIFO
00279 
00280     int8_t DRV_CANFDSPI_TransmitChannelAbort(CANFDSPI_MODULE_ID index,
00281             CAN_FIFO_CHANNEL channel);
00282 
00283 // *****************************************************************************
00284 //! Abort All transmissions
00285 
00286     int8_t DRV_CANFDSPI_TransmitAbortAll(CANFDSPI_MODULE_ID index);
00287 
00288 // *****************************************************************************
00289 //! Set Transmit Bandwidth Sharing Delay
00290     int8_t DRV_CANFDSPI_TransmitBandWidthSharingSet(CANFDSPI_MODULE_ID index,
00291             CAN_TX_BANDWITH_SHARING txbws);
00292 
00293 
00294 // *****************************************************************************
00295 // *****************************************************************************
00296 // Section: CAN Receive
00297 
00298 // *****************************************************************************
00299 //! Filter Object Configuration
00300     /*!
00301      * Configures ID of filter object
00302      */
00303 
00304     int8_t DRV_CANFDSPI_FilterObjectConfigure(CANFDSPI_MODULE_ID index,
00305             CAN_FILTER filter, CAN_FILTEROBJ_ID* id);
00306 
00307 // *****************************************************************************
00308 //! Filter Mask Configuration
00309     /*!
00310      * Configures Mask of filter object
00311      */
00312 
00313     int8_t DRV_CANFDSPI_FilterMaskConfigure(CANFDSPI_MODULE_ID index,
00314                                             CAN_FILTER filter, CAN_MASKOBJ_ID* mask);
00315 
00316 // *****************************************************************************
00317 //! Link Filter to FIFO
00318     /*!
00319      * Initializes the Pointer from Filter to FIFO
00320      * Enables or disables the Filter
00321      */
00322 
00323     int8_t DRV_CANFDSPI_FilterToFifoLink(CANFDSPI_MODULE_ID index,
00324                                          CAN_FILTER filter, CAN_FIFO_CHANNEL channel, bool enable);
00325 
00326 // *****************************************************************************
00327 //! Filter Enable
00328 
00329     int8_t DRV_CANFDSPI_FilterEnable(CANFDSPI_MODULE_ID index, CAN_FILTER filter);
00330 
00331 // *****************************************************************************
00332 //! Filter Disable
00333 
00334     int8_t DRV_CANFDSPI_FilterDisable(CANFDSPI_MODULE_ID index, CAN_FILTER filter);
00335 
00336 // *****************************************************************************
00337 //! Set Device Net Filter Count
00338     int8_t DRV_CANFDSPI_DeviceNetFilterCountSet(CANFDSPI_MODULE_ID index,
00339             CAN_DNET_FILTER_SIZE dnfc);
00340 
00341 // *****************************************************************************
00342 //! Configure Receive FIFO
00343 
00344     int8_t DRV_CANFDSPI_ReceiveChannelConfigure(CANFDSPI_MODULE_ID index,
00345             CAN_FIFO_CHANNEL channel, CAN_RX_FIFO_CONFIG* config);
00346 
00347 // *****************************************************************************
00348 //! Reset ReceiveChannelConfigure object to reset value
00349 
00350     int8_t DRV_CANFDSPI_ReceiveChannelConfigureObjectReset(CAN_RX_FIFO_CONFIG* config);
00351 
00352 // *****************************************************************************
00353 //! Receive Channel Status Get
00354 
00355     int8_t DRV_CANFDSPI_ReceiveChannelStatusGet(CANFDSPI_MODULE_ID index,
00356             CAN_FIFO_CHANNEL channel, CAN_RX_FIFO_STATUS* status);
00357 
00358 // *****************************************************************************
00359 //! Get Received Message
00360     /*!
00361      * Reads Received message from channel
00362      */
00363 
00364     int8_t DRV_CANFDSPI_ReceiveMessageGet(CANFDSPI_MODULE_ID index,
00365                                           CAN_FIFO_CHANNEL channel, CAN_RX_MSGOBJ* rxObj,
00366                                           uint8_t *rxd, uint8_t nBytes);
00367 
00368 // *****************************************************************************
00369 //! Receive FIFO Reset
00370 
00371     int8_t DRV_CANFDSPI_ReceiveChannelReset(CANFDSPI_MODULE_ID index,
00372                                             CAN_FIFO_CHANNEL channel);
00373 
00374 // *****************************************************************************
00375 //! Receive FIFO Update
00376     /*!
00377      * Sets UINC of the receive channel.
00378      */
00379 
00380     int8_t DRV_CANFDSPI_ReceiveChannelUpdate(CANFDSPI_MODULE_ID index,
00381             CAN_FIFO_CHANNEL channel);
00382 
00383 
00384 // *****************************************************************************
00385 // *****************************************************************************
00386 // Section: Transmit Event FIFO
00387 
00388 // *****************************************************************************
00389 //! Transmit Event FIFO Status Get
00390 
00391     int8_t DRV_CANFDSPI_TefStatusGet(CANFDSPI_MODULE_ID index,
00392                                      CAN_TEF_FIFO_STATUS* status);
00393 
00394 // *****************************************************************************
00395 //! Get Transmit Event FIFO Message
00396     /*!
00397      * Reads Transmit Event FIFO message
00398      */
00399 
00400     int8_t DRV_CANFDSPI_TefMessageGet(CANFDSPI_MODULE_ID index,
00401                                       CAN_TEF_MSGOBJ* tefObj);
00402 
00403 // *****************************************************************************
00404 //! Transmit Event FIFO Reset
00405 
00406     int8_t DRV_CANFDSPI_TefReset(CANFDSPI_MODULE_ID index);
00407 
00408 // *****************************************************************************
00409 //! Transmit Event FIFO Update
00410     /*!
00411      * Sets UINC of the TEF.
00412      */
00413 
00414     int8_t DRV_CANFDSPI_TefUpdate(CANFDSPI_MODULE_ID index);
00415 
00416 // *****************************************************************************
00417 //! Configure Transmit Event FIFO
00418 
00419     int8_t DRV_CANFDSPI_TefConfigure(CANFDSPI_MODULE_ID index, CAN_TEF_CONFIG* config);
00420 
00421 // *****************************************************************************
00422 //! Reset TefConfigure object to reset value
00423 
00424     int8_t DRV_CANFDSPI_TefConfigureObjectReset(CAN_TEF_CONFIG* config);
00425 
00426 
00427 // *****************************************************************************
00428 // *****************************************************************************
00429 // Section: Module Events
00430 
00431 // *****************************************************************************
00432 //! Module Event Get
00433     /*!
00434      * Reads interrupt Flags
00435      */
00436 
00437     int8_t DRV_CANFDSPI_ModuleEventGet(CANFDSPI_MODULE_ID index,
00438                                        CAN_MODULE_EVENT* flags);
00439 
00440 // *****************************************************************************
00441 //! Module Event Enable
00442     /*!
00443      * Enables interrupts
00444      */
00445 
00446     int8_t DRV_CANFDSPI_ModuleEventEnable(CANFDSPI_MODULE_ID index,
00447                                           int flags);
00448 
00449 // *****************************************************************************
00450 //! Module Event Disable
00451     /*!
00452      * Disables interrupts
00453      */
00454 
00455     int8_t DRV_CANFDSPI_ModuleEventDisable(CANFDSPI_MODULE_ID index,
00456                                            CAN_MODULE_EVENT flags);
00457 
00458 // *****************************************************************************
00459 //! Module Event Clear
00460     /*!
00461      * Clears interrupt Flags
00462      */
00463 
00464     int8_t DRV_CANFDSPI_ModuleEventClear(CANFDSPI_MODULE_ID index,
00465                                          CAN_MODULE_EVENT flags);
00466 
00467 // *****************************************************************************
00468 //! Get RX Code
00469 
00470     int8_t DRV_CANFDSPI_ModuleEventRxCodeGet(CANFDSPI_MODULE_ID index,
00471             CAN_RXCODE* rxCode);
00472 
00473 // *****************************************************************************
00474 //! Get TX Code
00475 
00476     int8_t DRV_CANFDSPI_ModuleEventTxCodeGet(CANFDSPI_MODULE_ID index,
00477             CAN_TXCODE* txCode);
00478 
00479 // *****************************************************************************
00480 //! Get Filter Hit
00481 
00482     int8_t DRV_CANFDSPI_ModuleEventFilterHitGet(CANFDSPI_MODULE_ID index,
00483             CAN_FILTER* filterHit);
00484 
00485 // *****************************************************************************
00486 //! Get ICODE
00487 
00488     int8_t DRV_CANFDSPI_ModuleEventIcodeGet(CANFDSPI_MODULE_ID index,
00489                                             CAN_ICODE* icode);
00490 
00491 // *****************************************************************************
00492 // *****************************************************************************
00493 // Section: Transmit FIFO Events
00494 
00495 // *****************************************************************************
00496 //! Transmit FIFO Event Get
00497     /*!
00498      * Reads Transmit FIFO interrupt Flags
00499      */
00500 
00501     int8_t DRV_CANFDSPI_TransmitChannelEventGet(CANFDSPI_MODULE_ID index,
00502             CAN_FIFO_CHANNEL channel, CAN_TX_FIFO_EVENT* flags);
00503 
00504 // *****************************************************************************
00505 //! Get pending interrupts of all transmit FIFOs
00506 
00507     int8_t DRV_CANFDSPI_TransmitEventGet(CANFDSPI_MODULE_ID index, uint32_t* txif);
00508 
00509 // *****************************************************************************
00510 //! Get pending TXATIF of all transmit FIFOs
00511 
00512     int8_t DRV_CANFDSPI_TransmitEventAttemptGet(CANFDSPI_MODULE_ID index,
00513             uint32_t* txatif);
00514 
00515 // *****************************************************************************
00516 //! Transmit FIFO Index Get
00517     /*!
00518      * Reads Transmit FIFO Index
00519      */
00520 
00521     int8_t DRV_CANFDSPI_TransmitChannelIndexGet(CANFDSPI_MODULE_ID index,
00522             CAN_FIFO_CHANNEL channel, uint8_t* idx);
00523 
00524 // *****************************************************************************
00525 //! Transmit FIFO Event Enable
00526     /*!
00527      * Enables Transmit FIFO interrupts
00528      */
00529 
00530     int8_t DRV_CANFDSPI_TransmitChannelEventEnable(CANFDSPI_MODULE_ID index,
00531             CAN_FIFO_CHANNEL channel, CAN_TX_FIFO_EVENT flags);
00532 
00533 // *****************************************************************************
00534 //! Transmit FIFO Event Disable
00535     /*!
00536      * Disables Transmit FIFO interrupts
00537      */
00538 
00539     int8_t DRV_CANFDSPI_TransmitChannelEventDisable(CANFDSPI_MODULE_ID index,
00540             CAN_FIFO_CHANNEL channel, CAN_TX_FIFO_EVENT flags);
00541 
00542 // *****************************************************************************
00543 //! Transmit FIFO Event Clear
00544     /*!
00545      * Clears Transmit FIFO Attempts Exhausted interrupt Flag
00546      */
00547 
00548     int8_t DRV_CANFDSPI_TransmitChannelEventAttemptClear(CANFDSPI_MODULE_ID index,
00549             CAN_FIFO_CHANNEL channel);
00550 
00551 
00552 // *****************************************************************************
00553 // *****************************************************************************
00554 // Section: Receive FIFO Events
00555 
00556 // *****************************************************************************
00557 //! Receive FIFO Event Get
00558     /*!
00559      * Reads Receive FIFO interrupt Flags
00560      */
00561 
00562     int8_t DRV_CANFDSPI_ReceiveChannelEventGet(CANFDSPI_MODULE_ID index,
00563             CAN_FIFO_CHANNEL channel, CAN_RX_FIFO_EVENT* flags);
00564 
00565 // *****************************************************************************
00566 //! Get pending interrupts of all receive FIFOs
00567 
00568     int8_t DRV_CANFDSPI_ReceiveEventGet(CANFDSPI_MODULE_ID index, uint32_t* rxif);
00569 
00570 // *****************************************************************************
00571 //!Get pending RXOVIF of all receive FIFOs
00572 
00573     int8_t DRV_CANFDSPI_ReceiveEventOverflowGet(CANFDSPI_MODULE_ID index, uint32_t* rxovif);
00574 
00575 // *****************************************************************************
00576 //! Receive FIFO Index Get
00577     /*!
00578      * Reads Receive FIFO Index
00579      */
00580 
00581     int8_t DRV_CANFDSPI_ReceiveChannelIndexGet(CANFDSPI_MODULE_ID index,
00582             CAN_FIFO_CHANNEL channel, uint8_t* idx);
00583 
00584 // *****************************************************************************
00585 //! Receive FIFO Event Enable
00586     /*!
00587      * Enables Receive FIFO interrupts
00588      */
00589 
00590     int8_t DRV_CANFDSPI_ReceiveChannelEventEnable(CANFDSPI_MODULE_ID index,
00591             CAN_FIFO_CHANNEL channel, CAN_RX_FIFO_EVENT flags);
00592 
00593 // *****************************************************************************
00594 //! Receive FIFO Event Disable
00595     /*!
00596      * Disables Receive FIFO interrupts
00597      */
00598 
00599     int8_t DRV_CANFDSPI_ReceiveChannelEventDisable(CANFDSPI_MODULE_ID index,
00600             CAN_FIFO_CHANNEL channel, CAN_RX_FIFO_EVENT flags);
00601 
00602 // *****************************************************************************
00603 //! Receive FIFO Event Clear
00604     /*!
00605      * Clears Receive FIFO Overflow interrupt Flag
00606      */
00607 
00608     int8_t DRV_CANFDSPI_ReceiveChannelEventOverflowClear(CANFDSPI_MODULE_ID index,
00609             CAN_FIFO_CHANNEL channel);
00610 
00611 
00612 // *****************************************************************************
00613 // *****************************************************************************
00614 // Section: Transmit Event FIFO Events
00615 
00616 // *****************************************************************************
00617 //! Transmit Event FIFO Event Get
00618     /*!
00619      * Reads Transmit Event FIFO interrupt Flags
00620      */
00621 
00622     int8_t DRV_CANFDSPI_TefEventGet(CANFDSPI_MODULE_ID index,
00623                                     CAN_TEF_FIFO_EVENT* flags);
00624 
00625 // *****************************************************************************
00626 //! Transmit Event FIFO Event Enable
00627     /*!
00628      * Enables Transmit Event FIFO interrupts
00629      */
00630 
00631     int8_t DRV_CANFDSPI_TefEventEnable(CANFDSPI_MODULE_ID index,
00632                                        CAN_TEF_FIFO_EVENT flags);
00633 
00634 // *****************************************************************************
00635 //! Transmit Event FIFO Event Disable
00636     /*!
00637      * Disables Transmit Event FIFO interrupts
00638      */
00639 
00640     int8_t DRV_CANFDSPI_TefEventDisable(CANFDSPI_MODULE_ID index,
00641                                         CAN_TEF_FIFO_EVENT flags);
00642 
00643 // *****************************************************************************
00644 //! Transmit Event FIFO Event Clear
00645     /*!
00646      * Clears Transmit Event FIFO Overflow interrupt Flag
00647      */
00648 
00649     int8_t DRV_CANFDSPI_TefEventOverflowClear(CANFDSPI_MODULE_ID index);
00650 
00651 
00652 // *****************************************************************************
00653 // *****************************************************************************
00654 // Section: Error Handling
00655 
00656 // *****************************************************************************
00657 //! Transmit Error Count Get
00658 
00659     int8_t DRV_CANFDSPI_ErrorCountTransmitGet(CANFDSPI_MODULE_ID index,
00660             uint8_t* tec);
00661 
00662 // *****************************************************************************
00663 //! Receive Error Count Get
00664 
00665     int8_t DRV_CANFDSPI_ErrorCountReceiveGet(CANFDSPI_MODULE_ID index,
00666             uint8_t* rec);
00667 
00668 // *****************************************************************************
00669 //! Error State Get
00670 
00671     int8_t DRV_CANFDSPI_ErrorStateGet(CANFDSPI_MODULE_ID index,
00672                                       CAN_ERROR_STATE* flags);
00673 
00674 // *****************************************************************************
00675 //! Error Counts and Error State Get
00676     /*!
00677      * Returns content of complete CiTREC
00678      */
00679 
00680     int8_t DRV_CANFDSPI_ErrorCountStateGet(CANFDSPI_MODULE_ID index,
00681                                            uint8_t* tec, uint8_t* rec, CAN_ERROR_STATE* flags);
00682 
00683 // *****************************************************************************
00684 //! Get Bus Diagnostic Registers: all data at once, since we want to keep them in synch
00685 
00686     int8_t DRV_CANFDSPI_BusDiagnosticsGet(CANFDSPI_MODULE_ID index,
00687                                           CAN_BUS_DIAGNOSTIC* bd);
00688 
00689 // *****************************************************************************
00690 //! Clear Bus Diagnostic Registers
00691 
00692     int8_t DRV_CANFDSPI_BusDiagnosticsClear(CANFDSPI_MODULE_ID index);
00693 
00694 
00695 // *****************************************************************************
00696 // *****************************************************************************
00697 // Section: ECC
00698 
00699 // *****************************************************************************
00700 //! Enable ECC
00701 
00702     int8_t DRV_CANFDSPI_EccEnable(CANFDSPI_MODULE_ID index);
00703 
00704 // *****************************************************************************
00705 //! Disable ECC
00706 
00707     int8_t DRV_CANFDSPI_EccDisable(CANFDSPI_MODULE_ID index);
00708 
00709 // *****************************************************************************
00710 //! ECC Event Get
00711 
00712     int8_t DRV_CANFDSPI_EccEventGet(CANFDSPI_MODULE_ID index,
00713                                     CAN_ECC_EVENT* flags);
00714 
00715 // *****************************************************************************
00716 //! Set ECC Parity
00717 
00718     int8_t DRV_CANFDSPI_EccParitySet(CANFDSPI_MODULE_ID index,
00719                                      uint8_t parity);
00720 
00721 // *****************************************************************************
00722 //! Get ECC Parity
00723 
00724     int8_t DRV_CANFDSPI_EccParityGet(CANFDSPI_MODULE_ID index,
00725                                      uint8_t* parity);
00726 
00727 // *****************************************************************************
00728 //! Get ECC Error Address
00729 
00730     int8_t DRV_CANFDSPI_EccErrorAddressGet(CANFDSPI_MODULE_ID index,
00731                                            uint16_t* a);
00732 
00733 // *****************************************************************************
00734 //! ECC Event Enable
00735 
00736     int8_t DRV_CANFDSPI_EccEventEnable(CANFDSPI_MODULE_ID index,
00737                                        CAN_ECC_EVENT flags);
00738 
00739 // *****************************************************************************
00740 //! ECC Event Disable
00741 
00742     int8_t DRV_CANFDSPI_EccEventDisable(CANFDSPI_MODULE_ID index,
00743                                         CAN_ECC_EVENT flags);
00744 
00745 // *****************************************************************************
00746 //! ECC Event Clear
00747 
00748     int8_t DRV_CANFDSPI_EccEventClear(CANFDSPI_MODULE_ID index,
00749                                       CAN_ECC_EVENT flags);
00750 
00751 // *****************************************************************************
00752 //! Initialize RAM
00753 
00754     int8_t DRV_CANFDSPI_RamInit(CANFDSPI_MODULE_ID index, uint8_t d);
00755 
00756 
00757 // *****************************************************************************
00758 // *****************************************************************************
00759 // Section: CRC
00760 
00761 // *****************************************************************************
00762 //! CRC Event Enable
00763 
00764     int8_t DRV_CANFDSPI_CrcEventEnable(CANFDSPI_MODULE_ID index,
00765                                        CAN_CRC_EVENT flags);
00766 
00767 // *****************************************************************************
00768 //! CRC Event Disable
00769 
00770     int8_t DRV_CANFDSPI_CrcEventDisable(CANFDSPI_MODULE_ID index,
00771                                         CAN_CRC_EVENT flags);
00772 
00773 // *****************************************************************************
00774 //! CRC Event Clear
00775 
00776     int8_t DRV_CANFDSPI_CrcEventClear(CANFDSPI_MODULE_ID index,
00777                                       CAN_CRC_EVENT flags);
00778 
00779 // *****************************************************************************
00780 //! CRC Event Get
00781 
00782     int8_t DRV_CANFDSPI_CrcEventGet(CANFDSPI_MODULE_ID index, CAN_CRC_EVENT* flags);
00783 
00784 // *****************************************************************************
00785 //! Get CRC Value from device
00786 
00787     int8_t DRV_CANFDSPI_CrcValueGet(CANFDSPI_MODULE_ID index, uint16_t* crc);
00788 
00789 
00790 // *****************************************************************************
00791 // *****************************************************************************
00792 // Section: Time Stamp
00793 
00794 // *****************************************************************************
00795 //! Time Stamp Enable
00796 
00797     int8_t DRV_CANFDSPI_TimeStampEnable(CANFDSPI_MODULE_ID index);
00798 
00799 // *****************************************************************************
00800 //! Time Stamp Disable
00801 
00802     int8_t DRV_CANFDSPI_TimeStampDisable(CANFDSPI_MODULE_ID index);
00803 
00804 // *****************************************************************************
00805 //! Time Stamp Get
00806 
00807     int8_t DRV_CANFDSPI_TimeStampGet(CANFDSPI_MODULE_ID index, uint32_t* ts);
00808 
00809 // *****************************************************************************
00810 //! Time Stamp Set
00811 
00812     int8_t DRV_CANFDSPI_TimeStampSet(CANFDSPI_MODULE_ID index, uint32_t ts);
00813 
00814 // *****************************************************************************
00815 //! Time Stamp Mode Configure
00816 
00817     int8_t DRV_CANFDSPI_TimeStampModeConfigure(CANFDSPI_MODULE_ID index,
00818             CAN_TS_MODE mode);
00819 
00820 // *****************************************************************************
00821 //! Time Stamp Prescaler Set
00822 
00823     int8_t DRV_CANFDSPI_TimeStampPrescalerSet(CANFDSPI_MODULE_ID index,
00824             uint16_t ps);
00825 
00826 
00827 // *****************************************************************************
00828 // *****************************************************************************
00829 // Section: Oscillator and Bit Time
00830 
00831 // *****************************************************************************
00832 //! Enable oscillator to wake-up from sleep
00833 
00834     int8_t DRV_CANFDSPI_OscillatorEnable(CANFDSPI_MODULE_ID index);
00835 
00836 // *****************************************************************************
00837 //! Set Oscillator Control
00838 
00839     int8_t DRV_CANFDSPI_OscillatorControlSet(CANFDSPI_MODULE_ID index,
00840             CAN_OSC_CTRL ctrl);
00841 
00842     int8_t DRV_CANFDSPI_OscillatorControlObjectReset(CAN_OSC_CTRL* ctrl);
00843 
00844 
00845 // *****************************************************************************
00846 //! Get Oscillator Status
00847 
00848     int8_t DRV_CANFDSPI_OscillatorStatusGet(CANFDSPI_MODULE_ID index,
00849                                             CAN_OSC_STATUS* status);
00850 
00851 // *****************************************************************************
00852 //! Configure Bit Time registers (based on CAN clock speed)
00853 
00854     int8_t DRV_CANFDSPI_BitTimeConfigure(CANFDSPI_MODULE_ID index,
00855                                          CAN_BITTIME_SETUP bitTime, CAN_SSP_MODE sspMode,
00856                                          CAN_SYSCLK_SPEED clk);
00857 
00858 // *****************************************************************************
00859 //! Configure Nominal bit time for 40MHz system clock
00860 
00861     int8_t DRV_CANFDSPI_BitTimeConfigureNominal40MHz(CANFDSPI_MODULE_ID index,
00862             CAN_BITTIME_SETUP bitTime);
00863 
00864 // *****************************************************************************
00865 //! Configure Data bit time for 40MHz system clock
00866 
00867     int8_t DRV_CANFDSPI_BitTimeConfigureData40MHz(CANFDSPI_MODULE_ID index,
00868             CAN_BITTIME_SETUP bitTime, CAN_SSP_MODE sspMode);
00869 
00870 // *****************************************************************************
00871 //! Configure Nominal bit time for 20MHz system clock
00872 
00873     int8_t DRV_CANFDSPI_BitTimeConfigureNominal20MHz(CANFDSPI_MODULE_ID index,
00874             CAN_BITTIME_SETUP bitTime);
00875 
00876 // *****************************************************************************
00877 //! Configure Data bit time for 20MHz system clock
00878 
00879     int8_t DRV_CANFDSPI_BitTimeConfigureData20MHz(CANFDSPI_MODULE_ID index,
00880             CAN_BITTIME_SETUP bitTime, CAN_SSP_MODE sspMode);
00881 
00882 // *****************************************************************************
00883 //! Configure Nominal bit time for 10MHz system clock
00884 
00885     int8_t DRV_CANFDSPI_BitTimeConfigureNominal10MHz(CANFDSPI_MODULE_ID index,
00886             CAN_BITTIME_SETUP bitTime);
00887 
00888 // *****************************************************************************
00889 //! Configure Data bit time for 10MHz system clock
00890 
00891     int8_t DRV_CANFDSPI_BitTimeConfigureData10MHz(CANFDSPI_MODULE_ID index,
00892             CAN_BITTIME_SETUP bitTime, CAN_SSP_MODE sspMode);
00893 
00894 
00895 // *****************************************************************************
00896 // *****************************************************************************
00897 // Section: GPIO
00898 
00899 // *****************************************************************************
00900 //! Initialize GPIO Mode
00901 
00902     int8_t DRV_CANFDSPI_GpioModeConfigure(CANFDSPI_MODULE_ID index,
00903                                           GPIO_PIN_MODE gpio0, GPIO_PIN_MODE gpio1);
00904 
00905 // *****************************************************************************
00906 //! Initialize GPIO Direction
00907 
00908     int8_t DRV_CANFDSPI_GpioDirectionConfigure(CANFDSPI_MODULE_ID index,
00909             GPIO_PIN_DIRECTION gpio0, GPIO_PIN_DIRECTION gpio1);
00910 
00911 // *****************************************************************************
00912 //! Enable Transceiver Standby Control
00913 
00914     int8_t DRV_CANFDSPI_GpioStandbyControlEnable(CANFDSPI_MODULE_ID index);
00915 
00916 // *****************************************************************************
00917 //! Disable Transceiver Standby Control
00918 
00919     int8_t DRV_CANFDSPI_GpioStandbyControlDisable(CANFDSPI_MODULE_ID index);
00920 
00921 // *****************************************************************************
00922 //! Configure Open Drain Interrupts
00923 
00924     int8_t DRV_CANFDSPI_GpioInterruptPinsOpenDrainConfigure(CANFDSPI_MODULE_ID index,
00925             GPIO_OPEN_DRAIN_MODE mode);
00926 
00927 // *****************************************************************************
00928 //! Configure Open Drain TXCAN
00929 
00930     int8_t DRV_CANFDSPI_GpioTransmitPinOpenDrainConfigure(CANFDSPI_MODULE_ID index,
00931             GPIO_OPEN_DRAIN_MODE mode);
00932 
00933 // *****************************************************************************
00934 //! GPIO Output Pin Set
00935 
00936     int8_t DRV_CANFDSPI_GpioPinSet(CANFDSPI_MODULE_ID index,
00937                                    GPIO_PIN_POS pos, GPIO_PIN_STATE latch);
00938 
00939 // *****************************************************************************
00940 //! GPIO Input Pin Read
00941 
00942     int8_t DRV_CANFDSPI_GpioPinRead(CANFDSPI_MODULE_ID index,
00943                                     GPIO_PIN_POS pos, GPIO_PIN_STATE* state);
00944 
00945 // *****************************************************************************
00946 //! Configure CLKO Pin
00947 
00948     int8_t DRV_CANFDSPI_GpioClockOutputConfigure(CANFDSPI_MODULE_ID index,
00949             GPIO_CLKO_MODE mode);
00950 
00951 
00952 // *****************************************************************************
00953 // *****************************************************************************
00954 // Section: Miscellaneous
00955 
00956 // *****************************************************************************
00957 //! DLC to number of actual data bytes conversion
00958 
00959     uint32_t DRV_CANFDSPI_DlcToDataBytes(/*CAN_DLC*/ uint8_t dlc);
00960 
00961 // *****************************************************************************
00962 //! FIFO Index Get
00963 
00964     int8_t DRV_CANFDSPI_FifoIndexGet(CANFDSPI_MODULE_ID index,
00965                                      CAN_FIFO_CHANNEL channel, uint8_t* mi);
00966 
00967 // *****************************************************************************
00968 //! Calculate CRC16
00969 
00970     uint16_t DRV_CANFDSPI_CalculateCRC16(uint8_t* data, uint16_t size);
00971 
00972 // *****************************************************************************
00973 //! Data bytes to DLC conversion
00974 
00975     CAN_DLC DRV_CANFDSPI_DataBytesToDlc(uint8_t n);
00976 
00977 #ifdef __cplusplus  // Provide C++ Compatibility
00978 }
00979 #endif
00980 
00981 #endif // _DRV_CANFDSPI_API_H
00982