drv_canfdspi_api.h

00001 /*******************************************************************************
00002   CAN FD SPI Driver: API Functions Header File
00003 
00004   Company:
00005     Microchip Technology Inc.
00006 
00007   File Name:
00008     drv_canfdspi_api.h
00009 
00010   Summary:
00011     This header file provides the API function prototypes for the CAN FD SPI
00012     controller.
00013 
00014   Description:
00015     API function prototypes for the CAN FD SPI controller like the MCP2517FD.
00016  *******************************************************************************/
00017 
00018 //DOM-IGNORE-BEGIN
00019 /*******************************************************************************
00020 Copyright (c) 2016 Microchip Technology Inc. and its subsidiaries.
00021 You may use this software and any derivatives exclusively with Microchip products.
00022 
00023 THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
00024 NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
00025 INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
00026 AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP PRODUCTS,
00027 COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
00028 
00029 IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
00030 INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER
00031 RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED
00032 OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT ALLOWED BY LAW,
00033 MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE
00034 WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
00035 
00036 MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE TERMS.
00037  *******************************************************************************/
00038 //DOM-IGNORE-END
00039 
00040 #ifndef _DRV_CANFDSPI_API_H
00041 #define _DRV_CANFDSPI_API_H
00042 
00043 // *****************************************************************************
00044 // *****************************************************************************
00045 // Section: Included Files
00046 
00047 #include <stdint.h>
00048 #include <stdbool.h>
00049 #include <stddef.h>
00050 #include <stdlib.h>
00051 #include "drv_canfdspi_defines.h"
00052 
00053 // DOM-IGNORE-BEGIN
00054 #ifdef __cplusplus  // Provide C++ Compatibility
00055 extern "C" {
00056 #endif
00057 // DOM-IGNORE-END
00058 
00059     typedef uint8_t CANFDSPI_MODULE_ID;
00060 
00061 // *****************************************************************************
00062 // *****************************************************************************
00063 //! Reset DUT
00064 
00065     int8_t DRV_CANFDSPI_Reset(CANFDSPI_MODULE_ID index);
00066 
00067 
00068 // *****************************************************************************
00069 // *****************************************************************************
00070 // Section: SPI Access Functions
00071 
00072 // *****************************************************************************
00073 //! SPI Read Byte
00074 
00075     int8_t DRV_CANFDSPI_ReadByte(CANFDSPI_MODULE_ID index, uint16_t address,
00076                                  uint8_t *rxd);
00077 
00078 // *****************************************************************************
00079 //! SPI Write Byte
00080 
00081     int8_t DRV_CANFDSPI_WriteByte(CANFDSPI_MODULE_ID index, uint16_t address,
00082                                   uint8_t txd);
00083 
00084 // *****************************************************************************
00085 //! SPI Read Word
00086 
00087     int8_t DRV_CANFDSPI_ReadWord(CANFDSPI_MODULE_ID index, uint16_t address,
00088                                  uint32_t *rxd);
00089 
00090 // *****************************************************************************
00091 //! SPI Write Word
00092 
00093     int8_t DRV_CANFDSPI_WriteWord(CANFDSPI_MODULE_ID index, uint16_t address,
00094                                   uint32_t txd);
00095 
00096 /// *****************************************************************************
00097 //! SPI Read Word
00098 
00099     int8_t DRV_CANFDSPI_ReadHalfWord(CANFDSPI_MODULE_ID index, uint16_t address,
00100                                      uint16_t *rxd);
00101 
00102 // *****************************************************************************
00103 //! SPI Write Word
00104 
00105     int8_t DRV_CANFDSPI_WriteHalfWord(CANFDSPI_MODULE_ID index, uint16_t address,
00106                                       uint16_t txd);
00107 
00108 // *****************************************************************************
00109 //! SPI Read Byte Array
00110 
00111     int8_t DRV_CANFDSPI_ReadByteArray(CANFDSPI_MODULE_ID index, uint16_t address,
00112                                       uint8_t *rxd, uint16_t nBytes);
00113 
00114 // *****************************************************************************
00115 //! SPI Write Byte Array
00116 
00117     int8_t DRV_CANFDSPI_WriteByteArray(CANFDSPI_MODULE_ID index, uint16_t address,
00118                                        uint8_t *txd, uint16_t nBytes);
00119 
00120 // *****************************************************************************
00121 //! SPI SFR Write Byte Safe
00122     /*!
00123      * Writes Byte to SFR at address using SPI CRC. Byte gets only written if CRC matches.
00124      *
00125      * Remark: The function doesn't check if the address is an SFR address.
00126      */
00127 
00128     int8_t DRV_CANFDSPI_WriteByteSafe(CANFDSPI_MODULE_ID index, uint16_t address,
00129                                       uint8_t txd);
00130 
00131 // *****************************************************************************
00132 //! SPI RAM Write Word Safe
00133     /*!
00134      * Writes Word to RAM at address using SPI CRC. Word gets only written if CRC matches.
00135      *
00136      * Remark: The function doesn't check if the address is a RAM address.
00137      */
00138 
00139     int8_t DRV_CANFDSPI_WriteWordSafe(CANFDSPI_MODULE_ID index, uint16_t address,
00140                                       uint32_t txd);
00141 
00142 // *****************************************************************************
00143 //! SPI Read Byte Array with CRC
00144 
00145     int8_t DRV_CANFDSPI_ReadByteArrayWithCRC(CANFDSPI_MODULE_ID index, uint16_t address,
00146             uint8_t *rxd, uint16_t nBytes, bool fromRam, bool* crcIsCorrect);
00147 
00148 // *****************************************************************************
00149 //! SPI Write Byte Array with CRC
00150 
00151     int8_t DRV_CANFDSPI_WriteByteArrayWithCRC(CANFDSPI_MODULE_ID index, uint16_t address,
00152             uint8_t *txd, uint16_t nBytes, bool fromRam);
00153 
00154 // *****************************************************************************
00155 //! SPI Read Word Array
00156 
00157     int8_t DRV_CANFDSPI_ReadWordArray(CANFDSPI_MODULE_ID index, uint16_t address,
00158                                       uint32_t *rxd, uint16_t nWords);
00159 
00160 // *****************************************************************************
00161 //! SPI Write Word Array
00162 
00163     int8_t DRV_CANFDSPI_WriteWordArray(CANFDSPI_MODULE_ID index, uint16_t address,
00164                                        uint32_t *txd, uint16_t nWords);
00165 
00166 
00167 // *****************************************************************************
00168 // *****************************************************************************
00169 // Section: Configuration
00170 
00171 // *****************************************************************************
00172 //! CAN Control register configuration
00173 
00174     int8_t DRV_CANFDSPI_Configure(CANFDSPI_MODULE_ID index, CAN_CONFIG* config);
00175 
00176 // *****************************************************************************
00177 //! Reset Configure object to reset values
00178     int8_t DRV_CANFDSPI_ConfigureObjectReset(CAN_CONFIG* config);
00179 
00180 
00181 // *****************************************************************************
00182 // *****************************************************************************
00183 // Section: Operating mode
00184 
00185 // *****************************************************************************
00186 //! Select Operation Mode
00187 
00188     int8_t DRV_CANFDSPI_OperationModeSelect(CANFDSPI_MODULE_ID index,
00189                                             CAN_OPERATION_MODE opMode);
00190 
00191 // *****************************************************************************
00192 //! Get Operation Mode
00193 
00194     CAN_OPERATION_MODE DRV_CANFDSPI_OperationModeGet(CANFDSPI_MODULE_ID index);
00195 
00196 
00197 // *****************************************************************************
00198 // *****************************************************************************
00199 // Section: CAN Transmit
00200 
00201 // *****************************************************************************
00202 //! Configure Transmit FIFO
00203 
00204     int8_t DRV_CANFDSPI_TransmitChannelConfigure(CANFDSPI_MODULE_ID index,
00205             CAN_FIFO_CHANNEL channel, CAN_TX_FIFO_CONFIG* config);
00206 
00207 // *****************************************************************************
00208 //! Reset TransmitChannelConfigure object to reset values
00209 
00210     int8_t DRV_CANFDSPI_TransmitChannelConfigureObjectReset(CAN_TX_FIFO_CONFIG* config);
00211 
00212 // *****************************************************************************
00213 //! Configure Transmit Queue
00214 
00215     int8_t DRV_CANFDSPI_TransmitQueueConfigure(CANFDSPI_MODULE_ID index,
00216             CAN_TX_QUEUE_CONFIG* config);
00217 
00218 // *****************************************************************************
00219 //! Reset TransmitQueueConfigure object to reset values
00220 
00221     int8_t DRV_CANFDSPI_TransmitQueueConfigureObjectReset(CAN_TX_QUEUE_CONFIG* config);
00222 
00223 // *****************************************************************************
00224 //! TX Channel Load
00225     /*!
00226      * Loads data into Transmit channel
00227      * Requests transmission, if flush==true
00228      */
00229 
00230     int8_t DRV_CANFDSPI_TransmitChannelLoad(CANFDSPI_MODULE_ID index,
00231                                             CAN_FIFO_CHANNEL channel, CAN_TX_MSGOBJ* txObj,
00232                                             uint8_t *txd, uint32_t txdNumBytes, bool flush);
00233 
00234 // *****************************************************************************
00235 //! TX Channel Flush
00236     /*!
00237      * Set TXREG of one channel
00238      */
00239 
00240     int8_t DRV_CANFDSPI_TransmitChannelFlush(CANFDSPI_MODULE_ID index,
00241             CAN_FIFO_CHANNEL channel);
00242 
00243 // *****************************************************************************
00244 //! Transmit Channel Status Get
00245 
00246     int8_t DRV_CANFDSPI_TransmitChannelStatusGet(CANFDSPI_MODULE_ID index,
00247             CAN_FIFO_CHANNEL channel, CAN_TX_FIFO_STATUS* status);
00248 
00249 // *****************************************************************************
00250 //! Transmit FIFO Reset
00251 
00252     int8_t DRV_CANFDSPI_TransmitChannelReset(CANFDSPI_MODULE_ID index,
00253             CAN_FIFO_CHANNEL channel);
00254 
00255 // *****************************************************************************
00256 //! Transmit FIFO Update
00257     /*!
00258      * Sets UINC of the transmit channel. Keeps TXREQ unchanged.
00259      */
00260 
00261     int8_t DRV_CANFDSPI_TransmitChannelUpdate(CANFDSPI_MODULE_ID index,
00262             CAN_FIFO_CHANNEL channel, bool flush);
00263 
00264 // *****************************************************************************
00265 //! Request transmissions using TXREQ register
00266 
00267     int8_t DRV_CANFDSPI_TransmitRequestSet(CANFDSPI_MODULE_ID index,
00268                                            CAN_TXREQ_CHANNEL txreq);
00269 
00270 // *****************************************************************************
00271 //! Get TXREQ register
00272 
00273     int8_t DRV_CANFDSPI_TransmitRequestGet(CANFDSPI_MODULE_ID index,
00274                                            uint32_t* txreq);
00275 
00276 // *****************************************************************************
00277 //! Abort transmission of single FIFO
00278 
00279     int8_t DRV_CANFDSPI_TransmitChannelAbort(CANFDSPI_MODULE_ID index,
00280             CAN_FIFO_CHANNEL channel);
00281 
00282 // *****************************************************************************
00283 //! Abort All transmissions
00284 
00285     int8_t DRV_CANFDSPI_TransmitAbortAll(CANFDSPI_MODULE_ID index);
00286 
00287 // *****************************************************************************
00288 //! Set Transmit Bandwidth Sharing Delay
00289     int8_t DRV_CANFDSPI_TransmitBandWidthSharingSet(CANFDSPI_MODULE_ID index,
00290             CAN_TX_BANDWITH_SHARING txbws);
00291 
00292 
00293 // *****************************************************************************
00294 // *****************************************************************************
00295 // Section: CAN Receive
00296 
00297 // *****************************************************************************
00298 //! Filter Object Configuration
00299     /*!
00300      * Configures ID of filter object
00301      */
00302 
00303     int8_t DRV_CANFDSPI_FilterObjectConfigure(CANFDSPI_MODULE_ID index,
00304             CAN_FILTER filter, CAN_FILTEROBJ_ID* id);
00305 
00306 // *****************************************************************************
00307 //! Filter Mask Configuration
00308     /*!
00309      * Configures Mask of filter object
00310      */
00311 
00312     int8_t DRV_CANFDSPI_FilterMaskConfigure(CANFDSPI_MODULE_ID index,
00313                                             CAN_FILTER filter, CAN_MASKOBJ_ID* mask);
00314 
00315 // *****************************************************************************
00316 //! Link Filter to FIFO
00317     /*!
00318      * Initializes the Pointer from Filter to FIFO
00319      * Enables or disables the Filter
00320      */
00321 
00322     int8_t DRV_CANFDSPI_FilterToFifoLink(CANFDSPI_MODULE_ID index,
00323                                          CAN_FILTER filter, CAN_FIFO_CHANNEL channel, bool enable);
00324 
00325 // *****************************************************************************
00326 //! Filter Enable
00327 
00328     int8_t DRV_CANFDSPI_FilterEnable(CANFDSPI_MODULE_ID index, CAN_FILTER filter);
00329 
00330 // *****************************************************************************
00331 //! Filter Disable
00332 
00333     int8_t DRV_CANFDSPI_FilterDisable(CANFDSPI_MODULE_ID index, CAN_FILTER filter);
00334 
00335 // *****************************************************************************
00336 //! Set Device Net Filter Count
00337     int8_t DRV_CANFDSPI_DeviceNetFilterCountSet(CANFDSPI_MODULE_ID index,
00338             CAN_DNET_FILTER_SIZE dnfc);
00339 
00340 // *****************************************************************************
00341 //! Configure Receive FIFO
00342 
00343     int8_t DRV_CANFDSPI_ReceiveChannelConfigure(CANFDSPI_MODULE_ID index,
00344             CAN_FIFO_CHANNEL channel, CAN_RX_FIFO_CONFIG* config);
00345 
00346 // *****************************************************************************
00347 //! Reset ReceiveChannelConfigure object to reset value
00348 
00349     int8_t DRV_CANFDSPI_ReceiveChannelConfigureObjectReset(CAN_RX_FIFO_CONFIG* config);
00350 
00351 // *****************************************************************************
00352 //! Receive Channel Status Get
00353 
00354     int8_t DRV_CANFDSPI_ReceiveChannelStatusGet(CANFDSPI_MODULE_ID index,
00355             CAN_FIFO_CHANNEL channel, CAN_RX_FIFO_STATUS* status);
00356 
00357 // *****************************************************************************
00358 //! Get Received Message
00359     /*!
00360      * Reads Received message from channel
00361      */
00362 
00363     int8_t DRV_CANFDSPI_ReceiveMessageGet(CANFDSPI_MODULE_ID index,
00364                                           CAN_FIFO_CHANNEL channel, CAN_RX_MSGOBJ* rxObj,
00365                                           uint8_t *rxd, uint8_t nBytes);
00366 
00367 // *****************************************************************************
00368 //! Receive FIFO Reset
00369 
00370     int8_t DRV_CANFDSPI_ReceiveChannelReset(CANFDSPI_MODULE_ID index,
00371                                             CAN_FIFO_CHANNEL channel);
00372 
00373 // *****************************************************************************
00374 //! Receive FIFO Update
00375     /*!
00376      * Sets UINC of the receive channel.
00377      */
00378 
00379     int8_t DRV_CANFDSPI_ReceiveChannelUpdate(CANFDSPI_MODULE_ID index,
00380             CAN_FIFO_CHANNEL channel);
00381 
00382 
00383 // *****************************************************************************
00384 // *****************************************************************************
00385 // Section: Transmit Event FIFO
00386 
00387 // *****************************************************************************
00388 //! Transmit Event FIFO Status Get
00389 
00390     int8_t DRV_CANFDSPI_TefStatusGet(CANFDSPI_MODULE_ID index,
00391                                      CAN_TEF_FIFO_STATUS* status);
00392 
00393 // *****************************************************************************
00394 //! Get Transmit Event FIFO Message
00395     /*!
00396      * Reads Transmit Event FIFO message
00397      */
00398 
00399     int8_t DRV_CANFDSPI_TefMessageGet(CANFDSPI_MODULE_ID index,
00400                                       CAN_TEF_MSGOBJ* tefObj);
00401 
00402 // *****************************************************************************
00403 //! Transmit Event FIFO Reset
00404 
00405     int8_t DRV_CANFDSPI_TefReset(CANFDSPI_MODULE_ID index);
00406 
00407 // *****************************************************************************
00408 //! Transmit Event FIFO Update
00409     /*!
00410      * Sets UINC of the TEF.
00411      */
00412 
00413     int8_t DRV_CANFDSPI_TefUpdate(CANFDSPI_MODULE_ID index);
00414 
00415 // *****************************************************************************
00416 //! Configure Transmit Event FIFO
00417 
00418     int8_t DRV_CANFDSPI_TefConfigure(CANFDSPI_MODULE_ID index, CAN_TEF_CONFIG* config);
00419 
00420 // *****************************************************************************
00421 //! Reset TefConfigure object to reset value
00422 
00423     int8_t DRV_CANFDSPI_TefConfigureObjectReset(CAN_TEF_CONFIG* config);
00424 
00425 
00426 // *****************************************************************************
00427 // *****************************************************************************
00428 // Section: Module Events
00429 
00430 // *****************************************************************************
00431 //! Module Event Get
00432     /*!
00433      * Reads interrupt Flags
00434      */
00435 
00436     int8_t DRV_CANFDSPI_ModuleEventGet(CANFDSPI_MODULE_ID index,
00437                                        CAN_MODULE_EVENT* flags);
00438 
00439 // *****************************************************************************
00440 //! Module Event Enable
00441     /*!
00442      * Enables interrupts
00443      */
00444 
00445     int8_t DRV_CANFDSPI_ModuleEventEnable(CANFDSPI_MODULE_ID index,
00446                                           CAN_MODULE_EVENT flags);
00447 
00448 // *****************************************************************************
00449 //! Module Event Disable
00450     /*!
00451      * Disables interrupts
00452      */
00453 
00454     int8_t DRV_CANFDSPI_ModuleEventDisable(CANFDSPI_MODULE_ID index,
00455                                            CAN_MODULE_EVENT flags);
00456 
00457 // *****************************************************************************
00458 //! Module Event Clear
00459     /*!
00460      * Clears interrupt Flags
00461      */
00462 
00463     int8_t DRV_CANFDSPI_ModuleEventClear(CANFDSPI_MODULE_ID index,
00464                                          CAN_MODULE_EVENT flags);
00465 
00466 // *****************************************************************************
00467 //! Get RX Code
00468 
00469     int8_t DRV_CANFDSPI_ModuleEventRxCodeGet(CANFDSPI_MODULE_ID index,
00470             CAN_RXCODE* rxCode);
00471 
00472 // *****************************************************************************
00473 //! Get TX Code
00474 
00475     int8_t DRV_CANFDSPI_ModuleEventTxCodeGet(CANFDSPI_MODULE_ID index,
00476             CAN_TXCODE* txCode);
00477 
00478 // *****************************************************************************
00479 //! Get Filter Hit
00480 
00481     int8_t DRV_CANFDSPI_ModuleEventFilterHitGet(CANFDSPI_MODULE_ID index,
00482             CAN_FILTER* filterHit);
00483 
00484 // *****************************************************************************
00485 //! Get ICODE
00486 
00487     int8_t DRV_CANFDSPI_ModuleEventIcodeGet(CANFDSPI_MODULE_ID index,
00488                                             CAN_ICODE* icode);
00489 
00490 // *****************************************************************************
00491 // *****************************************************************************
00492 // Section: Transmit FIFO Events
00493 
00494 // *****************************************************************************
00495 //! Transmit FIFO Event Get
00496     /*!
00497      * Reads Transmit FIFO interrupt Flags
00498      */
00499 
00500     int8_t DRV_CANFDSPI_TransmitChannelEventGet(CANFDSPI_MODULE_ID index,
00501             CAN_FIFO_CHANNEL channel, CAN_TX_FIFO_EVENT* flags);
00502 
00503 // *****************************************************************************
00504 //! Get pending interrupts of all transmit FIFOs
00505 
00506     int8_t DRV_CANFDSPI_TransmitEventGet(CANFDSPI_MODULE_ID index, uint32_t* txif);
00507 
00508 // *****************************************************************************
00509 //! Get pending TXATIF of all transmit FIFOs
00510 
00511     int8_t DRV_CANFDSPI_TransmitEventAttemptGet(CANFDSPI_MODULE_ID index,
00512             uint32_t* txatif);
00513 
00514 // *****************************************************************************
00515 //! Transmit FIFO Index Get
00516     /*!
00517      * Reads Transmit FIFO Index
00518      */
00519 
00520     int8_t DRV_CANFDSPI_TransmitChannelIndexGet(CANFDSPI_MODULE_ID index,
00521             CAN_FIFO_CHANNEL channel, uint8_t* idx);
00522 
00523 // *****************************************************************************
00524 //! Transmit FIFO Event Enable
00525     /*!
00526      * Enables Transmit FIFO interrupts
00527      */
00528 
00529     int8_t DRV_CANFDSPI_TransmitChannelEventEnable(CANFDSPI_MODULE_ID index,
00530             CAN_FIFO_CHANNEL channel, CAN_TX_FIFO_EVENT flags);
00531 
00532 // *****************************************************************************
00533 //! Transmit FIFO Event Disable
00534     /*!
00535      * Disables Transmit FIFO interrupts
00536      */
00537 
00538     int8_t DRV_CANFDSPI_TransmitChannelEventDisable(CANFDSPI_MODULE_ID index,
00539             CAN_FIFO_CHANNEL channel, CAN_TX_FIFO_EVENT flags);
00540 
00541 // *****************************************************************************
00542 //! Transmit FIFO Event Clear
00543     /*!
00544      * Clears Transmit FIFO Attempts Exhausted interrupt Flag
00545      */
00546 
00547     int8_t DRV_CANFDSPI_TransmitChannelEventAttemptClear(CANFDSPI_MODULE_ID index,
00548             CAN_FIFO_CHANNEL channel);
00549 
00550 
00551 // *****************************************************************************
00552 // *****************************************************************************
00553 // Section: Receive FIFO Events
00554 
00555 // *****************************************************************************
00556 //! Receive FIFO Event Get
00557     /*!
00558      * Reads Receive FIFO interrupt Flags
00559      */
00560 
00561     int8_t DRV_CANFDSPI_ReceiveChannelEventGet(CANFDSPI_MODULE_ID index,
00562             CAN_FIFO_CHANNEL channel, CAN_RX_FIFO_EVENT* flags);
00563 
00564 // *****************************************************************************
00565 //! Get pending interrupts of all receive FIFOs
00566 
00567     int8_t DRV_CANFDSPI_ReceiveEventGet(CANFDSPI_MODULE_ID index, uint32_t* rxif);
00568 
00569 // *****************************************************************************
00570 //!Get pending RXOVIF of all receive FIFOs
00571 
00572     int8_t DRV_CANFDSPI_ReceiveEventOverflowGet(CANFDSPI_MODULE_ID index, uint32_t* rxovif);
00573 
00574 // *****************************************************************************
00575 //! Receive FIFO Index Get
00576     /*!
00577      * Reads Receive FIFO Index
00578      */
00579 
00580     int8_t DRV_CANFDSPI_ReceiveChannelIndexGet(CANFDSPI_MODULE_ID index,
00581             CAN_FIFO_CHANNEL channel, uint8_t* idx);
00582 
00583 // *****************************************************************************
00584 //! Receive FIFO Event Enable
00585     /*!
00586      * Enables Receive FIFO interrupts
00587      */
00588 
00589     int8_t DRV_CANFDSPI_ReceiveChannelEventEnable(CANFDSPI_MODULE_ID index,
00590             CAN_FIFO_CHANNEL channel, CAN_RX_FIFO_EVENT flags);
00591 
00592 // *****************************************************************************
00593 //! Receive FIFO Event Disable
00594     /*!
00595      * Disables Receive FIFO interrupts
00596      */
00597 
00598     int8_t DRV_CANFDSPI_ReceiveChannelEventDisable(CANFDSPI_MODULE_ID index,
00599             CAN_FIFO_CHANNEL channel, CAN_RX_FIFO_EVENT flags);
00600 
00601 // *****************************************************************************
00602 //! Receive FIFO Event Clear
00603     /*!
00604      * Clears Receive FIFO Overflow interrupt Flag
00605      */
00606 
00607     int8_t DRV_CANFDSPI_ReceiveChannelEventOverflowClear(CANFDSPI_MODULE_ID index,
00608             CAN_FIFO_CHANNEL channel);
00609 
00610 
00611 // *****************************************************************************
00612 // *****************************************************************************
00613 // Section: Transmit Event FIFO Events
00614 
00615 // *****************************************************************************
00616 //! Transmit Event FIFO Event Get
00617     /*!
00618      * Reads Transmit Event FIFO interrupt Flags
00619      */
00620 
00621     int8_t DRV_CANFDSPI_TefEventGet(CANFDSPI_MODULE_ID index,
00622                                     CAN_TEF_FIFO_EVENT* flags);
00623 
00624 // *****************************************************************************
00625 //! Transmit Event FIFO Event Enable
00626     /*!
00627      * Enables Transmit Event FIFO interrupts
00628      */
00629 
00630     int8_t DRV_CANFDSPI_TefEventEnable(CANFDSPI_MODULE_ID index,
00631                                        CAN_TEF_FIFO_EVENT flags);
00632 
00633 // *****************************************************************************
00634 //! Transmit Event FIFO Event Disable
00635     /*!
00636      * Disables Transmit Event FIFO interrupts
00637      */
00638 
00639     int8_t DRV_CANFDSPI_TefEventDisable(CANFDSPI_MODULE_ID index,
00640                                         CAN_TEF_FIFO_EVENT flags);
00641 
00642 // *****************************************************************************
00643 //! Transmit Event FIFO Event Clear
00644     /*!
00645      * Clears Transmit Event FIFO Overflow interrupt Flag
00646      */
00647 
00648     int8_t DRV_CANFDSPI_TefEventOverflowClear(CANFDSPI_MODULE_ID index);
00649 
00650 
00651 // *****************************************************************************
00652 // *****************************************************************************
00653 // Section: Error Handling
00654 
00655 // *****************************************************************************
00656 //! Transmit Error Count Get
00657 
00658     int8_t DRV_CANFDSPI_ErrorCountTransmitGet(CANFDSPI_MODULE_ID index,
00659             uint8_t* tec);
00660 
00661 // *****************************************************************************
00662 //! Receive Error Count Get
00663 
00664     int8_t DRV_CANFDSPI_ErrorCountReceiveGet(CANFDSPI_MODULE_ID index,
00665             uint8_t* rec);
00666 
00667 // *****************************************************************************
00668 //! Error State Get
00669 
00670     int8_t DRV_CANFDSPI_ErrorStateGet(CANFDSPI_MODULE_ID index,
00671                                       CAN_ERROR_STATE* flags);
00672 
00673 // *****************************************************************************
00674 //! Error Counts and Error State Get
00675     /*!
00676      * Returns content of complete CiTREC
00677      */
00678 
00679     int8_t DRV_CANFDSPI_ErrorCountStateGet(CANFDSPI_MODULE_ID index,
00680                                            uint8_t* tec, uint8_t* rec, CAN_ERROR_STATE* flags);
00681 
00682 // *****************************************************************************
00683 //! Get Bus Diagnostic Registers: all data at once, since we want to keep them in synch
00684 
00685     int8_t DRV_CANFDSPI_BusDiagnosticsGet(CANFDSPI_MODULE_ID index,
00686                                           CAN_BUS_DIAGNOSTIC* bd);
00687 
00688 // *****************************************************************************
00689 //! Clear Bus Diagnostic Registers
00690 
00691     int8_t DRV_CANFDSPI_BusDiagnosticsClear(CANFDSPI_MODULE_ID index);
00692 
00693 
00694 // *****************************************************************************
00695 // *****************************************************************************
00696 // Section: ECC
00697 
00698 // *****************************************************************************
00699 //! Enable ECC
00700 
00701     int8_t DRV_CANFDSPI_EccEnable(CANFDSPI_MODULE_ID index);
00702 
00703 // *****************************************************************************
00704 //! Disable ECC
00705 
00706     int8_t DRV_CANFDSPI_EccDisable(CANFDSPI_MODULE_ID index);
00707 
00708 // *****************************************************************************
00709 //! ECC Event Get
00710 
00711     int8_t DRV_CANFDSPI_EccEventGet(CANFDSPI_MODULE_ID index,
00712                                     CAN_ECC_EVENT* flags);
00713 
00714 // *****************************************************************************
00715 //! Set ECC Parity
00716 
00717     int8_t DRV_CANFDSPI_EccParitySet(CANFDSPI_MODULE_ID index,
00718                                      uint8_t parity);
00719 
00720 // *****************************************************************************
00721 //! Get ECC Parity
00722 
00723     int8_t DRV_CANFDSPI_EccParityGet(CANFDSPI_MODULE_ID index,
00724                                      uint8_t* parity);
00725 
00726 // *****************************************************************************
00727 //! Get ECC Error Address
00728 
00729     int8_t DRV_CANFDSPI_EccErrorAddressGet(CANFDSPI_MODULE_ID index,
00730                                            uint16_t* a);
00731 
00732 // *****************************************************************************
00733 //! ECC Event Enable
00734 
00735     int8_t DRV_CANFDSPI_EccEventEnable(CANFDSPI_MODULE_ID index,
00736                                        CAN_ECC_EVENT flags);
00737 
00738 // *****************************************************************************
00739 //! ECC Event Disable
00740 
00741     int8_t DRV_CANFDSPI_EccEventDisable(CANFDSPI_MODULE_ID index,
00742                                         CAN_ECC_EVENT flags);
00743 
00744 // *****************************************************************************
00745 //! ECC Event Clear
00746 
00747     int8_t DRV_CANFDSPI_EccEventClear(CANFDSPI_MODULE_ID index,
00748                                       CAN_ECC_EVENT flags);
00749 
00750 // *****************************************************************************
00751 //! Initialize RAM
00752 
00753     int8_t DRV_CANFDSPI_RamInit(CANFDSPI_MODULE_ID index, uint8_t d);
00754 
00755 
00756 // *****************************************************************************
00757 // *****************************************************************************
00758 // Section: CRC
00759 
00760 // *****************************************************************************
00761 //! CRC Event Enable
00762 
00763     int8_t DRV_CANFDSPI_CrcEventEnable(CANFDSPI_MODULE_ID index,
00764                                        CAN_CRC_EVENT flags);
00765 
00766 // *****************************************************************************
00767 //! CRC Event Disable
00768 
00769     int8_t DRV_CANFDSPI_CrcEventDisable(CANFDSPI_MODULE_ID index,
00770                                         CAN_CRC_EVENT flags);
00771 
00772 // *****************************************************************************
00773 //! CRC Event Clear
00774 
00775     int8_t DRV_CANFDSPI_CrcEventClear(CANFDSPI_MODULE_ID index,
00776                                       CAN_CRC_EVENT flags);
00777 
00778 // *****************************************************************************
00779 //! CRC Event Get
00780 
00781     int8_t DRV_CANFDSPI_CrcEventGet(CANFDSPI_MODULE_ID index, CAN_CRC_EVENT* flags);
00782 
00783 // *****************************************************************************
00784 //! Get CRC Value from device
00785 
00786     int8_t DRV_CANFDSPI_CrcValueGet(CANFDSPI_MODULE_ID index, uint16_t* crc);
00787 
00788 
00789 // *****************************************************************************
00790 // *****************************************************************************
00791 // Section: Time Stamp
00792 
00793 // *****************************************************************************
00794 //! Time Stamp Enable
00795 
00796     int8_t DRV_CANFDSPI_TimeStampEnable(CANFDSPI_MODULE_ID index);
00797 
00798 // *****************************************************************************
00799 //! Time Stamp Disable
00800 
00801     int8_t DRV_CANFDSPI_TimeStampDisable(CANFDSPI_MODULE_ID index);
00802 
00803 // *****************************************************************************
00804 //! Time Stamp Get
00805 
00806     int8_t DRV_CANFDSPI_TimeStampGet(CANFDSPI_MODULE_ID index, uint32_t* ts);
00807 
00808 // *****************************************************************************
00809 //! Time Stamp Set
00810 
00811     int8_t DRV_CANFDSPI_TimeStampSet(CANFDSPI_MODULE_ID index, uint32_t ts);
00812 
00813 // *****************************************************************************
00814 //! Time Stamp Mode Configure
00815 
00816     int8_t DRV_CANFDSPI_TimeStampModeConfigure(CANFDSPI_MODULE_ID index,
00817             CAN_TS_MODE mode);
00818 
00819 // *****************************************************************************
00820 //! Time Stamp Prescaler Set
00821 
00822     int8_t DRV_CANFDSPI_TimeStampPrescalerSet(CANFDSPI_MODULE_ID index,
00823             uint16_t ps);
00824 
00825 
00826 // *****************************************************************************
00827 // *****************************************************************************
00828 // Section: Oscillator and Bit Time
00829 
00830 // *****************************************************************************
00831 //! Enable oscillator to wake-up from sleep
00832 
00833     int8_t DRV_CANFDSPI_OscillatorEnable(CANFDSPI_MODULE_ID index);
00834 
00835 // *****************************************************************************
00836 //! Set Oscillator Control
00837 
00838     int8_t DRV_CANFDSPI_OscillatorControlSet(CANFDSPI_MODULE_ID index,
00839             CAN_OSC_CTRL ctrl);
00840 
00841     int8_t DRV_CANFDSPI_OscillatorControlObjectReset(CAN_OSC_CTRL* ctrl);
00842 
00843 
00844 // *****************************************************************************
00845 //! Get Oscillator Status
00846 
00847     int8_t DRV_CANFDSPI_OscillatorStatusGet(CANFDSPI_MODULE_ID index,
00848                                             CAN_OSC_STATUS* status);
00849 
00850 // *****************************************************************************
00851 //! Configure Bit Time registers (based on CAN clock speed)
00852 
00853     int8_t DRV_CANFDSPI_BitTimeConfigure(CANFDSPI_MODULE_ID index,
00854                                          CAN_BITTIME_SETUP bitTime, CAN_SSP_MODE sspMode,
00855                                          CAN_SYSCLK_SPEED clk);
00856 
00857 // *****************************************************************************
00858 //! Configure Nominal bit time for 40MHz system clock
00859 
00860     int8_t DRV_CANFDSPI_BitTimeConfigureNominal40MHz(CANFDSPI_MODULE_ID index,
00861             CAN_BITTIME_SETUP bitTime);
00862 
00863 // *****************************************************************************
00864 //! Configure Data bit time for 40MHz system clock
00865 
00866     int8_t DRV_CANFDSPI_BitTimeConfigureData40MHz(CANFDSPI_MODULE_ID index,
00867             CAN_BITTIME_SETUP bitTime, CAN_SSP_MODE sspMode);
00868 
00869 // *****************************************************************************
00870 //! Configure Nominal bit time for 20MHz system clock
00871 
00872     int8_t DRV_CANFDSPI_BitTimeConfigureNominal20MHz(CANFDSPI_MODULE_ID index,
00873             CAN_BITTIME_SETUP bitTime);
00874 
00875 // *****************************************************************************
00876 //! Configure Data bit time for 20MHz system clock
00877 
00878     int8_t DRV_CANFDSPI_BitTimeConfigureData20MHz(CANFDSPI_MODULE_ID index,
00879             CAN_BITTIME_SETUP bitTime, CAN_SSP_MODE sspMode);
00880 
00881 // *****************************************************************************
00882 //! Configure Nominal bit time for 10MHz system clock
00883 
00884     int8_t DRV_CANFDSPI_BitTimeConfigureNominal10MHz(CANFDSPI_MODULE_ID index,
00885             CAN_BITTIME_SETUP bitTime);
00886 
00887 // *****************************************************************************
00888 //! Configure Data bit time for 10MHz system clock
00889 
00890     int8_t DRV_CANFDSPI_BitTimeConfigureData10MHz(CANFDSPI_MODULE_ID index,
00891             CAN_BITTIME_SETUP bitTime, CAN_SSP_MODE sspMode);
00892 
00893 
00894 // *****************************************************************************
00895 // *****************************************************************************
00896 // Section: GPIO
00897 
00898 // *****************************************************************************
00899 //! Initialize GPIO Mode
00900 
00901     int8_t DRV_CANFDSPI_GpioModeConfigure(CANFDSPI_MODULE_ID index,
00902                                           GPIO_PIN_MODE gpio0, GPIO_PIN_MODE gpio1);
00903 
00904 // *****************************************************************************
00905 //! Initialize GPIO Direction
00906 
00907     int8_t DRV_CANFDSPI_GpioDirectionConfigure(CANFDSPI_MODULE_ID index,
00908             GPIO_PIN_DIRECTION gpio0, GPIO_PIN_DIRECTION gpio1);
00909 
00910 // *****************************************************************************
00911 //! Enable Transceiver Standby Control
00912 
00913     int8_t DRV_CANFDSPI_GpioStandbyControlEnable(CANFDSPI_MODULE_ID index);
00914 
00915 // *****************************************************************************
00916 //! Disable Transceiver Standby Control
00917 
00918     int8_t DRV_CANFDSPI_GpioStandbyControlDisable(CANFDSPI_MODULE_ID index);
00919 
00920 // *****************************************************************************
00921 //! Configure Open Drain Interrupts
00922 
00923     int8_t DRV_CANFDSPI_GpioInterruptPinsOpenDrainConfigure(CANFDSPI_MODULE_ID index,
00924             GPIO_OPEN_DRAIN_MODE mode);
00925 
00926 // *****************************************************************************
00927 //! Configure Open Drain TXCAN
00928 
00929     int8_t DRV_CANFDSPI_GpioTransmitPinOpenDrainConfigure(CANFDSPI_MODULE_ID index,
00930             GPIO_OPEN_DRAIN_MODE mode);
00931 
00932 // *****************************************************************************
00933 //! GPIO Output Pin Set
00934 
00935     int8_t DRV_CANFDSPI_GpioPinSet(CANFDSPI_MODULE_ID index,
00936                                    GPIO_PIN_POS pos, GPIO_PIN_STATE latch);
00937 
00938 // *****************************************************************************
00939 //! GPIO Input Pin Read
00940 
00941     int8_t DRV_CANFDSPI_GpioPinRead(CANFDSPI_MODULE_ID index,
00942                                     GPIO_PIN_POS pos, GPIO_PIN_STATE* state);
00943 
00944 // *****************************************************************************
00945 //! Configure CLKO Pin
00946 
00947     int8_t DRV_CANFDSPI_GpioClockOutputConfigure(CANFDSPI_MODULE_ID index,
00948             GPIO_CLKO_MODE mode);
00949 
00950 
00951 // *****************************************************************************
00952 // *****************************************************************************
00953 // Section: Miscellaneous
00954 
00955 // *****************************************************************************
00956 //! DLC to number of actual data bytes conversion
00957 
00958     uint32_t DRV_CANFDSPI_DlcToDataBytes(CAN_DLC dlc);
00959 
00960 // *****************************************************************************
00961 //! FIFO Index Get
00962 
00963     int8_t DRV_CANFDSPI_FifoIndexGet(CANFDSPI_MODULE_ID index,
00964                                      CAN_FIFO_CHANNEL channel, uint8_t* mi);
00965 
00966 // *****************************************************************************
00967 //! Calculate CRC16
00968 
00969     uint16_t DRV_CANFDSPI_CalculateCRC16(uint8_t* data, uint16_t size);
00970 
00971 // *****************************************************************************
00972 //! Data bytes to DLC conversion
00973 
00974     CAN_DLC DRV_CANFDSPI_DataBytesToDlc(uint8_t n);
00975 
00976 #ifdef __cplusplus  // Provide C++ Compatibility
00977 }
00978 #endif
00979 
00980 #endif // _DRV_CANFDSPI_API_H
00981