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targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l151xc.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
67:4bcbbb9fcddf 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 67:4bcbbb9fcddf 1 /**
mbed_official 67:4bcbbb9fcddf 2 ******************************************************************************
mbed_official 67:4bcbbb9fcddf 3 * @file stm32l151xc.h
mbed_official 67:4bcbbb9fcddf 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V2.1.3
<> 144:ef7eb2e8f9f7 6 * @date 04-March-2016
mbed_official 67:4bcbbb9fcddf 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
mbed_official 67:4bcbbb9fcddf 8 * This file contains all the peripheral register's definitions, bits
mbed_official 67:4bcbbb9fcddf 9 * definitions and memory mapping for STM32L1xx devices.
mbed_official 67:4bcbbb9fcddf 10 *
mbed_official 67:4bcbbb9fcddf 11 * This file contains:
mbed_official 67:4bcbbb9fcddf 12 * - Data structures and the address mapping for all peripherals
mbed_official 67:4bcbbb9fcddf 13 * - Peripheral's registers declarations and bits definition
mbed_official 67:4bcbbb9fcddf 14 * - Macros to access peripheral’s registers hardware
mbed_official 67:4bcbbb9fcddf 15 *
mbed_official 67:4bcbbb9fcddf 16 ******************************************************************************
mbed_official 67:4bcbbb9fcddf 17 * @attention
mbed_official 67:4bcbbb9fcddf 18 *
<> 144:ef7eb2e8f9f7 19 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
mbed_official 67:4bcbbb9fcddf 20 *
mbed_official 67:4bcbbb9fcddf 21 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 67:4bcbbb9fcddf 22 * are permitted provided that the following conditions are met:
mbed_official 67:4bcbbb9fcddf 23 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 67:4bcbbb9fcddf 24 * this list of conditions and the following disclaimer.
mbed_official 67:4bcbbb9fcddf 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 67:4bcbbb9fcddf 26 * this list of conditions and the following disclaimer in the documentation
mbed_official 67:4bcbbb9fcddf 27 * and/or other materials provided with the distribution.
mbed_official 67:4bcbbb9fcddf 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 67:4bcbbb9fcddf 29 * may be used to endorse or promote products derived from this software
mbed_official 67:4bcbbb9fcddf 30 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 31 *
mbed_official 67:4bcbbb9fcddf 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 67:4bcbbb9fcddf 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 67:4bcbbb9fcddf 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 67:4bcbbb9fcddf 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 67:4bcbbb9fcddf 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 67:4bcbbb9fcddf 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 67:4bcbbb9fcddf 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 67:4bcbbb9fcddf 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 67:4bcbbb9fcddf 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 67:4bcbbb9fcddf 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 67:4bcbbb9fcddf 42 *
mbed_official 67:4bcbbb9fcddf 43 ******************************************************************************
mbed_official 67:4bcbbb9fcddf 44 */
mbed_official 67:4bcbbb9fcddf 45
mbed_official 67:4bcbbb9fcddf 46 /** @addtogroup CMSIS
mbed_official 67:4bcbbb9fcddf 47 * @{
mbed_official 67:4bcbbb9fcddf 48 */
mbed_official 67:4bcbbb9fcddf 49
mbed_official 67:4bcbbb9fcddf 50 /** @addtogroup stm32l151xc
mbed_official 67:4bcbbb9fcddf 51 * @{
mbed_official 67:4bcbbb9fcddf 52 */
mbed_official 67:4bcbbb9fcddf 53
mbed_official 67:4bcbbb9fcddf 54 #ifndef __STM32L151xC_H
mbed_official 67:4bcbbb9fcddf 55 #define __STM32L151xC_H
mbed_official 67:4bcbbb9fcddf 56
mbed_official 67:4bcbbb9fcddf 57 #ifdef __cplusplus
mbed_official 67:4bcbbb9fcddf 58 extern "C" {
mbed_official 67:4bcbbb9fcddf 59 #endif
mbed_official 67:4bcbbb9fcddf 60
mbed_official 67:4bcbbb9fcddf 61
mbed_official 67:4bcbbb9fcddf 62 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 67:4bcbbb9fcddf 63 * @{
mbed_official 67:4bcbbb9fcddf 64 */
mbed_official 67:4bcbbb9fcddf 65 /**
mbed_official 67:4bcbbb9fcddf 66 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
mbed_official 67:4bcbbb9fcddf 67 */
<> 144:ef7eb2e8f9f7 68 #define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */
<> 144:ef7eb2e8f9f7 69 #define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */
<> 144:ef7eb2e8f9f7 70 #define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */
<> 144:ef7eb2e8f9f7 71 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
mbed_official 67:4bcbbb9fcddf 72
mbed_official 67:4bcbbb9fcddf 73 /**
mbed_official 67:4bcbbb9fcddf 74 * @}
mbed_official 67:4bcbbb9fcddf 75 */
mbed_official 67:4bcbbb9fcddf 76
mbed_official 67:4bcbbb9fcddf 77 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 67:4bcbbb9fcddf 78 * @{
mbed_official 67:4bcbbb9fcddf 79 */
mbed_official 67:4bcbbb9fcddf 80
mbed_official 67:4bcbbb9fcddf 81 /**
mbed_official 67:4bcbbb9fcddf 82 * @brief STM32L1xx Interrupt Number Definition, according to the selected device
mbed_official 67:4bcbbb9fcddf 83 * in @ref Library_configuration_section
mbed_official 67:4bcbbb9fcddf 84 */
mbed_official 67:4bcbbb9fcddf 85
mbed_official 67:4bcbbb9fcddf 86 /*!< Interrupt Number Definition */
mbed_official 67:4bcbbb9fcddf 87 typedef enum
mbed_official 67:4bcbbb9fcddf 88 {
mbed_official 67:4bcbbb9fcddf 89 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
mbed_official 67:4bcbbb9fcddf 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 91 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
mbed_official 67:4bcbbb9fcddf 92 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
mbed_official 67:4bcbbb9fcddf 93 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
mbed_official 67:4bcbbb9fcddf 94 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
mbed_official 67:4bcbbb9fcddf 95 SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
mbed_official 67:4bcbbb9fcddf 96 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
mbed_official 67:4bcbbb9fcddf 97 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
mbed_official 67:4bcbbb9fcddf 98 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
mbed_official 67:4bcbbb9fcddf 99
mbed_official 67:4bcbbb9fcddf 100 /****** STM32L specific Interrupt Numbers ***********************************************************/
mbed_official 67:4bcbbb9fcddf 101 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 67:4bcbbb9fcddf 102 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 67:4bcbbb9fcddf 103 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
mbed_official 67:4bcbbb9fcddf 104 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
mbed_official 67:4bcbbb9fcddf 105 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 67:4bcbbb9fcddf 106 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 67:4bcbbb9fcddf 107 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 67:4bcbbb9fcddf 108 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 67:4bcbbb9fcddf 109 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 67:4bcbbb9fcddf 110 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 67:4bcbbb9fcddf 111 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 67:4bcbbb9fcddf 112 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
mbed_official 67:4bcbbb9fcddf 113 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
mbed_official 67:4bcbbb9fcddf 114 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
mbed_official 67:4bcbbb9fcddf 115 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
mbed_official 67:4bcbbb9fcddf 116 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
mbed_official 67:4bcbbb9fcddf 117 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
mbed_official 67:4bcbbb9fcddf 118 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
mbed_official 67:4bcbbb9fcddf 119 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
mbed_official 67:4bcbbb9fcddf 120 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
mbed_official 67:4bcbbb9fcddf 121 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
mbed_official 67:4bcbbb9fcddf 122 DAC_IRQn = 21, /*!< DAC Interrupt */
mbed_official 67:4bcbbb9fcddf 123 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
mbed_official 67:4bcbbb9fcddf 124 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 67:4bcbbb9fcddf 125 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
mbed_official 67:4bcbbb9fcddf 126 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
mbed_official 67:4bcbbb9fcddf 127 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
mbed_official 67:4bcbbb9fcddf 128 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 67:4bcbbb9fcddf 129 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 67:4bcbbb9fcddf 130 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 67:4bcbbb9fcddf 131 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 67:4bcbbb9fcddf 132 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 67:4bcbbb9fcddf 133 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 67:4bcbbb9fcddf 134 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 67:4bcbbb9fcddf 135 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 67:4bcbbb9fcddf 136 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 67:4bcbbb9fcddf 137 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 67:4bcbbb9fcddf 138 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 67:4bcbbb9fcddf 139 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 67:4bcbbb9fcddf 140 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 67:4bcbbb9fcddf 141 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
mbed_official 67:4bcbbb9fcddf 142 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
mbed_official 67:4bcbbb9fcddf 143 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
mbed_official 67:4bcbbb9fcddf 144 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
mbed_official 67:4bcbbb9fcddf 145 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
mbed_official 67:4bcbbb9fcddf 146 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
mbed_official 67:4bcbbb9fcddf 147 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
mbed_official 67:4bcbbb9fcddf 148 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
mbed_official 67:4bcbbb9fcddf 149 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
mbed_official 67:4bcbbb9fcddf 150 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
mbed_official 67:4bcbbb9fcddf 151 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
mbed_official 67:4bcbbb9fcddf 152 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
mbed_official 67:4bcbbb9fcddf 153 } IRQn_Type;
mbed_official 67:4bcbbb9fcddf 154
mbed_official 67:4bcbbb9fcddf 155 /**
mbed_official 67:4bcbbb9fcddf 156 * @}
mbed_official 67:4bcbbb9fcddf 157 */
mbed_official 67:4bcbbb9fcddf 158
mbed_official 67:4bcbbb9fcddf 159 #include "core_cm3.h"
mbed_official 67:4bcbbb9fcddf 160 #include "system_stm32l1xx.h"
mbed_official 67:4bcbbb9fcddf 161 #include <stdint.h>
mbed_official 67:4bcbbb9fcddf 162
mbed_official 67:4bcbbb9fcddf 163 /** @addtogroup Peripheral_registers_structures
mbed_official 67:4bcbbb9fcddf 164 * @{
mbed_official 67:4bcbbb9fcddf 165 */
mbed_official 67:4bcbbb9fcddf 166
mbed_official 67:4bcbbb9fcddf 167 /**
mbed_official 67:4bcbbb9fcddf 168 * @brief Analog to Digital Converter
mbed_official 67:4bcbbb9fcddf 169 */
mbed_official 67:4bcbbb9fcddf 170
mbed_official 67:4bcbbb9fcddf 171 typedef struct
mbed_official 67:4bcbbb9fcddf 172 {
mbed_official 67:4bcbbb9fcddf 173 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 174 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 175 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 176 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 177 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 178 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 179 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
mbed_official 67:4bcbbb9fcddf 180 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
mbed_official 67:4bcbbb9fcddf 181 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
mbed_official 67:4bcbbb9fcddf 182 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
mbed_official 67:4bcbbb9fcddf 183 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
mbed_official 67:4bcbbb9fcddf 184 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
mbed_official 67:4bcbbb9fcddf 185 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
mbed_official 67:4bcbbb9fcddf 186 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
mbed_official 67:4bcbbb9fcddf 187 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
mbed_official 67:4bcbbb9fcddf 188 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
mbed_official 67:4bcbbb9fcddf 189 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
mbed_official 67:4bcbbb9fcddf 190 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
mbed_official 67:4bcbbb9fcddf 191 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
mbed_official 67:4bcbbb9fcddf 192 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
mbed_official 67:4bcbbb9fcddf 193 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
mbed_official 67:4bcbbb9fcddf 194 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
mbed_official 67:4bcbbb9fcddf 195 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
mbed_official 67:4bcbbb9fcddf 196 uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */
mbed_official 67:4bcbbb9fcddf 197 } ADC_TypeDef;
mbed_official 67:4bcbbb9fcddf 198
mbed_official 67:4bcbbb9fcddf 199 typedef struct
mbed_official 67:4bcbbb9fcddf 200 {
mbed_official 67:4bcbbb9fcddf 201 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
mbed_official 67:4bcbbb9fcddf 202 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
mbed_official 67:4bcbbb9fcddf 203 } ADC_Common_TypeDef;
mbed_official 67:4bcbbb9fcddf 204
mbed_official 67:4bcbbb9fcddf 205 /**
mbed_official 67:4bcbbb9fcddf 206 * @brief Comparator
mbed_official 67:4bcbbb9fcddf 207 */
mbed_official 67:4bcbbb9fcddf 208
mbed_official 67:4bcbbb9fcddf 209 typedef struct
mbed_official 67:4bcbbb9fcddf 210 {
mbed_official 67:4bcbbb9fcddf 211 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 212 } COMP_TypeDef;
mbed_official 67:4bcbbb9fcddf 213
mbed_official 67:4bcbbb9fcddf 214 /**
mbed_official 67:4bcbbb9fcddf 215 * @brief CRC calculation unit
mbed_official 67:4bcbbb9fcddf 216 */
mbed_official 67:4bcbbb9fcddf 217
mbed_official 67:4bcbbb9fcddf 218 typedef struct
mbed_official 67:4bcbbb9fcddf 219 {
mbed_official 67:4bcbbb9fcddf 220 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 221 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 222 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
<> 144:ef7eb2e8f9f7 223 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
mbed_official 67:4bcbbb9fcddf 224 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 225 } CRC_TypeDef;
mbed_official 67:4bcbbb9fcddf 226
mbed_official 67:4bcbbb9fcddf 227 /**
mbed_official 67:4bcbbb9fcddf 228 * @brief Digital to Analog Converter
mbed_official 67:4bcbbb9fcddf 229 */
mbed_official 67:4bcbbb9fcddf 230
mbed_official 67:4bcbbb9fcddf 231 typedef struct
mbed_official 67:4bcbbb9fcddf 232 {
mbed_official 67:4bcbbb9fcddf 233 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 234 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 235 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 236 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 237 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 238 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 239 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 67:4bcbbb9fcddf 240 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 67:4bcbbb9fcddf 241 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 67:4bcbbb9fcddf 242 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 67:4bcbbb9fcddf 243 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 67:4bcbbb9fcddf 244 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 67:4bcbbb9fcddf 245 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 67:4bcbbb9fcddf 246 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 67:4bcbbb9fcddf 247 } DAC_TypeDef;
mbed_official 67:4bcbbb9fcddf 248
mbed_official 67:4bcbbb9fcddf 249 /**
mbed_official 67:4bcbbb9fcddf 250 * @brief Debug MCU
mbed_official 67:4bcbbb9fcddf 251 */
mbed_official 67:4bcbbb9fcddf 252
mbed_official 67:4bcbbb9fcddf 253 typedef struct
mbed_official 67:4bcbbb9fcddf 254 {
mbed_official 67:4bcbbb9fcddf 255 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 256 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 257 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 258 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 259 }DBGMCU_TypeDef;
mbed_official 67:4bcbbb9fcddf 260
mbed_official 67:4bcbbb9fcddf 261 /**
mbed_official 67:4bcbbb9fcddf 262 * @brief DMA Controller
mbed_official 67:4bcbbb9fcddf 263 */
mbed_official 67:4bcbbb9fcddf 264
mbed_official 67:4bcbbb9fcddf 265 typedef struct
mbed_official 67:4bcbbb9fcddf 266 {
mbed_official 67:4bcbbb9fcddf 267 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 67:4bcbbb9fcddf 268 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 67:4bcbbb9fcddf 269 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 67:4bcbbb9fcddf 270 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 67:4bcbbb9fcddf 271 } DMA_Channel_TypeDef;
mbed_official 67:4bcbbb9fcddf 272
mbed_official 67:4bcbbb9fcddf 273 typedef struct
mbed_official 67:4bcbbb9fcddf 274 {
mbed_official 67:4bcbbb9fcddf 275 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 276 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 277 } DMA_TypeDef;
mbed_official 67:4bcbbb9fcddf 278
mbed_official 67:4bcbbb9fcddf 279 /**
mbed_official 67:4bcbbb9fcddf 280 * @brief External Interrupt/Event Controller
mbed_official 67:4bcbbb9fcddf 281 */
mbed_official 67:4bcbbb9fcddf 282
mbed_official 67:4bcbbb9fcddf 283 typedef struct
mbed_official 67:4bcbbb9fcddf 284 {
mbed_official 67:4bcbbb9fcddf 285 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 286 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 287 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 288 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 289 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 290 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 291 } EXTI_TypeDef;
mbed_official 67:4bcbbb9fcddf 292
mbed_official 67:4bcbbb9fcddf 293 /**
mbed_official 67:4bcbbb9fcddf 294 * @brief FLASH Registers
mbed_official 67:4bcbbb9fcddf 295 */
mbed_official 67:4bcbbb9fcddf 296 typedef struct
mbed_official 67:4bcbbb9fcddf 297 {
mbed_official 67:4bcbbb9fcddf 298 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 299 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 300 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 301 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
mbed_official 67:4bcbbb9fcddf 302 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 303 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 304 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
mbed_official 67:4bcbbb9fcddf 305 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
mbed_official 67:4bcbbb9fcddf 306 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */
mbed_official 67:4bcbbb9fcddf 307 uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */
mbed_official 67:4bcbbb9fcddf 308 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
mbed_official 67:4bcbbb9fcddf 309 } FLASH_TypeDef;
mbed_official 67:4bcbbb9fcddf 310
mbed_official 67:4bcbbb9fcddf 311 /**
mbed_official 67:4bcbbb9fcddf 312 * @brief Option Bytes Registers
mbed_official 67:4bcbbb9fcddf 313 */
mbed_official 67:4bcbbb9fcddf 314 typedef struct
mbed_official 67:4bcbbb9fcddf 315 {
mbed_official 67:4bcbbb9fcddf 316 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 317 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 318 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 319 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 320 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 321 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 322 } OB_TypeDef;
mbed_official 67:4bcbbb9fcddf 323
mbed_official 67:4bcbbb9fcddf 324 /**
mbed_official 67:4bcbbb9fcddf 325 * @brief Operational Amplifier (OPAMP)
mbed_official 67:4bcbbb9fcddf 326 */
mbed_official 67:4bcbbb9fcddf 327 typedef struct
mbed_official 67:4bcbbb9fcddf 328 {
mbed_official 67:4bcbbb9fcddf 329 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 330 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 331 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 332 } OPAMP_TypeDef;
mbed_official 67:4bcbbb9fcddf 333
mbed_official 67:4bcbbb9fcddf 334 /**
mbed_official 67:4bcbbb9fcddf 335 * @brief General Purpose IO
mbed_official 67:4bcbbb9fcddf 336 */
mbed_official 67:4bcbbb9fcddf 337
mbed_official 67:4bcbbb9fcddf 338 typedef struct
mbed_official 67:4bcbbb9fcddf 339 {
mbed_official 67:4bcbbb9fcddf 340 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 341 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 342 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 343 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 344 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 345 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 346 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
mbed_official 67:4bcbbb9fcddf 347 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 67:4bcbbb9fcddf 348 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
mbed_official 67:4bcbbb9fcddf 349 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 67:4bcbbb9fcddf 350 } GPIO_TypeDef;
mbed_official 67:4bcbbb9fcddf 351
mbed_official 67:4bcbbb9fcddf 352 /**
mbed_official 67:4bcbbb9fcddf 353 * @brief SysTem Configuration
mbed_official 67:4bcbbb9fcddf 354 */
mbed_official 67:4bcbbb9fcddf 355
mbed_official 67:4bcbbb9fcddf 356 typedef struct
mbed_official 67:4bcbbb9fcddf 357 {
mbed_official 67:4bcbbb9fcddf 358 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 359 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 360 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
mbed_official 67:4bcbbb9fcddf 361 } SYSCFG_TypeDef;
mbed_official 67:4bcbbb9fcddf 362
mbed_official 67:4bcbbb9fcddf 363 /**
mbed_official 67:4bcbbb9fcddf 364 * @brief Inter-integrated Circuit Interface
mbed_official 67:4bcbbb9fcddf 365 */
mbed_official 67:4bcbbb9fcddf 366
mbed_official 67:4bcbbb9fcddf 367 typedef struct
mbed_official 67:4bcbbb9fcddf 368 {
mbed_official 67:4bcbbb9fcddf 369 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 370 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 371 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 372 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 373 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 374 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 375 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
mbed_official 67:4bcbbb9fcddf 376 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
mbed_official 67:4bcbbb9fcddf 377 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
mbed_official 67:4bcbbb9fcddf 378 } I2C_TypeDef;
mbed_official 67:4bcbbb9fcddf 379
mbed_official 67:4bcbbb9fcddf 380 /**
mbed_official 67:4bcbbb9fcddf 381 * @brief Independent WATCHDOG
mbed_official 67:4bcbbb9fcddf 382 */
mbed_official 67:4bcbbb9fcddf 383
mbed_official 67:4bcbbb9fcddf 384 typedef struct
mbed_official 67:4bcbbb9fcddf 385 {
mbed_official 67:4bcbbb9fcddf 386 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 387 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 388 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 389 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 390 } IWDG_TypeDef;
mbed_official 67:4bcbbb9fcddf 391
mbed_official 67:4bcbbb9fcddf 392 /**
mbed_official 67:4bcbbb9fcddf 393 * @brief Power Control
mbed_official 67:4bcbbb9fcddf 394 */
mbed_official 67:4bcbbb9fcddf 395
mbed_official 67:4bcbbb9fcddf 396 typedef struct
mbed_official 67:4bcbbb9fcddf 397 {
mbed_official 67:4bcbbb9fcddf 398 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 399 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 400 } PWR_TypeDef;
mbed_official 67:4bcbbb9fcddf 401
mbed_official 67:4bcbbb9fcddf 402 /**
mbed_official 67:4bcbbb9fcddf 403 * @brief Reset and Clock Control
mbed_official 67:4bcbbb9fcddf 404 */
mbed_official 67:4bcbbb9fcddf 405
mbed_official 67:4bcbbb9fcddf 406 typedef struct
mbed_official 67:4bcbbb9fcddf 407 {
mbed_official 67:4bcbbb9fcddf 408 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 409 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 410 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 411 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 412 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 413 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 414 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
mbed_official 67:4bcbbb9fcddf 415 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
mbed_official 67:4bcbbb9fcddf 416 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
mbed_official 67:4bcbbb9fcddf 417 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
mbed_official 67:4bcbbb9fcddf 418 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
mbed_official 67:4bcbbb9fcddf 419 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
mbed_official 67:4bcbbb9fcddf 420 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
mbed_official 67:4bcbbb9fcddf 421 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
mbed_official 67:4bcbbb9fcddf 422 } RCC_TypeDef;
mbed_official 67:4bcbbb9fcddf 423
mbed_official 67:4bcbbb9fcddf 424 /**
mbed_official 67:4bcbbb9fcddf 425 * @brief Routing Interface
mbed_official 67:4bcbbb9fcddf 426 */
mbed_official 67:4bcbbb9fcddf 427
mbed_official 67:4bcbbb9fcddf 428 typedef struct
mbed_official 67:4bcbbb9fcddf 429 {
mbed_official 67:4bcbbb9fcddf 430 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 431 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 432 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 433 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 434 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 435 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 436 uint32_t RESERVED1; /*!< Reserved, 0x18 */
mbed_official 67:4bcbbb9fcddf 437 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
mbed_official 67:4bcbbb9fcddf 438 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
mbed_official 67:4bcbbb9fcddf 439 __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
mbed_official 67:4bcbbb9fcddf 440 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
mbed_official 67:4bcbbb9fcddf 441 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
mbed_official 67:4bcbbb9fcddf 442 __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
mbed_official 67:4bcbbb9fcddf 443 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
mbed_official 67:4bcbbb9fcddf 444 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
mbed_official 67:4bcbbb9fcddf 445 __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
mbed_official 67:4bcbbb9fcddf 446 } RI_TypeDef;
mbed_official 67:4bcbbb9fcddf 447
mbed_official 67:4bcbbb9fcddf 448 /**
mbed_official 67:4bcbbb9fcddf 449 * @brief Real-Time Clock
mbed_official 67:4bcbbb9fcddf 450 */
mbed_official 67:4bcbbb9fcddf 451 typedef struct
mbed_official 67:4bcbbb9fcddf 452 {
mbed_official 67:4bcbbb9fcddf 453 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 454 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 455 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 456 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 457 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 458 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 459 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
mbed_official 67:4bcbbb9fcddf 460 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 67:4bcbbb9fcddf 461 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 67:4bcbbb9fcddf 462 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 67:4bcbbb9fcddf 463 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 67:4bcbbb9fcddf 464 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 67:4bcbbb9fcddf 465 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 67:4bcbbb9fcddf 466 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 67:4bcbbb9fcddf 467 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 67:4bcbbb9fcddf 468 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
mbed_official 67:4bcbbb9fcddf 469 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 67:4bcbbb9fcddf 470 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 67:4bcbbb9fcddf 471 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 67:4bcbbb9fcddf 472 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 67:4bcbbb9fcddf 473 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 67:4bcbbb9fcddf 474 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 67:4bcbbb9fcddf 475 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 67:4bcbbb9fcddf 476 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 67:4bcbbb9fcddf 477 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 67:4bcbbb9fcddf 478 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 67:4bcbbb9fcddf 479 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 67:4bcbbb9fcddf 480 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 67:4bcbbb9fcddf 481 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 67:4bcbbb9fcddf 482 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 67:4bcbbb9fcddf 483 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 67:4bcbbb9fcddf 484 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 67:4bcbbb9fcddf 485 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 67:4bcbbb9fcddf 486 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 67:4bcbbb9fcddf 487 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 67:4bcbbb9fcddf 488 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 67:4bcbbb9fcddf 489 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
mbed_official 67:4bcbbb9fcddf 490 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
mbed_official 67:4bcbbb9fcddf 491 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
mbed_official 67:4bcbbb9fcddf 492 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
mbed_official 67:4bcbbb9fcddf 493 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
mbed_official 67:4bcbbb9fcddf 494 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
mbed_official 67:4bcbbb9fcddf 495 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
mbed_official 67:4bcbbb9fcddf 496 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
mbed_official 67:4bcbbb9fcddf 497 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
mbed_official 67:4bcbbb9fcddf 498 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
mbed_official 67:4bcbbb9fcddf 499 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
mbed_official 67:4bcbbb9fcddf 500 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
mbed_official 67:4bcbbb9fcddf 501 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
mbed_official 67:4bcbbb9fcddf 502 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
mbed_official 67:4bcbbb9fcddf 503 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
mbed_official 67:4bcbbb9fcddf 504 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
mbed_official 67:4bcbbb9fcddf 505 } RTC_TypeDef;
mbed_official 67:4bcbbb9fcddf 506
mbed_official 67:4bcbbb9fcddf 507 /**
mbed_official 67:4bcbbb9fcddf 508 * @brief Serial Peripheral Interface
mbed_official 67:4bcbbb9fcddf 509 */
mbed_official 67:4bcbbb9fcddf 510
mbed_official 67:4bcbbb9fcddf 511 typedef struct
mbed_official 67:4bcbbb9fcddf 512 {
mbed_official 67:4bcbbb9fcddf 513 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 514 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 515 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 516 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 517 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 518 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 519 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 67:4bcbbb9fcddf 520 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 67:4bcbbb9fcddf 521 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 67:4bcbbb9fcddf 522 } SPI_TypeDef;
mbed_official 67:4bcbbb9fcddf 523
mbed_official 67:4bcbbb9fcddf 524 /**
mbed_official 67:4bcbbb9fcddf 525 * @brief TIM
mbed_official 67:4bcbbb9fcddf 526 */
mbed_official 67:4bcbbb9fcddf 527 typedef struct
mbed_official 67:4bcbbb9fcddf 528 {
mbed_official 67:4bcbbb9fcddf 529 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 530 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 531 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 532 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 533 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 534 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 535 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 67:4bcbbb9fcddf 536 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 67:4bcbbb9fcddf 537 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 67:4bcbbb9fcddf 538 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 67:4bcbbb9fcddf 539 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
mbed_official 67:4bcbbb9fcddf 540 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 67:4bcbbb9fcddf 541 uint32_t RESERVED12; /*!< Reserved, 0x30 */
mbed_official 67:4bcbbb9fcddf 542 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 67:4bcbbb9fcddf 543 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 67:4bcbbb9fcddf 544 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 67:4bcbbb9fcddf 545 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 67:4bcbbb9fcddf 546 uint32_t RESERVED17; /*!< Reserved, 0x44 */
mbed_official 67:4bcbbb9fcddf 547 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 67:4bcbbb9fcddf 548 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 67:4bcbbb9fcddf 549 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 67:4bcbbb9fcddf 550 } TIM_TypeDef;
mbed_official 67:4bcbbb9fcddf 551 /**
mbed_official 67:4bcbbb9fcddf 552 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 67:4bcbbb9fcddf 553 */
mbed_official 67:4bcbbb9fcddf 554
mbed_official 67:4bcbbb9fcddf 555 typedef struct
mbed_official 67:4bcbbb9fcddf 556 {
mbed_official 67:4bcbbb9fcddf 557 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 558 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 559 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 560 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 561 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 562 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 563 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
mbed_official 67:4bcbbb9fcddf 564 } USART_TypeDef;
mbed_official 67:4bcbbb9fcddf 565
mbed_official 67:4bcbbb9fcddf 566 /**
mbed_official 67:4bcbbb9fcddf 567 * @brief Universal Serial Bus Full Speed Device
mbed_official 67:4bcbbb9fcddf 568 */
mbed_official 67:4bcbbb9fcddf 569
mbed_official 67:4bcbbb9fcddf 570 typedef struct
mbed_official 67:4bcbbb9fcddf 571 {
mbed_official 67:4bcbbb9fcddf 572 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 573 __IO uint16_t RESERVED0; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 574 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 575 __IO uint16_t RESERVED1; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 576 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 577 __IO uint16_t RESERVED2; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 578 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
mbed_official 67:4bcbbb9fcddf 579 __IO uint16_t RESERVED3; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 580 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
mbed_official 67:4bcbbb9fcddf 581 __IO uint16_t RESERVED4; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 582 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
mbed_official 67:4bcbbb9fcddf 583 __IO uint16_t RESERVED5; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 584 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
mbed_official 67:4bcbbb9fcddf 585 __IO uint16_t RESERVED6; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 586 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
mbed_official 67:4bcbbb9fcddf 587 __IO uint16_t RESERVED7[17]; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 588 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
mbed_official 67:4bcbbb9fcddf 589 __IO uint16_t RESERVED8; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 590 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
mbed_official 67:4bcbbb9fcddf 591 __IO uint16_t RESERVED9; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 592 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
mbed_official 67:4bcbbb9fcddf 593 __IO uint16_t RESERVEDA; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 594 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
mbed_official 67:4bcbbb9fcddf 595 __IO uint16_t RESERVEDB; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 596 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
mbed_official 67:4bcbbb9fcddf 597 __IO uint16_t RESERVEDC; /*!< Reserved */
mbed_official 67:4bcbbb9fcddf 598 } USB_TypeDef;
mbed_official 67:4bcbbb9fcddf 599
mbed_official 67:4bcbbb9fcddf 600 /**
mbed_official 67:4bcbbb9fcddf 601 * @brief Window WATCHDOG
mbed_official 67:4bcbbb9fcddf 602 */
mbed_official 67:4bcbbb9fcddf 603 typedef struct
mbed_official 67:4bcbbb9fcddf 604 {
mbed_official 67:4bcbbb9fcddf 605 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 67:4bcbbb9fcddf 606 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 67:4bcbbb9fcddf 607 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 67:4bcbbb9fcddf 608 } WWDG_TypeDef;
mbed_official 67:4bcbbb9fcddf 609
mbed_official 67:4bcbbb9fcddf 610 /**
mbed_official 67:4bcbbb9fcddf 611 * @brief Universal Serial Bus Full Speed Device
mbed_official 67:4bcbbb9fcddf 612 */
mbed_official 67:4bcbbb9fcddf 613 /**
mbed_official 67:4bcbbb9fcddf 614 * @}
mbed_official 67:4bcbbb9fcddf 615 */
mbed_official 67:4bcbbb9fcddf 616
mbed_official 67:4bcbbb9fcddf 617 /** @addtogroup Peripheral_memory_map
mbed_official 67:4bcbbb9fcddf 618 * @{
mbed_official 67:4bcbbb9fcddf 619 */
mbed_official 67:4bcbbb9fcddf 620
<> 144:ef7eb2e8f9f7 621 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
<> 144:ef7eb2e8f9f7 622 #define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /*!< FLASH EEPROM base address in the alias region */
<> 144:ef7eb2e8f9f7 623 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
<> 144:ef7eb2e8f9f7 624 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
<> 144:ef7eb2e8f9f7 625 #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */
<> 144:ef7eb2e8f9f7 626 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
<> 144:ef7eb2e8f9f7 627 #define FLASH_END ((uint32_t)0x0803FFFFU) /*!< Program end FLASH address for Cat3 */
<> 144:ef7eb2e8f9f7 628 #define FLASH_EEPROM_END ((uint32_t)0x08081FFFU) /*!< FLASH EEPROM end address (8KB) */
mbed_official 67:4bcbbb9fcddf 629
mbed_official 67:4bcbbb9fcddf 630 /*!< Peripheral memory map */
mbed_official 67:4bcbbb9fcddf 631 #define APB1PERIPH_BASE PERIPH_BASE
<> 144:ef7eb2e8f9f7 632 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 144:ef7eb2e8f9f7 633 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
mbed_official 67:4bcbbb9fcddf 634
mbed_official 67:4bcbbb9fcddf 635 /*!< APB1 peripherals */
<> 144:ef7eb2e8f9f7 636 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
<> 144:ef7eb2e8f9f7 637 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
<> 144:ef7eb2e8f9f7 638 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
<> 144:ef7eb2e8f9f7 639 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
<> 144:ef7eb2e8f9f7 640 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
<> 144:ef7eb2e8f9f7 641 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
<> 144:ef7eb2e8f9f7 642 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
<> 144:ef7eb2e8f9f7 643 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
<> 144:ef7eb2e8f9f7 644 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
<> 144:ef7eb2e8f9f7 645 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
<> 144:ef7eb2e8f9f7 646 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
<> 144:ef7eb2e8f9f7 647 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
<> 144:ef7eb2e8f9f7 648 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
<> 144:ef7eb2e8f9f7 649 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
<> 144:ef7eb2e8f9f7 650 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U)
mbed_official 67:4bcbbb9fcddf 651
mbed_official 67:4bcbbb9fcddf 652 /* USB device FS */
<> 144:ef7eb2e8f9f7 653 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
<> 144:ef7eb2e8f9f7 654 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
mbed_official 67:4bcbbb9fcddf 655
mbed_official 67:4bcbbb9fcddf 656 /* USB device FS SRAM */
<> 144:ef7eb2e8f9f7 657 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
<> 144:ef7eb2e8f9f7 658 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
<> 144:ef7eb2e8f9f7 659 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U)
<> 144:ef7eb2e8f9f7 660 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04U)
<> 144:ef7eb2e8f9f7 661 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU)
mbed_official 67:4bcbbb9fcddf 662
mbed_official 67:4bcbbb9fcddf 663 /*!< APB2 peripherals */
<> 144:ef7eb2e8f9f7 664 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U)
<> 144:ef7eb2e8f9f7 665 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
<> 144:ef7eb2e8f9f7 666 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U)
<> 144:ef7eb2e8f9f7 667 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U)
<> 144:ef7eb2e8f9f7 668 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U)
<> 144:ef7eb2e8f9f7 669 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
<> 144:ef7eb2e8f9f7 670 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700U)
<> 144:ef7eb2e8f9f7 671 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
<> 144:ef7eb2e8f9f7 672 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
mbed_official 67:4bcbbb9fcddf 673
mbed_official 67:4bcbbb9fcddf 674 /*!< AHB peripherals */
<> 144:ef7eb2e8f9f7 675 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U)
<> 144:ef7eb2e8f9f7 676 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U)
<> 144:ef7eb2e8f9f7 677 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U)
<> 144:ef7eb2e8f9f7 678 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U)
<> 144:ef7eb2e8f9f7 679 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U)
<> 144:ef7eb2e8f9f7 680 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U)
<> 144:ef7eb2e8f9f7 681 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
<> 144:ef7eb2e8f9f7 682 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800U)
<> 144:ef7eb2e8f9f7 683 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */
<> 144:ef7eb2e8f9f7 684 #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
<> 144:ef7eb2e8f9f7 685 #define FLASHSIZE_BASE ((uint32_t)0x1FF800CCU) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
<> 144:ef7eb2e8f9f7 686 #define UID_BASE ((uint32_t)0x1FF800D0U) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
<> 144:ef7eb2e8f9f7 687 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U)
<> 144:ef7eb2e8f9f7 688 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
<> 144:ef7eb2e8f9f7 689 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
<> 144:ef7eb2e8f9f7 690 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
<> 144:ef7eb2e8f9f7 691 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
<> 144:ef7eb2e8f9f7 692 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
<> 144:ef7eb2e8f9f7 693 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
<> 144:ef7eb2e8f9f7 694 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
<> 144:ef7eb2e8f9f7 695 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U)
<> 144:ef7eb2e8f9f7 696 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008U)
<> 144:ef7eb2e8f9f7 697 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CU)
<> 144:ef7eb2e8f9f7 698 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030U)
<> 144:ef7eb2e8f9f7 699 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044U)
<> 144:ef7eb2e8f9f7 700 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058U)
<> 144:ef7eb2e8f9f7 701 #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */
mbed_official 67:4bcbbb9fcddf 702
mbed_official 67:4bcbbb9fcddf 703 /**
mbed_official 67:4bcbbb9fcddf 704 * @}
mbed_official 67:4bcbbb9fcddf 705 */
mbed_official 67:4bcbbb9fcddf 706
mbed_official 67:4bcbbb9fcddf 707 /** @addtogroup Peripheral_declaration
mbed_official 67:4bcbbb9fcddf 708 * @{
mbed_official 67:4bcbbb9fcddf 709 */
mbed_official 67:4bcbbb9fcddf 710
mbed_official 67:4bcbbb9fcddf 711 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 67:4bcbbb9fcddf 712 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 67:4bcbbb9fcddf 713 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 67:4bcbbb9fcddf 714 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official 67:4bcbbb9fcddf 715 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 67:4bcbbb9fcddf 716 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 67:4bcbbb9fcddf 717 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 67:4bcbbb9fcddf 718 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 67:4bcbbb9fcddf 719 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 67:4bcbbb9fcddf 720 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 67:4bcbbb9fcddf 721 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 67:4bcbbb9fcddf 722 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 67:4bcbbb9fcddf 723 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 67:4bcbbb9fcddf 724 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 67:4bcbbb9fcddf 725 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 67:4bcbbb9fcddf 726 /* USB device FS */
mbed_official 67:4bcbbb9fcddf 727 #define USB ((USB_TypeDef *) USB_BASE)
mbed_official 67:4bcbbb9fcddf 728 /* USB device FS SRAM */
mbed_official 67:4bcbbb9fcddf 729 #define PWR ((PWR_TypeDef *) PWR_BASE)
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
<> 144:ef7eb2e8f9f7 732 /* Legacy defines */
<> 144:ef7eb2e8f9f7 733 #define DAC DAC1
<> 144:ef7eb2e8f9f7 734
mbed_official 67:4bcbbb9fcddf 735 #define COMP ((COMP_TypeDef *) COMP_BASE)
mbed_official 67:4bcbbb9fcddf 736 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
<> 144:ef7eb2e8f9f7 737 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U))
mbed_official 67:4bcbbb9fcddf 738 #define RI ((RI_TypeDef *) RI_BASE)
mbed_official 67:4bcbbb9fcddf 739 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
mbed_official 67:4bcbbb9fcddf 740 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
<> 144:ef7eb2e8f9f7 741 #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
mbed_official 67:4bcbbb9fcddf 742 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 67:4bcbbb9fcddf 743 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 67:4bcbbb9fcddf 744 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official 67:4bcbbb9fcddf 745 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
mbed_official 67:4bcbbb9fcddf 746 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
<> 144:ef7eb2e8f9f7 747
mbed_official 67:4bcbbb9fcddf 748 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<> 144:ef7eb2e8f9f7 749 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
<> 144:ef7eb2e8f9f7 750 /* Legacy defines */
<> 144:ef7eb2e8f9f7 751 #define ADC ADC1_COMMON
<> 144:ef7eb2e8f9f7 752
mbed_official 67:4bcbbb9fcddf 753 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 67:4bcbbb9fcddf 754 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 67:4bcbbb9fcddf 755 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 67:4bcbbb9fcddf 756 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 67:4bcbbb9fcddf 757 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 67:4bcbbb9fcddf 758 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 67:4bcbbb9fcddf 759 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 67:4bcbbb9fcddf 760 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 67:4bcbbb9fcddf 761 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 67:4bcbbb9fcddf 762 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 67:4bcbbb9fcddf 763 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 67:4bcbbb9fcddf 764 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 67:4bcbbb9fcddf 765 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 67:4bcbbb9fcddf 766 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 67:4bcbbb9fcddf 767 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 67:4bcbbb9fcddf 768 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 67:4bcbbb9fcddf 769 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 67:4bcbbb9fcddf 770 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 67:4bcbbb9fcddf 771 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 67:4bcbbb9fcddf 772 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 67:4bcbbb9fcddf 773 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 67:4bcbbb9fcddf 774 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
mbed_official 67:4bcbbb9fcddf 775 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
mbed_official 67:4bcbbb9fcddf 776 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
mbed_official 67:4bcbbb9fcddf 777 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
mbed_official 67:4bcbbb9fcddf 778 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
mbed_official 67:4bcbbb9fcddf 779 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 67:4bcbbb9fcddf 780
mbed_official 67:4bcbbb9fcddf 781 /**
mbed_official 67:4bcbbb9fcddf 782 * @}
mbed_official 67:4bcbbb9fcddf 783 */
mbed_official 67:4bcbbb9fcddf 784
mbed_official 67:4bcbbb9fcddf 785 /** @addtogroup Exported_constants
mbed_official 67:4bcbbb9fcddf 786 * @{
mbed_official 67:4bcbbb9fcddf 787 */
mbed_official 67:4bcbbb9fcddf 788
mbed_official 67:4bcbbb9fcddf 789 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 67:4bcbbb9fcddf 790 * @{
mbed_official 67:4bcbbb9fcddf 791 */
mbed_official 67:4bcbbb9fcddf 792
mbed_official 67:4bcbbb9fcddf 793 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 794 /* Peripheral Registers Bits Definition */
mbed_official 67:4bcbbb9fcddf 795 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 796 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 797 /* */
mbed_official 67:4bcbbb9fcddf 798 /* Analog to Digital Converter (ADC) */
mbed_official 67:4bcbbb9fcddf 799 /* */
mbed_official 67:4bcbbb9fcddf 800 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 801
mbed_official 67:4bcbbb9fcddf 802 /******************** Bit definition for ADC_SR register ********************/
<> 144:ef7eb2e8f9f7 803 #define ADC_SR_AWD ((uint32_t)0x00000001U) /*!< ADC analog watchdog 1 flag */
<> 144:ef7eb2e8f9f7 804 #define ADC_SR_EOCS ((uint32_t)0x00000002U) /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
<> 144:ef7eb2e8f9f7 805 #define ADC_SR_JEOS ((uint32_t)0x00000004U) /*!< ADC group injected end of sequence conversions flag */
<> 144:ef7eb2e8f9f7 806 #define ADC_SR_JSTRT ((uint32_t)0x00000008U) /*!< ADC group injected conversion start flag */
<> 144:ef7eb2e8f9f7 807 #define ADC_SR_STRT ((uint32_t)0x00000010U) /*!< ADC group regular conversion start flag */
<> 144:ef7eb2e8f9f7 808 #define ADC_SR_OVR ((uint32_t)0x00000020U) /*!< ADC group regular overrun flag */
<> 144:ef7eb2e8f9f7 809 #define ADC_SR_ADONS ((uint32_t)0x00000040U) /*!< ADC ready flag */
<> 144:ef7eb2e8f9f7 810 #define ADC_SR_RCNR ((uint32_t)0x00000100U) /*!< ADC group regular not ready flag */
<> 144:ef7eb2e8f9f7 811 #define ADC_SR_JCNR ((uint32_t)0x00000200U) /*!< ADC group injected not ready flag */
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /* Legacy defines */
<> 144:ef7eb2e8f9f7 814 #define ADC_SR_EOC (ADC_SR_EOCS)
<> 144:ef7eb2e8f9f7 815 #define ADC_SR_JEOC (ADC_SR_JEOS)
mbed_official 67:4bcbbb9fcddf 816
mbed_official 67:4bcbbb9fcddf 817 /******************* Bit definition for ADC_CR1 register ********************/
<> 144:ef7eb2e8f9f7 818 #define ADC_CR1_AWDCH ((uint32_t)0x0000001FU) /*!< ADC analog watchdog 1 monitored channel selection */
<> 144:ef7eb2e8f9f7 819 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 820 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 821 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 822 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 823 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 #define ADC_CR1_EOCSIE ((uint32_t)0x00000020U) /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
<> 144:ef7eb2e8f9f7 826 #define ADC_CR1_AWDIE ((uint32_t)0x00000040U) /*!< ADC analog watchdog 1 interrupt */
<> 144:ef7eb2e8f9f7 827 #define ADC_CR1_JEOSIE ((uint32_t)0x00000080U) /*!< ADC group injected end of sequence conversions interrupt */
<> 144:ef7eb2e8f9f7 828 #define ADC_CR1_SCAN ((uint32_t)0x00000100U) /*!< ADC scan mode */
<> 144:ef7eb2e8f9f7 829 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
<> 144:ef7eb2e8f9f7 830 #define ADC_CR1_JAUTO ((uint32_t)0x00000400U) /*!< ADC group injected automatic trigger mode */
<> 144:ef7eb2e8f9f7 831 #define ADC_CR1_DISCEN ((uint32_t)0x00000800U) /*!< ADC group regular sequencer discontinuous mode */
<> 144:ef7eb2e8f9f7 832 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000U) /*!< ADC group injected sequencer discontinuous mode */
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000U) /*!< ADC group regular sequencer discontinuous number of ranks */
<> 144:ef7eb2e8f9f7 835 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 836 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 837 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 #define ADC_CR1_PDD ((uint32_t)0x00010000U) /*!< ADC power down during auto delay phase */
<> 144:ef7eb2e8f9f7 840 #define ADC_CR1_PDI ((uint32_t)0x00020000U) /*!< ADC power down during idle phase */
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 enable on scope ADC group injected */
<> 144:ef7eb2e8f9f7 843 #define ADC_CR1_AWDEN ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 #define ADC_CR1_RES ((uint32_t)0x03000000U) /*!< ADC resolution */
<> 144:ef7eb2e8f9f7 846 #define ADC_CR1_RES_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 847 #define ADC_CR1_RES_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 #define ADC_CR1_OVRIE ((uint32_t)0x04000000U) /*!< ADC group regular overrun interrupt */
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /* Legacy defines */
<> 144:ef7eb2e8f9f7 852 #define ADC_CR1_EOCIE (ADC_CR1_EOCSIE)
<> 144:ef7eb2e8f9f7 853 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
<> 144:ef7eb2e8f9f7 854
mbed_official 67:4bcbbb9fcddf 855 /******************* Bit definition for ADC_CR2 register ********************/
<> 144:ef7eb2e8f9f7 856 #define ADC_CR2_ADON ((uint32_t)0x00000001U) /*!< ADC enable */
<> 144:ef7eb2e8f9f7 857 #define ADC_CR2_CONT ((uint32_t)0x00000002U) /*!< ADC group regular continuous conversion mode */
<> 144:ef7eb2e8f9f7 858 #define ADC_CR2_CFG ((uint32_t)0x00000004U) /*!< ADC channels bank selection */
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 #define ADC_CR2_DELS ((uint32_t)0x00000070U) /*!< ADC auto delay selection */
<> 144:ef7eb2e8f9f7 861 #define ADC_CR2_DELS_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 862 #define ADC_CR2_DELS_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 863 #define ADC_CR2_DELS_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 #define ADC_CR2_DMA ((uint32_t)0x00000100U) /*!< ADC DMA transfer enable */
<> 144:ef7eb2e8f9f7 866 #define ADC_CR2_DDS ((uint32_t)0x00000200U) /*!< ADC DMA transfer configuration */
<> 144:ef7eb2e8f9f7 867 #define ADC_CR2_EOCS ((uint32_t)0x00000400U) /*!< ADC end of unitary or end of sequence conversions selection */
<> 144:ef7eb2e8f9f7 868 #define ADC_CR2_ALIGN ((uint32_t)0x00000800U) /*!< ADC data alignement */
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000U) /*!< ADC group injected external trigger source */
<> 144:ef7eb2e8f9f7 871 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 872 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 873 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 874 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000U) /*!< ADC group injected external trigger polarity */
<> 144:ef7eb2e8f9f7 877 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 878 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000U) /*!< ADC group injected conversion start */
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000U) /*!< ADC group regular external trigger source */
<> 144:ef7eb2e8f9f7 883 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 884 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 885 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 886 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 #define ADC_CR2_EXTEN ((uint32_t)0x30000000U) /*!< ADC group regular external trigger polarity */
<> 144:ef7eb2e8f9f7 889 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 890 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 #define ADC_CR2_SWSTART ((uint32_t)0x40000000U) /*!< ADC group regular conversion start */
mbed_official 67:4bcbbb9fcddf 893
mbed_official 67:4bcbbb9fcddf 894 /****************** Bit definition for ADC_SMPR1 register *******************/
<> 144:ef7eb2e8f9f7 895 #define ADC_SMPR1_SMP20 ((uint32_t)0x00000007U) /*!< ADC channel 20 sampling time selection */
<> 144:ef7eb2e8f9f7 896 #define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 897 #define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 898 #define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 #define ADC_SMPR1_SMP21 ((uint32_t)0x00000038U) /*!< ADC channel 21 sampling time selection */
<> 144:ef7eb2e8f9f7 901 #define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 902 #define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 903 #define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 #define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0U) /*!< ADC channel 22 sampling time selection */
<> 144:ef7eb2e8f9f7 906 #define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 907 #define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 908 #define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 #define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00U) /*!< ADC channel 23 sampling time selection */
<> 144:ef7eb2e8f9f7 911 #define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 912 #define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 913 #define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 #define ADC_SMPR1_SMP24 ((uint32_t)0x00007000U) /*!< ADC channel 24 sampling time selection */
<> 144:ef7eb2e8f9f7 916 #define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 917 #define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 918 #define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 #define ADC_SMPR1_SMP25 ((uint32_t)0x00038000U) /*!< ADC channel 25 sampling time selection */
<> 144:ef7eb2e8f9f7 921 #define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 922 #define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 923 #define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 #define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000U) /*!< ADC channel 26 sampling time selection */
<> 144:ef7eb2e8f9f7 926 #define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 927 #define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 928 #define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
mbed_official 67:4bcbbb9fcddf 929
mbed_official 67:4bcbbb9fcddf 930 /****************** Bit definition for ADC_SMPR2 register *******************/
<> 144:ef7eb2e8f9f7 931 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007U) /*!< ADC channel 10 sampling time selection */
<> 144:ef7eb2e8f9f7 932 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 933 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 934 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038U) /*!< ADC channel 11 sampling time selection */
<> 144:ef7eb2e8f9f7 937 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 938 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 939 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0U) /*!< ADC channel 12 sampling time selection */
<> 144:ef7eb2e8f9f7 942 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 943 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 944 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00U) /*!< ADC channel 13 sampling time selection */
<> 144:ef7eb2e8f9f7 947 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 948 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 949 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000U) /*!< ADC channel 14 sampling time selection */
<> 144:ef7eb2e8f9f7 952 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 953 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 954 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */
<> 144:ef7eb2e8f9f7 957 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 958 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 959 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000U) /*!< ADC channel 16 sampling time selection */
<> 144:ef7eb2e8f9f7 962 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 963 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 964 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000U) /*!< ADC channel 17 sampling time selection */
<> 144:ef7eb2e8f9f7 967 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 968 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 969 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000U) /*!< ADC channel 18 sampling time selection */
<> 144:ef7eb2e8f9f7 972 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 973 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 974 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 #define ADC_SMPR2_SMP19 ((uint32_t)0x38000000U) /*!< ADC channel 19 sampling time selection */
<> 144:ef7eb2e8f9f7 977 #define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 978 #define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 979 #define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000U) /*!< Bit 2 */
mbed_official 67:4bcbbb9fcddf 980
mbed_official 67:4bcbbb9fcddf 981 /****************** Bit definition for ADC_SMPR3 register *******************/
<> 144:ef7eb2e8f9f7 982 #define ADC_SMPR3_SMP0 ((uint32_t)0x00000007U) /*!< ADC channel 0 sampling time selection */
<> 144:ef7eb2e8f9f7 983 #define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 984 #define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 985 #define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
mbed_official 67:4bcbbb9fcddf 986
<> 144:ef7eb2e8f9f7 987 #define ADC_SMPR3_SMP1 ((uint32_t)0x00000038U) /*!< ADC channel 1 sampling time selection */
<> 144:ef7eb2e8f9f7 988 #define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 989 #define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 990 #define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 #define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0U) /*!< ADC channel 2 sampling time selection */
<> 144:ef7eb2e8f9f7 993 #define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 994 #define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 995 #define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 #define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00U) /*!< ADC channel 3 sampling time selection */
<> 144:ef7eb2e8f9f7 998 #define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 999 #define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1000 #define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 #define ADC_SMPR3_SMP4 ((uint32_t)0x00007000U) /*!< ADC channel 4 sampling time selection */
<> 144:ef7eb2e8f9f7 1003 #define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1004 #define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1005 #define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 #define ADC_SMPR3_SMP5 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */
<> 144:ef7eb2e8f9f7 1008 #define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1009 #define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1010 #define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 #define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000U) /*!< ADC channel 6 sampling time selection */
<> 144:ef7eb2e8f9f7 1013 #define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1014 #define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1015 #define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 #define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000U) /*!< ADC channel 7 sampling time selection */
<> 144:ef7eb2e8f9f7 1018 #define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1019 #define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1020 #define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 #define ADC_SMPR3_SMP8 ((uint32_t)0x07000000U) /*!< ADC channel 8 sampling time selection */
<> 144:ef7eb2e8f9f7 1023 #define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1024 #define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1025 #define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 #define ADC_SMPR3_SMP9 ((uint32_t)0x38000000U) /*!< ADC channel 9 sampling time selection */
<> 144:ef7eb2e8f9f7 1028 #define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1029 #define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1030 #define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000U) /*!< Bit 2 */
mbed_official 67:4bcbbb9fcddf 1031
mbed_official 67:4bcbbb9fcddf 1032 /****************** Bit definition for ADC_JOFR1 register *******************/
<> 144:ef7eb2e8f9f7 1033 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 1 offset value */
mbed_official 67:4bcbbb9fcddf 1034
mbed_official 67:4bcbbb9fcddf 1035 /****************** Bit definition for ADC_JOFR2 register *******************/
<> 144:ef7eb2e8f9f7 1036 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 2 offset value */
mbed_official 67:4bcbbb9fcddf 1037
mbed_official 67:4bcbbb9fcddf 1038 /****************** Bit definition for ADC_JOFR3 register *******************/
<> 144:ef7eb2e8f9f7 1039 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 3 offset value */
mbed_official 67:4bcbbb9fcddf 1040
mbed_official 67:4bcbbb9fcddf 1041 /****************** Bit definition for ADC_JOFR4 register *******************/
<> 144:ef7eb2e8f9f7 1042 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 4 offset value */
mbed_official 67:4bcbbb9fcddf 1043
mbed_official 67:4bcbbb9fcddf 1044 /******************* Bit definition for ADC_HTR register ********************/
<> 144:ef7eb2e8f9f7 1045 #define ADC_HTR_HT ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold high */
mbed_official 67:4bcbbb9fcddf 1046
mbed_official 67:4bcbbb9fcddf 1047 /******************* Bit definition for ADC_LTR register ********************/
<> 144:ef7eb2e8f9f7 1048 #define ADC_LTR_LT ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */
mbed_official 67:4bcbbb9fcddf 1049
mbed_official 67:4bcbbb9fcddf 1050 /******************* Bit definition for ADC_SQR1 register *******************/
<> 144:ef7eb2e8f9f7 1051 #define ADC_SQR1_L ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer scan length */
<> 144:ef7eb2e8f9f7 1052 #define ADC_SQR1_L_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1053 #define ADC_SQR1_L_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1054 #define ADC_SQR1_L_2 ((uint32_t)0x00400000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1055 #define ADC_SQR1_L_3 ((uint32_t)0x00800000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1056 #define ADC_SQR1_L_4 ((uint32_t)0x01000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 #define ADC_SQR1_SQ28 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 28 */
<> 144:ef7eb2e8f9f7 1059 #define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1060 #define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1061 #define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1062 #define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1063 #define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1064
<> 144:ef7eb2e8f9f7 1065 #define ADC_SQR1_SQ27 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 27 */
<> 144:ef7eb2e8f9f7 1066 #define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1067 #define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1068 #define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1069 #define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1070 #define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1071
<> 144:ef7eb2e8f9f7 1072 #define ADC_SQR1_SQ26 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 26 */
<> 144:ef7eb2e8f9f7 1073 #define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1074 #define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1075 #define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1076 #define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1077 #define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079 #define ADC_SQR1_SQ25 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 25 */
<> 144:ef7eb2e8f9f7 1080 #define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1081 #define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1082 #define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1083 #define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1084 #define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
mbed_official 67:4bcbbb9fcddf 1085
mbed_official 67:4bcbbb9fcddf 1086 /******************* Bit definition for ADC_SQR2 register *******************/
<> 144:ef7eb2e8f9f7 1087 #define ADC_SQR2_SQ19 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 19 */
<> 144:ef7eb2e8f9f7 1088 #define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1089 #define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1090 #define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1091 #define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1092 #define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 #define ADC_SQR2_SQ20 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 20 */
<> 144:ef7eb2e8f9f7 1095 #define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1096 #define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1097 #define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1098 #define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1099 #define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1100
<> 144:ef7eb2e8f9f7 1101 #define ADC_SQR2_SQ21 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 21 */
<> 144:ef7eb2e8f9f7 1102 #define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1103 #define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1104 #define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1105 #define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1106 #define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 #define ADC_SQR2_SQ22 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 22 */
<> 144:ef7eb2e8f9f7 1109 #define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1110 #define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1111 #define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1112 #define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1113 #define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 #define ADC_SQR2_SQ23 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 23 */
<> 144:ef7eb2e8f9f7 1116 #define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1117 #define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1118 #define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1119 #define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1120 #define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 #define ADC_SQR2_SQ24 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 24 */
<> 144:ef7eb2e8f9f7 1123 #define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1124 #define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1125 #define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1126 #define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1127 #define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000U) /*!< Bit 4 */
mbed_official 67:4bcbbb9fcddf 1128
mbed_official 67:4bcbbb9fcddf 1129 /******************* Bit definition for ADC_SQR3 register *******************/
<> 144:ef7eb2e8f9f7 1130 #define ADC_SQR3_SQ13 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 13 */
<> 144:ef7eb2e8f9f7 1131 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1132 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1133 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1134 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1135 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 #define ADC_SQR3_SQ14 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 14 */
<> 144:ef7eb2e8f9f7 1138 #define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1139 #define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1140 #define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1141 #define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1142 #define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 #define ADC_SQR3_SQ15 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 15 */
<> 144:ef7eb2e8f9f7 1145 #define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1146 #define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1147 #define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1148 #define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1149 #define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1150
<> 144:ef7eb2e8f9f7 1151 #define ADC_SQR3_SQ16 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 16 */
<> 144:ef7eb2e8f9f7 1152 #define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1153 #define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1154 #define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1155 #define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1156 #define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 #define ADC_SQR3_SQ17 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 17 */
<> 144:ef7eb2e8f9f7 1159 #define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1160 #define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1161 #define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1162 #define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1163 #define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 #define ADC_SQR3_SQ18 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 18 */
<> 144:ef7eb2e8f9f7 1166 #define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1167 #define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1168 #define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1169 #define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1170 #define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000U) /*!< Bit 4 */
mbed_official 67:4bcbbb9fcddf 1171
mbed_official 67:4bcbbb9fcddf 1172 /******************* Bit definition for ADC_SQR4 register *******************/
<> 144:ef7eb2e8f9f7 1173 #define ADC_SQR4_SQ7 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 7 */
<> 144:ef7eb2e8f9f7 1174 #define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1175 #define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1176 #define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1177 #define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1178 #define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1179
<> 144:ef7eb2e8f9f7 1180 #define ADC_SQR4_SQ8 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 8 */
<> 144:ef7eb2e8f9f7 1181 #define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1182 #define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1183 #define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1184 #define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1185 #define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 #define ADC_SQR4_SQ9 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 9 */
<> 144:ef7eb2e8f9f7 1188 #define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1189 #define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1190 #define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1191 #define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1192 #define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 #define ADC_SQR4_SQ10 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 10 */
<> 144:ef7eb2e8f9f7 1195 #define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1196 #define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1197 #define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1198 #define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1199 #define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1200
<> 144:ef7eb2e8f9f7 1201 #define ADC_SQR4_SQ11 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 11 */
<> 144:ef7eb2e8f9f7 1202 #define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1203 #define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1204 #define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1205 #define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1206 #define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 #define ADC_SQR4_SQ12 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 12 */
<> 144:ef7eb2e8f9f7 1209 #define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1210 #define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1211 #define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1212 #define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1213 #define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000U) /*!< Bit 4 */
mbed_official 67:4bcbbb9fcddf 1214
mbed_official 67:4bcbbb9fcddf 1215 /******************* Bit definition for ADC_SQR5 register *******************/
<> 144:ef7eb2e8f9f7 1216 #define ADC_SQR5_SQ1 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 1 */
<> 144:ef7eb2e8f9f7 1217 #define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1218 #define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1219 #define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1220 #define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1221 #define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 #define ADC_SQR5_SQ2 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 2 */
<> 144:ef7eb2e8f9f7 1224 #define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1225 #define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1226 #define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1227 #define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1228 #define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230 #define ADC_SQR5_SQ3 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 3 */
<> 144:ef7eb2e8f9f7 1231 #define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1232 #define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1233 #define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1234 #define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1235 #define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 #define ADC_SQR5_SQ4 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 4 */
<> 144:ef7eb2e8f9f7 1238 #define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1239 #define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1240 #define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1241 #define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1242 #define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1243
<> 144:ef7eb2e8f9f7 1244 #define ADC_SQR5_SQ5 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 5 */
<> 144:ef7eb2e8f9f7 1245 #define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1246 #define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1247 #define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1248 #define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1249 #define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1250
<> 144:ef7eb2e8f9f7 1251 #define ADC_SQR5_SQ6 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 6 */
<> 144:ef7eb2e8f9f7 1252 #define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1253 #define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1254 #define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1255 #define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1256 #define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000U) /*!< Bit 4 */
mbed_official 67:4bcbbb9fcddf 1257
mbed_official 67:4bcbbb9fcddf 1258
mbed_official 67:4bcbbb9fcddf 1259 /******************* Bit definition for ADC_JSQR register *******************/
<> 144:ef7eb2e8f9f7 1260 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001FU) /*!< ADC group injected sequencer rank 1 */
<> 144:ef7eb2e8f9f7 1261 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1262 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1263 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1264 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1265 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1266
<> 144:ef7eb2e8f9f7 1267 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0U) /*!< ADC group injected sequencer rank 2 */
<> 144:ef7eb2e8f9f7 1268 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1269 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1270 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1271 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1272 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1273
<> 144:ef7eb2e8f9f7 1274 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00U) /*!< ADC group injected sequencer rank 3 */
<> 144:ef7eb2e8f9f7 1275 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1276 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1277 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1278 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1279 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000U) /*!< ADC group injected sequencer rank 4 */
<> 144:ef7eb2e8f9f7 1282 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1283 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1284 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1285 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1286 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 #define ADC_JSQR_JL ((uint32_t)0x00300000U) /*!< ADC group injected sequencer scan length */
<> 144:ef7eb2e8f9f7 1289 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1290 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
mbed_official 67:4bcbbb9fcddf 1291
mbed_official 67:4bcbbb9fcddf 1292 /******************* Bit definition for ADC_JDR1 register *******************/
<> 144:ef7eb2e8f9f7 1293 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 1 conversion data */
mbed_official 67:4bcbbb9fcddf 1294
mbed_official 67:4bcbbb9fcddf 1295 /******************* Bit definition for ADC_JDR2 register *******************/
<> 144:ef7eb2e8f9f7 1296 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 2 conversion data */
mbed_official 67:4bcbbb9fcddf 1297
mbed_official 67:4bcbbb9fcddf 1298 /******************* Bit definition for ADC_JDR3 register *******************/
<> 144:ef7eb2e8f9f7 1299 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 3 conversion data */
mbed_official 67:4bcbbb9fcddf 1300
mbed_official 67:4bcbbb9fcddf 1301 /******************* Bit definition for ADC_JDR4 register *******************/
<> 144:ef7eb2e8f9f7 1302 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 4 conversion data */
mbed_official 67:4bcbbb9fcddf 1303
mbed_official 67:4bcbbb9fcddf 1304 /******************** Bit definition for ADC_DR register ********************/
<> 144:ef7eb2e8f9f7 1305 #define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */
mbed_official 67:4bcbbb9fcddf 1306
mbed_official 67:4bcbbb9fcddf 1307 /******************* Bit definition for ADC_CSR register ********************/
<> 144:ef7eb2e8f9f7 1308 #define ADC_CSR_AWD1 ((uint32_t)0x00000001U) /*!< ADC multimode master analog watchdog 1 flag */
<> 144:ef7eb2e8f9f7 1309 #define ADC_CSR_EOCS1 ((uint32_t)0x00000002U) /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
<> 144:ef7eb2e8f9f7 1310 #define ADC_CSR_JEOS1 ((uint32_t)0x00000004U) /*!< ADC multimode master group injected end of sequence conversions flag */
<> 144:ef7eb2e8f9f7 1311 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008U) /*!< ADC multimode master group injected conversion start flag */
<> 144:ef7eb2e8f9f7 1312 #define ADC_CSR_STRT1 ((uint32_t)0x00000010U) /*!< ADC multimode master group regular conversion start flag */
<> 144:ef7eb2e8f9f7 1313 #define ADC_CSR_OVR1 ((uint32_t)0x00000020U) /*!< ADC multimode master group regular overrun flag */
<> 144:ef7eb2e8f9f7 1314 #define ADC_CSR_ADONS1 ((uint32_t)0x00000040U) /*!< ADC multimode master ready flag */
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /* Legacy defines */
<> 144:ef7eb2e8f9f7 1317 #define ADC_CSR_EOC1 (ADC_CSR_EOCS1)
<> 144:ef7eb2e8f9f7 1318 #define ADC_CSR_JEOC1 (ADC_CSR_JEOS1)
mbed_official 67:4bcbbb9fcddf 1319
mbed_official 67:4bcbbb9fcddf 1320 /******************* Bit definition for ADC_CCR register ********************/
<> 144:ef7eb2e8f9f7 1321 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000U) /*!< ADC clock source asynchronous prescaler */
<> 144:ef7eb2e8f9f7 1322 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1323 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1324 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000U) /*!< ADC internal path to VrefInt and temperature sensor enable */
mbed_official 67:4bcbbb9fcddf 1325
mbed_official 67:4bcbbb9fcddf 1326 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1327 /* */
mbed_official 67:4bcbbb9fcddf 1328 /* Analog Comparators (COMP) */
mbed_official 67:4bcbbb9fcddf 1329 /* */
mbed_official 67:4bcbbb9fcddf 1330 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1331
mbed_official 67:4bcbbb9fcddf 1332 /****************** Bit definition for COMP_CSR register ********************/
<> 144:ef7eb2e8f9f7 1333 #define COMP_CSR_10KPU ((uint32_t)0x00000001U) /*!< 10K pull-up resistor */
<> 144:ef7eb2e8f9f7 1334 #define COMP_CSR_400KPU ((uint32_t)0x00000002U) /*!< 400K pull-up resistor */
<> 144:ef7eb2e8f9f7 1335 #define COMP_CSR_10KPD ((uint32_t)0x00000004U) /*!< 10K pull-down resistor */
<> 144:ef7eb2e8f9f7 1336 #define COMP_CSR_400KPD ((uint32_t)0x00000008U) /*!< 400K pull-down resistor */
<> 144:ef7eb2e8f9f7 1337 #define COMP_CSR_CMP1EN ((uint32_t)0x00000010U) /*!< Comparator 1 enable */
<> 144:ef7eb2e8f9f7 1338 #define COMP_CSR_CMP1OUT ((uint32_t)0x00000080U) /*!< Comparator 1 output */
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 #define COMP_CSR_SPEED ((uint32_t)0x00001000U) /*!< Comparator 2 speed */
<> 144:ef7eb2e8f9f7 1341 #define COMP_CSR_CMP2OUT ((uint32_t)0x00002000U) /*!< Comparator 2 ouput */
<> 144:ef7eb2e8f9f7 1342 #define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000U) /*!< Comparator Vref Enable */
<> 144:ef7eb2e8f9f7 1343 #define COMP_CSR_WNDWE ((uint32_t)0x00020000U) /*!< Window mode enable */
<> 144:ef7eb2e8f9f7 1344 #define COMP_CSR_INSEL ((uint32_t)0x001C0000U) /*!< INSEL[2:0] Inversion input Selection */
<> 144:ef7eb2e8f9f7 1345 #define COMP_CSR_INSEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1346 #define COMP_CSR_INSEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1347 #define COMP_CSR_INSEL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1348 #define COMP_CSR_OUTSEL ((uint32_t)0x00E00000U) /*!< OUTSEL[2:0] comparator 2 output redirection */
<> 144:ef7eb2e8f9f7 1349 #define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1350 #define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1351 #define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1352
<> 144:ef7eb2e8f9f7 1353 #define COMP_CSR_FCH3 ((uint32_t)0x04000000U) /*!< Bit 26 */
<> 144:ef7eb2e8f9f7 1354 #define COMP_CSR_FCH8 ((uint32_t)0x08000000U) /*!< Bit 27 */
<> 144:ef7eb2e8f9f7 1355 #define COMP_CSR_RCH13 ((uint32_t)0x10000000U) /*!< Bit 28 */
<> 144:ef7eb2e8f9f7 1356
<> 144:ef7eb2e8f9f7 1357 #define COMP_CSR_CAIE ((uint32_t)0x20000000U) /*!< Bit 29 */
<> 144:ef7eb2e8f9f7 1358 #define COMP_CSR_CAIF ((uint32_t)0x40000000U) /*!< Bit 30 */
<> 144:ef7eb2e8f9f7 1359 #define COMP_CSR_TSUSP ((uint32_t)0x80000000U) /*!< Bit 31 */
mbed_official 67:4bcbbb9fcddf 1360
mbed_official 67:4bcbbb9fcddf 1361 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1362 /* */
mbed_official 67:4bcbbb9fcddf 1363 /* Operational Amplifier (OPAMP) */
mbed_official 67:4bcbbb9fcddf 1364 /* */
mbed_official 67:4bcbbb9fcddf 1365 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1366 /******************* Bit definition for OPAMP_CSR register ******************/
<> 144:ef7eb2e8f9f7 1367 #define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001U) /*!< OPAMP1 disable */
<> 144:ef7eb2e8f9f7 1368 #define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002U) /*!< Switch 3 for OPAMP1 Enable */
<> 144:ef7eb2e8f9f7 1369 #define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004U) /*!< Switch 4 for OPAMP1 Enable */
<> 144:ef7eb2e8f9f7 1370 #define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008U) /*!< Switch 5 for OPAMP1 Enable */
<> 144:ef7eb2e8f9f7 1371 #define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010U) /*!< Switch 6 for OPAMP1 Enable */
<> 144:ef7eb2e8f9f7 1372 #define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020U) /*!< OPAMP1 Offset calibration for P differential pair */
<> 144:ef7eb2e8f9f7 1373 #define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040U) /*!< OPAMP1 Offset calibration for N differential pair */
<> 144:ef7eb2e8f9f7 1374 #define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080U) /*!< OPAMP1 Low power enable */
<> 144:ef7eb2e8f9f7 1375 #define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100U) /*!< OPAMP2 disable */
<> 144:ef7eb2e8f9f7 1376 #define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200U) /*!< Switch 3 for OPAMP2 Enable */
<> 144:ef7eb2e8f9f7 1377 #define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400U) /*!< Switch 4 for OPAMP2 Enable */
<> 144:ef7eb2e8f9f7 1378 #define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800U) /*!< Switch 5 for OPAMP2 Enable */
<> 144:ef7eb2e8f9f7 1379 #define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000U) /*!< Switch 6 for OPAMP2 Enable */
<> 144:ef7eb2e8f9f7 1380 #define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000U) /*!< OPAMP2 Offset calibration for P differential pair */
<> 144:ef7eb2e8f9f7 1381 #define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000U) /*!< OPAMP2 Offset calibration for N differential pair */
<> 144:ef7eb2e8f9f7 1382 #define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000U) /*!< OPAMP2 Low power enable */
<> 144:ef7eb2e8f9f7 1383 #define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000U) /*!< Switch ANA Enable for OPAMP1 */
<> 144:ef7eb2e8f9f7 1384 #define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000U) /*!< Switch ANA Enable for OPAMP2 */
<> 144:ef7eb2e8f9f7 1385 #define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000U) /*!< Switch 7 for OPAMP2 Enable */
<> 144:ef7eb2e8f9f7 1386 #define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000U) /*!< Power range selection */
<> 144:ef7eb2e8f9f7 1387 #define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000U) /*!< OPAMP1 calibration output */
<> 144:ef7eb2e8f9f7 1388 #define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000U) /*!< OPAMP2 calibration output */
mbed_official 67:4bcbbb9fcddf 1389
mbed_official 67:4bcbbb9fcddf 1390 /******************* Bit definition for OPAMP_OTR register ******************/
<> 144:ef7eb2e8f9f7 1391 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001FU) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
<> 144:ef7eb2e8f9f7 1392 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0U) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
<> 144:ef7eb2e8f9f7 1393 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00U) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
<> 144:ef7eb2e8f9f7 1394 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000U) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
<> 144:ef7eb2e8f9f7 1395 #define OPAMP_OTR_OT_USER ((uint32_t)0x80000000U) /*!< Switch to OPAMP offset user trimmed values */
mbed_official 67:4bcbbb9fcddf 1396
mbed_official 67:4bcbbb9fcddf 1397 /******************* Bit definition for OPAMP_LPOTR register ****************/
<> 144:ef7eb2e8f9f7 1398 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001FU) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
<> 144:ef7eb2e8f9f7 1399 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0U) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
<> 144:ef7eb2e8f9f7 1400 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00U) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
<> 144:ef7eb2e8f9f7 1401 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000U) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
mbed_official 67:4bcbbb9fcddf 1402
mbed_official 67:4bcbbb9fcddf 1403 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1404 /* */
mbed_official 67:4bcbbb9fcddf 1405 /* CRC calculation unit (CRC) */
mbed_official 67:4bcbbb9fcddf 1406 /* */
mbed_official 67:4bcbbb9fcddf 1407 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1408
mbed_official 67:4bcbbb9fcddf 1409 /******************* Bit definition for CRC_DR register *********************/
<> 144:ef7eb2e8f9f7 1410 #define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
mbed_official 67:4bcbbb9fcddf 1411
mbed_official 67:4bcbbb9fcddf 1412 /******************* Bit definition for CRC_IDR register ********************/
<> 144:ef7eb2e8f9f7 1413 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 67:4bcbbb9fcddf 1414
mbed_official 67:4bcbbb9fcddf 1415 /******************** Bit definition for CRC_CR register ********************/
<> 144:ef7eb2e8f9f7 1416 #define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET bit */
mbed_official 67:4bcbbb9fcddf 1417
mbed_official 67:4bcbbb9fcddf 1418 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1419 /* */
mbed_official 67:4bcbbb9fcddf 1420 /* Digital to Analog Converter (DAC) */
mbed_official 67:4bcbbb9fcddf 1421 /* */
mbed_official 67:4bcbbb9fcddf 1422 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1423
mbed_official 67:4bcbbb9fcddf 1424 /******************** Bit definition for DAC_CR register ********************/
<> 144:ef7eb2e8f9f7 1425 #define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!<DAC channel1 enable */
<> 144:ef7eb2e8f9f7 1426 #define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /*!<DAC channel1 output buffer disable */
<> 144:ef7eb2e8f9f7 1427 #define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!<DAC channel1 Trigger enable */
<> 144:ef7eb2e8f9f7 1428
<> 144:ef7eb2e8f9f7 1429 #define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
<> 144:ef7eb2e8f9f7 1430 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1431 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1432 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1433
<> 144:ef7eb2e8f9f7 1434 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
<> 144:ef7eb2e8f9f7 1435 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1436 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1437
<> 144:ef7eb2e8f9f7 1438 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
<> 144:ef7eb2e8f9f7 1439 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1440 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1441 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1442 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!<DAC channel1 DMA enable */
<> 144:ef7eb2e8f9f7 1445 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!<DAC channel1 DMA Interrupt enable */
<> 144:ef7eb2e8f9f7 1446 #define DAC_CR_EN2 ((uint32_t)0x00010000U) /*!<DAC channel2 enable */
<> 144:ef7eb2e8f9f7 1447 #define DAC_CR_BOFF2 ((uint32_t)0x00020000U) /*!<DAC channel2 output buffer disable */
<> 144:ef7eb2e8f9f7 1448 #define DAC_CR_TEN2 ((uint32_t)0x00040000U) /*!<DAC channel2 Trigger enable */
<> 144:ef7eb2e8f9f7 1449
<> 144:ef7eb2e8f9f7 1450 #define DAC_CR_TSEL2 ((uint32_t)0x00380000U) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
<> 144:ef7eb2e8f9f7 1451 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1452 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1453 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1454
<> 144:ef7eb2e8f9f7 1455 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000U) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
<> 144:ef7eb2e8f9f7 1456 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1457 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1458
<> 144:ef7eb2e8f9f7 1459 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000U) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
<> 144:ef7eb2e8f9f7 1460 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1461 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1462 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1463 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000U) /*!<DAC channel2 DMA enabled */
<> 144:ef7eb2e8f9f7 1466 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) /*!<DAC channel2 DMA underrun interrupt enable */
mbed_official 67:4bcbbb9fcddf 1467 /***************** Bit definition for DAC_SWTRIGR register ******************/
<> 144:ef7eb2e8f9f7 1468 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!<DAC channel1 software trigger */
<> 144:ef7eb2e8f9f7 1469 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002U) /*!<DAC channel2 software trigger */
mbed_official 67:4bcbbb9fcddf 1470
mbed_official 67:4bcbbb9fcddf 1471 /***************** Bit definition for DAC_DHR12R1 register ******************/
<> 144:ef7eb2e8f9f7 1472 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 67:4bcbbb9fcddf 1473
mbed_official 67:4bcbbb9fcddf 1474 /***************** Bit definition for DAC_DHR12L1 register ******************/
<> 144:ef7eb2e8f9f7 1475 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 67:4bcbbb9fcddf 1476
mbed_official 67:4bcbbb9fcddf 1477 /****************** Bit definition for DAC_DHR8R1 register ******************/
<> 144:ef7eb2e8f9f7 1478 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 67:4bcbbb9fcddf 1479
mbed_official 67:4bcbbb9fcddf 1480 /***************** Bit definition for DAC_DHR12R2 register ******************/
<> 144:ef7eb2e8f9f7 1481 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFFU) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 67:4bcbbb9fcddf 1482
mbed_official 67:4bcbbb9fcddf 1483 /***************** Bit definition for DAC_DHR12L2 register ******************/
<> 144:ef7eb2e8f9f7 1484 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 67:4bcbbb9fcddf 1485
mbed_official 67:4bcbbb9fcddf 1486 /****************** Bit definition for DAC_DHR8R2 register ******************/
<> 144:ef7eb2e8f9f7 1487 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FFU) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 67:4bcbbb9fcddf 1488
mbed_official 67:4bcbbb9fcddf 1489 /***************** Bit definition for DAC_DHR12RD register ******************/
<> 144:ef7eb2e8f9f7 1490 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFFU) /*!<DAC channel1 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 1491 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000U) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 67:4bcbbb9fcddf 1492
mbed_official 67:4bcbbb9fcddf 1493 /***************** Bit definition for DAC_DHR12LD register ******************/
<> 144:ef7eb2e8f9f7 1494 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel1 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 1495 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000U) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 67:4bcbbb9fcddf 1496
mbed_official 67:4bcbbb9fcddf 1497 /****************** Bit definition for DAC_DHR8RD register ******************/
<> 144:ef7eb2e8f9f7 1498 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FFU) /*!<DAC channel1 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 1499 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00U) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 67:4bcbbb9fcddf 1500
mbed_official 67:4bcbbb9fcddf 1501 /******************* Bit definition for DAC_DOR1 register *******************/
<> 144:ef7eb2e8f9f7 1502 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFFU) /*!<DAC channel1 data output */
mbed_official 67:4bcbbb9fcddf 1503
mbed_official 67:4bcbbb9fcddf 1504 /******************* Bit definition for DAC_DOR2 register *******************/
<> 144:ef7eb2e8f9f7 1505 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!<DAC channel2 data output */
mbed_official 67:4bcbbb9fcddf 1506
mbed_official 67:4bcbbb9fcddf 1507 /******************** Bit definition for DAC_SR register ********************/
<> 144:ef7eb2e8f9f7 1508 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!<DAC channel1 DMA underrun flag */
<> 144:ef7eb2e8f9f7 1509 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000U) /*!<DAC channel2 DMA underrun flag */
mbed_official 67:4bcbbb9fcddf 1510
mbed_official 67:4bcbbb9fcddf 1511 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1512 /* */
mbed_official 67:4bcbbb9fcddf 1513 /* Debug MCU (DBGMCU) */
mbed_official 67:4bcbbb9fcddf 1514 /* */
mbed_official 67:4bcbbb9fcddf 1515 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1516
mbed_official 67:4bcbbb9fcddf 1517 /**************** Bit definition for DBGMCU_IDCODE register *****************/
<> 144:ef7eb2e8f9f7 1518 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */
<> 144:ef7eb2e8f9f7 1519
<> 144:ef7eb2e8f9f7 1520 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */
<> 144:ef7eb2e8f9f7 1521 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1522 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1523 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 1524 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 1525 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 1526 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 1527 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 1528 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 1529 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 1530 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 1531 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 1532 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 1533 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 1534 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 1535 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 1536 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 1537
mbed_official 67:4bcbbb9fcddf 1538 /****************** Bit definition for DBGMCU_CR register *******************/
<> 144:ef7eb2e8f9f7 1539 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /*!< Debug Sleep Mode */
<> 144:ef7eb2e8f9f7 1540 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */
<> 144:ef7eb2e8f9f7 1541 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */
<> 144:ef7eb2e8f9f7 1542 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020U) /*!< Trace Pin Assignment Control */
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0U) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
<> 144:ef7eb2e8f9f7 1545 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1546 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
mbed_official 67:4bcbbb9fcddf 1547
mbed_official 67:4bcbbb9fcddf 1548 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
mbed_official 67:4bcbbb9fcddf 1549
<> 144:ef7eb2e8f9f7 1550 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 1551 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002U) /*!< TIM3 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 1552 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004U) /*!< TIM4 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 1553 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008U) /*!< TIM5 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 1554 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /*!< TIM6 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 1555 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020U) /*!< TIM7 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 1556 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Counter stopped when Core is halted */
<> 144:ef7eb2e8f9f7 1557 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */
<> 144:ef7eb2e8f9f7 1558 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */
<> 144:ef7eb2e8f9f7 1559 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000U) /*!< SMBUS timeout mode stopped when Core is halted */
<> 144:ef7eb2e8f9f7 1560 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000U) /*!< SMBUS timeout mode stopped when Core is halted */
mbed_official 67:4bcbbb9fcddf 1561
mbed_official 67:4bcbbb9fcddf 1562 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
mbed_official 67:4bcbbb9fcddf 1563
<> 144:ef7eb2e8f9f7 1564 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004U) /*!< TIM9 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 1565 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008U) /*!< TIM10 counter stopped when core is halted */
<> 144:ef7eb2e8f9f7 1566 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010U) /*!< TIM11 counter stopped when core is halted */
mbed_official 67:4bcbbb9fcddf 1567
mbed_official 67:4bcbbb9fcddf 1568 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1569 /* */
mbed_official 67:4bcbbb9fcddf 1570 /* DMA Controller (DMA) */
mbed_official 67:4bcbbb9fcddf 1571 /* */
mbed_official 67:4bcbbb9fcddf 1572 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1573
mbed_official 67:4bcbbb9fcddf 1574 /******************* Bit definition for DMA_ISR register ********************/
<> 144:ef7eb2e8f9f7 1575 #define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */
<> 144:ef7eb2e8f9f7 1576 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 1577 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */
<> 144:ef7eb2e8f9f7 1578 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */
<> 144:ef7eb2e8f9f7 1579 #define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */
<> 144:ef7eb2e8f9f7 1580 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 1581 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */
<> 144:ef7eb2e8f9f7 1582 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */
<> 144:ef7eb2e8f9f7 1583 #define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */
<> 144:ef7eb2e8f9f7 1584 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 1585 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */
<> 144:ef7eb2e8f9f7 1586 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */
<> 144:ef7eb2e8f9f7 1587 #define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */
<> 144:ef7eb2e8f9f7 1588 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 1589 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */
<> 144:ef7eb2e8f9f7 1590 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */
<> 144:ef7eb2e8f9f7 1591 #define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */
<> 144:ef7eb2e8f9f7 1592 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 1593 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */
<> 144:ef7eb2e8f9f7 1594 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */
<> 144:ef7eb2e8f9f7 1595 #define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */
<> 144:ef7eb2e8f9f7 1596 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 1597 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */
<> 144:ef7eb2e8f9f7 1598 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */
<> 144:ef7eb2e8f9f7 1599 #define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */
<> 144:ef7eb2e8f9f7 1600 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */
<> 144:ef7eb2e8f9f7 1601 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */
<> 144:ef7eb2e8f9f7 1602 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */
mbed_official 67:4bcbbb9fcddf 1603
mbed_official 67:4bcbbb9fcddf 1604 /******************* Bit definition for DMA_IFCR register *******************/
<> 144:ef7eb2e8f9f7 1605 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */
<> 144:ef7eb2e8f9f7 1606 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 1607 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */
<> 144:ef7eb2e8f9f7 1608 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */
<> 144:ef7eb2e8f9f7 1609 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */
<> 144:ef7eb2e8f9f7 1610 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 1611 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */
<> 144:ef7eb2e8f9f7 1612 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */
<> 144:ef7eb2e8f9f7 1613 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */
<> 144:ef7eb2e8f9f7 1614 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 1615 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */
<> 144:ef7eb2e8f9f7 1616 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */
<> 144:ef7eb2e8f9f7 1617 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */
<> 144:ef7eb2e8f9f7 1618 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 1619 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */
<> 144:ef7eb2e8f9f7 1620 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */
<> 144:ef7eb2e8f9f7 1621 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */
<> 144:ef7eb2e8f9f7 1622 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 1623 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */
<> 144:ef7eb2e8f9f7 1624 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */
<> 144:ef7eb2e8f9f7 1625 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */
<> 144:ef7eb2e8f9f7 1626 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 1627 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */
<> 144:ef7eb2e8f9f7 1628 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */
<> 144:ef7eb2e8f9f7 1629 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */
<> 144:ef7eb2e8f9f7 1630 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */
<> 144:ef7eb2e8f9f7 1631 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */
<> 144:ef7eb2e8f9f7 1632 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */
mbed_official 67:4bcbbb9fcddf 1633
mbed_official 67:4bcbbb9fcddf 1634 /******************* Bit definition for DMA_CCR register *******************/
<> 144:ef7eb2e8f9f7 1635 #define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable*/
<> 144:ef7eb2e8f9f7 1636 #define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */
<> 144:ef7eb2e8f9f7 1637 #define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */
<> 144:ef7eb2e8f9f7 1638 #define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */
<> 144:ef7eb2e8f9f7 1639 #define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */
<> 144:ef7eb2e8f9f7 1640 #define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */
<> 144:ef7eb2e8f9f7 1641 #define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */
<> 144:ef7eb2e8f9f7 1642 #define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */
<> 144:ef7eb2e8f9f7 1643
<> 144:ef7eb2e8f9f7 1644 #define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */
<> 144:ef7eb2e8f9f7 1645 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1646 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1647
<> 144:ef7eb2e8f9f7 1648 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */
<> 144:ef7eb2e8f9f7 1649 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1650 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1651
<> 144:ef7eb2e8f9f7 1652 #define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level) */
<> 144:ef7eb2e8f9f7 1653 #define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 1654 #define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 1655
<> 144:ef7eb2e8f9f7 1656 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */
<> 144:ef7eb2e8f9f7 1657
<> 144:ef7eb2e8f9f7 1658 /****************** Bit definition generic for DMA_CNDTR register *******************/
<> 144:ef7eb2e8f9f7 1659 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
mbed_official 67:4bcbbb9fcddf 1660
mbed_official 67:4bcbbb9fcddf 1661 /****************** Bit definition for DMA_CNDTR1 register ******************/
<> 144:ef7eb2e8f9f7 1662 #define DMA_CNDTR1_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
mbed_official 67:4bcbbb9fcddf 1663
mbed_official 67:4bcbbb9fcddf 1664 /****************** Bit definition for DMA_CNDTR2 register ******************/
<> 144:ef7eb2e8f9f7 1665 #define DMA_CNDTR2_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
mbed_official 67:4bcbbb9fcddf 1666
mbed_official 67:4bcbbb9fcddf 1667 /****************** Bit definition for DMA_CNDTR3 register ******************/
<> 144:ef7eb2e8f9f7 1668 #define DMA_CNDTR3_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
mbed_official 67:4bcbbb9fcddf 1669
mbed_official 67:4bcbbb9fcddf 1670 /****************** Bit definition for DMA_CNDTR4 register ******************/
<> 144:ef7eb2e8f9f7 1671 #define DMA_CNDTR4_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
mbed_official 67:4bcbbb9fcddf 1672
mbed_official 67:4bcbbb9fcddf 1673 /****************** Bit definition for DMA_CNDTR5 register ******************/
<> 144:ef7eb2e8f9f7 1674 #define DMA_CNDTR5_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
mbed_official 67:4bcbbb9fcddf 1675
mbed_official 67:4bcbbb9fcddf 1676 /****************** Bit definition for DMA_CNDTR6 register ******************/
<> 144:ef7eb2e8f9f7 1677 #define DMA_CNDTR6_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
mbed_official 67:4bcbbb9fcddf 1678
mbed_official 67:4bcbbb9fcddf 1679 /****************** Bit definition for DMA_CNDTR7 register ******************/
<> 144:ef7eb2e8f9f7 1680 #define DMA_CNDTR7_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
<> 144:ef7eb2e8f9f7 1681
<> 144:ef7eb2e8f9f7 1682 /****************** Bit definition generic for DMA_CPAR register ********************/
<> 144:ef7eb2e8f9f7 1683 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
mbed_official 67:4bcbbb9fcddf 1684
mbed_official 67:4bcbbb9fcddf 1685 /****************** Bit definition for DMA_CPAR1 register *******************/
<> 144:ef7eb2e8f9f7 1686 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
mbed_official 67:4bcbbb9fcddf 1687
mbed_official 67:4bcbbb9fcddf 1688 /****************** Bit definition for DMA_CPAR2 register *******************/
<> 144:ef7eb2e8f9f7 1689 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
mbed_official 67:4bcbbb9fcddf 1690
mbed_official 67:4bcbbb9fcddf 1691 /****************** Bit definition for DMA_CPAR3 register *******************/
<> 144:ef7eb2e8f9f7 1692 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
mbed_official 67:4bcbbb9fcddf 1693
mbed_official 67:4bcbbb9fcddf 1694
mbed_official 67:4bcbbb9fcddf 1695 /****************** Bit definition for DMA_CPAR4 register *******************/
<> 144:ef7eb2e8f9f7 1696 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
mbed_official 67:4bcbbb9fcddf 1697
mbed_official 67:4bcbbb9fcddf 1698 /****************** Bit definition for DMA_CPAR5 register *******************/
<> 144:ef7eb2e8f9f7 1699 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
mbed_official 67:4bcbbb9fcddf 1700
mbed_official 67:4bcbbb9fcddf 1701 /****************** Bit definition for DMA_CPAR6 register *******************/
<> 144:ef7eb2e8f9f7 1702 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
mbed_official 67:4bcbbb9fcddf 1703
mbed_official 67:4bcbbb9fcddf 1704
mbed_official 67:4bcbbb9fcddf 1705 /****************** Bit definition for DMA_CPAR7 register *******************/
<> 144:ef7eb2e8f9f7 1706 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
<> 144:ef7eb2e8f9f7 1707
<> 144:ef7eb2e8f9f7 1708 /****************** Bit definition generic for DMA_CMAR register ********************/
<> 144:ef7eb2e8f9f7 1709 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
mbed_official 67:4bcbbb9fcddf 1710
mbed_official 67:4bcbbb9fcddf 1711 /****************** Bit definition for DMA_CMAR1 register *******************/
<> 144:ef7eb2e8f9f7 1712 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
mbed_official 67:4bcbbb9fcddf 1713
mbed_official 67:4bcbbb9fcddf 1714 /****************** Bit definition for DMA_CMAR2 register *******************/
<> 144:ef7eb2e8f9f7 1715 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
mbed_official 67:4bcbbb9fcddf 1716
mbed_official 67:4bcbbb9fcddf 1717 /****************** Bit definition for DMA_CMAR3 register *******************/
<> 144:ef7eb2e8f9f7 1718 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
mbed_official 67:4bcbbb9fcddf 1719
mbed_official 67:4bcbbb9fcddf 1720
mbed_official 67:4bcbbb9fcddf 1721 /****************** Bit definition for DMA_CMAR4 register *******************/
<> 144:ef7eb2e8f9f7 1722 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
mbed_official 67:4bcbbb9fcddf 1723
mbed_official 67:4bcbbb9fcddf 1724 /****************** Bit definition for DMA_CMAR5 register *******************/
<> 144:ef7eb2e8f9f7 1725 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
mbed_official 67:4bcbbb9fcddf 1726
mbed_official 67:4bcbbb9fcddf 1727 /****************** Bit definition for DMA_CMAR6 register *******************/
<> 144:ef7eb2e8f9f7 1728 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
mbed_official 67:4bcbbb9fcddf 1729
mbed_official 67:4bcbbb9fcddf 1730 /****************** Bit definition for DMA_CMAR7 register *******************/
<> 144:ef7eb2e8f9f7 1731 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
mbed_official 67:4bcbbb9fcddf 1732
mbed_official 67:4bcbbb9fcddf 1733 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1734 /* */
mbed_official 67:4bcbbb9fcddf 1735 /* External Interrupt/Event Controller (EXTI) */
mbed_official 67:4bcbbb9fcddf 1736 /* */
mbed_official 67:4bcbbb9fcddf 1737 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 1738
mbed_official 67:4bcbbb9fcddf 1739 /******************* Bit definition for EXTI_IMR register *******************/
<> 144:ef7eb2e8f9f7 1740 #define EXTI_IMR_MR0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */
<> 144:ef7eb2e8f9f7 1741 #define EXTI_IMR_MR1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */
<> 144:ef7eb2e8f9f7 1742 #define EXTI_IMR_MR2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */
<> 144:ef7eb2e8f9f7 1743 #define EXTI_IMR_MR3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */
<> 144:ef7eb2e8f9f7 1744 #define EXTI_IMR_MR4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */
<> 144:ef7eb2e8f9f7 1745 #define EXTI_IMR_MR5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */
<> 144:ef7eb2e8f9f7 1746 #define EXTI_IMR_MR6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */
<> 144:ef7eb2e8f9f7 1747 #define EXTI_IMR_MR7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */
<> 144:ef7eb2e8f9f7 1748 #define EXTI_IMR_MR8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */
<> 144:ef7eb2e8f9f7 1749 #define EXTI_IMR_MR9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */
<> 144:ef7eb2e8f9f7 1750 #define EXTI_IMR_MR10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */
<> 144:ef7eb2e8f9f7 1751 #define EXTI_IMR_MR11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */
<> 144:ef7eb2e8f9f7 1752 #define EXTI_IMR_MR12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */
<> 144:ef7eb2e8f9f7 1753 #define EXTI_IMR_MR13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */
<> 144:ef7eb2e8f9f7 1754 #define EXTI_IMR_MR14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */
<> 144:ef7eb2e8f9f7 1755 #define EXTI_IMR_MR15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */
<> 144:ef7eb2e8f9f7 1756 #define EXTI_IMR_MR16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */
<> 144:ef7eb2e8f9f7 1757 #define EXTI_IMR_MR17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */
<> 144:ef7eb2e8f9f7 1758 #define EXTI_IMR_MR18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */
<> 144:ef7eb2e8f9f7 1759 #define EXTI_IMR_MR19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */
<> 144:ef7eb2e8f9f7 1760 #define EXTI_IMR_MR20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */
<> 144:ef7eb2e8f9f7 1761 #define EXTI_IMR_MR21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */
<> 144:ef7eb2e8f9f7 1762 #define EXTI_IMR_MR22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */
<> 144:ef7eb2e8f9f7 1763 #define EXTI_IMR_MR23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */
<> 144:ef7eb2e8f9f7 1764
<> 144:ef7eb2e8f9f7 1765 /* References Defines */
<> 144:ef7eb2e8f9f7 1766 #define EXTI_IMR_IM0 EXTI_IMR_MR0
<> 144:ef7eb2e8f9f7 1767 #define EXTI_IMR_IM1 EXTI_IMR_MR1
<> 144:ef7eb2e8f9f7 1768 #define EXTI_IMR_IM2 EXTI_IMR_MR2
<> 144:ef7eb2e8f9f7 1769 #define EXTI_IMR_IM3 EXTI_IMR_MR3
<> 144:ef7eb2e8f9f7 1770 #define EXTI_IMR_IM4 EXTI_IMR_MR4
<> 144:ef7eb2e8f9f7 1771 #define EXTI_IMR_IM5 EXTI_IMR_MR5
<> 144:ef7eb2e8f9f7 1772 #define EXTI_IMR_IM6 EXTI_IMR_MR6
<> 144:ef7eb2e8f9f7 1773 #define EXTI_IMR_IM7 EXTI_IMR_MR7
<> 144:ef7eb2e8f9f7 1774 #define EXTI_IMR_IM8 EXTI_IMR_MR8
<> 144:ef7eb2e8f9f7 1775 #define EXTI_IMR_IM9 EXTI_IMR_MR9
<> 144:ef7eb2e8f9f7 1776 #define EXTI_IMR_IM10 EXTI_IMR_MR10
<> 144:ef7eb2e8f9f7 1777 #define EXTI_IMR_IM11 EXTI_IMR_MR11
<> 144:ef7eb2e8f9f7 1778 #define EXTI_IMR_IM12 EXTI_IMR_MR12
<> 144:ef7eb2e8f9f7 1779 #define EXTI_IMR_IM13 EXTI_IMR_MR13
<> 144:ef7eb2e8f9f7 1780 #define EXTI_IMR_IM14 EXTI_IMR_MR14
<> 144:ef7eb2e8f9f7 1781 #define EXTI_IMR_IM15 EXTI_IMR_MR15
<> 144:ef7eb2e8f9f7 1782 #define EXTI_IMR_IM16 EXTI_IMR_MR16
<> 144:ef7eb2e8f9f7 1783 #define EXTI_IMR_IM17 EXTI_IMR_MR17
<> 144:ef7eb2e8f9f7 1784 #define EXTI_IMR_IM18 EXTI_IMR_MR18
<> 144:ef7eb2e8f9f7 1785 #define EXTI_IMR_IM19 EXTI_IMR_MR19
<> 144:ef7eb2e8f9f7 1786 #define EXTI_IMR_IM20 EXTI_IMR_MR20
<> 144:ef7eb2e8f9f7 1787 #define EXTI_IMR_IM21 EXTI_IMR_MR21
<> 144:ef7eb2e8f9f7 1788 #define EXTI_IMR_IM22 EXTI_IMR_MR22
<> 144:ef7eb2e8f9f7 1789 /* Category 3, 4 & 5 */
<> 144:ef7eb2e8f9f7 1790 #define EXTI_IMR_IM23 EXTI_IMR_MR23
<> 144:ef7eb2e8f9f7 1791 #define EXTI_IMR_IM ((uint32_t)0x00FFFFFFU) /*!< Interrupt Mask All */
mbed_official 67:4bcbbb9fcddf 1792
mbed_official 67:4bcbbb9fcddf 1793 /******************* Bit definition for EXTI_EMR register *******************/
<> 144:ef7eb2e8f9f7 1794 #define EXTI_EMR_MR0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */
<> 144:ef7eb2e8f9f7 1795 #define EXTI_EMR_MR1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */
<> 144:ef7eb2e8f9f7 1796 #define EXTI_EMR_MR2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */
<> 144:ef7eb2e8f9f7 1797 #define EXTI_EMR_MR3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */
<> 144:ef7eb2e8f9f7 1798 #define EXTI_EMR_MR4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */
<> 144:ef7eb2e8f9f7 1799 #define EXTI_EMR_MR5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */
<> 144:ef7eb2e8f9f7 1800 #define EXTI_EMR_MR6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */
<> 144:ef7eb2e8f9f7 1801 #define EXTI_EMR_MR7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */
<> 144:ef7eb2e8f9f7 1802 #define EXTI_EMR_MR8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */
<> 144:ef7eb2e8f9f7 1803 #define EXTI_EMR_MR9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */
<> 144:ef7eb2e8f9f7 1804 #define EXTI_EMR_MR10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */
<> 144:ef7eb2e8f9f7 1805 #define EXTI_EMR_MR11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */
<> 144:ef7eb2e8f9f7 1806 #define EXTI_EMR_MR12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */
<> 144:ef7eb2e8f9f7 1807 #define EXTI_EMR_MR13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */
<> 144:ef7eb2e8f9f7 1808 #define EXTI_EMR_MR14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */
<> 144:ef7eb2e8f9f7 1809 #define EXTI_EMR_MR15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */
<> 144:ef7eb2e8f9f7 1810 #define EXTI_EMR_MR16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */
<> 144:ef7eb2e8f9f7 1811 #define EXTI_EMR_MR17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */
<> 144:ef7eb2e8f9f7 1812 #define EXTI_EMR_MR18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */
<> 144:ef7eb2e8f9f7 1813 #define EXTI_EMR_MR19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */
<> 144:ef7eb2e8f9f7 1814 #define EXTI_EMR_MR20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */
<> 144:ef7eb2e8f9f7 1815 #define EXTI_EMR_MR21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */
<> 144:ef7eb2e8f9f7 1816 #define EXTI_EMR_MR22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */
<> 144:ef7eb2e8f9f7 1817 #define EXTI_EMR_MR23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */
<> 144:ef7eb2e8f9f7 1818
<> 144:ef7eb2e8f9f7 1819 /* References Defines */
<> 144:ef7eb2e8f9f7 1820 #define EXTI_EMR_EM0 EXTI_EMR_MR0
<> 144:ef7eb2e8f9f7 1821 #define EXTI_EMR_EM1 EXTI_EMR_MR1
<> 144:ef7eb2e8f9f7 1822 #define EXTI_EMR_EM2 EXTI_EMR_MR2
<> 144:ef7eb2e8f9f7 1823 #define EXTI_EMR_EM3 EXTI_EMR_MR3
<> 144:ef7eb2e8f9f7 1824 #define EXTI_EMR_EM4 EXTI_EMR_MR4
<> 144:ef7eb2e8f9f7 1825 #define EXTI_EMR_EM5 EXTI_EMR_MR5
<> 144:ef7eb2e8f9f7 1826 #define EXTI_EMR_EM6 EXTI_EMR_MR6
<> 144:ef7eb2e8f9f7 1827 #define EXTI_EMR_EM7 EXTI_EMR_MR7
<> 144:ef7eb2e8f9f7 1828 #define EXTI_EMR_EM8 EXTI_EMR_MR8
<> 144:ef7eb2e8f9f7 1829 #define EXTI_EMR_EM9 EXTI_EMR_MR9
<> 144:ef7eb2e8f9f7 1830 #define EXTI_EMR_EM10 EXTI_EMR_MR10
<> 144:ef7eb2e8f9f7 1831 #define EXTI_EMR_EM11 EXTI_EMR_MR11
<> 144:ef7eb2e8f9f7 1832 #define EXTI_EMR_EM12 EXTI_EMR_MR12
<> 144:ef7eb2e8f9f7 1833 #define EXTI_EMR_EM13 EXTI_EMR_MR13
<> 144:ef7eb2e8f9f7 1834 #define EXTI_EMR_EM14 EXTI_EMR_MR14
<> 144:ef7eb2e8f9f7 1835 #define EXTI_EMR_EM15 EXTI_EMR_MR15
<> 144:ef7eb2e8f9f7 1836 #define EXTI_EMR_EM16 EXTI_EMR_MR16
<> 144:ef7eb2e8f9f7 1837 #define EXTI_EMR_EM17 EXTI_EMR_MR17
<> 144:ef7eb2e8f9f7 1838 #define EXTI_EMR_EM18 EXTI_EMR_MR18
<> 144:ef7eb2e8f9f7 1839 #define EXTI_EMR_EM19 EXTI_EMR_MR19
<> 144:ef7eb2e8f9f7 1840 #define EXTI_EMR_EM20 EXTI_EMR_MR20
<> 144:ef7eb2e8f9f7 1841 #define EXTI_EMR_EM21 EXTI_EMR_MR21
<> 144:ef7eb2e8f9f7 1842 #define EXTI_EMR_EM22 EXTI_EMR_MR22
<> 144:ef7eb2e8f9f7 1843 #define EXTI_EMR_EM23 EXTI_EMR_MR23
mbed_official 67:4bcbbb9fcddf 1844
mbed_official 67:4bcbbb9fcddf 1845 /****************** Bit definition for EXTI_RTSR register *******************/
<> 144:ef7eb2e8f9f7 1846 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */
<> 144:ef7eb2e8f9f7 1847 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */
<> 144:ef7eb2e8f9f7 1848 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */
<> 144:ef7eb2e8f9f7 1849 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */
<> 144:ef7eb2e8f9f7 1850 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */
<> 144:ef7eb2e8f9f7 1851 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */
<> 144:ef7eb2e8f9f7 1852 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */
<> 144:ef7eb2e8f9f7 1853 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */
<> 144:ef7eb2e8f9f7 1854 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */
<> 144:ef7eb2e8f9f7 1855 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */
<> 144:ef7eb2e8f9f7 1856 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */
<> 144:ef7eb2e8f9f7 1857 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */
<> 144:ef7eb2e8f9f7 1858 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */
<> 144:ef7eb2e8f9f7 1859 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */
<> 144:ef7eb2e8f9f7 1860 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */
<> 144:ef7eb2e8f9f7 1861 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */
<> 144:ef7eb2e8f9f7 1862 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */
<> 144:ef7eb2e8f9f7 1863 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */
<> 144:ef7eb2e8f9f7 1864 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000U) /*!< Rising trigger event configuration bit of line 18 */
<> 144:ef7eb2e8f9f7 1865 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */
<> 144:ef7eb2e8f9f7 1866 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */
<> 144:ef7eb2e8f9f7 1867 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */
<> 144:ef7eb2e8f9f7 1868 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 1869 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000U) /*!< Rising trigger event configuration bit of line 23 */
<> 144:ef7eb2e8f9f7 1870
<> 144:ef7eb2e8f9f7 1871 /* References Defines */
<> 144:ef7eb2e8f9f7 1872 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
<> 144:ef7eb2e8f9f7 1873 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
<> 144:ef7eb2e8f9f7 1874 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
<> 144:ef7eb2e8f9f7 1875 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
<> 144:ef7eb2e8f9f7 1876 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
<> 144:ef7eb2e8f9f7 1877 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
<> 144:ef7eb2e8f9f7 1878 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
<> 144:ef7eb2e8f9f7 1879 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
<> 144:ef7eb2e8f9f7 1880 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
<> 144:ef7eb2e8f9f7 1881 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
<> 144:ef7eb2e8f9f7 1882 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
<> 144:ef7eb2e8f9f7 1883 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
<> 144:ef7eb2e8f9f7 1884 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
<> 144:ef7eb2e8f9f7 1885 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
<> 144:ef7eb2e8f9f7 1886 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
<> 144:ef7eb2e8f9f7 1887 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
<> 144:ef7eb2e8f9f7 1888 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
<> 144:ef7eb2e8f9f7 1889 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
<> 144:ef7eb2e8f9f7 1890 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
<> 144:ef7eb2e8f9f7 1891 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
<> 144:ef7eb2e8f9f7 1892 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
<> 144:ef7eb2e8f9f7 1893 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
<> 144:ef7eb2e8f9f7 1894 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
<> 144:ef7eb2e8f9f7 1895 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23
mbed_official 67:4bcbbb9fcddf 1896
mbed_official 67:4bcbbb9fcddf 1897 /****************** Bit definition for EXTI_FTSR register *******************/
<> 144:ef7eb2e8f9f7 1898 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */
<> 144:ef7eb2e8f9f7 1899 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */
<> 144:ef7eb2e8f9f7 1900 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */
<> 144:ef7eb2e8f9f7 1901 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */
<> 144:ef7eb2e8f9f7 1902 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */
<> 144:ef7eb2e8f9f7 1903 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */
<> 144:ef7eb2e8f9f7 1904 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */
<> 144:ef7eb2e8f9f7 1905 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */
<> 144:ef7eb2e8f9f7 1906 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */
<> 144:ef7eb2e8f9f7 1907 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */
<> 144:ef7eb2e8f9f7 1908 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */
<> 144:ef7eb2e8f9f7 1909 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */
<> 144:ef7eb2e8f9f7 1910 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */
<> 144:ef7eb2e8f9f7 1911 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */
<> 144:ef7eb2e8f9f7 1912 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */
<> 144:ef7eb2e8f9f7 1913 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */
<> 144:ef7eb2e8f9f7 1914 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */
<> 144:ef7eb2e8f9f7 1915 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */
<> 144:ef7eb2e8f9f7 1916 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000U) /*!< Falling trigger event configuration bit of line 18 */
<> 144:ef7eb2e8f9f7 1917 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */
<> 144:ef7eb2e8f9f7 1918 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */
<> 144:ef7eb2e8f9f7 1919 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */
<> 144:ef7eb2e8f9f7 1920 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 1921 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000U) /*!< Falling trigger event configuration bit of line 23 */
<> 144:ef7eb2e8f9f7 1922
<> 144:ef7eb2e8f9f7 1923 /* References Defines */
<> 144:ef7eb2e8f9f7 1924 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
<> 144:ef7eb2e8f9f7 1925 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
<> 144:ef7eb2e8f9f7 1926 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
<> 144:ef7eb2e8f9f7 1927 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
<> 144:ef7eb2e8f9f7 1928 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
<> 144:ef7eb2e8f9f7 1929 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
<> 144:ef7eb2e8f9f7 1930 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
<> 144:ef7eb2e8f9f7 1931 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
<> 144:ef7eb2e8f9f7 1932 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
<> 144:ef7eb2e8f9f7 1933 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
<> 144:ef7eb2e8f9f7 1934 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
<> 144:ef7eb2e8f9f7 1935 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
<> 144:ef7eb2e8f9f7 1936 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
<> 144:ef7eb2e8f9f7 1937 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
<> 144:ef7eb2e8f9f7 1938 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
<> 144:ef7eb2e8f9f7 1939 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
<> 144:ef7eb2e8f9f7 1940 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
<> 144:ef7eb2e8f9f7 1941 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
<> 144:ef7eb2e8f9f7 1942 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
<> 144:ef7eb2e8f9f7 1943 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
<> 144:ef7eb2e8f9f7 1944 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
<> 144:ef7eb2e8f9f7 1945 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
<> 144:ef7eb2e8f9f7 1946 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
<> 144:ef7eb2e8f9f7 1947 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23
mbed_official 67:4bcbbb9fcddf 1948
mbed_official 67:4bcbbb9fcddf 1949 /****************** Bit definition for EXTI_SWIER register ******************/
<> 144:ef7eb2e8f9f7 1950 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */
<> 144:ef7eb2e8f9f7 1951 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */
<> 144:ef7eb2e8f9f7 1952 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */
<> 144:ef7eb2e8f9f7 1953 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */
<> 144:ef7eb2e8f9f7 1954 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */
<> 144:ef7eb2e8f9f7 1955 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */
<> 144:ef7eb2e8f9f7 1956 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */
<> 144:ef7eb2e8f9f7 1957 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */
<> 144:ef7eb2e8f9f7 1958 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */
<> 144:ef7eb2e8f9f7 1959 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */
<> 144:ef7eb2e8f9f7 1960 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */
<> 144:ef7eb2e8f9f7 1961 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */
<> 144:ef7eb2e8f9f7 1962 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */
<> 144:ef7eb2e8f9f7 1963 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */
<> 144:ef7eb2e8f9f7 1964 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */
<> 144:ef7eb2e8f9f7 1965 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */
<> 144:ef7eb2e8f9f7 1966 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */
<> 144:ef7eb2e8f9f7 1967 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */
<> 144:ef7eb2e8f9f7 1968 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000U) /*!< Software Interrupt on line 18 */
<> 144:ef7eb2e8f9f7 1969 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */
<> 144:ef7eb2e8f9f7 1970 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */
<> 144:ef7eb2e8f9f7 1971 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */
<> 144:ef7eb2e8f9f7 1972 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */
<> 144:ef7eb2e8f9f7 1973 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000U) /*!< Software Interrupt on line 23 */
<> 144:ef7eb2e8f9f7 1974
<> 144:ef7eb2e8f9f7 1975 /* References Defines */
<> 144:ef7eb2e8f9f7 1976 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
<> 144:ef7eb2e8f9f7 1977 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
<> 144:ef7eb2e8f9f7 1978 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
<> 144:ef7eb2e8f9f7 1979 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
<> 144:ef7eb2e8f9f7 1980 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
<> 144:ef7eb2e8f9f7 1981 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
<> 144:ef7eb2e8f9f7 1982 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
<> 144:ef7eb2e8f9f7 1983 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
<> 144:ef7eb2e8f9f7 1984 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
<> 144:ef7eb2e8f9f7 1985 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
<> 144:ef7eb2e8f9f7 1986 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
<> 144:ef7eb2e8f9f7 1987 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
<> 144:ef7eb2e8f9f7 1988 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
<> 144:ef7eb2e8f9f7 1989 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
<> 144:ef7eb2e8f9f7 1990 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
<> 144:ef7eb2e8f9f7 1991 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
<> 144:ef7eb2e8f9f7 1992 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
<> 144:ef7eb2e8f9f7 1993 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
<> 144:ef7eb2e8f9f7 1994 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
<> 144:ef7eb2e8f9f7 1995 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
<> 144:ef7eb2e8f9f7 1996 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
<> 144:ef7eb2e8f9f7 1997 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
<> 144:ef7eb2e8f9f7 1998 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
<> 144:ef7eb2e8f9f7 1999 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
mbed_official 67:4bcbbb9fcddf 2000
mbed_official 67:4bcbbb9fcddf 2001 /******************* Bit definition for EXTI_PR register ********************/
<> 144:ef7eb2e8f9f7 2002 #define EXTI_PR_PR0 ((uint32_t)0x00000001U) /*!< Pending bit for line 0 */
<> 144:ef7eb2e8f9f7 2003 #define EXTI_PR_PR1 ((uint32_t)0x00000002U) /*!< Pending bit for line 1 */
<> 144:ef7eb2e8f9f7 2004 #define EXTI_PR_PR2 ((uint32_t)0x00000004U) /*!< Pending bit for line 2 */
<> 144:ef7eb2e8f9f7 2005 #define EXTI_PR_PR3 ((uint32_t)0x00000008U) /*!< Pending bit for line 3 */
<> 144:ef7eb2e8f9f7 2006 #define EXTI_PR_PR4 ((uint32_t)0x00000010U) /*!< Pending bit for line 4 */
<> 144:ef7eb2e8f9f7 2007 #define EXTI_PR_PR5 ((uint32_t)0x00000020U) /*!< Pending bit for line 5 */
<> 144:ef7eb2e8f9f7 2008 #define EXTI_PR_PR6 ((uint32_t)0x00000040U) /*!< Pending bit for line 6 */
<> 144:ef7eb2e8f9f7 2009 #define EXTI_PR_PR7 ((uint32_t)0x00000080U) /*!< Pending bit for line 7 */
<> 144:ef7eb2e8f9f7 2010 #define EXTI_PR_PR8 ((uint32_t)0x00000100U) /*!< Pending bit for line 8 */
<> 144:ef7eb2e8f9f7 2011 #define EXTI_PR_PR9 ((uint32_t)0x00000200U) /*!< Pending bit for line 9 */
<> 144:ef7eb2e8f9f7 2012 #define EXTI_PR_PR10 ((uint32_t)0x00000400U) /*!< Pending bit for line 10 */
<> 144:ef7eb2e8f9f7 2013 #define EXTI_PR_PR11 ((uint32_t)0x00000800U) /*!< Pending bit for line 11 */
<> 144:ef7eb2e8f9f7 2014 #define EXTI_PR_PR12 ((uint32_t)0x00001000U) /*!< Pending bit for line 12 */
<> 144:ef7eb2e8f9f7 2015 #define EXTI_PR_PR13 ((uint32_t)0x00002000U) /*!< Pending bit for line 13 */
<> 144:ef7eb2e8f9f7 2016 #define EXTI_PR_PR14 ((uint32_t)0x00004000U) /*!< Pending bit for line 14 */
<> 144:ef7eb2e8f9f7 2017 #define EXTI_PR_PR15 ((uint32_t)0x00008000U) /*!< Pending bit for line 15 */
<> 144:ef7eb2e8f9f7 2018 #define EXTI_PR_PR16 ((uint32_t)0x00010000U) /*!< Pending bit for line 16 */
<> 144:ef7eb2e8f9f7 2019 #define EXTI_PR_PR17 ((uint32_t)0x00020000U) /*!< Pending bit for line 17 */
<> 144:ef7eb2e8f9f7 2020 #define EXTI_PR_PR18 ((uint32_t)0x00040000U) /*!< Pending bit for line 18 */
<> 144:ef7eb2e8f9f7 2021 #define EXTI_PR_PR19 ((uint32_t)0x00080000U) /*!< Pending bit for line 19 */
<> 144:ef7eb2e8f9f7 2022 #define EXTI_PR_PR20 ((uint32_t)0x00100000U) /*!< Pending bit for line 20 */
<> 144:ef7eb2e8f9f7 2023 #define EXTI_PR_PR21 ((uint32_t)0x00200000U) /*!< Pending bit for line 21 */
<> 144:ef7eb2e8f9f7 2024 #define EXTI_PR_PR22 ((uint32_t)0x00400000U) /*!< Pending bit for line 22 */
<> 144:ef7eb2e8f9f7 2025 #define EXTI_PR_PR23 ((uint32_t)0x00800000U) /*!< Pending bit for line 23 */
<> 144:ef7eb2e8f9f7 2026
<> 144:ef7eb2e8f9f7 2027 /* References Defines */
<> 144:ef7eb2e8f9f7 2028 #define EXTI_PR_PIF0 EXTI_PR_PR0
<> 144:ef7eb2e8f9f7 2029 #define EXTI_PR_PIF1 EXTI_PR_PR1
<> 144:ef7eb2e8f9f7 2030 #define EXTI_PR_PIF2 EXTI_PR_PR2
<> 144:ef7eb2e8f9f7 2031 #define EXTI_PR_PIF3 EXTI_PR_PR3
<> 144:ef7eb2e8f9f7 2032 #define EXTI_PR_PIF4 EXTI_PR_PR4
<> 144:ef7eb2e8f9f7 2033 #define EXTI_PR_PIF5 EXTI_PR_PR5
<> 144:ef7eb2e8f9f7 2034 #define EXTI_PR_PIF6 EXTI_PR_PR6
<> 144:ef7eb2e8f9f7 2035 #define EXTI_PR_PIF7 EXTI_PR_PR7
<> 144:ef7eb2e8f9f7 2036 #define EXTI_PR_PIF8 EXTI_PR_PR8
<> 144:ef7eb2e8f9f7 2037 #define EXTI_PR_PIF9 EXTI_PR_PR9
<> 144:ef7eb2e8f9f7 2038 #define EXTI_PR_PIF10 EXTI_PR_PR10
<> 144:ef7eb2e8f9f7 2039 #define EXTI_PR_PIF11 EXTI_PR_PR11
<> 144:ef7eb2e8f9f7 2040 #define EXTI_PR_PIF12 EXTI_PR_PR12
<> 144:ef7eb2e8f9f7 2041 #define EXTI_PR_PIF13 EXTI_PR_PR13
<> 144:ef7eb2e8f9f7 2042 #define EXTI_PR_PIF14 EXTI_PR_PR14
<> 144:ef7eb2e8f9f7 2043 #define EXTI_PR_PIF15 EXTI_PR_PR15
<> 144:ef7eb2e8f9f7 2044 #define EXTI_PR_PIF16 EXTI_PR_PR16
<> 144:ef7eb2e8f9f7 2045 #define EXTI_PR_PIF17 EXTI_PR_PR17
<> 144:ef7eb2e8f9f7 2046 #define EXTI_PR_PIF18 EXTI_PR_PR18
<> 144:ef7eb2e8f9f7 2047 #define EXTI_PR_PIF19 EXTI_PR_PR19
<> 144:ef7eb2e8f9f7 2048 #define EXTI_PR_PIF20 EXTI_PR_PR20
<> 144:ef7eb2e8f9f7 2049 #define EXTI_PR_PIF21 EXTI_PR_PR21
<> 144:ef7eb2e8f9f7 2050 #define EXTI_PR_PIF22 EXTI_PR_PR22
<> 144:ef7eb2e8f9f7 2051 #define EXTI_PR_PIF23 EXTI_PR_PR23
mbed_official 67:4bcbbb9fcddf 2052
mbed_official 67:4bcbbb9fcddf 2053 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 2054 /* */
mbed_official 67:4bcbbb9fcddf 2055 /* FLASH, DATA EEPROM and Option Bytes Registers */
mbed_official 67:4bcbbb9fcddf 2056 /* (FLASH, DATA_EEPROM, OB) */
mbed_official 67:4bcbbb9fcddf 2057 /* */
mbed_official 67:4bcbbb9fcddf 2058 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 2059
mbed_official 67:4bcbbb9fcddf 2060 /******************* Bit definition for FLASH_ACR register ******************/
<> 144:ef7eb2e8f9f7 2061 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< Latency */
<> 144:ef7eb2e8f9f7 2062 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /*!< Prefetch Buffer Enable */
<> 144:ef7eb2e8f9f7 2063 #define FLASH_ACR_ACC64 ((uint32_t)0x00000004U) /*!< Access 64 bits */
<> 144:ef7eb2e8f9f7 2064 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /*!< Flash mode during sleep mode */
<> 144:ef7eb2e8f9f7 2065 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /*!< Flash mode during RUN mode */
mbed_official 67:4bcbbb9fcddf 2066
mbed_official 67:4bcbbb9fcddf 2067 /******************* Bit definition for FLASH_PECR register ******************/
<> 144:ef7eb2e8f9f7 2068 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /*!< FLASH_PECR and Flash data Lock */
<> 144:ef7eb2e8f9f7 2069 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /*!< Program matrix Lock */
<> 144:ef7eb2e8f9f7 2070 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /*!< Option byte matrix Lock */
<> 144:ef7eb2e8f9f7 2071 #define FLASH_PECR_PROG ((uint32_t)0x00000008U) /*!< Program matrix selection */
<> 144:ef7eb2e8f9f7 2072 #define FLASH_PECR_DATA ((uint32_t)0x00000010U) /*!< Data matrix selection */
<> 144:ef7eb2e8f9f7 2073 #define FLASH_PECR_FTDW ((uint32_t)0x00000100U) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
<> 144:ef7eb2e8f9f7 2074 #define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /*!< Page erasing mode */
<> 144:ef7eb2e8f9f7 2075 #define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /*!< Fast Page/Half Page programming mode */
<> 144:ef7eb2e8f9f7 2076 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /*!< End of programming interrupt */
<> 144:ef7eb2e8f9f7 2077 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /*!< Error interrupt */
<> 144:ef7eb2e8f9f7 2078 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /*!< Launch the option byte loading */
mbed_official 67:4bcbbb9fcddf 2079
mbed_official 67:4bcbbb9fcddf 2080 /****************** Bit definition for FLASH_PDKEYR register ******************/
<> 144:ef7eb2e8f9f7 2081 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
mbed_official 67:4bcbbb9fcddf 2082
mbed_official 67:4bcbbb9fcddf 2083 /****************** Bit definition for FLASH_PEKEYR register ******************/
<> 144:ef7eb2e8f9f7 2084 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
mbed_official 67:4bcbbb9fcddf 2085
mbed_official 67:4bcbbb9fcddf 2086 /****************** Bit definition for FLASH_PRGKEYR register ******************/
<> 144:ef7eb2e8f9f7 2087 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /*!< Program matrix Key */
mbed_official 67:4bcbbb9fcddf 2088
mbed_official 67:4bcbbb9fcddf 2089 /****************** Bit definition for FLASH_OPTKEYR register ******************/
<> 144:ef7eb2e8f9f7 2090 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option bytes matrix Key */
mbed_official 67:4bcbbb9fcddf 2091
mbed_official 67:4bcbbb9fcddf 2092 /****************** Bit definition for FLASH_SR register *******************/
<> 144:ef7eb2e8f9f7 2093 #define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */
<> 144:ef7eb2e8f9f7 2094 #define FLASH_SR_EOP ((uint32_t)0x00000002U) /*!< End Of Programming*/
<> 144:ef7eb2e8f9f7 2095 #define FLASH_SR_ENDHV ((uint32_t)0x00000004U) /*!< End of high voltage */
<> 144:ef7eb2e8f9f7 2096 #define FLASH_SR_READY ((uint32_t)0x00000008U) /*!< Flash ready after low power mode */
<> 144:ef7eb2e8f9f7 2097
<> 144:ef7eb2e8f9f7 2098 #define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /*!< Write protected error */
<> 144:ef7eb2e8f9f7 2099 #define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /*!< Programming Alignment Error */
<> 144:ef7eb2e8f9f7 2100 #define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /*!< Size error */
<> 144:ef7eb2e8f9f7 2101 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /*!< Option validity error */
<> 144:ef7eb2e8f9f7 2102 #define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000U) /*!< Option User validity error */
<> 144:ef7eb2e8f9f7 2103 #define FLASH_SR_RDERR ((uint32_t)0x00002000U) /*!< Read protected error */
mbed_official 67:4bcbbb9fcddf 2104
mbed_official 67:4bcbbb9fcddf 2105 /****************** Bit definition for FLASH_OBR register *******************/
<> 144:ef7eb2e8f9f7 2106 #define FLASH_OBR_RDPRT ((uint32_t)0x000000FFU) /*!< Read Protection */
<> 144:ef7eb2e8f9f7 2107 #define FLASH_OBR_SPRMOD ((uint32_t)0x00000100U) /*!< Selection of protection mode of WPRi bits */
<> 144:ef7eb2e8f9f7 2108 #define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000U) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
<> 144:ef7eb2e8f9f7 2109 #define FLASH_OBR_USER ((uint32_t)0x00700000U) /*!< User Option Bytes */
<> 144:ef7eb2e8f9f7 2110 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000U) /*!< IWDG_SW */
<> 144:ef7eb2e8f9f7 2111 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000U) /*!< nRST_STOP */
<> 144:ef7eb2e8f9f7 2112 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000U) /*!< nRST_STDBY */
mbed_official 67:4bcbbb9fcddf 2113
mbed_official 67:4bcbbb9fcddf 2114 /****************** Bit definition for FLASH_WRPR register ******************/
<> 144:ef7eb2e8f9f7 2115 #define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFFU) /*!< Write Protect sectors 0 to 31 */
<> 144:ef7eb2e8f9f7 2116 #define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFFU) /*!< Write Protect sectors 32 to 63 */
mbed_official 67:4bcbbb9fcddf 2117
mbed_official 67:4bcbbb9fcddf 2118 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 2119 /* */
mbed_official 67:4bcbbb9fcddf 2120 /* General Purpose I/O */
mbed_official 67:4bcbbb9fcddf 2121 /* */
mbed_official 67:4bcbbb9fcddf 2122 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 2123 /****************** Bits definition for GPIO_MODER register *****************/
<> 144:ef7eb2e8f9f7 2124 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003U)
<> 144:ef7eb2e8f9f7 2125 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 2126 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 2127
<> 144:ef7eb2e8f9f7 2128 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000CU)
<> 144:ef7eb2e8f9f7 2129 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 2130 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 2131
<> 144:ef7eb2e8f9f7 2132 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030U)
<> 144:ef7eb2e8f9f7 2133 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 2134 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 2135
<> 144:ef7eb2e8f9f7 2136 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0U)
<> 144:ef7eb2e8f9f7 2137 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 2138 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 2139
<> 144:ef7eb2e8f9f7 2140 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300U)
<> 144:ef7eb2e8f9f7 2141 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 2142 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 2143
<> 144:ef7eb2e8f9f7 2144 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00U)
<> 144:ef7eb2e8f9f7 2145 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 2146 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 2147
<> 144:ef7eb2e8f9f7 2148 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000U)
<> 144:ef7eb2e8f9f7 2149 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 2150 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 2151
<> 144:ef7eb2e8f9f7 2152 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000U)
<> 144:ef7eb2e8f9f7 2153 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 2154 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 2155
<> 144:ef7eb2e8f9f7 2156 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000U)
<> 144:ef7eb2e8f9f7 2157 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 2158 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 2159
<> 144:ef7eb2e8f9f7 2160 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000U)
<> 144:ef7eb2e8f9f7 2161 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 2162 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 2163
<> 144:ef7eb2e8f9f7 2164 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000U)
<> 144:ef7eb2e8f9f7 2165 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 2166 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 2167
<> 144:ef7eb2e8f9f7 2168 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000U)
<> 144:ef7eb2e8f9f7 2169 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 2170 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 2171
<> 144:ef7eb2e8f9f7 2172 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000U)
<> 144:ef7eb2e8f9f7 2173 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 2174 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 2175
<> 144:ef7eb2e8f9f7 2176 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000U)
<> 144:ef7eb2e8f9f7 2177 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 2178 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 2179
<> 144:ef7eb2e8f9f7 2180 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000U)
<> 144:ef7eb2e8f9f7 2181 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 2182 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 2183
<> 144:ef7eb2e8f9f7 2184 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000U)
<> 144:ef7eb2e8f9f7 2185 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000U)
<> 144:ef7eb2e8f9f7 2186 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000U)
mbed_official 67:4bcbbb9fcddf 2187
mbed_official 67:4bcbbb9fcddf 2188 /****************** Bits definition for GPIO_OTYPER register ****************/
<> 144:ef7eb2e8f9f7 2189 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 2190 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 2191 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 2192 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 2193 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 2194 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 2195 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 2196 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 2197 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 2198 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 2199 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 2200 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 2201 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 2202 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 2203 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 2204 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U)
mbed_official 67:4bcbbb9fcddf 2205
mbed_official 67:4bcbbb9fcddf 2206 /****************** Bits definition for GPIO_OSPEEDR register ***************/
<> 144:ef7eb2e8f9f7 2207 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003U)
<> 144:ef7eb2e8f9f7 2208 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 2209 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 2210
<> 144:ef7eb2e8f9f7 2211 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000CU)
<> 144:ef7eb2e8f9f7 2212 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 2213 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 2214
<> 144:ef7eb2e8f9f7 2215 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030U)
<> 144:ef7eb2e8f9f7 2216 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 2217 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 2218
<> 144:ef7eb2e8f9f7 2219 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0U)
<> 144:ef7eb2e8f9f7 2220 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 2221 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 2222
<> 144:ef7eb2e8f9f7 2223 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300U)
<> 144:ef7eb2e8f9f7 2224 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 2225 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 2226
<> 144:ef7eb2e8f9f7 2227 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00U)
<> 144:ef7eb2e8f9f7 2228 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 2229 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 2230
<> 144:ef7eb2e8f9f7 2231 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000U)
<> 144:ef7eb2e8f9f7 2232 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 2233 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 2234
<> 144:ef7eb2e8f9f7 2235 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000U)
<> 144:ef7eb2e8f9f7 2236 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 2237 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 2238
<> 144:ef7eb2e8f9f7 2239 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000U)
<> 144:ef7eb2e8f9f7 2240 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 2241 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 2242
<> 144:ef7eb2e8f9f7 2243 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000U)
<> 144:ef7eb2e8f9f7 2244 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 2245 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 2246
<> 144:ef7eb2e8f9f7 2247 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000U)
<> 144:ef7eb2e8f9f7 2248 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 2249 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 2250
<> 144:ef7eb2e8f9f7 2251 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000U)
<> 144:ef7eb2e8f9f7 2252 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 2253 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 2254
<> 144:ef7eb2e8f9f7 2255 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000U)
<> 144:ef7eb2e8f9f7 2256 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 2257 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 2258
<> 144:ef7eb2e8f9f7 2259 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000U)
<> 144:ef7eb2e8f9f7 2260 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 2261 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 2262
<> 144:ef7eb2e8f9f7 2263 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000U)
<> 144:ef7eb2e8f9f7 2264 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 2265 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 2266
<> 144:ef7eb2e8f9f7 2267 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000U)
<> 144:ef7eb2e8f9f7 2268 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000U)
<> 144:ef7eb2e8f9f7 2269 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000U)
mbed_official 67:4bcbbb9fcddf 2270
mbed_official 67:4bcbbb9fcddf 2271 /****************** Bits definition for GPIO_PUPDR register *****************/
<> 144:ef7eb2e8f9f7 2272 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003U)
<> 144:ef7eb2e8f9f7 2273 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 2274 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 2275
<> 144:ef7eb2e8f9f7 2276 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000CU)
<> 144:ef7eb2e8f9f7 2277 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 2278 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 2279
<> 144:ef7eb2e8f9f7 2280 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030U)
<> 144:ef7eb2e8f9f7 2281 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 2282 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 2283
<> 144:ef7eb2e8f9f7 2284 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0U)
<> 144:ef7eb2e8f9f7 2285 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 2286 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 2287
<> 144:ef7eb2e8f9f7 2288 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300U)
<> 144:ef7eb2e8f9f7 2289 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 2290 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 2291
<> 144:ef7eb2e8f9f7 2292 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00U)
<> 144:ef7eb2e8f9f7 2293 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 2294 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 2295
<> 144:ef7eb2e8f9f7 2296 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000U)
<> 144:ef7eb2e8f9f7 2297 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 2298 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 2299
<> 144:ef7eb2e8f9f7 2300 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000U)
<> 144:ef7eb2e8f9f7 2301 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 2302 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 2303
<> 144:ef7eb2e8f9f7 2304 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000U)
<> 144:ef7eb2e8f9f7 2305 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 2306 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 2307
<> 144:ef7eb2e8f9f7 2308 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000U)
<> 144:ef7eb2e8f9f7 2309 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 2310 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 2311
<> 144:ef7eb2e8f9f7 2312 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000U)
<> 144:ef7eb2e8f9f7 2313 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 2314 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 2315
<> 144:ef7eb2e8f9f7 2316 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000U)
<> 144:ef7eb2e8f9f7 2317 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 2318 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 2319
<> 144:ef7eb2e8f9f7 2320 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000U)
<> 144:ef7eb2e8f9f7 2321 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 2322 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 2323
<> 144:ef7eb2e8f9f7 2324 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000U)
<> 144:ef7eb2e8f9f7 2325 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 2326 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 2327
<> 144:ef7eb2e8f9f7 2328 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000U)
<> 144:ef7eb2e8f9f7 2329 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 2330 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 2331 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000U)
<> 144:ef7eb2e8f9f7 2332 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000U)
<> 144:ef7eb2e8f9f7 2333 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000U)
mbed_official 67:4bcbbb9fcddf 2334
mbed_official 67:4bcbbb9fcddf 2335 /****************** Bits definition for GPIO_IDR register *******************/
<> 144:ef7eb2e8f9f7 2336 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 2337 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 2338 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 2339 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 2340 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 2341 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 2342 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 2343 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 2344 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 2345 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 2346 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 2347 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 2348 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 2349 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 2350 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 2351 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000U)
mbed_official 67:4bcbbb9fcddf 2352
mbed_official 67:4bcbbb9fcddf 2353 /****************** Bits definition for GPIO_ODR register *******************/
<> 144:ef7eb2e8f9f7 2354 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 2355 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 2356 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 2357 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 2358 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 2359 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 2360 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 2361 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 2362 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 2363 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 2364 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 2365 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 2366 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 2367 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 2368 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 2369 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000U)
mbed_official 67:4bcbbb9fcddf 2370
mbed_official 67:4bcbbb9fcddf 2371 /****************** Bits definition for GPIO_BSRR register ******************/
<> 144:ef7eb2e8f9f7 2372 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 2373 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 2374 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 2375 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 2376 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 2377 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 2378 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 2379 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 2380 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 2381 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 2382 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 2383 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 2384 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 2385 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 2386 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 2387 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 2388 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 2389 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 2390 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 2391 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 2392 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 2393 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 2394 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 2395 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 2396 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 2397 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 2398 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 2399 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 2400 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 2401 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 2402 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U)
<> 144:ef7eb2e8f9f7 2403 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U)
mbed_official 67:4bcbbb9fcddf 2404
mbed_official 67:4bcbbb9fcddf 2405 /****************** Bit definition for GPIO_LCKR register ********************/
<> 144:ef7eb2e8f9f7 2406 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 2407 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 2408 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 2409 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 2410 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 2411 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 2412 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 2413 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 2414 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 2415 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 2416 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 2417 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 2418 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 2419 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 2420 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 2421 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 2422 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
mbed_official 67:4bcbbb9fcddf 2423
mbed_official 67:4bcbbb9fcddf 2424 /****************** Bit definition for GPIO_AFRL register ********************/
<> 144:ef7eb2e8f9f7 2425 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU)
<> 144:ef7eb2e8f9f7 2426 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U)
<> 144:ef7eb2e8f9f7 2427 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U)
<> 144:ef7eb2e8f9f7 2428 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U)
<> 144:ef7eb2e8f9f7 2429 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U)
<> 144:ef7eb2e8f9f7 2430 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U)
<> 144:ef7eb2e8f9f7 2431 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U)
<> 144:ef7eb2e8f9f7 2432 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U)
mbed_official 67:4bcbbb9fcddf 2433
mbed_official 67:4bcbbb9fcddf 2434 /****************** Bit definition for GPIO_AFRH register ********************/
<> 144:ef7eb2e8f9f7 2435 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU)
<> 144:ef7eb2e8f9f7 2436 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U)
<> 144:ef7eb2e8f9f7 2437 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U)
<> 144:ef7eb2e8f9f7 2438 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U)
<> 144:ef7eb2e8f9f7 2439 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U)
<> 144:ef7eb2e8f9f7 2440 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U)
<> 144:ef7eb2e8f9f7 2441 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U)
<> 144:ef7eb2e8f9f7 2442 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U)
mbed_official 67:4bcbbb9fcddf 2443
mbed_official 67:4bcbbb9fcddf 2444 /****************** Bit definition for GPIO_BRR register *********************/
<> 144:ef7eb2e8f9f7 2445 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 2446 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 2447 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 2448 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 2449 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 2450 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 2451 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 2452 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 2453 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 2454 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 2455 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 2456 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 2457 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 2458 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 2459 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 2460 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000U)
mbed_official 67:4bcbbb9fcddf 2461
mbed_official 67:4bcbbb9fcddf 2462 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 2463 /* */
mbed_official 67:4bcbbb9fcddf 2464 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 67:4bcbbb9fcddf 2465 /* */
mbed_official 67:4bcbbb9fcddf 2466 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 2467
mbed_official 67:4bcbbb9fcddf 2468 /******************* Bit definition for I2C_CR1 register ********************/
<> 144:ef7eb2e8f9f7 2469 #define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral Enable */
<> 144:ef7eb2e8f9f7 2470 #define I2C_CR1_SMBUS ((uint32_t)0x00000002U) /*!< SMBus Mode */
<> 144:ef7eb2e8f9f7 2471 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008U) /*!< SMBus Type */
<> 144:ef7eb2e8f9f7 2472 #define I2C_CR1_ENARP ((uint32_t)0x00000010U) /*!< ARP Enable */
<> 144:ef7eb2e8f9f7 2473 #define I2C_CR1_ENPEC ((uint32_t)0x00000020U) /*!< PEC Enable */
<> 144:ef7eb2e8f9f7 2474 #define I2C_CR1_ENGC ((uint32_t)0x00000040U) /*!< General Call Enable */
<> 144:ef7eb2e8f9f7 2475 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080U) /*!< Clock Stretching Disable (Slave mode) */
<> 144:ef7eb2e8f9f7 2476 #define I2C_CR1_START ((uint32_t)0x00000100U) /*!< Start Generation */
<> 144:ef7eb2e8f9f7 2477 #define I2C_CR1_STOP ((uint32_t)0x00000200U) /*!< Stop Generation */
<> 144:ef7eb2e8f9f7 2478 #define I2C_CR1_ACK ((uint32_t)0x00000400U) /*!< Acknowledge Enable */
<> 144:ef7eb2e8f9f7 2479 #define I2C_CR1_POS ((uint32_t)0x00000800U) /*!< Acknowledge/PEC Position (for data reception) */
<> 144:ef7eb2e8f9f7 2480 #define I2C_CR1_PEC ((uint32_t)0x00001000U) /*!< Packet Error Checking */
<> 144:ef7eb2e8f9f7 2481 #define I2C_CR1_ALERT ((uint32_t)0x00002000U) /*!< SMBus Alert */
<> 144:ef7eb2e8f9f7 2482 #define I2C_CR1_SWRST ((uint32_t)0x00008000U) /*!< Software Reset */
mbed_official 67:4bcbbb9fcddf 2483
mbed_official 67:4bcbbb9fcddf 2484 /******************* Bit definition for I2C_CR2 register ********************/
<> 144:ef7eb2e8f9f7 2485 #define I2C_CR2_FREQ ((uint32_t)0x0000003FU) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
<> 144:ef7eb2e8f9f7 2486 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2487 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2488 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 2489 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 2490 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 2491 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 2492
<> 144:ef7eb2e8f9f7 2493 #define I2C_CR2_ITERREN ((uint32_t)0x00000100U) /*!< Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 2494 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200U) /*!< Event Interrupt Enable */
<> 144:ef7eb2e8f9f7 2495 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400U) /*!< Buffer Interrupt Enable */
<> 144:ef7eb2e8f9f7 2496 #define I2C_CR2_DMAEN ((uint32_t)0x00000800U) /*!< DMA Requests Enable */
<> 144:ef7eb2e8f9f7 2497 #define I2C_CR2_LAST ((uint32_t)0x00001000U) /*!< DMA Last Transfer */
mbed_official 67:4bcbbb9fcddf 2498
mbed_official 67:4bcbbb9fcddf 2499 /******************* Bit definition for I2C_OAR1 register *******************/
<> 144:ef7eb2e8f9f7 2500 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FEU) /*!< Interface Address */
<> 144:ef7eb2e8f9f7 2501 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300U) /*!< Interface Address */
<> 144:ef7eb2e8f9f7 2502
<> 144:ef7eb2e8f9f7 2503 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2504 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2505 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 2506 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 2507 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 2508 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 2509 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 2510 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 2511 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 2512 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 2513
<> 144:ef7eb2e8f9f7 2514 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000U) /*!< Addressing Mode (Slave mode) */
mbed_official 67:4bcbbb9fcddf 2515
mbed_official 67:4bcbbb9fcddf 2516 /******************* Bit definition for I2C_OAR2 register *******************/
<> 144:ef7eb2e8f9f7 2517 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001U) /*!< Dual addressing mode enable */
<> 144:ef7eb2e8f9f7 2518 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FEU) /*!< Interface address */
mbed_official 67:4bcbbb9fcddf 2519
mbed_official 67:4bcbbb9fcddf 2520 /******************** Bit definition for I2C_DR register ********************/
<> 144:ef7eb2e8f9f7 2521 #define I2C_DR_DR ((uint32_t)0x000000FFU) /*!< 8-bit Data Register */
mbed_official 67:4bcbbb9fcddf 2522
mbed_official 67:4bcbbb9fcddf 2523 /******************* Bit definition for I2C_SR1 register ********************/
<> 144:ef7eb2e8f9f7 2524 #define I2C_SR1_SB ((uint32_t)0x00000001U) /*!< Start Bit (Master mode) */
<> 144:ef7eb2e8f9f7 2525 #define I2C_SR1_ADDR ((uint32_t)0x00000002U) /*!< Address sent (master mode)/matched (slave mode) */
<> 144:ef7eb2e8f9f7 2526 #define I2C_SR1_BTF ((uint32_t)0x00000004U) /*!< Byte Transfer Finished */
<> 144:ef7eb2e8f9f7 2527 #define I2C_SR1_ADD10 ((uint32_t)0x00000008U) /*!< 10-bit header sent (Master mode) */
<> 144:ef7eb2e8f9f7 2528 #define I2C_SR1_STOPF ((uint32_t)0x00000010U) /*!< Stop detection (Slave mode) */
<> 144:ef7eb2e8f9f7 2529 #define I2C_SR1_RXNE ((uint32_t)0x00000040U) /*!< Data Register not Empty (receivers) */
<> 144:ef7eb2e8f9f7 2530 #define I2C_SR1_TXE ((uint32_t)0x00000080U) /*!< Data Register Empty (transmitters) */
<> 144:ef7eb2e8f9f7 2531 #define I2C_SR1_BERR ((uint32_t)0x00000100U) /*!< Bus Error */
<> 144:ef7eb2e8f9f7 2532 #define I2C_SR1_ARLO ((uint32_t)0x00000200U) /*!< Arbitration Lost (master mode) */
<> 144:ef7eb2e8f9f7 2533 #define I2C_SR1_AF ((uint32_t)0x00000400U) /*!< Acknowledge Failure */
<> 144:ef7eb2e8f9f7 2534 #define I2C_SR1_OVR ((uint32_t)0x00000800U) /*!< Overrun/Underrun */
<> 144:ef7eb2e8f9f7 2535 #define I2C_SR1_PECERR ((uint32_t)0x00001000U) /*!< PEC Error in reception */
<> 144:ef7eb2e8f9f7 2536 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000U) /*!< Timeout or Tlow Error */
<> 144:ef7eb2e8f9f7 2537 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000U) /*!< SMBus Alert */
mbed_official 67:4bcbbb9fcddf 2538
mbed_official 67:4bcbbb9fcddf 2539 /******************* Bit definition for I2C_SR2 register ********************/
<> 144:ef7eb2e8f9f7 2540 #define I2C_SR2_MSL ((uint32_t)0x00000001U) /*!< Master/Slave */
<> 144:ef7eb2e8f9f7 2541 #define I2C_SR2_BUSY ((uint32_t)0x00000002U) /*!< Bus Busy */
<> 144:ef7eb2e8f9f7 2542 #define I2C_SR2_TRA ((uint32_t)0x00000004U) /*!< Transmitter/Receiver */
<> 144:ef7eb2e8f9f7 2543 #define I2C_SR2_GENCALL ((uint32_t)0x00000010U) /*!< General Call Address (Slave mode) */
<> 144:ef7eb2e8f9f7 2544 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020U) /*!< SMBus Device Default Address (Slave mode) */
<> 144:ef7eb2e8f9f7 2545 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040U) /*!< SMBus Host Header (Slave mode) */
<> 144:ef7eb2e8f9f7 2546 #define I2C_SR2_DUALF ((uint32_t)0x00000080U) /*!< Dual Flag (Slave mode) */
<> 144:ef7eb2e8f9f7 2547 #define I2C_SR2_PEC ((uint32_t)0x0000FF00U) /*!< Packet Error Checking Register */
mbed_official 67:4bcbbb9fcddf 2548
mbed_official 67:4bcbbb9fcddf 2549 /******************* Bit definition for I2C_CCR register ********************/
<> 144:ef7eb2e8f9f7 2550 #define I2C_CCR_CCR ((uint32_t)0x00000FFFU) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
<> 144:ef7eb2e8f9f7 2551 #define I2C_CCR_DUTY ((uint32_t)0x00004000U) /*!< Fast Mode Duty Cycle */
<> 144:ef7eb2e8f9f7 2552 #define I2C_CCR_FS ((uint32_t)0x00008000U) /*!< I2C Master Mode Selection */
mbed_official 67:4bcbbb9fcddf 2553
mbed_official 67:4bcbbb9fcddf 2554 /****************** Bit definition for I2C_TRISE register *******************/
<> 144:ef7eb2e8f9f7 2555 #define I2C_TRISE_TRISE ((uint32_t)0x0000003FU) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
mbed_official 67:4bcbbb9fcddf 2556
mbed_official 67:4bcbbb9fcddf 2557 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 2558 /* */
mbed_official 67:4bcbbb9fcddf 2559 /* Independent WATCHDOG (IWDG) */
mbed_official 67:4bcbbb9fcddf 2560 /* */
mbed_official 67:4bcbbb9fcddf 2561 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 2562
mbed_official 67:4bcbbb9fcddf 2563 /******************* Bit definition for IWDG_KR register ********************/
<> 144:ef7eb2e8f9f7 2564 #define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!< Key value (write only, read 0000h) */
mbed_official 67:4bcbbb9fcddf 2565
mbed_official 67:4bcbbb9fcddf 2566 /******************* Bit definition for IWDG_PR register ********************/
<> 144:ef7eb2e8f9f7 2567 #define IWDG_PR_PR ((uint32_t)0x00000007U) /*!< PR[2:0] (Prescaler divider) */
<> 144:ef7eb2e8f9f7 2568 #define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2569 #define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2570 #define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
mbed_official 67:4bcbbb9fcddf 2571
mbed_official 67:4bcbbb9fcddf 2572 /******************* Bit definition for IWDG_RLR register *******************/
<> 144:ef7eb2e8f9f7 2573 #define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!< Watchdog counter reload value */
mbed_official 67:4bcbbb9fcddf 2574
mbed_official 67:4bcbbb9fcddf 2575 /******************* Bit definition for IWDG_SR register ********************/
<> 144:ef7eb2e8f9f7 2576 #define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */
<> 144:ef7eb2e8f9f7 2577 #define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */
mbed_official 67:4bcbbb9fcddf 2578
mbed_official 67:4bcbbb9fcddf 2579 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 2580 /* */
mbed_official 67:4bcbbb9fcddf 2581 /* Power Control (PWR) */
mbed_official 67:4bcbbb9fcddf 2582 /* */
mbed_official 67:4bcbbb9fcddf 2583 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 2584
<> 144:ef7eb2e8f9f7 2585 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
<> 144:ef7eb2e8f9f7 2586
mbed_official 67:4bcbbb9fcddf 2587 /******************** Bit definition for PWR_CR register ********************/
<> 144:ef7eb2e8f9f7 2588 #define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /*!< Low-power deepsleep/sleep/low power run */
<> 144:ef7eb2e8f9f7 2589 #define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */
<> 144:ef7eb2e8f9f7 2590 #define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */
<> 144:ef7eb2e8f9f7 2591 #define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */
<> 144:ef7eb2e8f9f7 2592 #define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */
<> 144:ef7eb2e8f9f7 2593
<> 144:ef7eb2e8f9f7 2594 #define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */
<> 144:ef7eb2e8f9f7 2595 #define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2596 #define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2597 #define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
mbed_official 67:4bcbbb9fcddf 2598
mbed_official 67:4bcbbb9fcddf 2599 /*!< PVD level configuration */
<> 144:ef7eb2e8f9f7 2600 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */
<> 144:ef7eb2e8f9f7 2601 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */
<> 144:ef7eb2e8f9f7 2602 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */
<> 144:ef7eb2e8f9f7 2603 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */
<> 144:ef7eb2e8f9f7 2604 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */
<> 144:ef7eb2e8f9f7 2605 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */
<> 144:ef7eb2e8f9f7 2606 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */
<> 144:ef7eb2e8f9f7 2607 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */
<> 144:ef7eb2e8f9f7 2608
<> 144:ef7eb2e8f9f7 2609 #define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */
<> 144:ef7eb2e8f9f7 2610 #define PWR_CR_ULP ((uint32_t)0x00000200U) /*!< Ultra Low Power mode */
<> 144:ef7eb2e8f9f7 2611 #define PWR_CR_FWU ((uint32_t)0x00000400U) /*!< Fast wakeup */
<> 144:ef7eb2e8f9f7 2612
<> 144:ef7eb2e8f9f7 2613 #define PWR_CR_VOS ((uint32_t)0x00001800U) /*!< VOS[1:0] bits (Voltage scaling range selection) */
<> 144:ef7eb2e8f9f7 2614 #define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2615 #define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2616 #define PWR_CR_LPRUN ((uint32_t)0x00004000U) /*!< Low power run mode */
mbed_official 67:4bcbbb9fcddf 2617
mbed_official 67:4bcbbb9fcddf 2618 /******************* Bit definition for PWR_CSR register ********************/
<> 144:ef7eb2e8f9f7 2619 #define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */
<> 144:ef7eb2e8f9f7 2620 #define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */
<> 144:ef7eb2e8f9f7 2621 #define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */
<> 144:ef7eb2e8f9f7 2622 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */
<> 144:ef7eb2e8f9f7 2623 #define PWR_CSR_VOSF ((uint32_t)0x00000010U) /*!< Voltage Scaling select flag */
<> 144:ef7eb2e8f9f7 2624 #define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /*!< Regulator LP flag */
<> 144:ef7eb2e8f9f7 2625
<> 144:ef7eb2e8f9f7 2626 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */
<> 144:ef7eb2e8f9f7 2627 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */
<> 144:ef7eb2e8f9f7 2628 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400U) /*!< Enable WKUP pin 3 */
mbed_official 67:4bcbbb9fcddf 2629
mbed_official 67:4bcbbb9fcddf 2630 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 2631 /* */
mbed_official 67:4bcbbb9fcddf 2632 /* Reset and Clock Control (RCC) */
mbed_official 67:4bcbbb9fcddf 2633 /* */
mbed_official 67:4bcbbb9fcddf 2634 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2635 /*
<> 144:ef7eb2e8f9f7 2636 * @brief Specific device feature definitions (not present on all devices in the STM32F0 family)
<> 144:ef7eb2e8f9f7 2637 */
<> 144:ef7eb2e8f9f7 2638 #define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
<> 144:ef7eb2e8f9f7 2639
mbed_official 67:4bcbbb9fcddf 2640 /******************** Bit definition for RCC_CR register ********************/
<> 144:ef7eb2e8f9f7 2641 #define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */
<> 144:ef7eb2e8f9f7 2642 #define RCC_CR_HSIRDY ((uint32_t)0x00000002U) /*!< Internal High Speed clock ready flag */
<> 144:ef7eb2e8f9f7 2643
<> 144:ef7eb2e8f9f7 2644 #define RCC_CR_MSION ((uint32_t)0x00000100U) /*!< Internal Multi Speed clock enable */
<> 144:ef7eb2e8f9f7 2645 #define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /*!< Internal Multi Speed clock ready flag */
<> 144:ef7eb2e8f9f7 2646
<> 144:ef7eb2e8f9f7 2647 #define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed clock enable */
<> 144:ef7eb2e8f9f7 2648 #define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed clock ready flag */
<> 144:ef7eb2e8f9f7 2649 #define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed clock Bypass */
<> 144:ef7eb2e8f9f7 2650
<> 144:ef7eb2e8f9f7 2651 #define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< PLL enable */
<> 144:ef7eb2e8f9f7 2652 #define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< PLL clock ready flag */
<> 144:ef7eb2e8f9f7 2653 #define RCC_CR_CSSON ((uint32_t)0x10000000U) /*!< Clock Security System enable */
<> 144:ef7eb2e8f9f7 2654
<> 144:ef7eb2e8f9f7 2655 #define RCC_CR_RTCPRE ((uint32_t)0x60000000U) /*!< RTC Prescaler */
<> 144:ef7eb2e8f9f7 2656 #define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000U) /*!< Bit0 */
<> 144:ef7eb2e8f9f7 2657 #define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000U) /*!< Bit1 */
mbed_official 67:4bcbbb9fcddf 2658
mbed_official 67:4bcbbb9fcddf 2659 /******************** Bit definition for RCC_ICSCR register *****************/
<> 144:ef7eb2e8f9f7 2660 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /*!< Internal High Speed clock Calibration */
<> 144:ef7eb2e8f9f7 2661 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /*!< Internal High Speed clock trimming */
<> 144:ef7eb2e8f9f7 2662
<> 144:ef7eb2e8f9f7 2663 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /*!< Internal Multi Speed clock Range */
<> 144:ef7eb2e8f9f7 2664 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed clock Range 65.536 KHz */
<> 144:ef7eb2e8f9f7 2665 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /*!< Internal Multi Speed clock Range 131.072 KHz */
<> 144:ef7eb2e8f9f7 2666 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /*!< Internal Multi Speed clock Range 262.144 KHz */
<> 144:ef7eb2e8f9f7 2667 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /*!< Internal Multi Speed clock Range 524.288 KHz */
<> 144:ef7eb2e8f9f7 2668 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /*!< Internal Multi Speed clock Range 1.048 MHz */
<> 144:ef7eb2e8f9f7 2669 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /*!< Internal Multi Speed clock Range 2.097 MHz */
<> 144:ef7eb2e8f9f7 2670 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /*!< Internal Multi Speed clock Range 4.194 MHz */
<> 144:ef7eb2e8f9f7 2671 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /*!< Internal Multi Speed clock Calibration */
<> 144:ef7eb2e8f9f7 2672 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /*!< Internal Multi Speed clock trimming */
mbed_official 67:4bcbbb9fcddf 2673
mbed_official 67:4bcbbb9fcddf 2674 /******************** Bit definition for RCC_CFGR register ******************/
<> 144:ef7eb2e8f9f7 2675 #define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */
<> 144:ef7eb2e8f9f7 2676 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2677 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
mbed_official 67:4bcbbb9fcddf 2678
mbed_official 67:4bcbbb9fcddf 2679 /*!< SW configuration */
<> 144:ef7eb2e8f9f7 2680 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI selected as system clock */
<> 144:ef7eb2e8f9f7 2681 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI selected as system clock */
<> 144:ef7eb2e8f9f7 2682 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE selected as system clock */
<> 144:ef7eb2e8f9f7 2683 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selected as system clock */
<> 144:ef7eb2e8f9f7 2684
<> 144:ef7eb2e8f9f7 2685 #define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 144:ef7eb2e8f9f7 2686 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2687 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
mbed_official 67:4bcbbb9fcddf 2688
mbed_official 67:4bcbbb9fcddf 2689 /*!< SWS configuration */
<> 144:ef7eb2e8f9f7 2690 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */
<> 144:ef7eb2e8f9f7 2691 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI oscillator used as system clock */
<> 144:ef7eb2e8f9f7 2692 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */
<> 144:ef7eb2e8f9f7 2693 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */
<> 144:ef7eb2e8f9f7 2694
<> 144:ef7eb2e8f9f7 2695 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */
<> 144:ef7eb2e8f9f7 2696 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2697 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2698 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 2699 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!< Bit 3 */
mbed_official 67:4bcbbb9fcddf 2700
mbed_official 67:4bcbbb9fcddf 2701 /*!< HPRE configuration */
<> 144:ef7eb2e8f9f7 2702 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */
<> 144:ef7eb2e8f9f7 2703 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */
<> 144:ef7eb2e8f9f7 2704 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */
<> 144:ef7eb2e8f9f7 2705 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */
<> 144:ef7eb2e8f9f7 2706 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */
<> 144:ef7eb2e8f9f7 2707 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */
<> 144:ef7eb2e8f9f7 2708 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */
<> 144:ef7eb2e8f9f7 2709 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */
<> 144:ef7eb2e8f9f7 2710 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */
<> 144:ef7eb2e8f9f7 2711
<> 144:ef7eb2e8f9f7 2712 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB1 prescaler) */
<> 144:ef7eb2e8f9f7 2713 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2714 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2715 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
mbed_official 67:4bcbbb9fcddf 2716
mbed_official 67:4bcbbb9fcddf 2717 /*!< PPRE1 configuration */
<> 144:ef7eb2e8f9f7 2718 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
<> 144:ef7eb2e8f9f7 2719 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */
<> 144:ef7eb2e8f9f7 2720 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */
<> 144:ef7eb2e8f9f7 2721 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */
<> 144:ef7eb2e8f9f7 2722 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */
<> 144:ef7eb2e8f9f7 2723
<> 144:ef7eb2e8f9f7 2724 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 144:ef7eb2e8f9f7 2725 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2726 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2727 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!< Bit 2 */
mbed_official 67:4bcbbb9fcddf 2728
mbed_official 67:4bcbbb9fcddf 2729 /*!< PPRE2 configuration */
<> 144:ef7eb2e8f9f7 2730 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
<> 144:ef7eb2e8f9f7 2731 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */
<> 144:ef7eb2e8f9f7 2732 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */
<> 144:ef7eb2e8f9f7 2733 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */
<> 144:ef7eb2e8f9f7 2734 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */
mbed_official 67:4bcbbb9fcddf 2735
mbed_official 67:4bcbbb9fcddf 2736 /*!< PLL entry clock source*/
<> 144:ef7eb2e8f9f7 2737 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /*!< PLL entry clock source */
<> 144:ef7eb2e8f9f7 2738
<> 144:ef7eb2e8f9f7 2739 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /*!< HSI as PLL entry clock source */
<> 144:ef7eb2e8f9f7 2740 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /*!< HSE as PLL entry clock source */
mbed_official 67:4bcbbb9fcddf 2741
mbed_official 67:4bcbbb9fcddf 2742
mbed_official 67:4bcbbb9fcddf 2743 /*!< PLLMUL configuration */
<> 144:ef7eb2e8f9f7 2744 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
<> 144:ef7eb2e8f9f7 2745 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2746 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2747 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 2748 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /*!< Bit 3 */
mbed_official 67:4bcbbb9fcddf 2749
mbed_official 67:4bcbbb9fcddf 2750 /*!< PLLMUL configuration */
<> 144:ef7eb2e8f9f7 2751 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /*!< PLL input clock * 3 */
<> 144:ef7eb2e8f9f7 2752 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /*!< PLL input clock * 4 */
<> 144:ef7eb2e8f9f7 2753 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /*!< PLL input clock * 6 */
<> 144:ef7eb2e8f9f7 2754 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /*!< PLL input clock * 8 */
<> 144:ef7eb2e8f9f7 2755 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /*!< PLL input clock * 12 */
<> 144:ef7eb2e8f9f7 2756 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /*!< PLL input clock * 16 */
<> 144:ef7eb2e8f9f7 2757 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /*!< PLL input clock * 24 */
<> 144:ef7eb2e8f9f7 2758 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /*!< PLL input clock * 32 */
<> 144:ef7eb2e8f9f7 2759 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /*!< PLL input clock * 48 */
mbed_official 67:4bcbbb9fcddf 2760
mbed_official 67:4bcbbb9fcddf 2761 /*!< PLLDIV configuration */
<> 144:ef7eb2e8f9f7 2762 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /*!< PLLDIV[1:0] bits (PLL Output Division) */
<> 144:ef7eb2e8f9f7 2763 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /*!< Bit0 */
<> 144:ef7eb2e8f9f7 2764 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /*!< Bit1 */
mbed_official 67:4bcbbb9fcddf 2765
mbed_official 67:4bcbbb9fcddf 2766
mbed_official 67:4bcbbb9fcddf 2767 /*!< PLLDIV configuration */
<> 144:ef7eb2e8f9f7 2768 #define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000U) /*!< PLL clock output = CKVCO / 1 */
<> 144:ef7eb2e8f9f7 2769 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /*!< PLL clock output = CKVCO / 2 */
<> 144:ef7eb2e8f9f7 2770 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /*!< PLL clock output = CKVCO / 3 */
<> 144:ef7eb2e8f9f7 2771 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /*!< PLL clock output = CKVCO / 4 */
<> 144:ef7eb2e8f9f7 2772
<> 144:ef7eb2e8f9f7 2773
<> 144:ef7eb2e8f9f7 2774 #define RCC_CFGR_MCOSEL ((uint32_t)0x07000000U) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
<> 144:ef7eb2e8f9f7 2775 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2776 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2777 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
mbed_official 67:4bcbbb9fcddf 2778
mbed_official 67:4bcbbb9fcddf 2779 /*!< MCO configuration */
<> 144:ef7eb2e8f9f7 2780 #define RCC_CFGR_MCOSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
<> 144:ef7eb2e8f9f7 2781 #define RCC_CFGR_MCOSEL_SYSCLK ((uint32_t)0x01000000U) /*!< System clock selected */
<> 144:ef7eb2e8f9f7 2782 #define RCC_CFGR_MCOSEL_HSI ((uint32_t)0x02000000U) /*!< Internal 16 MHz RC oscillator clock selected */
<> 144:ef7eb2e8f9f7 2783 #define RCC_CFGR_MCOSEL_MSI ((uint32_t)0x03000000U) /*!< Internal Medium Speed RC oscillator clock selected */
<> 144:ef7eb2e8f9f7 2784 #define RCC_CFGR_MCOSEL_HSE ((uint32_t)0x04000000U) /*!< External 1-25 MHz oscillator clock selected */
<> 144:ef7eb2e8f9f7 2785 #define RCC_CFGR_MCOSEL_PLL ((uint32_t)0x05000000U) /*!< PLL clock divided */
<> 144:ef7eb2e8f9f7 2786 #define RCC_CFGR_MCOSEL_LSI ((uint32_t)0x06000000U) /*!< LSI selected */
<> 144:ef7eb2e8f9f7 2787 #define RCC_CFGR_MCOSEL_LSE ((uint32_t)0x07000000U) /*!< LSE selected */
<> 144:ef7eb2e8f9f7 2788
<> 144:ef7eb2e8f9f7 2789 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
<> 144:ef7eb2e8f9f7 2790 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2791 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2792 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2793
<> 144:ef7eb2e8f9f7 2794 /*!< MCO Prescaler configuration */
<> 144:ef7eb2e8f9f7 2795 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */
<> 144:ef7eb2e8f9f7 2796 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
<> 144:ef7eb2e8f9f7 2797 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
<> 144:ef7eb2e8f9f7 2798 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */
<> 144:ef7eb2e8f9f7 2799 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */
<> 144:ef7eb2e8f9f7 2800
<> 144:ef7eb2e8f9f7 2801 /* Legacy aliases */
<> 144:ef7eb2e8f9f7 2802 #define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1
<> 144:ef7eb2e8f9f7 2803 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2
<> 144:ef7eb2e8f9f7 2804 #define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4
<> 144:ef7eb2e8f9f7 2805 #define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8
<> 144:ef7eb2e8f9f7 2806 #define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16
<> 144:ef7eb2e8f9f7 2807 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
<> 144:ef7eb2e8f9f7 2808 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
<> 144:ef7eb2e8f9f7 2809 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
<> 144:ef7eb2e8f9f7 2810 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
<> 144:ef7eb2e8f9f7 2811 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
<> 144:ef7eb2e8f9f7 2812 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
<> 144:ef7eb2e8f9f7 2813 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
<> 144:ef7eb2e8f9f7 2814 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
mbed_official 67:4bcbbb9fcddf 2815
mbed_official 67:4bcbbb9fcddf 2816 /*!<****************** Bit definition for RCC_CIR register ********************/
<> 144:ef7eb2e8f9f7 2817 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 2818 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 2819 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 2820 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 2821 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 2822 #define RCC_CIR_MSIRDYF ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 2823 #define RCC_CIR_LSECSSF ((uint32_t)0x00000040U) /*!< LSE CSS Interrupt flag */
<> 144:ef7eb2e8f9f7 2824 #define RCC_CIR_CSSF ((uint32_t)0x00000080U) /*!< Clock Security System Interrupt flag */
<> 144:ef7eb2e8f9f7 2825
<> 144:ef7eb2e8f9f7 2826 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100U) /*!< LSI Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 2827 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200U) /*!< LSE Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 2828 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400U) /*!< HSI Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 2829 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800U) /*!< HSE Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 2830 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000U) /*!< PLL Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 2831 #define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000U) /*!< MSI Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 2832 #define RCC_CIR_LSECSSIE ((uint32_t)0x00004000U) /*!< LSE CSS Interrupt Enable */
<> 144:ef7eb2e8f9f7 2833
<> 144:ef7eb2e8f9f7 2834 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000U) /*!< LSI Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 2835 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000U) /*!< LSE Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 2836 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000U) /*!< HSI Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 2837 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000U) /*!< HSE Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 2838 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000U) /*!< PLL Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 2839 #define RCC_CIR_MSIRDYC ((uint32_t)0x00200000U) /*!< MSI Ready Interrupt Clear */
<> 144:ef7eb2e8f9f7 2840 #define RCC_CIR_LSECSSC ((uint32_t)0x00400000U) /*!< LSE CSS Interrupt Clear */
<> 144:ef7eb2e8f9f7 2841 #define RCC_CIR_CSSC ((uint32_t)0x00800000U) /*!< Clock Security System Interrupt Clear */
mbed_official 67:4bcbbb9fcddf 2842
mbed_official 67:4bcbbb9fcddf 2843 /***************** Bit definition for RCC_AHBRSTR register ******************/
<> 144:ef7eb2e8f9f7 2844 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001U) /*!< GPIO port A reset */
<> 144:ef7eb2e8f9f7 2845 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002U) /*!< GPIO port B reset */
<> 144:ef7eb2e8f9f7 2846 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004U) /*!< GPIO port C reset */
<> 144:ef7eb2e8f9f7 2847 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008U) /*!< GPIO port D reset */
<> 144:ef7eb2e8f9f7 2848 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010U) /*!< GPIO port E reset */
<> 144:ef7eb2e8f9f7 2849 #define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020U) /*!< GPIO port H reset */
<> 144:ef7eb2e8f9f7 2850 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /*!< CRC reset */
<> 144:ef7eb2e8f9f7 2851 #define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000U) /*!< FLITF reset */
<> 144:ef7eb2e8f9f7 2852 #define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000U) /*!< DMA1 reset */
<> 144:ef7eb2e8f9f7 2853 #define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000U) /*!< DMA2 reset */
mbed_official 67:4bcbbb9fcddf 2854
mbed_official 67:4bcbbb9fcddf 2855 /***************** Bit definition for RCC_APB2RSTR register *****************/
<> 144:ef7eb2e8f9f7 2856 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /*!< System Configuration SYSCFG reset */
<> 144:ef7eb2e8f9f7 2857 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004U) /*!< TIM9 reset */
<> 144:ef7eb2e8f9f7 2858 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008U) /*!< TIM10 reset */
<> 144:ef7eb2e8f9f7 2859 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010U) /*!< TIM11 reset */
<> 144:ef7eb2e8f9f7 2860 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200U) /*!< ADC1 reset */
<> 144:ef7eb2e8f9f7 2861 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /*!< SPI1 reset */
<> 144:ef7eb2e8f9f7 2862 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U) /*!< USART1 reset */
mbed_official 67:4bcbbb9fcddf 2863
mbed_official 67:4bcbbb9fcddf 2864 /***************** Bit definition for RCC_APB1RSTR register *****************/
<> 144:ef7eb2e8f9f7 2865 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /*!< Timer 2 reset */
<> 144:ef7eb2e8f9f7 2866 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002U) /*!< Timer 3 reset */
<> 144:ef7eb2e8f9f7 2867 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004U) /*!< Timer 4 reset */
<> 144:ef7eb2e8f9f7 2868 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008U) /*!< Timer 5 reset */
<> 144:ef7eb2e8f9f7 2869 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010U) /*!< Timer 6 reset */
<> 144:ef7eb2e8f9f7 2870 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020U) /*!< Timer 7 reset */
<> 144:ef7eb2e8f9f7 2871 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /*!< Window Watchdog reset */
<> 144:ef7eb2e8f9f7 2872 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000U) /*!< SPI 2 reset */
<> 144:ef7eb2e8f9f7 2873 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000U) /*!< SPI 3 reset */
<> 144:ef7eb2e8f9f7 2874 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /*!< USART 2 reset */
<> 144:ef7eb2e8f9f7 2875 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000U) /*!< USART 3 reset */
<> 144:ef7eb2e8f9f7 2876 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /*!< I2C 1 reset */
<> 144:ef7eb2e8f9f7 2877 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000U) /*!< I2C 2 reset */
<> 144:ef7eb2e8f9f7 2878 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000U) /*!< USB reset */
<> 144:ef7eb2e8f9f7 2879 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /*!< Power interface reset */
<> 144:ef7eb2e8f9f7 2880 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000U) /*!< DAC interface reset */
<> 144:ef7eb2e8f9f7 2881 #define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000U) /*!< Comparator interface reset */
mbed_official 67:4bcbbb9fcddf 2882
mbed_official 67:4bcbbb9fcddf 2883 /****************** Bit definition for RCC_AHBENR register ******************/
<> 144:ef7eb2e8f9f7 2884 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enable */
<> 144:ef7eb2e8f9f7 2885 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enable */
<> 144:ef7eb2e8f9f7 2886 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enable */
<> 144:ef7eb2e8f9f7 2887 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enable */
<> 144:ef7eb2e8f9f7 2888 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010U) /*!< GPIO port E clock enable */
<> 144:ef7eb2e8f9f7 2889 #define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020U) /*!< GPIO port H clock enable */
<> 144:ef7eb2e8f9f7 2890 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /*!< CRC clock enable */
<> 144:ef7eb2e8f9f7 2891 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000U) /*!< FLITF clock enable (has effect only when
mbed_official 67:4bcbbb9fcddf 2892 the Flash memory is in power down mode) */
<> 144:ef7eb2e8f9f7 2893 #define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000U) /*!< DMA1 clock enable */
<> 144:ef7eb2e8f9f7 2894 #define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000U) /*!< DMA2 clock enable */
mbed_official 67:4bcbbb9fcddf 2895
mbed_official 67:4bcbbb9fcddf 2896 /****************** Bit definition for RCC_APB2ENR register *****************/
<> 144:ef7eb2e8f9f7 2897 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /*!< System Configuration SYSCFG clock enable */
<> 144:ef7eb2e8f9f7 2898 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004U) /*!< TIM9 interface clock enable */
<> 144:ef7eb2e8f9f7 2899 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008U) /*!< TIM10 interface clock enable */
<> 144:ef7eb2e8f9f7 2900 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010U) /*!< TIM11 Timer clock enable */
<> 144:ef7eb2e8f9f7 2901 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200U) /*!< ADC1 clock enable */
<> 144:ef7eb2e8f9f7 2902 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /*!< SPI1 clock enable */
<> 144:ef7eb2e8f9f7 2903 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U) /*!< USART1 clock enable */
mbed_official 67:4bcbbb9fcddf 2904
mbed_official 67:4bcbbb9fcddf 2905 /***************** Bit definition for RCC_APB1ENR register ******************/
<> 144:ef7eb2e8f9f7 2906 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled*/
<> 144:ef7eb2e8f9f7 2907 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002U) /*!< Timer 3 clock enable */
<> 144:ef7eb2e8f9f7 2908 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004U) /*!< Timer 4 clock enable */
<> 144:ef7eb2e8f9f7 2909 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008U) /*!< Timer 5 clock enable */
<> 144:ef7eb2e8f9f7 2910 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010U) /*!< Timer 6 clock enable */
<> 144:ef7eb2e8f9f7 2911 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020U) /*!< Timer 7 clock enable */
<> 144:ef7eb2e8f9f7 2912 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enable */
<> 144:ef7eb2e8f9f7 2913 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000U) /*!< SPI 2 clock enable */
<> 144:ef7eb2e8f9f7 2914 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000U) /*!< SPI 3 clock enable */
<> 144:ef7eb2e8f9f7 2915 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /*!< USART 2 clock enable */
<> 144:ef7eb2e8f9f7 2916 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000U) /*!< USART 3 clock enable */
<> 144:ef7eb2e8f9f7 2917 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /*!< I2C 1 clock enable */
<> 144:ef7eb2e8f9f7 2918 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000U) /*!< I2C 2 clock enable */
<> 144:ef7eb2e8f9f7 2919 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000U) /*!< USB clock enable */
<> 144:ef7eb2e8f9f7 2920 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /*!< Power interface clock enable */
<> 144:ef7eb2e8f9f7 2921 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000U) /*!< DAC interface clock enable */
<> 144:ef7eb2e8f9f7 2922 #define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000U) /*!< Comparator interface clock enable */
mbed_official 67:4bcbbb9fcddf 2923
mbed_official 67:4bcbbb9fcddf 2924 /****************** Bit definition for RCC_AHBLPENR register ****************/
<> 144:ef7eb2e8f9f7 2925 #define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2926 #define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2927 #define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2928 #define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2929 #define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010U) /*!< GPIO port E clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2930 #define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020U) /*!< GPIO port H clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2931 #define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000U) /*!< CRC clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2932 #define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000U) /*!< Flash Interface clock enabled in sleep mode
mbed_official 67:4bcbbb9fcddf 2933 (has effect only when the Flash memory is
mbed_official 67:4bcbbb9fcddf 2934 in power down mode) */
<> 144:ef7eb2e8f9f7 2935 #define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000U) /*!< SRAM clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2936 #define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000U) /*!< DMA1 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2937 #define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000U) /*!< DMA2 clock enabled in sleep mode */
mbed_official 67:4bcbbb9fcddf 2938
mbed_official 67:4bcbbb9fcddf 2939 /****************** Bit definition for RCC_APB2LPENR register ***************/
<> 144:ef7eb2e8f9f7 2940 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001U) /*!< System Configuration SYSCFG clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2941 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004U) /*!< TIM9 interface clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2942 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008U) /*!< TIM10 interface clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2943 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010U) /*!< TIM11 Timer clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2944 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200U) /*!< ADC1 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2945 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000U) /*!< SPI1 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2946 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000U) /*!< USART1 clock enabled in sleep mode */
mbed_official 67:4bcbbb9fcddf 2947
mbed_official 67:4bcbbb9fcddf 2948 /***************** Bit definition for RCC_APB1LPENR register ****************/
<> 144:ef7eb2e8f9f7 2949 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2950 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002U) /*!< Timer 3 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2951 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004U) /*!< Timer 4 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2952 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008U) /*!< Timer 5 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2953 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010U) /*!< Timer 6 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2954 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020U) /*!< Timer 7 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2955 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2956 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000U) /*!< SPI 2 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2957 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000U) /*!< SPI 3 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2958 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000U) /*!< USART 2 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2959 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000U) /*!< USART 3 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2960 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000U) /*!< I2C 1 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2961 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000U) /*!< I2C 2 clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2962 #define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000U) /*!< USB clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2963 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000U) /*!< Power interface clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2964 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000U) /*!< DAC interface clock enabled in sleep mode */
<> 144:ef7eb2e8f9f7 2965 #define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000U) /*!< Comparator interface clock enabled in sleep mode*/
mbed_official 67:4bcbbb9fcddf 2966
mbed_official 67:4bcbbb9fcddf 2967 /******************* Bit definition for RCC_CSR register ********************/
<> 144:ef7eb2e8f9f7 2968 #define RCC_CSR_LSION ((uint32_t)0x00000001U) /*!< Internal Low Speed oscillator enable */
<> 144:ef7eb2e8f9f7 2969 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /*!< Internal Low Speed oscillator Ready */
<> 144:ef7eb2e8f9f7 2970
<> 144:ef7eb2e8f9f7 2971 #define RCC_CSR_LSEON ((uint32_t)0x00000100U) /*!< External Low Speed oscillator enable */
<> 144:ef7eb2e8f9f7 2972 #define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /*!< External Low Speed oscillator Ready */
<> 144:ef7eb2e8f9f7 2973 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /*!< External Low Speed oscillator Bypass */
<> 144:ef7eb2e8f9f7 2974
<> 144:ef7eb2e8f9f7 2975 #define RCC_CSR_LSECSSON ((uint32_t)0x00000800U) /*!< External Low Speed oscillator CSS Enable */
<> 144:ef7eb2e8f9f7 2976 #define RCC_CSR_LSECSSD ((uint32_t)0x00001000U) /*!< External Low Speed oscillator CSS Detected */
<> 144:ef7eb2e8f9f7 2977
<> 144:ef7eb2e8f9f7 2978 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
<> 144:ef7eb2e8f9f7 2979 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2980 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
mbed_official 67:4bcbbb9fcddf 2981
mbed_official 67:4bcbbb9fcddf 2982 /*!< RTC congiguration */
<> 144:ef7eb2e8f9f7 2983 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
<> 144:ef7eb2e8f9f7 2984 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /*!< LSE oscillator clock used as RTC clock */
<> 144:ef7eb2e8f9f7 2985 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /*!< LSI oscillator clock used as RTC clock */
<> 144:ef7eb2e8f9f7 2986 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
<> 144:ef7eb2e8f9f7 2987
<> 144:ef7eb2e8f9f7 2988 #define RCC_CSR_RTCEN ((uint32_t)0x00400000U) /*!< RTC clock enable */
<> 144:ef7eb2e8f9f7 2989 #define RCC_CSR_RTCRST ((uint32_t)0x00800000U) /*!< RTC reset */
mbed_official 67:4bcbbb9fcddf 2990
<> 144:ef7eb2e8f9f7 2991 #define RCC_CSR_RMVF ((uint32_t)0x01000000U) /*!< Remove reset flag */
<> 144:ef7eb2e8f9f7 2992 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /*!< Option Bytes Loader reset flag */
<> 144:ef7eb2e8f9f7 2993 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /*!< PIN reset flag */
<> 144:ef7eb2e8f9f7 2994 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /*!< POR/PDR reset flag */
<> 144:ef7eb2e8f9f7 2995 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /*!< Software Reset flag */
<> 144:ef7eb2e8f9f7 2996 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /*!< Independent Watchdog reset flag */
<> 144:ef7eb2e8f9f7 2997 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /*!< Window watchdog reset flag */
<> 144:ef7eb2e8f9f7 2998 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /*!< Low-Power reset flag */
mbed_official 67:4bcbbb9fcddf 2999
mbed_official 67:4bcbbb9fcddf 3000 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 3001 /* */
mbed_official 67:4bcbbb9fcddf 3002 /* Real-Time Clock (RTC) */
mbed_official 67:4bcbbb9fcddf 3003 /* */
mbed_official 67:4bcbbb9fcddf 3004 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3005 /*
<> 144:ef7eb2e8f9f7 3006 * @brief Specific device feature definitions (not present on all devices in the STM32F0 family)
<> 144:ef7eb2e8f9f7 3007 */
<> 144:ef7eb2e8f9f7 3008 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
<> 144:ef7eb2e8f9f7 3009 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
<> 144:ef7eb2e8f9f7 3010 #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */
<> 144:ef7eb2e8f9f7 3011 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
<> 144:ef7eb2e8f9f7 3012 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */
<> 144:ef7eb2e8f9f7 3013 #define RTC_SMOOTHCALIB_SUPPORT /*!< Smooth digital calibration feature support */
<> 144:ef7eb2e8f9f7 3014 #define RTC_SUBSECOND_SUPPORT /*!< Sub-second feature support */
<> 144:ef7eb2e8f9f7 3015
mbed_official 67:4bcbbb9fcddf 3016 /******************** Bits definition for RTC_TR register *******************/
<> 144:ef7eb2e8f9f7 3017 #define RTC_TR_PM ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 3018 #define RTC_TR_HT ((uint32_t)0x00300000U)
<> 144:ef7eb2e8f9f7 3019 #define RTC_TR_HT_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 3020 #define RTC_TR_HT_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 3021 #define RTC_TR_HU ((uint32_t)0x000F0000U)
<> 144:ef7eb2e8f9f7 3022 #define RTC_TR_HU_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 3023 #define RTC_TR_HU_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 3024 #define RTC_TR_HU_2 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 3025 #define RTC_TR_HU_3 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 3026 #define RTC_TR_MNT ((uint32_t)0x00007000U)
<> 144:ef7eb2e8f9f7 3027 #define RTC_TR_MNT_0 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 3028 #define RTC_TR_MNT_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 3029 #define RTC_TR_MNT_2 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 3030 #define RTC_TR_MNU ((uint32_t)0x00000F00U)
<> 144:ef7eb2e8f9f7 3031 #define RTC_TR_MNU_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 3032 #define RTC_TR_MNU_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 3033 #define RTC_TR_MNU_2 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 3034 #define RTC_TR_MNU_3 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 3035 #define RTC_TR_ST ((uint32_t)0x00000070U)
<> 144:ef7eb2e8f9f7 3036 #define RTC_TR_ST_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 3037 #define RTC_TR_ST_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 3038 #define RTC_TR_ST_2 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 3039 #define RTC_TR_SU ((uint32_t)0x0000000FU)
<> 144:ef7eb2e8f9f7 3040 #define RTC_TR_SU_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 3041 #define RTC_TR_SU_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 3042 #define RTC_TR_SU_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 3043 #define RTC_TR_SU_3 ((uint32_t)0x00000008U)
mbed_official 67:4bcbbb9fcddf 3044
mbed_official 67:4bcbbb9fcddf 3045 /******************** Bits definition for RTC_DR register *******************/
<> 144:ef7eb2e8f9f7 3046 #define RTC_DR_YT ((uint32_t)0x00F00000U)
<> 144:ef7eb2e8f9f7 3047 #define RTC_DR_YT_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 3048 #define RTC_DR_YT_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 3049 #define RTC_DR_YT_2 ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 3050 #define RTC_DR_YT_3 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 3051 #define RTC_DR_YU ((uint32_t)0x000F0000U)
<> 144:ef7eb2e8f9f7 3052 #define RTC_DR_YU_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 3053 #define RTC_DR_YU_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 3054 #define RTC_DR_YU_2 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 3055 #define RTC_DR_YU_3 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 3056 #define RTC_DR_WDU ((uint32_t)0x0000E000U)
<> 144:ef7eb2e8f9f7 3057 #define RTC_DR_WDU_0 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 3058 #define RTC_DR_WDU_1 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 3059 #define RTC_DR_WDU_2 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 3060 #define RTC_DR_MT ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 3061 #define RTC_DR_MU ((uint32_t)0x00000F00U)
<> 144:ef7eb2e8f9f7 3062 #define RTC_DR_MU_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 3063 #define RTC_DR_MU_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 3064 #define RTC_DR_MU_2 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 3065 #define RTC_DR_MU_3 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 3066 #define RTC_DR_DT ((uint32_t)0x00000030U)
<> 144:ef7eb2e8f9f7 3067 #define RTC_DR_DT_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 3068 #define RTC_DR_DT_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 3069 #define RTC_DR_DU ((uint32_t)0x0000000FU)
<> 144:ef7eb2e8f9f7 3070 #define RTC_DR_DU_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 3071 #define RTC_DR_DU_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 3072 #define RTC_DR_DU_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 3073 #define RTC_DR_DU_3 ((uint32_t)0x00000008U)
mbed_official 67:4bcbbb9fcddf 3074
mbed_official 67:4bcbbb9fcddf 3075 /******************** Bits definition for RTC_CR register *******************/
<> 144:ef7eb2e8f9f7 3076 #define RTC_CR_COE ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 3077 #define RTC_CR_OSEL ((uint32_t)0x00600000U)
<> 144:ef7eb2e8f9f7 3078 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 3079 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 3080 #define RTC_CR_POL ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 3081 #define RTC_CR_COSEL ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 3082 #define RTC_CR_BCK ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 3083 #define RTC_CR_SUB1H ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 3084 #define RTC_CR_ADD1H ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 3085 #define RTC_CR_TSIE ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 3086 #define RTC_CR_WUTIE ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 3087 #define RTC_CR_ALRBIE ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 3088 #define RTC_CR_ALRAIE ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 3089 #define RTC_CR_TSE ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 3090 #define RTC_CR_WUTE ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 3091 #define RTC_CR_ALRBE ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 3092 #define RTC_CR_ALRAE ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 3093 #define RTC_CR_DCE ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 3094 #define RTC_CR_FMT ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 3095 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 3096 #define RTC_CR_REFCKON ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 3097 #define RTC_CR_TSEDGE ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 3098 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007U)
<> 144:ef7eb2e8f9f7 3099 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 3100 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 3101 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U)
mbed_official 67:4bcbbb9fcddf 3102
mbed_official 67:4bcbbb9fcddf 3103 /******************** Bits definition for RTC_ISR register ******************/
<> 144:ef7eb2e8f9f7 3104 #define RTC_ISR_RECALPF ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 3105 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 3106 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 3107 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 3108 #define RTC_ISR_TSOVF ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 3109 #define RTC_ISR_TSF ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 3110 #define RTC_ISR_WUTF ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 3111 #define RTC_ISR_ALRBF ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 3112 #define RTC_ISR_ALRAF ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 3113 #define RTC_ISR_INIT ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 3114 #define RTC_ISR_INITF ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 3115 #define RTC_ISR_RSF ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 3116 #define RTC_ISR_INITS ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 3117 #define RTC_ISR_SHPF ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 3118 #define RTC_ISR_WUTWF ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 3119 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 3120 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001U)
mbed_official 67:4bcbbb9fcddf 3121
mbed_official 67:4bcbbb9fcddf 3122 /******************** Bits definition for RTC_PRER register *****************/
<> 144:ef7eb2e8f9f7 3123 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U)
<> 144:ef7eb2e8f9f7 3124 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU)
mbed_official 67:4bcbbb9fcddf 3125
mbed_official 67:4bcbbb9fcddf 3126 /******************** Bits definition for RTC_WUTR register *****************/
<> 144:ef7eb2e8f9f7 3127 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
mbed_official 67:4bcbbb9fcddf 3128
mbed_official 67:4bcbbb9fcddf 3129 /******************** Bits definition for RTC_CALIBR register ***************/
<> 144:ef7eb2e8f9f7 3130 #define RTC_CALIBR_DCS ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 3131 #define RTC_CALIBR_DC ((uint32_t)0x0000001FU)
mbed_official 67:4bcbbb9fcddf 3132
mbed_official 67:4bcbbb9fcddf 3133 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 144:ef7eb2e8f9f7 3134 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U)
<> 144:ef7eb2e8f9f7 3135 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U)
<> 144:ef7eb2e8f9f7 3136 #define RTC_ALRMAR_DT ((uint32_t)0x30000000U)
<> 144:ef7eb2e8f9f7 3137 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 3138 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 3139 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000U)
<> 144:ef7eb2e8f9f7 3140 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 3141 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 3142 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 3143 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 3144 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 3145 #define RTC_ALRMAR_PM ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 3146 #define RTC_ALRMAR_HT ((uint32_t)0x00300000U)
<> 144:ef7eb2e8f9f7 3147 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 3148 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 3149 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000U)
<> 144:ef7eb2e8f9f7 3150 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 3151 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 3152 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 3153 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 3154 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 3155 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000U)
<> 144:ef7eb2e8f9f7 3156 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 3157 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 3158 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 3159 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U)
<> 144:ef7eb2e8f9f7 3160 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 3161 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 3162 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 3163 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 3164 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 3165 #define RTC_ALRMAR_ST ((uint32_t)0x00000070U)
<> 144:ef7eb2e8f9f7 3166 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 3167 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 3168 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 3169 #define RTC_ALRMAR_SU ((uint32_t)0x0000000FU)
<> 144:ef7eb2e8f9f7 3170 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 3171 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 3172 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 3173 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U)
mbed_official 67:4bcbbb9fcddf 3174
mbed_official 67:4bcbbb9fcddf 3175 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 144:ef7eb2e8f9f7 3176 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U)
<> 144:ef7eb2e8f9f7 3177 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U)
<> 144:ef7eb2e8f9f7 3178 #define RTC_ALRMBR_DT ((uint32_t)0x30000000U)
<> 144:ef7eb2e8f9f7 3179 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 3180 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 3181 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000U)
<> 144:ef7eb2e8f9f7 3182 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 3183 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 3184 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 3185 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 3186 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 3187 #define RTC_ALRMBR_PM ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 3188 #define RTC_ALRMBR_HT ((uint32_t)0x00300000U)
<> 144:ef7eb2e8f9f7 3189 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 3190 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 3191 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000U)
<> 144:ef7eb2e8f9f7 3192 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 3193 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 3194 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 3195 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 3196 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 3197 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000U)
<> 144:ef7eb2e8f9f7 3198 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 3199 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 3200 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 3201 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U)
<> 144:ef7eb2e8f9f7 3202 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 3203 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 3204 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 3205 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 3206 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 3207 #define RTC_ALRMBR_ST ((uint32_t)0x00000070U)
<> 144:ef7eb2e8f9f7 3208 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 3209 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 3210 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 3211 #define RTC_ALRMBR_SU ((uint32_t)0x0000000FU)
<> 144:ef7eb2e8f9f7 3212 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 3213 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 3214 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 3215 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U)
mbed_official 67:4bcbbb9fcddf 3216
mbed_official 67:4bcbbb9fcddf 3217 /******************** Bits definition for RTC_WPR register ******************/
<> 144:ef7eb2e8f9f7 3218 #define RTC_WPR_KEY ((uint32_t)0x000000FFU)
mbed_official 67:4bcbbb9fcddf 3219
mbed_official 67:4bcbbb9fcddf 3220 /******************** Bits definition for RTC_SSR register ******************/
<> 144:ef7eb2e8f9f7 3221 #define RTC_SSR_SS ((uint32_t)0x0000FFFFU)
mbed_official 67:4bcbbb9fcddf 3222
mbed_official 67:4bcbbb9fcddf 3223 /******************** Bits definition for RTC_SHIFTR register ***************/
<> 144:ef7eb2e8f9f7 3224 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU)
<> 144:ef7eb2e8f9f7 3225 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U)
mbed_official 67:4bcbbb9fcddf 3226
mbed_official 67:4bcbbb9fcddf 3227 /******************** Bits definition for RTC_TSTR register *****************/
<> 144:ef7eb2e8f9f7 3228 #define RTC_TSTR_PM ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 3229 #define RTC_TSTR_HT ((uint32_t)0x00300000U)
<> 144:ef7eb2e8f9f7 3230 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 3231 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 3232 #define RTC_TSTR_HU ((uint32_t)0x000F0000U)
<> 144:ef7eb2e8f9f7 3233 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 3234 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 3235 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 3236 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 3237 #define RTC_TSTR_MNT ((uint32_t)0x00007000U)
<> 144:ef7eb2e8f9f7 3238 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 3239 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 3240 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 3241 #define RTC_TSTR_MNU ((uint32_t)0x00000F00U)
<> 144:ef7eb2e8f9f7 3242 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 3243 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 3244 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 3245 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 3246 #define RTC_TSTR_ST ((uint32_t)0x00000070U)
<> 144:ef7eb2e8f9f7 3247 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 3248 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 3249 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 3250 #define RTC_TSTR_SU ((uint32_t)0x0000000FU)
<> 144:ef7eb2e8f9f7 3251 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 3252 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 3253 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 3254 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008U)
mbed_official 67:4bcbbb9fcddf 3255
mbed_official 67:4bcbbb9fcddf 3256 /******************** Bits definition for RTC_TSDR register *****************/
<> 144:ef7eb2e8f9f7 3257 #define RTC_TSDR_WDU ((uint32_t)0x0000E000U)
<> 144:ef7eb2e8f9f7 3258 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 3259 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 3260 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 3261 #define RTC_TSDR_MT ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 3262 #define RTC_TSDR_MU ((uint32_t)0x00000F00U)
<> 144:ef7eb2e8f9f7 3263 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 3264 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 3265 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 3266 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 3267 #define RTC_TSDR_DT ((uint32_t)0x00000030U)
<> 144:ef7eb2e8f9f7 3268 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 3269 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 3270 #define RTC_TSDR_DU ((uint32_t)0x0000000FU)
<> 144:ef7eb2e8f9f7 3271 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 3272 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 3273 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 3274 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008U)
mbed_official 67:4bcbbb9fcddf 3275
mbed_official 67:4bcbbb9fcddf 3276 /******************** Bits definition for RTC_TSSSR register ****************/
<> 144:ef7eb2e8f9f7 3277 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
mbed_official 67:4bcbbb9fcddf 3278
mbed_official 67:4bcbbb9fcddf 3279 /******************** Bits definition for RTC_CAL register *****************/
<> 144:ef7eb2e8f9f7 3280 #define RTC_CALR_CALP ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 3281 #define RTC_CALR_CALW8 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 3282 #define RTC_CALR_CALW16 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 3283 #define RTC_CALR_CALM ((uint32_t)0x000001FFU)
<> 144:ef7eb2e8f9f7 3284 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 3285 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 3286 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 3287 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 3288 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 3289 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 3290 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 3291 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 3292 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100U)
mbed_official 67:4bcbbb9fcddf 3293
mbed_official 67:4bcbbb9fcddf 3294 /******************** Bits definition for RTC_TAFCR register ****************/
<> 144:ef7eb2e8f9f7 3295 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 3296 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 3297 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000U)
<> 144:ef7eb2e8f9f7 3298 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 3299 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 3300 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800U)
<> 144:ef7eb2e8f9f7 3301 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 3302 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 3303 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700U)
<> 144:ef7eb2e8f9f7 3304 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 3305 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 3306 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 3307 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 3308 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 3309 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 3310 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 3311 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 3312 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 3313 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 3314 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001U)
mbed_official 67:4bcbbb9fcddf 3315
mbed_official 67:4bcbbb9fcddf 3316 /******************** Bits definition for RTC_ALRMASSR register *************/
<> 144:ef7eb2e8f9f7 3317 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
<> 144:ef7eb2e8f9f7 3318 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 3319 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 3320 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 3321 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 3322 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
mbed_official 67:4bcbbb9fcddf 3323
mbed_official 67:4bcbbb9fcddf 3324 /******************** Bits definition for RTC_ALRMBSSR register *************/
<> 144:ef7eb2e8f9f7 3325 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
<> 144:ef7eb2e8f9f7 3326 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 3327 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 3328 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 3329 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 3330 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
mbed_official 67:4bcbbb9fcddf 3331
mbed_official 67:4bcbbb9fcddf 3332 /******************** Bits definition for RTC_BKP0R register ****************/
<> 144:ef7eb2e8f9f7 3333 #define RTC_BKP0R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3334
mbed_official 67:4bcbbb9fcddf 3335 /******************** Bits definition for RTC_BKP1R register ****************/
<> 144:ef7eb2e8f9f7 3336 #define RTC_BKP1R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3337
mbed_official 67:4bcbbb9fcddf 3338 /******************** Bits definition for RTC_BKP2R register ****************/
<> 144:ef7eb2e8f9f7 3339 #define RTC_BKP2R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3340
mbed_official 67:4bcbbb9fcddf 3341 /******************** Bits definition for RTC_BKP3R register ****************/
<> 144:ef7eb2e8f9f7 3342 #define RTC_BKP3R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3343
mbed_official 67:4bcbbb9fcddf 3344 /******************** Bits definition for RTC_BKP4R register ****************/
<> 144:ef7eb2e8f9f7 3345 #define RTC_BKP4R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3346
mbed_official 67:4bcbbb9fcddf 3347 /******************** Bits definition for RTC_BKP5R register ****************/
<> 144:ef7eb2e8f9f7 3348 #define RTC_BKP5R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3349
mbed_official 67:4bcbbb9fcddf 3350 /******************** Bits definition for RTC_BKP6R register ****************/
<> 144:ef7eb2e8f9f7 3351 #define RTC_BKP6R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3352
mbed_official 67:4bcbbb9fcddf 3353 /******************** Bits definition for RTC_BKP7R register ****************/
<> 144:ef7eb2e8f9f7 3354 #define RTC_BKP7R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3355
mbed_official 67:4bcbbb9fcddf 3356 /******************** Bits definition for RTC_BKP8R register ****************/
<> 144:ef7eb2e8f9f7 3357 #define RTC_BKP8R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3358
mbed_official 67:4bcbbb9fcddf 3359 /******************** Bits definition for RTC_BKP9R register ****************/
<> 144:ef7eb2e8f9f7 3360 #define RTC_BKP9R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3361
mbed_official 67:4bcbbb9fcddf 3362 /******************** Bits definition for RTC_BKP10R register ***************/
<> 144:ef7eb2e8f9f7 3363 #define RTC_BKP10R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3364
mbed_official 67:4bcbbb9fcddf 3365 /******************** Bits definition for RTC_BKP11R register ***************/
<> 144:ef7eb2e8f9f7 3366 #define RTC_BKP11R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3367
mbed_official 67:4bcbbb9fcddf 3368 /******************** Bits definition for RTC_BKP12R register ***************/
<> 144:ef7eb2e8f9f7 3369 #define RTC_BKP12R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3370
mbed_official 67:4bcbbb9fcddf 3371 /******************** Bits definition for RTC_BKP13R register ***************/
<> 144:ef7eb2e8f9f7 3372 #define RTC_BKP13R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3373
mbed_official 67:4bcbbb9fcddf 3374 /******************** Bits definition for RTC_BKP14R register ***************/
<> 144:ef7eb2e8f9f7 3375 #define RTC_BKP14R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3376
mbed_official 67:4bcbbb9fcddf 3377 /******************** Bits definition for RTC_BKP15R register ***************/
<> 144:ef7eb2e8f9f7 3378 #define RTC_BKP15R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3379
mbed_official 67:4bcbbb9fcddf 3380 /******************** Bits definition for RTC_BKP16R register ***************/
<> 144:ef7eb2e8f9f7 3381 #define RTC_BKP16R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3382
mbed_official 67:4bcbbb9fcddf 3383 /******************** Bits definition for RTC_BKP17R register ***************/
<> 144:ef7eb2e8f9f7 3384 #define RTC_BKP17R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3385
mbed_official 67:4bcbbb9fcddf 3386 /******************** Bits definition for RTC_BKP18R register ***************/
<> 144:ef7eb2e8f9f7 3387 #define RTC_BKP18R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3388
mbed_official 67:4bcbbb9fcddf 3389 /******************** Bits definition for RTC_BKP19R register ***************/
<> 144:ef7eb2e8f9f7 3390 #define RTC_BKP19R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3391
mbed_official 67:4bcbbb9fcddf 3392 /******************** Bits definition for RTC_BKP20R register ***************/
<> 144:ef7eb2e8f9f7 3393 #define RTC_BKP20R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3394
mbed_official 67:4bcbbb9fcddf 3395 /******************** Bits definition for RTC_BKP21R register ***************/
<> 144:ef7eb2e8f9f7 3396 #define RTC_BKP21R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3397
mbed_official 67:4bcbbb9fcddf 3398 /******************** Bits definition for RTC_BKP22R register ***************/
<> 144:ef7eb2e8f9f7 3399 #define RTC_BKP22R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3400
mbed_official 67:4bcbbb9fcddf 3401 /******************** Bits definition for RTC_BKP23R register ***************/
<> 144:ef7eb2e8f9f7 3402 #define RTC_BKP23R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3403
mbed_official 67:4bcbbb9fcddf 3404 /******************** Bits definition for RTC_BKP24R register ***************/
<> 144:ef7eb2e8f9f7 3405 #define RTC_BKP24R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3406
mbed_official 67:4bcbbb9fcddf 3407 /******************** Bits definition for RTC_BKP25R register ***************/
<> 144:ef7eb2e8f9f7 3408 #define RTC_BKP25R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3409
mbed_official 67:4bcbbb9fcddf 3410 /******************** Bits definition for RTC_BKP26R register ***************/
<> 144:ef7eb2e8f9f7 3411 #define RTC_BKP26R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3412
mbed_official 67:4bcbbb9fcddf 3413 /******************** Bits definition for RTC_BKP27R register ***************/
<> 144:ef7eb2e8f9f7 3414 #define RTC_BKP27R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3415
mbed_official 67:4bcbbb9fcddf 3416 /******************** Bits definition for RTC_BKP28R register ***************/
<> 144:ef7eb2e8f9f7 3417 #define RTC_BKP28R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3418
mbed_official 67:4bcbbb9fcddf 3419 /******************** Bits definition for RTC_BKP29R register ***************/
<> 144:ef7eb2e8f9f7 3420 #define RTC_BKP29R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3421
mbed_official 67:4bcbbb9fcddf 3422 /******************** Bits definition for RTC_BKP30R register ***************/
<> 144:ef7eb2e8f9f7 3423 #define RTC_BKP30R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3424
mbed_official 67:4bcbbb9fcddf 3425 /******************** Bits definition for RTC_BKP31R register ***************/
<> 144:ef7eb2e8f9f7 3426 #define RTC_BKP31R ((uint32_t)0xFFFFFFFFU)
mbed_official 67:4bcbbb9fcddf 3427
mbed_official 67:4bcbbb9fcddf 3428 /******************** Number of backup registers ******************************/
mbed_official 67:4bcbbb9fcddf 3429 #define RTC_BKP_NUMBER 32
mbed_official 67:4bcbbb9fcddf 3430
mbed_official 67:4bcbbb9fcddf 3431 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 3432 /* */
mbed_official 67:4bcbbb9fcddf 3433 /* Serial Peripheral Interface (SPI) */
mbed_official 67:4bcbbb9fcddf 3434 /* */
mbed_official 67:4bcbbb9fcddf 3435 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 3436
<> 144:ef7eb2e8f9f7 3437 /*
<> 144:ef7eb2e8f9f7 3438 * @brief Specific device feature definitions (not present on all devices in the STM32F3 family)
<> 144:ef7eb2e8f9f7 3439 */
<> 144:ef7eb2e8f9f7 3440 #define SPI_I2S_SUPPORT
<> 144:ef7eb2e8f9f7 3441
mbed_official 67:4bcbbb9fcddf 3442 /******************* Bit definition for SPI_CR1 register ********************/
<> 144:ef7eb2e8f9f7 3443 #define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!< Clock Phase */
<> 144:ef7eb2e8f9f7 3444 #define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!< Clock Polarity */
<> 144:ef7eb2e8f9f7 3445 #define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!< Master Selection */
<> 144:ef7eb2e8f9f7 3446
<> 144:ef7eb2e8f9f7 3447 #define SPI_CR1_BR ((uint32_t)0x00000038U) /*!< BR[2:0] bits (Baud Rate Control) */
<> 144:ef7eb2e8f9f7 3448 #define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3449 #define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3450 #define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3451
<> 144:ef7eb2e8f9f7 3452 #define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!< SPI Enable */
<> 144:ef7eb2e8f9f7 3453 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!< Frame Format */
<> 144:ef7eb2e8f9f7 3454 #define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!< Internal slave select */
<> 144:ef7eb2e8f9f7 3455 #define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!< Software slave management */
<> 144:ef7eb2e8f9f7 3456 #define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!< Receive only */
<> 144:ef7eb2e8f9f7 3457 #define SPI_CR1_DFF ((uint32_t)0x00000800U) /*!< Data Frame Format */
<> 144:ef7eb2e8f9f7 3458 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!< Transmit CRC next */
<> 144:ef7eb2e8f9f7 3459 #define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!< Hardware CRC calculation enable */
<> 144:ef7eb2e8f9f7 3460 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!< Output enable in bidirectional mode */
<> 144:ef7eb2e8f9f7 3461 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!< Bidirectional data mode enable */
mbed_official 67:4bcbbb9fcddf 3462
mbed_official 67:4bcbbb9fcddf 3463 /******************* Bit definition for SPI_CR2 register ********************/
<> 144:ef7eb2e8f9f7 3464 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */
<> 144:ef7eb2e8f9f7 3465 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */
<> 144:ef7eb2e8f9f7 3466 #define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */
<> 144:ef7eb2e8f9f7 3467 #define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame format */
<> 144:ef7eb2e8f9f7 3468 #define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 3469 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 3470 #define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 67:4bcbbb9fcddf 3471
mbed_official 67:4bcbbb9fcddf 3472 /******************** Bit definition for SPI_SR register ********************/
<> 144:ef7eb2e8f9f7 3473 #define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */
<> 144:ef7eb2e8f9f7 3474 #define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */
<> 144:ef7eb2e8f9f7 3475 #define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */
<> 144:ef7eb2e8f9f7 3476 #define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */
<> 144:ef7eb2e8f9f7 3477 #define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */
<> 144:ef7eb2e8f9f7 3478 #define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */
<> 144:ef7eb2e8f9f7 3479 #define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */
<> 144:ef7eb2e8f9f7 3480 #define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */
<> 144:ef7eb2e8f9f7 3481 #define SPI_SR_FRE ((uint32_t)0x00000100U) /*!<Frame format error flag */
mbed_official 67:4bcbbb9fcddf 3482
mbed_official 67:4bcbbb9fcddf 3483 /******************** Bit definition for SPI_DR register ********************/
<> 144:ef7eb2e8f9f7 3484 #define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!< Data Register */
mbed_official 67:4bcbbb9fcddf 3485
mbed_official 67:4bcbbb9fcddf 3486 /******************* Bit definition for SPI_CRCPR register ******************/
<> 144:ef7eb2e8f9f7 3487 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!< CRC polynomial register */
mbed_official 67:4bcbbb9fcddf 3488
mbed_official 67:4bcbbb9fcddf 3489 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 144:ef7eb2e8f9f7 3490 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!< Rx CRC Register */
mbed_official 67:4bcbbb9fcddf 3491
mbed_official 67:4bcbbb9fcddf 3492 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 144:ef7eb2e8f9f7 3493 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!< Tx CRC Register */
mbed_official 67:4bcbbb9fcddf 3494
mbed_official 67:4bcbbb9fcddf 3495 /****************** Bit definition for SPI_I2SCFGR register *****************/
<> 144:ef7eb2e8f9f7 3496 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001U) /*!<Channel length (number of bits per audio channel) */
<> 144:ef7eb2e8f9f7 3497
<> 144:ef7eb2e8f9f7 3498 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006U) /*!<DATLEN[1:0] bits (Data length to be transferred) */
<> 144:ef7eb2e8f9f7 3499 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3500 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3501
<> 144:ef7eb2e8f9f7 3502 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008U) /*!<steady state clock polarity */
<> 144:ef7eb2e8f9f7 3503
<> 144:ef7eb2e8f9f7 3504 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030U) /*!<I2SSTD[1:0] bits (I2S standard selection) */
<> 144:ef7eb2e8f9f7 3505 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3506 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3507
<> 144:ef7eb2e8f9f7 3508 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080U) /*!<PCM frame synchronization */
<> 144:ef7eb2e8f9f7 3509
<> 144:ef7eb2e8f9f7 3510 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300U) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
<> 144:ef7eb2e8f9f7 3511 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3512 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3513
<> 144:ef7eb2e8f9f7 3514 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400U) /*!<I2S Enable */
<> 144:ef7eb2e8f9f7 3515 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800U) /*!<I2S mode selection */
mbed_official 67:4bcbbb9fcddf 3516
mbed_official 67:4bcbbb9fcddf 3517 /****************** Bit definition for SPI_I2SPR register *******************/
<> 144:ef7eb2e8f9f7 3518 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FFU) /*!<I2S Linear prescaler */
<> 144:ef7eb2e8f9f7 3519 #define SPI_I2SPR_ODD ((uint32_t)0x00000100U) /*!<Odd factor for the prescaler */
<> 144:ef7eb2e8f9f7 3520 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200U) /*!<Master Clock Output Enable */
mbed_official 67:4bcbbb9fcddf 3521
mbed_official 67:4bcbbb9fcddf 3522 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 3523 /* */
mbed_official 67:4bcbbb9fcddf 3524 /* System Configuration (SYSCFG) */
mbed_official 67:4bcbbb9fcddf 3525 /* */
mbed_official 67:4bcbbb9fcddf 3526 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 3527 /***************** Bit definition for SYSCFG_MEMRMP register ****************/
<> 144:ef7eb2e8f9f7 3528 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003U) /*!< SYSCFG_Memory Remap Config */
<> 144:ef7eb2e8f9f7 3529 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3530 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3531 #define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300U) /*!< Boot mode Config */
<> 144:ef7eb2e8f9f7 3532 #define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3533 #define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
mbed_official 67:4bcbbb9fcddf 3534
mbed_official 67:4bcbbb9fcddf 3535 /***************** Bit definition for SYSCFG_PMC register *******************/
<> 144:ef7eb2e8f9f7 3536 #define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001U) /*!< SYSCFG PMC */
mbed_official 67:4bcbbb9fcddf 3537
mbed_official 67:4bcbbb9fcddf 3538 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 144:ef7eb2e8f9f7 3539 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000FU) /*!< EXTI 0 configuration */
<> 144:ef7eb2e8f9f7 3540 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0U) /*!< EXTI 1 configuration */
<> 144:ef7eb2e8f9f7 3541 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00U) /*!< EXTI 2 configuration */
<> 144:ef7eb2e8f9f7 3542 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000U) /*!< EXTI 3 configuration */
mbed_official 67:4bcbbb9fcddf 3543
mbed_official 67:4bcbbb9fcddf 3544 /**
mbed_official 67:4bcbbb9fcddf 3545 * @brief EXTI0 configuration
mbed_official 67:4bcbbb9fcddf 3546 */
<> 144:ef7eb2e8f9f7 3547 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!< PA[0] pin */
<> 144:ef7eb2e8f9f7 3548 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!< PB[0] pin */
<> 144:ef7eb2e8f9f7 3549 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!< PC[0] pin */
<> 144:ef7eb2e8f9f7 3550 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003U) /*!< PD[0] pin */
<> 144:ef7eb2e8f9f7 3551 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004U) /*!< PE[0] pin */
<> 144:ef7eb2e8f9f7 3552 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005U) /*!< PH[0] pin */
<> 144:ef7eb2e8f9f7 3553 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000006U) /*!< PF[0] pin */
<> 144:ef7eb2e8f9f7 3554 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000007U) /*!< PG[0] pin */
mbed_official 67:4bcbbb9fcddf 3555
mbed_official 67:4bcbbb9fcddf 3556 /**
mbed_official 67:4bcbbb9fcddf 3557 * @brief EXTI1 configuration
mbed_official 67:4bcbbb9fcddf 3558 */
<> 144:ef7eb2e8f9f7 3559 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!< PA[1] pin */
<> 144:ef7eb2e8f9f7 3560 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!< PB[1] pin */
<> 144:ef7eb2e8f9f7 3561 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!< PC[1] pin */
<> 144:ef7eb2e8f9f7 3562 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030U) /*!< PD[1] pin */
<> 144:ef7eb2e8f9f7 3563 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040U) /*!< PE[1] pin */
<> 144:ef7eb2e8f9f7 3564 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050U) /*!< PH[1] pin */
<> 144:ef7eb2e8f9f7 3565 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000060U) /*!< PF[1] pin */
<> 144:ef7eb2e8f9f7 3566 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000070U) /*!< PG[1] pin */
mbed_official 67:4bcbbb9fcddf 3567
mbed_official 67:4bcbbb9fcddf 3568 /**
mbed_official 67:4bcbbb9fcddf 3569 * @brief EXTI2 configuration
mbed_official 67:4bcbbb9fcddf 3570 */
<> 144:ef7eb2e8f9f7 3571 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!< PA[2] pin */
<> 144:ef7eb2e8f9f7 3572 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!< PB[2] pin */
<> 144:ef7eb2e8f9f7 3573 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!< PC[2] pin */
<> 144:ef7eb2e8f9f7 3574 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!< PD[2] pin */
<> 144:ef7eb2e8f9f7 3575 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400U) /*!< PE[2] pin */
<> 144:ef7eb2e8f9f7 3576 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000500U) /*!< PH[2] pin */
<> 144:ef7eb2e8f9f7 3577 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000600U) /*!< PF[2] pin */
<> 144:ef7eb2e8f9f7 3578 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000700U) /*!< PG[2] pin */
mbed_official 67:4bcbbb9fcddf 3579
mbed_official 67:4bcbbb9fcddf 3580 /**
mbed_official 67:4bcbbb9fcddf 3581 * @brief EXTI3 configuration
mbed_official 67:4bcbbb9fcddf 3582 */
<> 144:ef7eb2e8f9f7 3583 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!< PA[3] pin */
<> 144:ef7eb2e8f9f7 3584 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!< PB[3] pin */
<> 144:ef7eb2e8f9f7 3585 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!< PC[3] pin */
<> 144:ef7eb2e8f9f7 3586 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000U) /*!< PD[3] pin */
<> 144:ef7eb2e8f9f7 3587 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000U) /*!< PE[3] pin */
<> 144:ef7eb2e8f9f7 3588 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00003000U) /*!< PF[3] pin */
<> 144:ef7eb2e8f9f7 3589 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00004000U) /*!< PG[3] pin */
mbed_official 67:4bcbbb9fcddf 3590
mbed_official 67:4bcbbb9fcddf 3591 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
<> 144:ef7eb2e8f9f7 3592 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000FU) /*!< EXTI 4 configuration */
<> 144:ef7eb2e8f9f7 3593 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0U) /*!< EXTI 5 configuration */
<> 144:ef7eb2e8f9f7 3594 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00U) /*!< EXTI 6 configuration */
<> 144:ef7eb2e8f9f7 3595 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000U) /*!< EXTI 7 configuration */
mbed_official 67:4bcbbb9fcddf 3596
mbed_official 67:4bcbbb9fcddf 3597 /**
mbed_official 67:4bcbbb9fcddf 3598 * @brief EXTI4 configuration
mbed_official 67:4bcbbb9fcddf 3599 */
<> 144:ef7eb2e8f9f7 3600 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!< PA[4] pin */
<> 144:ef7eb2e8f9f7 3601 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!< PB[4] pin */
<> 144:ef7eb2e8f9f7 3602 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!< PC[4] pin */
<> 144:ef7eb2e8f9f7 3603 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003U) /*!< PD[4] pin */
<> 144:ef7eb2e8f9f7 3604 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004U) /*!< PE[4] pin */
<> 144:ef7eb2e8f9f7 3605 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000006U) /*!< PF[4] pin */
<> 144:ef7eb2e8f9f7 3606 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000007U) /*!< PG[4] pin */
mbed_official 67:4bcbbb9fcddf 3607
mbed_official 67:4bcbbb9fcddf 3608 /**
mbed_official 67:4bcbbb9fcddf 3609 * @brief EXTI5 configuration
mbed_official 67:4bcbbb9fcddf 3610 */
<> 144:ef7eb2e8f9f7 3611 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!< PA[5] pin */
<> 144:ef7eb2e8f9f7 3612 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!< PB[5] pin */
<> 144:ef7eb2e8f9f7 3613 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!< PC[5] pin */
<> 144:ef7eb2e8f9f7 3614 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030U) /*!< PD[5] pin */
<> 144:ef7eb2e8f9f7 3615 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040U) /*!< PE[5] pin */
<> 144:ef7eb2e8f9f7 3616 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000060U) /*!< PF[5] pin */
<> 144:ef7eb2e8f9f7 3617 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000070U) /*!< PG[5] pin */
mbed_official 67:4bcbbb9fcddf 3618
mbed_official 67:4bcbbb9fcddf 3619 /**
mbed_official 67:4bcbbb9fcddf 3620 * @brief EXTI6 configuration
mbed_official 67:4bcbbb9fcddf 3621 */
<> 144:ef7eb2e8f9f7 3622 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!< PA[6] pin */
<> 144:ef7eb2e8f9f7 3623 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!< PB[6] pin */
<> 144:ef7eb2e8f9f7 3624 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!< PC[6] pin */
<> 144:ef7eb2e8f9f7 3625 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300U) /*!< PD[6] pin */
<> 144:ef7eb2e8f9f7 3626 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400U) /*!< PE[6] pin */
<> 144:ef7eb2e8f9f7 3627 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000600U) /*!< PF[6] pin */
<> 144:ef7eb2e8f9f7 3628 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000700U) /*!< PG[6] pin */
mbed_official 67:4bcbbb9fcddf 3629
mbed_official 67:4bcbbb9fcddf 3630 /**
mbed_official 67:4bcbbb9fcddf 3631 * @brief EXTI7 configuration
mbed_official 67:4bcbbb9fcddf 3632 */
<> 144:ef7eb2e8f9f7 3633 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!< PA[7] pin */
<> 144:ef7eb2e8f9f7 3634 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!< PB[7] pin */
<> 144:ef7eb2e8f9f7 3635 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!< PC[7] pin */
<> 144:ef7eb2e8f9f7 3636 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000U) /*!< PD[7] pin */
<> 144:ef7eb2e8f9f7 3637 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000U) /*!< PE[7] pin */
<> 144:ef7eb2e8f9f7 3638 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00006000U) /*!< PF[7] pin */
<> 144:ef7eb2e8f9f7 3639 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00007000U) /*!< PG[7] pin */
mbed_official 67:4bcbbb9fcddf 3640
mbed_official 67:4bcbbb9fcddf 3641 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
<> 144:ef7eb2e8f9f7 3642 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000FU) /*!< EXTI 8 configuration */
<> 144:ef7eb2e8f9f7 3643 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0U) /*!< EXTI 9 configuration */
<> 144:ef7eb2e8f9f7 3644 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00U) /*!< EXTI 10 configuration */
<> 144:ef7eb2e8f9f7 3645 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000U) /*!< EXTI 11 configuration */
mbed_official 67:4bcbbb9fcddf 3646
mbed_official 67:4bcbbb9fcddf 3647 /**
mbed_official 67:4bcbbb9fcddf 3648 * @brief EXTI8 configuration
mbed_official 67:4bcbbb9fcddf 3649 */
<> 144:ef7eb2e8f9f7 3650 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!< PA[8] pin */
<> 144:ef7eb2e8f9f7 3651 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!< PB[8] pin */
<> 144:ef7eb2e8f9f7 3652 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!< PC[8] pin */
<> 144:ef7eb2e8f9f7 3653 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003U) /*!< PD[8] pin */
<> 144:ef7eb2e8f9f7 3654 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004U) /*!< PE[8] pin */
<> 144:ef7eb2e8f9f7 3655 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000006U) /*!< PF[8] pin */
<> 144:ef7eb2e8f9f7 3656 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000007U) /*!< PG[8] pin */
mbed_official 67:4bcbbb9fcddf 3657
mbed_official 67:4bcbbb9fcddf 3658 /**
mbed_official 67:4bcbbb9fcddf 3659 * @brief EXTI9 configuration
mbed_official 67:4bcbbb9fcddf 3660 */
<> 144:ef7eb2e8f9f7 3661 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!< PA[9] pin */
<> 144:ef7eb2e8f9f7 3662 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!< PB[9] pin */
<> 144:ef7eb2e8f9f7 3663 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!< PC[9] pin */
<> 144:ef7eb2e8f9f7 3664 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030U) /*!< PD[9] pin */
<> 144:ef7eb2e8f9f7 3665 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040U) /*!< PE[9] pin */
<> 144:ef7eb2e8f9f7 3666 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000060U) /*!< PF[9] pin */
<> 144:ef7eb2e8f9f7 3667 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000070U) /*!< PG[9] pin */
mbed_official 67:4bcbbb9fcddf 3668
mbed_official 67:4bcbbb9fcddf 3669 /**
mbed_official 67:4bcbbb9fcddf 3670 * @brief EXTI10 configuration
mbed_official 67:4bcbbb9fcddf 3671 */
<> 144:ef7eb2e8f9f7 3672 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!< PA[10] pin */
<> 144:ef7eb2e8f9f7 3673 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!< PB[10] pin */
<> 144:ef7eb2e8f9f7 3674 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!< PC[10] pin */
<> 144:ef7eb2e8f9f7 3675 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300U) /*!< PD[10] pin */
<> 144:ef7eb2e8f9f7 3676 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400U) /*!< PE[10] pin */
<> 144:ef7eb2e8f9f7 3677 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000600U) /*!< PF[10] pin */
<> 144:ef7eb2e8f9f7 3678 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000700U) /*!< PG[10] pin */
mbed_official 67:4bcbbb9fcddf 3679
mbed_official 67:4bcbbb9fcddf 3680 /**
mbed_official 67:4bcbbb9fcddf 3681 * @brief EXTI11 configuration
mbed_official 67:4bcbbb9fcddf 3682 */
<> 144:ef7eb2e8f9f7 3683 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!< PA[11] pin */
<> 144:ef7eb2e8f9f7 3684 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!< PB[11] pin */
<> 144:ef7eb2e8f9f7 3685 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!< PC[11] pin */
<> 144:ef7eb2e8f9f7 3686 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000U) /*!< PD[11] pin */
<> 144:ef7eb2e8f9f7 3687 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000U) /*!< PE[11] pin */
<> 144:ef7eb2e8f9f7 3688 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00006000U) /*!< PF[11] pin */
<> 144:ef7eb2e8f9f7 3689 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00007000U) /*!< PG[11] pin */
mbed_official 67:4bcbbb9fcddf 3690
mbed_official 67:4bcbbb9fcddf 3691 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
<> 144:ef7eb2e8f9f7 3692 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000FU) /*!< EXTI 12 configuration */
<> 144:ef7eb2e8f9f7 3693 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0U) /*!< EXTI 13 configuration */
<> 144:ef7eb2e8f9f7 3694 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00U) /*!< EXTI 14 configuration */
<> 144:ef7eb2e8f9f7 3695 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000U) /*!< EXTI 15 configuration */
mbed_official 67:4bcbbb9fcddf 3696
mbed_official 67:4bcbbb9fcddf 3697 /**
mbed_official 67:4bcbbb9fcddf 3698 * @brief EXTI12 configuration
mbed_official 67:4bcbbb9fcddf 3699 */
<> 144:ef7eb2e8f9f7 3700 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!< PA[12] pin */
<> 144:ef7eb2e8f9f7 3701 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!< PB[12] pin */
<> 144:ef7eb2e8f9f7 3702 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!< PC[12] pin */
<> 144:ef7eb2e8f9f7 3703 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003U) /*!< PD[12] pin */
<> 144:ef7eb2e8f9f7 3704 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004U) /*!< PE[12] pin */
<> 144:ef7eb2e8f9f7 3705 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000006U) /*!< PF[12] pin */
<> 144:ef7eb2e8f9f7 3706 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000007U) /*!< PG[12] pin */
mbed_official 67:4bcbbb9fcddf 3707
mbed_official 67:4bcbbb9fcddf 3708 /**
mbed_official 67:4bcbbb9fcddf 3709 * @brief EXTI13 configuration
mbed_official 67:4bcbbb9fcddf 3710 */
<> 144:ef7eb2e8f9f7 3711 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!< PA[13] pin */
<> 144:ef7eb2e8f9f7 3712 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!< PB[13] pin */
<> 144:ef7eb2e8f9f7 3713 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!< PC[13] pin */
<> 144:ef7eb2e8f9f7 3714 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030U) /*!< PD[13] pin */
<> 144:ef7eb2e8f9f7 3715 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040U) /*!< PE[13] pin */
<> 144:ef7eb2e8f9f7 3716 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000060U) /*!< PF[13] pin */
<> 144:ef7eb2e8f9f7 3717 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000070U) /*!< PG[13] pin */
mbed_official 67:4bcbbb9fcddf 3718
mbed_official 67:4bcbbb9fcddf 3719 /**
mbed_official 67:4bcbbb9fcddf 3720 * @brief EXTI14 configuration
mbed_official 67:4bcbbb9fcddf 3721 */
<> 144:ef7eb2e8f9f7 3722 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!< PA[14] pin */
<> 144:ef7eb2e8f9f7 3723 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!< PB[14] pin */
<> 144:ef7eb2e8f9f7 3724 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!< PC[14] pin */
<> 144:ef7eb2e8f9f7 3725 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300U) /*!< PD[14] pin */
<> 144:ef7eb2e8f9f7 3726 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400U) /*!< PE[14] pin */
<> 144:ef7eb2e8f9f7 3727 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000600U) /*!< PF[14] pin */
<> 144:ef7eb2e8f9f7 3728 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000700U) /*!< PG[14] pin */
mbed_official 67:4bcbbb9fcddf 3729
mbed_official 67:4bcbbb9fcddf 3730 /**
mbed_official 67:4bcbbb9fcddf 3731 * @brief EXTI15 configuration
mbed_official 67:4bcbbb9fcddf 3732 */
<> 144:ef7eb2e8f9f7 3733 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!< PA[15] pin */
<> 144:ef7eb2e8f9f7 3734 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!< PB[15] pin */
<> 144:ef7eb2e8f9f7 3735 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!< PC[15] pin */
<> 144:ef7eb2e8f9f7 3736 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000U) /*!< PD[15] pin */
<> 144:ef7eb2e8f9f7 3737 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000U) /*!< PE[15] pin */
<> 144:ef7eb2e8f9f7 3738 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00006000U) /*!< PF[15] pin */
<> 144:ef7eb2e8f9f7 3739 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00007000U) /*!< PG[15] pin */
mbed_official 67:4bcbbb9fcddf 3740
mbed_official 67:4bcbbb9fcddf 3741 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 3742 /* */
mbed_official 67:4bcbbb9fcddf 3743 /* Routing Interface (RI) */
mbed_official 67:4bcbbb9fcddf 3744 /* */
mbed_official 67:4bcbbb9fcddf 3745 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 3746
mbed_official 67:4bcbbb9fcddf 3747 /******************** Bit definition for RI_ICR register ********************/
<> 144:ef7eb2e8f9f7 3748 #define RI_ICR_IC1OS ((uint32_t)0x0000000FU) /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
<> 144:ef7eb2e8f9f7 3749 #define RI_ICR_IC1OS_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3750 #define RI_ICR_IC1OS_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3751 #define RI_ICR_IC1OS_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3752 #define RI_ICR_IC1OS_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3753
<> 144:ef7eb2e8f9f7 3754 #define RI_ICR_IC2OS ((uint32_t)0x000000F0U) /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
<> 144:ef7eb2e8f9f7 3755 #define RI_ICR_IC2OS_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3756 #define RI_ICR_IC2OS_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3757 #define RI_ICR_IC2OS_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3758 #define RI_ICR_IC2OS_3 ((uint32_t)0x00000080U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3759
<> 144:ef7eb2e8f9f7 3760 #define RI_ICR_IC3OS ((uint32_t)0x00000F00U) /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
<> 144:ef7eb2e8f9f7 3761 #define RI_ICR_IC3OS_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3762 #define RI_ICR_IC3OS_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3763 #define RI_ICR_IC3OS_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3764 #define RI_ICR_IC3OS_3 ((uint32_t)0x00000800U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3765
<> 144:ef7eb2e8f9f7 3766 #define RI_ICR_IC4OS ((uint32_t)0x0000F000U) /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
<> 144:ef7eb2e8f9f7 3767 #define RI_ICR_IC4OS_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3768 #define RI_ICR_IC4OS_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3769 #define RI_ICR_IC4OS_2 ((uint32_t)0x00004000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3770 #define RI_ICR_IC4OS_3 ((uint32_t)0x00008000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3771
<> 144:ef7eb2e8f9f7 3772 #define RI_ICR_TIM ((uint32_t)0x00030000U) /*!< TIM[3:0] bits (Timers select bits) */
<> 144:ef7eb2e8f9f7 3773 #define RI_ICR_TIM_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3774 #define RI_ICR_TIM_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3775
<> 144:ef7eb2e8f9f7 3776 #define RI_ICR_IC1 ((uint32_t)0x00040000U) /*!< Input capture 1 */
<> 144:ef7eb2e8f9f7 3777 #define RI_ICR_IC2 ((uint32_t)0x00080000U) /*!< Input capture 2 */
<> 144:ef7eb2e8f9f7 3778 #define RI_ICR_IC3 ((uint32_t)0x00100000U) /*!< Input capture 3 */
<> 144:ef7eb2e8f9f7 3779 #define RI_ICR_IC4 ((uint32_t)0x00200000U) /*!< Input capture 4 */
mbed_official 67:4bcbbb9fcddf 3780
mbed_official 67:4bcbbb9fcddf 3781 /******************** Bit definition for RI_ASCR1 register ********************/
<> 144:ef7eb2e8f9f7 3782 #define RI_ASCR1_CH ((uint32_t)0x7BFDFFFFU) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
<> 144:ef7eb2e8f9f7 3783 #define RI_ASCR1_CH_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3784 #define RI_ASCR1_CH_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3785 #define RI_ASCR1_CH_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3786 #define RI_ASCR1_CH_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3787 #define RI_ASCR1_CH_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 3788 #define RI_ASCR1_CH_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 3789 #define RI_ASCR1_CH_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 3790 #define RI_ASCR1_CH_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 3791 #define RI_ASCR1_CH_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 3792 #define RI_ASCR1_CH_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 3793 #define RI_ASCR1_CH_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 3794 #define RI_ASCR1_CH_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 3795 #define RI_ASCR1_CH_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 3796 #define RI_ASCR1_CH_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 3797 #define RI_ASCR1_CH_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 3798 #define RI_ASCR1_CH_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
<> 144:ef7eb2e8f9f7 3799 #define RI_ASCR1_CH_31 ((uint32_t)0x00010000U) /*!< Bit 16 */
<> 144:ef7eb2e8f9f7 3800 #define RI_ASCR1_CH_18 ((uint32_t)0x00040000U) /*!< Bit 18 */
<> 144:ef7eb2e8f9f7 3801 #define RI_ASCR1_CH_19 ((uint32_t)0x00080000U) /*!< Bit 19 */
<> 144:ef7eb2e8f9f7 3802 #define RI_ASCR1_CH_20 ((uint32_t)0x00100000U) /*!< Bit 20 */
<> 144:ef7eb2e8f9f7 3803 #define RI_ASCR1_CH_21 ((uint32_t)0x00200000U) /*!< Bit 21 */
<> 144:ef7eb2e8f9f7 3804 #define RI_ASCR1_CH_22 ((uint32_t)0x00400000U) /*!< Bit 22 */
<> 144:ef7eb2e8f9f7 3805 #define RI_ASCR1_CH_23 ((uint32_t)0x00800000U) /*!< Bit 23 */
<> 144:ef7eb2e8f9f7 3806 #define RI_ASCR1_CH_24 ((uint32_t)0x01000000U) /*!< Bit 24 */
<> 144:ef7eb2e8f9f7 3807 #define RI_ASCR1_CH_25 ((uint32_t)0x02000000U) /*!< Bit 25 */
<> 144:ef7eb2e8f9f7 3808 #define RI_ASCR1_VCOMP ((uint32_t)0x04000000U) /*!< ADC analog switch selection for internal node to COMP1 */
<> 144:ef7eb2e8f9f7 3809 #define RI_ASCR1_CH_27 ((uint32_t)0x08000000U) /*!< Bit 27 */
<> 144:ef7eb2e8f9f7 3810 #define RI_ASCR1_CH_28 ((uint32_t)0x10000000U) /*!< Bit 28 */
<> 144:ef7eb2e8f9f7 3811 #define RI_ASCR1_CH_29 ((uint32_t)0x20000000U) /*!< Bit 29 */
<> 144:ef7eb2e8f9f7 3812 #define RI_ASCR1_CH_30 ((uint32_t)0x40000000U) /*!< Bit 30 */
<> 144:ef7eb2e8f9f7 3813 #define RI_ASCR1_SCM ((uint32_t)0x80000000U) /*!< I/O Switch control mode */
mbed_official 67:4bcbbb9fcddf 3814
mbed_official 67:4bcbbb9fcddf 3815 /******************** Bit definition for RI_ASCR2 register ********************/
<> 144:ef7eb2e8f9f7 3816 #define RI_ASCR2_GR10_1 ((uint32_t)0x00000001U) /*!< GR10-1 selection bit */
<> 144:ef7eb2e8f9f7 3817 #define RI_ASCR2_GR10_2 ((uint32_t)0x00000002U) /*!< GR10-2 selection bit */
<> 144:ef7eb2e8f9f7 3818 #define RI_ASCR2_GR10_3 ((uint32_t)0x00000004U) /*!< GR10-3 selection bit */
<> 144:ef7eb2e8f9f7 3819 #define RI_ASCR2_GR10_4 ((uint32_t)0x00000008U) /*!< GR10-4 selection bit */
<> 144:ef7eb2e8f9f7 3820 #define RI_ASCR2_GR6_1 ((uint32_t)0x00000010U) /*!< GR6-1 selection bit */
<> 144:ef7eb2e8f9f7 3821 #define RI_ASCR2_GR6_2 ((uint32_t)0x00000020U) /*!< GR6-2 selection bit */
<> 144:ef7eb2e8f9f7 3822 #define RI_ASCR2_GR5_1 ((uint32_t)0x00000040U) /*!< GR5-1 selection bit */
<> 144:ef7eb2e8f9f7 3823 #define RI_ASCR2_GR5_2 ((uint32_t)0x00000080U) /*!< GR5-2 selection bit */
<> 144:ef7eb2e8f9f7 3824 #define RI_ASCR2_GR5_3 ((uint32_t)0x00000100U) /*!< GR5-3 selection bit */
<> 144:ef7eb2e8f9f7 3825 #define RI_ASCR2_GR4_1 ((uint32_t)0x00000200U) /*!< GR4-1 selection bit */
<> 144:ef7eb2e8f9f7 3826 #define RI_ASCR2_GR4_2 ((uint32_t)0x00000400U) /*!< GR4-2 selection bit */
<> 144:ef7eb2e8f9f7 3827 #define RI_ASCR2_GR4_3 ((uint32_t)0x00000800U) /*!< GR4-3 selection bit */
<> 144:ef7eb2e8f9f7 3828 #define RI_ASCR2_GR4_4 ((uint32_t)0x00008000U) /*!< GR4-4 selection bit */
<> 144:ef7eb2e8f9f7 3829 #define RI_ASCR2_CH0b ((uint32_t)0x00010000U) /*!< CH0b selection bit */
<> 144:ef7eb2e8f9f7 3830 #define RI_ASCR2_GR6_3 ((uint32_t)0x08000000U) /*!< GR6-3 selection bit */
<> 144:ef7eb2e8f9f7 3831 #define RI_ASCR2_GR6_4 ((uint32_t)0x10000000U) /*!< GR6-4 selection bit */
mbed_official 67:4bcbbb9fcddf 3832
mbed_official 67:4bcbbb9fcddf 3833 /******************** Bit definition for RI_HYSCR1 register ********************/
<> 144:ef7eb2e8f9f7 3834 #define RI_HYSCR1_PA ((uint32_t)0x0000FFFFU) /*!< PA[15:0] Port A Hysteresis selection */
<> 144:ef7eb2e8f9f7 3835 #define RI_HYSCR1_PA_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3836 #define RI_HYSCR1_PA_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3837 #define RI_HYSCR1_PA_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3838 #define RI_HYSCR1_PA_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3839 #define RI_HYSCR1_PA_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 3840 #define RI_HYSCR1_PA_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 3841 #define RI_HYSCR1_PA_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 3842 #define RI_HYSCR1_PA_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 3843 #define RI_HYSCR1_PA_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 3844 #define RI_HYSCR1_PA_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 3845 #define RI_HYSCR1_PA_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 3846 #define RI_HYSCR1_PA_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 3847 #define RI_HYSCR1_PA_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 3848 #define RI_HYSCR1_PA_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 3849 #define RI_HYSCR1_PA_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 3850 #define RI_HYSCR1_PA_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
<> 144:ef7eb2e8f9f7 3851
<> 144:ef7eb2e8f9f7 3852 #define RI_HYSCR1_PB ((uint32_t)0xFFFF0000U) /*!< PB[15:0] Port B Hysteresis selection */
<> 144:ef7eb2e8f9f7 3853 #define RI_HYSCR1_PB_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3854 #define RI_HYSCR1_PB_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3855 #define RI_HYSCR1_PB_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3856 #define RI_HYSCR1_PB_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3857 #define RI_HYSCR1_PB_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 3858 #define RI_HYSCR1_PB_5 ((uint32_t)0x00200000U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 3859 #define RI_HYSCR1_PB_6 ((uint32_t)0x00400000U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 3860 #define RI_HYSCR1_PB_7 ((uint32_t)0x00800000U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 3861 #define RI_HYSCR1_PB_8 ((uint32_t)0x01000000U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 3862 #define RI_HYSCR1_PB_9 ((uint32_t)0x02000000U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 3863 #define RI_HYSCR1_PB_10 ((uint32_t)0x04000000U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 3864 #define RI_HYSCR1_PB_11 ((uint32_t)0x08000000U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 3865 #define RI_HYSCR1_PB_12 ((uint32_t)0x10000000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 3866 #define RI_HYSCR1_PB_13 ((uint32_t)0x20000000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 3867 #define RI_HYSCR1_PB_14 ((uint32_t)0x40000000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 3868 #define RI_HYSCR1_PB_15 ((uint32_t)0x80000000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 3869
mbed_official 67:4bcbbb9fcddf 3870 /******************** Bit definition for RI_HYSCR2 register ********************/
<> 144:ef7eb2e8f9f7 3871 #define RI_HYSCR2_PC ((uint32_t)0x0000FFFFU) /*!< PC[15:0] Port C Hysteresis selection */
<> 144:ef7eb2e8f9f7 3872 #define RI_HYSCR2_PC_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3873 #define RI_HYSCR2_PC_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3874 #define RI_HYSCR2_PC_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3875 #define RI_HYSCR2_PC_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3876 #define RI_HYSCR2_PC_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 3877 #define RI_HYSCR2_PC_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 3878 #define RI_HYSCR2_PC_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 3879 #define RI_HYSCR2_PC_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 3880 #define RI_HYSCR2_PC_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 3881 #define RI_HYSCR2_PC_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 3882 #define RI_HYSCR2_PC_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 3883 #define RI_HYSCR2_PC_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 3884 #define RI_HYSCR2_PC_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 3885 #define RI_HYSCR2_PC_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 3886 #define RI_HYSCR2_PC_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 3887 #define RI_HYSCR2_PC_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
<> 144:ef7eb2e8f9f7 3888
<> 144:ef7eb2e8f9f7 3889 #define RI_HYSCR2_PD ((uint32_t)0xFFFF0000U) /*!< PD[15:0] Port D Hysteresis selection */
<> 144:ef7eb2e8f9f7 3890 #define RI_HYSCR2_PD_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3891 #define RI_HYSCR2_PD_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3892 #define RI_HYSCR2_PD_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3893 #define RI_HYSCR2_PD_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3894 #define RI_HYSCR2_PD_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 3895 #define RI_HYSCR2_PD_5 ((uint32_t)0x00200000U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 3896 #define RI_HYSCR2_PD_6 ((uint32_t)0x00400000U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 3897 #define RI_HYSCR2_PD_7 ((uint32_t)0x00800000U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 3898 #define RI_HYSCR2_PD_8 ((uint32_t)0x01000000U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 3899 #define RI_HYSCR2_PD_9 ((uint32_t)0x02000000U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 3900 #define RI_HYSCR2_PD_10 ((uint32_t)0x04000000U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 3901 #define RI_HYSCR2_PD_11 ((uint32_t)0x08000000U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 3902 #define RI_HYSCR2_PD_12 ((uint32_t)0x10000000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 3903 #define RI_HYSCR2_PD_13 ((uint32_t)0x20000000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 3904 #define RI_HYSCR2_PD_14 ((uint32_t)0x40000000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 3905 #define RI_HYSCR2_PD_15 ((uint32_t)0x80000000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 3906
mbed_official 67:4bcbbb9fcddf 3907 /******************** Bit definition for RI_HYSCR3 register ********************/
<> 144:ef7eb2e8f9f7 3908 #define RI_HYSCR3_PE ((uint32_t)0x0000FFFFU) /*!< PE[15:0] Port E Hysteresis selection */
<> 144:ef7eb2e8f9f7 3909 #define RI_HYSCR3_PE_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3910 #define RI_HYSCR3_PE_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3911 #define RI_HYSCR3_PE_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3912 #define RI_HYSCR3_PE_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3913 #define RI_HYSCR3_PE_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 3914 #define RI_HYSCR3_PE_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 3915 #define RI_HYSCR3_PE_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 3916 #define RI_HYSCR3_PE_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 3917 #define RI_HYSCR3_PE_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 3918 #define RI_HYSCR3_PE_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 3919 #define RI_HYSCR3_PE_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 3920 #define RI_HYSCR3_PE_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 3921 #define RI_HYSCR3_PE_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 3922 #define RI_HYSCR3_PE_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 3923 #define RI_HYSCR3_PE_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 3924 #define RI_HYSCR3_PE_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 3925
mbed_official 67:4bcbbb9fcddf 3926 /******************** Bit definition for RI_ASMR1 register ********************/
<> 144:ef7eb2e8f9f7 3927 #define RI_ASMR1_PA ((uint32_t)0x0000FFFFU) /*!< PA[15:0] Port A selection*/
<> 144:ef7eb2e8f9f7 3928 #define RI_ASMR1_PA_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3929 #define RI_ASMR1_PA_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3930 #define RI_ASMR1_PA_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3931 #define RI_ASMR1_PA_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3932 #define RI_ASMR1_PA_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 3933 #define RI_ASMR1_PA_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 3934 #define RI_ASMR1_PA_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 3935 #define RI_ASMR1_PA_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 3936 #define RI_ASMR1_PA_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 3937 #define RI_ASMR1_PA_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 3938 #define RI_ASMR1_PA_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 3939 #define RI_ASMR1_PA_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 3940 #define RI_ASMR1_PA_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 3941 #define RI_ASMR1_PA_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 3942 #define RI_ASMR1_PA_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 3943 #define RI_ASMR1_PA_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 3944
mbed_official 67:4bcbbb9fcddf 3945 /******************** Bit definition for RI_CMR1 register ********************/
<> 144:ef7eb2e8f9f7 3946 #define RI_CMR1_PA ((uint32_t)0x0000FFFFU) /*!< PA[15:0] Port A selection*/
<> 144:ef7eb2e8f9f7 3947 #define RI_CMR1_PA_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3948 #define RI_CMR1_PA_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3949 #define RI_CMR1_PA_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3950 #define RI_CMR1_PA_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3951 #define RI_CMR1_PA_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 3952 #define RI_CMR1_PA_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 3953 #define RI_CMR1_PA_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 3954 #define RI_CMR1_PA_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 3955 #define RI_CMR1_PA_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 3956 #define RI_CMR1_PA_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 3957 #define RI_CMR1_PA_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 3958 #define RI_CMR1_PA_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 3959 #define RI_CMR1_PA_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 3960 #define RI_CMR1_PA_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 3961 #define RI_CMR1_PA_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 3962 #define RI_CMR1_PA_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 3963
mbed_official 67:4bcbbb9fcddf 3964 /******************** Bit definition for RI_CICR1 register ********************/
<> 144:ef7eb2e8f9f7 3965 #define RI_CICR1_PA ((uint32_t)0x0000FFFFU) /*!< PA[15:0] Port A selection*/
<> 144:ef7eb2e8f9f7 3966 #define RI_CICR1_PA_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3967 #define RI_CICR1_PA_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3968 #define RI_CICR1_PA_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3969 #define RI_CICR1_PA_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3970 #define RI_CICR1_PA_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 3971 #define RI_CICR1_PA_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 3972 #define RI_CICR1_PA_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 3973 #define RI_CICR1_PA_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 3974 #define RI_CICR1_PA_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 3975 #define RI_CICR1_PA_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 3976 #define RI_CICR1_PA_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 3977 #define RI_CICR1_PA_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 3978 #define RI_CICR1_PA_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 3979 #define RI_CICR1_PA_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 3980 #define RI_CICR1_PA_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 3981 #define RI_CICR1_PA_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 3982
mbed_official 67:4bcbbb9fcddf 3983 /******************** Bit definition for RI_ASMR2 register ********************/
<> 144:ef7eb2e8f9f7 3984 #define RI_ASMR2_PB ((uint32_t)0x0000FFFFU) /*!< PB[15:0] Port B selection */
<> 144:ef7eb2e8f9f7 3985 #define RI_ASMR2_PB_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3986 #define RI_ASMR2_PB_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3987 #define RI_ASMR2_PB_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3988 #define RI_ASMR2_PB_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 3989 #define RI_ASMR2_PB_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 3990 #define RI_ASMR2_PB_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 3991 #define RI_ASMR2_PB_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 3992 #define RI_ASMR2_PB_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 3993 #define RI_ASMR2_PB_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 3994 #define RI_ASMR2_PB_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 3995 #define RI_ASMR2_PB_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 3996 #define RI_ASMR2_PB_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 3997 #define RI_ASMR2_PB_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 3998 #define RI_ASMR2_PB_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 3999 #define RI_ASMR2_PB_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 4000 #define RI_ASMR2_PB_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 4001
mbed_official 67:4bcbbb9fcddf 4002 /******************** Bit definition for RI_CMR2 register ********************/
<> 144:ef7eb2e8f9f7 4003 #define RI_CMR2_PB ((uint32_t)0x0000FFFFU) /*!< PB[15:0] Port B selection */
<> 144:ef7eb2e8f9f7 4004 #define RI_CMR2_PB_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4005 #define RI_CMR2_PB_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4006 #define RI_CMR2_PB_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4007 #define RI_CMR2_PB_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4008 #define RI_CMR2_PB_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4009 #define RI_CMR2_PB_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 4010 #define RI_CMR2_PB_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 4011 #define RI_CMR2_PB_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 4012 #define RI_CMR2_PB_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 4013 #define RI_CMR2_PB_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 4014 #define RI_CMR2_PB_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 4015 #define RI_CMR2_PB_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 4016 #define RI_CMR2_PB_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 4017 #define RI_CMR2_PB_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 4018 #define RI_CMR2_PB_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 4019 #define RI_CMR2_PB_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 4020
mbed_official 67:4bcbbb9fcddf 4021 /******************** Bit definition for RI_CICR2 register ********************/
<> 144:ef7eb2e8f9f7 4022 #define RI_CICR2_PB ((uint32_t)0x0000FFFFU) /*!< PB[15:0] Port B selection */
<> 144:ef7eb2e8f9f7 4023 #define RI_CICR2_PB_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4024 #define RI_CICR2_PB_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4025 #define RI_CICR2_PB_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4026 #define RI_CICR2_PB_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4027 #define RI_CICR2_PB_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4028 #define RI_CICR2_PB_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 4029 #define RI_CICR2_PB_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 4030 #define RI_CICR2_PB_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 4031 #define RI_CICR2_PB_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 4032 #define RI_CICR2_PB_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 4033 #define RI_CICR2_PB_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 4034 #define RI_CICR2_PB_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 4035 #define RI_CICR2_PB_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 4036 #define RI_CICR2_PB_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 4037 #define RI_CICR2_PB_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 4038 #define RI_CICR2_PB_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 4039
mbed_official 67:4bcbbb9fcddf 4040 /******************** Bit definition for RI_ASMR3 register ********************/
<> 144:ef7eb2e8f9f7 4041 #define RI_ASMR3_PC ((uint32_t)0x0000FFFFU) /*!< PC[15:0] Port C selection */
<> 144:ef7eb2e8f9f7 4042 #define RI_ASMR3_PC_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4043 #define RI_ASMR3_PC_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4044 #define RI_ASMR3_PC_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4045 #define RI_ASMR3_PC_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4046 #define RI_ASMR3_PC_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4047 #define RI_ASMR3_PC_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 4048 #define RI_ASMR3_PC_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 4049 #define RI_ASMR3_PC_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 4050 #define RI_ASMR3_PC_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 4051 #define RI_ASMR3_PC_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 4052 #define RI_ASMR3_PC_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 4053 #define RI_ASMR3_PC_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 4054 #define RI_ASMR3_PC_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 4055 #define RI_ASMR3_PC_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 4056 #define RI_ASMR3_PC_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 4057 #define RI_ASMR3_PC_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 4058
mbed_official 67:4bcbbb9fcddf 4059 /******************** Bit definition for RI_CMR3 register ********************/
<> 144:ef7eb2e8f9f7 4060 #define RI_CMR3_PC ((uint32_t)0x0000FFFFU) /*!< PC[15:0] Port C selection */
<> 144:ef7eb2e8f9f7 4061 #define RI_CMR3_PC_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4062 #define RI_CMR3_PC_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4063 #define RI_CMR3_PC_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4064 #define RI_CMR3_PC_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4065 #define RI_CMR3_PC_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4066 #define RI_CMR3_PC_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 4067 #define RI_CMR3_PC_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 4068 #define RI_CMR3_PC_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 4069 #define RI_CMR3_PC_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 4070 #define RI_CMR3_PC_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 4071 #define RI_CMR3_PC_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 4072 #define RI_CMR3_PC_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 4073 #define RI_CMR3_PC_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 4074 #define RI_CMR3_PC_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 4075 #define RI_CMR3_PC_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 4076 #define RI_CMR3_PC_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 4077
mbed_official 67:4bcbbb9fcddf 4078 /******************** Bit definition for RI_CICR3 register ********************/
<> 144:ef7eb2e8f9f7 4079 #define RI_CICR3_PC ((uint32_t)0x0000FFFFU) /*!< PC[15:0] Port C selection */
<> 144:ef7eb2e8f9f7 4080 #define RI_CICR3_PC_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4081 #define RI_CICR3_PC_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4082 #define RI_CICR3_PC_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4083 #define RI_CICR3_PC_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4084 #define RI_CICR3_PC_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4085 #define RI_CICR3_PC_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 4086 #define RI_CICR3_PC_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 4087 #define RI_CICR3_PC_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 4088 #define RI_CICR3_PC_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
<> 144:ef7eb2e8f9f7 4089 #define RI_CICR3_PC_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
<> 144:ef7eb2e8f9f7 4090 #define RI_CICR3_PC_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
<> 144:ef7eb2e8f9f7 4091 #define RI_CICR3_PC_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
<> 144:ef7eb2e8f9f7 4092 #define RI_CICR3_PC_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
<> 144:ef7eb2e8f9f7 4093 #define RI_CICR3_PC_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
<> 144:ef7eb2e8f9f7 4094 #define RI_CICR3_PC_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
<> 144:ef7eb2e8f9f7 4095 #define RI_CICR3_PC_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
mbed_official 67:4bcbbb9fcddf 4096
mbed_official 67:4bcbbb9fcddf 4097 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 4098 /* */
mbed_official 67:4bcbbb9fcddf 4099 /* Timers (TIM) */
mbed_official 67:4bcbbb9fcddf 4100 /* */
mbed_official 67:4bcbbb9fcddf 4101 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 4102
mbed_official 67:4bcbbb9fcddf 4103 /******************* Bit definition for TIM_CR1 register ********************/
<> 144:ef7eb2e8f9f7 4104 #define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!<Counter enable */
<> 144:ef7eb2e8f9f7 4105 #define TIM_CR1_UDIS ((uint32_t)0x00000002U) /*!<Update disable */
<> 144:ef7eb2e8f9f7 4106 #define TIM_CR1_URS ((uint32_t)0x00000004U) /*!<Update request source */
<> 144:ef7eb2e8f9f7 4107 #define TIM_CR1_OPM ((uint32_t)0x00000008U) /*!<One pulse mode */
<> 144:ef7eb2e8f9f7 4108 #define TIM_CR1_DIR ((uint32_t)0x00000010U) /*!<Direction */
<> 144:ef7eb2e8f9f7 4109
<> 144:ef7eb2e8f9f7 4110 #define TIM_CR1_CMS ((uint32_t)0x00000060U) /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 144:ef7eb2e8f9f7 4111 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4112 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4113
<> 144:ef7eb2e8f9f7 4114 #define TIM_CR1_ARPE ((uint32_t)0x00000080U) /*!<Auto-reload preload enable */
<> 144:ef7eb2e8f9f7 4115
<> 144:ef7eb2e8f9f7 4116 #define TIM_CR1_CKD ((uint32_t)0x00000300U) /*!<CKD[1:0] bits (clock division) */
<> 144:ef7eb2e8f9f7 4117 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4118 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
mbed_official 67:4bcbbb9fcddf 4119
mbed_official 67:4bcbbb9fcddf 4120 /******************* Bit definition for TIM_CR2 register ********************/
<> 144:ef7eb2e8f9f7 4121 #define TIM_CR2_CCDS ((uint32_t)0x00000008U) /*!<Capture/Compare DMA Selection */
<> 144:ef7eb2e8f9f7 4122
<> 144:ef7eb2e8f9f7 4123 #define TIM_CR2_MMS ((uint32_t)0x00000070U) /*!<MMS[2:0] bits (Master Mode Selection) */
<> 144:ef7eb2e8f9f7 4124 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4125 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4126 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4127
<> 144:ef7eb2e8f9f7 4128 #define TIM_CR2_TI1S ((uint32_t)0x00000080U) /*!<TI1 Selection */
mbed_official 67:4bcbbb9fcddf 4129
mbed_official 67:4bcbbb9fcddf 4130 /******************* Bit definition for TIM_SMCR register *******************/
<> 144:ef7eb2e8f9f7 4131 #define TIM_SMCR_SMS ((uint32_t)0x00000007U) /*!<SMS[2:0] bits (Slave mode selection) */
<> 144:ef7eb2e8f9f7 4132 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4133 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4134 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4135
<> 144:ef7eb2e8f9f7 4136 #define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /*!< OCREF clear selection */
<> 144:ef7eb2e8f9f7 4137
<> 144:ef7eb2e8f9f7 4138 #define TIM_SMCR_TS ((uint32_t)0x00000070U) /*!<TS[2:0] bits (Trigger selection) */
<> 144:ef7eb2e8f9f7 4139 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4140 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4141 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4142
<> 144:ef7eb2e8f9f7 4143 #define TIM_SMCR_MSM ((uint32_t)0x00000080U) /*!<Master/slave mode */
<> 144:ef7eb2e8f9f7 4144
<> 144:ef7eb2e8f9f7 4145 #define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /*!<ETF[3:0] bits (External trigger filter) */
<> 144:ef7eb2e8f9f7 4146 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4147 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4148 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4149 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4150
<> 144:ef7eb2e8f9f7 4151 #define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 144:ef7eb2e8f9f7 4152 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4153 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4154
<> 144:ef7eb2e8f9f7 4155 #define TIM_SMCR_ECE ((uint32_t)0x00004000U) /*!<External clock enable */
<> 144:ef7eb2e8f9f7 4156 #define TIM_SMCR_ETP ((uint32_t)0x00008000U) /*!<External trigger polarity */
mbed_official 67:4bcbbb9fcddf 4157
mbed_official 67:4bcbbb9fcddf 4158 /******************* Bit definition for TIM_DIER register *******************/
<> 144:ef7eb2e8f9f7 4159 #define TIM_DIER_UIE ((uint32_t)0x00000001U) /*!<Update interrupt enable */
<> 144:ef7eb2e8f9f7 4160 #define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt enable */
<> 144:ef7eb2e8f9f7 4161 #define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt enable */
<> 144:ef7eb2e8f9f7 4162 #define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt enable */
<> 144:ef7eb2e8f9f7 4163 #define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt enable */
<> 144:ef7eb2e8f9f7 4164 #define TIM_DIER_TIE ((uint32_t)0x00000040U) /*!<Trigger interrupt enable */
<> 144:ef7eb2e8f9f7 4165 #define TIM_DIER_UDE ((uint32_t)0x00000100U) /*!<Update DMA request enable */
<> 144:ef7eb2e8f9f7 4166 #define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /*!<Capture/Compare 1 DMA request enable */
<> 144:ef7eb2e8f9f7 4167 #define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /*!<Capture/Compare 2 DMA request enable */
<> 144:ef7eb2e8f9f7 4168 #define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /*!<Capture/Compare 3 DMA request enable */
<> 144:ef7eb2e8f9f7 4169 #define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /*!<Capture/Compare 4 DMA request enable */
<> 144:ef7eb2e8f9f7 4170 #define TIM_DIER_COMDE ((uint16_t)0x2000U) /*!<COM DMA request enable */
<> 144:ef7eb2e8f9f7 4171 #define TIM_DIER_TDE ((uint32_t)0x00004000U) /*!<Trigger DMA request enable */
mbed_official 67:4bcbbb9fcddf 4172
mbed_official 67:4bcbbb9fcddf 4173 /******************** Bit definition for TIM_SR register ********************/
<> 144:ef7eb2e8f9f7 4174 #define TIM_SR_UIF ((uint32_t)0x00000001U) /*!<Update interrupt Flag */
<> 144:ef7eb2e8f9f7 4175 #define TIM_SR_CC1IF ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt Flag */
<> 144:ef7eb2e8f9f7 4176 #define TIM_SR_CC2IF ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt Flag */
<> 144:ef7eb2e8f9f7 4177 #define TIM_SR_CC3IF ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt Flag */
<> 144:ef7eb2e8f9f7 4178 #define TIM_SR_CC4IF ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt Flag */
<> 144:ef7eb2e8f9f7 4179 #define TIM_SR_TIF ((uint32_t)0x00000040U) /*!<Trigger interrupt Flag */
<> 144:ef7eb2e8f9f7 4180 #define TIM_SR_CC1OF ((uint32_t)0x00000200U) /*!<Capture/Compare 1 Overcapture Flag */
<> 144:ef7eb2e8f9f7 4181 #define TIM_SR_CC2OF ((uint32_t)0x00000400U) /*!<Capture/Compare 2 Overcapture Flag */
<> 144:ef7eb2e8f9f7 4182 #define TIM_SR_CC3OF ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Overcapture Flag */
<> 144:ef7eb2e8f9f7 4183 #define TIM_SR_CC4OF ((uint32_t)0x00001000U) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 67:4bcbbb9fcddf 4184
mbed_official 67:4bcbbb9fcddf 4185 /******************* Bit definition for TIM_EGR register ********************/
<> 144:ef7eb2e8f9f7 4186 #define TIM_EGR_UG ((uint32_t)0x00000001U) /*!<Update Generation */
<> 144:ef7eb2e8f9f7 4187 #define TIM_EGR_CC1G ((uint32_t)0x00000002U) /*!<Capture/Compare 1 Generation */
<> 144:ef7eb2e8f9f7 4188 #define TIM_EGR_CC2G ((uint32_t)0x00000004U) /*!<Capture/Compare 2 Generation */
<> 144:ef7eb2e8f9f7 4189 #define TIM_EGR_CC3G ((uint32_t)0x00000008U) /*!<Capture/Compare 3 Generation */
<> 144:ef7eb2e8f9f7 4190 #define TIM_EGR_CC4G ((uint32_t)0x00000010U) /*!<Capture/Compare 4 Generation */
<> 144:ef7eb2e8f9f7 4191 #define TIM_EGR_TG ((uint32_t)0x00000040U) /*!<Trigger Generation */
mbed_official 67:4bcbbb9fcddf 4192
mbed_official 67:4bcbbb9fcddf 4193 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 144:ef7eb2e8f9f7 4194 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 144:ef7eb2e8f9f7 4195 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4196 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4197
<> 144:ef7eb2e8f9f7 4198 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /*!<Output Compare 1 Fast enable */
<> 144:ef7eb2e8f9f7 4199 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /*!<Output Compare 1 Preload enable */
<> 144:ef7eb2e8f9f7 4200
<> 144:ef7eb2e8f9f7 4201 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070U) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 144:ef7eb2e8f9f7 4202 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4203 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4204 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4205
<> 144:ef7eb2e8f9f7 4206 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /*!<Output Compare 1Clear Enable */
<> 144:ef7eb2e8f9f7 4207
<> 144:ef7eb2e8f9f7 4208 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 144:ef7eb2e8f9f7 4209 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4210 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4211
<> 144:ef7eb2e8f9f7 4212 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /*!<Output Compare 2 Fast enable */
<> 144:ef7eb2e8f9f7 4213 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /*!<Output Compare 2 Preload enable */
<> 144:ef7eb2e8f9f7 4214
<> 144:ef7eb2e8f9f7 4215 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000U) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 144:ef7eb2e8f9f7 4216 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4217 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4218 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4219
<> 144:ef7eb2e8f9f7 4220 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /*!<Output Compare 2 Clear Enable */
mbed_official 67:4bcbbb9fcddf 4221
mbed_official 67:4bcbbb9fcddf 4222 /*----------------------------------------------------------------------------*/
mbed_official 67:4bcbbb9fcddf 4223
<> 144:ef7eb2e8f9f7 4224 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 144:ef7eb2e8f9f7 4225 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4226 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4227
<> 144:ef7eb2e8f9f7 4228 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 144:ef7eb2e8f9f7 4229 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4230 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4231 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4232 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4233
<> 144:ef7eb2e8f9f7 4234 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 144:ef7eb2e8f9f7 4235 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4236 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4237
<> 144:ef7eb2e8f9f7 4238 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 144:ef7eb2e8f9f7 4239 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4240 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4241 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4242 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
mbed_official 67:4bcbbb9fcddf 4243
mbed_official 67:4bcbbb9fcddf 4244 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 144:ef7eb2e8f9f7 4245 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 144:ef7eb2e8f9f7 4246 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4247 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4248
<> 144:ef7eb2e8f9f7 4249 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /*!<Output Compare 3 Fast enable */
<> 144:ef7eb2e8f9f7 4250 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /*!<Output Compare 3 Preload enable */
<> 144:ef7eb2e8f9f7 4251
<> 144:ef7eb2e8f9f7 4252 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070U) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 144:ef7eb2e8f9f7 4253 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4254 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4255 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4256
<> 144:ef7eb2e8f9f7 4257 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /*!<Output Compare 3 Clear Enable */
<> 144:ef7eb2e8f9f7 4258
<> 144:ef7eb2e8f9f7 4259 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 144:ef7eb2e8f9f7 4260 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4261 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4262
<> 144:ef7eb2e8f9f7 4263 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /*!<Output Compare 4 Fast enable */
<> 144:ef7eb2e8f9f7 4264 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /*!<Output Compare 4 Preload enable */
<> 144:ef7eb2e8f9f7 4265
<> 144:ef7eb2e8f9f7 4266 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000U) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 144:ef7eb2e8f9f7 4267 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4268 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4269 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4270
<> 144:ef7eb2e8f9f7 4271 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /*!<Output Compare 4 Clear Enable */
mbed_official 67:4bcbbb9fcddf 4272
mbed_official 67:4bcbbb9fcddf 4273 /*----------------------------------------------------------------------------*/
mbed_official 67:4bcbbb9fcddf 4274
<> 144:ef7eb2e8f9f7 4275 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 144:ef7eb2e8f9f7 4276 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4277 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4278
<> 144:ef7eb2e8f9f7 4279 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 144:ef7eb2e8f9f7 4280 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4281 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4282 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4283 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4284
<> 144:ef7eb2e8f9f7 4285 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 144:ef7eb2e8f9f7 4286 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4287 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4288
<> 144:ef7eb2e8f9f7 4289 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 144:ef7eb2e8f9f7 4290 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4291 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4292 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4293 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
mbed_official 67:4bcbbb9fcddf 4294
mbed_official 67:4bcbbb9fcddf 4295 /******************* Bit definition for TIM_CCER register *******************/
<> 144:ef7eb2e8f9f7 4296 #define TIM_CCER_CC1E ((uint32_t)0x00000001U) /*!<Capture/Compare 1 output enable */
<> 144:ef7eb2e8f9f7 4297 #define TIM_CCER_CC1P ((uint32_t)0x00000002U) /*!<Capture/Compare 1 output Polarity */
<> 144:ef7eb2e8f9f7 4298 #define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /*!<Capture/Compare 1 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 4299 #define TIM_CCER_CC2E ((uint32_t)0x00000010U) /*!<Capture/Compare 2 output enable */
<> 144:ef7eb2e8f9f7 4300 #define TIM_CCER_CC2P ((uint32_t)0x00000020U) /*!<Capture/Compare 2 output Polarity */
<> 144:ef7eb2e8f9f7 4301 #define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /*!<Capture/Compare 2 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 4302 #define TIM_CCER_CC3E ((uint32_t)0x00000100U) /*!<Capture/Compare 3 output enable */
<> 144:ef7eb2e8f9f7 4303 #define TIM_CCER_CC3P ((uint32_t)0x00000200U) /*!<Capture/Compare 3 output Polarity */
<> 144:ef7eb2e8f9f7 4304 #define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 4305 #define TIM_CCER_CC4E ((uint32_t)0x00001000U) /*!<Capture/Compare 4 output enable */
<> 144:ef7eb2e8f9f7 4306 #define TIM_CCER_CC4P ((uint32_t)0x00002000U) /*!<Capture/Compare 4 output Polarity */
<> 144:ef7eb2e8f9f7 4307 #define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 67:4bcbbb9fcddf 4308
mbed_official 67:4bcbbb9fcddf 4309 /******************* Bit definition for TIM_CNT register ********************/
<> 144:ef7eb2e8f9f7 4310 #define TIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!<Counter Value */
mbed_official 67:4bcbbb9fcddf 4311
mbed_official 67:4bcbbb9fcddf 4312 /******************* Bit definition for TIM_PSC register ********************/
<> 144:ef7eb2e8f9f7 4313 #define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /*!<Prescaler Value */
mbed_official 67:4bcbbb9fcddf 4314
mbed_official 67:4bcbbb9fcddf 4315 /******************* Bit definition for TIM_ARR register ********************/
<> 144:ef7eb2e8f9f7 4316 #define TIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!<actual auto-reload Value */
mbed_official 67:4bcbbb9fcddf 4317
mbed_official 67:4bcbbb9fcddf 4318 /******************* Bit definition for TIM_CCR1 register *******************/
<> 144:ef7eb2e8f9f7 4319 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 1 Value */
mbed_official 67:4bcbbb9fcddf 4320
mbed_official 67:4bcbbb9fcddf 4321 /******************* Bit definition for TIM_CCR2 register *******************/
<> 144:ef7eb2e8f9f7 4322 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 2 Value */
mbed_official 67:4bcbbb9fcddf 4323
mbed_official 67:4bcbbb9fcddf 4324 /******************* Bit definition for TIM_CCR3 register *******************/
<> 144:ef7eb2e8f9f7 4325 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 3 Value */
mbed_official 67:4bcbbb9fcddf 4326
mbed_official 67:4bcbbb9fcddf 4327 /******************* Bit definition for TIM_CCR4 register *******************/
<> 144:ef7eb2e8f9f7 4328 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 4 Value */
mbed_official 67:4bcbbb9fcddf 4329
mbed_official 67:4bcbbb9fcddf 4330 /******************* Bit definition for TIM_DCR register ********************/
<> 144:ef7eb2e8f9f7 4331 #define TIM_DCR_DBA ((uint32_t)0x0000001FU) /*!<DBA[4:0] bits (DMA Base Address) */
<> 144:ef7eb2e8f9f7 4332 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4333 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4334 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4335 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4336 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4337
<> 144:ef7eb2e8f9f7 4338 #define TIM_DCR_DBL ((uint32_t)0x00001F00U) /*!<DBL[4:0] bits (DMA Burst Length) */
<> 144:ef7eb2e8f9f7 4339 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4340 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4341 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4342 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4343 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
mbed_official 67:4bcbbb9fcddf 4344
mbed_official 67:4bcbbb9fcddf 4345 /******************* Bit definition for TIM_DMAR register *******************/
<> 144:ef7eb2e8f9f7 4346 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /*!<DMA register for burst accesses */
mbed_official 67:4bcbbb9fcddf 4347
mbed_official 67:4bcbbb9fcddf 4348 /******************* Bit definition for TIM_OR register *********************/
<> 144:ef7eb2e8f9f7 4349 #define TIM_OR_TI1RMP ((uint32_t)0x00000003U) /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
<> 144:ef7eb2e8f9f7 4350 #define TIM_OR_TI1RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4351 #define TIM_OR_TI1RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4352
<> 144:ef7eb2e8f9f7 4353 #define TIM_OR_ETR_RMP ((uint32_t)0x00000004U) /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
<> 144:ef7eb2e8f9f7 4354 #define TIM_OR_TI1_RMP_RI ((uint32_t)0x00000008U) /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
mbed_official 67:4bcbbb9fcddf 4355
mbed_official 67:4bcbbb9fcddf 4356 /*----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 4357 #define TIM9_OR_ITR1_RMP ((uint32_t)0x00000004U) /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
mbed_official 67:4bcbbb9fcddf 4358
mbed_official 67:4bcbbb9fcddf 4359 /*----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 4360 #define TIM2_OR_ITR1_RMP ((uint32_t)0x00000001U) /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
mbed_official 67:4bcbbb9fcddf 4361
mbed_official 67:4bcbbb9fcddf 4362 /*----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 4363 #define TIM3_OR_ITR2_RMP ((uint32_t)0x00000001U) /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
mbed_official 67:4bcbbb9fcddf 4364
mbed_official 67:4bcbbb9fcddf 4365 /*----------------------------------------------------------------------------*/
mbed_official 67:4bcbbb9fcddf 4366
mbed_official 67:4bcbbb9fcddf 4367
mbed_official 67:4bcbbb9fcddf 4368 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 4369 /* */
mbed_official 67:4bcbbb9fcddf 4370 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 67:4bcbbb9fcddf 4371 /* */
mbed_official 67:4bcbbb9fcddf 4372 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 4373
mbed_official 67:4bcbbb9fcddf 4374 /******************* Bit definition for USART_SR register *******************/
<> 144:ef7eb2e8f9f7 4375 #define USART_SR_PE ((uint32_t)0x00000001U) /*!< Parity Error */
<> 144:ef7eb2e8f9f7 4376 #define USART_SR_FE ((uint32_t)0x00000002U) /*!< Framing Error */
<> 144:ef7eb2e8f9f7 4377 #define USART_SR_NE ((uint32_t)0x00000004U) /*!< Noise Error Flag */
<> 144:ef7eb2e8f9f7 4378 #define USART_SR_ORE ((uint32_t)0x00000008U) /*!< OverRun Error */
<> 144:ef7eb2e8f9f7 4379 #define USART_SR_IDLE ((uint32_t)0x00000010U) /*!< IDLE line detected */
<> 144:ef7eb2e8f9f7 4380 #define USART_SR_RXNE ((uint32_t)0x00000020U) /*!< Read Data Register Not Empty */
<> 144:ef7eb2e8f9f7 4381 #define USART_SR_TC ((uint32_t)0x00000040U) /*!< Transmission Complete */
<> 144:ef7eb2e8f9f7 4382 #define USART_SR_TXE ((uint32_t)0x00000080U) /*!< Transmit Data Register Empty */
<> 144:ef7eb2e8f9f7 4383 #define USART_SR_LBD ((uint32_t)0x00000100U) /*!< LIN Break Detection Flag */
<> 144:ef7eb2e8f9f7 4384 #define USART_SR_CTS ((uint32_t)0x00000200U) /*!< CTS Flag */
mbed_official 67:4bcbbb9fcddf 4385
mbed_official 67:4bcbbb9fcddf 4386 /******************* Bit definition for USART_DR register *******************/
<> 144:ef7eb2e8f9f7 4387 #define USART_DR_DR ((uint32_t)0x000001FFU) /*!< Data value */
mbed_official 67:4bcbbb9fcddf 4388
mbed_official 67:4bcbbb9fcddf 4389 /****************** Bit definition for USART_BRR register *******************/
<> 144:ef7eb2e8f9f7 4390 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000FU) /*!< Fraction of USARTDIV */
<> 144:ef7eb2e8f9f7 4391 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0U) /*!< Mantissa of USARTDIV */
mbed_official 67:4bcbbb9fcddf 4392
mbed_official 67:4bcbbb9fcddf 4393 /****************** Bit definition for USART_CR1 register *******************/
<> 144:ef7eb2e8f9f7 4394 #define USART_CR1_SBK ((uint32_t)0x00000001U) /*!< Send Break */
<> 144:ef7eb2e8f9f7 4395 #define USART_CR1_RWU ((uint32_t)0x00000002U) /*!< Receiver wakeup */
<> 144:ef7eb2e8f9f7 4396 #define USART_CR1_RE ((uint32_t)0x00000004U) /*!< Receiver Enable */
<> 144:ef7eb2e8f9f7 4397 #define USART_CR1_TE ((uint32_t)0x00000008U) /*!< Transmitter Enable */
<> 144:ef7eb2e8f9f7 4398 #define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /*!< IDLE Interrupt Enable */
<> 144:ef7eb2e8f9f7 4399 #define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /*!< RXNE Interrupt Enable */
<> 144:ef7eb2e8f9f7 4400 #define USART_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transmission Complete Interrupt Enable */
<> 144:ef7eb2e8f9f7 4401 #define USART_CR1_TXEIE ((uint32_t)0x00000080U) /*!< PE Interrupt Enable */
<> 144:ef7eb2e8f9f7 4402 #define USART_CR1_PEIE ((uint32_t)0x00000100U) /*!< PE Interrupt Enable */
<> 144:ef7eb2e8f9f7 4403 #define USART_CR1_PS ((uint32_t)0x00000200U) /*!< Parity Selection */
<> 144:ef7eb2e8f9f7 4404 #define USART_CR1_PCE ((uint32_t)0x00000400U) /*!< Parity Control Enable */
<> 144:ef7eb2e8f9f7 4405 #define USART_CR1_WAKE ((uint32_t)0x00000800U) /*!< Wakeup method */
<> 144:ef7eb2e8f9f7 4406 #define USART_CR1_M ((uint32_t)0x00001000U) /*!< Word length */
<> 144:ef7eb2e8f9f7 4407 #define USART_CR1_UE ((uint32_t)0x00002000U) /*!< USART Enable */
<> 144:ef7eb2e8f9f7 4408 #define USART_CR1_OVER8 ((uint32_t)0x00008000U) /*!< Oversampling by 8-bit mode */
mbed_official 67:4bcbbb9fcddf 4409
mbed_official 67:4bcbbb9fcddf 4410 /****************** Bit definition for USART_CR2 register *******************/
<> 144:ef7eb2e8f9f7 4411 #define USART_CR2_ADD ((uint32_t)0x0000000FU) /*!< Address of the USART node */
<> 144:ef7eb2e8f9f7 4412 #define USART_CR2_LBDL ((uint32_t)0x00000020U) /*!< LIN Break Detection Length */
<> 144:ef7eb2e8f9f7 4413 #define USART_CR2_LBDIE ((uint32_t)0x00000040U) /*!< LIN Break Detection Interrupt Enable */
<> 144:ef7eb2e8f9f7 4414 #define USART_CR2_LBCL ((uint32_t)0x00000100U) /*!< Last Bit Clock pulse */
<> 144:ef7eb2e8f9f7 4415 #define USART_CR2_CPHA ((uint32_t)0x00000200U) /*!< Clock Phase */
<> 144:ef7eb2e8f9f7 4416 #define USART_CR2_CPOL ((uint32_t)0x00000400U) /*!< Clock Polarity */
<> 144:ef7eb2e8f9f7 4417 #define USART_CR2_CLKEN ((uint32_t)0x00000800U) /*!< Clock Enable */
<> 144:ef7eb2e8f9f7 4418
<> 144:ef7eb2e8f9f7 4419 #define USART_CR2_STOP ((uint32_t)0x00003000U) /*!< STOP[1:0] bits (STOP bits) */
<> 144:ef7eb2e8f9f7 4420 #define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4421 #define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4422
<> 144:ef7eb2e8f9f7 4423 #define USART_CR2_LINEN ((uint32_t)0x00004000U) /*!< LIN mode enable */
mbed_official 67:4bcbbb9fcddf 4424
mbed_official 67:4bcbbb9fcddf 4425 /****************** Bit definition for USART_CR3 register *******************/
<> 144:ef7eb2e8f9f7 4426 #define USART_CR3_EIE ((uint32_t)0x00000001U) /*!< Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 4427 #define USART_CR3_IREN ((uint32_t)0x00000002U) /*!< IrDA mode Enable */
<> 144:ef7eb2e8f9f7 4428 #define USART_CR3_IRLP ((uint32_t)0x00000004U) /*!< IrDA Low-Power */
<> 144:ef7eb2e8f9f7 4429 #define USART_CR3_HDSEL ((uint32_t)0x00000008U) /*!< Half-Duplex Selection */
<> 144:ef7eb2e8f9f7 4430 #define USART_CR3_NACK ((uint32_t)0x00000010U) /*!< Smartcard NACK enable */
<> 144:ef7eb2e8f9f7 4431 #define USART_CR3_SCEN ((uint32_t)0x00000020U) /*!< Smartcard mode enable */
<> 144:ef7eb2e8f9f7 4432 #define USART_CR3_DMAR ((uint32_t)0x00000040U) /*!< DMA Enable Receiver */
<> 144:ef7eb2e8f9f7 4433 #define USART_CR3_DMAT ((uint32_t)0x00000080U) /*!< DMA Enable Transmitter */
<> 144:ef7eb2e8f9f7 4434 #define USART_CR3_RTSE ((uint32_t)0x00000100U) /*!< RTS Enable */
<> 144:ef7eb2e8f9f7 4435 #define USART_CR3_CTSE ((uint32_t)0x00000200U) /*!< CTS Enable */
<> 144:ef7eb2e8f9f7 4436 #define USART_CR3_CTSIE ((uint32_t)0x00000400U) /*!< CTS Interrupt Enable */
<> 144:ef7eb2e8f9f7 4437 #define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /*!< One sample bit method enable */
mbed_official 67:4bcbbb9fcddf 4438
mbed_official 67:4bcbbb9fcddf 4439 /****************** Bit definition for USART_GTPR register ******************/
<> 144:ef7eb2e8f9f7 4440 #define USART_GTPR_PSC ((uint32_t)0x000000FFU) /*!< PSC[7:0] bits (Prescaler value) */
<> 144:ef7eb2e8f9f7 4441 #define USART_GTPR_PSC_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4442 #define USART_GTPR_PSC_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4443 #define USART_GTPR_PSC_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4444 #define USART_GTPR_PSC_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4445 #define USART_GTPR_PSC_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4446 #define USART_GTPR_PSC_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 4447 #define USART_GTPR_PSC_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 4448 #define USART_GTPR_PSC_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 4449
<> 144:ef7eb2e8f9f7 4450 #define USART_GTPR_GT ((uint32_t)0x0000FF00U) /*!< Guard time value */
mbed_official 67:4bcbbb9fcddf 4451
mbed_official 67:4bcbbb9fcddf 4452 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 4453 /* */
mbed_official 67:4bcbbb9fcddf 4454 /* Universal Serial Bus (USB) */
mbed_official 67:4bcbbb9fcddf 4455 /* */
mbed_official 67:4bcbbb9fcddf 4456 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 4457
mbed_official 67:4bcbbb9fcddf 4458 /*!<Endpoint-specific registers */
mbed_official 67:4bcbbb9fcddf 4459
mbed_official 67:4bcbbb9fcddf 4460 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
<> 144:ef7eb2e8f9f7 4461 #define USB_EP1R (USB_BASE + 0x00000004U) /*!< endpoint 1 register address */
<> 144:ef7eb2e8f9f7 4462 #define USB_EP2R (USB_BASE + 0x00000008U) /*!< endpoint 2 register address */
<> 144:ef7eb2e8f9f7 4463 #define USB_EP3R (USB_BASE + 0x0000000CU) /*!< endpoint 3 register address */
<> 144:ef7eb2e8f9f7 4464 #define USB_EP4R (USB_BASE + 0x00000010U) /*!< endpoint 4 register address */
<> 144:ef7eb2e8f9f7 4465 #define USB_EP5R (USB_BASE + 0x00000014U) /*!< endpoint 5 register address */
<> 144:ef7eb2e8f9f7 4466 #define USB_EP6R (USB_BASE + 0x00000018U) /*!< endpoint 6 register address */
<> 144:ef7eb2e8f9f7 4467 #define USB_EP7R (USB_BASE + 0x0000001CU) /*!< endpoint 7 register address */
mbed_official 67:4bcbbb9fcddf 4468
mbed_official 67:4bcbbb9fcddf 4469 /* bit positions */
<> 144:ef7eb2e8f9f7 4470 #define USB_EP_CTR_RX ((uint32_t)0x00008000U) /*!< EndPoint Correct TRansfer RX */
<> 144:ef7eb2e8f9f7 4471 #define USB_EP_DTOG_RX ((uint32_t)0x00004000U) /*!< EndPoint Data TOGGLE RX */
<> 144:ef7eb2e8f9f7 4472 #define USB_EPRX_STAT ((uint32_t)0x00003000U) /*!< EndPoint RX STATus bit field */
<> 144:ef7eb2e8f9f7 4473 #define USB_EP_SETUP ((uint32_t)0x00000800U) /*!< EndPoint SETUP */
<> 144:ef7eb2e8f9f7 4474 #define USB_EP_T_FIELD ((uint32_t)0x00000600U) /*!< EndPoint TYPE */
<> 144:ef7eb2e8f9f7 4475 #define USB_EP_KIND ((uint32_t)0x00000100U) /*!< EndPoint KIND */
<> 144:ef7eb2e8f9f7 4476 #define USB_EP_CTR_TX ((uint32_t)0x00000080U) /*!< EndPoint Correct TRansfer TX */
<> 144:ef7eb2e8f9f7 4477 #define USB_EP_DTOG_TX ((uint32_t)0x00000040U) /*!< EndPoint Data TOGGLE TX */
<> 144:ef7eb2e8f9f7 4478 #define USB_EPTX_STAT ((uint32_t)0x00000030U) /*!< EndPoint TX STATus bit field */
<> 144:ef7eb2e8f9f7 4479 #define USB_EPADDR_FIELD ((uint32_t)0x0000000FU) /*!< EndPoint ADDRess FIELD */
mbed_official 67:4bcbbb9fcddf 4480
mbed_official 67:4bcbbb9fcddf 4481 /* EndPoint REGister MASK (no toggle fields) */
mbed_official 67:4bcbbb9fcddf 4482 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
mbed_official 67:4bcbbb9fcddf 4483 /*!< EP_TYPE[1:0] EndPoint TYPE */
<> 144:ef7eb2e8f9f7 4484 #define USB_EP_TYPE_MASK ((uint32_t)0x00000600U) /*!< EndPoint TYPE Mask */
<> 144:ef7eb2e8f9f7 4485 #define USB_EP_BULK ((uint32_t)0x00000000U) /*!< EndPoint BULK */
<> 144:ef7eb2e8f9f7 4486 #define USB_EP_CONTROL ((uint32_t)0x00000200U) /*!< EndPoint CONTROL */
<> 144:ef7eb2e8f9f7 4487 #define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400U) /*!< EndPoint ISOCHRONOUS */
<> 144:ef7eb2e8f9f7 4488 #define USB_EP_INTERRUPT ((uint32_t)0x00000600U) /*!< EndPoint INTERRUPT */
mbed_official 67:4bcbbb9fcddf 4489 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
mbed_official 67:4bcbbb9fcddf 4490
mbed_official 67:4bcbbb9fcddf 4491 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
mbed_official 67:4bcbbb9fcddf 4492 /*!< STAT_TX[1:0] STATus for TX transfer */
<> 144:ef7eb2e8f9f7 4493 #define USB_EP_TX_DIS ((uint32_t)0x00000000U) /*!< EndPoint TX DISabled */
<> 144:ef7eb2e8f9f7 4494 #define USB_EP_TX_STALL ((uint32_t)0x00000010U) /*!< EndPoint TX STALLed */
<> 144:ef7eb2e8f9f7 4495 #define USB_EP_TX_NAK ((uint32_t)0x00000020U) /*!< EndPoint TX NAKed */
<> 144:ef7eb2e8f9f7 4496 #define USB_EP_TX_VALID ((uint32_t)0x00000030U) /*!< EndPoint TX VALID */
<> 144:ef7eb2e8f9f7 4497 #define USB_EPTX_DTOG1 ((uint32_t)0x00000010U) /*!< EndPoint TX Data TOGgle bit1 */
<> 144:ef7eb2e8f9f7 4498 #define USB_EPTX_DTOG2 ((uint32_t)0x00000020U) /*!< EndPoint TX Data TOGgle bit2 */
mbed_official 67:4bcbbb9fcddf 4499 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
mbed_official 67:4bcbbb9fcddf 4500 /*!< STAT_RX[1:0] STATus for RX transfer */
<> 144:ef7eb2e8f9f7 4501 #define USB_EP_RX_DIS ((uint32_t)0x00000000U) /*!< EndPoint RX DISabled */
<> 144:ef7eb2e8f9f7 4502 #define USB_EP_RX_STALL ((uint32_t)0x00001000U) /*!< EndPoint RX STALLed */
<> 144:ef7eb2e8f9f7 4503 #define USB_EP_RX_NAK ((uint32_t)0x00002000U) /*!< EndPoint RX NAKed */
<> 144:ef7eb2e8f9f7 4504 #define USB_EP_RX_VALID ((uint32_t)0x00003000U) /*!< EndPoint RX VALID */
<> 144:ef7eb2e8f9f7 4505 #define USB_EPRX_DTOG1 ((uint32_t)0x00001000U) /*!< EndPoint RX Data TOGgle bit1 */
<> 144:ef7eb2e8f9f7 4506 #define USB_EPRX_DTOG2 ((uint32_t)0x00002000U) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 67:4bcbbb9fcddf 4507 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
mbed_official 67:4bcbbb9fcddf 4508
mbed_official 67:4bcbbb9fcddf 4509 /******************* Bit definition for USB_EP0R register *******************/
<> 144:ef7eb2e8f9f7 4510 #define USB_EP0R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
<> 144:ef7eb2e8f9f7 4511
<> 144:ef7eb2e8f9f7 4512 #define USB_EP0R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 144:ef7eb2e8f9f7 4513 #define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4514 #define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4515
<> 144:ef7eb2e8f9f7 4516 #define USB_EP0R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
<> 144:ef7eb2e8f9f7 4517 #define USB_EP0R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
<> 144:ef7eb2e8f9f7 4518 #define USB_EP0R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
<> 144:ef7eb2e8f9f7 4519
<> 144:ef7eb2e8f9f7 4520 #define USB_EP0R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 144:ef7eb2e8f9f7 4521 #define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4522 #define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4523
<> 144:ef7eb2e8f9f7 4524 #define USB_EP0R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
<> 144:ef7eb2e8f9f7 4525
<> 144:ef7eb2e8f9f7 4526 #define USB_EP0R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 144:ef7eb2e8f9f7 4527 #define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4528 #define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4529
<> 144:ef7eb2e8f9f7 4530 #define USB_EP0R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
<> 144:ef7eb2e8f9f7 4531 #define USB_EP0R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
mbed_official 67:4bcbbb9fcddf 4532
mbed_official 67:4bcbbb9fcddf 4533 /******************* Bit definition for USB_EP1R register *******************/
<> 144:ef7eb2e8f9f7 4534 #define USB_EP1R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
<> 144:ef7eb2e8f9f7 4535
<> 144:ef7eb2e8f9f7 4536 #define USB_EP1R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 144:ef7eb2e8f9f7 4537 #define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4538 #define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4539
<> 144:ef7eb2e8f9f7 4540 #define USB_EP1R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
<> 144:ef7eb2e8f9f7 4541 #define USB_EP1R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
<> 144:ef7eb2e8f9f7 4542 #define USB_EP1R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
<> 144:ef7eb2e8f9f7 4543
<> 144:ef7eb2e8f9f7 4544 #define USB_EP1R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 144:ef7eb2e8f9f7 4545 #define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4546 #define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4547
<> 144:ef7eb2e8f9f7 4548 #define USB_EP1R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
<> 144:ef7eb2e8f9f7 4549
<> 144:ef7eb2e8f9f7 4550 #define USB_EP1R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 144:ef7eb2e8f9f7 4551 #define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4552 #define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4553
<> 144:ef7eb2e8f9f7 4554 #define USB_EP1R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
<> 144:ef7eb2e8f9f7 4555 #define USB_EP1R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
mbed_official 67:4bcbbb9fcddf 4556
mbed_official 67:4bcbbb9fcddf 4557 /******************* Bit definition for USB_EP2R register *******************/
<> 144:ef7eb2e8f9f7 4558 #define USB_EP2R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
<> 144:ef7eb2e8f9f7 4559
<> 144:ef7eb2e8f9f7 4560 #define USB_EP2R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 144:ef7eb2e8f9f7 4561 #define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4562 #define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4563
<> 144:ef7eb2e8f9f7 4564 #define USB_EP2R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
<> 144:ef7eb2e8f9f7 4565 #define USB_EP2R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
<> 144:ef7eb2e8f9f7 4566 #define USB_EP2R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
<> 144:ef7eb2e8f9f7 4567
<> 144:ef7eb2e8f9f7 4568 #define USB_EP2R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 144:ef7eb2e8f9f7 4569 #define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4570 #define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4571
<> 144:ef7eb2e8f9f7 4572 #define USB_EP2R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
<> 144:ef7eb2e8f9f7 4573
<> 144:ef7eb2e8f9f7 4574 #define USB_EP2R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 144:ef7eb2e8f9f7 4575 #define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4576 #define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4577
<> 144:ef7eb2e8f9f7 4578 #define USB_EP2R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
<> 144:ef7eb2e8f9f7 4579 #define USB_EP2R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
mbed_official 67:4bcbbb9fcddf 4580
mbed_official 67:4bcbbb9fcddf 4581 /******************* Bit definition for USB_EP3R register *******************/
<> 144:ef7eb2e8f9f7 4582 #define USB_EP3R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
<> 144:ef7eb2e8f9f7 4583
<> 144:ef7eb2e8f9f7 4584 #define USB_EP3R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 144:ef7eb2e8f9f7 4585 #define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4586 #define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4587
<> 144:ef7eb2e8f9f7 4588 #define USB_EP3R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
<> 144:ef7eb2e8f9f7 4589 #define USB_EP3R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
<> 144:ef7eb2e8f9f7 4590 #define USB_EP3R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
<> 144:ef7eb2e8f9f7 4591
<> 144:ef7eb2e8f9f7 4592 #define USB_EP3R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 144:ef7eb2e8f9f7 4593 #define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4594 #define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4595
<> 144:ef7eb2e8f9f7 4596 #define USB_EP3R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
<> 144:ef7eb2e8f9f7 4597
<> 144:ef7eb2e8f9f7 4598 #define USB_EP3R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 144:ef7eb2e8f9f7 4599 #define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4600 #define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4601
<> 144:ef7eb2e8f9f7 4602 #define USB_EP3R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
<> 144:ef7eb2e8f9f7 4603 #define USB_EP3R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
mbed_official 67:4bcbbb9fcddf 4604
mbed_official 67:4bcbbb9fcddf 4605 /******************* Bit definition for USB_EP4R register *******************/
<> 144:ef7eb2e8f9f7 4606 #define USB_EP4R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
<> 144:ef7eb2e8f9f7 4607
<> 144:ef7eb2e8f9f7 4608 #define USB_EP4R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 144:ef7eb2e8f9f7 4609 #define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4610 #define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4611
<> 144:ef7eb2e8f9f7 4612 #define USB_EP4R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
<> 144:ef7eb2e8f9f7 4613 #define USB_EP4R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
<> 144:ef7eb2e8f9f7 4614 #define USB_EP4R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
<> 144:ef7eb2e8f9f7 4615
<> 144:ef7eb2e8f9f7 4616 #define USB_EP4R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 144:ef7eb2e8f9f7 4617 #define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4618 #define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4619
<> 144:ef7eb2e8f9f7 4620 #define USB_EP4R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
<> 144:ef7eb2e8f9f7 4621
<> 144:ef7eb2e8f9f7 4622 #define USB_EP4R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 144:ef7eb2e8f9f7 4623 #define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4624 #define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4625
<> 144:ef7eb2e8f9f7 4626 #define USB_EP4R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
<> 144:ef7eb2e8f9f7 4627 #define USB_EP4R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
mbed_official 67:4bcbbb9fcddf 4628
mbed_official 67:4bcbbb9fcddf 4629 /******************* Bit definition for USB_EP5R register *******************/
<> 144:ef7eb2e8f9f7 4630 #define USB_EP5R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
<> 144:ef7eb2e8f9f7 4631
<> 144:ef7eb2e8f9f7 4632 #define USB_EP5R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 144:ef7eb2e8f9f7 4633 #define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4634 #define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4635
<> 144:ef7eb2e8f9f7 4636 #define USB_EP5R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
<> 144:ef7eb2e8f9f7 4637 #define USB_EP5R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
<> 144:ef7eb2e8f9f7 4638 #define USB_EP5R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
<> 144:ef7eb2e8f9f7 4639
<> 144:ef7eb2e8f9f7 4640 #define USB_EP5R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 144:ef7eb2e8f9f7 4641 #define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4642 #define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4643
<> 144:ef7eb2e8f9f7 4644 #define USB_EP5R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
<> 144:ef7eb2e8f9f7 4645
<> 144:ef7eb2e8f9f7 4646 #define USB_EP5R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 144:ef7eb2e8f9f7 4647 #define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4648 #define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4649
<> 144:ef7eb2e8f9f7 4650 #define USB_EP5R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
<> 144:ef7eb2e8f9f7 4651 #define USB_EP5R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
mbed_official 67:4bcbbb9fcddf 4652
mbed_official 67:4bcbbb9fcddf 4653 /******************* Bit definition for USB_EP6R register *******************/
<> 144:ef7eb2e8f9f7 4654 #define USB_EP6R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
<> 144:ef7eb2e8f9f7 4655
<> 144:ef7eb2e8f9f7 4656 #define USB_EP6R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 144:ef7eb2e8f9f7 4657 #define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4658 #define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4659
<> 144:ef7eb2e8f9f7 4660 #define USB_EP6R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
<> 144:ef7eb2e8f9f7 4661 #define USB_EP6R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
<> 144:ef7eb2e8f9f7 4662 #define USB_EP6R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
<> 144:ef7eb2e8f9f7 4663
<> 144:ef7eb2e8f9f7 4664 #define USB_EP6R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 144:ef7eb2e8f9f7 4665 #define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4666 #define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4667
<> 144:ef7eb2e8f9f7 4668 #define USB_EP6R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
<> 144:ef7eb2e8f9f7 4669
<> 144:ef7eb2e8f9f7 4670 #define USB_EP6R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 144:ef7eb2e8f9f7 4671 #define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4672 #define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4673
<> 144:ef7eb2e8f9f7 4674 #define USB_EP6R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
<> 144:ef7eb2e8f9f7 4675 #define USB_EP6R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
mbed_official 67:4bcbbb9fcddf 4676
mbed_official 67:4bcbbb9fcddf 4677 /******************* Bit definition for USB_EP7R register *******************/
<> 144:ef7eb2e8f9f7 4678 #define USB_EP7R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
<> 144:ef7eb2e8f9f7 4679
<> 144:ef7eb2e8f9f7 4680 #define USB_EP7R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
<> 144:ef7eb2e8f9f7 4681 #define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4682 #define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4683
<> 144:ef7eb2e8f9f7 4684 #define USB_EP7R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
<> 144:ef7eb2e8f9f7 4685 #define USB_EP7R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
<> 144:ef7eb2e8f9f7 4686 #define USB_EP7R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
<> 144:ef7eb2e8f9f7 4687
<> 144:ef7eb2e8f9f7 4688 #define USB_EP7R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
<> 144:ef7eb2e8f9f7 4689 #define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4690 #define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4691
<> 144:ef7eb2e8f9f7 4692 #define USB_EP7R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
<> 144:ef7eb2e8f9f7 4693
<> 144:ef7eb2e8f9f7 4694 #define USB_EP7R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
<> 144:ef7eb2e8f9f7 4695 #define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4696 #define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4697
<> 144:ef7eb2e8f9f7 4698 #define USB_EP7R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
<> 144:ef7eb2e8f9f7 4699 #define USB_EP7R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
mbed_official 67:4bcbbb9fcddf 4700
mbed_official 67:4bcbbb9fcddf 4701 /*!<Common registers */
mbed_official 67:4bcbbb9fcddf 4702
<> 144:ef7eb2e8f9f7 4703 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
<> 144:ef7eb2e8f9f7 4704 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
<> 144:ef7eb2e8f9f7 4705 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
<> 144:ef7eb2e8f9f7 4706 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
<> 144:ef7eb2e8f9f7 4707 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
mbed_official 67:4bcbbb9fcddf 4708
mbed_official 67:4bcbbb9fcddf 4709
mbed_official 67:4bcbbb9fcddf 4710
mbed_official 67:4bcbbb9fcddf 4711 /******************* Bit definition for USB_CNTR register *******************/
<> 144:ef7eb2e8f9f7 4712 #define USB_CNTR_FRES ((uint32_t)0x00000001U) /*!<Force USB Reset */
<> 144:ef7eb2e8f9f7 4713 #define USB_CNTR_PDWN ((uint32_t)0x00000002U) /*!<Power down */
<> 144:ef7eb2e8f9f7 4714 #define USB_CNTR_LPMODE ((uint32_t)0x00000004U) /*!<Low-power mode */
<> 144:ef7eb2e8f9f7 4715 #define USB_CNTR_FSUSP ((uint32_t)0x00000008U) /*!<Force suspend */
<> 144:ef7eb2e8f9f7 4716 #define USB_CNTR_RESUME ((uint32_t)0x00000010U) /*!<Resume request */
<> 144:ef7eb2e8f9f7 4717 #define USB_CNTR_ESOFM ((uint32_t)0x00000100U) /*!<Expected Start Of Frame Interrupt Mask */
<> 144:ef7eb2e8f9f7 4718 #define USB_CNTR_SOFM ((uint32_t)0x00000200U) /*!<Start Of Frame Interrupt Mask */
<> 144:ef7eb2e8f9f7 4719 #define USB_CNTR_RESETM ((uint32_t)0x00000400U) /*!<RESET Interrupt Mask */
<> 144:ef7eb2e8f9f7 4720 #define USB_CNTR_SUSPM ((uint32_t)0x00000800U) /*!<Suspend mode Interrupt Mask */
<> 144:ef7eb2e8f9f7 4721 #define USB_CNTR_WKUPM ((uint32_t)0x00001000U) /*!<Wakeup Interrupt Mask */
<> 144:ef7eb2e8f9f7 4722 #define USB_CNTR_ERRM ((uint32_t)0x00002000U) /*!<Error Interrupt Mask */
<> 144:ef7eb2e8f9f7 4723 #define USB_CNTR_PMAOVRM ((uint32_t)0x00004000U) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
<> 144:ef7eb2e8f9f7 4724 #define USB_CNTR_CTRM ((uint32_t)0x00008000U) /*!<Correct Transfer Interrupt Mask */
mbed_official 67:4bcbbb9fcddf 4725
mbed_official 67:4bcbbb9fcddf 4726 /******************* Bit definition for USB_ISTR register *******************/
<> 144:ef7eb2e8f9f7 4727 #define USB_ISTR_EP_ID ((uint32_t)0x0000000FU) /*!<Endpoint Identifier */
<> 144:ef7eb2e8f9f7 4728 #define USB_ISTR_DIR ((uint32_t)0x00000010U) /*!<Direction of transaction */
<> 144:ef7eb2e8f9f7 4729 #define USB_ISTR_ESOF ((uint32_t)0x00000100U) /*!<Expected Start Of Frame */
<> 144:ef7eb2e8f9f7 4730 #define USB_ISTR_SOF ((uint32_t)0x00000200U) /*!<Start Of Frame */
<> 144:ef7eb2e8f9f7 4731 #define USB_ISTR_RESET ((uint32_t)0x00000400U) /*!<USB RESET request */
<> 144:ef7eb2e8f9f7 4732 #define USB_ISTR_SUSP ((uint32_t)0x00000800U) /*!<Suspend mode request */
<> 144:ef7eb2e8f9f7 4733 #define USB_ISTR_WKUP ((uint32_t)0x00001000U) /*!<Wake up */
<> 144:ef7eb2e8f9f7 4734 #define USB_ISTR_ERR ((uint32_t)0x00002000U) /*!<Error */
<> 144:ef7eb2e8f9f7 4735 #define USB_ISTR_PMAOVR ((uint32_t)0x00004000U) /*!<Packet Memory Area Over / Underrun */
<> 144:ef7eb2e8f9f7 4736 #define USB_ISTR_CTR ((uint32_t)0x00008000U) /*!<Correct Transfer */
mbed_official 67:4bcbbb9fcddf 4737
mbed_official 67:4bcbbb9fcddf 4738 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
mbed_official 67:4bcbbb9fcddf 4739 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
mbed_official 67:4bcbbb9fcddf 4740 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
mbed_official 67:4bcbbb9fcddf 4741 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
mbed_official 67:4bcbbb9fcddf 4742 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
mbed_official 67:4bcbbb9fcddf 4743 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
mbed_official 67:4bcbbb9fcddf 4744 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
mbed_official 67:4bcbbb9fcddf 4745 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
mbed_official 67:4bcbbb9fcddf 4746
mbed_official 67:4bcbbb9fcddf 4747
mbed_official 67:4bcbbb9fcddf 4748 /******************* Bit definition for USB_FNR register ********************/
<> 144:ef7eb2e8f9f7 4749 #define USB_FNR_FN ((uint32_t)0x000007FFU) /*!<Frame Number */
<> 144:ef7eb2e8f9f7 4750 #define USB_FNR_LSOF ((uint32_t)0x00001800U) /*!<Lost SOF */
<> 144:ef7eb2e8f9f7 4751 #define USB_FNR_LCK ((uint32_t)0x00002000U) /*!<Locked */
<> 144:ef7eb2e8f9f7 4752 #define USB_FNR_RXDM ((uint32_t)0x00004000U) /*!<Receive Data - Line Status */
<> 144:ef7eb2e8f9f7 4753 #define USB_FNR_RXDP ((uint32_t)0x00008000U) /*!<Receive Data + Line Status */
mbed_official 67:4bcbbb9fcddf 4754
mbed_official 67:4bcbbb9fcddf 4755 /****************** Bit definition for USB_DADDR register *******************/
<> 144:ef7eb2e8f9f7 4756 #define USB_DADDR_ADD ((uint32_t)0x0000007FU) /*!<ADD[6:0] bits (Device Address) */
<> 144:ef7eb2e8f9f7 4757 #define USB_DADDR_ADD0 ((uint32_t)0x00000001U) /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4758 #define USB_DADDR_ADD1 ((uint32_t)0x00000002U) /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4759 #define USB_DADDR_ADD2 ((uint32_t)0x00000004U) /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4760 #define USB_DADDR_ADD3 ((uint32_t)0x00000008U) /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4761 #define USB_DADDR_ADD4 ((uint32_t)0x00000010U) /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4762 #define USB_DADDR_ADD5 ((uint32_t)0x00000020U) /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4763 #define USB_DADDR_ADD6 ((uint32_t)0x00000040U) /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4764
<> 144:ef7eb2e8f9f7 4765 #define USB_DADDR_EF ((uint32_t)0x00000080U) /*!<Enable Function */
mbed_official 67:4bcbbb9fcddf 4766
mbed_official 67:4bcbbb9fcddf 4767 /****************** Bit definition for USB_BTABLE register ******************/
<> 144:ef7eb2e8f9f7 4768 #define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8U) /*!<Buffer Table */
mbed_official 67:4bcbbb9fcddf 4769
mbed_official 67:4bcbbb9fcddf 4770 /*!< Buffer descriptor table */
mbed_official 67:4bcbbb9fcddf 4771 /***************** Bit definition for USB_ADDR0_TX register *****************/
<> 144:ef7eb2e8f9f7 4772 #define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 0 */
mbed_official 67:4bcbbb9fcddf 4773
mbed_official 67:4bcbbb9fcddf 4774 /***************** Bit definition for USB_ADDR1_TX register *****************/
<> 144:ef7eb2e8f9f7 4775 #define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 1 */
mbed_official 67:4bcbbb9fcddf 4776
mbed_official 67:4bcbbb9fcddf 4777 /***************** Bit definition for USB_ADDR2_TX register *****************/
<> 144:ef7eb2e8f9f7 4778 #define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 2 */
mbed_official 67:4bcbbb9fcddf 4779
mbed_official 67:4bcbbb9fcddf 4780 /***************** Bit definition for USB_ADDR3_TX register *****************/
<> 144:ef7eb2e8f9f7 4781 #define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 3 */
mbed_official 67:4bcbbb9fcddf 4782
mbed_official 67:4bcbbb9fcddf 4783 /***************** Bit definition for USB_ADDR4_TX register *****************/
<> 144:ef7eb2e8f9f7 4784 #define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 4 */
mbed_official 67:4bcbbb9fcddf 4785
mbed_official 67:4bcbbb9fcddf 4786 /***************** Bit definition for USB_ADDR5_TX register *****************/
<> 144:ef7eb2e8f9f7 4787 #define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 5 */
mbed_official 67:4bcbbb9fcddf 4788
mbed_official 67:4bcbbb9fcddf 4789 /***************** Bit definition for USB_ADDR6_TX register *****************/
<> 144:ef7eb2e8f9f7 4790 #define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 6 */
mbed_official 67:4bcbbb9fcddf 4791
mbed_official 67:4bcbbb9fcddf 4792 /***************** Bit definition for USB_ADDR7_TX register *****************/
<> 144:ef7eb2e8f9f7 4793 #define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 7 */
mbed_official 67:4bcbbb9fcddf 4794
mbed_official 67:4bcbbb9fcddf 4795 /*----------------------------------------------------------------------------*/
mbed_official 67:4bcbbb9fcddf 4796
mbed_official 67:4bcbbb9fcddf 4797 /***************** Bit definition for USB_COUNT0_TX register ****************/
<> 144:ef7eb2e8f9f7 4798 #define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 0 */
mbed_official 67:4bcbbb9fcddf 4799
mbed_official 67:4bcbbb9fcddf 4800 /***************** Bit definition for USB_COUNT1_TX register ****************/
<> 144:ef7eb2e8f9f7 4801 #define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 1 */
mbed_official 67:4bcbbb9fcddf 4802
mbed_official 67:4bcbbb9fcddf 4803 /***************** Bit definition for USB_COUNT2_TX register ****************/
<> 144:ef7eb2e8f9f7 4804 #define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 2 */
mbed_official 67:4bcbbb9fcddf 4805
mbed_official 67:4bcbbb9fcddf 4806 /***************** Bit definition for USB_COUNT3_TX register ****************/
<> 144:ef7eb2e8f9f7 4807 #define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 3 */
mbed_official 67:4bcbbb9fcddf 4808
mbed_official 67:4bcbbb9fcddf 4809 /***************** Bit definition for USB_COUNT4_TX register ****************/
<> 144:ef7eb2e8f9f7 4810 #define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 4 */
mbed_official 67:4bcbbb9fcddf 4811
mbed_official 67:4bcbbb9fcddf 4812 /***************** Bit definition for USB_COUNT5_TX register ****************/
<> 144:ef7eb2e8f9f7 4813 #define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 5 */
mbed_official 67:4bcbbb9fcddf 4814
mbed_official 67:4bcbbb9fcddf 4815 /***************** Bit definition for USB_COUNT6_TX register ****************/
<> 144:ef7eb2e8f9f7 4816 #define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 6 */
mbed_official 67:4bcbbb9fcddf 4817
mbed_official 67:4bcbbb9fcddf 4818 /***************** Bit definition for USB_COUNT7_TX register ****************/
<> 144:ef7eb2e8f9f7 4819 #define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 7 */
mbed_official 67:4bcbbb9fcddf 4820
mbed_official 67:4bcbbb9fcddf 4821 /*----------------------------------------------------------------------------*/
mbed_official 67:4bcbbb9fcddf 4822
mbed_official 67:4bcbbb9fcddf 4823 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
<> 144:ef7eb2e8f9f7 4824 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 0 (low) */
mbed_official 67:4bcbbb9fcddf 4825
mbed_official 67:4bcbbb9fcddf 4826 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
<> 144:ef7eb2e8f9f7 4827 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
mbed_official 67:4bcbbb9fcddf 4828
mbed_official 67:4bcbbb9fcddf 4829 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
<> 144:ef7eb2e8f9f7 4830 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 1 (low) */
mbed_official 67:4bcbbb9fcddf 4831
mbed_official 67:4bcbbb9fcddf 4832 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
<> 144:ef7eb2e8f9f7 4833 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
mbed_official 67:4bcbbb9fcddf 4834
mbed_official 67:4bcbbb9fcddf 4835 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
<> 144:ef7eb2e8f9f7 4836 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 2 (low) */
mbed_official 67:4bcbbb9fcddf 4837
mbed_official 67:4bcbbb9fcddf 4838 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
<> 144:ef7eb2e8f9f7 4839 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
mbed_official 67:4bcbbb9fcddf 4840
mbed_official 67:4bcbbb9fcddf 4841 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
<> 144:ef7eb2e8f9f7 4842 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x00000000U03FF) /*!< Transmission Byte Count 3 (low) */
mbed_official 67:4bcbbb9fcddf 4843
mbed_official 67:4bcbbb9fcddf 4844 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
<> 144:ef7eb2e8f9f7 4845 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FFU0000) /*!< Transmission Byte Count 3 (high) */
mbed_official 67:4bcbbb9fcddf 4846
mbed_official 67:4bcbbb9fcddf 4847 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
<> 144:ef7eb2e8f9f7 4848 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 4 (low) */
mbed_official 67:4bcbbb9fcddf 4849
mbed_official 67:4bcbbb9fcddf 4850 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
<> 144:ef7eb2e8f9f7 4851 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
mbed_official 67:4bcbbb9fcddf 4852
mbed_official 67:4bcbbb9fcddf 4853 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
<> 144:ef7eb2e8f9f7 4854 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 5 (low) */
mbed_official 67:4bcbbb9fcddf 4855
mbed_official 67:4bcbbb9fcddf 4856 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
<> 144:ef7eb2e8f9f7 4857 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
mbed_official 67:4bcbbb9fcddf 4858
mbed_official 67:4bcbbb9fcddf 4859 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
<> 144:ef7eb2e8f9f7 4860 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 6 (low) */
mbed_official 67:4bcbbb9fcddf 4861
mbed_official 67:4bcbbb9fcddf 4862 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
<> 144:ef7eb2e8f9f7 4863 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
mbed_official 67:4bcbbb9fcddf 4864
mbed_official 67:4bcbbb9fcddf 4865 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
<> 144:ef7eb2e8f9f7 4866 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 7 (low) */
mbed_official 67:4bcbbb9fcddf 4867
mbed_official 67:4bcbbb9fcddf 4868 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
<> 144:ef7eb2e8f9f7 4869 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
mbed_official 67:4bcbbb9fcddf 4870
mbed_official 67:4bcbbb9fcddf 4871 /*----------------------------------------------------------------------------*/
mbed_official 67:4bcbbb9fcddf 4872
mbed_official 67:4bcbbb9fcddf 4873 /***************** Bit definition for USB_ADDR0_RX register *****************/
<> 144:ef7eb2e8f9f7 4874 #define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 0 */
mbed_official 67:4bcbbb9fcddf 4875
mbed_official 67:4bcbbb9fcddf 4876 /***************** Bit definition for USB_ADDR1_RX register *****************/
<> 144:ef7eb2e8f9f7 4877 #define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 1 */
mbed_official 67:4bcbbb9fcddf 4878
mbed_official 67:4bcbbb9fcddf 4879 /***************** Bit definition for USB_ADDR2_RX register *****************/
<> 144:ef7eb2e8f9f7 4880 #define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 2 */
mbed_official 67:4bcbbb9fcddf 4881
mbed_official 67:4bcbbb9fcddf 4882 /***************** Bit definition for USB_ADDR3_RX register *****************/
<> 144:ef7eb2e8f9f7 4883 #define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 3 */
mbed_official 67:4bcbbb9fcddf 4884
mbed_official 67:4bcbbb9fcddf 4885 /***************** Bit definition for USB_ADDR4_RX register *****************/
<> 144:ef7eb2e8f9f7 4886 #define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 4 */
mbed_official 67:4bcbbb9fcddf 4887
mbed_official 67:4bcbbb9fcddf 4888 /***************** Bit definition for USB_ADDR5_RX register *****************/
<> 144:ef7eb2e8f9f7 4889 #define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 5 */
mbed_official 67:4bcbbb9fcddf 4890
mbed_official 67:4bcbbb9fcddf 4891 /***************** Bit definition for USB_ADDR6_RX register *****************/
<> 144:ef7eb2e8f9f7 4892 #define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 6 */
mbed_official 67:4bcbbb9fcddf 4893
mbed_official 67:4bcbbb9fcddf 4894 /***************** Bit definition for USB_ADDR7_RX register *****************/
<> 144:ef7eb2e8f9f7 4895 #define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 7 */
mbed_official 67:4bcbbb9fcddf 4896
mbed_official 67:4bcbbb9fcddf 4897 /*----------------------------------------------------------------------------*/
mbed_official 67:4bcbbb9fcddf 4898
mbed_official 67:4bcbbb9fcddf 4899 /***************** Bit definition for USB_COUNT0_RX register ****************/
<> 144:ef7eb2e8f9f7 4900 #define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
<> 144:ef7eb2e8f9f7 4901
<> 144:ef7eb2e8f9f7 4902 #define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 144:ef7eb2e8f9f7 4903 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4904 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4905 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4906 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4907 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4908
<> 144:ef7eb2e8f9f7 4909 #define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
mbed_official 67:4bcbbb9fcddf 4910
mbed_official 67:4bcbbb9fcddf 4911 /***************** Bit definition for USB_COUNT1_RX register ****************/
<> 144:ef7eb2e8f9f7 4912 #define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
<> 144:ef7eb2e8f9f7 4913
<> 144:ef7eb2e8f9f7 4914 #define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 144:ef7eb2e8f9f7 4915 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4916 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4917 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4918 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4919 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4920
<> 144:ef7eb2e8f9f7 4921 #define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
mbed_official 67:4bcbbb9fcddf 4922
mbed_official 67:4bcbbb9fcddf 4923 /***************** Bit definition for USB_COUNT2_RX register ****************/
<> 144:ef7eb2e8f9f7 4924 #define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
<> 144:ef7eb2e8f9f7 4925
<> 144:ef7eb2e8f9f7 4926 #define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 144:ef7eb2e8f9f7 4927 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4928 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4929 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4930 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4931 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4932
<> 144:ef7eb2e8f9f7 4933 #define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
mbed_official 67:4bcbbb9fcddf 4934
mbed_official 67:4bcbbb9fcddf 4935 /***************** Bit definition for USB_COUNT3_RX register ****************/
<> 144:ef7eb2e8f9f7 4936 #define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
<> 144:ef7eb2e8f9f7 4937
<> 144:ef7eb2e8f9f7 4938 #define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 144:ef7eb2e8f9f7 4939 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4940 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4941 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4942 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4943 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4944
<> 144:ef7eb2e8f9f7 4945 #define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
mbed_official 67:4bcbbb9fcddf 4946
mbed_official 67:4bcbbb9fcddf 4947 /***************** Bit definition for USB_COUNT4_RX register ****************/
<> 144:ef7eb2e8f9f7 4948 #define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
<> 144:ef7eb2e8f9f7 4949
<> 144:ef7eb2e8f9f7 4950 #define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 144:ef7eb2e8f9f7 4951 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4952 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4953 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4954 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4955 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4956
<> 144:ef7eb2e8f9f7 4957 #define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
mbed_official 67:4bcbbb9fcddf 4958
mbed_official 67:4bcbbb9fcddf 4959 /***************** Bit definition for USB_COUNT5_RX register ****************/
<> 144:ef7eb2e8f9f7 4960 #define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
<> 144:ef7eb2e8f9f7 4961
<> 144:ef7eb2e8f9f7 4962 #define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 144:ef7eb2e8f9f7 4963 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4964 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4965 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4966 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4967 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4968
<> 144:ef7eb2e8f9f7 4969 #define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
mbed_official 67:4bcbbb9fcddf 4970
mbed_official 67:4bcbbb9fcddf 4971 /***************** Bit definition for USB_COUNT6_RX register ****************/
<> 144:ef7eb2e8f9f7 4972 #define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
<> 144:ef7eb2e8f9f7 4973
<> 144:ef7eb2e8f9f7 4974 #define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 144:ef7eb2e8f9f7 4975 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4976 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4977 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4978 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4979 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4980
<> 144:ef7eb2e8f9f7 4981 #define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
mbed_official 67:4bcbbb9fcddf 4982
mbed_official 67:4bcbbb9fcddf 4983 /***************** Bit definition for USB_COUNT7_RX register ****************/
<> 144:ef7eb2e8f9f7 4984 #define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
<> 144:ef7eb2e8f9f7 4985
<> 144:ef7eb2e8f9f7 4986 #define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
<> 144:ef7eb2e8f9f7 4987 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 4988 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 4989 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 4990 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 4991 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 4992
<> 144:ef7eb2e8f9f7 4993 #define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
mbed_official 67:4bcbbb9fcddf 4994
mbed_official 67:4bcbbb9fcddf 4995 /*----------------------------------------------------------------------------*/
mbed_official 67:4bcbbb9fcddf 4996
mbed_official 67:4bcbbb9fcddf 4997 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
<> 144:ef7eb2e8f9f7 4998 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
<> 144:ef7eb2e8f9f7 4999
<> 144:ef7eb2e8f9f7 5000 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 144:ef7eb2e8f9f7 5001 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5002 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5003 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5004 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5005 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5006
<> 144:ef7eb2e8f9f7 5007 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
mbed_official 67:4bcbbb9fcddf 5008
mbed_official 67:4bcbbb9fcddf 5009 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
<> 144:ef7eb2e8f9f7 5010 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
<> 144:ef7eb2e8f9f7 5011
<> 144:ef7eb2e8f9f7 5012 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 144:ef7eb2e8f9f7 5013 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5014 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5015 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5016 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5017 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5018
<> 144:ef7eb2e8f9f7 5019 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
mbed_official 67:4bcbbb9fcddf 5020
mbed_official 67:4bcbbb9fcddf 5021 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
<> 144:ef7eb2e8f9f7 5022 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
<> 144:ef7eb2e8f9f7 5023
<> 144:ef7eb2e8f9f7 5024 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 144:ef7eb2e8f9f7 5025 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5026 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5027 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5028 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5029 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5030
<> 144:ef7eb2e8f9f7 5031 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
mbed_official 67:4bcbbb9fcddf 5032
mbed_official 67:4bcbbb9fcddf 5033 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
<> 144:ef7eb2e8f9f7 5034 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
<> 144:ef7eb2e8f9f7 5035
<> 144:ef7eb2e8f9f7 5036 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 144:ef7eb2e8f9f7 5037 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5038 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5039 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5040 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5041 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5042
<> 144:ef7eb2e8f9f7 5043 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
mbed_official 67:4bcbbb9fcddf 5044
mbed_official 67:4bcbbb9fcddf 5045 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
<> 144:ef7eb2e8f9f7 5046 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
<> 144:ef7eb2e8f9f7 5047
<> 144:ef7eb2e8f9f7 5048 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 144:ef7eb2e8f9f7 5049 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5050 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5051 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5052 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5053 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5054
<> 144:ef7eb2e8f9f7 5055 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
mbed_official 67:4bcbbb9fcddf 5056
mbed_official 67:4bcbbb9fcddf 5057 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
<> 144:ef7eb2e8f9f7 5058 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
<> 144:ef7eb2e8f9f7 5059
<> 144:ef7eb2e8f9f7 5060 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 144:ef7eb2e8f9f7 5061 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5062 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5063 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5064 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5065 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5066
<> 144:ef7eb2e8f9f7 5067 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
mbed_official 67:4bcbbb9fcddf 5068
mbed_official 67:4bcbbb9fcddf 5069 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
<> 144:ef7eb2e8f9f7 5070 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
<> 144:ef7eb2e8f9f7 5071
<> 144:ef7eb2e8f9f7 5072 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 144:ef7eb2e8f9f7 5073 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5074 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5075 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5076 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5077 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5078
<> 144:ef7eb2e8f9f7 5079 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
mbed_official 67:4bcbbb9fcddf 5080
mbed_official 67:4bcbbb9fcddf 5081 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
<> 144:ef7eb2e8f9f7 5082 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
<> 144:ef7eb2e8f9f7 5083
<> 144:ef7eb2e8f9f7 5084 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 144:ef7eb2e8f9f7 5085 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5086 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5087 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5088 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5089 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5090
<> 144:ef7eb2e8f9f7 5091 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
mbed_official 67:4bcbbb9fcddf 5092
mbed_official 67:4bcbbb9fcddf 5093 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
<> 144:ef7eb2e8f9f7 5094 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
<> 144:ef7eb2e8f9f7 5095
<> 144:ef7eb2e8f9f7 5096 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 144:ef7eb2e8f9f7 5097 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5098 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5099 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5100 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5101 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5102
<> 144:ef7eb2e8f9f7 5103 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
mbed_official 67:4bcbbb9fcddf 5104
mbed_official 67:4bcbbb9fcddf 5105 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
<> 144:ef7eb2e8f9f7 5106 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
<> 144:ef7eb2e8f9f7 5107
<> 144:ef7eb2e8f9f7 5108 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 144:ef7eb2e8f9f7 5109 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5110 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5111 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5112 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5113 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5114
<> 144:ef7eb2e8f9f7 5115 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
mbed_official 67:4bcbbb9fcddf 5116
mbed_official 67:4bcbbb9fcddf 5117 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
<> 144:ef7eb2e8f9f7 5118 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
<> 144:ef7eb2e8f9f7 5119
<> 144:ef7eb2e8f9f7 5120 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 144:ef7eb2e8f9f7 5121 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5122 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5123 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5124 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5125 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5126
<> 144:ef7eb2e8f9f7 5127 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
mbed_official 67:4bcbbb9fcddf 5128
mbed_official 67:4bcbbb9fcddf 5129 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
<> 144:ef7eb2e8f9f7 5130 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
<> 144:ef7eb2e8f9f7 5131
<> 144:ef7eb2e8f9f7 5132 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 144:ef7eb2e8f9f7 5133 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5134 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5135 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5136 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5137 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5138
<> 144:ef7eb2e8f9f7 5139 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
mbed_official 67:4bcbbb9fcddf 5140
mbed_official 67:4bcbbb9fcddf 5141 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
<> 144:ef7eb2e8f9f7 5142 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
<> 144:ef7eb2e8f9f7 5143
<> 144:ef7eb2e8f9f7 5144 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 144:ef7eb2e8f9f7 5145 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5146 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5147 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5148 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5149 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5150
<> 144:ef7eb2e8f9f7 5151 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
mbed_official 67:4bcbbb9fcddf 5152
mbed_official 67:4bcbbb9fcddf 5153 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
<> 144:ef7eb2e8f9f7 5154 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
<> 144:ef7eb2e8f9f7 5155
<> 144:ef7eb2e8f9f7 5156 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 144:ef7eb2e8f9f7 5157 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5158 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5159 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5160 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5161 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5162
<> 144:ef7eb2e8f9f7 5163 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
mbed_official 67:4bcbbb9fcddf 5164
mbed_official 67:4bcbbb9fcddf 5165 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
<> 144:ef7eb2e8f9f7 5166 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
<> 144:ef7eb2e8f9f7 5167
<> 144:ef7eb2e8f9f7 5168 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
<> 144:ef7eb2e8f9f7 5169 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5170 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5171 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5172 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5173 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5174
<> 144:ef7eb2e8f9f7 5175 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
mbed_official 67:4bcbbb9fcddf 5176
mbed_official 67:4bcbbb9fcddf 5177 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
<> 144:ef7eb2e8f9f7 5178 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
<> 144:ef7eb2e8f9f7 5179
<> 144:ef7eb2e8f9f7 5180 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
<> 144:ef7eb2e8f9f7 5181 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5182 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5183 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5184 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5185 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5186
<> 144:ef7eb2e8f9f7 5187 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
mbed_official 67:4bcbbb9fcddf 5188
mbed_official 67:4bcbbb9fcddf 5189 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 5190 /* */
mbed_official 67:4bcbbb9fcddf 5191 /* Window WATCHDOG (WWDG) */
mbed_official 67:4bcbbb9fcddf 5192 /* */
mbed_official 67:4bcbbb9fcddf 5193 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 5194
mbed_official 67:4bcbbb9fcddf 5195 /******************* Bit definition for WWDG_CR register ********************/
<> 144:ef7eb2e8f9f7 5196 #define WWDG_CR_T ((uint32_t)0x0000007FU) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 144:ef7eb2e8f9f7 5197 #define WWDG_CR_T_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5198 #define WWDG_CR_T_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5199 #define WWDG_CR_T_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5200 #define WWDG_CR_T_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5201 #define WWDG_CR_T_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5202 #define WWDG_CR_T_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 5203 #define WWDG_CR_T_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 5204
<> 144:ef7eb2e8f9f7 5205 /* Legacy defines */
<> 144:ef7eb2e8f9f7 5206 #define WWDG_CR_T0 WWDG_CR_T_0
<> 144:ef7eb2e8f9f7 5207 #define WWDG_CR_T1 WWDG_CR_T_1
<> 144:ef7eb2e8f9f7 5208 #define WWDG_CR_T2 WWDG_CR_T_2
<> 144:ef7eb2e8f9f7 5209 #define WWDG_CR_T3 WWDG_CR_T_3
<> 144:ef7eb2e8f9f7 5210 #define WWDG_CR_T4 WWDG_CR_T_4
<> 144:ef7eb2e8f9f7 5211 #define WWDG_CR_T5 WWDG_CR_T_5
<> 144:ef7eb2e8f9f7 5212 #define WWDG_CR_T6 WWDG_CR_T_6
<> 144:ef7eb2e8f9f7 5213
<> 144:ef7eb2e8f9f7 5214 #define WWDG_CR_WDGA ((uint32_t)0x00000080U) /*!< Activation bit */
mbed_official 67:4bcbbb9fcddf 5215
mbed_official 67:4bcbbb9fcddf 5216 /******************* Bit definition for WWDG_CFR register *******************/
<> 144:ef7eb2e8f9f7 5217 #define WWDG_CFR_W ((uint32_t)0x0000007FU) /*!< W[6:0] bits (7-bit window value) */
<> 144:ef7eb2e8f9f7 5218 #define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5219 #define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5220 #define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5221 #define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5222 #define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5223 #define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 5224 #define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 5225
<> 144:ef7eb2e8f9f7 5226 /* Legacy defines */
<> 144:ef7eb2e8f9f7 5227 #define WWDG_CFR_W0 WWDG_CFR_W_0
<> 144:ef7eb2e8f9f7 5228 #define WWDG_CFR_W1 WWDG_CFR_W_1
<> 144:ef7eb2e8f9f7 5229 #define WWDG_CFR_W2 WWDG_CFR_W_2
<> 144:ef7eb2e8f9f7 5230 #define WWDG_CFR_W3 WWDG_CFR_W_3
<> 144:ef7eb2e8f9f7 5231 #define WWDG_CFR_W4 WWDG_CFR_W_4
<> 144:ef7eb2e8f9f7 5232 #define WWDG_CFR_W5 WWDG_CFR_W_5
<> 144:ef7eb2e8f9f7 5233 #define WWDG_CFR_W6 WWDG_CFR_W_6
<> 144:ef7eb2e8f9f7 5234
<> 144:ef7eb2e8f9f7 5235 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /*!< WDGTB[1:0] bits (Timer Base) */
<> 144:ef7eb2e8f9f7 5236 #define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5237 #define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5238
<> 144:ef7eb2e8f9f7 5239 /* Legacy defines */
<> 144:ef7eb2e8f9f7 5240 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
<> 144:ef7eb2e8f9f7 5241 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
<> 144:ef7eb2e8f9f7 5242
<> 144:ef7eb2e8f9f7 5243 #define WWDG_CFR_EWI ((uint32_t)0x00000200U) /*!< Early Wakeup Interrupt */
mbed_official 67:4bcbbb9fcddf 5244
mbed_official 67:4bcbbb9fcddf 5245 /******************* Bit definition for WWDG_SR register ********************/
<> 144:ef7eb2e8f9f7 5246 #define WWDG_SR_EWIF ((uint32_t)0x00000001U) /*!< Early Wakeup Interrupt Flag */
mbed_official 67:4bcbbb9fcddf 5247
mbed_official 67:4bcbbb9fcddf 5248 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 5249 /* */
mbed_official 67:4bcbbb9fcddf 5250 /* SystemTick (SysTick) */
mbed_official 67:4bcbbb9fcddf 5251 /* */
mbed_official 67:4bcbbb9fcddf 5252 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 5253
mbed_official 67:4bcbbb9fcddf 5254 /***************** Bit definition for SysTick_CTRL register *****************/
<> 144:ef7eb2e8f9f7 5255 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001U) /*!< Counter enable */
<> 144:ef7eb2e8f9f7 5256 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002U) /*!< Counting down to 0 pends the SysTick handler */
<> 144:ef7eb2e8f9f7 5257 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004U) /*!< Clock source */
<> 144:ef7eb2e8f9f7 5258 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000U) /*!< Count Flag */
mbed_official 67:4bcbbb9fcddf 5259
mbed_official 67:4bcbbb9fcddf 5260 /***************** Bit definition for SysTick_LOAD register *****************/
<> 144:ef7eb2e8f9f7 5261 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
mbed_official 67:4bcbbb9fcddf 5262
mbed_official 67:4bcbbb9fcddf 5263 /***************** Bit definition for SysTick_VAL register ******************/
<> 144:ef7eb2e8f9f7 5264 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFFU) /*!< Current value at the time the register is accessed */
mbed_official 67:4bcbbb9fcddf 5265
mbed_official 67:4bcbbb9fcddf 5266 /***************** Bit definition for SysTick_CALIB register ****************/
<> 144:ef7eb2e8f9f7 5267 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFFU) /*!< Reload value to use for 10ms timing */
<> 144:ef7eb2e8f9f7 5268 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000U) /*!< Calibration value is not exactly 10 ms */
<> 144:ef7eb2e8f9f7 5269 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000U) /*!< The reference clock is not provided */
mbed_official 67:4bcbbb9fcddf 5270
mbed_official 67:4bcbbb9fcddf 5271 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 5272 /* */
mbed_official 67:4bcbbb9fcddf 5273 /* Nested Vectored Interrupt Controller (NVIC) */
mbed_official 67:4bcbbb9fcddf 5274 /* */
mbed_official 67:4bcbbb9fcddf 5275 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 5276
mbed_official 67:4bcbbb9fcddf 5277 /****************** Bit definition for NVIC_ISER register *******************/
<> 144:ef7eb2e8f9f7 5278 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFFU) /*!< Interrupt set enable bits */
<> 144:ef7eb2e8f9f7 5279 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
<> 144:ef7eb2e8f9f7 5280 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
<> 144:ef7eb2e8f9f7 5281 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
<> 144:ef7eb2e8f9f7 5282 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
<> 144:ef7eb2e8f9f7 5283 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
<> 144:ef7eb2e8f9f7 5284 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
<> 144:ef7eb2e8f9f7 5285 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
<> 144:ef7eb2e8f9f7 5286 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
<> 144:ef7eb2e8f9f7 5287 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
<> 144:ef7eb2e8f9f7 5288 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
<> 144:ef7eb2e8f9f7 5289 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
<> 144:ef7eb2e8f9f7 5290 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
<> 144:ef7eb2e8f9f7 5291 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
<> 144:ef7eb2e8f9f7 5292 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
<> 144:ef7eb2e8f9f7 5293 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
<> 144:ef7eb2e8f9f7 5294 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
<> 144:ef7eb2e8f9f7 5295 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000U) /*!< bit 16 */
<> 144:ef7eb2e8f9f7 5296 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000U) /*!< bit 17 */
<> 144:ef7eb2e8f9f7 5297 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000U) /*!< bit 18 */
<> 144:ef7eb2e8f9f7 5298 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000U) /*!< bit 19 */
<> 144:ef7eb2e8f9f7 5299 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000U) /*!< bit 20 */
<> 144:ef7eb2e8f9f7 5300 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000U) /*!< bit 21 */
<> 144:ef7eb2e8f9f7 5301 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000U) /*!< bit 22 */
<> 144:ef7eb2e8f9f7 5302 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000U) /*!< bit 23 */
<> 144:ef7eb2e8f9f7 5303 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000U) /*!< bit 24 */
<> 144:ef7eb2e8f9f7 5304 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000U) /*!< bit 25 */
<> 144:ef7eb2e8f9f7 5305 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000U) /*!< bit 26 */
<> 144:ef7eb2e8f9f7 5306 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000U) /*!< bit 27 */
<> 144:ef7eb2e8f9f7 5307 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000U) /*!< bit 28 */
<> 144:ef7eb2e8f9f7 5308 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000U) /*!< bit 29 */
<> 144:ef7eb2e8f9f7 5309 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000U) /*!< bit 30 */
<> 144:ef7eb2e8f9f7 5310 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000U) /*!< bit 31 */
mbed_official 67:4bcbbb9fcddf 5311
mbed_official 67:4bcbbb9fcddf 5312 /****************** Bit definition for NVIC_ICER register *******************/
<> 144:ef7eb2e8f9f7 5313 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFFU) /*!< Interrupt clear-enable bits */
<> 144:ef7eb2e8f9f7 5314 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
<> 144:ef7eb2e8f9f7 5315 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
<> 144:ef7eb2e8f9f7 5316 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
<> 144:ef7eb2e8f9f7 5317 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
<> 144:ef7eb2e8f9f7 5318 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
<> 144:ef7eb2e8f9f7 5319 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
<> 144:ef7eb2e8f9f7 5320 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
<> 144:ef7eb2e8f9f7 5321 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
<> 144:ef7eb2e8f9f7 5322 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
<> 144:ef7eb2e8f9f7 5323 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
<> 144:ef7eb2e8f9f7 5324 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
<> 144:ef7eb2e8f9f7 5325 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
<> 144:ef7eb2e8f9f7 5326 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
<> 144:ef7eb2e8f9f7 5327 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
<> 144:ef7eb2e8f9f7 5328 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
<> 144:ef7eb2e8f9f7 5329 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
<> 144:ef7eb2e8f9f7 5330 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000U) /*!< bit 16 */
<> 144:ef7eb2e8f9f7 5331 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000U) /*!< bit 17 */
<> 144:ef7eb2e8f9f7 5332 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000U) /*!< bit 18 */
<> 144:ef7eb2e8f9f7 5333 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000U) /*!< bit 19 */
<> 144:ef7eb2e8f9f7 5334 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000U) /*!< bit 20 */
<> 144:ef7eb2e8f9f7 5335 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000U) /*!< bit 21 */
<> 144:ef7eb2e8f9f7 5336 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000U) /*!< bit 22 */
<> 144:ef7eb2e8f9f7 5337 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000U) /*!< bit 23 */
<> 144:ef7eb2e8f9f7 5338 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000U) /*!< bit 24 */
<> 144:ef7eb2e8f9f7 5339 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000U) /*!< bit 25 */
<> 144:ef7eb2e8f9f7 5340 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000U) /*!< bit 26 */
<> 144:ef7eb2e8f9f7 5341 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000U) /*!< bit 27 */
<> 144:ef7eb2e8f9f7 5342 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000U) /*!< bit 28 */
<> 144:ef7eb2e8f9f7 5343 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000U) /*!< bit 29 */
<> 144:ef7eb2e8f9f7 5344 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000U) /*!< bit 30 */
<> 144:ef7eb2e8f9f7 5345 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000U) /*!< bit 31 */
mbed_official 67:4bcbbb9fcddf 5346
mbed_official 67:4bcbbb9fcddf 5347 /****************** Bit definition for NVIC_ISPR register *******************/
<> 144:ef7eb2e8f9f7 5348 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFFU) /*!< Interrupt set-pending bits */
<> 144:ef7eb2e8f9f7 5349 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001U) /*!< bit 0 */
<> 144:ef7eb2e8f9f7 5350 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002U) /*!< bit 1 */
<> 144:ef7eb2e8f9f7 5351 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004U) /*!< bit 2 */
<> 144:ef7eb2e8f9f7 5352 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008U) /*!< bit 3 */
<> 144:ef7eb2e8f9f7 5353 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010U) /*!< bit 4 */
<> 144:ef7eb2e8f9f7 5354 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020U) /*!< bit 5 */
<> 144:ef7eb2e8f9f7 5355 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040U) /*!< bit 6 */
<> 144:ef7eb2e8f9f7 5356 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080U) /*!< bit 7 */
<> 144:ef7eb2e8f9f7 5357 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100U) /*!< bit 8 */
<> 144:ef7eb2e8f9f7 5358 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200U) /*!< bit 9 */
<> 144:ef7eb2e8f9f7 5359 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400U) /*!< bit 10 */
<> 144:ef7eb2e8f9f7 5360 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800U) /*!< bit 11 */
<> 144:ef7eb2e8f9f7 5361 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000U) /*!< bit 12 */
<> 144:ef7eb2e8f9f7 5362 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000U) /*!< bit 13 */
<> 144:ef7eb2e8f9f7 5363 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000U) /*!< bit 14 */
<> 144:ef7eb2e8f9f7 5364 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000U) /*!< bit 15 */
<> 144:ef7eb2e8f9f7 5365 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000U) /*!< bit 16 */
<> 144:ef7eb2e8f9f7 5366 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000U) /*!< bit 17 */
<> 144:ef7eb2e8f9f7 5367 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000U) /*!< bit 18 */
<> 144:ef7eb2e8f9f7 5368 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000U) /*!< bit 19 */
<> 144:ef7eb2e8f9f7 5369 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000U) /*!< bit 20 */
<> 144:ef7eb2e8f9f7 5370 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000U) /*!< bit 21 */
<> 144:ef7eb2e8f9f7 5371 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000U) /*!< bit 22 */
<> 144:ef7eb2e8f9f7 5372 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000U) /*!< bit 23 */
<> 144:ef7eb2e8f9f7 5373 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000U) /*!< bit 24 */
<> 144:ef7eb2e8f9f7 5374 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000U) /*!< bit 25 */
<> 144:ef7eb2e8f9f7 5375 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000U) /*!< bit 26 */
<> 144:ef7eb2e8f9f7 5376 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000U) /*!< bit 27 */
<> 144:ef7eb2e8f9f7 5377 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000U) /*!< bit 28 */
<> 144:ef7eb2e8f9f7 5378 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000U) /*!< bit 29 */
<> 144:ef7eb2e8f9f7 5379 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000U) /*!< bit 30 */
<> 144:ef7eb2e8f9f7 5380 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000U) /*!< bit 31 */
mbed_official 67:4bcbbb9fcddf 5381
mbed_official 67:4bcbbb9fcddf 5382 /****************** Bit definition for NVIC_ICPR register *******************/
<> 144:ef7eb2e8f9f7 5383 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFFU) /*!< Interrupt clear-pending bits */
<> 144:ef7eb2e8f9f7 5384 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001U) /*!< bit 0 */
<> 144:ef7eb2e8f9f7 5385 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002U) /*!< bit 1 */
<> 144:ef7eb2e8f9f7 5386 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004U) /*!< bit 2 */
<> 144:ef7eb2e8f9f7 5387 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008U) /*!< bit 3 */
<> 144:ef7eb2e8f9f7 5388 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010U) /*!< bit 4 */
<> 144:ef7eb2e8f9f7 5389 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020U) /*!< bit 5 */
<> 144:ef7eb2e8f9f7 5390 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040U) /*!< bit 6 */
<> 144:ef7eb2e8f9f7 5391 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080U) /*!< bit 7 */
<> 144:ef7eb2e8f9f7 5392 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100U) /*!< bit 8 */
<> 144:ef7eb2e8f9f7 5393 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200U) /*!< bit 9 */
<> 144:ef7eb2e8f9f7 5394 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400U) /*!< bit 10 */
<> 144:ef7eb2e8f9f7 5395 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800U) /*!< bit 11 */
<> 144:ef7eb2e8f9f7 5396 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000U) /*!< bit 12 */
<> 144:ef7eb2e8f9f7 5397 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000U) /*!< bit 13 */
<> 144:ef7eb2e8f9f7 5398 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000U) /*!< bit 14 */
<> 144:ef7eb2e8f9f7 5399 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000U) /*!< bit 15 */
<> 144:ef7eb2e8f9f7 5400 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000U) /*!< bit 16 */
<> 144:ef7eb2e8f9f7 5401 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000U) /*!< bit 17 */
<> 144:ef7eb2e8f9f7 5402 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000U) /*!< bit 18 */
<> 144:ef7eb2e8f9f7 5403 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000U) /*!< bit 19 */
<> 144:ef7eb2e8f9f7 5404 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000U) /*!< bit 20 */
<> 144:ef7eb2e8f9f7 5405 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000U) /*!< bit 21 */
<> 144:ef7eb2e8f9f7 5406 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000U) /*!< bit 22 */
<> 144:ef7eb2e8f9f7 5407 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000U) /*!< bit 23 */
<> 144:ef7eb2e8f9f7 5408 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000U) /*!< bit 24 */
<> 144:ef7eb2e8f9f7 5409 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000U) /*!< bit 25 */
<> 144:ef7eb2e8f9f7 5410 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000U) /*!< bit 26 */
<> 144:ef7eb2e8f9f7 5411 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000U) /*!< bit 27 */
<> 144:ef7eb2e8f9f7 5412 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000U) /*!< bit 28 */
<> 144:ef7eb2e8f9f7 5413 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000U) /*!< bit 29 */
<> 144:ef7eb2e8f9f7 5414 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000U) /*!< bit 30 */
<> 144:ef7eb2e8f9f7 5415 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000U) /*!< bit 31 */
mbed_official 67:4bcbbb9fcddf 5416
mbed_official 67:4bcbbb9fcddf 5417 /****************** Bit definition for NVIC_IABR register *******************/
<> 144:ef7eb2e8f9f7 5418 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFFU) /*!< Interrupt active flags */
<> 144:ef7eb2e8f9f7 5419 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001U) /*!< bit 0 */
<> 144:ef7eb2e8f9f7 5420 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002U) /*!< bit 1 */
<> 144:ef7eb2e8f9f7 5421 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004U) /*!< bit 2 */
<> 144:ef7eb2e8f9f7 5422 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008U) /*!< bit 3 */
<> 144:ef7eb2e8f9f7 5423 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010U) /*!< bit 4 */
<> 144:ef7eb2e8f9f7 5424 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020U) /*!< bit 5 */
<> 144:ef7eb2e8f9f7 5425 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040U) /*!< bit 6 */
<> 144:ef7eb2e8f9f7 5426 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080U) /*!< bit 7 */
<> 144:ef7eb2e8f9f7 5427 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100U) /*!< bit 8 */
<> 144:ef7eb2e8f9f7 5428 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200U) /*!< bit 9 */
<> 144:ef7eb2e8f9f7 5429 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400U) /*!< bit 10 */
<> 144:ef7eb2e8f9f7 5430 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800U) /*!< bit 11 */
<> 144:ef7eb2e8f9f7 5431 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000U) /*!< bit 12 */
<> 144:ef7eb2e8f9f7 5432 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000U) /*!< bit 13 */
<> 144:ef7eb2e8f9f7 5433 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000U) /*!< bit 14 */
<> 144:ef7eb2e8f9f7 5434 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000U) /*!< bit 15 */
<> 144:ef7eb2e8f9f7 5435 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000U) /*!< bit 16 */
<> 144:ef7eb2e8f9f7 5436 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000U) /*!< bit 17 */
<> 144:ef7eb2e8f9f7 5437 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000U) /*!< bit 18 */
<> 144:ef7eb2e8f9f7 5438 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000U) /*!< bit 19 */
<> 144:ef7eb2e8f9f7 5439 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000U) /*!< bit 20 */
<> 144:ef7eb2e8f9f7 5440 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000U) /*!< bit 21 */
<> 144:ef7eb2e8f9f7 5441 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000U) /*!< bit 22 */
<> 144:ef7eb2e8f9f7 5442 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000U) /*!< bit 23 */
<> 144:ef7eb2e8f9f7 5443 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000U) /*!< bit 24 */
<> 144:ef7eb2e8f9f7 5444 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000U) /*!< bit 25 */
<> 144:ef7eb2e8f9f7 5445 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000U) /*!< bit 26 */
<> 144:ef7eb2e8f9f7 5446 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000U) /*!< bit 27 */
<> 144:ef7eb2e8f9f7 5447 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000U) /*!< bit 28 */
<> 144:ef7eb2e8f9f7 5448 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000U) /*!< bit 29 */
<> 144:ef7eb2e8f9f7 5449 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000U) /*!< bit 30 */
<> 144:ef7eb2e8f9f7 5450 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000U) /*!< bit 31 */
mbed_official 67:4bcbbb9fcddf 5451
mbed_official 67:4bcbbb9fcddf 5452 /****************** Bit definition for NVIC_PRI0 register *******************/
<> 144:ef7eb2e8f9f7 5453 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 0 */
<> 144:ef7eb2e8f9f7 5454 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 1 */
<> 144:ef7eb2e8f9f7 5455 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 2 */
<> 144:ef7eb2e8f9f7 5456 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 3 */
mbed_official 67:4bcbbb9fcddf 5457
mbed_official 67:4bcbbb9fcddf 5458 /****************** Bit definition for NVIC_PRI1 register *******************/
<> 144:ef7eb2e8f9f7 5459 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 4 */
<> 144:ef7eb2e8f9f7 5460 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 5 */
<> 144:ef7eb2e8f9f7 5461 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 6 */
<> 144:ef7eb2e8f9f7 5462 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 7 */
mbed_official 67:4bcbbb9fcddf 5463
mbed_official 67:4bcbbb9fcddf 5464 /****************** Bit definition for NVIC_PRI2 register *******************/
<> 144:ef7eb2e8f9f7 5465 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 8 */
<> 144:ef7eb2e8f9f7 5466 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 9 */
<> 144:ef7eb2e8f9f7 5467 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 10 */
<> 144:ef7eb2e8f9f7 5468 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 11 */
mbed_official 67:4bcbbb9fcddf 5469
mbed_official 67:4bcbbb9fcddf 5470 /****************** Bit definition for NVIC_PRI3 register *******************/
<> 144:ef7eb2e8f9f7 5471 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 12 */
<> 144:ef7eb2e8f9f7 5472 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 13 */
<> 144:ef7eb2e8f9f7 5473 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 14 */
<> 144:ef7eb2e8f9f7 5474 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 15 */
mbed_official 67:4bcbbb9fcddf 5475
mbed_official 67:4bcbbb9fcddf 5476 /****************** Bit definition for NVIC_PRI4 register *******************/
<> 144:ef7eb2e8f9f7 5477 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 16 */
<> 144:ef7eb2e8f9f7 5478 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 17 */
<> 144:ef7eb2e8f9f7 5479 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 18 */
<> 144:ef7eb2e8f9f7 5480 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 19 */
mbed_official 67:4bcbbb9fcddf 5481
mbed_official 67:4bcbbb9fcddf 5482 /****************** Bit definition for NVIC_PRI5 register *******************/
<> 144:ef7eb2e8f9f7 5483 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 20 */
<> 144:ef7eb2e8f9f7 5484 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 21 */
<> 144:ef7eb2e8f9f7 5485 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 22 */
<> 144:ef7eb2e8f9f7 5486 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 23 */
mbed_official 67:4bcbbb9fcddf 5487
mbed_official 67:4bcbbb9fcddf 5488 /****************** Bit definition for NVIC_PRI6 register *******************/
<> 144:ef7eb2e8f9f7 5489 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 24 */
<> 144:ef7eb2e8f9f7 5490 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 25 */
<> 144:ef7eb2e8f9f7 5491 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 26 */
<> 144:ef7eb2e8f9f7 5492 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 27 */
mbed_official 67:4bcbbb9fcddf 5493
mbed_official 67:4bcbbb9fcddf 5494 /****************** Bit definition for NVIC_PRI7 register *******************/
<> 144:ef7eb2e8f9f7 5495 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 28 */
<> 144:ef7eb2e8f9f7 5496 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 29 */
<> 144:ef7eb2e8f9f7 5497 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 30 */
<> 144:ef7eb2e8f9f7 5498 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 31 */
mbed_official 67:4bcbbb9fcddf 5499
mbed_official 67:4bcbbb9fcddf 5500 /****************** Bit definition for SCB_CPUID register *******************/
<> 144:ef7eb2e8f9f7 5501 #define SCB_CPUID_REVISION ((uint32_t)0x0000000FU) /*!< Implementation defined revision number */
<> 144:ef7eb2e8f9f7 5502 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0U) /*!< Number of processor within family */
<> 144:ef7eb2e8f9f7 5503 #define SCB_CPUID_Constant ((uint32_t)0x000F0000U) /*!< Reads as 0x0F */
<> 144:ef7eb2e8f9f7 5504 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000U) /*!< Implementation defined variant number */
<> 144:ef7eb2e8f9f7 5505 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000U) /*!< Implementer code. ARM is 0x41 */
mbed_official 67:4bcbbb9fcddf 5506
mbed_official 67:4bcbbb9fcddf 5507 /******************* Bit definition for SCB_ICSR register *******************/
<> 144:ef7eb2e8f9f7 5508 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FFU) /*!< Active ISR number field */
<> 144:ef7eb2e8f9f7 5509 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
<> 144:ef7eb2e8f9f7 5510 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000U) /*!< Pending ISR number field */
<> 144:ef7eb2e8f9f7 5511 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000U) /*!< Interrupt pending flag */
<> 144:ef7eb2e8f9f7 5512 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
<> 144:ef7eb2e8f9f7 5513 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000U) /*!< Clear pending SysTick bit */
<> 144:ef7eb2e8f9f7 5514 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000U) /*!< Set pending SysTick bit */
<> 144:ef7eb2e8f9f7 5515 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000U) /*!< Clear pending pendSV bit */
<> 144:ef7eb2e8f9f7 5516 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000U) /*!< Set pending pendSV bit */
<> 144:ef7eb2e8f9f7 5517 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000U) /*!< Set pending NMI bit */
mbed_official 67:4bcbbb9fcddf 5518
mbed_official 67:4bcbbb9fcddf 5519 /******************* Bit definition for SCB_VTOR register *******************/
<> 144:ef7eb2e8f9f7 5520 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80U) /*!< Vector table base offset field */
<> 144:ef7eb2e8f9f7 5521 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000U) /*!< Table base in code(0) or RAM(1) */
mbed_official 67:4bcbbb9fcddf 5522
mbed_official 67:4bcbbb9fcddf 5523 /*!<***************** Bit definition for SCB_AIRCR register *******************/
<> 144:ef7eb2e8f9f7 5524 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001U) /*!< System Reset bit */
<> 144:ef7eb2e8f9f7 5525 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002U) /*!< Clear active vector bit */
<> 144:ef7eb2e8f9f7 5526 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004U) /*!< Requests chip control logic to generate a reset */
<> 144:ef7eb2e8f9f7 5527
<> 144:ef7eb2e8f9f7 5528 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */
<> 144:ef7eb2e8f9f7 5529 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5530 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5531 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
mbed_official 67:4bcbbb9fcddf 5532
mbed_official 67:4bcbbb9fcddf 5533 /* prority group configuration */
<> 144:ef7eb2e8f9f7 5534 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
<> 144:ef7eb2e8f9f7 5535 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
<> 144:ef7eb2e8f9f7 5536 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
<> 144:ef7eb2e8f9f7 5537 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
<> 144:ef7eb2e8f9f7 5538 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
<> 144:ef7eb2e8f9f7 5539 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
<> 144:ef7eb2e8f9f7 5540 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
<> 144:ef7eb2e8f9f7 5541 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
<> 144:ef7eb2e8f9f7 5542
<> 144:ef7eb2e8f9f7 5543 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000U) /*!< Data endianness bit */
<> 144:ef7eb2e8f9f7 5544 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
mbed_official 67:4bcbbb9fcddf 5545
mbed_official 67:4bcbbb9fcddf 5546 /******************* Bit definition for SCB_SCR register ********************/
<> 144:ef7eb2e8f9f7 5547 #define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002U) /*!< Sleep on exit bit */
<> 144:ef7eb2e8f9f7 5548 #define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004U) /*!< Sleep deep bit */
<> 144:ef7eb2e8f9f7 5549 #define SCB_SCR_SEVONPEND ((uint32_t)0x00000010U) /*!< Wake up from WFE */
mbed_official 67:4bcbbb9fcddf 5550
mbed_official 67:4bcbbb9fcddf 5551 /******************** Bit definition for SCB_CCR register *******************/
<> 144:ef7eb2e8f9f7 5552 #define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
<> 144:ef7eb2e8f9f7 5553 #define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
<> 144:ef7eb2e8f9f7 5554 #define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008U) /*!< Trap for unaligned access */
<> 144:ef7eb2e8f9f7 5555 #define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010U) /*!< Trap on Divide by 0 */
<> 144:ef7eb2e8f9f7 5556 #define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100U) /*!< Handlers running at priority -1 and -2 */
<> 144:ef7eb2e8f9f7 5557 #define SCB_CCR_STKALIGN ((uint32_t)0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
mbed_official 67:4bcbbb9fcddf 5558
mbed_official 67:4bcbbb9fcddf 5559 /******************* Bit definition for SCB_SHPR register ********************/
<> 144:ef7eb2e8f9f7 5560 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FFU) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
<> 144:ef7eb2e8f9f7 5561 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00U) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
<> 144:ef7eb2e8f9f7 5562 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000U) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
<> 144:ef7eb2e8f9f7 5563 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000U) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
mbed_official 67:4bcbbb9fcddf 5564
mbed_official 67:4bcbbb9fcddf 5565 /****************** Bit definition for SCB_SHCSR register *******************/
<> 144:ef7eb2e8f9f7 5566 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001U) /*!< MemManage is active */
<> 144:ef7eb2e8f9f7 5567 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002U) /*!< BusFault is active */
<> 144:ef7eb2e8f9f7 5568 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008U) /*!< UsageFault is active */
<> 144:ef7eb2e8f9f7 5569 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080U) /*!< SVCall is active */
<> 144:ef7eb2e8f9f7 5570 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100U) /*!< Monitor is active */
<> 144:ef7eb2e8f9f7 5571 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400U) /*!< PendSV is active */
<> 144:ef7eb2e8f9f7 5572 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800U) /*!< SysTick is active */
<> 144:ef7eb2e8f9f7 5573 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000U) /*!< Usage Fault is pended */
<> 144:ef7eb2e8f9f7 5574 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000U) /*!< MemManage is pended */
<> 144:ef7eb2e8f9f7 5575 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000U) /*!< Bus Fault is pended */
<> 144:ef7eb2e8f9f7 5576 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000U) /*!< SVCall is pended */
<> 144:ef7eb2e8f9f7 5577 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000U) /*!< MemManage enable */
<> 144:ef7eb2e8f9f7 5578 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000U) /*!< Bus Fault enable */
<> 144:ef7eb2e8f9f7 5579 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000U) /*!< UsageFault enable */
mbed_official 67:4bcbbb9fcddf 5580
mbed_official 67:4bcbbb9fcddf 5581 /******************* Bit definition for SCB_CFSR register *******************/
mbed_official 67:4bcbbb9fcddf 5582 /*!< MFSR */
<> 144:ef7eb2e8f9f7 5583 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001U) /*!< Instruction access violation */
<> 144:ef7eb2e8f9f7 5584 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002U) /*!< Data access violation */
<> 144:ef7eb2e8f9f7 5585 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008U) /*!< Unstacking error */
<> 144:ef7eb2e8f9f7 5586 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010U) /*!< Stacking error */
<> 144:ef7eb2e8f9f7 5587 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080U) /*!< Memory Manage Address Register address valid flag */
mbed_official 67:4bcbbb9fcddf 5588 /*!< BFSR */
<> 144:ef7eb2e8f9f7 5589 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100U) /*!< Instruction bus error flag */
<> 144:ef7eb2e8f9f7 5590 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200U) /*!< Precise data bus error */
<> 144:ef7eb2e8f9f7 5591 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400U) /*!< Imprecise data bus error */
<> 144:ef7eb2e8f9f7 5592 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800U) /*!< Unstacking error */
<> 144:ef7eb2e8f9f7 5593 #define SCB_CFSR_STKERR ((uint32_t)0x00001000U) /*!< Stacking error */
<> 144:ef7eb2e8f9f7 5594 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000U) /*!< Bus Fault Address Register address valid flag */
mbed_official 67:4bcbbb9fcddf 5595 /*!< UFSR */
<> 144:ef7eb2e8f9f7 5596 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000U) /*!< The processor attempt to excecute an undefined instruction */
<> 144:ef7eb2e8f9f7 5597 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000U) /*!< Invalid combination of EPSR and instruction */
<> 144:ef7eb2e8f9f7 5598 #define SCB_CFSR_INVPC ((uint32_t)0x00040000U) /*!< Attempt to load EXC_RETURN into pc illegally */
<> 144:ef7eb2e8f9f7 5599 #define SCB_CFSR_NOCP ((uint32_t)0x00080000U) /*!< Attempt to use a coprocessor instruction */
<> 144:ef7eb2e8f9f7 5600 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000U) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
<> 144:ef7eb2e8f9f7 5601 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000U) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
mbed_official 67:4bcbbb9fcddf 5602
mbed_official 67:4bcbbb9fcddf 5603 /******************* Bit definition for SCB_HFSR register *******************/
<> 144:ef7eb2e8f9f7 5604 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002U) /*!< Fault occures because of vector table read on exception processing */
<> 144:ef7eb2e8f9f7 5605 #define SCB_HFSR_FORCED ((uint32_t)0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
<> 144:ef7eb2e8f9f7 5606 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000U) /*!< Fault related to debug */
mbed_official 67:4bcbbb9fcddf 5607
mbed_official 67:4bcbbb9fcddf 5608 /******************* Bit definition for SCB_DFSR register *******************/
<> 144:ef7eb2e8f9f7 5609 #define SCB_DFSR_HALTED ((uint32_t)0x00000001U) /*!< Halt request flag */
<> 144:ef7eb2e8f9f7 5610 #define SCB_DFSR_BKPT ((uint32_t)0x00000002U) /*!< BKPT flag */
<> 144:ef7eb2e8f9f7 5611 #define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */
<> 144:ef7eb2e8f9f7 5612 #define SCB_DFSR_VCATCH ((uint32_t)0x00000008U) /*!< Vector catch flag */
<> 144:ef7eb2e8f9f7 5613 #define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010U) /*!< External debug request flag */
mbed_official 67:4bcbbb9fcddf 5614
mbed_official 67:4bcbbb9fcddf 5615 /******************* Bit definition for SCB_MMFAR register ******************/
<> 144:ef7eb2e8f9f7 5616 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFFU) /*!< Mem Manage fault address field */
mbed_official 67:4bcbbb9fcddf 5617
mbed_official 67:4bcbbb9fcddf 5618 /******************* Bit definition for SCB_BFAR register *******************/
<> 144:ef7eb2e8f9f7 5619 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFFU) /*!< Bus fault address field */
mbed_official 67:4bcbbb9fcddf 5620
mbed_official 67:4bcbbb9fcddf 5621 /******************* Bit definition for SCB_afsr register *******************/
<> 144:ef7eb2e8f9f7 5622 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFFU) /*!< Implementation defined */
mbed_official 67:4bcbbb9fcddf 5623 /**
mbed_official 67:4bcbbb9fcddf 5624 * @}
mbed_official 67:4bcbbb9fcddf 5625 */
mbed_official 67:4bcbbb9fcddf 5626
mbed_official 67:4bcbbb9fcddf 5627 /**
mbed_official 67:4bcbbb9fcddf 5628 * @}
mbed_official 67:4bcbbb9fcddf 5629 */
mbed_official 67:4bcbbb9fcddf 5630 /** @addtogroup Exported_macro
mbed_official 67:4bcbbb9fcddf 5631 * @{
mbed_official 67:4bcbbb9fcddf 5632 */
mbed_official 67:4bcbbb9fcddf 5633
mbed_official 67:4bcbbb9fcddf 5634 /****************************** ADC Instances *********************************/
mbed_official 67:4bcbbb9fcddf 5635 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official 67:4bcbbb9fcddf 5636
<> 144:ef7eb2e8f9f7 5637 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
<> 144:ef7eb2e8f9f7 5638
mbed_official 67:4bcbbb9fcddf 5639 /******************************** COMP Instances ******************************/
mbed_official 67:4bcbbb9fcddf 5640 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
mbed_official 67:4bcbbb9fcddf 5641 ((INSTANCE) == COMP2))
mbed_official 67:4bcbbb9fcddf 5642
mbed_official 67:4bcbbb9fcddf 5643 /****************************** CRC Instances *********************************/
mbed_official 67:4bcbbb9fcddf 5644 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 67:4bcbbb9fcddf 5645
mbed_official 67:4bcbbb9fcddf 5646 /****************************** DAC Instances *********************************/
mbed_official 67:4bcbbb9fcddf 5647 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 67:4bcbbb9fcddf 5648
mbed_official 67:4bcbbb9fcddf 5649 /****************************** DMA Instances *********************************/
mbed_official 67:4bcbbb9fcddf 5650 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
mbed_official 67:4bcbbb9fcddf 5651 ((INSTANCE) == DMA1_Channel2) || \
mbed_official 67:4bcbbb9fcddf 5652 ((INSTANCE) == DMA1_Channel3) || \
mbed_official 67:4bcbbb9fcddf 5653 ((INSTANCE) == DMA1_Channel4) || \
mbed_official 67:4bcbbb9fcddf 5654 ((INSTANCE) == DMA1_Channel5) || \
mbed_official 67:4bcbbb9fcddf 5655 ((INSTANCE) == DMA1_Channel6) || \
mbed_official 67:4bcbbb9fcddf 5656 ((INSTANCE) == DMA1_Channel7) || \
mbed_official 67:4bcbbb9fcddf 5657 ((INSTANCE) == DMA2_Channel1) || \
mbed_official 67:4bcbbb9fcddf 5658 ((INSTANCE) == DMA2_Channel2) || \
mbed_official 67:4bcbbb9fcddf 5659 ((INSTANCE) == DMA2_Channel3) || \
mbed_official 67:4bcbbb9fcddf 5660 ((INSTANCE) == DMA2_Channel4) || \
mbed_official 67:4bcbbb9fcddf 5661 ((INSTANCE) == DMA2_Channel5))
mbed_official 67:4bcbbb9fcddf 5662
mbed_official 67:4bcbbb9fcddf 5663 /******************************* GPIO Instances *******************************/
mbed_official 67:4bcbbb9fcddf 5664 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 67:4bcbbb9fcddf 5665 ((INSTANCE) == GPIOB) || \
mbed_official 67:4bcbbb9fcddf 5666 ((INSTANCE) == GPIOC) || \
mbed_official 67:4bcbbb9fcddf 5667 ((INSTANCE) == GPIOD) || \
mbed_official 67:4bcbbb9fcddf 5668 ((INSTANCE) == GPIOE) || \
mbed_official 67:4bcbbb9fcddf 5669 ((INSTANCE) == GPIOH))
mbed_official 67:4bcbbb9fcddf 5670
<> 144:ef7eb2e8f9f7 5671 /**************************** GPIO Alternate Function Instances ***************/
<> 144:ef7eb2e8f9f7 5672 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
<> 144:ef7eb2e8f9f7 5673
mbed_official 67:4bcbbb9fcddf 5674 /**************************** GPIO Lock Instances *****************************/
mbed_official 67:4bcbbb9fcddf 5675 /* On L1, all GPIO Bank support the Lock mechanism */
mbed_official 67:4bcbbb9fcddf 5676 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
mbed_official 67:4bcbbb9fcddf 5677
mbed_official 67:4bcbbb9fcddf 5678 /******************************** I2C Instances *******************************/
mbed_official 67:4bcbbb9fcddf 5679 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 67:4bcbbb9fcddf 5680 ((INSTANCE) == I2C2))
mbed_official 67:4bcbbb9fcddf 5681
<> 144:ef7eb2e8f9f7 5682 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
mbed_official 67:4bcbbb9fcddf 5683 ((INSTANCE) == SPI3))
mbed_official 67:4bcbbb9fcddf 5684 /****************************** IWDG Instances ********************************/
mbed_official 67:4bcbbb9fcddf 5685 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 67:4bcbbb9fcddf 5686
mbed_official 67:4bcbbb9fcddf 5687 /****************************** OPAMP Instances *******************************/
mbed_official 67:4bcbbb9fcddf 5688 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
mbed_official 67:4bcbbb9fcddf 5689 ((INSTANCE) == OPAMP2))
mbed_official 67:4bcbbb9fcddf 5690
mbed_official 67:4bcbbb9fcddf 5691 /****************************** RTC Instances *********************************/
mbed_official 67:4bcbbb9fcddf 5692 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 67:4bcbbb9fcddf 5693
mbed_official 67:4bcbbb9fcddf 5694 /******************************** SPI Instances *******************************/
mbed_official 67:4bcbbb9fcddf 5695 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 67:4bcbbb9fcddf 5696 ((INSTANCE) == SPI2) || \
mbed_official 67:4bcbbb9fcddf 5697 ((INSTANCE) == SPI3))
mbed_official 67:4bcbbb9fcddf 5698
mbed_official 67:4bcbbb9fcddf 5699 /****************************** TIM Instances *********************************/
mbed_official 67:4bcbbb9fcddf 5700 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5701 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5702 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5703 ((INSTANCE) == TIM5) || \
mbed_official 67:4bcbbb9fcddf 5704 ((INSTANCE) == TIM6) || \
mbed_official 67:4bcbbb9fcddf 5705 ((INSTANCE) == TIM7) || \
mbed_official 67:4bcbbb9fcddf 5706 ((INSTANCE) == TIM9) || \
mbed_official 67:4bcbbb9fcddf 5707 ((INSTANCE) == TIM10) || \
mbed_official 67:4bcbbb9fcddf 5708 ((INSTANCE) == TIM11))
mbed_official 67:4bcbbb9fcddf 5709
mbed_official 67:4bcbbb9fcddf 5710 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5711 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5712 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5713 ((INSTANCE) == TIM5) || \
mbed_official 67:4bcbbb9fcddf 5714 ((INSTANCE) == TIM9) || \
mbed_official 67:4bcbbb9fcddf 5715 ((INSTANCE) == TIM10) || \
mbed_official 67:4bcbbb9fcddf 5716 ((INSTANCE) == TIM11))
mbed_official 67:4bcbbb9fcddf 5717
mbed_official 67:4bcbbb9fcddf 5718 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5719 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5720 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5721 ((INSTANCE) == TIM5) || \
mbed_official 67:4bcbbb9fcddf 5722 ((INSTANCE) == TIM9))
mbed_official 67:4bcbbb9fcddf 5723
mbed_official 67:4bcbbb9fcddf 5724 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5725 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5726 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5727 ((INSTANCE) == TIM5))
mbed_official 67:4bcbbb9fcddf 5728
mbed_official 67:4bcbbb9fcddf 5729 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5730 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5731 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5732 ((INSTANCE) == TIM5))
mbed_official 67:4bcbbb9fcddf 5733
mbed_official 67:4bcbbb9fcddf 5734 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5735 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5736 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5737 ((INSTANCE) == TIM5) || \
mbed_official 67:4bcbbb9fcddf 5738 ((INSTANCE) == TIM9))
mbed_official 67:4bcbbb9fcddf 5739
mbed_official 67:4bcbbb9fcddf 5740 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5741 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5742 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5743 ((INSTANCE) == TIM5) || \
mbed_official 67:4bcbbb9fcddf 5744 ((INSTANCE) == TIM9) || \
mbed_official 67:4bcbbb9fcddf 5745 ((INSTANCE) == TIM10) || \
mbed_official 67:4bcbbb9fcddf 5746 ((INSTANCE) == TIM11))
mbed_official 67:4bcbbb9fcddf 5747
mbed_official 67:4bcbbb9fcddf 5748 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5749 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5750 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5751 ((INSTANCE) == TIM5) || \
mbed_official 67:4bcbbb9fcddf 5752 ((INSTANCE) == TIM9))
mbed_official 67:4bcbbb9fcddf 5753
mbed_official 67:4bcbbb9fcddf 5754 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5755 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5756 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5757 ((INSTANCE) == TIM5) || \
mbed_official 67:4bcbbb9fcddf 5758 ((INSTANCE) == TIM9))
mbed_official 67:4bcbbb9fcddf 5759
mbed_official 67:4bcbbb9fcddf 5760 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5761 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5762 ((INSTANCE) == TIM4))
mbed_official 67:4bcbbb9fcddf 5763
mbed_official 67:4bcbbb9fcddf 5764 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5765 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5766 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5767 ((INSTANCE) == TIM5))
mbed_official 67:4bcbbb9fcddf 5768
mbed_official 67:4bcbbb9fcddf 5769 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5770 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5771 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5772 ((INSTANCE) == TIM5) || \
mbed_official 67:4bcbbb9fcddf 5773 ((INSTANCE) == TIM6) || \
mbed_official 67:4bcbbb9fcddf 5774 ((INSTANCE) == TIM7) || \
mbed_official 67:4bcbbb9fcddf 5775 ((INSTANCE) == TIM9))
mbed_official 67:4bcbbb9fcddf 5776
mbed_official 67:4bcbbb9fcddf 5777 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5778 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5779 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5780 ((INSTANCE) == TIM5) || \
mbed_official 67:4bcbbb9fcddf 5781 ((INSTANCE) == TIM9))
mbed_official 67:4bcbbb9fcddf 5782
mbed_official 67:4bcbbb9fcddf 5783 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
mbed_official 67:4bcbbb9fcddf 5784
mbed_official 67:4bcbbb9fcddf 5785 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5786 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5787 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5788 ((INSTANCE) == TIM5))
mbed_official 67:4bcbbb9fcddf 5789
mbed_official 67:4bcbbb9fcddf 5790 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 67:4bcbbb9fcddf 5791 ((((INSTANCE) == TIM2) && \
mbed_official 67:4bcbbb9fcddf 5792 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 67:4bcbbb9fcddf 5793 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 67:4bcbbb9fcddf 5794 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 67:4bcbbb9fcddf 5795 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 67:4bcbbb9fcddf 5796 || \
mbed_official 67:4bcbbb9fcddf 5797 (((INSTANCE) == TIM3) && \
mbed_official 67:4bcbbb9fcddf 5798 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 67:4bcbbb9fcddf 5799 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 67:4bcbbb9fcddf 5800 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 67:4bcbbb9fcddf 5801 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 67:4bcbbb9fcddf 5802 || \
mbed_official 67:4bcbbb9fcddf 5803 (((INSTANCE) == TIM4) && \
mbed_official 67:4bcbbb9fcddf 5804 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 67:4bcbbb9fcddf 5805 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 67:4bcbbb9fcddf 5806 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 67:4bcbbb9fcddf 5807 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 67:4bcbbb9fcddf 5808 || \
mbed_official 67:4bcbbb9fcddf 5809 (((INSTANCE) == TIM5) && \
mbed_official 67:4bcbbb9fcddf 5810 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 67:4bcbbb9fcddf 5811 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 67:4bcbbb9fcddf 5812 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 67:4bcbbb9fcddf 5813 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 67:4bcbbb9fcddf 5814 || \
mbed_official 67:4bcbbb9fcddf 5815 (((INSTANCE) == TIM9) && \
mbed_official 67:4bcbbb9fcddf 5816 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 67:4bcbbb9fcddf 5817 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 67:4bcbbb9fcddf 5818 || \
mbed_official 67:4bcbbb9fcddf 5819 (((INSTANCE) == TIM10) && \
mbed_official 67:4bcbbb9fcddf 5820 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 67:4bcbbb9fcddf 5821 || \
mbed_official 67:4bcbbb9fcddf 5822 (((INSTANCE) == TIM11) && \
mbed_official 67:4bcbbb9fcddf 5823 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 67:4bcbbb9fcddf 5824
mbed_official 67:4bcbbb9fcddf 5825 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5826 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5827 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5828 ((INSTANCE) == TIM5) || \
mbed_official 67:4bcbbb9fcddf 5829 ((INSTANCE) == TIM9) || \
mbed_official 67:4bcbbb9fcddf 5830 ((INSTANCE) == TIM10) || \
mbed_official 67:4bcbbb9fcddf 5831 ((INSTANCE) == TIM11))
mbed_official 67:4bcbbb9fcddf 5832
mbed_official 67:4bcbbb9fcddf 5833 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5834 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5835 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5836 ((INSTANCE) == TIM5) || \
mbed_official 67:4bcbbb9fcddf 5837 ((INSTANCE) == TIM6) || \
mbed_official 67:4bcbbb9fcddf 5838 ((INSTANCE) == TIM7))
mbed_official 67:4bcbbb9fcddf 5839
mbed_official 67:4bcbbb9fcddf 5840 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5841 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5842 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5843 ((INSTANCE) == TIM5))
mbed_official 67:4bcbbb9fcddf 5844
mbed_official 67:4bcbbb9fcddf 5845 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5846 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5847 ((INSTANCE) == TIM4) || \
mbed_official 67:4bcbbb9fcddf 5848 ((INSTANCE) == TIM5) || \
mbed_official 67:4bcbbb9fcddf 5849 ((INSTANCE) == TIM9))
mbed_official 67:4bcbbb9fcddf 5850
mbed_official 67:4bcbbb9fcddf 5851 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5852 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5853 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 5854 ((INSTANCE) == TIM5))
mbed_official 67:4bcbbb9fcddf 5855
mbed_official 67:4bcbbb9fcddf 5856 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 67:4bcbbb9fcddf 5857 ((INSTANCE) == TIM3) || \
mbed_official 67:4bcbbb9fcddf 5858 ((INSTANCE) == TIM9) || \
mbed_official 67:4bcbbb9fcddf 5859 ((INSTANCE) == TIM10) || \
mbed_official 67:4bcbbb9fcddf 5860 ((INSTANCE) == TIM11))
mbed_official 67:4bcbbb9fcddf 5861
mbed_official 67:4bcbbb9fcddf 5862 /******************** USART Instances : Synchronous mode **********************/
mbed_official 67:4bcbbb9fcddf 5863 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 67:4bcbbb9fcddf 5864 ((INSTANCE) == USART2) || \
mbed_official 67:4bcbbb9fcddf 5865 ((INSTANCE) == USART3))
mbed_official 67:4bcbbb9fcddf 5866
mbed_official 67:4bcbbb9fcddf 5867 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 67:4bcbbb9fcddf 5868 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 67:4bcbbb9fcddf 5869 ((INSTANCE) == USART2) || \
mbed_official 67:4bcbbb9fcddf 5870 ((INSTANCE) == USART3))
mbed_official 67:4bcbbb9fcddf 5871
mbed_official 67:4bcbbb9fcddf 5872 /******************** UART Instances : Half-Duplex mode **********************/
mbed_official 67:4bcbbb9fcddf 5873 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 67:4bcbbb9fcddf 5874 ((INSTANCE) == USART2) || \
mbed_official 67:4bcbbb9fcddf 5875 ((INSTANCE) == USART3))
mbed_official 67:4bcbbb9fcddf 5876
mbed_official 67:4bcbbb9fcddf 5877 /******************** UART Instances : LIN mode **********************/
mbed_official 67:4bcbbb9fcddf 5878 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 67:4bcbbb9fcddf 5879 ((INSTANCE) == USART2) || \
mbed_official 67:4bcbbb9fcddf 5880 ((INSTANCE) == USART3))
mbed_official 67:4bcbbb9fcddf 5881
mbed_official 67:4bcbbb9fcddf 5882 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 67:4bcbbb9fcddf 5883 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 67:4bcbbb9fcddf 5884 ((INSTANCE) == USART2) || \
mbed_official 67:4bcbbb9fcddf 5885 ((INSTANCE) == USART3))
mbed_official 67:4bcbbb9fcddf 5886
mbed_official 67:4bcbbb9fcddf 5887 /********************* UART Instances : Smard card mode ***********************/
mbed_official 67:4bcbbb9fcddf 5888 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 67:4bcbbb9fcddf 5889 ((INSTANCE) == USART2) || \
mbed_official 67:4bcbbb9fcddf 5890 ((INSTANCE) == USART3))
mbed_official 67:4bcbbb9fcddf 5891
mbed_official 67:4bcbbb9fcddf 5892 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 67:4bcbbb9fcddf 5893 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 67:4bcbbb9fcddf 5894 ((INSTANCE) == USART2) || \
mbed_official 67:4bcbbb9fcddf 5895 ((INSTANCE) == USART3))
mbed_official 67:4bcbbb9fcddf 5896
mbed_official 67:4bcbbb9fcddf 5897 /***************** UART Instances : Multi-Processor mode **********************/
mbed_official 67:4bcbbb9fcddf 5898 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 67:4bcbbb9fcddf 5899 ((INSTANCE) == USART2) || \
mbed_official 67:4bcbbb9fcddf 5900 ((INSTANCE) == USART3))
mbed_official 67:4bcbbb9fcddf 5901
mbed_official 67:4bcbbb9fcddf 5902 /****************************** WWDG Instances ********************************/
mbed_official 67:4bcbbb9fcddf 5903 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 67:4bcbbb9fcddf 5904
mbed_official 67:4bcbbb9fcddf 5905 /****************************** USB Instances ********************************/
mbed_official 67:4bcbbb9fcddf 5906 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
mbed_official 67:4bcbbb9fcddf 5907
mbed_official 67:4bcbbb9fcddf 5908 /**
mbed_official 67:4bcbbb9fcddf 5909 * @}
mbed_official 67:4bcbbb9fcddf 5910 */
mbed_official 67:4bcbbb9fcddf 5911
mbed_official 67:4bcbbb9fcddf 5912 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 5913 /* For a painless codes migration between the STM32L1xx device product */
mbed_official 67:4bcbbb9fcddf 5914 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 67:4bcbbb9fcddf 5915 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 67:4bcbbb9fcddf 5916 /* No need to update developed interrupt code when moving across */
mbed_official 67:4bcbbb9fcddf 5917 /* product lines within the same STM32L1 Family */
mbed_official 67:4bcbbb9fcddf 5918 /******************************************************************************/
mbed_official 67:4bcbbb9fcddf 5919
mbed_official 67:4bcbbb9fcddf 5920 /* Aliases for __IRQn */
mbed_official 67:4bcbbb9fcddf 5921
mbed_official 67:4bcbbb9fcddf 5922 /* Aliases for __IRQHandler */
mbed_official 67:4bcbbb9fcddf 5923
mbed_official 67:4bcbbb9fcddf 5924 /**
mbed_official 67:4bcbbb9fcddf 5925 * @}
mbed_official 67:4bcbbb9fcddf 5926 */
mbed_official 67:4bcbbb9fcddf 5927
mbed_official 67:4bcbbb9fcddf 5928 /**
mbed_official 67:4bcbbb9fcddf 5929 * @}
mbed_official 67:4bcbbb9fcddf 5930 */
mbed_official 67:4bcbbb9fcddf 5931
mbed_official 67:4bcbbb9fcddf 5932 #ifdef __cplusplus
mbed_official 67:4bcbbb9fcddf 5933 }
mbed_official 67:4bcbbb9fcddf 5934 #endif /* __cplusplus */
mbed_official 67:4bcbbb9fcddf 5935
mbed_official 67:4bcbbb9fcddf 5936 #endif /* __STM32L151xC_H */
mbed_official 67:4bcbbb9fcddf 5937
mbed_official 67:4bcbbb9fcddf 5938
mbed_official 67:4bcbbb9fcddf 5939
mbed_official 67:4bcbbb9fcddf 5940 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/