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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cortex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
124:6a4a5b7d7324 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_cortex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief CORTEX HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the CORTEX:
<> 144:ef7eb2e8f9f7 11 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 *** How to configure Interrupts using Cortex HAL driver ***
<> 144:ef7eb2e8f9f7 21 ===========================================================
<> 144:ef7eb2e8f9f7 22 [..]
<> 144:ef7eb2e8f9f7 23 This section provide functions allowing to configure the NVIC interrupts (IRQ).
<> 144:ef7eb2e8f9f7 24 The Cortex-M3 exceptions are managed by CMSIS functions.
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
<> 144:ef7eb2e8f9f7 27 function according to the following table.
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 The table below gives the allowed values of the pre-emption priority and subpriority according
<> 144:ef7eb2e8f9f7 30 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
<> 144:ef7eb2e8f9f7 31 ==========================================================================================================================
<> 144:ef7eb2e8f9f7 32 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
<> 144:ef7eb2e8f9f7 33 ==========================================================================================================================
<> 144:ef7eb2e8f9f7 34 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 35 | | | 4 bits for subpriority
<> 144:ef7eb2e8f9f7 36 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 37 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 38 | | | 3 bits for subpriority
<> 144:ef7eb2e8f9f7 39 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 40 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 41 | | | 2 bits for subpriority
<> 144:ef7eb2e8f9f7 42 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 43 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 44 | | | 1 bits for subpriority
<> 144:ef7eb2e8f9f7 45 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 46 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 47 | | | 0 bits for subpriority
<> 144:ef7eb2e8f9f7 48 ==========================================================================================================================
<> 144:ef7eb2e8f9f7 49 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
<> 144:ef7eb2e8f9f7 55 The pending IRQ priority will be managed only by the sub priority.
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 -@- IRQ priority order (sorted by highest to lowest priority):
<> 144:ef7eb2e8f9f7 58 (+@) Lowest pre-emption priority
<> 144:ef7eb2e8f9f7 59 (+@) Lowest sub priority
<> 144:ef7eb2e8f9f7 60 (+@) Lowest hardware priority (IRQ number)
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 [..]
<> 144:ef7eb2e8f9f7 63 *** How to configure Systick using Cortex HAL driver ***
<> 144:ef7eb2e8f9f7 64 ========================================================
<> 144:ef7eb2e8f9f7 65 [..]
<> 144:ef7eb2e8f9f7 66 Setup SysTick Timer for 1 msec interrupts.
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
<> 144:ef7eb2e8f9f7 69 is a CMSIS function that:
<> 144:ef7eb2e8f9f7 70 (++) Configures the SysTick Reload register with value passed as function parameter.
<> 144:ef7eb2e8f9f7 71 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
<> 144:ef7eb2e8f9f7 72 (++) Resets the SysTick Counter register.
<> 144:ef7eb2e8f9f7 73 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
<> 144:ef7eb2e8f9f7 74 (++) Enables the SysTick Interrupt.
<> 144:ef7eb2e8f9f7 75 (++) Starts the SysTick Counter.
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function
<> 144:ef7eb2e8f9f7 78 HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
<> 144:ef7eb2e8f9f7 79 HAL_SYSTICK_Config() function call.
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 (+) You can change the SysTick IRQ priority by calling the
<> 144:ef7eb2e8f9f7 82 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 83 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 (+) To adjust the SysTick time base, use the following formula:
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
<> 144:ef7eb2e8f9f7 88 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 89 (++) Reload Value should not exceed 0xFFFFFF
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 @endverbatim
<> 144:ef7eb2e8f9f7 92 ******************************************************************************
<> 144:ef7eb2e8f9f7 93 * @attention
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 96 *
<> 144:ef7eb2e8f9f7 97 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 98 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 99 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 100 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 101 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 102 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 103 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 104 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 105 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 106 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 107 *
<> 144:ef7eb2e8f9f7 108 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 109 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 110 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 111 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 112 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 113 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 114 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 115 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 116 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 117 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 118 *
<> 144:ef7eb2e8f9f7 119 ******************************************************************************
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 123 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 126 * @{
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** @defgroup CORTEX CORTEX
<> 144:ef7eb2e8f9f7 130 * @brief CORTEX HAL module driver
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 #ifdef HAL_CORTEX_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 137 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 141 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
<> 144:ef7eb2e8f9f7 144 * @{
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 149 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 150 *
<> 144:ef7eb2e8f9f7 151 @verbatim
<> 144:ef7eb2e8f9f7 152 ==============================================================================
<> 144:ef7eb2e8f9f7 153 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 154 ==============================================================================
<> 144:ef7eb2e8f9f7 155 [..]
<> 144:ef7eb2e8f9f7 156 This section provide the Cortex HAL driver functions allowing to configure Interrupts
<> 144:ef7eb2e8f9f7 157 Systick functionalities
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 @endverbatim
<> 144:ef7eb2e8f9f7 160 * @{
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /**
<> 144:ef7eb2e8f9f7 165 * @brief Sets the priority grouping field (pre-emption priority and subpriority)
<> 144:ef7eb2e8f9f7 166 * using the required unlock sequence.
<> 144:ef7eb2e8f9f7 167 * @param PriorityGroup: The priority grouping bits length.
<> 144:ef7eb2e8f9f7 168 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 169 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 170 * 4 bits for subpriority
<> 144:ef7eb2e8f9f7 171 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 172 * 3 bits for subpriority
<> 144:ef7eb2e8f9f7 173 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 174 * 2 bits for subpriority
<> 144:ef7eb2e8f9f7 175 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 176 * 1 bits for subpriority
<> 144:ef7eb2e8f9f7 177 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 178 * 0 bits for subpriority
<> 144:ef7eb2e8f9f7 179 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
<> 144:ef7eb2e8f9f7 180 * The pending IRQ priority will be managed only by the subpriority.
<> 144:ef7eb2e8f9f7 181 * @retval None
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 /* Check the parameters */
<> 144:ef7eb2e8f9f7 186 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
<> 144:ef7eb2e8f9f7 189 NVIC_SetPriorityGrouping(PriorityGroup);
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /**
<> 144:ef7eb2e8f9f7 193 * @brief Sets the priority of an interrupt.
<> 144:ef7eb2e8f9f7 194 * @param IRQn: External interrupt number
<> 144:ef7eb2e8f9f7 195 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 196 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 197 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
<> 144:ef7eb2e8f9f7 198 * This parameter can be a value between 0 and 15
<> 144:ef7eb2e8f9f7 199 * A lower priority value indicates a higher priority
<> 144:ef7eb2e8f9f7 200 * @param SubPriority: the subpriority level for the IRQ channel.
<> 144:ef7eb2e8f9f7 201 * This parameter can be a value between 0 and 15
<> 144:ef7eb2e8f9f7 202 * A lower priority value indicates a higher priority.
<> 144:ef7eb2e8f9f7 203 * @retval None
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 uint32_t prioritygroup = 0x00;
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Check the parameters */
<> 144:ef7eb2e8f9f7 210 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
<> 144:ef7eb2e8f9f7 211 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 prioritygroup = NVIC_GetPriorityGrouping();
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
<> 144:ef7eb2e8f9f7 216 }
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /**
<> 144:ef7eb2e8f9f7 219 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 220 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
<> 144:ef7eb2e8f9f7 221 * function should be called before.
<> 144:ef7eb2e8f9f7 222 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 223 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 224 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 225 * @retval None
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 /* Check the parameters */
<> 144:ef7eb2e8f9f7 230 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* Enable interrupt */
<> 144:ef7eb2e8f9f7 233 NVIC_EnableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 238 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 239 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 240 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 241 * @retval None
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 /* Check the parameters */
<> 144:ef7eb2e8f9f7 246 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* Disable interrupt */
<> 144:ef7eb2e8f9f7 250 NVIC_DisableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @brief Initiates a system reset request to reset the MCU.
<> 144:ef7eb2e8f9f7 255 * @retval None
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 void HAL_NVIC_SystemReset(void)
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 /* System Reset */
<> 144:ef7eb2e8f9f7 260 NVIC_SystemReset();
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 144:ef7eb2e8f9f7 265 * Counter is in free running mode to generate periodic interrupts.
<> 144:ef7eb2e8f9f7 266 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
<> 144:ef7eb2e8f9f7 267 * @retval status: - 0 Function succeeded.
<> 144:ef7eb2e8f9f7 268 * - 1 Function failed.
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 return SysTick_Config(TicksNumb);
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @}
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 279 * @brief Cortex control functions
<> 144:ef7eb2e8f9f7 280 *
<> 144:ef7eb2e8f9f7 281 @verbatim
<> 144:ef7eb2e8f9f7 282 ==============================================================================
<> 144:ef7eb2e8f9f7 283 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 284 ==============================================================================
<> 144:ef7eb2e8f9f7 285 [..]
<> 144:ef7eb2e8f9f7 286 This subsection provides a set of functions allowing to control the CORTEX
<> 144:ef7eb2e8f9f7 287 (NVIC, SYSTICK, MPU) functionalities.
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 @endverbatim
<> 144:ef7eb2e8f9f7 291 * @{
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @brief Initializes and configures the Region and the memory to be protected.
<> 144:ef7eb2e8f9f7 297 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 298 * the initialization and configuration information.
<> 144:ef7eb2e8f9f7 299 * @retval None
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* Check the parameters */
<> 144:ef7eb2e8f9f7 304 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
<> 144:ef7eb2e8f9f7 305 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* Set the Region number */
<> 144:ef7eb2e8f9f7 308 MPU->RNR = MPU_Init->Number;
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 if ((MPU_Init->Enable) != RESET)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 /* Check the parameters */
<> 144:ef7eb2e8f9f7 313 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
<> 144:ef7eb2e8f9f7 314 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
<> 144:ef7eb2e8f9f7 315 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
<> 144:ef7eb2e8f9f7 316 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
<> 144:ef7eb2e8f9f7 317 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
<> 144:ef7eb2e8f9f7 318 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
<> 144:ef7eb2e8f9f7 319 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
<> 144:ef7eb2e8f9f7 320 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 MPU->RBAR = MPU_Init->BaseAddress;
<> 144:ef7eb2e8f9f7 323 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
<> 144:ef7eb2e8f9f7 324 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
<> 144:ef7eb2e8f9f7 325 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
<> 144:ef7eb2e8f9f7 326 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
<> 144:ef7eb2e8f9f7 327 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
<> 144:ef7eb2e8f9f7 328 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
<> 144:ef7eb2e8f9f7 329 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
<> 144:ef7eb2e8f9f7 330 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
<> 144:ef7eb2e8f9f7 331 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333 else
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 MPU->RBAR = 0x00;
<> 144:ef7eb2e8f9f7 336 MPU->RASR = 0x00;
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /**
<> 144:ef7eb2e8f9f7 342 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
<> 144:ef7eb2e8f9f7 343 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 uint32_t HAL_NVIC_GetPriorityGrouping(void)
<> 144:ef7eb2e8f9f7 346 {
<> 144:ef7eb2e8f9f7 347 /* Get the PRIGROUP[10:8] field value */
<> 144:ef7eb2e8f9f7 348 return NVIC_GetPriorityGrouping();
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @brief Gets the priority of an interrupt.
<> 144:ef7eb2e8f9f7 353 * @param IRQn: External interrupt number
<> 144:ef7eb2e8f9f7 354 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 355 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 356 * @param PriorityGroup: the priority grouping bits length.
<> 144:ef7eb2e8f9f7 357 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 358 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 359 * 4 bits for subpriority
<> 144:ef7eb2e8f9f7 360 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 361 * 3 bits for subpriority
<> 144:ef7eb2e8f9f7 362 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 363 * 2 bits for subpriority
<> 144:ef7eb2e8f9f7 364 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 365 * 1 bits for subpriority
<> 144:ef7eb2e8f9f7 366 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 367 * 0 bits for subpriority
<> 144:ef7eb2e8f9f7 368 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
<> 144:ef7eb2e8f9f7 369 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
<> 144:ef7eb2e8f9f7 370 * @retval None
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<> 144:ef7eb2e8f9f7 373 {
<> 144:ef7eb2e8f9f7 374 /* Check the parameters */
<> 144:ef7eb2e8f9f7 375 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 144:ef7eb2e8f9f7 376 /* Get priority for Cortex-M system or device specific interrupts */
<> 144:ef7eb2e8f9f7 377 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @brief Sets Pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 382 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 383 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 384 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 385 * @retval None
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 /* Set interrupt pending */
<> 144:ef7eb2e8f9f7 390 NVIC_SetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 391 }
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
<> 144:ef7eb2e8f9f7 395 * and returns the pending bit for the specified interrupt).
<> 144:ef7eb2e8f9f7 396 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 397 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 398 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 399 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 400 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 /* Return 1 if pending else 0 */
<> 144:ef7eb2e8f9f7 405 return NVIC_GetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /**
<> 144:ef7eb2e8f9f7 409 * @brief Clears the pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 410 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 411 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 412 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 413 * @retval None
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 416 {
<> 144:ef7eb2e8f9f7 417 /* Clear pending interrupt */
<> 144:ef7eb2e8f9f7 418 NVIC_ClearPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 419 }
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /**
<> 144:ef7eb2e8f9f7 422 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
<> 144:ef7eb2e8f9f7 423 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 424 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 425 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 426 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 427 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 /* Return 1 if active else 0 */
<> 144:ef7eb2e8f9f7 432 return NVIC_GetActive(IRQn);
<> 144:ef7eb2e8f9f7 433 }
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /**
<> 144:ef7eb2e8f9f7 436 * @brief Configures the SysTick clock source.
<> 144:ef7eb2e8f9f7 437 * @param CLKSource: specifies the SysTick clock source.
<> 144:ef7eb2e8f9f7 438 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 439 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 440 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 441 * @retval None
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 /* Check the parameters */
<> 144:ef7eb2e8f9f7 446 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
<> 144:ef7eb2e8f9f7 447 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
<> 144:ef7eb2e8f9f7 448 {
<> 144:ef7eb2e8f9f7 449 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451 else
<> 144:ef7eb2e8f9f7 452 {
<> 144:ef7eb2e8f9f7 453 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 454 }
<> 144:ef7eb2e8f9f7 455 }
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /**
<> 144:ef7eb2e8f9f7 458 * @brief This function handles SYSTICK interrupt request.
<> 144:ef7eb2e8f9f7 459 * @retval None
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461 void HAL_SYSTICK_IRQHandler(void)
<> 144:ef7eb2e8f9f7 462 {
<> 144:ef7eb2e8f9f7 463 HAL_SYSTICK_Callback();
<> 144:ef7eb2e8f9f7 464 }
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @brief SYSTICK callback.
<> 144:ef7eb2e8f9f7 468 * @retval None
<> 144:ef7eb2e8f9f7 469 */
<> 144:ef7eb2e8f9f7 470 __weak void HAL_SYSTICK_Callback(void)
<> 144:ef7eb2e8f9f7 471 {
<> 144:ef7eb2e8f9f7 472 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 473 the HAL_SYSTICK_Callback could be implemented in the user file
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @}
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /**
<> 144:ef7eb2e8f9f7 482 * @}
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 #endif /* HAL_CORTEX_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 486 /**
<> 144:ef7eb2e8f9f7 487 * @}
<> 144:ef7eb2e8f9f7 488 */
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /**
<> 144:ef7eb2e8f9f7 491 * @}
<> 144:ef7eb2e8f9f7 492 */
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/