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targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.s@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
<> 144:ef7eb2e8f9f7 2 ;* File Name : startup_stm32f031x6.s
<> 144:ef7eb2e8f9f7 3 ;* Author : MCD Application Team
<> 144:ef7eb2e8f9f7 4 ;* Version : V2.2.2
<> 144:ef7eb2e8f9f7 5 ;* Date : 26-June-2015
<> 144:ef7eb2e8f9f7 6 ;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain.
<> 144:ef7eb2e8f9f7 7 ;* This module performs:
<> 144:ef7eb2e8f9f7 8 ;* - Set the initial SP
<> 144:ef7eb2e8f9f7 9 ;* - Set the initial PC == Reset_Handler
<> 144:ef7eb2e8f9f7 10 ;* - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 11 ;* - Branches to __main in the C library (which eventually
<> 144:ef7eb2e8f9f7 12 ;* calls main()).
<> 144:ef7eb2e8f9f7 13 ;* After Reset the CortexM0 processor is in Thread mode,
<> 144:ef7eb2e8f9f7 14 ;* priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 15 ;* <<< Use Configuration Wizard in Context Menu >>>
<> 144:ef7eb2e8f9f7 16 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 17 ;
<> 144:ef7eb2e8f9f7 18 ;* Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 19 ;* are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 20 ;* 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 21 ;* this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 22 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 23 ;* this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 24 ;* and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 25 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 26 ;* may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 27 ;* without specific prior written permission.
<> 144:ef7eb2e8f9f7 28 ;*
<> 144:ef7eb2e8f9f7 29 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 30 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 31 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 32 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 33 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 34 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 35 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 36 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 37 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 38 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 39 ;
<> 144:ef7eb2e8f9f7 40 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 ; Amount of memory (in bytes) allocated for Stack
<> 144:ef7eb2e8f9f7 43 ; Tailor this value to your application needs
<> 144:ef7eb2e8f9f7 44 ; <h> Stack Configuration
<> 144:ef7eb2e8f9f7 45 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 46 ; </h>
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 Stack_Size EQU 0x00000400
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 51 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 Stack_Mem SPACE Stack_Size
<> 144:ef7eb2e8f9f7 54 __initial_sp EQU 0x20001000 ; Top of RAM
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 ; <h> Heap Configuration
<> 144:ef7eb2e8f9f7 58 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 59 ; </h>
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 Heap_Size EQU 0x00000400
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 64 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 65 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 __heap_base
<> 144:ef7eb2e8f9f7 68 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 69 __heap_limit EQU (__initial_sp - Stack_Size)
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 PRESERVE8
<> 144:ef7eb2e8f9f7 72 THUMB
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 76 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 77 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 78 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 79 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 82 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 83 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 84 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 85 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 86 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 87 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 88 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 89 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 90 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 91 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 92 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 93 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 94 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 95 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 96 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 ; External Interrupts
<> 144:ef7eb2e8f9f7 99 DCD WWDG_IRQHandler ; Window Watchdog
<> 144:ef7eb2e8f9f7 100 DCD PVD_IRQHandler ; PVD through EXTI Line detect
<> 144:ef7eb2e8f9f7 101 DCD RTC_IRQHandler ; RTC through EXTI Line
<> 144:ef7eb2e8f9f7 102 DCD FLASH_IRQHandler ; FLASH
<> 144:ef7eb2e8f9f7 103 DCD RCC_IRQHandler ; RCC
<> 144:ef7eb2e8f9f7 104 DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
<> 144:ef7eb2e8f9f7 105 DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
<> 144:ef7eb2e8f9f7 106 DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
<> 144:ef7eb2e8f9f7 107 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 108 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
<> 144:ef7eb2e8f9f7 109 DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
<> 144:ef7eb2e8f9f7 110 DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
<> 144:ef7eb2e8f9f7 111 DCD ADC1_IRQHandler ; ADC1
<> 144:ef7eb2e8f9f7 112 DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
<> 144:ef7eb2e8f9f7 113 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
<> 144:ef7eb2e8f9f7 114 DCD TIM2_IRQHandler ; TIM2
<> 144:ef7eb2e8f9f7 115 DCD TIM3_IRQHandler ; TIM3
<> 144:ef7eb2e8f9f7 116 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 117 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 118 DCD TIM14_IRQHandler ; TIM14
<> 144:ef7eb2e8f9f7 119 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 120 DCD TIM16_IRQHandler ; TIM16
<> 144:ef7eb2e8f9f7 121 DCD TIM17_IRQHandler ; TIM17
<> 144:ef7eb2e8f9f7 122 DCD I2C1_IRQHandler ; I2C1
<> 144:ef7eb2e8f9f7 123 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 124 DCD SPI1_IRQHandler ; SPI1
<> 144:ef7eb2e8f9f7 125 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 126 DCD USART1_IRQHandler ; USART1
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 __Vectors_End
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 ; Reset handler routine
<> 144:ef7eb2e8f9f7 136 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 137 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 138 IMPORT __main
<> 144:ef7eb2e8f9f7 139 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 140 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 141 BLX R0
<> 144:ef7eb2e8f9f7 142 LDR R0, =__main
<> 144:ef7eb2e8f9f7 143 BX R0
<> 144:ef7eb2e8f9f7 144 ENDP
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 149 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 150 B .
<> 144:ef7eb2e8f9f7 151 ENDP
<> 144:ef7eb2e8f9f7 152 HardFault_Handler\
<> 144:ef7eb2e8f9f7 153 PROC
<> 144:ef7eb2e8f9f7 154 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 155 B .
<> 144:ef7eb2e8f9f7 156 ENDP
<> 144:ef7eb2e8f9f7 157 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 158 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 159 B .
<> 144:ef7eb2e8f9f7 160 ENDP
<> 144:ef7eb2e8f9f7 161 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 162 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 163 B .
<> 144:ef7eb2e8f9f7 164 ENDP
<> 144:ef7eb2e8f9f7 165 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 166 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 167 B .
<> 144:ef7eb2e8f9f7 168 ENDP
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 Default_Handler PROC
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 EXPORT WWDG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 173 EXPORT PVD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 174 EXPORT RTC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 175 EXPORT FLASH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 176 EXPORT RCC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 177 EXPORT EXTI0_1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 178 EXPORT EXTI2_3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 179 EXPORT EXTI4_15_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 180 EXPORT DMA1_Channel1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 181 EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 182 EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 183 EXPORT ADC1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 184 EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 185 EXPORT TIM1_CC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 186 EXPORT TIM2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 187 EXPORT TIM3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 188 EXPORT TIM14_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 189 EXPORT TIM16_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 190 EXPORT TIM17_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 191 EXPORT I2C1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 192 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 193 EXPORT USART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 197 PVD_IRQHandler
<> 144:ef7eb2e8f9f7 198 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 199 FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 200 RCC_IRQHandler
<> 144:ef7eb2e8f9f7 201 EXTI0_1_IRQHandler
<> 144:ef7eb2e8f9f7 202 EXTI2_3_IRQHandler
<> 144:ef7eb2e8f9f7 203 EXTI4_15_IRQHandler
<> 144:ef7eb2e8f9f7 204 DMA1_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 205 DMA1_Channel2_3_IRQHandler
<> 144:ef7eb2e8f9f7 206 DMA1_Channel4_5_IRQHandler
<> 144:ef7eb2e8f9f7 207 ADC1_IRQHandler
<> 144:ef7eb2e8f9f7 208 TIM1_BRK_UP_TRG_COM_IRQHandler
<> 144:ef7eb2e8f9f7 209 TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 210 TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 211 TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 212 TIM14_IRQHandler
<> 144:ef7eb2e8f9f7 213 TIM16_IRQHandler
<> 144:ef7eb2e8f9f7 214 TIM17_IRQHandler
<> 144:ef7eb2e8f9f7 215 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 216 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 217 USART1_IRQHandler
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 B .
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 ENDP
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 ALIGN
<> 144:ef7eb2e8f9f7 224 END
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****