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targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c@80:bdf1132a57cf, 2016-03-02 (annotated)

Committer:
mbed_official
Date:
Wed Mar 02 14:30:11 2016 +0000
Revision:
80:bdf1132a57cf
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision de3b14ec9234d586b155fd24badc22775489a3dc



Full URL: https://github.com/mbedmicro/mbed/commit/de3b14ec9234d586b155fd24badc22775489a3dc/



latest changes to add arduino support, plus fixes for IOTSS BEID

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2015 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include <math.h>
bogdanm 0:9b334a45a8ff 17
bogdanm 0:9b334a45a8ff 18 #include "spi_api.h"
bogdanm 0:9b334a45a8ff 19 #include "spi_def.h"
bogdanm 0:9b334a45a8ff 20 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 21 #include "pinmap.h"
bogdanm 0:9b334a45a8ff 22 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 23 #include "wait_api.h"
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 static const PinMap PinMap_SPI_SCLK[] = {
bogdanm 0:9b334a45a8ff 26 {SCLK_SPI , SPI_0, 0},
bogdanm 0:9b334a45a8ff 27 {CLCD_SCLK , SPI_1, 0},
mbed_official 80:bdf1132a57cf 28 {ADC_SCLK , SPI_2, 0},
mbed_official 80:bdf1132a57cf 29 {SHIELD_0_SPI_SCK , SPI_3, 0},
mbed_official 80:bdf1132a57cf 30 {SHIELD_1_SPI_SCK , SPI_4, 0},
bogdanm 0:9b334a45a8ff 31 {NC , NC , 0}
bogdanm 0:9b334a45a8ff 32 };
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 static const PinMap PinMap_SPI_MOSI[] = {
bogdanm 0:9b334a45a8ff 35 {MOSI_SPI, SPI_0, 0},
bogdanm 0:9b334a45a8ff 36 {CLCD_MOSI, SPI_1, 0},
mbed_official 80:bdf1132a57cf 37 {ADC_MOSI, SPI_2, 0},
mbed_official 80:bdf1132a57cf 38 {SHIELD_0_SPI_MOSI, SPI_3, 0},
mbed_official 80:bdf1132a57cf 39 {SHIELD_1_SPI_MOSI, SPI_4, 0},
bogdanm 0:9b334a45a8ff 40 {NC , NC , 0}
bogdanm 0:9b334a45a8ff 41 };
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 static const PinMap PinMap_SPI_MISO[] = {
bogdanm 0:9b334a45a8ff 44 {MISO_SPI, SPI_0, 0},
bogdanm 0:9b334a45a8ff 45 {CLCD_MISO, SPI_1, 0},
mbed_official 80:bdf1132a57cf 46 {ADC_MISO, SPI_2, 0},
mbed_official 80:bdf1132a57cf 47 {SHIELD_0_SPI_MISO, SPI_3, 0},
mbed_official 80:bdf1132a57cf 48 {SHIELD_1_SPI_MISO, SPI_4, 0},
bogdanm 0:9b334a45a8ff 49 {NC , NC , 0}
bogdanm 0:9b334a45a8ff 50 };
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 static const PinMap PinMap_SPI_SSEL[] = {
bogdanm 0:9b334a45a8ff 53 {SSEL_SPI, SPI_0, 0},
bogdanm 0:9b334a45a8ff 54 {CLCD_SSEL, SPI_1, 0},
mbed_official 80:bdf1132a57cf 55 {ADC_SSEL, SPI_2, 0},
mbed_official 80:bdf1132a57cf 56 {SHIELD_0_SPI_nCS, SPI_3, 0},
mbed_official 80:bdf1132a57cf 57 {SHIELD_1_SPI_nCS, SPI_4, 0},
bogdanm 0:9b334a45a8ff 58 {NC , NC , 0}
bogdanm 0:9b334a45a8ff 59 };
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 static inline int ssp_disable(spi_t *obj);
bogdanm 0:9b334a45a8ff 62 static inline int ssp_enable(spi_t *obj);
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
mbed_official 80:bdf1132a57cf 65
mbed_official 80:bdf1132a57cf 66 int altfunction[4];
mbed_official 80:bdf1132a57cf 67 // determine the SPI to use
bogdanm 0:9b334a45a8ff 68 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
bogdanm 0:9b334a45a8ff 69 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
bogdanm 0:9b334a45a8ff 70 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
bogdanm 0:9b334a45a8ff 71 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
bogdanm 0:9b334a45a8ff 72 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
bogdanm 0:9b334a45a8ff 73 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
bogdanm 0:9b334a45a8ff 74 obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
bogdanm 0:9b334a45a8ff 75 if ((int)obj->spi == NC) {
bogdanm 0:9b334a45a8ff 76 error("SPI pinout mapping failed");
bogdanm 0:9b334a45a8ff 77 }
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 // enable power and clocking
bogdanm 0:9b334a45a8ff 80 switch ((int)obj->spi) {
mbed_official 80:bdf1132a57cf 81 case (int)SPI_0:
mbed_official 80:bdf1132a57cf 82 obj->spi->CR1 = 0;
mbed_official 80:bdf1132a57cf 83 obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
mbed_official 80:bdf1132a57cf 84 obj->spi->CPSR = SSP_CPSR_DFLT;
mbed_official 80:bdf1132a57cf 85 obj->spi->IMSC = 0x8;
mbed_official 80:bdf1132a57cf 86 obj->spi->DMACR = 0;
mbed_official 80:bdf1132a57cf 87 obj->spi->CR1 = SSP_CR1_SSE_Msk;
mbed_official 80:bdf1132a57cf 88 obj->spi->ICR = 0x3;
mbed_official 80:bdf1132a57cf 89 break;
bogdanm 0:9b334a45a8ff 90 case (int)SPI_1:
mbed_official 80:bdf1132a57cf 91 /* Configure SSP used for LCD */
mbed_official 80:bdf1132a57cf 92 obj->spi->CR1 = 0; /* Synchronous serial port disable */
mbed_official 80:bdf1132a57cf 93 obj->spi->DMACR = 0; /* Disable FIFO DMA */
mbed_official 80:bdf1132a57cf 94 obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */
mbed_official 80:bdf1132a57cf 95 obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */
mbed_official 80:bdf1132a57cf 96 (1ul << 1) ); /* Clear SSPRTINTR interrupt */
mbed_official 80:bdf1132a57cf 97 obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */
mbed_official 80:bdf1132a57cf 98 (0ul << 4) | /* Motorola frame format */
mbed_official 80:bdf1132a57cf 99 (0ul << 6) | /* CPOL = 0 */
mbed_official 80:bdf1132a57cf 100 (0ul << 7) | /* CPHA = 0 */
mbed_official 80:bdf1132a57cf 101 (1ul << 8) ); /* Set serial clock rate */
mbed_official 80:bdf1132a57cf 102 obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */
mbed_official 80:bdf1132a57cf 103 obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */
mbed_official 80:bdf1132a57cf 104 (0ul << 2) ); /* Device configured as master */
mbed_official 80:bdf1132a57cf 105 break;
mbed_official 80:bdf1132a57cf 106 case (int)SPI_2:
mbed_official 80:bdf1132a57cf 107 obj->spi->CR1 = 0;
mbed_official 80:bdf1132a57cf 108 obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
mbed_official 80:bdf1132a57cf 109 obj->spi->CPSR = SSP_CPSR_DFLT;
mbed_official 80:bdf1132a57cf 110 obj->spi->IMSC = 0x8;
mbed_official 80:bdf1132a57cf 111 obj->spi->DMACR = 0;
mbed_official 80:bdf1132a57cf 112 obj->spi->CR1 = SSP_CR1_SSE_Msk;
mbed_official 80:bdf1132a57cf 113 obj->spi->ICR = 0x3;
mbed_official 80:bdf1132a57cf 114 break;
mbed_official 80:bdf1132a57cf 115 case (int)SPI_3:
mbed_official 80:bdf1132a57cf 116 obj->spi->CR1 = 0;
mbed_official 80:bdf1132a57cf 117 obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
mbed_official 80:bdf1132a57cf 118 obj->spi->CPSR = SSP_CPSR_DFLT;
mbed_official 80:bdf1132a57cf 119 obj->spi->IMSC = 0x8;
mbed_official 80:bdf1132a57cf 120 obj->spi->DMACR = 0;
mbed_official 80:bdf1132a57cf 121 obj->spi->CR1 = SSP_CR1_SSE_Msk;
mbed_official 80:bdf1132a57cf 122 obj->spi->ICR = 0x3;
mbed_official 80:bdf1132a57cf 123 break;
mbed_official 80:bdf1132a57cf 124 case (int)SPI_4:
mbed_official 80:bdf1132a57cf 125 obj->spi->CR1 = 0;
mbed_official 80:bdf1132a57cf 126 obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
mbed_official 80:bdf1132a57cf 127 obj->spi->CPSR = SSP_CPSR_DFLT;
mbed_official 80:bdf1132a57cf 128 obj->spi->IMSC = 0x8;
mbed_official 80:bdf1132a57cf 129 obj->spi->DMACR = 0;
mbed_official 80:bdf1132a57cf 130 obj->spi->CR1 = SSP_CR1_SSE_Msk;
mbed_official 80:bdf1132a57cf 131 obj->spi->ICR = 0x3;
mbed_official 80:bdf1132a57cf 132 break;
bogdanm 0:9b334a45a8ff 133 }
bogdanm 0:9b334a45a8ff 134
mbed_official 80:bdf1132a57cf 135 if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;}
mbed_official 80:bdf1132a57cf 136 if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;}
mbed_official 80:bdf1132a57cf 137 if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;}
mbed_official 80:bdf1132a57cf 138 if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;}
mbed_official 80:bdf1132a57cf 139
mbed_official 80:bdf1132a57cf 140 // enable alt function
mbed_official 80:bdf1132a57cf 141 switch ((int)obj->spi) {
mbed_official 80:bdf1132a57cf 142 case (int)SPI_2:
mbed_official 80:bdf1132a57cf 143 CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[0]<<2 | altfunction[1]<<1 | altfunction[3]);
mbed_official 80:bdf1132a57cf 144 break;
mbed_official 80:bdf1132a57cf 145 case (int)SPI_3:
mbed_official 80:bdf1132a57cf 146 CMSDK_GPIO0->ALTFUNCSET |= (altfunction[1]<<14 | altfunction[0]<<13 | altfunction[3]<<12 | altfunction[2]<<11);
mbed_official 80:bdf1132a57cf 147 break;
mbed_official 80:bdf1132a57cf 148 case (int)SPI_4:
mbed_official 80:bdf1132a57cf 149 CMSDK_GPIO2->ALTFUNCSET |= (altfunction[2]<<12 | altfunction[1]<<8 | altfunction[0]<<7 | altfunction[3]<<6);
mbed_official 80:bdf1132a57cf 150 break;
mbed_official 80:bdf1132a57cf 151 }
mbed_official 80:bdf1132a57cf 152
bogdanm 0:9b334a45a8ff 153 // set default format and frequency
bogdanm 0:9b334a45a8ff 154 if (ssel == NC) {
bogdanm 0:9b334a45a8ff 155 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
bogdanm 0:9b334a45a8ff 156 } else {
bogdanm 0:9b334a45a8ff 157 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
bogdanm 0:9b334a45a8ff 158 }
bogdanm 0:9b334a45a8ff 159 spi_frequency(obj, 1000000);
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 // enable the ssp channel
bogdanm 0:9b334a45a8ff 162 ssp_enable(obj);
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 // pin out the spi pins
bogdanm 0:9b334a45a8ff 165 pinmap_pinout(mosi, PinMap_SPI_MOSI);
bogdanm 0:9b334a45a8ff 166 pinmap_pinout(miso, PinMap_SPI_MISO);
bogdanm 0:9b334a45a8ff 167 pinmap_pinout(sclk, PinMap_SPI_SCLK);
bogdanm 0:9b334a45a8ff 168 if (ssel != NC) {
bogdanm 0:9b334a45a8ff 169 pinmap_pinout(ssel, PinMap_SPI_SSEL);
bogdanm 0:9b334a45a8ff 170 }
bogdanm 0:9b334a45a8ff 171 }
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 void spi_free(spi_t *obj) {}
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 void spi_format(spi_t *obj, int bits, int mode, int slave) {
bogdanm 0:9b334a45a8ff 176 ssp_disable(obj);
bogdanm 0:9b334a45a8ff 177 if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
bogdanm 0:9b334a45a8ff 178 error("SPI format error");
bogdanm 0:9b334a45a8ff 179 }
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 int polarity = (mode & 0x2) ? 1 : 0;
bogdanm 0:9b334a45a8ff 182 int phase = (mode & 0x1) ? 1 : 0;
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 // set it up
bogdanm 0:9b334a45a8ff 185 int DSS = bits - 1; // DSS (data select size)
bogdanm 0:9b334a45a8ff 186 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
bogdanm 0:9b334a45a8ff 187 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 int FRF = 0; // FRF (frame format) = SPI
bogdanm 0:9b334a45a8ff 190 uint32_t tmp = obj->spi->CR0;
bogdanm 0:9b334a45a8ff 191 tmp &= ~(0xFFFF);
bogdanm 0:9b334a45a8ff 192 tmp |= DSS << 0
bogdanm 0:9b334a45a8ff 193 | FRF << 4
bogdanm 0:9b334a45a8ff 194 | SPO << 6
bogdanm 0:9b334a45a8ff 195 | SPH << 7;
bogdanm 0:9b334a45a8ff 196 obj->spi->CR0 = tmp;
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 tmp = obj->spi->CR1;
bogdanm 0:9b334a45a8ff 199 tmp &= ~(0xD);
bogdanm 0:9b334a45a8ff 200 tmp |= 0 << 0 // LBM - loop back mode - off
bogdanm 0:9b334a45a8ff 201 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
bogdanm 0:9b334a45a8ff 202 | 0 << 3; // SOD - slave output disable - na
bogdanm 0:9b334a45a8ff 203 obj->spi->CR1 = tmp;
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 ssp_enable(obj);
bogdanm 0:9b334a45a8ff 206 }
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 void spi_frequency(spi_t *obj, int hz) {
bogdanm 0:9b334a45a8ff 209 ssp_disable(obj);
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 uint32_t PCLK = SystemCoreClock;
bogdanm 0:9b334a45a8ff 212
mbed_official 80:bdf1132a57cf 213 int prescaler;
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
bogdanm 0:9b334a45a8ff 216 int prescale_hz = PCLK / prescaler;
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 // calculate the divider
bogdanm 0:9b334a45a8ff 219 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 // check we can support the divider
bogdanm 0:9b334a45a8ff 222 if (divider < 256) {
bogdanm 0:9b334a45a8ff 223 // prescaler
bogdanm 0:9b334a45a8ff 224 obj->spi->CPSR = prescaler;
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 // divider
bogdanm 0:9b334a45a8ff 227 obj->spi->CR0 &= ~(0xFFFF << 8);
bogdanm 0:9b334a45a8ff 228 obj->spi->CR0 |= (divider - 1) << 8;
bogdanm 0:9b334a45a8ff 229 ssp_enable(obj);
bogdanm 0:9b334a45a8ff 230 return;
bogdanm 0:9b334a45a8ff 231 }
bogdanm 0:9b334a45a8ff 232 }
bogdanm 0:9b334a45a8ff 233 error("Couldn't setup requested SPI frequency");
bogdanm 0:9b334a45a8ff 234 }
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 static inline int ssp_disable(spi_t *obj) {
bogdanm 0:9b334a45a8ff 237 return obj->spi->CR1 &= ~(1 << 1);
bogdanm 0:9b334a45a8ff 238 }
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 static inline int ssp_enable(spi_t *obj) {
bogdanm 0:9b334a45a8ff 241 return obj->spi->CR1 |= SSP_CR1_SSE_Msk;
bogdanm 0:9b334a45a8ff 242 }
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 static inline int ssp_readable(spi_t *obj) {
bogdanm 0:9b334a45a8ff 245 return obj->spi->SR & (1 << 2);
bogdanm 0:9b334a45a8ff 246 }
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 static inline int ssp_writeable(spi_t *obj) {
bogdanm 0:9b334a45a8ff 249 return obj->spi->SR & SSP_SR_BSY_Msk;
bogdanm 0:9b334a45a8ff 250 }
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 static inline void ssp_write(spi_t *obj, int value) {
bogdanm 0:9b334a45a8ff 253 obj->spi->DR = value;
bogdanm 0:9b334a45a8ff 254 while (ssp_writeable(obj));
bogdanm 0:9b334a45a8ff 255 }
bogdanm 0:9b334a45a8ff 256 static inline int ssp_read(spi_t *obj) {
mbed_official 80:bdf1132a57cf 257 int read_DR = obj->spi->DR;
bogdanm 0:9b334a45a8ff 258 return read_DR;
bogdanm 0:9b334a45a8ff 259 }
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 static inline int ssp_busy(spi_t *obj) {
bogdanm 0:9b334a45a8ff 262 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
bogdanm 0:9b334a45a8ff 263 }
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 int spi_master_write(spi_t *obj, int value) {
bogdanm 0:9b334a45a8ff 266 ssp_write(obj, value);
mbed_official 80:bdf1132a57cf 267 while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */
bogdanm 0:9b334a45a8ff 268 return (ssp_read(obj));
bogdanm 0:9b334a45a8ff 269 }
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 int spi_slave_receive(spi_t *obj) {
bogdanm 0:9b334a45a8ff 272 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
bogdanm 0:9b334a45a8ff 273 }
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 int spi_slave_read(spi_t *obj) {
bogdanm 0:9b334a45a8ff 276 return obj->spi->DR;
bogdanm 0:9b334a45a8ff 277 }
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 void spi_slave_write(spi_t *obj, int value) {
bogdanm 0:9b334a45a8ff 280 while (ssp_writeable(obj) == 0) ;
bogdanm 0:9b334a45a8ff 281 obj->spi->DR = value;
bogdanm 0:9b334a45a8ff 282 }
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 int spi_busy(spi_t *obj) {
bogdanm 0:9b334a45a8ff 285 return ssp_busy(obj);
bogdanm 0:9b334a45a8ff 286 }